Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5604BC Rev. 8, 11/2010
MPC5604B/C
MAPBGA–225
208 15 mm x 15 mm MAPBGA (17 x 17 x 1.7 mm)
QFN12 144 LQFP ##_mm_x_##mm
(20 x 20 x 1.4 mm)
MPC5604B/C Microcontroller Data Sheet
32-bit MCU family built on the Power Architecture® for automotive body electronics applications Features • Single issue, 32-bit CPU core complex (e200z0) — Compliant with the Power Architecture® embedded category — Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 512 KB on-chip code flash supported with the flash controller 64 (4 × 16) KB on-chip data flash memory with ECC Up to 48 KB on-chip SRAM Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) 10-bit analog-to-digital converter (ADC) 3 serial peripheral interface (DSPI) modules
1 2 3
100 LQFP (14 x 14 x 1.4 mm)
SOT-343R ##_mm_x_##mm
TBD
PKG-TBD ## mm x ## mm
64 LQFP (10 x 10 x 1.4 mm)
4
• • • • •
• •
5 6 7
• •
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 35 4.5 Recommended operating conditions . . . . . . . . . . . . . . 36 4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 40 4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . 51 4.9 Power management electrical characteristics . . . . . . . 53 4.10 Low voltage domain power consumption . . . . . . . . . . . 56 4.11 Flash memory electrical characteristics . . . . . . . . . . . . 58 4.12 Electromagnetic compatibility (EMC) characteristics . . 62 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.14 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.15 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 69 4.16 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.17 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.18 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 72 4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 89 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 100
• •
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009, 2010. All rights reserved.
Introduction
• • • • • • • • • •
Up to 4 serial communication interface (LINFlex) modules Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers 1 inter IC communication interface (I2C) module Up to 123 configurable general purpose pins supporting input and output operations (package dependent) Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution 1 System Module Timer (STM) Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels
1
1.1
Introduction
Document overview
This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.
1.2
Description
The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture® embedded category. The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 2 Freescale Semiconductor
3
Table 1. MPC5604B/C device comparison1
Device Feature MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG e200z0h Static – up to 64 MHz 256 KB 384 KB 64 KB (4 × 16 KB) 24 KB 32 KB 28 KB 8-entry 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 40 KB 32 KB 48 KB 512 KB
Introduction
CPU Execution speed2 Code Flash MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor Data Flash RAM MPU ADC CTU Total timer I/O3 12 ch, eMIOS 16-bit • PWM + MC + IC/OC4 • PWM + IC/OC4 • IC/OC4 SCI (LINFlex) SPI (DSPI) CAN (FlexCAN) I2C 32 kHz oscillator GPIO8 Debug 45 79 123 45 79 45 79 2 2
6
Yes 28 ch, 16-bit 5 ch 20 ch 3 ch 35 3 2 5 3 6 2 37 1 Yes 123 JTAG 45 79 45 79 123 45 79 123 Nexus2+ 3 2 5 56 ch, 16-bit 10 ch 40 ch 6 ch 12 ch, 16-bit 2 ch 10 ch 0 ch 28 ch, 16-bit 5 ch 20 ch 3 ch 12 ch, 16-bit 2 ch 10 ch 0 ch 28 ch, 16-bit 5 ch 20 ch 3 ch 56ch, 16-bit 10 ch 40 ch 6 ch 12 ch, 16-bit 2 ch 10 ch 0 ch 28 ch, 16-bit 5 ch 20 ch 3 ch 4 3 6 2 37 3 2 5 3 6 12 ch, 16-bit 2 ch 10 ch 0 ch 28 ch, 16-bit 5 ch 20 ch 3 ch 56 ch, 16-bit 10 ch 40 ch 6 ch 12 ch, 16-bit 2 ch 10 ch 0 ch 28 ch, 16-bit 5 ch 20 ch 3 ch 56 ch, 16-bit 10 ch 40 ch 6 ch
2 ch 10 ch 0 ch
Table 1. MPC5604B/C device comparison1 (continued)
Device Feature MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG 64 LQFP9 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 64 LQFP9 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 64 LQFP9 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 208 MAPBG A10 Introduction
4 Package
1 2
Feature set dependent on selected peripheral multiplexing—table shows example implementation Based on 125 °C ambient operating temperature 3 Refer to eMIOS section of device reference manual for information on the channel configuration and functions 4 IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter 5 SCI0, SCI1 and SCI2 are available. SCI3 is not available. 6 CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7 CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available. 8 I/O count based on multiplexing with peripherals 9 All 64 LQFPinformation is indicative and must be confirmed during silicon validation. 10 208 MAPBGA available only as development package for Nexus2+
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor
Block diagram
2
Block diagram
Figure 1. MPC5604B/C series block diagram
JTAG JTAG port Nexus port Nexus NMI SIUL Voltage regulator NMI Interrupt requests from peripheral blocks INTC Clocks FMPLL CMU Instructions e200z0h (Master) Data Nexus 2+ (Master) 64-bit 2 x 3 Crossbar Switch SRAM 48 KB Code Flash Data Flash 512 KB 64 KB
Figure 1 shows a top-level block diagram of the MPC5604B/C device series.
SRAM controller MPU
Flash controller
(Slave) (Slave) (Slave)
MPU registers
RTC
STM
SWT
ECSM
PIT
MC_RGM MC_CGM MC_ME
MC_PCU
BAM
SSCM
Peripheral bridge
Interrupt request
SIUL Reset control External interrupt request IMUX GPIO and pad control
36 Ch. ADC
CTU
2x eMIOS
4x LINFlex
3x DSPI
I2C
6x FlexCAN
WKPU
I/O Legend: ADC BAM FlexCAN CMU CTU DSPI eMIOS FMPLL I2C IMUX INTC JTAG LINFlex ECSM MC_CGM
...
...
...
...
...
Interrupt request with wakeup functionality
Analog-to-Digital Converter Boot Assist Module Controller Area Network Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) Error Correction Status Module Clock Generation Module
MC_ME MC_PCU MC_RGM MPU Nexus NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU
Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface (NDI) Level Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 5
Block diagram
Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 2. MPC5604B/C series block summary
Block Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter Boot assist module (BAM) Clock monitor unit (CMU) Cross triggering unit (CTU) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Monitors clock source (internal and external) integrity Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via “n” programmable channels. Enhanced modular input output system (eMIOS) Flash memory Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Internal multiplexer (IMUX) SIU subblock Generates high-speed system clocks and supports programmable frequency modulation Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) JTAG controller LINflex controller Clock generation module (MC_CGM) Mode entry module (MC_ME) Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides logic and control required for the generation of system and peripheral clocks Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Centralizes reset sources and manages the device reset sequence of the device
Power control unit (MC_PCU)
Reset generation module (MC_RGM)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 6 Freescale Semiconductor
Block diagram
Table 2. MPC5604B/C series block summary (continued)
Block Memory protection unit (MPU) Nexus development interface (NDI) Periodic interrupt timer (PIT) Real-time counter (RTC) Function Provides hardware access control for all memory references generated in a device Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Produces periodic interrupts and triggers A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Provides storage for program code, constants, and variables Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AUTOSAR and operating system tasks Provides protection from runaway code The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width
System integration unit (SIU)
Static random-access memory (SRAM) System status configuration module (SSCM) System timer module (STM) System watchdog timer (SWT) Wakeup unit (WKPU)
Crossbar (XBAR) switch
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 7
Package pinouts and signal descriptions
3
3.1
Package pinouts and signal descriptions
Package pinouts
Figure 2. LQFP 64-pin configuration (top view)1
The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3]
PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC
Figure 3. LQFP 64-pin configuration 5CAN 4LIN (top view)2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3]
PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA[11] PA[10] PA[9] PA[8] PA[7] PF[14] PF[15] PG[0] PG[1] PA[3] PB[15] PB[14] PB[11] PB[7] VDD_HV_ADC VSS_HV_ADC
1. All 64 LQFPinformation is indicative and must be confirmed during silicon validation. MPC5604B/C Microcontroller Data Sheet, Rev. 8 8 Freescale Semiconductor
PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Package pinouts and signal descriptions
Figure 4. LQFP 100-pin configuration (top view)
PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12]
100 LQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC
Note: Availability of port pin alternate functions depends on product selection.
2. All 64 LQFPinformation is indicative and must be confirmed during silicon validation. MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 9
PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Package pinouts and signal descriptions
Figure 5. LQFP 144-pin configuration (top view)
PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12]
144 LQFP
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC
Note: Availability of port pin alternate functions depends on product selection.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 10 Freescale Semiconductor
PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4]
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Package pinouts and signal descriptions
1 A B C D E F G H J K L M N P R T
PC[8]
2
PC[13]
3
NC
4
NC
5
PH[8]
6
PH[4]
7
PC[5]
8
PC[0]
9
NC
10
NC
11
PC[2]
12
NC
13
PE[15]
14
NC
15
NC
16
NC
A B C D E F G H J K L M N P R T
PC[9]
PB[2]
NC
PC[12]
PE[6]
PH[5]
PC[4]
PH[9]
PH[10]
NC
PC[3]
PG[11]
PG[15]
PG[14]
PA[11]
PA[10]
PC[14]
VDD_HV
PB[3]
PE[7]
PH[7]
PE[5]
PE[3]
VSS_LV
PC[1]
NC
PA[5]
NC
PE[14]
PE[12]
PA[9]
PA[8]
NC
NC
PC[15]
NC
PH[6]
PE[4]
PE[2]
VDD_LV
VDD_HV
NC
PA[6]
NC
PG[10]
PF[14]
PE[13]
PA[7]
PG[4]
PG[5]
PG[3]
PG[2]
PG[1]
PG[0]
PF[15]
VDD_HV
PE[0]
PA[2]
PA[1]
PE[1]
PH[0]
PH[1]
PH[3]
PH[2]
PE[9]
PE[8]
PE[10]
PA[0]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV
NC
NC
MSEO
VSS_HV
PE[11]
VDD_HV
NC
VSS_HV VSS_HV VSS_HV VSS_HV
MDO3
MDO2
MDO0
MDO1
RESET
VSS_LV
NC
NC
VSS_HV VSS_HV VSS_HV VSS_HV
NC
NC
NC
NC
EVTI
NC
VDD_BV
VDD_LV
VSS_HV VSS_HV VSS_HV VSS_HV
NC
PG[12]
PA[3]
PG[13]
PG[9]
PG[8]
NC
EVTO
PB[15]
PD[15]
PD[14]
PB[14]
PG[7]
PG[6]
PC[10]
PC[11]
PB[13]
PD[13]
PD[12]
PB[12]
PB[1]
PF[9]
PB[0]
NC
NC
PA[4]
VSS_LV
EXTAL
VDD_HV
PF[0]
PF[4]
NC
PB[11]
PD[10] VDD_HV _ADC PD[7]
PD[9]
PD[11]
PF[8]
NC
PC[7]
NC
NC
PA[14]
VDD_LV
XTAL
PB[10] OSC32K _XTAL OSC32K _EXTAL
PF[1]
PF[5]
PD[0]
PD[3]
PB[6] VSS_HV _ADC PD[8]
PB[7]
PF[12]
PC[6]
PF[10]
PF[11]
VDD_HV
PA[15]
PA[13]
NC
PF[3]
PF[7]
PD[2]
PD[4]
PB[5]
NC
NC
NC
MCKO
NC
PF[13]
PA[12]
NC
PF[2]
PF[6]
PD[1]
PD[5]
PD[6]
PB[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
15
16
Note: 208 MAPBGA available only as development package for Nexus 2+.
= Not connected
Figure 6. 208 MAPBGA configuration
3.2
Pin muxing
Table 3 defines the pin list and muxing for this device. Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 11
12
Table 3. Functional port pin descriptions
Package pinouts and signal descriptions Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 5 5
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 G4
PA[0]
PCR[0]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3
GPIO[0] E0UC[0] CLKOUT — WKUP[19]4 GPIO[1] E0UC[1] — — NMI5 WKUP[2]4 GPIO[2] E0UC[2] — — WKUP[3]4 GPIO[3] E0UC[3] — — EIRQ[0] GPIO[4] E0UC[4] — — WKUP[9]4 GPIO[5] E0UC[5] — —
SIUL eMIOS0 CGL — WKPU SIUL eMIOS0 — — WKPU WKPU SIUL eMIOS0 — — WKPU SIUL eMIOS0 — — SIUL SIUL eMIOS0 — — WKPU SIUL eMIOS0 — —
I/O I/O O — I I/O I/O — — I I I/O I/O — — I I/O I/O — — I I/O I/O — — I I/O I/O — —
M
Tristate
12
16
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor
PA[1]
PCR[1]
S
Tristate
4
4
7
11
F3
PA[2]
PCR[2]
S
Tristate
3
3
5
9
F2
PA[3]
PCR[3]
S
Tristate
43
39
68
90
K15
PA[4]
PCR[4]
S
Tristate
20
20
29
43
N6
PA[5]
PCR[5]
M
Tristate
51
51
79
118
C11
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 52 52 Package pinouts and signal descriptions
13 PA[6] PCR[6] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — N/A6 — AF0 AF1 AF2 AF3 N/A6 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PA[7] PCR[7] PA[8] PCR[8] PA[9] PCR[9] PA[10] PCR[10] PA[11] PCR[11]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 D11
GPIO[6] E0UC[6] — — EIRQ[1] GPIO[7] E0UC[7] LIN3TX — EIRQ[2] GPIO[8] E0UC[8] — — EIRQ[3] ABS[0] LIN3RX GPIO[9] E0UC[9] — — FAB GPIO[10] E0UC[10] SDA — GPIO[11] E0UC[11] SCL —
SIUL eMIOS0 — — SIUL SIUL eMIOS0 LINFlex_3 — SIUL SIUL eMIOS0 — — SIUL BAM LINFlex_3 SIUL eMIOS_0 — — BAM SIUL eMIOS_0 I2C_0 — SIUL eMIOS0 I2C_0 —
I/O I/O — — I I/O I/O O — I I/O I/O — — I I I I/O I/O — — I I/O I/O I/O — I/O I/O I/O —
S
Tristate
80
119
S
Tristate
44
44
71
104
D16
S
Input, weak pull-up
45
45
72
105
C16
S
Pulldown
46
46
73
106
C15
S
Tristate
47
47
74
107
B16
S
Tristate
48
48
75
108
B15
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 22 22 Package pinouts and signal descriptions
14 PA[12] PCR[12] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PA[13] PCR[13] PA[14] PCR[14] PA[15] PCR[15] PB[0] PCR[16] PB[1] PCR[17]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 T7
GPIO[12] — — — SIN_0 GPIO[13] SOUT_0 — — GPIO[14] SCK_0 CS0_0 — EIRQ[4] GPIO[15] CS0_0 SCK_0 — WKUP[10]4 GPIO[16] CAN0TX — — GPIO[17] — — — WKUP[4]4 CAN0RX
SIUL — — — DSPI0 SIUL DSPI_0 — — SIUL DSPI_0 DSPI_0 — SIUL SIUL DSPI_0 DSPI_0 — WKPU SIUL FlexCAN_0 — — SIUL — — — WKPU FlexCAN_0
I/O — — — I I/O O — — I/O I/O I/O — I I/O I/O I/O — I I/O O — — I/O — — — I I
S
Tristate
31
45
M
Tristate
21
21
30
44
R7
M
Tristate
19
19
28
42
P6
M
Tristate
18
18
27
40
R6
M
Tristate
14
14
23
31
N3
S
Tristate
15
15
24
32
N1
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 64 64 Package pinouts and signal descriptions
15 PB[2] PCR[18] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PB[3] PCR[19] PB[4] PCR[20] PB[5] PCR[21] PB[6] PCR[22] PB[7] PCR[23]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 B2
GPIO[18] LIN0TX SDA — GPIO[19] — SCL — WKUP[11]4 LIN0RX GPIO[20] — — — ANP[0] GPIO[21] — — — ANP[1] GPIO[22] — — — ANP[2] GPIO[23] — — — ANP[3]
SIUL LINFlex_0 I2C_0 — SIUL — I2C_0 — WKPU LINFlex_0 SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC
I/O O I/O — I/O — I/O — I I I — — — I I — — — I I — — — I I — — — I
M
Tristate
100
144
S
Tristate
1
1
1
1
C3
I
Tristate
32
32
50
72
T16
I
Tristate
35
—
53
75
R16
I
Tristate
36
—
54
76
P15
I
Tristate
37
35
55
77
P16
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 30 30 Package pinouts and signal descriptions
16 PB[8] PCR[24] AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PB[9] PCR[25] PB[10] PCR[26] PB[11]8 PCR[27] PB[12] PCR[28] PB[13] PCR[29]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 R9
GPIO[24] — — — ANS[0] OSC32K_XTAL7 GPIO[25] — — — ANS[1] OSC32K_EXTAL7 GPIO[26] — — — ANS[2] WKUP[8]4 GPIO[27] E0UC[3] — CS0_0 ANS[3] GPIO[28] E0UC[4] — CS1_0 ANX[0] GPIO[29] E0UC[5] — CS2_0 ANX[1]
SIUL — — — ADC SXOSC SIUL — — — ADC SXOSC SIUL — — — ADC WKPU SIUL eMIOS_0 — DSPI_0 ADC SIUL eMIOS — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC
I — — — I I/O I — — — I I/O I/O — — — I I I/O I/O — I/O I I/O I/O — O I I/O I/O — O I
I
Tristate
39
53
I
Tristate
29
29
38
52
T9
J
Tristate
31
31
40
54
P9
J
Tristate
38
36
59
81
N13
J
Tristate
39
—
61
83
M16
J
Tristate
40
—
63
85
M13
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 41 37 Package pinouts and signal descriptions
17 PB[14] PCR[30] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PB[15] PCR[31] PC[0]9 PCR[32] PC[1]9 PCR[33] PC[2] PCR[34] PC[3] PCR[35]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 L16
GPIO[30] E0UC[6] — CS3_0 ANX[2] GPIO[31] E0UC[7] — CS4_0 ANX[3] GPIO[32] — TDI — GPIO[33] — TDO10 — GPIO[34] SCK_1 CAN4TX11 — EIRQ[5] GPIO[35] CS0_1 MA[0] — CAN1RX CAN4RX11 EIRQ[6]
SIUL eMIOS0 — DSPI_0 ADC SIUL eMIOS_0 — DSPI_0 ADC SIUL — JTAGC — SIUL — JTAGC — SIUL DSPI_1 LINFlex_4 — SIUL SIUL DSPI_1 ADC — FlexCAN_1 FlexCAN_4 SIUL
I/O I/O — O I I/O I/O — O I I/O — I — I/O — O — I/O I/O O — I I/O I/O O — I I I
J
Tristate
65
87
J
Tristate
42
38
67
89
L13
M
Input, weak pull-up Tristate
59
59
87
126
A8
M
54
54
82
121
C9
M
Tristate
50
50
78
117
A11
S
Tristate
49
49
77
116
B11
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 62 62 Package pinouts and signal descriptions
18 PC[4] PCR[36] AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PC[5] PCR[37] PC[6] PCR[38] PC[7] PCR[39] PC[8] PCR[40] PC[9] PCR[41]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 B7
GPIO[36] — — — SIN_1 CAN3RX11 GPIO[37] SOUT_1 CAN3TX11 — EIRQ[7] GPIO[38] LIN1TX — — GPIO[39] — — — LIN1RX WKUP[12]4 GPIO[40] LIN2TX — — GPIO[41] — — — LIN2RX WKUP[13]4
SIUL — — — DSPI_1 FlexCAN_3 SIUL DSPI1 FlexCAN_3 — SIUL SIUL LINFlex_1 — — SIUL — — — LINFlex_1 WKPU SIUL LINFlex_2 — — SIUL — — — LINFlex_2 WKPU
I/O — — — I I I/O O O — I I/O O — — I/O — — — I I I/O O — — I/O — — — I I
M
Tristate
92
131
M
Tristate
61
61
91
130
A7
S
Tristate
16
16
25
36
R2
S
Tristate
17
17
26
37
P3
S
Tristate
63
63
99
143
A1
S
Tristate
2
2
2
2
B1
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN 13 13 Package pinouts and signal descriptions
19 PC[10] PCR[42] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PC[11] PCR[43] PC[12] PCR[44] PC[13] PCR[45] PC[14] PCR[46] PC[15] PCR[47]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 M3
GPIO[42] CAN1TX CAN4TX11 MA[1] GPIO[43] — — — CAN1RX CAN4RX11 WKUP[5]4 GPIO[44] E0UC[12] — — SIN_2 GPIO[45] E0UC[13] SOUT_2 — GPIO[46] E0UC[14] SCK_2 — EIRQ[8] GPIO[47] E0UC[15] CS0_2 —
SIUL FlexCAN_1 FlexCAN_4 ADC SIUL — — — FlexCAN_1 FlexCAN_4 WKPU SIUL eMIOS_0 — — DSPI_2 SIUL eMIOS_0 DSPI_2 — SIUL eMIOS_0 DSPI_2 — SIUL SIUL eMIOS_0 DSPI_2 —
I/O O O O I/O — — — I I I I/O I/O — — I I/O I/O O — I/O I/O I/O — I I/O I/O I/O —
M
Tristate
22
28
S
Tristate
—
—
21
27
M4
M
Tristate
—
—
97
141
B4
S
Tristate
—
—
98
142
A2
S
Tristate
—
—
3
3
C1
M
Tristate
—
—
4
4
D3
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
20 PD[0] PCR[48] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PD[1] PCR[49] PD[2] PCR[50] PD[3] PCR[51] PD[4] PCR[52] PD[5] PCR[53]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 P12
GPIO[48] — — — ANP[4] GPIO[49] — — — ANP[5] GPIO[50] — — — ANP[6] GPIO[51] — — — ANP[7] GPIO[52] — — — ANP[8] GPIO[53] — — — ANP[9]
SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC
I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I
I
Tristate
41
63
I
Tristate
—
—
42
64
T12
I
Tristate
—
—
43
65
R12
I
Tristate
—
—
44
66
P13
I
Tristate
—
—
45
67
R13
I
Tristate
—
—
46
68
T13
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
21 PD[6] PCR[54] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PD[7] PCR[55] PD[8] PCR[56] PD[9] PCR[57] PD[10] PCR[58] PD[11] PCR[59]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 T14
GPIO[54] — — — ANP[10] GPIO[55] — — — ANP[11] GPIO[56] — — — ANP[12] GPIO[57] — — — ANP[13] GPIO[58] — — — ANP[14] GPIO[59] — — — ANP[15]
SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC SIUL — — — ADC
I — — — I I — — — I I — — — I I — — — I I — — — I I — — — I
I
Tristate
47
69
I
Tristate
—
—
48
70
R14
I
Tristate
—
—
49
71
T15
I
Tristate
—
—
56
78
N15
I
Tristate
—
—
57
79
N14
I
Tristate
—
—
58
80
N16
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
22 PD[12]8 PCR[60] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PD[13] PCR[61] PD[14] PCR[62] PD[15] PCR[63] PE[0] PCR[64] PE[1] PCR[65]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 M15
GPIO[60] CS5_0 E0UC[24] — ANS[4] GPIO[61] CS0_1 E0UC[25] — ANS[5] GPIO[62] CS1_1 E0UC[26] — ANS[6] GPIO[63] CS2_1 E0UC[27] — ANS[7] GPIO[64] E0UC[16] — — CAN5RX11 WKUP[6]4 GPIO[65] E0UC[17] CAN5TX11 —
SIUL DSPI_0 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC SIUL DSPI_1 eMIOS_0 — ADC SIUL eMIOS_0 — — FlexCAN_5 WKPU SIUL eMIOS_0 FlexCAN_5 —
I/O O I/O — I I/O I/O I/O — I I/O O I/O — I I/O O I/O — I I/O I/O — — I I I/O I/O O —
J
Tristate
60
82
J
Tristate
—
—
62
84
M14
J
Tristate
—
—
64
86
L15
J
Tristate
—
—
66
88
L14
S
Tristate
—
—
6
10
F1
M
Tristate
—
—
8
12
F4
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
23 PE[2] PCR[66] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PE[3] PCR[67] PE[4] PCR[68] PE[5] PCR[69] PE[6] PCR[70] PE[7] PCR[71] PE[8] PCR[72]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 D7
GPIO[66] E0UC[18] — — SIN_1 GPIO[67] E0UC[19] SOUT_1 — GPIO[68] E0UC[20] SCK_1 — EIRQ[9] GPIO[69] E0UC[21] CS0_1 MA[2] GPIO[70] E0UC[22] CS3_0 MA[1] GPIO[71] E0UC[23] CS2_0 MA[0] GPIO[72] CAN2TX12 E0UC[22] CAN3TX11
SIUL eMIOS0 — — DSPI_1 SIUL eMIOS0 DSPI_1 — SIUL eMIOS0 DSPI_1 — SIUL SIUL eMIOS_0 DSPI_1 ADC SIUL eMIOS_0 DSPI_0 ADC SIUL eMIOS_0 DSPI_0 ADC
I/O I/O — — I I/O I/O O — I/O I/O I/O — I I/O I/O I/O O I/O I/O O O I/O I/O O O
M
Tristate
89
128
M
Tristate
—
—
90
129
C7
M
Tristate
—
—
93
132
D6
M
Tristate
—
—
94
133
C6
M
Tristate
—
—
95
139
B5
M
Tristate
—
—
96
140
C4
SIUL I/O FlexCAN_2 O eMIOS0 I/O FlexCAN_3 O
M
Tristate
—
—
9
13
G2
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
24 PE[9] PCR[73] AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PE[10] PCR[74] PE[11] PCR[75] PE[12] PCR[76] PE[13] PCR[77] PE[14] PCR[78]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 G1
GPIO[73] — E0UC[23] — WKUP[7]4 CAN2RX12 CAN3RX11 GPIO[74] LIN3TX CS3_1 — EIRQ[10] GPIO[75] — CS4_1 — LIN3RX WKUP[14]4 GPIO[76] — E1UC[19]13 — SIN_2 EIRQ[11] GPIO[77] SOUT2 E1UC[20] — GPIO[78] SCK_2 E1UC[21] — EIRQ[12]
SIUL — eMIOS_0 — WKPU FlexCAN_2 FlexCAN_3 SIUL LINFlex_3 DSPI_1 — SIUL SIUL — DSPI_1 — LINFlex_3 WKPU SIUL — eMIOS_1 — DSPI_2 SIUL SIUL DSPI_2 eMIOS_1 — SIUL DSPI_2 eMIOS_1 — SIUL
I/O — I/O — I I I I/O O O — I I/O — O — I I I/O — I/O — I I I/O O I/O — I/O I/O I/O — I
S
Tristate
10
14
S
Tristate
—
—
11
15
G3
S
Tristate
—
—
13
17
H2
S
Tristate
—
—
76
109
C14
S
Tristate
—
—
—
103
D15
S
Tristate
—
—
—
112
C13
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
25 PE[15] PCR[79] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PF[0] PCR[80] PF[1] PCR[81] PF[2] PCR[82] PF[3] PCR[83] PF[4] PCR[84]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 A13
GPIO[79] CS0_2 E1UC[22] — GPIO[80] E0UC[10] CS3_1 — ANS[8] GPIO[81] E0UC[11] CS4_1 — ANS[9] GPIO[82] E0UC[12] CS0_2 — ANS[10] GPIO[83] E0UC[13] CS1_2 — ANS[11] GPIO[84] E0UC[14] CS2_2 — ANS[12]
SIUL DSPI_2 eMIOS_1 — SIUL eMIOS_0 DSPI_1 — ADC SIUL eMIOS_0 DSPI_1 — I SIUL eMIOS_0 DSPI_2 — ADC SIUL eMIOS_0 DSPI_2 — ADC SIUL eMIOS_0 DSPI_2 — ADC
I/O I/O I/O — I/O I/O O — I I/O I/O O — I I/O I/O I/O — I I/O I/O O — I I/O I/O O — I
M
Tristate
—
113
J
Tristate
—
—
—
55
N10
J
Tristate
—
—
—
56
P10
J
Tristate
—
—
—
57
T10
J
Tristate
—
—
—
58
R10
J
Tristate
—
—
—
59
N11
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
26 PF[5] PCR[85] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PF[6] PCR[86] PF[7] PCR[87] PF[8] PCR[88] PF[9] PCR[89] PF[10] PCR[90]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 P11
GPIO[85] E0UC[22] CS3_2 — ANS[13] GPIO[86] E0UC[23] — — ANS[14] GPIO[87] — — — ANS[15] GPIO[88] CAN3TX14 CS4_0 CAN2TX15 GPIO[89] — CS5_0 — CAN2RX15 CAN3RX14 GPIO[90] — — —
SIUL eMIOS_0 DSPI_2 — ADC SIUL eMIOS_0 — — ADC SIUL — — — ADC SIUL FlexCAN_3 DSPI_0 FlexCAN_2 SIUL — DSPI_0 — FlexCAN_2 FlexCAN_3 SIUL — — —
I/O I/O O — I I/O I/O — — I I/O — — — I I/O O O O I/O — O — I I I/O — — —
J
Tristate
—
60
J
Tristate
—
—
—
61
T11
J
Tristate
—
—
—
62
R11
M
Tristate
—
—
—
34
P1
S
Tristate
—
—
—
33
N2
M
Tristate
—
—
—
38
R3
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
27 PF[11] PCR[91] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PF[12] PCR[92] PF[13] PCR[93] PF[14] PCR[94] PF[15] PCR[95] PG[0] PCR[96]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 R4
GPIO[91] — — — WKUP[15]4 GPIO[92] E1UC[25] — — GPIO[93] E1UC[26] — — WKUP[16]4 GPIO[94] CAN4TX11 E1UC[27] CAN1TX GPIO[95] — — — CAN1RX CAN4RX11 EIRQ[13] GPIO[96] CAN5TX11 E1UC[23] —
SIUL — — — WKPU SIUL eMIOS_1 — — SIUL eMIOS_1 — — WKPU SIUL FlexCAN_4 eMIOS_1 FlexCAN_4 SIUL — — — FlexCAN_1 FlexCAN_4 SIUL SIUL FlexCAN_5 eMIOS_1 —
I/O — — — I I/O I/O — — I/O I/O — — I I/O O I/O O I/O — — — I I I I/O O I/O —
S
Tristate
—
39
M
Tristate
—
—
—
35
R1
S
Tristate
—
—
—
41
T6
M
Tristate
—
43
—
102
D14
S
Tristate
—
42
—
101
E15
M
Tristate
—
41
—
98
E14
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — 40 Package pinouts and signal descriptions
28 PG[1] PCR[97] AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PG[2] PCR[98] PG[3] PCR[99] PG[4] PCR[100] PG[5] PCR[101] PG[6] PCR[102] PG[7] PCR[103]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 E13
GPIO[97] — E1UC[24] — CAN5RX11 EIRQ[14] GPIO[98] E1UC[11] — — GPIO[99] E1UC[12] — — WKUP[17]4 GPIO[100] E1UC[13] — — GPIO[101] E1UC[14] — — WKUP[18]4 GPIO[102] E1UC[15] — — GPIO[103] E1UC[16] — —
SIUL — eMIOS_1 — FlexCAN_5 SIUL SIUL eMIOS_1 — — SIUL eMIOS_1 — — WKPU SIUL eMIOS_1 — — SIUL eMIOS_1 — — WKPU SIUL eMIOS_1 — — SIUL eMIOS_1 — —
I/O — I/O — I I I/O I/O — — I/O I/O — — I I/O I/O — — I/O I/O — — I I/O I/O — — I/O I/O — —
S
Tristate
—
97
M
Tristate
—
—
—
8
E4
S
Tristate
—
—
—
7
E3
M
Tristate
—
—
—
6
E1
S
Tristate
—
—
—
5
E2
M
Tristate
—
—
—
30
M2
M
Tristate
—
—
—
29
M1
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
29 PG[8] PCR[104] AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PG[9] PCR[105] PG[10] PCR[106] PG[11] PCR[107] PG[12] PCR[108] PG[13] PCR[109] PG[14] PCR[110]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 L2
GPIO[104] E1UC[17] — CS0_2 EIRQ[15] GPIO[105] E1UC[18] — SCK_2 GPIO[106] E0UC[24] — — GPIO[107] E0UC[25] — — GPIO[108] E0UC[26] — — GPIO[109] E0UC[27] — — GPIO[110] E1UC[0] — —
SIUL eMIOS_1 — DSPI_2 SIUL SIUL eMIOS1 — DSPI_2 SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL eMIOS_0 — — SIUL eMIOS_1 — —
I/O I/O — I/O I I/O I/O — I/O I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — —
S
Tristate
—
26
S
Tristate
—
—
—
25
L1
S
Tristate
—
—
—
114
D13
M
Tristate
—
—
—
115
B12
M
Tristate
—
—
—
92
K14
M
Tristate
—
—
—
91
K16
S
Tristate
—
—
—
110
B14
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
30 PG[15] PCR[111] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PH[0] PCR[112] PH[1] PCR[113] PH[2] PCR[114] PH[3] PCR[115] PH[4] PCR[116] PH[5] PCR[117]
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 B13
GPIO[111] E1UC[1] — — GPIO[112] E1UC[2] — — SIN1 GPIO[113] E1UC[3] SOUT1 — GPIO[114] E1UC[4] SCK_1 — GPIO[115] E1UC[5] CS0_1 — GPIO[116] E1UC[6] — — GPIO[117] E1UC[7] — —
SIUL eMIOS_1 — — SIUL eMIOS_1 — — DSPI_1 SIUL eMIOS_1 DSPI_1 — SIUL eMIOS_1 DSPI_1 — SIUL eMIOS_1 DSPI_1 — SIUL eMIOS_1 — — SIUL eMIOS_1 — —
I/O I/O — — I/O I/O — — I I/O I/O O — I/O I/O I/O — I/O I/O I/O — I/O I/O — — I/O I/O — —
M
Tristate
—
111
M
Tristate
—
—
—
93
F13
M
Tristate
—
—
—
94
F14
M
Tristate
—
—
—
95
F16
M
Tristate
—
—
—
96
F15
M
Tristate
—
—
—
134
A6
S
Tristate
—
—
—
135
B6
Table 3. Functional port pin descriptions (continued)
Pin No. Port pin PCR register Alternate function1 I/O Pad RESET direction2 type config. 64 LQFP 64 5CAN 4 LQFP LIN — — Package pinouts and signal descriptions
31 PH[6] PCR[118] AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor PH[7] PCR[119] PH[8] PCR[120] PH[9]9 PCR[121] PH[10]9 PCR[122]
1 2 3 4 5 6 7
Function
Peripheral
100 LQFP
144 LQFP
208 MAP BGA3 D5
GPIO[118] E1UC[8] — MA[2] GPIO[119] E1UC[9] CS3_2 MA[1] GPIO[120] E1UC[10] CS2_2 MA[0] GPIO[121] — TCK — GPIO[122] — TMS —
SIUL eMIOS_1 — ADC SIUL eMIOS_1 DSPI_2 ADC SIUL eMIOS_1 DSPI_2 ADC SIUL — JTAGC — SIUL — JTAGC —
I/O I/O — O I/O I/O O O I/O I/O O O I/O — I — I/O — I —
M
Tristate
—
136
M
Tristate
—
—
—
137
C5
M
Tristate
—
—
—
138
A5
S
Input, weak pull-up Input, weak pull-up
—
—
88
127
B8
S
—
—
81
120
B9
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 208 MAPBGA available only as development package for Nexus2+ All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. Value of PCR.IBE bit must be 0
8
This pad is used on MPC5607B 100-pin and 144-pinto provide supply for the second ADC. Therefore it is recommended not using it to keep the compatibility with the family devices. 9 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed, in this case MPC5604B/C get incompliance with IEEE 1149.1-2001. 10 The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47–100 kOhms should be added between the TDO pin and VDD. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. 11 Available only on MPC560xC versions and MPC5604B 208 MAPBGA devices 12 Not available on MPC5602B devices 13 Not available in 100 LQFP package 14 Available only on MPC5604B 208 MAPBGA devices 15 Not available on MPC5603B 144-pin devices
32 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor
Electrical characteristics
4
4.1
Electrical characteristics
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.
CAUTION
All 64 LQFPinformation is indicative and must be confirmed during silicon validation.
Electrical characteristics
4.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where appropriate. Table 4. Parameter classifications
Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where appropriate.
4.3
NVUSRO register
Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 33
Electrical characteristics
4.3.1
NVUSRO[PAD3V5V] field description
Table 5. PAD3V5V field description1
Value2 0 1
1 2
Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration.
Description High voltage supply is 5.0 V High voltage supply is 3.3 V
See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V bit value.
4.3.2
NVUSRO[OSCILLATOR_MARGIN] field description
Table 6. OSCILLATOR_MARGIN field description1
Value2 0 1
1 2
Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.
Description Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz)
See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.
The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. For a detailed description of the NVUSRO register, please refer to the MPC5604B/C Reference Manual.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 34 Freescale Semiconductor
Electrical characteristics
4.4
Absolute maximum ratings
Table 7. Absolute maximum ratings
Value Symbol VSS VDD VSS_LV Parameter Conditions Min SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — — — 0 0.3 Max 0 6.0 V V V Unit
VSS0.1 VSS+0.1
VDD_BV
— Relative to VDD —
0.3 0.3
6.0 VDD+0.3
V
VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) VIN SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition
VSS0.1 VSS+0.1
V
— Relative to VDD — Relative to VDD — —
0.3
6.0
V
VDD 0.3 VDD+0.3 0.3 — 10 50 — — — 55 6.0 VDD+0.3 10 50 70 64 150 150 mA °C mA mA V
IINJPAD IINJSUM
IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V ± 10%, PAD3V5V = 0 supply segment VDD = 3.3 V ± 10%, PAD3V5V = 1 ICORELV SR Low voltage static current sink through VDD_BV TSTORAGE SR Storage temperature — —
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 35
Electrical characteristics
4.5
Recommended operating conditions
Table 8. Recommended operating conditions (3.3 V)
Value Symbol VSS VDD
1
Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6
Conditions Min — — — — Relative to VDD — — Relative to VDD — Relative to VDD — — — fCPU < 64 MHz — fCPU < 64 MHz — fCPU < 64 MHz — 0 3.0 Max 0 3.6
Unit V V V V
VSS_LV2 VDD_BV3
VSS0.1 VSS+0.1 3.0 3.6
VDD0.1 VDD+0.1 VSS0.1 VSS+0.1 3.05 3.6 V V
VSS_ADC VDD_ADC4
VDD0.1 VDD+0.1 VSS0.1 — 5 50 — 40 40 40 40 40 40 — VDD+0.1 5 50 0.25 85 110 105 130 125 150 V/µs °C mA V
VIN
IINJPAD IINJSUM TVDD
TA C-Grade Part SR Ambient temperature under bias TJ C-Grade Part SR Junction temperature under bias TA V-Grade Part SR Ambient temperature under bias TJ V-Grade Part SR Junction temperature under bias TA M-Grade Part SR Ambient temperature under bias TJ M-Grade Part SR Junction temperature under bias
1 2 3 4 5
6
100 nF capacitance needs to be provided between each VDD/VSS pair 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation
MPC5604B/C Microcontroller Data Sheet, Rev. 8 36 Freescale Semiconductor
Electrical characteristics
Table 9. Recommended operating conditions (5.0 V)
Value Symbol VSS VDD
1
Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV pins with respect to ground (VSS) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS)
Conditions Min — — Voltage drop2 — 0 4.5 3.0 Max 0 5.5 5.5
Unit V V
VSS_LV3
VSS0.1 VSS+0.1
V
VDD_BV4
— Voltage drop2
4.5 3.0
5.5 5.5
V
Relative to VDD VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) Voltage drop2 Relative to VDD VIN SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD slope to ensure correct power up6 SR Ambient temperature under bias SR Junction temperature under bias SR Ambient temperature under bias SR Junction temperature under bias SR Ambient temperature under bias SR Junction temperature under bias — Relative to VDD — — — fCPU < 64 MHz — fCPU < 64 MHz — fCPU < 64 MHz — —
VDD0.1 VDD+0.1 VSS0.1 VSS+0.1 V
VDD_ADC5
—
4.5 3.0
5.5 5.5
V
VDD0.1 VDD+0.1 VSS0.1 — 5 50 — 40 40 40 40 40 40 — VDD+0.1 5 50 0.25 85 110 105 130 125 150 V/µs °C mA V
IINJPAD IINJSUM TVDD TA C-Grade Part TJ C-Grade Part TA V-Grade Part TJ V-Grade Part TA M-Grade Part TJ M-Grade Part
1 2 3 4 5 6
100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 37
Electrical characteristics
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
4.6
4.6.1
Thermal characteristics
Package thermal characteristics
Table 10. LQFP thermal characteristics1
Symbol RJA CC C D Parameter Thermal resistance, junction-to-ambient natural convection3 Conditions2 Single-layer board - 1s Pin count 64 100 144 Four-layer board - 2s2p 64 100 144 RJB CC D Thermal resistance, junction-to-board4 Single-layer board - 1s 64 100 144 Four-layer board - 2s2p 64 100 144 RJC CC D Thermal resistance, junction-to-case5 Single-layer board - 1s 64 100 144 Four-layer board - 2s2p 64 100 144 JB CC D Junction-to-board thermal characterization parameter, natural convection Single-layer board - 1s 64 100 144 Four-layer board - 2s2p 64 100 144 Value 60 64 64 42 51 49 24 36 37 24 34 35 11 22 22 11 22 22 TBD 33 34 TBD 34 35 °C/W °C/W °C/W Unit °C/W
MPC5604B/C Microcontroller Data Sheet, Rev. 8 38 Freescale Semiconductor
Electrical characteristics
Table 10. LQFP thermal characteristics1 (continued)
Symbol JC CC C D Parameter Junction-to-case thermal characterization parameter, natural convection Conditions2 Single-layer board - 1s Pin count 64 100 144 Four-layer board - 2s2p 64 100 144
1 2
Value TBD 9 10 TBD 9 10
Unit °C/W
Thermal characteristics are based on simulation. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C 3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 4 Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 39
Electrical characteristics
4.6.2
Power considerations
TJ = TA + (PD x RJA) Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Eqn. 1
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 °C) Therefore, solving equations 1 and 2: K = PD x (TA + 273 °C) + RJA x PD2 Eqn. 3 Eqn. 2
Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA.
4.7
4.7.1
• • • •
I/O pad electrical characteristics
I/O pad types
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability. Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC) providing low input leakage.
The device provides four main I/O pad types depending on the associated alternate functions:
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 40 Freescale Semiconductor
Electrical characteristics
4.7.2
I/O input DC characteristics
Figure 7. I/O input DC electrical characteristics definition
VIN VDD VIH
Table 11 provides input DC electrical characteristics as described in Figure 7.
VHYS
VIL
PDIx = ‘1’ (GPDI register of SIUL)
PDIx = ‘0’
Table 11. I/O input DC electrical characteristics
Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) — — — No injection on adjacent pin TA = 40 °C TA = 25 °C TA = 105 °C TA = 125 °C — — 0.65VDD 0.4 0.1VDD — — — — — 1000 Value Unit Typ — — — 2 2 12 70 — — Max VDD+0.4 0.35VDD — — — 500 1000 40 — ns ns nA V
VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P D P WFI
1 2 2
SR P Wakeup input filtered pulse
WNFI2 SR P Wakeup input not filtered pulse
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 41
Electrical characteristics
4.7.3
• • • •
I/O output DC characteristics
Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 13 provides output driver characteristics for I/O pads when in SLOW configuration. Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 15 provides output driver characteristics for I/O pads when in FAST configuration. Table 12. I/O pull-up/pull-down DC electrical characteristics
The following tables provide DC characteristics for bidirectional pads:
Symbol
C
Parameter
Conditions1 Min VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0 PAD3V5V = 1 VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0 PAD3V5V = 1 VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1
2
Value Unit Typ — — — — — — Max 150 250 150 150 250 150 µA µA 10 10 10 10 10 10
|IWPU| CC P Weak pull-up current absolute value C P |IWPD| CC P Weak pull-down current absolute value C P
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 13. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min VOH CC P Output high level SLOW configuration C C Push Pull IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) Push Pull IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ — Max — V
0.8VDD VDD0.8
— —
— —
VOL CC P Output low level SLOW configuration C C
—
—
0.1VDD
V
— —
— —
0.1VDD 0.5
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 42 Freescale Semiconductor
Electrical characteristics
Table 14. MEDIUM configuration output buffer electrical characteristics
Symbol C Parameter Conditions1 Min Push Pull IOH = 3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 P IOH = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOH = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOH = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD 0.8VDD Value Unit Typ — — Max — — V
C C
0.8VDD VDD0.8
— —
— —
C
0.8VDD — —
— — —
— 0.2VDD 0.1VDD V
VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 P IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) IOL = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0
C C
— —
— —
0.1VDD 0.5
C
1 2
—
—
0.1VDD
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 15. FAST configuration output buffer electrical characteristics
Symbol C Parameter Push Pull Conditions1 Min VOH CC P Output high level FAST configuration C C IOH = 14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOH = 7mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOH = 11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) 0.8VDD Value Unit Typ — Max — V
0.8VDD VDD0.8
— —
— —
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 43
Electrical characteristics
Table 15. FAST configuration output buffer electrical characteristics (continued)
Symbol C Parameter Push Pull Conditions1 Min VOL CC P Output low level FAST configuration C C IOL = 14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) IOL = 7mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 IOL = 11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) — Value Unit Typ — Max 0.1VDD V
— —
— —
0.1VDD 0.5
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
4.7.4
Output pin transition times
Table 16. Output pin transition times
Value Unit Min Typ — — — — — — — — — — — — — — — — — — Max 50 100 125 50 100 125 10 20 40 12 25 40 4 6 12 4 7 12 ns ns ns — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — — — — — — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — —
Symbol
C
Parameter
Conditions1 CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF
2
Ttr CC D Output transition time output pin2 SLOW configuration T D D T D Ttr CC D Output transition time output pin2 MEDIUM configuration T D D T D Ttr CC D Output transition time output pin FAST configuration
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 25 pF CL = 50 pF CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 8 44 Freescale Semiconductor
Electrical characteristics
2
CL includes device and package capacitances (CPKG < 5 pF).
4.7.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 17. Table 18 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 17. I/O supply segment
Supply segment Package 1 208 MAPBGA1 144 LQFP 100 LQFP 64 LQFP
1 2 2
2
3
4
5 MCKO — — —
6 MDOn/MSEO — — —
Equivalent to 144 LQFP segment pad distribution pin20–pin49 pin16–pin35 pin8–pin26 pin51–pin99 pin37–pin69 pin28–pin55 pin100–pin122 pin 123–pin19 pin70–pin83 pin56–pin7 pin 84–pin15 —
208 MAPBGA available only as development package for Nexus2+ All 64 LQFPinformation is indicative and must be confirmed during silicon validation.
Table 18. I/O consumption
Symbol ISWTSLW,2 C Parameter CL = 25 pF Conditions1 Min CC D Dynamic I/O current for SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — — — — Value Unit Typ — — — — — — Max 20 16 29 17 110 50 mA mA mA
ISWTMED2
CC D Dynamic I/O current for MEDIUM configuration
ISWTFST2
CC D Dynamic I/O current for FAST configuration
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 45
Electrical characteristics
Table 18. I/O consumption (continued)
Symbol IRMSSLW C Parameter Conditions1 Min CC D Root medium square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz IRMSMED CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%, I/O current for PAD3V5V = 0 CL = 25 pF, 40 MHz MEDIUM configuration CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz IRMSFST CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%, I/O current for FAST PAD3V5V = 0 CL = 25 pF, 64 MHz configuration CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz CL = 100 pF, 40 MHz IAVGSEG SR D Sum of all the static I/O current within a supply segment VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — — — — — — — — — — — — — — — Value Unit Typ — — — — — — — — — — — — — — — — — — — — Max 2.3 3.2 6.6 1.6 2.3 4.7 6.6 13.4 18.3 5 8.5 11 22 33 56 14 20 35 70 65 mA mA mA mA
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 19 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below the 100%. Table 19. I/O weight1
144/100 LQFP PAD 64 LQFP2
Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 10% 10% 9% 9% — — — 13% 12% 12% 11% 11% — — — 12% 10% 10% 9% 9% — — — 13% 12% 12% 11% 11% — — — 12%
PB[3] PC[9] PC[14] PC[15]
MPC5604B/C Microcontroller Data Sheet, Rev. 8 46 Freescale Semiconductor
Electrical characteristics
Table 19. I/O weight1
144/100 LQFP PAD 64 LQFP2
Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 9% 9% 9% 8% 8% 8% 7% 7% 7% 6% 6% 5% 5% 9% 9% 9% 9% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 9% 8% 8% 8% 7% — 12% — 12% — — — 10% 9% — — 8% — — — — 13% 14% 14% 14% — — 15% 15% — — 14% — 12% — 11% — 10% 11% 10% 10% 10% 9% 9% 9% 8% 8% 7% 7% 6% 6% 10% 11% 11% 11% 11% 12% 12% 12% 12% 12% 12% 12% 12% 12% 11% 10% 10% 9% 9% 9% — 11% — 10% — — — 9% 8% — — 7% — — — — 12% 12% 12% 12% — — 13% 13% — — 12% — 11% — 10% — 9% 9% 9% 9% 8% 8% 8% 7% 7% 7% 6% 6% 5% 5% 9% 9% 9% 9% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 9% 8% 8% 8% 7% — 12% — 12% — — — 10% 9% — — 8% — — — — 13% 14% 14% 14% — — 15% 15% — — 14% — 12% — 11% — 10% 11% 10% 10% 10% 9% 9% 9% 8% 8% 7% 7% 6% 6% 10% 11% 11% 11% 11% 12% 12% 12% 12% 12% 12% 12% 12% 12% 11% 10% 10% 9% 9% 9% — 11% — 10% — — — 9% 8% — — 7% — — — — 12% 12% 12% 12% — — 13% 13% — — 12% — 11% — 10% — 9%
PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13]
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 47
Electrical characteristics
Table 19. I/O weight1
144/100 LQFP PAD 64 LQFP2
Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 7% 1% 1% 6% 6% 7% 7% 7% 8% 8% 8% 9% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 11% 11% 11% 10% 10% — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 8% 1% 1% 7% 7% 8% 8% 9% 9% 10% 10% 10% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 13% 13% 13% 12% 12% — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 7% 1% 1% 6% 6% 7% 7% 8% 8% 8% 9% 9% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 17% 18% 18% 18% 18% — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 8% 1% 1% 7% 7% 8% 8% 9% 9% 10% 10% 11% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 2% 2% 2% 2% 2% 2% 21% 21% 21% 21% 21% — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PA[12] PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] PB[5] PB[6] PB[7] PD[9] PD[10] PD[11] PB[11] PD[12] PB[12] PD[13] PB[13]
MPC5604B/C Microcontroller Data Sheet, Rev. 8 48 Freescale Semiconductor
Electrical characteristics
Table 19. I/O weight1
144/100 LQFP PAD 64 LQFP2
Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 10% 10% 10% 9% 9% 9% 9% 5% 5% 5% 4% 4% 3% 3% 4% 4% 5% 5% 5% 6% 6% 7% 7% 7% 7% 7% 6% 6% 6% 6% 5% 5% 5% — — — — — 13% 12% 8% 7% 6% 6% — 4% — 5% — — — — — — — — 10% — 9% — 9% — 8% 7% — — 12% 12% 11% 11% 11% 10% 10% 6% 6% 5% 5% 4% 4% 4% 5% 5% 6% 6% 6% 7% 8% 8% 8% 8% 8% 8% 8% 7% 7% 7% 6% 6% 5% — — — — — 11% 11% 7% 6% 6% 5% — 4% — 5% — — — — — — — — 9% — 8% — 8% — 7% 6% — — 18% 18% 18% 18% 18% 18% 18% 18% 18% 18% 18% 18% 17% 17% 16% 16% 16% 16% 15% 15% 14% 11% 10% 10% 9% 9% 8% 8% 7% 6% 6% 5% 5% — — — — — 26% 26% 26% 26% 25% 25% — 25% — 23% — — — — — — — — 14% — 12% — 11% — 9% 8% — — 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 21% 20% 20% 19% 19% 19% 18% 18% 17% 14% 12% 12% 11% 10% 10% 9% 9% 8% 7% 6% 5% — — — — — 23% 23% 23% 23% 22% 22% — 22% — 21% — — — — — — — — 12% — 11% — 10% — 8% 7% — —
PD[14] PB[14] PD[15] PB[15] PA[3] PG[13] PG[12] PH[0] PH[1] PH[2] PH[3] PG[1] PG[0] PF[15] PF[14] PE[13] PA[7] PA[8] PA[9] PA[10] PA[11] PE[12] PG[14] PG[15] PE[14] PE[15] PG[10] PG[11] PC[3] PC[2] PA[5] PA[6] PC[1]
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 49
Electrical characteristics
Table 19. I/O weight1
144/100 LQFP PAD 64 LQFP2
Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 6% 7% 8% 8% 8% 8% 9% 9% 9% 9% 9% 10% 10% 10% 10% 10% 10% 10% 9% 10% 11% 11% 12% 12% 12% 13% — 13% 13% 14% 14% 14% 14% — — 15% 7% 9% 9% 9% 10% 10% 10% 11% 11% 11% 11% 11% 12% 12% 12% 12% 12% 12% 8% 9% 9% 10% 10% 11% 11% 11% — 12% 12% 12% 12% 12% 13% — — 13% 6% 7% 8% 8% 8% 8% 9% 9% 9% 9% 9% 10% 10% 10% 10% 10% 10% 10% 9% 10% 11% 11% 12% 12% 12% 13% — 13% 13% 14% 14% 14% 14% — — 15% 7% 9% 9% 9% 10% 10% 10% 11% 11% 11% 11% 11% 12% 12% 12% 12% 12% 12% 8% 9% 9% 10% 10% 11% 11% 11% — 12% 12% 12% 12% 12% 13% — — 13%
PC[0] PE[2] PE[3] PC[5] PC[4] PE[4] PE[5] PH[4] PH[5] PH[6] PH[7] PH[8] PE[6] PE[7] PC[12] PC[13] PC[8] PB[2]
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified All 64 LQFPinformation is indicative and must be confirmed during silicon validation.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 50 Freescale Semiconductor
Electrical characteristics
4.8
RESET electrical characteristics
Figure 8. Start-up reset requirements
VDD VDDMIN
The device implements a dedicated bidirectional RESET pin.
RESET
VIH VIL device reset forced by RESET device start-up phase
Figure 9. Noise filtering on reset signal
VRESET hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 51
Electrical characteristics
Table 20. Reset electrical characteristics
Symbol VIH VIL VHYS VOL C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level — — — Push Pull, IOL = 2mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 Push Pull, IOL = 1mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) CL = 25pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 50pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 100pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 25pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 50pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 WFRST SR P RESET input filtered pulse WNFRST SR P RESET input not filtered pulse |IWPU| CC P Weak pull-up current absolute value P C
1 2
Value Unit Typ — — — — Max VDD+0.4 0.35VDD — 0.1VDD V V V V 0.65VDD 0.4 0.1VDD —
C C
— —
— —
0.1VDD 0.5
Ttr
CC D Output transition time output pin3
— — — — — — — 1000 10 10 10
— — — — — — — — — — —
10 20 40 12 25 40 40 — 150 150 250
ns
— — VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 5.0 V ± 10%, PAD3V5V = 12
ns ns µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range. 3 C includes device and package capacitance (C L PKG < 5 pF).
MPC5604B/C Microcontroller Data Sheet, Rev. 8 52 Freescale Semiconductor
Electrical characteristics
4.9
4.9.1
• • •
Power management electrical characteristics
Voltage regulator electrical characteristics
HV—High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV—High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: — LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. — LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. — LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 10. Voltage regulator capacitance connection
CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_LV
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
VDD_BV VREF CDEC1 (Ballast decoupling) CREG1 (LV_COR/LV_DFLA)
VDD_BV
VDD_LV
VDD_LVn Voltage Regulator
DEVICE
I
VSS_LVn
VSS_LV VSS_LV VDD_LV VSS VDD
GND
DEVICE
GND
GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling)
The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 53
Electrical characteristics
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5, “Recommended operating conditions). Table 21. Voltage regulator electrical characteristics
Symbol CREGn RREG CDEC1 C Parameter Conditions1 Min SR — Internal voltage regulator external capacitance SR — Stability capacitor equivalent serial resistance SR — Decoupling capacitance2 ballast — — VDD_BV/VSS_LV pair: VDD_BV = 4.5 V to 5.5 V VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V CDEC2 VMREG SR — Decoupling capacitance regulator supply CC T Main regulator output voltage P IMREG IMREGINT SR — Main regulator current provided to VDD_LV domain CC D Main regulator module current consumption VDD/VSS pair Before exiting from reset After trimming — IMREG = 200 mA IMREG = 0 mA 200 — 1003 400 10 — 1.15 — — — 1.15 — — — 1.15 — — — — 100 1.32 1.28 — — — 1.23 — — 5 1.23 — — 2 — Value Unit Typ — — 4704 Max 500 0.2 — — — — 1.32 150 2 1 1.32 15 600 — 1.32 5 100 — 4006 mA V mA µA V mA µA mA mA nF V nF nF
VLPREG ILPREG ILPREGINT
CC P Low power regulator output voltage After trimming SR — Low power regulator current provided to VDD_LV domain —
CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 °C — ILPREG = 0 mA; TA = 55 °C After trimming — IULPREG = 5 mA; TA = 55 °C IULPREG = 0 mA; TA = 55 °C
VULPREG IULPREG IULPREGINT
CC P Ultra low power regulator output voltage SR — Ultra low power regulator current provided to VDD_LV domain CC D Ultra low power regulator module current consumption
IDD_BV
1 2
CC D In-rush current on VDD_BV during power-up5
—
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 3 This value is acceptable to guarantee operation from 4.5 V to 5.5 V
MPC5604B/C Microcontroller Data Sheet, Rev. 8 54 Freescale Semiconductor
Electrical characteristics
4
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 5 In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external LV capacitances to be load) 6 The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
4.9.2
• • • • •
Voltage monitor electrical characteristics
POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0
The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied:
NOTE
When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 11. Low voltage monitor vs reset
VDD
VLVDHVxH VLVDHVxL
RESET
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 55
Electrical characteristics
Table 22. Low voltage monitor electrical characteristics
Symbol VPORUP VPORH C Parameter Conditions1 Min SR P Supply for functional POR module CC P Power-on reset threshold T VLVDHV3H VLVDHV3L VLVDHV5H VLVDHV5L CC T LVDHV3 low voltage detector high threshold CC P LVDHV3 low voltage detector low threshold CC T LVDHV5 low voltage detector high threshold CC P LVDHV5 low voltage detector low threshold — TA = 25 °C, after trimming — — 1.0 1.5 1.5 — 2.6 — 3.8 1.08 1.08 Value Unit Typ — — — — — — — — — Max 5.5 2.6 2.6 2.95 2.9 4.5 4.4 1.15 1.14 V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
4.10
Low voltage domain power consumption
Table 23. Low voltage power domain electrical characteristics
Symbol IDDMAX2 IDDRUN4 C Parameter Conditions1 Min CC D RUN mode maximum average current CC T RUN mode typical average current5 T T P P IDDHALT CC C HALT mode P IDDSTOP CC P STOP mode current D D D P
7
Table 23 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application.
Value Unit Typ 115 7 18 29 40 51 8 14 180 500 1 2 4.5 Max 1403 — — — — — 15 25 7008 — — — 128 mA µA mA mA mA — — — — — — — — — — — — —
— fCPU = 8 MHz fCPU = 16 MHz fCPU = 32 MHz fCPU = 48 MHz fCPU = 64 MHz
current6
Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 125 °C Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 55 °C TA = 85 °C TA = 105 °C TA = 125 °C
MPC5604B/C Microcontroller Data Sheet, Rev. 8 56 Freescale Semiconductor
Electrical characteristics
Table 23. Low voltage power domain electrical characteristics (continued)
Symbol IDDSTDBY2 C Parameter Conditions1 Min CC P STANDBY2 mode current9 Slow internal RC oscillator TA = 25 °C (128 kHz) running D TA = 55 °C D D P IDDSTDBY1 CC T STANDBY1 mode current10 D D D D
1 2
Value Unit Typ 30 75 180 315 560 20 45 100 165 280 Max 100 — — — 1700 60 — — — 900 µA µA — — — — — — — — — —
TA = 85 °C TA = 105 °C TA = 125 °C Slow internal RC oscillator TA = 25 °C (128 kHz) running TA = 55 °C TA = 85 °C TA = 105 °C TA = 125 °C
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components: IDDMAX = IDD(vdd_bv) + IDD(vdd_hv) + IDD(Vdd_hv_adc). It does not include a fourth component linked to I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3 Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 21. 4 RUN current measured with typical application with accesses on both flash and RAM. 5 Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6 Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue watchdog 7 Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8 When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9 Only for the “P” classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum consumption, all possible modules switched-off. 10 ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules switched-off.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 57
Electrical characteristics
4.11
4.11.1
Flash memory electrical characteristics
Program/Erase characteristics
Table 24. Program and erase specifications
Value Symbol C Parameter Min Typ1 22 300 400 800 — Initial max2 50 500 600 1300 30 Max3 500 5000 5000 7500 30 Unit
Table 24 shows the program and erase characteristics.
Tdwprogram CC C Double word (64 bits) program time4 T16Kpperase T32Kpperase T128Kpperase Tesus
1 2
— — — — —
µs ms ms ms µs
16 KB block pre-program and erase time 32 KB block pre-program and erase time 128 KB block pre-program and erase time CC D Erase Suspend Latency
Typical program and erase times assume nominal supply values and operation at 25 °C. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.
Table 25. Flash module life
Value Symbol P/E C Parameter Conditions Min CC C Number of program/erase cycles per block for 16 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 32 KB blocks over the operating temperature range (TJ) CC C Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) — 100,000 Typ — Max — cycles Unit
P/E
—
10,000 100,000
—
cycles
P/E
—
1,000
100,000
—
cycles
Retention CC C Minimum data retention at 85 °C average ambient temperature1
Blocks with 0–1,000 P/E cycles Blocks with 1,001–10,000 P/E cycles Blocks with 10,001–100,000 P/E cycles
20 10
— —
— —
years years
5
—
—
years
MPC5604B/C Microcontroller Data Sheet, Rev. 8 58 Freescale Semiconductor
Electrical characteristics
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 26. Flash read access timing
Symbol fREAD C Parameter Conditions1 2 wait states 1 wait state 0 wait states Max 64 40 20 Unit MHz
CC P Maximum frequency for Flash reading C C
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 59
Electrical characteristics
4.11.2
Flash power supply DC characteristics
Table 27. Code Flash power supply DC electrical characteristics
Table 27 shows the power supply DC characteristics on external supply.
Symbol
C
Parameter
Conditions1 Min Code Flash module read fCPU = 64 MHz3 Data Flash module read fCPU = 64 MHz3 — — —
Value Unit Typ 15 15 15 Max 33 33 33 mA mA
IFREAD2 CC D Sum of the current consumption on VDDHV and VDDBV on read access
IFMOD2 CC D Sum of the current consumption on VDDHV and VDDBV on matrix modification (program/erase)
Program/Erase on-going while reading Code Flash registers fCPU = 64 MHz3 Program/Erase on-going while reading Data Flash registers fCPU = 64 MHz3
—
15
33
IFLPW
CC D Sum of the current consumption on VDDHV and VDDBV
during Code Flash low-power mode during Data Flash low-power mode
— — — —
— — — —
900 900 150 150
µA
IFPWD
CC D Sum of the current consumption on VDDHV and VDDBV
during Code Flash power-down mode during Data Flash power-down mode
µA
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified This value is only relative to the actual duration of the read cycle 3f CPU 64 MHz can be achieved only at up to 105 °C
1
MPC5604B/C Microcontroller Data Sheet, Rev. 8 60 Freescale Semiconductor
Electrical characteristics
4.11.3
Start-up/Switch-off timings
Table 28. Start-up time/Switch-off time
Symbol C Parameter Conditions1 Min Code Flash Data Flash Code Flash Data Flash Code Flash Data Flash Code Flash Data Flash Code Flash Data Flash — — — — — — — — — — Value Unit Typ — — — — — — — — — — Max 125 125 0.5 0.5 30 30 0.5 0.5 1.5 1.5 µs
TFLARSTEXIT
CC T Delay for Flash module to exit reset mode T
TFLALPEXIT
CC T Delay for Flash module to exit low-power mode T CC T Delay for Flash module to exit power-down mode T
TFLAPDEXIT
TFLALPENTRY CC T Delay for Flash module to enter low-power mode T TFLAPDENTRY CC T Delay for Flash module to enter power-down T mode
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 61
Electrical characteristics
4.12
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.12.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. • Software recommendations:The software flowchart must include the management of runaway conditions such as: — Corrupted program counter — Unexpected reset — Critical data corruption (control registers...) Prequalification trials:Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
•
4.12.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 29. EMI radiated emission measurement1,2
Value Symbol — C Parameter Conditions Min SR — Scan range — — — No PLL frequency VDD = 5 V, TA = 25 °C, modulation LQFP144 package Test conforming to IEC 61967-2, ± 2% PLL frequency fOSC = 8 MHz/fCPU = 64 MHz modulation 0.150 — — — — Typ — 64 1.28 — — Max 1000 MHz — — 18 14 MHz V dBµV dBµV Unit
fCPU SR — Operating frequency VDD_LV SR — LV operating voltages SEMI CC T Peak level
1 2
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative.
4.12.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 62 Freescale Semiconductor
Electrical characteristics
4.12.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 30. ESD absolute maximum ratings1 2
Symbol C Ratings Conditions TA = 25 °C conforming to AEC-Q100-002 TA = 25 °C conforming to AEC-Q100-003 TA = 25 °C conforming to AEC-Q100-011 Class H1C M2 C3A Max value 2000 200 500 750 (corners) Unit V
VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) VESD(MM) CC T Electrostatic discharge voltage (Machine Model) VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
4.12.3.2
• •
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 31. Latch-up results
Symbol LU CC C Parameter Conditions TA = 125 °C conforming to JESD 78 Class II level A
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
T Static latch-up class
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 63
Electrical characteristics
4.13
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
The device provides an oscillator/resonator driver. Figure 12 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 32 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. Figure 12. Crystal oscillator and resonator connection scheme
EXTAL C1 Crystal XTAL EXTAL
DEVICE
VDD
C2
I
R
EXTAL XTAL Resonator XTAL
DEVICE
DEVICE
Note: XTAL/EXTAL must not be directly used to drive external circuits.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 64 Freescale Semiconductor
Electrical characteristics
Table 32. Crystal description
Crystal equivalent series resistance ESR 300 300 150 120 120 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00
Nominal frequency (MHz)
NDK crystal reference
4 8 10 12 16
1
NX8045GB NX5032GA
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.).
Figure 13. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
S_MTRANS bit (ME_GS register) ‘1’
‘0’ VXTAL VFXOSC VFXOSCOP 10% TFXOSCSU valid internal clock
1/fFXOSC 90%
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 65
Electrical characteristics
Table 33. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics
Symbol fFXOSC gmFXOSC C Parameter Conditions1 Min SR — Fast external crystal oscillator frequency CC C Fast external crystal oscillator transconductance CC P — VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VFXOSCOP CC P Oscillation operating point IFXOSC,2 TFXOSCSU CC T Fast external crystal oscillator consumption CC T Fast external crystal oscillator start-up time — — fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VIH VIL
1 2
Value Unit Typ — — Max 16.0 8.2 MHz mA/V 4.0 2.2
2.0
—
7.4
CC C
2.7
—
9.7
CC C
2.5
—
9.2
VFXOSC
CC T Oscillation amplitude at EXTAL
1.3 1.3 — — — — 0.65VDD 0.4
— — 0.95 2 — — — —
— —
V
V 3 6 1.8 VDD+0.4 0.35VDD V V mA ms
SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger)
Oscillator bypass mode Oscillator bypass mode
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 66 Freescale Semiconductor
Electrical characteristics
4.14
Slow external crystal oscillator (32 kHz) electrical characteristics
Figure 14. Crystal oscillator and resonator connection scheme
The device provides a low power oscillator/resonator driver.
OSC32K_EXTAL C1
OSC32K_EXTAL Resonator OSC32K_XTAL C2
OSC32K_XTAL
DEVICE
Crystal
DEVICE
Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
Figure 15. Equivalent circuit of a quartz crystal
C0
C1
Crystal
C2 C1
Cm
Rm
Lm C2
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 67
Electrical characteristics
Table 34. Crystal motional characteristics1
Value Symbol Lm Cm Parameter Motional inductance Motional capacitance Conditions Min — — — AC coupled @ C0 = 2.85 pF4 AC coupled @ C0 = 4.9 pF
4
Unit Typ 11.796 2 — — — — — Max — — 28 65 50 35 30 KH fF pF k — — 18 — — — —
C1/C2 Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground2 Rm3 Motional resistance
AC coupled @ C0 = 7.0 pF4 AC coupled @ C0 = 9.0 pF
1 2 4
The crystal used is Epson Toyocom MC306. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 Maximum ESR (R ) of the crystal is 50 k m 4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins
Figure 16. Slow external crystal oscillator (32 kHz) electrical characteristics
OSCON bit (OSC_CTL register) 1
0
VOSC32K_XTAL VSXOSC 90%
1/fSXOSC
10% TSXOSCSU valid internal clock
MPC5604B/C Microcontroller Data Sheet, Rev. 8 68 Freescale Semiconductor
Electrical characteristics
Table 35. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol fSXOSC VSXOSC C Parameter Conditions1 Min SR — Slow external crystal oscillator frequency CC T Oscillation amplitude — — — — — 32 — — — — Value Unit Typ 32.768 2.1 2.5 — — Max 40 — — 8 22 kHz V µA µA s
ISXOSCBIAS CC T Oscillation bias current ISXOSC TSXOSCSU
1 2
CC T Slow external crystal oscillator consumption CC T Slow external crystal oscillator start-up time
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal
4.15
FMPLL electrical characteristics
Table 36. FMPLL electrical characteristics
Symbol fPLLIN C Parameter Conditions1 Min SR — FMPLL reference clock2 SR — FMPLL reference clock duty cycle2 — — — — — — — Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles TA = 25 °C — — 4 40 16 256 245 — 20 Value Unit Typ — — — — — — — 40 — — Max 64 60 64 512 533 64 150 100 10 4 MHz MHz µs ns mA MHz % MHz MHz
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver.
PLLIN
fPLLOUT CC D FMPLL output clock frequency fVCO3 CC P VCO frequency without frequency modulation C VCO frequency with frequency modulation fCPU fFREE tLOCK SR — System clock frequency CC P Free-running frequency CC P FMPLL lock time
tLTJIT CC — FMPLL long term jitter IPLL
1 2
CC C FMPLL consumption
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3 Frequency modulation is considered ± 4%
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 69
Electrical characteristics
4.16
Fast internal RC oscillator (16 MHz) electrical characteristics
Table 37. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol fFIRC C Parameter Conditions1 Min CC P Fast internal RC oscillator high TA = 25 °C, trimmed frequency SR — — — 12 — — Value Unit Typ 16 Max — 20 200 µA MHz
The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.
IFIRCRUN2, CC T Fast internal RC oscillator high TA = 25 °C, trimmed frequency current in running mode IFIRCPWD CC D Fast internal RC oscillator high TA = 125 °C frequency current in power down mode sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz TFIRCSU FIRCPRE CC C Fast internal RC oscillator start-up time CC T Fast internal RC oscillator precision after software trimming of fFIRC VDD = 5.0 V ± 10% TA = 25 °C
—
—
10
µA
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C frequency and system clock current in stop mode
— — — — — — 1
500 600 700 900 1250 1.1 —
— — — — — 2.0 +1
µA
µs %
FIRCTRIM CC T Fast internal RC oscillator trimming step FIRCVAR CC P Fast internal RC oscillator variation in overtemperature and supply with respect to fFIRC at TA = 25 °C in high-frequency configuration
TA = 25 °C —
— 5
1.6 — +5
% %
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
4.17
Slow internal RC oscillator (128 kHz) electrical characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 70 Freescale Semiconductor
Electrical characteristics
Table 38. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol fSIRC ISIRC2, TSIRCSU SIRCPRE SIRCTRIM SIRCVAR C Parameter Conditions1 Min CC P Slow internal RC oscillator low frequency SR — CC C Slow internal RC oscillator low frequency current TA = 25 °C, trimmed — TA = 25 °C, trimmed — 100 — — 2 — — 10 Value Unit Typ 128 — — 8 — 2.7 — Max — 150 5 12 +2 — +10 % µA µs % kHz
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10% time CC C Slow internal RC oscillator precision TA = 25 °C after software trimming of fSIRC CC C Slow internal RC oscillator trimming step
CC C Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 °C in high frequency configuration
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 71
Electrical characteristics
4.18
4.18.1
ADC electrical characteristics
Introduction
Figure 17. ADC characteristic and error definitions
Offset Error OSE 1023 Gain Error GE
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.
1022 1021
1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2)
code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
2 1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal)
Offset Error OSE
4.18.2
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
MPC5604B/C Microcontroller Data Sheet, Rev. 8 72 Freescale Semiconductor
Electrical characteristics
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD - -V A -------------------------------------------------------------------------- 1 LSB R EQ 2
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 73
Electrical characteristics
Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 18. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP2
CS
RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 19. Input equivalent circuit (extended channels)
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2
Sampling
Source RS
Filter RF
Current Limiter RL
RAD
VA
CF
CP1
CP3
CP2
CS
RS RF CF RL RSW RAD CP CS
Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance
MPC5604B/C Microcontroller Data Sheet, Rev. 8 74 Freescale Semiconductor
Electrical characteristics
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 18): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 20. Transient behavior during sampling phase
VCS VA VA2
Voltage transient on CS V 1 Slave mode Slave mode Master mode Slave mode Slave mode Slave mode
—
tASC
—
—
1303
—
—
1303
ns
2 3 4
tCSCext4 SR D CS to SCK delay tASCext5 SR D After SCK delay tSDC CC D SCK duty cycle SR D
32 1/fDSPI + 5 — tSCK/2 — 7 43 5 0 26
— — tSCK/2 — — — — — — —
— — — — 1/fDSPI + 70 — — — — —
32 1/fDSPI + 5 — tSCK/2 — 7 145 5 0 26
— — tSCK/2 — — — — — — —
— — — — 1/fDSPI + 130 — — — — —
ns ns ns
5 6 9
tA tDI tSUI
SR D Slave access time SR D Slave SOUT disable time
ns ns ns
SR D Data setup time for inputs Master mode Slave mode
10
tHI
SR D Data hold time for inputs
Master mode Slave mode
ns
Table 42. DSPI characteristics1 (continued)
DSPI0/DSPI1 No. 11 Symbol tSUO7 tHO7 C Parameter Min CC D Data valid after SCK edge Master mode Slave mode 12 CC D Data hold time for outputs Master mode Slave mode
1 2
82 MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor
3 4 5 6 7
DSPI2 Unit Max 32 52 — — Min — — 0 13 Typ — — — — Max 50 160 — — ns ns
Electrical characteristics
Typ — — — —
— — 0 8
Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is asserted. DSPI2 has only SLOW SCK available. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. SCK and SOUT configured as MEDIUM pad
Electrical characteristics
Figure 22. DSPI classic SPI timing – master, CPHA = 0
2 PCSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 10 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Note: Numbers shown reference Table 42
Figure 23. DSPI classic SPI timing – master, CPHA = 1
PCSx
SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Note: Numbers shown reference Table 42
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 83
Electrical characteristics
Figure 24. DSPI classic SPI timing – slave, CPHA = 0
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Note: Numbers shown reference Table 42.
Figure 25. DSPI classic SPI timing – slave, CPHA = 1
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 42
MPC5604B/C Microcontroller Data Sheet, Rev. 8 84 Freescale Semiconductor
Electrical characteristics
Figure 26. DSPI modified transfer format timing – master, CPHA = 0
3 PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Note: Numbers shown reference Table 42.
Figure 27. DSPI modified transfer format timing – master, CPHA = 1
PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Note: Numbers shown reference Table 42
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 85
Electrical characteristics
Figure 28. DSPI modified transfer format timing – slave, CPHA = 0
3
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 4
6
Last Data 10 Last Data
Note: Numbers shown reference Table 42
Figure 29. DSPI modified transfer format timing – slave, CPHA = 1
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 42
MPC5604B/C Microcontroller Data Sheet, Rev. 8 86 Freescale Semiconductor
Electrical characteristics
4.19.3
Nexus characteristics
Table 43. Nexus characteristics
Value
No. 1 2 3 4 5 10
Symbol tTCYC tMCYC tMDOV tMSEOV tEVTOV tNTDIS tNTMSS
C
Parameter Min Typ — — — — — — — — — — — Max — — 8 8 8 — — — — — — 64 32 — — — 15 15 5 5 35 6
Unit ns ns ns ns ns ns ns ns ns ns ns
CC D TCK cycle time CC D MCKO cycle time CC D MCKO low to MDO data valid CC D MCKO low to MSEO_b data valid CC D MCKO low to EVTO data valid CC D TDI data setup time CC D TMS data setup time CC D TDI data hold time CC D TMS data hold time CC D TCK low to TDO data valid CC D TCK low to TDO data invalid
11
tNTDIH tNTMSH
12 13
tTDOV tTDOI
Figure 30. Nexus TDI, TMS, TDO timing
TCK
10 11
TMS, TDI
12
TDO
Note: Numbers shown reference Table 43
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 87
Electrical characteristics
4.19.4
JTAG characteristics
Table 44. JTAG characteristics
Value
No. 1 2 3 4 5 6 7
Symbol tJCYC tTDIS tTDIH tTMSS tTMSH tTDOV tTDOI CC CC CC CC CC CC CC
C
Parameter Min Typ — — — — — — — Max — — — — — 33 — 64 15 5 15 5 — 6
Unit ns ns ns ns ns ns ns
D TCK cycle time D TDI setup time D TDI hold time D TMS setup time D TMS hold time D TCK low to TDO valid D TCK low to TDO invalid
Figure 31. Timing diagram – JTAG boundary scan
TCK
2/4
3/5
DATA INPUTS 6
INPUT DATA VALID
DATA OUTPUTS
OUTPUT DATA VALID
7
DATA OUTPUTS
Note: Numbers shown reference Table 44
MPC5604B/C Microcontroller Data Sheet, Rev. 8 88 Freescale Semiconductor
Package characteristics
5
5.1
5.1.1
Package characteristics
Package mechanical data
64 LQFP
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 89
Package characteristics
Figure 32. 64 LQFP package mechanical drawing (1 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 90 Freescale Semiconductor
Package characteristics
Figure 33. 64 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 91
Package characteristics
Figure 34. 64 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 92 Freescale Semiconductor
Package characteristics
5.1.2
100 LQFP
Figure 35. 100 LQFP package mechanical drawing (1 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 93
Package characteristics
Figure 36. 100 LQFP package mechanical drawing (2 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 94 Freescale Semiconductor
Package characteristics
Figure 37. 100 LQFP package mechanical drawing (3 of 3)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 95
Package characteristics
5.1.3
144 LQFP
Figure 38. 144 LQFP package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 96 Freescale Semiconductor
Package characteristics
Figure 39. 144 LQFP package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 97
Package characteristics
5.1.4
208 MAPBGA
Figure 40. 208 MAPBGA package mechanical drawing (1 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 98 Freescale Semiconductor
Package characteristics
Figure 41. 208 MAPBGA package mechanical drawing (2 of 2)
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 99
Ordering information
6
Ordering information
Figure 42. Commercial product code structure
Example code: Qualification Status PowerPC Core Automotive Platform Core Version Flash Size (core dependent) Product Fab and Mask Indicator Temperature spec. Package Code Frequency R = Tape & Reel (blank if Tray) M PC 56 0 4 B F1 M LL 4 R
Qualification Status M = MC status S = Auto qualified P = PC status Automotive Platform 56 = PPC in 90nm Core Version 0 = e200z0
Flash Size (z0 core) 2 = 256 KB 3 = 384 KB 4 = 512 KB Product B = Body C = Gateway Fab and Mask Indicator F = ATMC 1 = Maskset Revision
Temperature spec. C = -40 to 85 °C V = -40 to 105 °C M = -40 to 125 °C Package Code LH = 64 LQFP LL = 100 LQFP LQ = 144 LQFP MG = 208 MAPBGA1 Frequency 4 = Up to 48 MHz 6 = Up to 64 MHz
1
208 MAPBGA available only as development package for Nexus2+
7
Document revision history
Table 45. Revision history
Revision 1 Date 04-Apr-2008 Initial release. Description of Changes
Table 45 summarizes revisions to this document.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 100 Freescale Semiconductor
Document revision history
Table 45. Revision history (continued)
Revision 2 Date Description of Changes
06-Mar-2009 Made minor editing and formatting changes to improve readability Harmonized oscillator naming throughout document Features: —Replaced 32 KB with 48 KB as max SRAM size —Updated descripiton of INTC —Changed max number of GPIO pins from 121 to 123 Updated Section 1.2, Description Updated Table 2 Added Section 2, Block diagram Section 3, Package pinouts and signal descriptions: Removed signal descriptions (these are found in the device reference manual) Updated Figure 5: —Replaced VPP with VSS_HV on pin 18 —Added MA[1] as AF3 for PC[10] (pin 28) —Added MA[0] as AF2 for PC[3] (pin 116) —Changed description for pin 120 to PH[10] / GPIO[122] / TMS —Changed description for pin 127 to PH[9] / GPIO[121] / TCK —Replaced NMI[0] with NMI on pin 11 Updated Figure 4: —Replaced VPP with VSS_HV on pin 14 —Added MA[1] as AF3 for PC[10] (pin 22) —Added MA[0] as AF2 for PC[3] (pin 77) —Changed description for pin 81 to PH[10] / GPIO[122] / TMS —Changed description for pin 88 to PH[9] / GPIO[121] / TCK —Removed E1UC[19] from pin 76 —Replaced [11] with WKUP[11] for PB[3] (pin 1) —Replaced NMI[0] with NMI on pin 7 Updated Figure 6: —Changed description for ball B8 from TCK to PH[9] —Changed description for ball B9 from TMS to PH[10] —Updated descriptions for balls R9 and T9 Added Section 4.2, Parameter classification and tagged parameters in tables where appropriate Added Section 4.3, NVUSRO register Updated Table 5 Section 4.5, Recommended operating conditions: Added note on RAM data retention to end of section Updated Table 6 and Table 7 Added Section 4.6.1, Package thermal characteristics Updated Section 4.6.2, Power considerations Updated Figure 7 Updated Table 9, Table 10, Table 11, Table 12 and Table 13 Added Section 4.7.4, Output pin transition times Updated Table 16 Updated Figure 8 Updated Table 18 Section 4.9.1, Voltage regulator electrical characteristics: Amended description of LV_PLL Figure 10: Exchanged position of symbols CDEC1 and CDEC2 Updated Table 19
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 101
Document revision history
Table 45. Revision history (continued)
Revision 2 Date Description of Changes
06-Mar-2009 Added Figure 11 Updated Table 20 and Table 21 Updated Section 4.11, Flash memory electrical characteristics Added Section 4.12, Electromagnetic compatibility (EMC) characteristics Updated Section 4.13, Fast external crystal oscillator (4 to 16 MHz) electrical characteristics Updated Section 4.14, Slow external crystal oscillator (32 kHz) electrical characteristics Updated Table 34, Table 35 and Table 36 Added Section 4.19, On-chip peripherals Added Table 37 Updated Table 38 Updated Table 47 Added Section Appendix A, Abbreviations 06-Aug-2009 Updated Figure 6 Table 5 • VDD_ADC: changed min value for “relative to VDD“ condition • VIN: changed min value for “relative to VDD“ condition • ICORELV: added new row Table 7 • TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part: added new rows • Changed capacitance value in footnote Table 14 • MEDIUM configuration: added condition for PAD3V5V = 0 Updated Figure 10 Table 19 • CDEC1: changed min value • IMREG: changed max value • IDD_BV: added max value footnote Table 20 • VLVDHV3H: changed max value • VLVDHV3L: added max value • VLVDHV5H: changed max value • VLVDHV5L: added max value Updated Table 21 Table 23 • Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“ Table 31 • IFXOSC: added typ value Table 33 • VSXOSC: changed typ value • TSXOSCSU: added max value footnote Table 34 • tLTJIT: added max value Updated Figure 36
4
MPC5604B/C Microcontroller Data Sheet, Rev. 8 102 Freescale Semiconductor
Document revision history
Table 45. Revision history (continued)
Revision 5 Date Description of Changes
02-Nov-2009 In the “MPC5604B/C series block summary“ table, added a new row. In the “Absolute maximum ratings” table, changed max value of VDD_BV, VDD_ADC, and VIN. In the ”Recommended operating conditions (3.3 V)” table, deleted min value of TVDD. In the “Reset electrical characteristics“ table, changed footnotes 3 and 5. In the “Voltage regulator electrical characteristics“ table: • CREGn: changed max value. • CDEC1: split into 2 rows. • Updated voltage values in footnote 4 In the “Low voltage monitor electrical characteristics“ table: • Updated column Conditions. • VLVDLVCORL, VLVDLVBKPL: changed min/max value. In the “Program and erase specifications“ table, added initial max valueof Tdwprogram. In the “Flash module life“ table, changed min value for blocks with 100K P/E cycles In the “Flash power supply DC electrical characteristics“ table: • IFREAD, IFMOD: added typ value. • Added footnote 1. Added “ NVUSRO[WATCHDOG_EN] field description“ section. Section 4.18: “ADC electrical characteristics“ has been moved up in hierarchy (it was Section 4.18.5). In the “ ADC conversion characteristics“ table, changed initial max value of RAD. In the “On-chip peripherals current consumption“ table: • Removed min/max from the heading. • Changed unit of measurement and consequently rounded the values.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 103
Document revision history
Table 45. Revision history (continued)
Revision 6 Date Description of Changes
15-Mar-2010 In the “Introduction” section, relocated a note. In the “MPC5604B/C device comparison“ table, added footnote regarding SCI and CAN. In the “Absolute maximum ratings“ table, removed the min value of VIN relative tio VDD. In the ”Recommended operating conditions (3.3 V)” table: • TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part: added new rows. • TVDD: made single row. In the “LQFP thermal characteristics” table, added more rows. Removed “208 MAPBGA thermal characteristics” table. In the “I/O consuption“ table: • Removed IDYNSEG row. • Added “I/O weight “ table. In the “Voltage regulator electrical characteristics“ table: • Updated the values. • Removed IVREGREF and IVREDLVD12. • Added a note about IDD_BC. In the “Low voltage monitor electrical characteristics“ table: • Updated VPORH values. • Updated VLVDLVCORL value. Entirely updated the “Low voltage power domain electrical characteristics“ table. In the “Program and erase specifications“ table, inserted Teslat row. Entirely updated the “Flash power supply DC electrical characteristics“ table. Entirely updated the “Start-up time/Switch-off time“ table. In the “Crystal oscillator and resonator connection scheme“ figure, relocated a note. In the ”Slow external crystal oscillator (32 kHz) electrical characteristics” table: • Removed gmSXOSC row. • Inserted values of ISXOSCBIAS. Entirely updated the “Fast internal RC oscillator (16 MHz) electrical characteristics“ table. In the “ADC conversion characteristics” table: updated the description of the conditions of tADC_PU and tADC_S. Entirely updated the “DSPI characteristics“ table. In the “Orderable part number summary” table, modified some orderable part number. Updated the “Commercial product code structure” figure. Removed the note about the condition from “Flash read access timing“ table Removed the notes that assert the values need to be confirmed before validation Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin configuration” Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP 144-pin package mechanical drawing”
MPC5604B/C Microcontroller Data Sheet, Rev. 8 104 Freescale Semiconductor
Document revision history
Table 45. Revision history (continued)
Revision 7 Date 05-Jul-2010 Description of Changes Added 64 LQFP package information Updated the “Features“ section. Figures “LQFP 100-pin configuration” and “LQFP 100-pin configuration”: removed alternate function information Added “Functional port pin descriptions” table Added eDMA block in the “MPC5604B/C series block diagram” figure Deleted the “NVUSRO[WATCHDOG_EN] field description“ section In the ”Recommended operating conditions (3.3 V)” and ”Recommended operating conditions (5.0 V)” tables, deleted the conditions of TA C-Grade Part, TA V-Grade Part, TA M-Grade
Part
In the “LQFP thermal characteristics” table, rounded the values. In the “RESET electrical characteristics” section, replaced “nRSTIN” with “RESET”. In the “I/O input DC electrical characteristics” table: • WFI: insered a footnote • WNFI: insered a footnote In the “Low voltage monitor electrical characteristics“ table: • changed min valueVLVDHV3L, from 2.7 to 2.6 • Inserted max value of VLVDLVCORL In the ”FMPLL electrical characteristics” table, rounded the values of fVCO. In the “DSPI characteristics” table: • Added tASC row • Update values of tA In the “ADC conversion characteristics” table, added “IADCPWD” and “IADCRUN” rows Removed “Orderable part number summary” table. 8 25-Nov-2010 Editorial changes and improvements. In the “MPC5604B/C device comparison“ table, changed the temperature value from 105 to 125 °C, in the footnote regarding “Execution speed”. In the ”Recommended operating conditions (3.3 V)” and ”Recommended operating conditions (5.0 V)” tables, restored the conditions of TA C-Grade Part, TA V-Grade Part, TA
M-Grade Part
In the “LQFP thermal characteristics” table, added values concerning 64 LQFP package. In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo in last row of conditions column, there was IOH that now is IOL. In the “Reset electrical characteristics” table, changed the parameter classification tag for VOL and |IWPU|. In the “Low voltage monitor electrical characteristics“ table, changed the max value of VLVDLVCORL from 1.5V to 1.15V. In the “Program and erase specifications“ table, replaced “Teslat” with “Tesus”. In the “FMPLL electrical characteristics” table, changed the parameter classification tag for fVCO.
MPC5604B/C Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 105
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