Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5646C Rev. 3, May 2011
MPC5646C
MPC5646C Microcontroller Data Sheet
• e200z4d dual issue, 32-bit core Power Architecture compliant CPU – Up to 120 MHz – 4 KB, 2/4-Way Set Associative Instruction Cache – Variable length encoding (VLE) – Embedded floating-point (FPU) unit – Supports Nexus3+ • e200z0h single issue, 32-bit core Power Architecture compliant CPU – Up to 80 MHz – Variable length encoding (VLE) – Supports Nexus3+ • Up to 3 MB on-chip flash memory: flash page buffers to improve access time • Up to 256 KB on-chip SRAM • 64 KB on-chip data flash memory to support EEPROM emulation • Up to 16 semaphores across all slave ports • User selectable MBIST • Low-power modes supported: STOP, HALT, STANDBY • 16 region Memory Protection Unit (MPU) • Dual-core Interrupt Controller (INTC). Interrupt sources can be routed to e200z4d, e200z0h, or both • Frequency-Modulated Phase-Locked Loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, flash memory, and SRAM from multiple bus masters • 32 channel eDMA controller with DMAMUX • Timer supports input/output channels providing 16-bit input capture, output compare, and PWM functions (eMIOS) • 2 analog-to-digital converters (ADC): one 10-bit and one 12-bit • Cross Trigger Unit (CTU) to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT • Up to 8 serial peripheral interface (DSPI) modules • Up to 10 serial communication interface (LINFlex) modules
176-pin LQFP (24 24 mm) 256 MAPBGA (17 17 mm) 208-pin LQFP (28 28 mm)
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Up to 6 full CAN (FlexCAN) modules with 64 MBs each CAN Sampler to catch ID of CAN message 1 inter IC communication interface (I2C) module Up to 177 (LQFP) or 199 (BGA) configurable general purpose I/O pins System clocks sources – 4–40 MHz external crystal oscillator – 16 MHz internal RC oscillator – FMPLL Additionally, there are two low power oscillators: 128 kHz internal RC oscillator, 32 kHz external crystal oscillator Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillators or external 4–40 MHz crystal – Supports autonomous wake-up with 1 ms resolution with max timeout of 2 seconds – Optional support from external 32 kHz crystal oscillator, supporting wake-up with 1 second resolution and max timeout of 1 hour 1 System Timer Module (STM) with four 32-bit compare channels Up to 8 periodic interrupt timers (PIT) with 32-bit counter resolution 1 Real Time Interrupt (RTI) with 32-bit counter resolution 1 Safety Enhanced Software Watchdog Timer (SWT) that supports keyed functionality 1 dual-channel FlexRay Controller with 128 message buffers 1 Fast Ethernet Controller (FEC) On-chip voltage regulator (VREG) Cryptographic Services Engine (CSE) Offered in the following standard package types: – 176-pin LQFP, 24 24 mm, 0.5 mm Lead Pitch – 208-pin LQFP, 28 28 mm, 0.5 mm Lead Pitch – 256-ball MAPBGA, 17 17mm, 1.0 mm Lead Pitch
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2010, 2011. All rights reserved. Preliminary—Subject to Change Without Notice
Table of Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .9 3.1 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.3 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2.1 NVUSRO [PAD3V5V(0)] field description . . . . .40 4.2.2 NVUSRO [PAD3V5V(1)] field description . . . . .40 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .40 4.4 Recommended operating conditions . . . . . . . . . . . . . .42 4.5 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .45 4.5.1 Package thermal characteristics . . . . . . . . . . . .45 4.5.2 Power considerations. . . . . . . . . . . . . . . . . . . . .45 4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .46 4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . .46 4.6.3 I/O output DC characteristics. . . . . . . . . . . . . . .47 4.6.4 Output pin transition times . . . . . . . . . . . . . . . . .50 4.6.5 I/O pad current specification . . . . . . . . . . . . . . .51 4.7 RESET electrical characteristics. . . . . . . . . . . . . . . . . .53 4.8 Power management electrical characteristics. . . . . . . .55 4.8.1 Voltage regulator electrical characteristics . . . .55 4.8.2 VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 Voltage monitor electrical characteristics. . . . . .57 4.9 Low voltage domain power consumption . . . . . . . . . . .58 4.10 Flash memory electrical characteristics . . . . . . . . . . . .60 4.10.1 Program/Erase characteristics. . . . . . . . . . . . . .60 4.10.2 Flash memory power supply DC characteristics62 4.10.3 Flash memory start-up/switch-off timings . . . . .63 4.11 Electromagnetic compatibility (EMC) characteristics . .63 4.11.1 Designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.11.2 Electromagnetic interference (EMI) . . . . . . . . . 64 4.11.3 Absolute maximum ratings (electrical sensitivity)64 4.12 Fast external crystal oscillator (4–40 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 70 4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 72 4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.18 Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . 82 4.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) . . . . . . . . . . . . . . . . . . . 82 4.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) . . . . . . . . . . . . . . . . . . . . . . . 83 4.18.3 MII Async Inputs Signal Timing (CRS and COL)84 4.18.4 MII Serial Management Channel Timing (MDIO and MDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . 86 4.19.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 88 4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 96 4.19.4 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . 98 Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 100 5.1.1 176 LQFP package mechanical drawing . . . . 100 5.1.2 208 LQFP package mechanical drawing . . . . 103 5.1.3 256 MAPBGA package mechanical drawing . 108 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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5
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MPC5646C Microcontroller Data Sheet, Rev. 3 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor
1
1.1
Introduction
Document Overview
This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the MPC5646C device. To ensure a complete understanding of the device functionality, refer also to the MPC5646C Reference Manual.
1.2
Description
The MPC5646C is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. The MPC5646C family expands the range of the MPC560xB microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the MPC5646C automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3
Table 1. MPC5646C family comparison1
Feature Package CPU Execution speed
2
4 MPC5644B e200z4d Up to 120 MHz (e200z4d) Code flash memory MPC5646C Microcontroller Data Sheet, Rev. 3 Data flash memory SRAM MPU eDMA
4
MPC5644C 256 BGA
MPC5645B
MPC5645C 256 BGA
MPC5646B
MPC5646C 256 BGA
176 208 176 208 LQFP LQFP LQFP LQFP
176 208 176 208 LQFP LQFP LQFP LQFP e200z4d Up to 120 MHz (e200z4d)
176 208 176 208 LQFP LQFP LQFP LQFP e200z4d Up to 120 MHz (e200z4d)
e200z4d + e200z0h Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)3 1.5 MB
e200z4d + e200z0h Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)3 2 MB 4 x16 KB
e200z4d + e200z0h Up to 120 MHz (e200z4d) Up to 80 MHz (e200z0h)3 3 MB
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
128 KB
192 KB
160 KB 16-entry 32 ch
256 KB
192 KB
256 KB
10-bit ADC dedicated5,6 shared with 12-bit ADC7 12-bit ADC dedicated8 shared with 10-bit ADC7 CTU Total timer I/O9 eMIOS 10 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 19 ch 33 ch 27 ch 33 ch 27 ch 33 ch
19 ch 64 ch 64 ch, 16-bit 10 8 6 Yes Yes No Yes No 1 Yes No Yes
SCI (LINFlexD) SPI (DSPI) CAN (FlexCAN)10 FlexRay STCU
11
Ethernet I2C
Table 1. MPC5646C family comparison1 (continued)
Feature Package 32 kHz oscillator (SXOSC) GPIO
12
Freescale Semiconductor
MPC5644B
MPC5644C 256 BGA
MPC5645B
MPC5645C 256 BGA
MPC5646B
MPC5646C 256 BGA
176 208 176 208 LQFP LQFP LQFP LQFP
176 208 176 208 LQFP LQFP LQFP LQFP Yes
176 208 176 208 LQFP LQFP LQFP LQFP
147
177
147
177
199 Nexus 3+
147
177
147
177
199 Nexus 3+
147
177
147
177
199 Nexus 3+
Debug Cryptographic Services Engine (CSE) MPC5646C Microcontroller Data Sheet, Rev. 3
1 2
JTAG
JTAG Optional
JTAG
Preliminary—Subject to Change Without Notice
5
Feature set dependent on selected peripheral multiplexing; table shows example. Based on 125 C ambient operating temperature and subject to full device characterisation. 3 The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system frequency. There is a configurable e200z0 system clock divider for this purpose. 4 DMAMUX also included that allows for software selection of 32 out of a possible 57 sources. 5 Not shared with 12-bit ADC, but possibly shared with other alternate functions. 6 There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels. 7 16x precision channels (ANP) and 3x standard (ANS). 8 Not shared with 10-bit ADC, but possibly shared with other alternate functions. 9 As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference manual for information on the channel configuration and functions. 10 CAN Sampler also included that allows ID of CAN message to be captured when in low power mode. 11 STCU controls MBIST activation and reporting. 12 Estimated I/O count for proposed packages based on multiplexing with peripherals.
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Block diagram
FEC JTAGC CSE Nexus 3+ e200z0h FlexRay
Instructions (Master) Data (Master) Instructions (Master) Data (Master)
Figure 1 shows the detailed block diagram of the MPC5646C.
64-bit 8 x 5 crossbar switch
JTAG Port Nexus Port Nexus NMI0 Voltage regulator NMI1 SRAM 2 128 KB Code Flash Data Flash 64 KB 2 1.5 MB
e200z4d Nexus 3+
MPU
2 SRAM controller
Flash memory controller
(Slave) (Slave)
NMI0 Interrupt requests from peripheral blocks
(Slave) MPU registers eDMA ( Master ) 8 DMAMUX CAN Sampler
NMI1
INTC Clocks FMPLL CMU
STCU
16 x Semaphores
RTC/API 4 STM
SWT
ECSM
PIT RTI
MC_RGM MC_CGM MC_ME MC_PCU
BAM
SSCM
WKPU
Peripheral Bridge
Interrupt Request
SIUL Reset Control External Interrupt Request IMUX GPIO & Pad Control
10 ch(1) 1 12-bit ADC
27 ch or 33 ch(2) 1 10-bit ADC
CTU
2 32 ch eMIOS
10 LINFlexD
8 DSPI
I2C
6 FlexCAN
(3)
I/O
(3) JTAGC LINFlexD MC_ME MC_CGM MC_PCU MC_RGM MPU Nexus NMI PIT_RTI RTC/API SIUL SRAM SSCM STM SWT STCU WKPU JTAG controller Local Interconnect Network Flexible with DMA support Mode Entry Module Clock Generation Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface Non-Maskable Interrupt Periodic Interrupt Timer with Real-Time Interrupt Real-Time Clock/ Autonomous Periodic Interrupt System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Self Test Control Unit Wakeup Unit
Legend:
ADC BAM CSE CAN CMU CTU DMAMUX DSPI eDMA FlexCAN FEC eMIOS ECSM FMPLL FlexRay I2C IMUX INTC
Analog-to-Digital Converter Boot Assist Module Cryptographic Services Engine Controller Area Network (FlexCAN) Clock Monitor Unit Cross Triggering Unit DMA Channel Multiplexer Deserial Serial Peripheral Interface enhanced Direct Memory Access Controller Area Network controller modules Fast Ethenet Controller Enhanced Modular Input Output System Error Correction Status Module Frequency-Modulated Phase-Locked Loop FlexRay Communication Controller Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller
Notes:
1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table. 2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table. 3) 16 x precision channels (ANP) are mapped on input only I/O cells.
Figure 1. MPC5646C block diagram
MPC5646C Microcontroller Data Sheet, Rev. 3 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 2 summarizes the functions of the blocks present on the MPC5646C. Table 2. MPC5646C series block summary
Block Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) Clock monitor unit (CMU) Cross triggering unit (CTU) Cryptographic Security Engine (CSE) Crossbar (XBAR) switch A block of read-only memory containing VLE code which is executed according to the boot mode of the device Monitors clock source (internal and external) integrity Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Supports the encoding and decoding of any kind of data Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width Allows to route DMA sources (called slots) to DMA channels
DMA Channel Multiplexer (DMAMUX)
Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via “n” programmable channels. Enhanced modular input output system (eMIOS) Flash memory Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Generates high-speed system clocks and supports programmable frequency modulation
FlexRay (FlexRay communication Provides high-speed distributed control for advanced automotive applications controller) Fast Ethernet Controller (FEC) Internal multiplexer (IMUX) SIUL subblock Ethernet Media Access Controller (MAC) designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) JTAG controller Provides priority-based preemptive scheduling of interrupt requests for both e200z0h and e200z4d cores Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7
Table 2. MPC5646C series block summary (continued)
Block LinFlexD (Local Interconnect Network Flexible with DMA support) Memory protection unit (MPU) Clock generation module (MC_CGM) Power control unit (MC_PCU) Function Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides hardware access control for all memory references generated in a device Provides logic and control required for the generation of system and peripheral clocks Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Centralizes reset sources and manages the device reset sequence of the device Provides a mechanism for controlling the device operational mode and modetransition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Handles external events that must produce an immediate response, such as power down detection Provides real-time development capabilities for e200z0h and e200z4d core processor
Reset generation module (MC_RGM) Mode entry module (MC_ME)
Non-Maskable Interrupt (NMI) Nexus Development Interface (NDI)
Periodic interrupt timer/ Real Time Produces periodic interrupts and triggers Interrupt Timer (PIT_RTI) Real-time counter (RTC/API) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode). Supports autonomous periodic interrupt (API) function to generate a periodic wakeup request to exit a low power mode or an interrupt request Provides storage for program code, constants, and variables
Static random-access memory (SRAM)
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration System status and configuration module (SSCM) System timer module (STM) Semaphores Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable Provides a set of output compare events to support AutoSAR and operating system tasks Provides the hardware support needed in multi-core systems for sharing resources and provides a simple mechanism to achieve lock/unlock operations via a single write access. Supports external sources that can generate interrupts or wakeup events, of which can cause non-maskable interrupt requests or wakeup events.
Wake Unit (WKPU)
MPC5646C Microcontroller Data Sheet, Rev. 3 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor
3
Package pinouts and signal descriptions
The available LQFP pinouts and the MAPBGA ballmaps are provided in the following figures. For functional port pin description, see Table 4.
PB[2] PC[8] PC[13] PC[12] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV_A VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] PB[3] PC[9] PC[14] PC[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] PI[6] PI[7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PEp[10] A[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VRC_CTRL PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176 LQFP Top view
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
PA[11] PA[10]
PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PI[13] PI[12] PI[11] VDD_LV VSS_LV PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0
NOTE 1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2)Availability of port pin alternate functions depends on product selection.
Freescale Semiconductor
PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4]
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Figure 2. 176-pin LQFP configuration
MPC5646C Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice 9
NOTE 1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2) Availability of port pin alternate functions depends on product selection.
10
PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PJ[12] PJ[11] PA[4] PK[0] PJ[15] PJ[14] PJ[13] PA[13] PJ[10] PJ[9] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV_A PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PJ[3] PJ[2] PJ[1] PJ[0] PI[15] PI[14] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] VDD_HV_A VSS_HV PD[8] PB[4]
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
PB[3] PC[9] PC[14] PC[15] PJ[4] VDD_HV_A VSS_HV PH[15] PH[13] PH[14] P[I6] P[I7] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV_A VSS_HV RESET VSS_LV VDD_LV VRC_CTRL PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PK[1] PK[2] PK[3] PK[4] PK[5] PK[6] PK[7] PK[8] PF[9] PF[8] PF[12] PC[6]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
PB[2] PC[8] PC[13] PC[12] PL[0] PK[15] PK[14] PK[13] PK[12] PK[11] PK[10] PK[9] PI[0] PI[1] PI[2] PI[3] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV_A VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PI[4] PI[5] PH[12] PH[11] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12]
PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV_B VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13]
PA[3]
208 LQFP
Top view
PI[13] PI[12] PI[11] PI[10] VDD_LV VSS_LV PI[9] PI[8] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] VDD_HV_A VSS_HV PD[12] VDD_HV_ADC1 VSS_HV_ADC1 PB[11] PD[11] PD[10] PD[9] PJ[5] PJ[6] PJ[7] PJ[8] PB[7] PB[6] PB[5] VDD_HV_ADC0 VSS_HV_ADC0
Figure 3. 208-pin LQFP configuration
MPC5646C Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PC[15]
PB[2]
PC[13]
PI[1]
PE[7]
PH[8]
PE[2]
PE[4]
PC[4]
PE[3]
PH[9]
PI[4]
PH[11]
PE[14]
PA[10]
PG[11]
A
B
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
B
PH[14]
C
VDD_HV _A
PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV
VDD_HV _A
PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
C
D
PG[5]
PI[6]
PJ[4]
PB[3]
PK[15]
PI[2]
PH[4]
VDD_LV
PC[1]
PH[10]
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
D
E
PG[3]
PI[7]
PH[15]
PG[2]
PG[0]
PG[1]
PH[0]
VDD_HV _A PG[13]
E
F
PA[2]
PG[4]
PA[1]
PE[1]
PH[1]
PH[3]
PG[12]
F
G
PE[8]
PE[0]
PE[10]
PA[0]
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VDD_HV _B VDD_HV _A PD[15]
PI[13]
PI[12]
PA[3]
G
H
PE[9]
VDD_HV _A VRC_CT RL VSS_LV
PE[11]
PK[1]
VSS_LV
VSS_HV
VSS_HV
VSS_HV
VDD_LV
VSS_LV
PI[11]
H
J
VSS_HV
VDD_LV
PG[9]
VSS_LV
VSS_LV
VSS_HV
VSS_HV
PI[8]
PI[9]
PI[10]
J
K
RESET
PG[8]
PC[11]
VSS_LV
VSS_LV
VSS_LV
VDD_LV
PD[14]
PD[13]
PB[14]
PB[15]
K
L
PC[10]
PG[7]
PB[0]
PK[2]
PD[12]
PB[12]
PB[13]
VDD_HV _ADC1 VSS_HV _ADC1 PD[9]
L
M
PG[6]
PB[1]
PK[4]
PF[9]
PB[11]
PD[10]
PD[11]
M
N
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13]
VDD_HV _A PA[12]
PB[10]
PF[6]
VDD_HV _A PF[7]
PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
N
P
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PF[0]
PF[5]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
P
R
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6]
VDD_HV _ADC0 VSS_HV _ADC0
PB[7]
R
T
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL
VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5]
PB[4]
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2) Availability of port pin alternate functions depends on product selection.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11
1
PC[15]
2
PB[2]
3
PC[13]
4
PI[1]
5
PE[7]
6
PH[8]
7
PE[2]
8
PE[4]
9
PC[4]
10
PE[3]
11
PH[9]
12
PI[4]
13
PH[11]
14
PE[14]
15
PA[10]
16
PG[11]
A
A
B
PH[13]
PC[14]
PC[8]
PC[12]
PI[3]
PE[6]
PH[5]
PE[5]
PC[5]
PC[0]
PC[2]
PH[12]
PG[10]
PA[11]
PA[9]
PA[8]
B
C
PH[14]
VDD_HV_ A PI[6]
PC[9]
PL[0]
PI[0]
PH[7]
PH[6]
VSS_LV
VDD_HV_ A PC[1]
PA[5]
PC[3]
PE[15]
PG[14]
PE[12]
PA[7]
PE[13]
C
D
PG[5]
PJ[4]
PB[3]
PK[15]
PI[2]
PH[4]
VDD_LV
PH[10]
PA[6]
PI[5]
PG[15]
PF[14]
PF[15]
PH[2]
D
E
PG[3]
PI[7]
PH[15]
PG[2]
VDD_LV
VSS_LV
PK[10]
PK[9]
PM[1]
PM[0]
PL[15]
PL[14]
PG[0]
PG[1]
PH[0]
VDD_HV_ A PG[13]
E
F
PA[2]
PG[4]
PA[1]
PE[1]
PL[2]
PM[6]
PL[1]
PK[11]
PM[5]
PL[13]
PL[12]
PM[2]
PH[1]
PH[3]
PG[12]
F
G
PE[8]
PE[0]
PE[10]
PA[0]
PL[3]
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[12]
VDD_HV_ B VDD_HV_ A PD[15]
PI[13]
PI[12]
PA[3]
G
H
PE[9]
VDD_HV_ A VRC_CTR L VSS_LV
PE[11]
PK[1]
PL[4]
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
VSS_HV
PK[13]
VDD_LV
VSS_LV
PI[11]
H
J
VSS_HV
VDD_LV
PG[9]
PL[5]
VSS_LV
VSS_LV
VSS_LV
VSS_HV
VSS_HV
VSS_HV
PK[14]
PI[8]
PI[9]
PI[10]
J
K
RESET
PG[8]
PC[11]
PL[6]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[3]
PD[14]
PD[13]
PB[14]
PB[15]
K
L
PC[10]
PG[7]
PB[0]
PK[2]
PL[7]
VSS_LV
VSS_LV
VSS_LV
VSS_LV
VDD_LV
VDD_LV
PM[4]
PD[12]
PB[12]
PB[13]
VDD_HV_ ADC1 VSS_HV_ ADC1 PD[9]
L
M
PG[6]
PB[1]
PK[4]
PF[9]
PK[5]
PK[6]
PK[7]
PK[8]
PL[8]
PL[9]
PL[10]
PL[11]
PB[11]
PD[10]
PD[11]
M
N
PK[3]
PF[8]
PC[6]
PC[7]
PJ[13]
VDD_HV_ A PA[12]
PB[10]
PF[6]
VDD_HV_ A PF[7]
PJ[1]
PD[2]
PJ[5]
PB[5]
PB[6]
PJ[6]
N
P
PF[12]
PF[10]
PF[13]
PA[14]
PJ[9]
PF[0]
PF[5]
PJ[3]
PI[15]
PD[4]
PD[7]
PD[8]
PJ[8]
PJ[7]
P
R
PF[11]
PA[15]
PJ[11]
PJ[15]
PA[13]
PF[2]
PF[3]
PF[4]
VDD_LV
PJ[2]
PJ[0]
PD[0]
PD[3]
PD[6]
VDD_HV_ ADC0 VSS_HV_ ADC0
PB[7]
R
T
PJ[12]
PA[4]
PK[0]
PJ[14]
PJ[10]
PF[1]
XTAL
EXTAL
VSS_LV
PB[9]
PB[8]
PI[14]
PD[1]
PD[5]
PB[4]
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3]. 2)Availability of port pin alternate functions depends on product selection.
Figure 4. 256-pin BGA configuration
3.1
Pad types
S = Slow1 M = Medium1, 2
In the device the following types of pads are available for system pins and functional port pins:
1. See the I/O pad electrical characteristics in the device data sheet for details. 2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by default. Only exception is PC[1] which is in medium configuration by default (refer to PCR.SRC in the reference manual, Pad Configuration Registers (PCR0—PCR198)). MPC5646C Microcontroller Data Sheet, Rev. 3 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor
F = Fast1, 2 I = Input only with analog feature1 A = Analog
3.2
System pins
Table 3. System pin descriptions
Pin number 176 LQFP 208 LQFP I/O direction Pad type RESET config. 256 MAPBGA K1 T8 T7 G4 256 MAPBGA
The system pins are listed in Table 3.
Port pin
Function
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter.
I/O
M
Input, weak pull-up only after PHASE2 —
29
29
EXTAL
Analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. Analog input for the clock generator when the oscillator is in bypass mode. Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used.
I/O
A1
58
74
XTAL
I
A1
—
56
72
1
For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range voltage.
3.3
Functional ports
Table 4. Functional port pin descriptions
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP 24 Port pin RESET config. Tristate
The functional port pins are listed in Table 4.
PCR
Function
PA[0]
PCR[0]
AF0 AF1 AF2 AF3 — —
GPIO[0] E0UC[0] CLKOUT E0UC[13] WKPU[19] CAN1RX
SIUL eMIOS_0 MC_CGM eMIOS_0 WKPU FlexCAN_1
I/O I/O O I/O I I
M/S
24
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA F3 F1 G16 T2 C10 D11 C15 RESET config. Tristate
PCR
Function
PA[1]
PCR[1]
AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — —
GPIO[1] E0UC[1] — — WKPU[2] CAN3RX NMI[0]3 GPIO[2] E0UC[2] — MA[2] WKPU[3] NMI[1]3 GPIO[3] E0UC[3] LIN5TX CS4_1 RX_ER_CLK EIRQ[0] ADC1_S[0] GPIO[4] E0UC[4] — CS0_1 LIN5RX WKPU[9] GPIO[5] E0UC[5] LIN4TX GPIO[6] E0UC[6] — CS1_1 LIN4RX EIRQ[1] GPIO[7] E0UC[7] LIN3TX — RXD[2] EIRQ[2] ADC1_S[1]
SIUL eMIOS_0 — — WKPU FlexCAN_3 WKPU SIUL eMIOS_0 — ADC_0 WKPU WKPU SIUL eMIOS_0 LINFlexD_5 DSPI_1 FEC SIUL ADC_1 SIUL eMIOS_0 — DSPI_1 LINFlexD_5 WKPU SIUL eMIOS_0 LINFlexD_4 SIUL eMIOS_0 — DSPI_1 LINFlexD_4 SIUL SIUL eMIOS_0 LINFlexD_3 — FEC SIUL ADC_1
I/O I/O — — I I I I/O I/O — O I I I/O I/O O O I I I I/O I/O — I/O I I I/O I/O O I/O I/O — O I I I/O I/O O — I I I
S
19
19
PA[2]
PCR[2]
S
Tristate
17
17
PA[3]
PCR[3]
M/S
Tristate
114
138
PA[4]
PCR[4]
S
Tristate
51
61
PA[5]
PCR[5]
M/S
Tristate
146
170
PA[6]
PCR[6]
S
Tristate
147
171
PA[7]
PCR[7]
M/S
Tristate
128
152
MPC5646C Microcontroller Data Sheet, Rev. 3 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA B16 B15 A15 B14 P6 R5 P4 RESET config. Input, weak pull-up
PCR
Function
PA[8]
PCR[8]
AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 —
GPIO[8] E0UC[8] E0UC[14] — RXD[1] EIRQ[3] ABS[0] LIN3RX GPIO[9] E0UC[9] — CS2_1 RXD[0] FAB GPIO[10] E0UC[10] SDA LIN2TX COL ADC1_S[2] SIN_1 GPIO[11] E0UC[11] SCL — RX_ER EIRQ[16] LIN2RX ADC1_S[3] GPIO[12] — E0UC[28] CS3_1 EIRQ[17] SIN_0 GPIO[13] SOUT_0 E0UC[29] — GPIO[14] SCK_0 CS0_0 E0UC[0] EIRQ[4]
SIUL eMIOS_0 eMIOS_0 — FEC SIUL MC_RGM LINFlexD_3 SIUL eMIOS_0 — DSPI1 FEC MC_RGM SIUL eMIOS_0 I2C LINFlexD_2 FEC ADC_1 DSPI_1 SIUL eMIOS_0 I2C — FEC SIUL LINFlexD_2 ADC_1 SIUL — eMIOS_0 DSPI1 SIUL DSPI_0 SIUL DSPI_0 eMIOS_0 — SIUL DSPI_0 DSPI_0 eMIOS_0 SIUL
I/O I/O I/O — I I I I I/O I/O — O I I I/O I/O I/O O I I I I/O I/O I/O — I I I I I/O — I/O O I I I/O O I/O — I/O I/O I/O I/O I
M/S
129
153
PA[9]
PCR[9]
M/S
Pulldown
130
154
PA[10]
PCR[10]
M/S
Tristate
131
155
PA[11]
PCR[11]
M/S
Tristate
132
156
PA[12]
PCR[12]
S
Tristate
53
69
PA[13]
PCR[13]
M/S
Tristate
52
66
PA[14]
PCR[14]
M/S
Tristate
50
58
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA R2 L3 M2 A2 D4 T16 N13 N14 RESET config. Tristate
PCR
Function
PA[15]
PCR[15]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 — — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — —
GPIO[15] CS0_0 SCK_0 E0UC[1] WKPU[10] GPIO[16] CAN0TX E0UC[30] LIN0TX GPIO[17] — E0UC[31] LIN0RX WKPU[4] CAN0RX GPIO[18] LIN0TX SDA E0UC[30] GPIO[19] E0UC[31] SCL — WKPU[11] LIN0RX GPI[20] — — — ADC0_P[0] ADC1_P[0] GPI[21] — — — ADC0_P[1] ADC1_P[1] GPI[22] — — — ADC0_P[2] ADC1_P[2]
SIUL DSPI_0 DSPI_0 eMIOS_0 WKPU SIUL FlexCAN_0 eMIOS_0 LINFlexD_0 SIUL — eMIOS_0 LINFlexD_0 WKPU FlexCAN_0 SIUL LINFlexD_0 I2C eMIOS_0 SIUL eMIOS_0 I2C — WKPU LINFlexD_0 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1
I/O I/O I/O I/O I I/O O I/O I I/O — I/O I I I I/O O I/O I/O I/O I/O I/O — I I I — — — I I I — — — I I I — — — I I
M/S
48
56
PB[0]
PCR[16]
M/S
Tristate
39
39
PB[1]
PCR[17]
S
Tristate
40
40
PB[2]
PCR[18]
M/S
Tristate
176
208
PB[3]
PCR[19]
S
Tristate
1
1
PB[4]
PCR[20]
I
Tristate
88
104
PB[5]
PCR[21]
I
Tristate
91
107
PB[6]
PCR[22]
I
Tristate
92
108
MPC5646C Microcontroller Data Sheet, Rev. 3 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA R16 T11 T10 N7 M13 L14 L15 RESET config. Tristate
PCR
Function
PB[7]
PCR[23]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPI[23] — — — ADC0_P[3] ADC1_P[3] GPI[24] — — — ADC0_S[0] ADC1_S[4] WKPU[25] OSC32k_XTAL4 GPI[25] — — — ADC0_S[1] ADC1_S[5] WKPU[26] OSC32k_EXTAL4 GPIO[26] SOUT_1 CAN3TX — ADC0_S[2] ADC1_S[6] WKPU[8] GPIO[27] E0UC[3] — CS0_0 ADC0_S[3] GPIO[28] E0UC[4] — CS1_0 ADC0_X[0] GPIO[29] E0UC[5] — CS2_0 ADC0_X[1]
SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 WKPU SXOSC SIUL — — — ADC_0 ADC_1 WKPU SXOSC SIUL DSPI_1 FlexCAN_3 — ADC_0 ADC_1 WKPU SIUL eMIOS_0 — DSPI_0 ADC_0 SIUL eMIOS_0 — DSPI_0 ADC_0 SIUL eMIOS_0 — DSPI_0 ADC_0
I — — — I I I — — — I I I I I — — — I I I I I/O O — — I I I I/O I/O — I/O I I/O I/O — O I I/O I/O — O I
I
93
109
PB[8]
PCR[24]
I
—
61
77
PB[9]5
PCR[25]
I
—
60
76
PB[10]
PCR[26]
S
Tristate
62
78
PB[11]
PCR[27]
S
Tristate
97
117
PB[12]
PCR[28]
S
Tristate
101
123
PB[13]
PCR[29]
S
Tristate
103
125
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA K15 K16 B10 D9 B11 C11 A9 B9 RESET config. Tristate
PCR
Function
PB[14]
PCR[30]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 ALT4 — — — AF0 AF1 AF2 AF3 ALT4 —
GPIO[30] E0UC[6] — CS3_0 ADC0_X[2] GPIO[31] E0UC[7] — CS4_0 ADC0_X[3] GPIO[32] — TDI — GPIO[33] — TDO — GPIO[34] SCK_1 CAN4TX — EIRQ[5] GPIO[35] CS0_1 MA[0] — CAN1RX CAN4RX EIRQ[6] GPIO[36] E1UC[31] — FR_B_TX_EN SIN_1 CAN3RX EIRQ[18] GPIO[37] SOUT_1 CAN3TX — FR_A_TX EIRQ[7]
SIUL eMIOS_0 — DSPI_0 ADC_0 SIUL eMIOS_0 — DSPI_0 ADC_0 SIUL — JTAGC — SIUL — JTAGC — SIUL DSPI_1 FlexCAN_4 — SIUL SIUL DSPI_1 ADC_0 — FlexCAN_1 FlexCAN_4 SIUL SIUL eMIOS_1 — Flexray DSPI_1 FlexCAN_3 SIUL SIUL DSPI_1 FlexCAN_3 — Flexray SIUL
I/O I/O — O I I/O I/O — O I I/O — I — I/O — O — I/O I/O O — I I/O I/O O I I I I/O I/O — O I I I I/O O O — O I
S
105
127
PB[15]
PCR[31]
S
Tristate
107
129
PC[0]6
PCR[32]
M/S
Input, weak pull-up Tristate
154
178
PC[1]6
PCR[33]
F/M
149
173
PC[2]
PCR[34]
M/S
Tristate
145
169
PC[3]
PCR[35]
S
Tristate
144
168
PC[4]
PCR[36]
M/S
Tristate
159
183
PC[5]
PCR[37]
M/S
Tristate
158
182
MPC5646C Microcontroller Data Sheet, Rev. 3 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA N3 N4 B3 C3 L1 K4 B4 A3 RESET config. Tristate
PCR
Function
PC[6]
PCR[38]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 ALT4 — — AF0 AF1 AF2 AF3 ALT4
GPIO[38] LIN1TX E1UC[28] — GPIO[39] — E1UC[29] — LIN1RX WKPU[12] GPIO[40] LIN2TX E0UC[3] — GPIO[41] — E0UC[7] — LIN2RX WKPU[13] GPIO[42] CAN1TX CAN4TX MA[1] GPIO[43] — — MA[2] CAN1RX CAN4RX WKPU[5] GPIO[44] E0UC[12] — — FR_DBG[0] SIN_2 EIRQ[19] GPIO[45] E0UC[13] SOUT_2 — FR_DBG[1]
SIUL LINFlexD_1 eMIOS_1 — SIUL — eMIOS_1 — LINFlexD_1 WKPU SIUL LINFlexD_2 eMIOS_0 — SIUL — eMIOS_0 — LINFlexD_2 WKPU SIUL FlexCAN_1 FlexCAN_4 ADC_0 SIUL — — ADC_0 FlexCAN_1 FlexCAN_4 WKPU SIUL eMIOS_0 — — Flexray DSPI_2 SIUL SIUL eMIOS_0 DSPI_2 — Flexray
I/O O I/O — I/O — I/O — I I I/O O I/O — I/O — I/O — I I I/O O O O I/O — — O I I I I/O I/O — — O I I I/O I/O O — O
S
44
52
PC[7]
PCR[39]
S
Tristate
45
53
PC[8]
PCR[40]
S
Tristate
175
207
PC[9]
PCR[41]
S
Tristate
2
2
PC[10]
PCR[42]
M/S
Tristate
36
36
PC[11]
PCR[43]
S
Tristate
35
35
PC[12]
PCR[44]
M/S
Tristate
173
205
PC[13]
PCR[45]
M/S
Tristate
174
206
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA B2 A1 R12 T13 N11 R13 P12 RESET config. Tristate
PCR
Function
PC[14]
PCR[46]
AF0 AF1 AF2 AF3 ALT4 — AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — —
GPIO[46] E0UC[14] SCK_2 — FR_DBG[2] EIRQ[8] GPIO[47] E0UC[15] CS0_2 — FR_DBG[3] EIRQ[20] GPI[48] — — — ADC0_P[4] ADC1_P[4] WKPU[27] GPI[49] — — — ADC0_P[5] ADC1_P[5] WKPU[28] GPI[50] — — — ADC0_P[6] ADC1_P[6] GPI[51] — — — ADC0_P[7] ADC1_P[7] GPI[52] — — — ADC0_P[8] ADC1_P[8]
SIUL eMIOS_0 DSPI_2 — Flexray SIUL SIUL eMIOS_0 DSPI_2 — Flexray SIUL SIUL — — — ADC_0 ADC_1 WKPU SIUL — — — ADC_0 ADC_1 WKPU SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1
I/O I/O I/O — O I I/O I/O I/O — O I I — — — I I I I — — — I I I I — — — I I I — — — I I I — — — I I
M/S
3
3
PC[15]
PCR[47]
M/S
Tristate
4
4
PD[0]
PCR[48]
I
Tristate
77
93
PD[1]
PCR[49]
I
Tristate
78
94
PD[2]
PCR[50]
I
Tristate
79
95
PD[3]
PCR[51]
I
Tristate
80
96
PD[4]
PCR[52]
I
Tristate
81
97
MPC5646C Microcontroller Data Sheet, Rev. 3 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA T14 R14 P13 P14 N16 M14 M15 RESET config. Tristate
PCR
Function
PD[5]
PCR[53]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — —
GPI[53] — — — ADC0_P[9] ADC1_P[9] GPI[54] — — — ADC0_P[10] ADC1_P[10] GPI[55] — — — ADC0_P[11] ADC1_P[11] GPI[56] — — — ADC0_P[12] ADC1_P[12] GPI[57] — — — ADC0_P[13] ADC1_P[13] GPI[58] — — — ADC0_P[14] ADC1_P[14] GPI[59] — — — ADC0_P[15] ADC1_P[15]
SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1 SIUL — — — ADC_0 ADC_1
I — — — I I I — — — I I I — — — I I I — — — I I I — — — I I I — — — I I I — — — I I
I
82
98
PD[6]
PCR[54]
I
Tristate
83
99
PD[7]
PCR[55]
I
Tristate
84
100
PD[8]
PCR[56]
I
Tristate
87
103
PD[9]
PCR[57]
I
Tristate
94
114
PD[10]
PCR[58]
I
Tristate
95
115
PD[11]
PCR[59]
I
Tristate
96
116
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA L13 K14 K13 J13 G2 F4 A7 RESET config. Tristate
PCR
Function
PD[12]
PCR[60]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 ALT4 — AF0 AF1 AF2 AF3 ALT4 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 ALT4 — —
GPIO[60] CS5_0 E0UC[24] — ADC0_S[4] GPIO[61] CS0_1 E0UC[25] — ADC0_S[5] GPIO[62] CS1_1 E0UC[26] — FR_DBG[0] ADC0_S[6] GPIO[63] CS2_1 E0UC[27] — FR_DBG[1] ADC0_S[7] GPIO[64] E0UC[16] — — CAN5RX WKPU[6] GPIO[65] E0UC[17] CAN5TX — GPIO[66] E0UC[18] — — FR_A_TX_EN SIN_1 EIRQ[21]
SIUL DSPI_0 eMIOS_0 — ADC_0 SIUL DSPI_1 eMIOS_0 — ADC_0 SIUL DSPI_1 eMIOS_0 — Flexray ADC_0 SIUL DSPI_1 eMIOS_0 — Flexray ADC_0 SIUL eMIOS_0 — — FlexCAN_5 WKPU SIUL eMIOS_0 FlexCAN_5 — SIUL eMIOS_0 — — Flexray DSPI_1 SIUL
I/O O I/O — I I/O I/O I/O — I I/O O I/O — O I I/O O I/O — O I I/O I/O — — I I I/O I/O O — I/O I/O — — O I I
S
100
120
PD[13]
PCR[61]
S
Tristate
102
124
PD[14]
PCR[62]
S
Tristate
104
126
PD[15]
PCR[63]
S
Tristate
106
128
PE[0]
PCR[64]
S
Tristate
18
18
PE[1]
PCR[65]
M/S
Tristate
20
20
PE[2]
PCR[66]
M/S
Tristate
156
180
MPC5646C Microcontroller Data Sheet, Rev. 3 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA A10 A8 B8 B6 A5 G1 H1 G3 RESET config. Tristate
PCR
Function
PE[3]
PCR[67]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 ALT4 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3 —
GPIO[67] E0UC[19] SOUT_1 — FR_A_RX WKPU[29] GPIO[68] E0UC[20] SCK_1 — FR_B_TX EIRQ[9] GPIO[69] E0UC[21] CS0_1 MA[2] FR_B_RX WKPU[30] GPIO[70] E0UC[22] CS3_0 MA[1] EIRQ[22] GPIO[71] E0UC[23] CS2_0 MA[0] EIRQ[23] GPIO[72] CAN2TX E0UC[22] CAN3TX GPIO[73] — E0UC[23] — WKPU[7] CAN2RX CAN3RX GPIO[74] LIN3TX CS3_1 E1UC[30] EIRQ[10]
SIUL eMIOS_0 DSPI_1 — Flexray WKPU SIUL eMIOS_0 DSPI_1 — Flexray SIUL SIUL eMIOS_0 DSPI_1 ADC_0 Flexray WKPU SIUL eMIOS_0 DSPI_0 ADC_0 SIUL SIUL eMIOS_0 DSPI_0 ADC_0 SIUL SIUL FlexCAN_2 eMIOS_0 FlexCAN_3 SIUL — eMIOS_0 — WKPU FlexCAN_2 FlexCAN_3 SIUL LINFlexD_3 DSPI_1 eMIOS_1 SIUL
I/O I/O O — I I I/O I/O I/O — O I I/O I/O I/O O I I I/O I/O O O I I/O I/O O O I I/O O I/O O I/O — I/O — I I I I/O O O I/O I
M/S
157
181
PE[4]
PCR[68]
M/S
Tristate
160
184
PE[5]
PCR[69]
M/S
Tristate
161
185
PE[6]
PCR[70]
M/S
Tristate
167
191
PE[7]
PCR[71]
M/S
Tristate
168
192
PE[8]
PCR[72]
M/S
Tristate
21
21
PE[9]
PCR[73]
S
Tristate
22
22
PE[10]
PCR[74]
S
Tristate
23
23
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA H3 C14 C16 A14 C12 P7 T6 R6 RESET config. Tristate
PCR
Function
PE[11]
PCR[75]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[75] E0UC[24] CS4_1 — LIN3RX WKPU[14] GPIO[76] — E1UC[19] — CRS SIN_2 EIRQ[11] ADC1_S[7] GPIO[77] SOUT_2 E1UC[20] — RXD[3] GPIO[78] SCK_2 E1UC[21] — EIRQ[12] GPIO[79] CS0_2 E1UC[22] SCK_6 GPIO[80] E0UC[10] CS3_1 — ADC0_S[8] GPIO[81] E0UC[11] CS4_1 — ADC0_S[9] GPIO[82] E0UC[12] CS0_2 — ADC0_S[10]
SIUL eMIOS_0 DSPI_1 — LINFlexD_3 WKPU SIUL — eMIOS_1 — FEC DSPI_2 SIUL ADC_1 SIUL DSPI_2 eMIOS_1 — FEC SIUL DSPI_2 eMIOS_1 — SIUL SIUL DSPI_2 eMIOS_1 DSPI_6 SIUL eMIOS_0 DSPI_1 — ADC_0 SIUL eMIOS_0 DSPI_1 — ADC_0 SIUL eMIOS_0 DSPI_2 — ADC_0
I/O I/O O — I I I/O — I/O — I I I I I/O O I/O — I I/O I/O I/O — I I/O I/O I/O I/O I/O I/O O — I I/O I/O O — I I/O I/O I/O — I
S
25
25
PE[12]
PCR[76]
M/S
Tristate
133
157
PE[13]
PCR[77]
M/S
Tristate
127
151
PE[14]
PCR[78]
M/S
Tristate
136
160
PE[15]
PCR[79]
M/S
Tristate
137
161
PF[0]
PCR[80]
S
Tristate
63
79
PF[1]
PCR[81]
S
Tristate
64
80
PF[2]
PCR[82]
S
Tristate
65
81
MPC5646C Microcontroller Data Sheet, Rev. 3 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA R7 R8 P8 N8 P9 N2 M4 P2 RESET config. Tristate
PCR
Function
PF[3]
PCR[83]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — — AF0 AF1 AF2 AF3
GPIO[83] E0UC[13] CS1_2 — ADC0_S[11] GPIO[84] E0UC[14] CS2_2 — ADC0_S[12] GPIO[85] E0UC[22] CS3_2 — ADC0_S[13] GPIO[86] E0UC[23] CS1_1 — ADC0_S[14] GPIO[87] — CS2_1 — ADC0_S[15] GPIO[88] CAN3TX CS4_0 CAN2TX GPIO[89] E1UC[1] CS5_0 — CAN2RX CAN3RX WKPU[22] GPIO[90] CS1_0 LIN4TX E1UC[2]
SIUL eMIOS_0 DSPI_2 — ADC_0 SIUL eMIOS_0 DSPI_2 — ADC_0 SIUL eMIOS_0 DSPI_2 — ADC_0 SIUL eMIOS_0 DSPI_1 — ADC_0 SIUL — DSPI_1 — ADC_0 SIUL FlexCAN_3 DSPI_0 FlexCAN_2 SIUL eMIOS_1 DSPI_0 — FlexCAN_2 FlexCAN_3 WKPU SIUL DSPI_0 LINFlexD_4 eMIOS_1
I/O I/O O — I I/O I/O O — I I/O I/O O — I I/O I/O O — I I/O — O — I I/O O O O I/O I/O O — I I I I/O O O I/O
S
66
82
PF[4]
PCR[84]
S
Tristate
67
83
PF[5]
PCR[85]
S
Tristate
68
84
PF[6]
PCR[86]
S
Tristate
69
85
PF[7]
PCR[87]
S
Tristate
70
86
PF[8]
PCR[88]
M/S
Tristate
42
50
PF[9]
PCR[89]
S
Tristate
41
49
PF[10]
PCR[90]
M/S
Tristate
46
54
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA R1 P1 P3 D14 D15 E13 E14 RESET config. Tristate
PCR
Function
PF[11]
PCR[91]
AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 — — —
GPIO[91] CS2_0 E1UC[3] — LIN4RX WKPU[15] GPIO[92] E1UC[25] LIN5TX — GPIO[93] E1UC[26] — — LIN5RX WKPU[16] GPIO[94] CAN4TX E1UC[27] CAN1TX MDIO GPIO[95] E1UC[4] — — RX_DV CAN1RX CAN4RX EIRQ[13] GPIO[96] CAN5TX E1UC[23] — MDC GPIO[97] — E1UC[24] — TX_CLK CAN5RX EIRQ[14]
SIUL DSPI_0 eMIOS_1 — LINFlexD_4 WKPU SIUL eMIOS_1 LINFlexD_5 — SIUL eMIOS_1 — — LINFlexD_5 WKPU SIUL FlexCAN_4 eMIOS_1 FlexCAN_1 FEC SIUL eMIOS_1 — — FEC FlexCAN_1 FlexCAN_4 SIUL SIUL FlexCAN_5 eMIOS_1 — FEC SIUL — eMIOS_1 — FEC FlexCAN_5 SIUL
I/O O I/O — I I I/O I/O O — I/O I/O — — I I I/O O I/O O I/O I/O I/O — — I I I I I/O O I/O — O I/O — I/O — I I I
S
47
55
PF[12]
PCR[92]
M/S
Tristate
43
51
PF[13]
PCR[93]
S
Tristate
49
57
PF[14]
PCR[94]
M/S
Tristate
126
150
PF[15]
PCR[95]
M/S
Tristate
125
149
PG[0]
PCR[96]
F
Tristate
122
146
PG[1]
PCR[97]
M
Tristate
121
145
MPC5646C Microcontroller Data Sheet, Rev. 3 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA E4 E1 F2 D1 M1 L2 K3 J4 RESET config. Tristate
PCR
Function
PG[2]
PCR[98]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — —
GPIO[98] E1UC[11] SOUT_3 — GPIO[99] E1UC[12] CS0_3 — WKPU[17] GPIO[100] E1UC[13] SCK_3 — GPIO[101] E1UC[14] — — WKPU[18] SIN_3 GPIO[102] E1UC[15] LIN6TX — GPIO[103] E1UC[16] E1UC[30] — LIN6RX WKPU[20] GPIO[104] E1UC[17] LIN7TX CS0_2 EIRQ[15] GPIO[105] E1UC[18] — SCK_2 LIN7RX WKPU[21]
SIUL eMIOS_1 DSPI_3 — SIUL eMIOS_1 DSPI_3 — WKPU SIUL eMIOS_1 DSPI_3 — SIUL eMIOS_1 — — WKPU DSPI_3 SIUL eMIOS_1 LINFlexD_6 — SIUL eMIOS_1 eMIOS_1 — LINFlexD_6 WKPU SIUL eMIOS_1 LINFlexD_7 DSPI_2 SIUL SIUL eMIOS_1 — DSPI_2 LINFlexD_7 WKPU
I/O I/O O — I/O I/O I/O — I I/O I/O I/O — I/O I/O — — I I I/O I/O O — I/O I/O I/O — I I I/O I/O O I/O I I/O I/O — I/O I I
M/S
16
16
PG[3]
PCR[99]
S
Tristate
15
15
PG[4]
PCR[100]
M/S
Tristate
14
14
PG[5]
PCR[101]
S
Tristate
13
13
PG[6]
PCR[102]
M/S
Tristate
38
38
PG[7]
PCR[103]
S
Tristate
37
37
PG[8]
PCR[104]
S
Tristate
34
34
PG[9]
PCR[105]
S
Tristate
33
33
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA B13 A16 F15 F16 C13 D13 E15 F13 RESET config. Tristate
PCR
Function
PG[10]
PCR[106]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 ALT4 — AF0 AF1 AF2 AF3 ALT4
GPIO[106] E0UC[24] E1UC[31] — SIN_4 GPIO[107] E0UC[25] CS0_4 CS0_6 GPIO[108] E0UC[26] SOUT_4 — TXD[2] GPIO[109] E0UC[27] SCK_4 — TXD[3] GPIO[110] E1UC[0] LIN8TX — SIN_6 GPIO[111] E1UC[1] SOUT_6 — LIN8RX GPIO[112] E1UC[2] — — TXD[1] SIN_1 GPIO[113] E1UC[3] SOUT_1 — TXD[0]
SIUL eMIOS_0 eMIOS_1 — DSPI_4 SIUL eMIOS_0 DSPI_4 DSPI_6 SIUL eMIOS_0 DSPI_4 — FEC SIUL eMIOS_0 DSPI_4 — FEC SIUL eMIOS_1 LINFlexD_8 — DSPI_6 SIUL eMIOS_1 DSPI_6 — LINFlexD_8 SIUL eMIOS_1 — — FEC DSPI_1 SIUL eMIOS_1 DSPI_1 — FEC
I/O I/O I/O — I I/O I/O I/O I/O I/O I/O O — O I/O I/O I/O — O I/O I/O O — I I/O I/O O — I I/O I/O — — O I I/O I/O O — O
S
138
162
PG[11]
PCR[107]
M/S
Tristate
139
163
PG[12]
PCR[108]
M/S
Tristate
116
140
PG[13]
PCR[109]
M/S
Tristate
115
139
PG[14]
PCR[110]
S
Tristate
134
158
PG[15]
PCR[111]
M/S
Tristate
135
159
PH[0]
PCR[112]
M/S
Tristate
117
141
PH[1]
PCR[113]
M/S
Tristate
118
142
MPC5646C Microcontroller Data Sheet, Rev. 3 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA D16 F14 D7 B7 C7 C6 A6 A11 D10 RESET config. Tristate
PCR
Function
PH[2]
PCR[114]
AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[114] E1UC[4] SCK_1 — TX_EN GPIO[115] E1UC[5] CS0_1 — TX_ER GPIO[116] E1UC[6] SOUT_7 — GPIO[117] E1UC[7] — — SIN_7 GPIO[118] E1UC[8] SCK_7 MA[2] GPIO[119] E1UC[9] CS3_2 MA[1] CS0_7 GPIO[120] E1UC[10] CS2_2 MA[0] GPIO[121] — — — TCK GPIO[122] — — — TMS
SIUL eMIOS_1 DSPI_1 — FEC SIUL eMIOS_1 DSPI_1 — FEC SIUL eMIOS_1 DSPI_7 — SIUL eMIOS_1 — — DSPI_7 SIUL eMIOS_1 DSPI_7 ADC_0 SIUL eMIOS_1 DSPI_2 ADC_0 DSPI_7 SIUL eMIOS_1 DSPI_2 ADC_0 SIUL — — — JTAGC SIUL — — — JTAGC
I/O I/O I/O — O I/O I/O I/O — O I/O I/O O — I/O I/O — — I I/O I/O I/O O I/O I/O O O I/O I/O I/O O O I/O — — — I I/O — — — I
M/S
119
143
PH[3]
PCR[115]
M/S
Tristate
120
144
PH[4]
PCR[116]
M/S
Tristate
162
186
PH[5]
PCR[117]
S
Tristate
163
187
PH[6]
PCR[118]
M/S
Tristate
164
188
PH[7]
PCR[119]
M/S
Tristate
165
189
PH[8]
PCR[120]
M/S
Tristate
166
190
PH[9]6
PCR[121]
S
Input, weak pull-up
155
179
PH[10]6 PCR[122]
M/S
Input, weak pull-up
148
172
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA A13 B12 B1 C1 E3 C5 A4 D6 B5 RESET config. Tristate
PCR
Function
PH[11]
PCR[123]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — —
GPIO[123] SOUT_3 CS0_4 E1UC[5] GPIO[124] SCK_3 CS1_4 E1UC[25] GPIO[125] SOUT_4 CS0_3 E1UC[26] GPIO[126] SCK_4 CS1_3 E1UC[27] GPIO[127] SOUT_5 — E1UC[17] GPIO[128] E0UC[28] LIN8TX — GPIO[129] E0UC[29] — — WKPU[24] LIN8RX GPIO[130] E0UC[30] LIN9TX — GPIO[131] E0UC[31] — — WKPU[23] LIN9RX
SIUL DSPI_3 DSPI_4 eMIOS_1 SIUL DSPI_3 DSPI_4 eMIOS_1 SIUL DSPI_4 DSPI_3 eMIOS_1 SIUL DSPI_4 DSPI_3 eMIOS_1 SIUL DSPI_5 — eMIOS_1 SIUL eMIOS_0 LINFlexD_8 — SIUL eMIOS_0 — — WKPU LINFlexD_8 SIUL eMIOS_0 LINFlexD_9 — SIUL eMIOS_0 — — WKPU LINFlexD_9
I/O O I/O I/O I/O I/O O I/O I/O O I/O I/O I/O I/O O I/O I/O O — I/O I/O I/O O — I/O I/O — — I I I/O I/O O — I/O I/O — — I I
M/S
140
164
PH[12]
PCR[124]
M/S
Tristate
141
165
PH[13]
PCR[125]
M/S
Tristate
9
9
PH[14]
PCR[126]
M/S
Tristate
10
10
PH[15]
PCR[127]
M/S
Tristate
8
8
PI[0]
PCR[128]
S
Tristate
172
196
PI[1]
PCR[129]
S
Tristate
171
195
PI[2]
PCR[130]
S
Tristate
170
194
PI[3]
PCR[131]
S
Tristate
169
193
MPC5646C Microcontroller Data Sheet, Rev. 3 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA A12 D12 D2 E2 J14 J15 J16 H16 RESET config. Tristate
PCR
Function
PI[4]
PCR[132]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 ALT4 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — —
GPIO[132] E1UC[28] SOUT_4 — GPIO[133] E1UC[29] SCK_4 CS2_5 CS2_6 GPIO[134] E1UC[30] CS0_4 CS0_5 CS0_6 GPIO[135] E1UC[31] CS1_4 CS1_5 CS1_6 GPIO[136] — — — ADC0_S[16] GPIO[137] — — — ADC0_S[17] GPIO[138] — — — ADC0_S[18] GPIO[139] — — — ADC0_S[19] SIN_3
SIUL eMIOS_1 DSPI_4 — SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 SIUL eMIOS_1 DSPI_4 DSPI_5 DSPI_6 SIUL — — — ADC_0 SIUL — — — ADC_0 SIUL — — — ADC_0 SIUL — — — ADC_0 DSPI_3
I/O I/O O — I/O I/O I/O O O I/O I/O I/O I/O I/O I/O I/O O O O I/O — — — I I/O — — — I I/O — — — I I/O — — — I I
M/S
143
167
PI[5]
PCR[133]
M/S
Tristate
142
166
PI[6]
PCR[134]
S
Tristate
11
11
PI[7]
PCR[135]
S
Tristate
12
12
PI[8]
PCR[136]
S
Tristate
108
130
PI[9]
PCR[137]
S
Tristate
—
131
PI[10]
PCR[138]
S
Tristate
—
134
PI[11]
PCR[139]
S
Tristate
111
135
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA G15 G14 T12 P11 R11 N10 R10 P10 RESET config. Tristate
PCR
Function
PI[12]
PCR[140]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[140] CS0_3 CS0_2 — ADC0_S[20] GPIO[141] CS1_3 CS1_2 — ADC0_S[21] GPIO[142] — — — ADC0_S[22] SIN_4 GPIO[143] CS0_4 CS2_2 — ADC0_S[23] GPIO[144] CS1_4 CS3_2 — ADC0_S[24] GPIO[145] — — — ADC0_S[25] SIN_5 GPIO[146] CS0_5 CS0_6 CS0_7 ADC0_S[26] GPIO[147] CS1_5 CS1_6 CS1_7 ADC0_S[27]
SIUL DSPI_3 DSPI_2 — ADC_0 SIUL DSPI_3 DSPI_2 — ADC_0 SIUL — — — ADC_0 DSPI_4 SIUL DSPI_4 DSPI_2 — ADC_0 SIUL DSPI_4 DSPI_2 — ADC_0 SIUL — — —— ADC_0 DSPI_5 SIUL DSPI_5 DSPI_6 DSPI_7 ADC_0 SIUL DSPI_5 DSPI_6 DSPI_7 ADC_0
I/O I/O I/O — I I/O O O — I I/O — — — I I I/O I/O O — I I/O O O — I I/O — — — I I I/O I/O I/O I/O I I/O O O O I
S
112
136
PI[13]
PCR[141]
S
Tristate
113
137
PI[14]
PCR[142]
S
Tristate
76
92
PI[15]
PCR[143]
S
Tristate
75
91
PJ[0]
PCR[144]
S
Tristate
74
90
PJ[1]
PCR[145]
S
Tristate
73
89
PJ[2]
PCR[146]
S
Tristate
72
88
PJ[3]
PCR[147]
S
Tristate
71
87
MPC5646C Microcontroller Data Sheet, Rev. 3 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA D3 N12 N15 P16 P15 P5 T5 R3 RESET config. Tristate
PCR
Function
PJ[4]
PCR[148]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 —
GPIO[148] SCK_5 E1UC[18] — GPIO[149] — — — ADC0_S[28] GPIO[150] — — — ADC0_S[29] GPIO[151] — — — ADC0_S[30] GPIO[152] — — — ADC0_S[31] GPIO[153] — — — ADC1_S[8] GPIO[154] — — — ADC1_S[9] GPIO[155] — — — ADC1_S[10]
SIUL DSPI_5 eMIOS_1 — SIUL — — — ADC_0 SIUL — — — ADC_0 SIUL — — — ADC_0 SIUL — — — ADC_0 SIUL — — — ADC_1 SIUL — — — ADC_1 SIUL — — — ADC_1
I/O I/O I/O — I/O — — — I I/O — — — I I/O — — — I I/O — — — I I/O — — — I I/O — — — I I/O — — — I
M/S
5
5
PJ[5]
PCR[149]
S
Tristate
—
113
PJ[6]
PCR[150]
S
Tristate
—
112
PJ[7]
PCR[151]
S
Tristate
—
111
PJ[8]
PCR[152]
S
Tristate
—
110
PJ[9]
PCR[153]
S
Tristate
—
68
PJ[10]
PCR[154]
S
Tristate
—
67
PJ[11]
PCR[155]
S
Tristate
—
60
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA T1 N5 T4 R4 T3 H4 L4 N1 RESET config. Tristate
PCR
Function
PJ[12]
PCR[156]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 — — — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — —
GPIO[156] — — — ADC1_S[11] GPIO[157] — CS1_7 — CAN4RX ADC1_S[12] CAN1RX WKPU[31] GPIO[158] CAN1TX CAN4TX CS2_7 GPIO[159] — CS1_6 — CAN1RX GPIO[160] CAN1TX CS2_6 — GPIO[161] CS3_6 — — CAN4RX GPIO[162] CAN4TX — — GPIO[163] E1UC[0] — — CAN5RX LIN8RX
SIUL — — — ADC_1 SIUL — DSPI_7 — FlexCAN_4 ADC_1 FlexCAN_1 WKPU SIUL FlexCAN_1 FlexCAN_4 DSPI_7 SIUL — DSPI_6 — FlexCAN_1 SIUL FlexCAN_1 DSPI_6 — SIUL DSPI_6 — — FlexCAN_4 SIUL FlexCAN_4 — — SIUL eMIOS_1 — — FlexCAN_5 LINFlexD_8
I/O — — — I I/O — O — I I I I I/O O O O I/O — O — I I/O O O — I/O O — — I I/O O — — I/O I/O — — I I
S
—
59
PJ[13]
PCR[157]
S
Tristate
—
65
PJ[14]
PCR[158]
M/S
Tristate
—
64
PJ[15]
PCR[159]
M/S
Tristate
—
63
PK[0]
PCR[160]
M/S
Tristate
—
62
PK[1]
PCR[161]
M/S
Tristate
—
41
PK[2]
PCR[162]
M/S
Tristate
—
42
PK[3]
PCR[163]
M/S
Tristate
—
43
MPC5646C Microcontroller Data Sheet, Rev. 3 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA M3 M5 M6 M7 M8 E8 E7 F8 G12 RESET config. Tristate
PCR
Function
PK[4]
PCR[164]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3
GPIO[164] LIN8TX CAN5TX E1UC[1] GPIO[165] — — — CAN2RX LIN2RX GPIO[166] CAN2TX LIN2TX — GPIO[167] — — — CAN3RX LIN3RX GPIO[168] CAN3TX LIN3TX — GPIO[169] — — — SIN_4 GPIO[170] SOUT_4 — — GPIO[171] SCK_4 — — GPIO[172] CS0_4 — —
SIUL LINFlexD_8 FlexCAN_5 eMIOS_1 SIUL — — — FlexCAN_2 LINFlexD_2 SIUL FlexCAN_2 LINFlexD_2 — SIUL — — — FlexCAN_3 LINFlexD_3 SIUL FlexCAN_3 LINFlexD_3 — SIUL — — — DSPI_4 SIUL DSPI_4 — — SIUL DSPI_4 — — SIUL DSPI_4 — —
I/O O O I/O I/O — — — I I I/O O O — I/O — — — I I I/O O O — I/O — — — I I/O O — — I/O I/O — — I/O I/O — —
M/S
—
44
PK[5]
PCR[165]
M/S
Tristate
—
45
PK[6]
PCR[166]
M/S
Tristate
—
46
PK[7]
PCR[167]
M/S
Tristate
—
47
PK[8]
PCR[168]
M/S
Tristate
—
48
PK[9]
PCR[169]
M/S
Tristate
—
197
PK[10]
PCR[170]
M/S
Tristate
—
198
PK[11]
PCR[171]
M/S
Tristate
—
199
PK[12]
PCR[172]
M/S
Tristate
—
200
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA H12 J12 D5 C4 F7 F5 G5 H5 J5 K5 RESET config. Tristate
PCR
Function
PK[13]
PCR[173]
AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3
GPIO[173] CS3_6 CS2_7 SCK_1 CAN3RX GPIO[174] CAN3TX CS3_7 CS0_1 GPIO[175] — — — SIN_1 SIN_7 GPIO[176] SOUT_1 SOUT_7 — GPIO[177] — — — GPIO[178] — MDO08 — GPIO[179] — MDO1 — GPIO[180] — MDO2 — GPIO[181] — MDO3 — GPIO[182] — MDO4 —
SIUL DSPI_6 DSPI_7 DSPI_1 FlexCAN_3 SIUL FlexCAN_3 DSPI_7 DSPI_1 SIUL — — — DSPI_1 DSPI_7 SIUL DSPI_1 DSPI_7 — SIUL — — — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus —
I/O O O I/O I I/O O O I/O I/O — — — I I I/O O O — I/O — — — I/O — O — I/O — O — I/O — O — I/O — O — I/O — O —
M/S
—
201
PK[14]
PCR[174]
M/S
Tristate
—
202
PK[15]
PCR[175]
M/S
Tristate
—
203
PL[0]
PCR[176]
M/S
Tristate
—
204
PL[1]
PCR[177]
M/S
Tristate
—
—
PL[2]
PCR[178]7
M/S
Tristate
—
—
PL[3]
PCR[179]
M/S
Tristate
—
—
PL[4]
PCR[180]
M/S
Tristate
—
—
PL[5]
PCR[181]
M/S
Tristate
—
—
PL[6]
PCR[182]
M/S
Tristate
—
—
MPC5646C Microcontroller Data Sheet, Rev. 3 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA L5 M9 M10 M11 M12 F11 F10 E12 E11 E10 RESET config. Tristate
PCR
Function
PL[7]
PCR[183]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 — AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3
GPIO[183] — MDO5 — GPIO[184] — — — EVTI GPIO[185] — MSEO0 — GPIO[186] — MCKO — GPIO[187] — MSEO1 — GPIO[188] — EVTO — GPIO[189] — MDO6 — GPIO[190] — MDO7 — GPIO[191] — MDO8 — GPIO[192] — MDO9 —
SIUL — Nexus — SIUL — — — Nexus SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus — SIUL — Nexus —
I/O — O — I/O — — — I I/O — O — I/O — O — I/O — O — I/O — O — I/O — O — I/O — O — I/O — O — I/O — O —
M/S
—
—
PL[8]
PCR[184]
S
Pull-up
—
—
PL[9]
PCR[185]
M/S
Tristate
—
—
PL[10]
PCR[186]
F/S
Tristate
—
—
PL[11]
PCR[187]
M/S
Tristate
—
—
PL[12]
PCR[188]
M/S
Tristate
—
—
PL[13]
PCR[189]
M/S
Tristate
—
—
PL[14]
PCR[190]
M/S
Tristate
—
—
PL[15]
PCR[191]
M/S
Tristate
—
—
PM[0]
PCR[192]
M/S
Tristate
—
—
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37
Table 4. Functional port pin descriptions (continued)
Pin number Peripheral I/O direction2 Alternate function1 Pad type 176 LQFP 208 LQFP Port pin 256 MAPBGA E9 F12 K12 L12 F9 F6 RESET config. Tristate
PCR
Function
PM[1]
PCR[193]
AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3 AF0 AF1 AF2 AF3
GPIO[193] — MDO10 — GPIO[194] — MDO11 — GPIO[195] — — — GPIO[196] — — — GPIO[197] — — — GPIO[198] — — —
SIUL — Nexus — SIUL — Nexus — SIUL — — — SIUL — — — SIUL — — — SIUL — — —
I/O — O — I/O — O — I/O — — — I/O — — — I/O — — — I/O — — —
M/S
—
—
PM[2]
PCR[194]
M/S
Tristate
—
—
PM[3]
PCR[195]
M/S
Tristate
—
—
PM[4]
PCR[196]
M/S
Tristate
—
—
PM[5]
PCR[197]
M/S
Tristate
—
—
PM[6]
PCR[198]
M/S
Tristate
—
—
1
2 3 4
5 6
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 000 AF0; PCR.PA = 001 AF1; PCR.PA = 010 AF2; PCR.PA = 011 AF3; PCR.PA = 100 ALT4. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is ignored. SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins, other functionality of the pin cannot be used and it should be ensured that application never programs OBE and PUE bit of the corresponding PCR to "1". If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10] can induce coupling on PB[9] and disturb oscillator frequency. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed.
MPC5646C Microcontroller Data Sheet, Rev. 3 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor
7
When MBIST is enabled to run ( STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V before the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST operation. When MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally drive the pad. 8 These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development Interface "Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO[1:0], and MCKO ports by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by programming NDI ((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]).
4
Electrical Characteristics
This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS_HV). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column.
4.1
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 5 are used and the parameters are tagged accordingly in the tables where appropriate. Table 5. Parameter classifications
Classification tag P C T Tag description Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where appropriate.
4.2
NVUSRO register
Portions of the device configuration, such as high voltage supply is controlled via bit values in the Non-Volatile User Options Register (NVUSRO). For a detailed description of the NVUSRO register, see MPC5646C Reference Manual.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39
4.2.1
NVUSRO [PAD3V5V(0)] field description
Table 6. PAD3V5V(0) field description
Value1 0 1 Description High voltage supply is 5.0 V High voltage supply is 3.3 V
Table 6 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for VDD_HV_A domain.
1
'1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.2.2
NVUSRO [PAD3V5V(1)] field description
Table 7 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device configuration for VDD_HV_B domain. Table 7. PAD3V5V(1) field description
Value1 0 1
1
Description High voltage supply is 5.0 V High voltage supply is 3.3 V
'1' is delivery value. It is part of shadow flash memory, thus programmable by customer.
The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.
4.3
Absolute maximum ratings
Table 8. Absolute maximum ratings
Value Symbol VSS_HV VDD_HV_A Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV_A pins with respect to ground (VSS_HV) SR Voltage on VDD_HV_B pins with respect to common ground (VSS_HV) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS_HV) Base control voltage for external BCP68 NPN device Conditions Min — — 0 –0.3 Max 0 6.0 V V Unit
VDD_HV_B1
—
–0.3
6.0
V
VSS_LV
—
VSS_HV 0.1
VSS_HV 0.1
V
VRC_CTRL2
Relative to VDD_LV
0
VDD_LV + 1
V
MPC5646C Microcontroller Data Sheet, Rev. 3 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 8. Absolute maximum ratings (continued)
Value Symbol VSS_ADC Parameter SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS_HV) Conditions Min — VSS_HV 0.1 Max VSS_HV + 0.1 V Unit
VDD_HV_ADC0 SR Voltage on VDD_HV_ADC0 with respect to ground (VSS_HV) VDD_HV_ADC14 SR Voltage on VDD_HV_ADC1 with respect to ground (VSS_HV) VIN IINJPAD IINJSUM SR Voltage on any GPIO pin with respect to ground (VSS_HV) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR Sum of all the static I/O current within a supply segment (VDD_HV_A or VDD_HV_B) SR Storage temperature
— Relative to VDD_HV_A — Relative to VDD_HV_A2 Relative to VDD_HV_A/HV_B — —
3
–0.3
6.0
V
VDD_HV_A 0.3 VDD_HV_A+0.3 –0.3 VDD_HV_A0.3 6.0 VDD_HV_A+0.3 V mA V
VDD_HV_A/HV_B VDD_HV_A/HV_B 0.3 +0.3 –10 –50 10 50
IAVGSEG5
VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 — –556
70 64 150
mA
TSTORAGE
1 2 3 4 5 6
°C
VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust against any supply order. This voltage is internally generated by the device and no external voltage should be supplied. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±300 mV of VDD_HV_B when these channels are used for ADC_1. Any temperature beyond 125 °C should limit the current to 50 mA (max). This is the storage temperature for the flash memory.
NOTE
Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD_HV_A/HV_B or VIN < VSS_HV), the voltage on pins with respect to ground (VSS_HV) must not exceed the recommended values.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41
4.4
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Value Symbol VSS_HV VDD_HV_A1 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV_A pins with respect to ground (VSS_HV) SR Voltage on VDD_HV_B pins with respect to ground (VSS_HV) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS_HV) Base control voltage for external BCP68 NPN device SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS_HV) Conditions Min — — 0 3.0 Max 0 3.6 V V Unit
VDD_HV_B1
—
3.0
3.6
V
VSS_LV2
—
VSS_HV 0.1
VSS_HV + 0.1
V
VRC_CTRL3 VSS_ADC
Relative to VDD_LV —
0 VSS_HV 0.1
VDD_LV + 1 VSS_HV + 0.1
V V
VDD_HV_ADC04 SR Voltage on VDD_HV_ADC0 with respect to ground (VSS_HV) VDD_HV_ADC17 SR Voltage on VDD_HV_ADC1 with respect to ground (VSS_HV) VIN SR Voltage on any GPIO pin with respect to ground (VSS_HV)
— Relative to VDD_HV_A6
3.05
3.6
V
VDD_HV_A 0.1 VDD_HV_A + 0.1 3.0 3.6 V
— Relative to VDD_HV_A6
VDD_HV_A 0.1 VDD_HV_A + 0.1 VSS_HV 0.1 — 5 50 — VDD_HV_A/HV_B + 0.1 5 50 mA V
— Relative to VDD_HV_A/HV_B — —
IINJPAD IINJSUM
SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD_HV_A slope to ensure correct power up8 SR Ambient temperature under bias SR Junction temperature under bias
TVDD
— — fCPU up to 120 MHz 2% —
— 0.5 –40 40
0.5 — 125 150
V/µs V/min °C
TA TJ
1
100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each VDD/VSS_HV pair.
MPC5646C Microcontroller Data Sheet, Rev. 3 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor
2 3 4 5
6 7 8
100 nF EMI capacitance and 10 µF bulk capacitance need to be provided between each of the four VDD_LV/VSS_LV supply pairs. For details refer to the Power Management chapter of the MPC5646C Reference Manual. This voltage is internally generated by the device and no external voltage should be supplied. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1. Guaranteed by the device validation.
Table 10. Recommended operating conditions (5.0 V)
Value Symbol VSS_HV VDD_HV_A1 Parameter SR Digital ground on VSS_HV pins SR Voltage on VDD_HV_A pins with respect to ground (VSS_HV) SR Generic GPIO functionality Ethernet/3.3 V functionality (See the notes in all figures in Section 3, “Package pinouts and signal descriptions” for the list of channels operating in VDD_HV_B domain) VSS_LV3 SR Voltage on VSS_LV (Low voltage digital supply) pins with respect to ground (VSS_HV) Base control voltage for external BCP68 NPN device SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC reference) pin with respect to ground (VSS_HV) Conditions Min — — Voltage drop — —
2
Unit Max 0 5.5 5.5 5.5 3.6 V V V V 0 4.5 3.0 3.0 3.0
VDD_HV_B
—
VSS_HV – 0.1
VSS_HV + 0.1
V
VRC_CTRL4 VSS_ADC
Relative to VDD_LV —
0 VSS_HV – 0.1
VDD_LV + 1 VSS_HV + 0.1
V V
VDD_HV_ADC05 SR Voltage on VDD_HV_ADC0 with respect to ground (VSS_HV)
— Voltage drop
(2)
4.5 3.0 VDD_HV_A – 0.1 4.5 3.0 VDD_HV_A 0.1
5.5 5.5 VDD_HV_A + 0.1 5.5 5.5 VDD_HV_A + 0.1
V
Relative to VDD_HV_A6 VDD_HV_ADC17 SR Voltage on VDD_HV_ADC1 with respect to ground (VSS_HV) — Voltage drop(2) Relative to VDD_HV_A6
V
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43
Table 10. Recommended operating conditions (5.0 V) (continued)
Value Symbol VIN Parameter SR Voltage on any GPIO pin with respect to ground (VSS_HV) Conditions Min — Relative to VDD_HV_A/HV_B — — — — — — — — — — VSS_HV –0.1 — –5 –50 — 0.5 40 40 40 40 40 40 Max — VDD_HV_A/HV_B + 0.1 5 50 0.5 — 85 110 105 130 125 150 °C V/µs V/min mA V Unit
IINJPAD IINJSUM TVDD
SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition SR VDD_HV_A slope to ensure correct power up8
TA C-Grade Part SR Ambient temperature under bias TJ C-Grade Part SR Junction temperature under bias TA V-Grade Part SR Ambient temperature under bias TJ V-Grade Part SR Junction temperature under bias TA M-Grade Part SR Ambient temperature under bias TJ M-Grade Part SR Junction temperature under bias
1 2
3 4 5 6 7 8
100 nF EMI capacitance and 10 µF bulk capacitance needs to be provided between each VDD_HV_A/HV_B/VSS_HV pair. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC electrical characteristics (startup time, IDD, negative resistance, ESR and duty cycle) will not be guaranteed to stay within the stated limits when operating below 4.5 V and above 3.6 V. However, OSC functionality is guaranteed within the entire range (3.0 V–5.5 V). 100 nF EMI capacitance and 40 µF bulk capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. This voltage is internally generated by the device and no external voltage should be supplied. 100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is 6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1. Guaranteed by device validation.
NOTE
SRAM retention guaranteed to LVD levels.
MPC5646C Microcontroller Data Sheet, Rev. 3 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor
4.5
4.5.1
Thermal characteristics
Package thermal characteristics
Table 11. LQFP thermal characteristics1
Symbol RJA CC C D Parameter Thermal resistance, junction-to-ambient natural convection4 Thermal resistance, junction-to-ambient natural convection7 Conditions Single-layer board—1s Four-layer board—2s2p7
2
Value3 Pin count Min 176 208 176 208 — — — — Typ — — — — Max 385 41
6
Unit °C/W °C/W °C/W °C/W
RJA
CC
D
31 34
1 2 3 4
5 6 7
Thermal characteristics are targets based on simulation that are subject to change per device characterization. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C. All values need to be confirmed during device validation. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-2 and JESD51-6 Junction-to-Board thermal resistance determined per JEDEC JESD51-8.
Table 12. 256 MAPBGA thermal characteristics1
Symbol RJA
1
C
Parameter
Conditions Single-layer board—1s Four-layer board—2s2p
Value 432 26
3
Unit °C/W
CC
— Thermal resistance, junction-to-ambient natural convection
Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-ambient thermal resistance determined per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-6 with the board horizontal.
2
4.5.2
Power considerations
TJ = TA + (PD RJA) Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Eqn. 1
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1:
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 °C) Therefore, solving equations 1 and 2: K = PD (TA + 273 °C) + RJA PD2 Eqn. 3 Eqn. 2
Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA.
4.6
4.6.1
• • • • •
I/O pad electrical characteristics
I/O pad types
Slow pads—These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads—These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads—These pads provide maximum speed. These are used for improved Nexus debugging capability. Input only pads—These pads are associated to ADC channels and 32 kHz low power external crystal oscillator providing low input leakage. Low power pads—These pads are active in standby mode for wakeup source.
The device provides four main I/O pad types depending on the associated alternate functions:
Also, medium/slow and fast/medium pads are available in design which can be configured to behave like a slow/medium and medium/fast pads depending upon the slew-rate control. Medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
4.6.2
I/O input DC characteristics
Table 13 provides input DC electrical characteristics as described in Figure 5.
MPC5646C Microcontroller Data Sheet, Rev. 3 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor
VIN VDD VIH
VHYS
VIL
PDIx = ‘1 (GPDI register of SIUL)
PDIx = ‘0’
Figure 5. I/O input DC electrical characteristics definition Table 13. I/O input DC electrical characteristics
Symbol VIH VIL C Parameter Conditions1 Min SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) — — — No injection TA = 40 °C on adjacent TA = 25 °C pin TA = 105 °C TA = 125 °C — — 0.65VDD 0.3 0.1VDD — — — — — 10004 Value2 Unit Typ — — — 2 2 12 70 — — Max VDD + 0.4 0.35VDD — — — 500 1000 404 — ns ns nA V
VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P D P WFI SR P Width of input pulse rejected by analog filter3
WNFI SR P Width of input pulse accepted by analog filter(3)
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation. 3 Analog filters are available on all wakeup lines. 4 The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending on silicon sample to sample variation.
4.6.3
I/O output DC characteristics
The following tables provide DC characteristics for bidirectional pads:
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47
• • • •
Table 14 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 15 provides output driver characteristics for I/O pads when in SLOW configuration. Table 16 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 17 provides output driver characteristics for I/O pads when in FAST configuration. Table 14. I/O pull-up/pull-down DC electrical characteristics
Symbol |IWPU| CC C P C P |IWPD| CC P C P
1 2
Parameter
Conditions1,2 Min 10 10 10 10 10 10
Value Unit Typ — — — — — — Max 150 250 150 150 250 150 µA µA
Weak pull-up VIN = VIL, VDD = PAD3V5V = 0 current absolute 5.0 V ± 10% PAD3V5V = 13 value VIN = VIL, VDD = PAD3V5V = 1 3.3 V ± 10% Weak pull-down VIN = VIH, VDD = PAD3V5V = 0 current absolute 5.0 V ± 10% PAD3V5V = 1 value VIN = VIH, VDD = PAD3V5V = 1 3.3 V ± 10%
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 15. SLOW configuration output buffer electrical characteristics
Symbol C Parameter Conditions1,2 Min VOH CC P Output high level SLOW configuration C P VOL CC P Output low level SLOW configuration C Push Pull IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 0.8VDD 0.8VDD Value Unit Typ — — — — — Max — — — 0.1VDD 0.1VDD V V
IOH = 1.5 mA, VDD 0.8 VDD = 3.3 V ± 10%, PAD3V5V = 1 Push Pull IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) IOL = 1.5 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 — —
P
1 2
—
—
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5646C Microcontroller Data Sheet, Rev. 3 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 16. MEDIUM configuration output buffer electrical characteristics
Symbol VOH CC C C Parameter Output high level MEDIUM configuration Conditions1,2 Min Push Pull IOH = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 IOH = 1.5 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 IOH = 2 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 Output low level MEDIUM configuration Push Pull IOL = 3 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 IOL = 1.5 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) IOL = 2 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 0.8VDD Value Unit Typ — Max —
C
0.8VDD
—
—
V
C
VDD 0.8
—
—
VOL
CC
C
—
—
0.2VDD
C
—
—
0.1VDD
V
C
—
—
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
1 2
Table 17. FAST configuration output buffer electrical characteristics
Symbol VOH CC C P Parameter Conditions1,2 Min Output high level Push Pull IOH = 14 mA, FAST VDD = 5.0 V ± 10%, PAD3V5V = 0 configuration IOH = 7 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 IOH = 11 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 0.8VDD Value Unit Typ — Max — V
C
0.8VDD
—
—
C
VDD 0.8
—
—
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49
Table 17. FAST configuration output buffer electrical characteristics (continued)
Symbol VOL CC C P Parameter Conditions1,2 Min Output low level Push Pull IOL = 14 mA, FAST VDD = 5.0 V ± 10%, PAD3V5V = 0 configuration IOL = 7 mA, VDD = 5.0 V ± 10%, PAD3V5V = 1(3) IOL = 11 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 — Value Unit Typ — Max 0.1VDD V
C
—
—
0.1VDD
C
—
—
0.5
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 The configuration PAD3V5 = 1 when V DD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
1 2
4.6.4
Output pin transition times
Table 18. Output pin transition times
Value3 Unit Min Typ — — — — — — — — — — — — Max 50 100 125 40 50 75 10 20 40 12 25 40 ns ns — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 — — — — — —
Symbol Ttr CC
C D T D D T D
Parameter
Conditions1,2 VDD = 5.0 V ± 10%, PAD3V5V = 0
Output transition time CL = 25 pF output pin4 CL = 50 pF SLOW configuration CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF Output transition time CL = 25 pF output pin(4) CL = 50 pF MEDIUM configuration CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF
Ttr
CC
D T D D T D
MPC5646C Microcontroller Data Sheet, Rev. 3 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 18. Output pin transition times (continued)
Symbol Ttr CC C D Parameter Conditions
1,2
Value3 Unit Min Typ — — — — — — Max 4 6 12 4 7 12 ns — — —
Output transition time CL = 25 pF output pin(4) CL = 50 pF FAST configuration CL = 100 pF CL = 25 pF CL = 50 pF CL = 100 pF
VDD = 5.0 V ± 10%, PAD3V5V = 0
VDD = 3.3 V ± 10%, PAD3V5V = 1
— — —
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 All values need to be confirmed during device validation. 4 C includes device and package capacitances (C L PKG < 5 pF).
1 2
4.6.5
I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated to a VDD/VSS_HV supply pair as described in Table 19. Table 20 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 19. I/O supplies
Package 256 MAPBGA 208 LQFP pin6 (VDD_HV_A) pin7 (VSS_HV) pin6 (VDD_HV_A) pin7 (VSS_HV) I/O Supplies Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11 pin27 (VDD_HV_A) pin28 (VSS_HV) pin27 (VDD_HV_A) pin28 (VSS_HV) pin73 (VSS_HV) pin75 (VDD_HV_A) pin57 (VSS_HV) pin59 (VDD_HV_A) pin101 (VDD_HV_A) pin102 (VSS_HV) pin85 (VDD_HV_A) pin86 (VSS_HV) pin132 (VSS_HV) pin133 (VDD_HV_A) pin123 (VSS_HV) pin124 (VDD_HV_B) pin147 (VSS_HV) pin148 (VDD_HV_B) pin150 (VSS_HV) pin151 (VDD_HV_A) pin174 (VSS_HV) pin175 (VDD_HV_A) — —
176 LQFP
—
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51
Table 20. I/O consumption
Symbol ISWTSLW,4 C Parameter Conditions1,2 Min CC D Peak I/O current for CL = 25 pF SLOW configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 ISWTMED(4) CC D Peak I/O current for MEDIUM configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 IRMSSLW CC D Root mean square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz CL = 100 pF, 2 MHz IRMSMED CC D Root mean square I/O current for MEDIUM configuration CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz CL = 100 pF, 13 MHz IRMSFST CC D Root mean square CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%, I/O current for FAST PAD3V5V = 0 CL = 25 pF, 64 MHz configuration CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz CL = 100 pF, 40 MHz IAVGSEG SR D Sum of all the static I/O current within a supply segment VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 5.0 V ± 10%, PAD3V5V = 0 — — — — — — — — — VDD = 3.3 V ± 10%, PAD3V5V = 1 — — — — — — — — — — — — — — — — — Value3 Unit Typ — — — — — — — — — — — — — — — — — — — — — — — — — — Max 19.9 15.5 28.8 16.3 113.5 52.1 2.22 3.13 6.54 1.51 2.14 4.33 6.5 13.32 18.26 4.91 8.47 10.94 21.05 mA 33 55.77 14 20 34.89 70 654 mA mA mA mA mA mA
ISWTFST(4)
CC D Peak I/O current for FAST configuration
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. 3 All values need to be confirmed during device validation. 4 Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
1 2
MPC5646C Microcontroller Data Sheet, Rev. 3 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor
4.7
RESET electrical characteristics
VDD_HV_A VDDMIN
The device implements a dedicated bidirectional RESET pin.
RESET
VIH VIL device reset forced by RESET device start-up phase
Figure 6. Start-up reset requirements
VRESET hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset
Figure 7. Noise filtering on reset signal Table 21. Reset electrical characteristics
Symbol VIH C Parameter Conditions1 Min SR P Input High Level CMOS (Schmitt Trigger) — 0.65VDD Value2 Unit Typ — Max VDD + 0.4 V
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 53
Table 21. Reset electrical characteristics (continued)
Symbol VIL VHYS VOL C Parameter Conditions — — Push Pull, IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) Push Pull, IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 13 Push Pull, IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) Ttr CC D Output transition time output pin4 MEDIUM configuration CL = 25 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 50 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 100 pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 25 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 50 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 WFRST SR P Reset input filtered pulse WNFRST SR P Reset input not filtered pulse |IWPU| CC P Weak pull-up current absolute value — — VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 5.0 V ± 10%, PAD3V5V = 15
1 2 1
Value2 Unit Min Typ — — — Max 0.35VDD — 0.1VDD V V V 0.3 0.1VDD —
SR P Input low Level CMOS (Schmitt Trigger) CC C Input hysteresis CMOS (Schmitt Trigger) CC P Output low level
— —
— —
0.1VDD 0.5
— — — — — — — 1000 10 10 10
— — — — — — — — — — —
10 20 40 12 25 40 40 — 150 150 250
ns
ns ns µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation. 3 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the device Reference Manual). 4 C includes device and package capacitance (C L PKG < 5 pF). 5 The configuration PAD3V5 = 1 when V DD = 5 V is only transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
MPC5646C Microcontroller Data Sheet, Rev. 3 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor
4.8
4.8.1
• •
Power management electrical characteristics
Voltage regulator electrical characteristics
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD_HV_A power pin. LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the on-chip VREG with an external ballast (BCP68 NPN device). It is further split into four main domains to ensure noise isolation between critical LV modules within the device: — LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. — LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is shorted with LV_COR through double bonding. — LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR through double bonding. — LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.
100 nf
VDD_LV VSS_LV VDD_LV
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage supply VDD_HV_A. The following supplies are involved:
100 nf
VSS_LV VDD_LV
100 nf
VSS_LV
40 f (4 10 f) PD1 Switchable Domain (FMPLL, Flash)
(CREGn)
PD0 (always on domain)
PD0 Logic
32 KB Split
56 KB Split
8 KB Split
CTRL VDD_LV VSS_LV Off chip BCP68 NPN driver VRC_CTRL HPVDD
CTRL
CTRL
HPREG
LPVDD
sw1 ( 2.6 V for correct functionality. The device is not monitoring this supply hence the external component must meet the 2.6 V criteria through external monitoring if required. Table 22. Voltage regulator electrical characteristics
Symbol CREGn RREG CREGP C Parameter Conditions1 Min SR — External ballast stability capacitance SR — Stability capacitor equivalent serial resistance SR — Decoupling capacitance (Close to the pin) — — VDD_HV_A/HV_B/VSS_HV pair VDD_LV/VSS_LV pair CDEC2 VMREG SR — Stability capacitance regulator VDD_HV_A/VSS_HV supply (Close to the ballast collector) CC P Main regulator output voltage Before trimming After trimming IMREG IMREGINT SR — Main regulator current provided to VDD_LV domain CC D Main regulator module current consumption — IMREG = 200 mA IMREG = 0 mA 10 — — — — — — — 40 — Value2 Unit Typ — — 100 100 — 1.32 1.28 — — — 1.23 — Max 60 0.2 — — 40 — — 350 2 1 — 50 V mA mA mA F nF nF F V
•
VLPREG ILPREG
CC P Low power regulator output voltage After trimming SR — Low power regulator current provided to VDD_LV domain —
MPC5646C Microcontroller Data Sheet, Rev. 3 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 22. Voltage regulator electrical characteristics (continued)
Symbol ILPREGINT C Parameter Conditions
1
Value2 Unit Min Typ — 20 2 Max 600 — — A A — — —
CC D Low power regulator module current ILPREG = 15 mA; consumption TA = 55 °C — ILPREG = 0 mA; TA = 55 °C TA = 55 °C
IVREGREF
CC D Main LVDs and reference current consumption (low power and main regulator switched off) CC D Main LVD current consumption (switch-off during standby) CC D In-rush current on VDD_HV_A3 during power-up
IVREDLVD12 IDD_HV_A
1 2
TA = 55 °C —
— —
1 —
— 6004
A mA
VDD_HV_A = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Assumption is V DD_HV_A is now supplying the external ballast. This current is the ballast inrush current. 4 Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in ~25 steps to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA
4.8.3
• • • • •
Voltage monitor electrical characteristics
POR monitors VDD_HV_A during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD_HV_A to ensure device is reset below minimum functional supply LVDHV5 monitors VDD_HV_A when application uses device in the 5.0 V±10% range LVDLVCOR monitors power domain No. 1 (PD1) LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply.
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD_HV_A and the VDD_LV voltage while device is supplied:
NOTE
When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57
VDDHV/LV
VLVDHVxH/LVxH VLVDHVxL/LVxL
RESET
Figure 9. Low voltage monitor vs. Reset Table 23. Low voltage monitor electrical characteristics
Symbol VPORUP VPORH VLVDHV3H VLVDHV3L VLVDHV5H VLVDHV5L C Parameter Conditions1 Min SR P Supply for functional POR module CC P Power-on reset threshold CC T LVDHV3 low voltage detector high threshold CC T LVDHV3 low voltage detector low threshold CC T LVDHV5 low voltage detector high threshold CC T LVDHV5 low voltage detector low threshold — — — — — — TA = 25 °C, after trimming 1.0 1.5 2.7 2.6 4.3 4.2 Value2 Unit Typ — — — — — — 1.14
3
Max 5.5 2.6 2.85 2.74 4.5 4.4 V
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold
1
1.143
2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 The min. and max variation across process voltage and temperature will be available after device characterization. Expected to be within 10 mV.
4.9
Low voltage domain power consumption
Table 24 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application.
MPC5646C Microcontroller Data Sheet, Rev. 3 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 24. Low voltage power domain electrical characteristics
Symbol IDDMAX4 IDDRUN C Parameter Conditions1 Min CC D RUN mode maximum average current CC T RUN mode typical average current7 T CC P HALT mode current
11 12
Value Typ2 210 1758,9 110 — 25 400
9 8
Max3 3005,6 2409,10 150
10
Unit mA mA mA mA µA mA µA µA µA µA µA µA µA mA µA µA
— at 120 MHz at 80 MHz — No clocks active TA = 25 °C TA = 150 °C No clocks active TA = 25 °C TA = 150 °C No clocks active TA = 25 °C TA = 150 °C No clocks active TA = 25 °C TA = 150 °C — — — — TA = 25 °C TA = 25 °C TA = 25 °C TA = 25 °C TA = 25 °C TA = 25 °C
— —
IDDHALT IDDSTOP
35 1200
9,13
CC P STOP mode current P
— — — — — — — — — — — —
109 60 1000 45 800 25 500 — — — —
309 175 3000 135 2000 75 1000 5 3 500 5
IDDSTDBY3 CC P STANDBY3 mode (96 KB RAM current14 P retained) IDDSTDBY2 CC P STANDBY2 mode (64 KB RAM current15 P retained) IDDSTDBY1 CC T STANDBY1 mode (8 KB RAM current16 P retained) Adders in LP CC T 32 kHz OSC mode 4–40 MHz OSC 16 MHz IRC 128 kHz IRC
1 2 3 4
5 6 7
8
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified All temperatures are based on an ambient temperature. Target typical current consumption for the following typical operating conditions and configuration. Process = typical, Voltage = 1.2 V. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage = 1.32 V. Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 22. Maximum “allowed” current is package dependent. Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. RUN current measured with typical application with accesses on both code flash and RAM. Subject to change, Configuration: 1 e200z4d + 4 kbit/s Cache, 1 eDMA (32 ch), 4 FlexCAN (2 500 kbit/s, 2 125 kbit/s), 10 LINFlexD (20 kbit/s), 8 DSPI (4 2 Mbit/s, 3 4 Mbit/s, 1 10 Mbit/s), 40 PWM (200 Hz), 40 ADC Input, 1 CTU (40 ch.), 1 FlexRay (2 ch., 10 Mbit/s), 1 RTC, 4 PIT, 1 SWT, 1 STM. Ethernet and e200z0h disabled. Also reduced timed I/O channels for smaller packages. RUN current measured with typical application with accesses on both code flash and RAM.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59
9
This value is obtained from limited sample set Subject to change, Configuration: 1 e200z4d + 4 kbit/s Cache, 1 e200z0h (1/2 system frequency), CSE, 1 eDMA (10 ch.), 6 FlexCAN (4 500 kbit/s, 2 125 kbit/s), 4 LINFlexD (20 kbit/s), 6 DSPI (2 2 Mbit/s, 3 4 Mbit/s, 1 10 Mbit/s), 16 Timed I/O, 16 ADC Input, 1 FlexRay (2 ch., 10 Mbit/s), 1 FEC (100 Mbit/s), 1 RTC, 4 PIT, 1 SWT, 1 STM. For lower pin count packages reduce the amount of timed I/O’s and ADC channels. RUN current measured with typical application with accesses on both code flash and RAM. 11 Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2 ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication, instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs. 12 Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON. All possible peripherals off and clock gated. Flash in power down mode. 13 This current is the maximum value at room temperature for any sample. The condition is same as note 11. 14 Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption, all possible modules switched-off. 15 Only for the “P” classification: LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption, all possible modules switched-off. 16 LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched OFF.
10
4.10
4.10.1
Flash memory electrical characteristics
Program/Erase characteristics
Table 25 shows the code flash memory program and erase characteristics. Table 25. Code flash memory—Program and erase specifications
Value Symbol C Parameter Min Tdwprogram T16Kpperase T32Kpperase T128Kpperase Teslat tESRT tPABT tEAPT
1
Typ1 18 200 300 600 — — — —
Initial max2 50 500 600 1300 30 — 10 30
Max3 500 5000 5000 5000 30 — 10 30
Unit
Double word (64 bits) program time4 C 16 KB block pre-program and erase time 32 KB block pre-program and erase time 128 KB block pre-program and erase time CC D Erase Suspend Latency C Erase Suspend Request Rate D Program Abort Latency D Erase Abort Latency
— — — — — 20 — —
µs ms ms ms µs ms µs µs
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.
MPC5646C Microcontroller Data Sheet, Rev. 3 60 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 26 shows the data flash memory program and erase characteristics. Table 26. Data flash memory—Program and erase specifications
Value Symbol C Parameter Min Twprogram T16Kpperase Teslat tESRT tPABT tEAPT
1
Typ1 30 700 — — — —
Initial max2 70 800 30 — 12 30
Max3 500 5000 30 — 12 30
Unit
Word (32 bits) program time4 C 16 KB block pre-program and erase time
— — — 10 — —
µs ms µs ms µs µs
D Erase Suspend Latency CC C Erase Suspend Request Rate D Program Abort Latency D Erase Abort Latency
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead.
Table 27. Flash memory module life
Value Symbol P/E CC C Parameter Conditions Min C Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) Retention CC C Minimum data retention at 85 °C average ambient temperature1 — 100,000 Typ 100,000 cycles Unit
—
10,000
100,000 cycles
—
1,000
100,000 cycles
Blocks with 0–1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles
20 10 5
— — —
years years years
1
Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 61
ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Table 28. Flash memory read access timing
Conditions1 Symbol C Parameter Code flash memory Data flash memory 13 wait states 9 wait state — 7 wait states Max Unit
fREAD
CC
P Maximum frequency for Flash reading 5 wait states C D C 3 wait state 3 wait states2 —
120 2% 80 2% 64 2% MHz
1 2
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. Wait states are subject to change per device characterization.
4.10.2
Flash memory power supply DC characteristics
Table 29. Flash memory power supply DC electrical characteristics
Table 29 shows the flash memory power supply DC characteristics on external supply.
Symbol
Parameter
Conditions1 Min
Value2 Unit Typ Max 33 13 52 13 1.1 mA mA mA
ICFREAD3 CC Sum of the current consumption Flash memory module read Code flash on VDD_HV_A on read access memory fCPU = 120 MHz 2%4 IDFREAD(3) Data flash memory
Code flash ICFMOD(3) CC Sum of the current consumption Program/Erase on-going while reading flash memory memory on VDD_HV_A (program/erase) registers IDFMOD(3) Data flash fCPU = 120 MHz 2% (4) memory ICFLPW(3) CC Sum of the current consumption on VDD_HV_A during flash memory low power mode ICFPWD(3) CC Sum of the current consumption on VDD_HV_A during flash memory power down mode (3) IDFPWD
1
Code flash memory Code flash memory Data flash memory
150 150
µA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Data based on characterization results, not tested in production. 4 fCPU 120 MHz 2% can be achieved over full temperature 125 °C ambient, 150 °C junction temperature.
2
MPC5646C Microcontroller Data Sheet, Rev. 3 62 Preliminary—Subject to Change Without Notice Freescale Semiconductor
4.10.3
Flash memory start-up/switch-off timings
Table 30. Start-up time/Switch-off time
Value Unit Min Typ — — — — — — 0.5 0.5 µs — — — — — 30 Max 125 — — — —
Symbol TFLARSTEXIT
C
Parameter Code flash memory Data flash memory
Conditions1 —
CC D Delay for flash memory module to exit reset mode
TFLALPEXIT TFLAPDEXIT
CC T Delay for flash memory module to exit low-power mode CC T Delay for flash memory module to exit power-down mode
Code flash memory Code flash memory Data flash memory
TFLALPENTRY CC T Delay for flash memory module to enter low-power mode
1
Code flash memory
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
4.11
Electromagnetic compatibility (EMC) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
4.11.1
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and pre-qualification tests in relation with the EMC level requested for the application. • Software recommendations The software flowchart must include the management of runaway conditions such as: — Corrupted program counter — Unexpected reset — Critical data corruption (control registers) Pre-qualification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
•
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 63
4.11.2
Electromagnetic interference (EMI)
The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI measurements. Table 31. EMI radiated emission measurement1,2
Value Symbol — C Parameter Conditions Min SR — Scan range — — — No PLL frequency VDD = 5 V, TA = 25 °C, modulation LQFP176 package Test conforming to IEC 61967-2, ± 2% PLL frequency fOSC = 40 MHz/fCPU = 120 MHz modulation 0.150 — — — — 120 1.28 — — Typ Max 1000 MHz — — 18 MHz V dBµV Unit
fCPU SR — Operating frequency VDD_LV SR — LV operating voltages SEMI CC T Peak level
143 dBµV
EMI testing and I/O port waveforms per IEC 61967-1, -2, -4. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 3 All values need to be confirmed during device validation.
2
1
4.11.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
4.11.3.1
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts (n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 32. ESD absolute maximum ratings1,2
Symbol Ratings Conditions TA = 25 °C conforming to AEC-Q100-002 TA = 25 °C conforming to AEC-Q100-003 TA = 25 °C conforming to AEC-Q100-011 Class H1C M2 C3A Max value3 2000 200 500 750 (corners) Unit V
VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(MM) Electrostatic discharge voltage (Machine Model) VESD(CDM) Electrostatic discharge voltage (Charged Device Model)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production.
MPC5646C Microcontroller Data Sheet, Rev. 3 64 Preliminary—Subject to Change Without Notice Freescale Semiconductor
4.11.3.2
• •
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance: A supply over-voltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Table 33. Latch-up results
Symbol LU Parameter Static latch-up class Conditions TA = 125 °C conforming to JESD 78 Class II level A
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
4.12
Fast external crystal oscillator (4–40 MHz) electrical characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 34 provides the parameter description of 4 MHz to 40 MHz crystals used for the design simulations.
EXTAL C1 Crystal XTAL RD XTAL
DEVICE
VDD
C2
I
R
EXTAL EXTAL Resonator XTAL
DEVICE
DEVICE
Figure 10. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65
Table 34. Crystal description
Crystal equivalent series resistance ESR 300 300 NX5032GA 150 120 120 NX5032GA 50 Crystal motional capacitance (Cm) fF 2.68 2.46 2.93 3.11 3.90 6.18 Crystal motional inductance (Lm) mH 591.0 160.7 86.6 56.5 25.3 2.56 Load on xtalin/xtalout C1 = C2 (pF)1 21 17 15 15 10 8 Shunt capacitance between xtalout and xtalin C02 (pF) 2.93 3.01 2.91 2.93 3.00 3.49
Nominal frequency (MHz)
NDK crystal reference
4 8 10 12 16 40
1
NX8045GB
The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2 The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.).
S_MTRANS bit (ME_GS register) 1
0 VXTAL VFXOSC VFXOSCOP 10% TMXOSCSU valid internal clock
1/fMXOSC 90%
Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics Table 35. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Symbol fFXOSC gmFXOSC C Parameter Conditions1 Min SR — Fast external crystal oscillator frequency — 4.0 8.699 9.440 Value2 Unit Typ — 13.159 13.159 Max 40.0 15.846 16.859 MHz mA/V
CC C Fast external crystal VDD = 3.3 V ± 10% oscillator VDD = 5.0 V ± 10% transconductance
MPC5646C Microcontroller Data Sheet, Rev. 3 66 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 35. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
Symbol VFXOSC C Parameter Conditions
1
Value2 Unit Min Typ 0.95 Max — V —
CC T Oscillation fOSC = 40 MHz amplitude at EXTAL For both VDD = 3.3 V ± 10%, VDD = 5.0 V ± 10% CC P Oscillation operating point —
VFXOSCOP IFXOSC,3
— — — — — —
1.8 2 2.3 1.3 1.6 — 2.2 2.5
V
CC T Fast external crystal VDD = 3.3 V ± 10%, oscillator fOSC = 40 MHz consumption VDD = 5.0 V ± 10%, fOSC = 40 MHz VDD = 3.3 V ± 10%, fOSC = 16 MHz VDD = 5.0 V ± 10%, fOSC = 16 MHz
mA 1.5 1.8 5 ms
TFXOSCSU
CC T Fast external crystal fOSC = 40 MHz oscillator start-up For both VDD = 3.3 V ± time 10%, VDD = 5.0 V ± 10% SR P Input high level CMOS (Schmitt Trigger) SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode Oscillator bypass mode
VIH
0.65VDD_HV_A
—
VDD_HV_A + 0.4
V
VIL
0.3
—
0.35VDD_HV_A
V
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals).
1 2
4.13
Slow external crystal oscillator (32 kHz) electrical characteristics
The device provides a low power oscillator/resonator driver.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 67
OSC32K_EXTAL C1 RP
OSC32K_EXTAL Resonator OSC32K_XTAL C2
OSC32K_XTAL
DEVICE
Crystal
DEVICE
Figure 12. Crystal oscillator and resonator connection scheme
NOTE
OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.
l
C0
C1
Crystal
C2 C1
Cm
Rm
Lm C2
Figure 13. Equivalent circuit of a quartz crystal Table 36. Crystal motional characteristics1
Value Symbol Lm Cm Parameter Motional inductance Motional capacitance Conditions Min — — — AC coupled @ C0 = 2.85 pF4 AC coupled @ C0 = 4.9 pF AC coupled @ C0 = 7.0
(4)
Unit Typ 11.796 2 — — — — — Max — — 28 65 50 35 30 KH fF pF k — — 18 — — — —
C1/C2 Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground2 Rm3 Motional resistance
pF(4)
AC coupled @ C0 = 9.0 pF(4)
MPC5646C Microcontroller Data Sheet, Rev. 3 68 Preliminary—Subject to Change Without Notice Freescale Semiconductor
1 2
The crystal used is Epson Toyocom MC306. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3 Maximum ESR (Rm) of the crystal is 50 k 4 C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.
OSCON bit (OSC_CTL register) 1
0
VOSC32K_XTAL VLPXOSC32K 90%
1/fLPXOSC32K
10% TLPXOSC32KSU valid internal clock
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics Table 37. Slow external crystal oscillator (32 kHz) electrical characteristics
Symbol fSXOSC gmSXOSC C Parameter Conditions1 Min SR — Slow external crystal oscillator frequency CC — Slow external crystal oscillator transconductance CC T Oscillation amplitude — VDD = 3.3 V ± 10%, VDD = 5.0 V ± 10% — — — — 32 17.45 17.79 1.2 1.2 — — Value2 Unit Typ 32.768 — — 1.4 — — — Max 40 28.23 29.91 1.7 4.4 7 23 V µA µA s kHz µA/V
VSXOSC
ISXOSCBIAS CC T Oscillation bias current ISXOSC TSXOSCSU
1
CC T Slow external crystal oscillator consumption CC T Slow external crystal oscillator start-up time
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.
2
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 69
4.14
FMPLL electrical characteristics
Table 38. FMPLL electrical characteristics
Symbol fPLLIN PLLIN C Parameter Conditions — — — — — Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 40 MHz (resonator), fPLLCLK @ 120 MHz, 4000 cycles TA = 25 °C —
1
The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver.
Value2 Unit Min Typ — — — — — 40 — Max 64 60 120 120 + 2%4 150 100 6 (for < 1ppm) 3 MHz % MHz MHz MHz µs ns 4 40 16 — 20
SR — FMPLL reference clock3 SR — FMPLL reference clock duty cycle(3)
fPLLOUT CC P FMPLL output clock frequency fCPU fFREE tLOCK SR — System clock frequency CC P Free-running frequency CC P FMPLL lock time
tLTJIT CC — FMPLL long term jitter
IPLL
1 2
CC C FMPLL consumption
—
—
mA
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 4f CPU 120 + 2% MHz can be achieved at 125 °C.
4.15
Fast internal RC oscillator (16 MHz) electrical characteristics
Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol fFIRC
3,
The device provides a 16 MHz main internal RC oscillator. This is used as the default clock at the power-up of the device and can also be used as input to PLL.
C
Parameter
Conditions1 Min TA = 25 °C, trimmed — TA = 25 °C, trimmed — 12 —
Value2 Unit Typ 16 Max — 20 — 200 µA MHz
CC P Fast internal RC oscillator high frequency SR — CC T Fast internal RC oscillator high frequency current in running mode CC D Fast internal RC oscillator high frequency current in power D down mode D
IFIRCRUN
IFIRCPWD
TA = 25 °C TA = 55 °C TA = 125 °C
— — —
— — —
100 200 1
nA nA µA
MPC5646C Microcontroller Data Sheet, Rev. 3 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 39. Fast internal RC oscillator (16 MHz) electrical characteristics
Symbol C Parameter Conditions
1
Value2 Unit Min Typ 500 600 700 900 1250 — — — — — Max — — — — — 2.0 5 2.0 5 +1 % µs µA — — — — — — — — — 1
IFIRCSTOP CC T Fast internal RC oscillator high TA = 25 °C frequency and system clock current in stop mode
sysclk = off sysclk = 2 MHz sysclk = 4 MHz sysclk = 8 MHz sysclk = 16 MHz
TFIRCSU
CC C Fast internal RC oscillator start-up time — — —
TA = 55 °C
VDD = 5.0 V ± 10% VDD = 3.3 V ± 10%
TA = 125 °C VDD = 5.0 V ± 10% VDD = 3.3 V ± 10% TA = 25 °C
FIRCPRE
CC C Fast internal RC oscillator precision after software trimming of fFIRC
FIRCTRIM CC C Fast internal RC oscillator trimming step FIRCVAR CC C Fast internal RC oscillator variation over temperature and supply with respect to fFIRC at TA = 25 °C in high-frequency configuration
TA = 25 °C —
— 5
1.6 — +5
% %
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
1 2
4.16
Slow internal RC oscillator (128 kHz) electrical characteristics
Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics
Symbol fSIRC ISIRC3, TSIRCSU C Parameter Conditions1 Min CC P Slow internal RC oscillator low frequency SR — CC C Slow internal RC oscillator low frequency current TA = 25 °C, trimmed — TA = 25 °C, trimmed — 100 — — Value2 Unit Typ 128 — — 8 Max — 150 5 12 µA µs kHz
The device provides a 128 kHz low power internal RC oscillator. This can be used as the reference clock for the RTC module.
CC P Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ± 10% time
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71
Table 40. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Symbol SIRCPRE SIRCTRIM SIRCVAR C Parameter Conditions TA = 25 °C —
1
Value2 Unit Min Typ — 2.7 — Max +2 — +10 % % 2 — 10
CC C Slow internal RC oscillator precision after software trimming of fSIRC CC C Slow internal RC oscillator trimming step
CC C Slow internal RC oscillator variation High frequency configuration in temperature and supply with respect to fSIRC at TA = 55 °C in high frequency configuration
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.
1 2
4.17
4.17.1
ADC electrical characteristics
Introduction
NOTE
Due to ADC limitations, the two ADCs cannot sample a shared channel at the same time i.e., their sampling windows cannot overlap if a shared channel is selected. If this is done, neither of the ADCs can guarantee their conversion accuracies.
The device provides two Successive Approximation Register (SAR) analog-to-digital converters (10-bit and 12-bit).
MPC5646C Microcontroller Data Sheet, Rev. 3 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Offset Error OSE 1023
Gain Error GE
1022 1021
1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2)
code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve
2 1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal)
Offset Error OSE
Figure 15. ADC_0 characteristic and error definitions
4.17.1.1
Input impedance and ADC accuracy
In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Eqn. 4 R S + R F + R L + R SW + R AD -1 V A -------------------------------------------------------------------------- -- LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF Current Limiter RL Channel Selection RSW1
Sampling
RAD
VA
CF
CP1
CP2
CS
RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance
Figure 16. Input equivalent circuit (precise channels)
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF Current Limiter RL Channel Selection RSW1 Extended Switch RSW2
Sampling
RAD
VA
CF
CP1
CP3
CP2
CS
RS RF CF RL RSW RAD CP CS
Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance
Figure 17. Input equivalent circuit (extended channels) MPC5646C Microcontroller Data Sheet, Rev. 3 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close).
VCS VA VA2
Voltage Transient on CS V 1 CS to SCK Delay2 After SCK Delay3 SCK Duty Cycle Slave Setup Time (SS active to SCK setup time) Slave Hold Time (SS active to SCK hold time) Slave Access Time (SS active to SOUT valid)4 Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) CSx to PCSS time PCSS to PCSx time
tSCK
Refer note1 — 15 7 15 0.4 tSCK 5 10 — — 0 0
ns ns ns ns ns ns ns ns ns ns ns ns
tCSC tASC
tCSC tASC tSDC tSUSS tHSS tA tDIS tPCSC tPASC
MPC5646C Microcontroller Data Sheet, Rev. 3 88 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Table 49. DSPI timing (continued)
Spec
Characteristic
Symbol Min Max
Unit
9
Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)5 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)5 Master (MTFE = 1, CPHA = 1) Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
tSUI 36 5 36 36 tHI 0 4 0 0 tSUO — — — — tHO 06 9.5 07 08 12 37 12 12 — — — — ns ns ns ns ns ns ns ns — — — — ns ns ns ns — — — — ns ns ns ns
10
11
12
1 2 3 4 5 6 7 8
This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this table. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For JPC5604B, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > tCSC . The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For JPC5604B, the spec value of tASC will be attained only if TDSPI x PASC x ASC > tASC. The parameter value is obtained from tSUSS and tSUO for slave. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is 2 ns. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is 2 n. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is 2 ns.
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 89
2 CSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Note: Numbers shown reference Table 49.
Figure 25. DSPI classic SPI timing–master, CPHA = 0
CSx
SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Note: Numbers shown reference Table 49.
Figure 26. DSPI classic SPI timing–master, CPHA = 1
MPC5646C Microcontroller Data Sheet, Rev. 3 90 Preliminary—Subject to Change Without Notice Freescale Semiconductor
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Note: Numbers shown reference Table 49.
Figure 27. DSPI classic SPI timing–slave, CPHA = 0
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 91
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 49.
Figure 28. DSPI classic SPI timing–slave, CPHA = 1
MPC5646C Microcontroller Data Sheet, Rev. 3 92 Preliminary—Subject to Change Without Notice Freescale Semiconductor
3 CSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Note: Numbers shown reference Table 49.
Figure 29. DSPI modified transfer format timing–master, CPHA = 0
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 93
CSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Note: Numbers shown reference Table 49.
Figure 30. DSPI modified transfer format timing–master, CPHA = 1
MPC5646C Microcontroller Data Sheet, Rev. 3 94 Preliminary—Subject to Change Without Notice Freescale Semiconductor
SS
2 1
3
SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Note: Numbers shown reference Table 49.
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Note: Numbers shown reference Table 49.
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1
MPC5646C Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 95
7 PCSS CSx
8
Note: Numbers shown reference Table 49.
Figure 33. DSPI PCS strobe (PCSS) timing
4.19.3
Nexus characteristics
Table 50. Nexus debug port timing1
Spec 1 2 3 Characteristic MCKO Cycle Time2 MCKO Duty Cycle MCKO Low to MDO, MSEO, EVTO Data Valid3 EVTI Pulse Width EVTO Pulse Width TCK Cycle Time4 TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid Symbol tMCYC tMDC tMDOV Min 16.3 40 –0.1 Max — 60 0.25 Unit ns % tMCYC
4 5 6 7 8 9 10
1
tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV
4.0 1 40 40 8 5 0
—
tTCYC tMCYC
— 60 — — 25
ns % ns ns ns
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 4.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11. 2 MCKO can run up to 1/2 of full system frequency. It can also run at system frequency when it is
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