MPC5668x
MPC5668x Microcontroller Data Sheet
MPC5668x features: • 32-bit CPU core complex (e200z650) – Compliant with Power Architecture embedded category – 32 KB unified cache with line locking and eight-entry store buffer – Execution speed static to 116 MHz • 32-bit I/O processor (e200z0) – Execution speed static to 1/2 CPU core speed (58 MHz) • 2 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 512 KB + 80 KB (592 KB) on-chip ECC SRAM (MPC5668G) • 128 KB on-chip ECC SRAM (MPC5668E) • 16-entry Memory Protection Unit (MPC5668E only) • Direct memory access controller – 16-channel on MPC5668G – 32-channel on MPC5668E • Fast ethernet controller – Supports 10-Mbps and 100-Mbps IEEE 802.3 MII, 10-Mbps 7-wire interface – IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) • Media Local Bus (MLB) interface (MPC5668G only) – Supports 16 logical channels, max speed 1024 Fs • Interrupt controller (INTC) supports 316 external interrupt vectors (22 are reserved) • System clocks – Frequency-modulated phase-locked loop (FMPLL) – 4 – 40 MHz crystal oscillator (XTAL) – 32 kHz crystal oscillator (XTAL) – Dedicated 16 MHz and 128 kHz internal RC oscillators • Analog to Digital Converter (ADC) module – 10-bit A/D resolution – 32 external channels – 36 internal channels (MPC5668G) – 64 internal channels (MPC5668E)
MAPBGA–208 17 mm x 17 mm MAPBGA–256 17 mm x 17 mm
• Cross-Triggering Unit (MPC5668E only) – Internal conversion triggering for ADC – Triggerable by internal timers or eMIOS200 • Deserial Serial Peripheral Interface (DSPI) – Four individual DSPI modules – Full duplex, synchronous transfers – Master or slave operation • Inter-IC communication (I2C) interface – Four individual I2C modules – Multi-master operation • Serial Communication Interface (eSCI) module – Two-channel DMA interface – Configurable as LIN bus master • eMIOS200 timed input/output – 24 channels, 16-bit timers (MPC5668G) – 32 channels, 16-bit timers (MPC5668E) • Controller Area Network (FlexCAN) module – Compliant with CAN protocol specification, Version 2.0B active – 64 mailboxes, each configurable as transmit or receive • Dual-channel FlexRay controller – Full implementation of FlexRay Protocol Specification 2.1, RevA – 128 message buffers • JTAG controller (MPC5668G only) – Compliant with the IEEE 1149.1-2001 • Nexus Development Interface (NDI) – Available in 256 MAPBGA package only – Compliant with IEEE-ISTO 5001-2003 – Nexus class 3 development support on e200z650 – Nexus class 2+ development support on e200z0 • Internal voltage regulator allows operation from single 3.3 V or 5 V supply
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5668X Rev. 3, 9/2009
Table of Contents
1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 MPC5668x Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 208-ball MAPBGA Pin Assignments . . . . . . . . . . . . . . . .6 3.2 256-ball MAPBGA Pin Assignments . . . . . . . . . . . . . . . .7 3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8 3.3.1 Power and Ground Supply Summary . . . . . . . .25 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .27 4.2.1 General Notes for Specifications at Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .28 4.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.4 VRC Electrical Specifications . . . . . . . . . . . . . . . . . . . .30 4.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30 4.6 Operating Current Specifications . . . . . . . . . . . . . .32 4.7 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .34 4.7.1 I/O Pad VDD33 Current Specifications . . . . . . . .35 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . Oscillators Electrical Characteristics . . . . . . . . . . . . . . FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . ADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . Flash Memory Electrical Characteristics . . . . . . . . . . . Pad AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.1 Reset and Boot Configuration Pins . . . . . . . . . 4.14.2 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . . 4.14.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . 4.14.4 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 4.14.5 Enhanced Modular I/O Subsystem (eMIOS) . . 4.14.6 Deserial Serial Peripheral Interface (DSPI) . . . 4.14.7 MLB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14.8 Fast Ethernet Interface . . . . . . . . . . . . . . . . . . Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 38 39 39 40 43 43 43 44 47 49 50 55 57 61 61 65
4
5 6
Table 1. MPC5668G/MPC5668E Comparison
Feature Package RAM with ECC MPU DMA Ethernet (FEC) MediaLB (MLB-DIM) FlexRay ADC (10-bit) Total Timer I/O (eMIOS200) Cross Trigger Unit (CTU) SCI (eSCI) SPI (DSPI) CAN (FlexCAN) I2C Nexus3 Debug (e200Z6) Nexus2+ Debug (e200Z0) MPC5668G 208 MAPBGA 256 MAPBGA MPC5668E 208 MAPBGA 256 MAPBGA
592 KB No 16-channel Yes Yes Yes (128 Message Buffers) 36 internal channels Supports 32 external channels 24 channels, 16-bit No 6 4 6 4 Supported on 256BGA — emulation package
128 KB 16 entry 32-channel No No No 64 internal channels Supports 32 external channels 32 channels, 16-bit Yes 12 4 5 4 Supported on 256BGA — emulation package
MPC5668x Microcontroller Data Sheet, Rev. 3 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Ordering Information
1
1.1
Ordering Information
Orderable Parts
S PC 5668G F 0A V MG R
Qualification status Core code Device number Fabrication Site Revision Temperature range Package identifier Tape and reel status
Qualification Status P = Prototype M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Core Code PC = Power Architecture
Fabrication Site F = Freescale Temperature Range V = –40 °C to 105 °C
Package Identifier MG = 208 MAPBGA Pb-free MJ = 256 MAPBGA Pb-free Tape and Reel Status R = Tape and reel (blank) = Trays
Note: Not all options are available on all devices. Refer to Table 1.
Table 1 shows the orderable part numbers for the MPC5668x. Table 1. Orderable Part Numbers
Freescale Part Number1 SPC5668GF0AVMG SPC5668GF0AVMJ4
1
Speed (MHz) Package Description MPC5668G 208 MAPBGA package Lead-free (PbFree) MPC5668G 256 MAPBGA package Lead-free (PbFree) Max3 (fMAX) 116 116
Operating Temperature2 Min (TL) –40 °C –40 °C Max (TH) 105 °C 105 °C
All packaged devices are PPC5668x, rather than MPC5668x or SPC5668x, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. 2 The lowest ambient operating temperature (TA) is referenced by TL; the highest ambient operating temperature is referenced by TH. 3 Maximum speed is the maximum frequency allowed including frequency modulation (FM). 4 The 256 MAPBGA package for the MPC5668x is not intended for full production qualification, and is supplied for development use only.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
MPC5668x Block Diagrams
2
MPC5668x Block Diagrams
DEBUG JTAG NDI Nexus3(Z6) NDI Nexus2+(Z0)
Figure 1 shows a top-level block diagram of the MPC5668G device.
MPC5668G
MASTERS e200z650 Core VLE MMU(32TLB)
32 kHz XTAL
4–40 MHz XTAL
16 MHz IRC
VREG Controller
128 kHz IRC
FMPLL
RTC/API SWT STM
Semaphores e200z0 Core VLE FPU/SPE 32K Cache 4/8 Way 16ChDMA Mux FEC MLB-DIM FlexRay
INTC PIT BAM SIU
SPP Crossbar Switch (XBAR)
AIPS(0) Bridge B 6 x eSCI 36 x ADC 24 x eMIOS 2 x I2C 2 x DSPI 6 x FlexCAN
AIPS(1) Bridge A 2 x DSPI 2 x I2C 512 KB 80 KB SRAM (ECC) ECSM LEGEND
I2 C INTC JTAG MLB-DIM NDI PIT RTC SIU STM SWT VREG
2 MB Flash (ECC) ECSM
SRAM (ECC) Standby RAM ECSM
ADC – Analog to Digital Converter BAM – Boot Assist Module DSPI – Serial Peripherals Interface ECC – Error Correction Code ECSM – Error Correction Status Module eMIOS – Timed Input Output eDMA – Enhanced Direct Memory Access controller eSCI – Serial Communications Interface FEC – Fast Ethernet Controller FlexCAN – Controller Area Network controller FlexRay™ – FlexRay Bus Controller FMPLL – Frequency Modulated Phase Locked Loop
– Inter IC Controller – Interrupt Controller – Joint Test Action Group interface – Media Local Bus Device Interface Module – Nexus Debug Interface – Periodic Interrupt Timer – Real Time Clock – System Integration – System Timer Module – Software Watchdog Timer – Voltage Regulator
Figure 1. MPC5668G Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. 3 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
MPC5668x Block Diagrams
Figure 2 shows a top level block diagram for the MPC5668E device.
DEBUG JTAG NDI Nexus3(Z6) NDI Nexus2+(Z0)
MPC5668E
MASTERS e200z650 Core VLE MMU(32TLB)
32 kHz XTAL
4–40 MHz XTAL
16 MHz IRC
VREG Controller
128 kHz IRC
FMPLL
RTC/API SWT STM
e200z0 Core VLE
FPU/SPE 32K Cache 4/8 Way
Semaphores 32ChDMA Mux
INTC PIT BAM SIU
SPP Crossbar Switch (XBAR) Memory Protection Unit (MPU)
AIPS(0) Bridge B 64 x ADC 2 MB Flash (ECC) ECSM CTU LEGEND
ADC BAM CTU DSPI ECC ECSM eDMA eMIOS200 eSCI FlexCAN FMPLL – Analog to Digital Converter – Boot Assist Module – Cross Triggering Unit – Serial Peripherals Interface controller – Error Correction Code – Error Correction Status Module – Enhanced Direct Memory Access controller – Timed Input Output – Serial Communications Interface – Controller Area Network controller – Frequency Modulated Phase Locked Loop
AIPS(1) Bridge A 4 x eSCI 2 x DSPI 2 x I 2C 128 KB SRAM (ECC) Standby RAM ECSM
5 x FlexCAN 2 x DSPI 2 x I2C
32 x eMIOS 8 x eSCI
I2 C INTC JTAG MPU NDI PIT RTC SIU STM SWT VREG
– Inter IC Controller – Interrupt Controller – Joint Test Action Group interface – Memory Protection Unit – Nexus Debug Interface – Periodic Interrupt Timer – Real Time Clock – System Integration – System Timer Module – Software Watchdog Timer – Voltage Regulator
Figure 2. MPC5668E Block Diagram
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
3
3.1
Pin Assignments
208-ball MAPBGA Pin Assignments
1 A B C D E F G H J K L M N P R T VSS PD2 PD3 PD5 PD7 PD9 PD11 PD13 PF1 PK1 PK0 PF4 PF6 PF8 PF10 VSS 1 2 PD0 PD1 PD4 PD6 PD8 PD10 PD12 PF0 PF2 PK2 PE7 PE6 PF3 PF5 PF7 PF9 2 3 PG1 PG0 PD14 PD15 PE0 PE3 PE4 PE5 TDI 4 PC12 PC11 PC14 VDD PE1 PE2 VSS VDD PE8 5 PC9 PC10 PC13 PC15 6 PC7 PC8 PC5 VDDE1 7 PC2 PC3 PC6 VSS 8 PB13 PB14 PC1 PC4 9 PB10 PB11 PB15 PC0 10 PB8 VRC PB12 VDD 11 12 13 14 15 16 VSS VRH VRL PA14 PA15 PA2 PA4 PA6 PG11 PG12 PG13 PG14 PG15 PH1 PH2 VSS 16 A B C D E F G H J K L M N P R T
Figure 3 shows the 208-ball MAPBGA pin assignments.
RESET VDDSYN XTAL EXTAL VSSSYN VRCCTL PB6 PB7 PB9 PB4 PB5 PB2 PB3 PA10 PA11 PA13 VDD VRCSEL VDDE3 VDD VDD33 TEST PJ10 PJ11 PJ12 PJ13 12 VSS PF15 PJ14 PJ15 13 PB0 PB1 PA12 PA9 PA8 PA7
PG2
VDDA VSSA PA0 PA1 PA3 PA5 PG6 PG7 PG8 PG9 PG10 PH3 PH4 PH6
PH7
208 MAPBGA Ball Map
(as viewed from top through the package)
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
PG3 PG4 PG5 PF13 PF12 PF14 PH5 PH0 14
JCOMP VDDEMLB TMS TDO PE10 TCK PF11 PK3 3 VDDE2 PE9 PE11 PE12 PK4 PK5 4 VDD PE13 PK6 PK7 5
Note: This ballmap is preliminary and should not be used for board design.
PE15 PK10 PK8 PK9 6 PE14 PH8 PJ0 PJ1 7 PH9 PH10 PJ2 PJ3 8 PH11 PH12 PJ4 PJ5 9 VDDE4 PH13 PJ6 PJ7 10 PH15 PH14 PJ9 PJ8 11
15
Figure 3. MPC5668x 208-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. 3 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
3.2
256-ball MAPBGA Pin Assignments
256 MAPBGA Ball Map
(as viewed from top through the package)
1 A B C D E F G H J K L M N P R T VSS PD2 PD3 PD5 PD7 PD9 PD11 PD13 PF1 PK1 PK0 PF4 PF6 PF8 PF10 VSS 1 2 PD0 PD1 PD4 PD6 PD8 PD10 PD12 PF0 PF2 PK2 PE7 PE6 PF3 PF5 PF7 PF9 2 3 PG1 PG0 PD14 PD15 PE0 PE3 PE4 PE5 TDI 4 PC12 PC11 PC14 VDD PE1 PE2 VSS VDD PE8 5 PC9 PC10 PC13 PC15 6 PC7 PC8 PC5 VDDE1 7 PC2 PC3 PC6 VSS VSS VSS VSS VSS VSS VSS VDDENEX 8 PB13 PB14 PC1 PC4 VSS VSS VSS VSS VSS VSS VSS 9 PB10 PB11 PB15 PC0 VSS VSS VSS VSS
VSS
Figure 4 shows the 256-ball MAPBGA pin assignments.
10 PB8 VRC PB12 VDD VSS VSS VSS VSS VSS
11
12
13
14
15
16 VSS VRH VRL PA14 PA15 PA2 PA4 PA6 PG11 PG12 PG13 PG14 PG15 PH1 PH2 VSS 16 A B C D E F G H J K L M N P R T
RESET VDDSYN XTAL VRCCTL PB6 PB7 VSS VSS VSS VSS VSS PB9 PB4 PB5 VSS VSS VSS VSS VSS VSS VSS EVTO PJ10 PJ11 PJ12 PJ13 12 PB2 PB3 PA10 PA11 PA13 VDD VRCSEL VDDE3 VDD VDD33 TEST VSS PF15 PJ14 PJ15 13
EXTAL VSSSYN PB0 PB1 PA12 PA9 PA8 PA7
PG2
VDDA VSSA PA0 PA1 PA3 PA5 PG6 PG7 PG8 PG9 PG10 PH3 PH4 PH6
PH7
MDO0 VDDENEX MDO1 MDO2 VSS VSS
MDO3 MDO4 MDO6 MDO5 VSS VSS
PG3 PG4 PG5 PF13 PF12 PF14 PH5 PH0 14
JCOMP VDDEMLB MDO7 TMS TDO PE10 TCK PF11 PK3 3 VDDE2 MDO8 PE9 PE11 PE12 PK4 PK5 4
VSS VSS
VSS VDDENEX VSS VSS EVTI PH15
MDO9 MDO10 MDO11 MSEO1 MSEO0 MCKO VDD PE13 PK6 PK7 5 PE15 PE14 PH9 PH11 VDDE4
Note: This ballmap is PH12 PH13 and preliminary PK10 PH8 PH10 PH14 should not be used for board design.
PK8 PK9 6 PJ0 PJ1 7 PJ2 PJ4 PJ6 PJ9 PJ8 11 PJ3 8 PJ7 10
PJ5 9
15
Figure 4. MPC5668x 256-ball MAPBGA (full diagram)
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
3.3
Pin Muxing and Reset States
Table 2 shows the signals properties for each pin on MPC5668x. For all port pins that have an associated SIU_PCRn register to control pin properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5). When an alternate function is not implemented for a value of SIU_PCRn[PA], a dash is shown in the Description column and the respective value in the PA bitfield is reserved.
GPIO Supported 2 (PCR) Functions Num3 PA[0] AN[0] 0 PA4 00 01 10 11 Description Port A GPI ADC Analog Input — — GPIO Function 1 Functions 2 and 3 not implemented
Figure 5. Supported Functions Example
Table 2. MPC5668x Signal Properties
GPIO Supported 4 2 (PCR) PA Functions 3 Num Status Description I/O Type Voltage Pad Type5 During Reset6 After Reset7 Package Pin Locations 208 BGA 256 BGA
Pin Name1
Port A (16) PA0 PA[0] AN[0] 0 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — I I — — I I — — I I — — I I — — I I — — I I — — VDDA IHA — — D15 D15
PA1
PA[1] AN[1]
1
VDDA
IHA
—
—
E15
E15
PA2
PA[2] AN[2]
2
VDDA
IHA
—
—
F16
F16
PA3
PA[3] AN[3]
3
VDDA
IHA
—
—
F15
F15
PA4
PA[4] AN[4]
4
VDDA
IHA
—
—
G16
G16
PA5
PA[5] AN[5]
5
VDDA
IHA
—
—
G15
G15
MPC5668x Microcontroller Data Sheet, Rev. 3 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PA[6] AN[6] 6 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA H16 256 BGA H16
Pin Name1
PA6
Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input External 32 kHz Crystal In — Port A GPI ADC Analog Input External 32 kHz Crystal Out —
I I — — I I — — I I — — I I — — I I — — I I — — I I — — I I — — I I I — I I O —
VDDA
IHA
PA7
PA[7] AN[7]
7
VDDA
IHA
—
—
G14
G14
PA8
PA[8] AN[8]
8
VDDA
IHA
—
—
F14
F14
PA9
PA[9] AN[9]
9
VDDA
IHA
—
—
E14
E14
PA10
PA[10] AN[10]
10
VDDA
IHA
—
—
D13
D13
PA11
PA[11] AN[11]
11
VDDA
IHA
—
—
E13
E13
PA12
PA[12] AN[12]
12
VDDA
IHA
—
—
D14
D14
PA13
PA[13] AN[13]
13
VDDA
IHA
—
—
F13
F13
PA14
PA[14] AN[14] EXTAL32 PA[15] AN[15] XTAL32
14
VDDA
IHA
—
—
D16
D16
PA15
15
VDDA
IHA
—
—
E16
E16
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 Status Description I/O Type Voltage Pad Type5 During Reset6 After Reset7 Package Pin Locations 208 BGA 256 BGA
Pin Name1
Port B (16) PB0 PB[0] 16 AN[16]/ANW 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Port B GPIO ADC Analog Input/Mux In — — Port B GPIO ADC Analog Input/Mux In — — Port B GPIO ADC Analog Input/Mux In — — Port B GPIO ADC Analog Input/Mux In — — Port B GPIO ADC Analog Input — — Port B GPIO ADC Analog Input — — Port B GPIO ADC Analog Input — — Port B GPIO ADC Analog Input — — Port B GPIO ADC Analog Input DSPI_A Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_A Peripheral Chip Select — I/O I — — I/O I — — I/O I — — I/O I — — I/O I — — I/O I — — I/O I — — I/O I — — I/O I O — I/O I O — VDDE1 SHA — — B14 B14
PB1
PB[1] AN[17]/ANX
17
VDDE1
SHA
—
—
C14
C14
PB2
PB[2] AN[18]/ANY
18
VDDE1
SHA
—
—
B13
B13
PB3
PB[3] AN[19]/ANZ
19
VDDE1
SHA
—
—
C13
C13
PB4
PB[4] AN[20]
20
VDDE1
SHA
—
—
C12
C12
PB5
PB[5] AN[21]
21
VDDE1
SHA
—
—
D12
D12
PB6
PB[6] AN[22]
22
VDDE1
SHA
—
—
C11
C11
PB7
PB[7] AN[23]
23
VDDE1
SHA
—
—
D11
D11
PB8
PB[8] AN[24] PCS_A[2] PB[9] AN[25] PCS_A[3]
24
VDDE1
SHA
—
—
A10
A10
PB9
25
VDDE1
SHA
—
—
B12
B12
MPC5668x Microcontroller Data Sheet, Rev. 3 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PB[10] AN[26] PCS_B[4] PB[11] AN[27] PCS_B[5] PB[12] AN[28] PCS_C[1] PB[13] AN[29] PCS_C[2] PB[14] AN[30] PCS_D[3] PB[15] AN[31] PCS_D[4] 26 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA A9 256 BGA A9
Pin Name1
PB10
Port B GPIO ADC Analog Input DSPI_B Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_B Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_C Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_C Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_D Peripheral Chip Select — Port B GPIO ADC Analog Input DSPI_D Peripheral Chip Select — Port C (16)
I/O I O — I/O I O — I/O I O — I/O I O — I/O I O — I/O I O —
VDDE1
SHA
PB11
27
VDDE1
SHA
—
—
B9
B9
PB12
28
VDDE1
SHA
—
—
C10
C10
PB13
29
VDDE1
SHA
—
—
A8
A8
PB14
30
VDDE1
SHA
—
—
B8
B8
PB15
31
VDDE1
SHA
—
—
C9
C9
PC0
PC[0] AN[32]
32
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Port C GPIO ADC Analog Input — — Port C GPIO ADC Analog Input — — Port C GPIO ADC Analog Input Nexus Event In — Port C GPIO ADC Analog Input Nexus Event Out —
I/O I — — I/O I — — I/O I I — I/O I O —
VDDE1
SHA
—
—
D9
D9
PC1
PC[1] AN[33]
33
VDDE1
SHA
—
—
C8
C8
PC2
PC[2] AN[34] EVTI PC[3] AN[35] EVTO
34
VDDE1
SHA
—
—
A7
A7
PC3
35
VDDE1
SHA
—
—
B7
B7
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PC[4] AN[36] 36 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA D8 256 BGA D8
Pin Name1
PC4
Port C GPIO ADC Analog Input — — Port C GPIO ADC Analog Input Z6 Core Non-Maskable Interrupt — Port C GPIO ADC Analog Input Z0 Core Non-Maskable Interrupt — Port C GPIO ADC Analog Input FlexRay Debug — Port C GPIO ADC Analog Input FlexRay Debug — Port C GPIO ADC Analog Input FlexRay Debug — Port C GPIO ADC Analog Input FlexRay Debug — Port C GPIO ADC Analog Input — I2C_C Serial Clock Port C GPIO ADC Analog Input — I2C_C Serial Data Port C GPIO ADC Analog Input — ADC Ext. Mux Address Select Port C GPIO ADC Analog Input — ADC Ext. Mux Address Select
I/O I — — I/O I I — I/O I I — I/O I O — I/O I O — I/O I O — I/O I O — I/O I — I/O I/O I — I/O I/O I — O I/O I — O
VDDE1
SHA
PC5
PC[5] AN[37] Z6NMI PC[6] AN[38] Z0NMI PC[7] AN[39] FR_DBG3 PC[8] AN[40] FR_DBG2 PC[9] AN[41] FR_DBG1 PC[10] AN[42] FR_DBG0 PC[11] AN[43] — SCL_C PC[12] AN[44] — SDA_C PC[13] AN[45] — MA[0] PC[14] AN[46] — MA[1]
37
VDDE1
SHA
—
—
C6
C6
PC6
38
VDDE1
SHA
—
—
C7
C7
PC7
39
VDDE1
SHA
—
—
A6
A6
PC8
40
VDDE1
SHA
—
—
B6
B6
PC9
41
VDDE1
SHA
—
—
A5
A5
PC10
42
VDDE1
SHA
—
—
B5
B5
PC11
43
VDDE1
SHA
—
—
B4
B4
PC12
44
VDDE1
SHA
—
—
A4
A4
PC13
45
VDDE1
SHA
—
—
C5
C5
PC14
46
VDDE1
SHA
—
—
C4
C4
MPC5668x Microcontroller Data Sheet, Rev. 3 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PC[15] AN[47] — MA[2] 47 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA D5 256 BGA D5
Pin Name1
PC15
Port C GPIO ADC Analog Input — ADC Ext. Mux Address Select Port D (16)
I/O I — O
VDDE1
SHA
PD0
PD[0] CNTX_A
48
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Port D GPIO FlexCAN_A Transmit — — Port D GPIO FlexCAN_A Receive — — Port D GPIO FlexCAN_B Transmit — — Port D GPIO FlexCAN_B Receive — — Port D GPIO FlexCAN_C Transmit — — Port D GPIO FlexCAN_C Receive — — Port D GPIO FlexCAN_D Transmit SCI_K Transmit I2C_B Serial Clock Port D GPIO FlexCAN_D Receive SCI_K Receive I2C_B Serial Data Port D GPIO FlexCAN_E Transmit SCI_L Transmit I2C_C Serial Clock
I/O O — — I/O I — — I/O O — — I/O I — — I/O O — — I/O I — — I/O O O I/O I/O I I I/O I/O O O I/O
VDDE2
SH
—
—
A2
A2
PD1
PD[1] CNRX_A
49
VDDE2
SH
—
—
B2
B2
PD2
PD[2] CNTX_B
50
VDDE2
SH
—
—
B1
B1
PD3
PD[3] CNRX_B
51
VDDE2
SH
—
—
C1
C1
PD4
PD[4] CNTX_C
52
VDDE2
SH
—
—
C2
C2
PD5
PD[5] CNRX_C
53
VDDE2
SH
—
—
D1
D1
PD6
PD[6] CNTX_D TXD_K SCL_B PD[7] CNRX_D RXD_K SDA_B PD[8] CNTX_E TXD_L SCL_C
54
VDDE2
SH
—
—
D2
D2
PD7
55
VDDE2
SH
—
—
E1
E1
PD8
56
VDDE2
SH
—
—
E2
E2
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PD[9] CNRX_E RXD_L SDA_C PD[10] CNTX_F TXD_M SCL_D PD[11] CNRX_F RXD_M SDA_D PD[12] TXD_A 57 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA F1 256 BGA F1
Pin Name1
PD9
Port D GPIO FlexCAN_E Receive SCI_L Receive I2C_C Serial Data Port D GPIO FlexCAN_F Transmit SCI_M Transmit I2C_D Serial Clock Port D GPIO FlexCAN_F Receive SCI_M Receive I2C_D Serial Data Port D GPIO eSCI_A Transmit — — Port D GPIO eSCI_A Receive — — Port D GPIO eSCI_B Transmit — — Port D GPIO eSCI_B Receive — — Port E (16)
I/O I I I/O I/O O O I/O I/O I I I/O I/O O — — I/O I — — I/O O — — I/O I — —
VDDE2
SH
PD10
58
VDDE2
SH
—
—
F2
F2
PD11
59
VDDE2
SH
—
—
G1
G1
PD12
60
VDDE2
SH
—
—
G2
G2
PD13
PD[13] RXD_A
61
VDDE2
SH
—
—
H1
H1
PD14
PD[14] TXD_B
62
VDDE2
SH
—
—
C3
C3
PD15
PD[15] RXD_B
63
VDDE2
SH
—
—
D3
D3
PE0
PE[0] TXD_C eMIOS[31] PE[1] RXD_C eMIOS[30] PE[2] TXD_D eMIOS[29]
64
00 01 10 11 00 01 10 11 00 01 10 11
Port E GPIO eSCI_C Transmit eMIOS Channel — Port E GPIO eSCI_C Receive eMIOS Channel — Port E GPIO eSCI_D Transmit eMIOS Channel —
I/O O I/O — I/O I I/O I/O O I/O
VDDE2
SH
—
—
E3
E3
PE1
65
VDDE2
SH
—
—
E4
E4
PE2
66
VDDE2
SH
—
—
F4
F4
MPC5668x Microcontroller Data Sheet, Rev. 3 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PE[3] RXD_D eMIOS[28] PE[4] TXD_E eMIOS[27] PE[5] RXD_E eMIOS[26] PE[6] TXD_F eMIOS[25] PE[7] RXD_F eMIOS[24] PE[8] TXD_G PCS_A[1] PE[9] RXD_G PCS_A[4] PE[10] TXD_H PCS_B[3] PE[11] RXD_H PCS_B[2] PE[12] TXD_J PCS_C[5] PE[13] RXD_J PCS_C[3] 67 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA F3 256 BGA F3
Pin Name1
PE3
Port E GPIO eSCI_D Receive eMIOS Channel — Port E GPIO eSCI_E Transmit eMIOS Channel — Port E GPIO eSCI_E Receive eMIOS Channel — Port E GPIO eSCI_F Transmit eMIOS Channel — Port E GPIO eSCI_F Receive eMIOS Channel — Port E GPIO eSCI_G Transmit DSPI_A Peripheral Chip Select — Port E GPIO eSCI_G Receive DSPI_A Peripheral Chip Select — Port E GPIO eSCI_H Transmit DSPI_B Peripheral Chip Select — Port E GPIO eSCI_H Receive DSPI_B Peripheral Chip Select — Port E GPIO eSCI_J Transmit DSPI_C Peripheral Chip Select — Port E GPIO eSCI_J Receive DSPI_C Peripheral Chip Select —
I/O I I/O I/O O I/O I/O I I/O I/O O I/O I/O I I/O I/O O O I/O I O I/O O O I/O I O I/O O O I/O I O
VDDE2
SH
PE4
68
VDDE2
SH
—
—
G3
G3
PE5
69
VDDE2
SH
—
—
H3
H3
PE6
70
VDDE2
SH
—
—
M2
M2
PE7
71
VDDE2
SH
—
—
L2
L2
PE8
72
VDDE2
SH
—
—
J4
J4
PE9
73
VDDE2
SH
—
—
M4
M4
PE10
74
VDDE2
SH
—
—
N3
N3
PE11
75
VDDE2
SH
—
—
N4
N4
PE12
76
VDDE2
SH
—
—
P4
P4
PE13
77
VDDE2
SH
—
—
P5
P5
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PE[14] SCL_A PCS_D[2] PE[15] SDA_A PCS_D[5] 78 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA N7 256 BGA N7
Pin Name1
PE14
Port E GPIO I2C_A Serial Clock DSPI_D Peripheral Chip Select — Port E GPIO I2C_A Serial Data DSPI_D Peripheral Chip Select — Port F (16)
I/O I/O O — I/O I/O O —
VDDE2
SH
PE15
79
VDDE2
SH
—
—
N6
N6
PF0
PF[0] SCK_A
80
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Port F GPIO DSPI_A Serial Clock — — Port F GPIO DSPI_A Serial Data Out — — Port F GPIO DSPI_A Serial Data In — — Port F GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port F GPIO DSPI_B Serial Clock DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port F GPIO DSPI_B Serial Data Out DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port F GPIO DSPI_B Serial Data In DSPI_A Peripheral Chip Select DSPI_C Peripheral Chip Select Port F GPIO DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select DSPI_D Peripheral Chip Select
I/O I/O — — I/O O — — I/O I — — I/O I/O O O I/O I/O O O I/O O O O I/O I O O I/O I/O O O
VDDE2
MH
—
—
H2
H2
PF1
PF[1] SOUT_A
81
VDDE2
MH
—
—
J1
J1
PF2
PF[2] SIN_A
82
VDDE2
SH
—
—
J2
J2
PF3
PF[3] PCS_A[0] PCS_B[5] PCS_C[4] PF[4] SCK_B PCS_A[1] PCS_C[2] PF[5] SOUT_B PCS_A[2] PCS_C[3] PF[6] SIN_B PCS_A[3] PCS_C[5] PF[7] PCS_B[0] PCS_C[5] PCS_D[4]
83
VDDE2
SH
—
—
N2
N2
PF4
84
VDDE2
MH
—
—
M1
M1
PF5
85
VDDE2
MH
—
—
P2
P2
PF6
86
VDDE2
SH
—
—
N1
N1
PF7
87
VDDE2
SH
—
—
R2
R2
MPC5668x Microcontroller Data Sheet, Rev. 3 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PF[8] SCK_C 88 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA P1 256 BGA P1
Pin Name1
PF8
Port F GPIO DSPI_C Serial Clock — — Port F GPIO DSPI_C Serial Data Out — — Port F GPIO DSPI_C Serial Data In — — Port F GPIO DSPI_C Peripheral Chip Select DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select Port F GPIO DSPI_D Serial Clock — — Port F GPIO DSPI_D Serial Data Out — — Port F GPIO DSPI_D Serial Data In — — Port F GPIO DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select Port G (16)
I/O I/O — — I/O O — — I/O I — — I/O I/O O O I/O I/O — — I/O O — — I/O I — — I/O I/O O O
VDDE2
MH
PF9
PF[9] SOUT_C
89
VDDE2
MH
—
—
T2
T2
PF10
PF[10] SIN_C
90
VDDE2
SH
—
—
R1
R1
PF11
PF[11] PCS_C[0] PCS_D[5] PCS_A[4] PF[12] SCK_D
91
VDDE2
SH
—
—
R3
R3
PF12
92
VDDE3
MH
—
—
N14
N14
PF13
PF[13] SOUT_D
93
VDDE3
MH
—
—
M14
M14
PF14
PF[14] SIN_D
94
VDDE3
SH
—
—
P14
P14
PF15
PF[15] PCS_D[0] PCS_A[5] PCS_B[4]
95
VDDE3
SH
—
—
P13
P13
PG0
PG[0] PCS_A[4] PCS_B[3] AN[48] PG[1] PCS_A[5] PCS_B[4] AN[49]
96
00 01 10 11 00 01 10 11
Port G GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select ADC Analog Input Port G GPIO DSPI_A Peripheral Chip Select DSPI_B Peripheral Chip Select ADC Analog Input
I/O O O I I/O O O I
VDDE2
SHA
—
—
B3
B3
PG1
97
VDDE2
SHA
—
—
A3
A3
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PG[2] PCS_D[1] SCL_C AN[50] PG[3] PCS_D[2] SDA_C AN[51] PG[4] PCS_D[3] SCL_B AN[52] PG[5] PCS_D[4] SDA_B AN[53] PG[6] PCS_C[1] FEC_MDC AN[54] PG[7] PCS_C[2] FEC_MDIO AN[55] 98 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA H14 256 BGA H14
Pin Name1
PG2
Port G GPIO DSPI_D Peripheral Chip Select I2C_C Serial Clock ADC Analog Input Port G GPIO DSPI_D Peripheral Chip Select I2C_C Serial Data ADC Analog Input Port G GPIO DSPI_D Peripheral Chip Select I2C_B Serial Clock ADC Analog Input Port G GPIO DSPI_D Peripheral Chip Select I2C_C Serial Data ADC Analog Input Port G GPIO DSPI_C Peripheral Chip Select Ethernet Mgmt. Data Clock ADC Analog Input Port G GPIO DSPI_C Peripheral Chip Select Ethernet Mgmt. Data I/O ADC Analog Input Port G GPIO eMIOS Channel Ethernet Transmit Clock ADC Analog Input Port G GPIO eMIOS Channel Ethernet Carrier Sense ADC Analog Input Port G GPIO eMIOS Channel Ethernet Transmit Error ADC Analog Input Port G GPIO eMIOS Channel Ethernet Receive Clock ADC Analog Input Port G GPIO eMIOS Channel Ethernet Transmit Data ADC Analog Input
I/O O I/O I I/O O I/O I I/O O I/O I I/O O I/O I I/O O O I I/O O I/O I I/O I/O I I I/O I/O I I I/O I/O O I I/O I/O I I I/O I/O O I
VDDE3
SHA
PG3
99
VDDE3
SHA
—
—
J14
J14
PG4
100
VDDE3
SHA
—
—
K14
K14
PG5
101
VDDE3
SHA
—
—
L14
L14
PG6
102
VDDE3
MHA
—
—
H15
H15
PG7
103
VDDE3
MHA
—
—
J15
J15
PG8
PG[8] 104 eMIOS[7] FEC_TX_CLK AN[56] PG[9] eMIOS[6] FEC_CRS AN[57] 105
VDDE3
SHA
—
—
K15
K15
PG9
VDDE3
SHA
—
—
L15
L15
PG10
PG[10] 106 eMIOS[5] FEC_TX_ER AN[58] PG[11] 107 eMIOS[4] FEC_RX_CLK AN[59] PG[12] 108 eMIOS[3] FEC_TXD[0] AN[60]
VDDE3
MHA
—
—
M15
M15
PG11
VDDE3
SHA
—
—
J16
J16
PG12
VDDE3
MHA
—
—
K16
K16
MPC5668x Microcontroller Data Sheet, Rev. 3 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PG[13] 109 eMIOS[2] FEC_TXD[1] AN[61] PG[14] 110 eMIOS[1] FEC_TXD[2] AN[62] PG[15] 111 eMIOS[0] FEC_TXD[3] AN[63] 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA L16 256 BGA L16
Pin Name1
PG13
Port G GPIO eMIOS Channel Ethernet Transmit Data ADC Analog Input Port G GPIO eMIOS Channel Ethernet Transmit Data ADC Analog Input Port G GPIO eMIOS Channel Ethernet Transmit Data ADC Analog Input Port H (16)
I/O I/O O I I/O I/O O I I/O I/O O I
VDDE3
MHA
PG14
VDDE3
MHA
—
—
M16
M16
PG15
VDDE3
MHA
—
—
N16
N16
PH0
PH[0] eMIOS[31] FEC_COL
112
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Port H GPIO eMIOS Channel Ethernet Collision — Port H GPIO eMIOS Channel Ethernet Receive Data Valid — Port H GPIO eMIOS Channel Ethernet Transmit Enable — Port H GPIO eMIOS Channel Ethernet Receive Error — Port H GPIO eMIOS Channel Ethernet Receive Data — Port H GPIO eMIOS Channel Ethernet Receive Data — Port H GPIO eMIOS Channel Ethernet Receive Data —
I/O I/O I — I/O I/O I — I/O I/O O — I/O I/O I — I/O I/O I — I/O I/O I — I/O I/O I —
VDDE3
SH
—
—
T14
T14
PH1
PH[1] 113 eMIOS[30] FEC_RX_DV 114 PH[2] eMIOS[29] FEC_TX_EN PH[3] 115 eMIOS[28] FEC_RX_ER PH[4] 116 eMIOS[27] FEC_RXD[0] PH[5] 117 eMIOS[26] FEC_RXD[1] PH[6] 118 eMIOS[25] FEC_RXD[2]
VDDE3
SH
—
—
P16
P16
PH2
VDDE3
MH
—
—
R16
R16
PH3
VDDE3
SH
—
—
N15
N15
PH4
VDDE3
SH
—
—
P15
P15
PH5
VDDE3
SH
—
—
R14
R14
PH6
VDDE3
SH
—
—
R15
R15
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PH[7] 119 eMIOS[24] FEC_RXD[3] PH[8] eMIOS[23] 120 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA T15 256 BGA T15
Pin Name1
PH7
Port H GPIO eMIOS Channel Ethernet Receive Data — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port H GPIO eMIOS Channel — — Port J (16)
I/O I/O I — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — —
VDDE3
SH
PH8
VDDE4
SH
—
—
P7
P7
PH9
PH[9] eMIOS[22]
121
VDDE4
SH
—
—
N8
N8
PH10
PH[10] eMIOS[21]
122
VDDE4
SH
—
—
P8
P8
PH11
PH[11] eMIOS[20]
123
VDDE4
SH
—
—
N9
N9
PH12
PH[12] eMIOS[19]
124
VDDE4
SH
—
—
P9
P9
PH13
PH[13] eMIOS[18]
125
VDDE4
SH
—
—
P10
P10
PH14
PH[14] eMIOS[17]
126
VDDE4
SH
—
—
P11
P11
PH15
PH[15] eMIOS[16]
127
VDDE4
SH
—
—
N11
N11
PJ0
PJ[0] eMIOS[15] PCS_A[4]
128
00 01 10 11
Port J GPIO eMIOS Channel DSPI_A Peripheral Chip Select —
I/O I/O O —
VDDE4
SH
—
—
R7
R7
MPC5668x Microcontroller Data Sheet, Rev. 3 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PJ[1] eMIOS[14] PCS_A[5] PJ[2] eMIOS[13] PCS_B[1] PJ[3] eMIOS[12] PCS_B[2] PJ[4] eMIOS[11] PCS_C[3] PJ[5] eMIOS[10] PCS_C[4] PJ[6] eMIOS[09] PCS_D[5] PJ[7] eMIOS[08] PCS_D[1] PJ[8] eMIOS[07] 129 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA T7 256 BGA T7
Pin Name1
PJ1
Port J GPIO eMIOS Channel DSPI_A Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_B Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_B Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_C Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_C Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_D Peripheral Chip Select — Port J GPIO eMIOS Channel DSPI_D Peripheral Chip Select — Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — —
I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — —
VDDE4
SH
PJ2
130
VDDE4
SH
—
—
R8
R8
PJ3
131
VDDE4
SH
—
—
T8
T8
PJ4
132
VDDE4
SH
—
—
R9
R9
PJ5
133
VDDE4
SH
—
—
T9
T9
PJ6
134
VDDE4
SH
—
—
R10
R10
PJ7
135
VDDE4
SH
—
—
T10
T10
PJ8
136
VDDE4
SH
—
—
T11
T11
PJ9
PJ[9] eMIOS[06]
137
VDDE4
SH
—
—
R11
R11
PJ10
PJ[10] eMIOS[05]
138
VDDE4
SH
—
—
N12
N12
PJ11
PJ[11] eMIOS[04]
139
VDDE4
SH
—
—
P12
P12
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PJ[12] eMIOS[03] 140 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA R12 256 BGA R12
Pin Name1
PJ12
Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — — Port J GPIO eMIOS Channel — — Port K (11)
I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — —
VDDE4
SH
PJ13
PJ[13] eMIOS[02]
141
VDDE4
SH
—
—
T12
T12
PJ14
PJ[14] eMIOS[01]
142
VDDE4
SH
—
—
R13
R13
PJ15
PJ[15] eMIOS[00]
143
VDDE4
SH
—
—
T13
T13
PK0
PK[0] MLBCLK SCK_B CLKOUT PK[1] MLBSIG SOUT_B PCS_D[4] PK[2] MLBDAT SIN_B PCS_D[5] PK[3] FR_A_RX MA[0] PCS_C[1] PK[4] FR_A_TX MA[1] PCS_C[2]
144
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Port K GPIO Media Local Bus Clock DSPI_B Serial Clock CLKOUT (Test Only) Port K GPIO Media Local Bus Signal DSPI_B Serial Data Out DSPI_D Peripheral Chip Select Port K GPIO Media Local Bus Data DSPI_B Serial Data In DSPI_D Peripheral Chip Select Port K GPIO FlexRay A Receive Data ADC Ext. Mux Address Select DSPI_C Peripheral Chip Select Port K GPIO FlexRay A Transmit Data ADC Ext. Mux Address Select DSPI_C Peripheral Chip Select Port K GPIO FlexRay A Transmit Enable ADC Ext. Mux Address Select DSPI_C Peripheral Chip Select
I/O I I/O O I/O I/O O O I/O I/O I O I/O I O O I/O O O O I/O O O O
VDDEMLB
F
—
—
L1
L1
PK1
145
VDDEMLB
F
—
—
K1
K1
PK2
146
VDDEMLB
F
—
—
K2
K2
PK3
147
VDDE2
SH
—
—
T3
T3
PK4
148
VDDE2
MH
—
—
R4
R4
PK5
PK[5] 149 FR_A_TX_EN MA[2] PCS_C[3]
VDDE2
MH
—
—
T4
T4
MPC5668x Microcontroller Data Sheet, Rev. 3 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 PK[6] FR_B_RX PCS_B[1] PCS_C[4] PK[7] FR_B_TX PCS_B[2] PCS_C[5] 150 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA R5 256 BGA R5
Pin Name1
PK6
Port K GPIO FlexRay B Receive Data DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port K GPIO FlexRay B Transmit Data DSPI_B Peripheral Chip Select DSPI_C Peripheral Chip Select Port K GPIO FlexRay B Transmit Enable DSPI_B Peripheral Chip Select DSPI_A Peripheral Chip Select Port K GPIO CLKOUT (User mode) DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select Boot Configuration Port K GPIO DSPI_B Peripheral Chip Select DSPI_D Peripheral Chip Select DSPI_A Peripheral Chip Select
I/O I O O I/O O O O I/O O O O I/O O O O I I/O O O O
VDDE2
SH
PK7
151
VDDE2
MH
—
—
T5
T5
PK8
PK[8] 152 FR_B_TX_EN PCS_B[3] PCS_A[1] PK[9] CLKOUT PCS_D[1] PCS_A[2] BOOTCFG PK[10] PCS_B[5] PCS_D[2] PCS_A[3] 153
VDDE2
MH
—
—
R6
R6
PK9
VDDE2
MH
BOOT GPIO CFG (Pulldown) — —
T6
T6
PK10
154
VDDE2
SH
P6
P6
Nexus Pins (17) EVTI EVTO EVTI EVTO — — — — — — — — — — — — — — — — — Nexus Event In — Nexus Event Out — Nexus Message Start/End Out — Nexus Message Start/End Out — Nexus Message Clock Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out — Nexus Message Data Out I O O O O O O O O O O O O O O O VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX VDDENEX F F F F F F F F F F F F F F F F — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — M11 M12 M9 M8 M10 E5 F5 G5 H5 H6 J6 J5 K5 L5 M5 M6
MSEO0 MSEO[0] MSEO1 MSEO[1] MCKO MDO0 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MDO8 MDO9 MCKO MDO[0] MDO[1] MDO[2] MDO[3] MDO[4] MDO[5] MDO[6] MDO[7] MDO[8] MDO[9]
MDO10 MDO[10]
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
Table 2. MPC5668x Signal Properties (continued)
GPIO Supported 4 2 (PCR) PA Functions Num3 — Status Description I/O Type Voltage Pad Type5 During Reset6 — After Reset7 — Package Pin Locations 208 BGA — 256 BGA M7
Pin Name1
MDO11 MDO[11]
— Nexus Message Data Out
O
VDDENEX
F
Miscellaneous Pins (9) EXTAL XTAL TDI TDO TMS TCK EXTAL EXTCLK XTAL TDI TDO TMS TCK — — — — — — — — — — Main Crystal Oscillator Input External Clock Input — Main Crystal Oscillator Output — JTAG Test Data Input — JTAG Test Data Output — JTAG Test Mode Select Input — JTAG Test Clock Input — JTAG Compliancy — Test Mode Select — External Reset I I O I O I I I I I/O VDDSYN VDDSYN VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE3 VDDE1 A A SH MH MH SH SH IH MH EXTAL XTAL TDI (Pull Up) TDO (Pull Up8) TMS (Pull Up) TCK (Pull Down)
JCOMP (Pull Down)
A14 A13 J3 M3 L3 P3 K3 M13 A11
A14 A13 J3 M3 L3 P3 K3 M13 A11
JCOMP JCOMP TEST TEST
TEST9 RESET (Pull Up)
RESET RESET
1 2
3 4 5 6
7
8 9
The primary signal name is used as the pin label on the BGA map for identification purposes. Each line in the Signal Name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are designated in the PA field of the System Integration Unit (SIU) PCR registers except where explicitly noted. The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number. The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table indicates that this value for PC is reserved on this pin, and should not be used. The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only, M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad. The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. Pullup is enabled only when JCOMP is negated. Tie to VSS for normal operation.
MPC5668x Microcontroller Data Sheet, Rev. 3 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Pin Assignments
3.3.1
Power and Ground Supply Summary
Table 3. MPC5668x Power/Ground
Package Pin Locations 208 Internal Logic Power External I/O Power 1.2 V 3.3–5.0 V D4, D10, H4, G13, K13, N5 D6 L4 J13 N10 Analog Power 3.3 V I/O Power Media Local Bus Power Nexus Power Voltage Regulator Select Voltage Regulator Control Voltage Voltage Regulator Control Output Clock Synthesizer Power Analog High Voltage Reference Analog Low Voltage Reference Ground 3.3–5.0 V 3.3 V 2.5 or 3.3 V 3.3 V VSSA / VDDA 3.3–5.0 V
— 3
Pin Name VDD VDDE1 VDDE2 VDDE3 VDDE4 VDDA VDD33 VDDEMLB VDDENEX2 VRCSEL VRC VRCCTL VDDSYN VRH VRL VSS
Function Description
Voltage1
256 D4, D10, H4, G13, K13, N5 D6 L4 J13 N10 B15 L13 K4 E6, K11, L7 H13 B10 B11 A12 B16 C16
B15 L13 K4 — H13 B10 B11 A12 B16 C16
3.3 V 3.3–5.0 V 0V 0V
A1, A16, D7, G4, G[7:10], A1, A16, D7, E[7:12], F[7:12], H[7:10], J[7:10], K[7:10], N13, G4, G[6:12], H[7:12], J[7:12], T1, T16 K[6:10], K12, L[8:10], L12, N13, T1, T16 C15 A15 C15 A15
VSSA VSSSYN
1 2
Analog Ground Clock Synthesizer Ground
0V 0V
Nominal voltages. Dedicated Nexus power pin on 256-pin package only. On the 208-pin package, VDDENEX is tied to VSS internal to the package substrate and is not available externally. 3 Base current to external NPN power transistor. Voltage may vary.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4
Electrical Characteristics
NOTE
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon the finalized specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5668x.
4.1
Spec 1 2 3 4 5 6
Maximum Ratings
Table 4. Absolute Maximum Ratings1
Characteristic 1.2 V Core Supply Voltage 3.3 V Clock Synthesizer Voltage 3.3 V I/O Buffer Voltage 3.3–5.0 V Voltage Regulator Control Voltage 3.3–5.0 V Analog Supply Voltage (reference to VSSA) 3.3–5.0 V External I/O Supply Voltage4 VDDE15 VDDE25 VDDE35 VDDE45 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –1.07 –1.06 –0.3 5.5 5.5 5.5 5.5 3.6 3.6 VDDEx + 0.3 V8 VDDEx + 0.3 V7 Minimum of 5.5 or VDDA + 0.3 5.5 100 100 2 3 150.0 235.0 3 V V V V Symbol VDD VDDSYN VDD33 VRC VDDA Min –0.3 –0.3 –0.3 –0.3 –0.3 Max2 1.323 3.6 3.6 5.5 5.5 Unit V V V V V V
7 8 9
2.5–3.3 V External I/O Supply Voltage (MLB) 3.3 V External I/O Supply Voltage (Nexus) DC Input VDDE1, VDDE2, VDDE3, VDDE4 VDDEMLB, VDDENEX Analog Reference High Voltage Voltage6
VDDEMLB5 VDDENEX5 VIN
10
VRH
11 12 13 14 15 16 17 18
Analog Reference Low Voltage VSS to VSSA Differential Voltage VSS to VSSSYN Differential Voltage Maximum DC Digital Input digital F, MH, SH, and IH pins) Current9 (per pin, applies to all
VRL VSS – VSSA VSS – VSSSYN IMAXD IMAXA TSTG
–0.3 –100 –100 –2 –3 –55.0 — —
V mV mV mA mA
o
Maximum DC Analog Input Current10 (per pin, applies to all analog AE and A pins) Storage Temperature Range Maximum Solder Temperature Moisture Sensitivity Level12
11
C
TSDR MSL
oC
MPC5668x Microcontroller Data Sheet, Rev. 3 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum specifications for device stress have not yet been determined. 3 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 4 All functional non-supply I/O pins are clamped to V SS and VDDEx. 5 VDDEx are separate power segments and may be powered independently with no differential voltage constraints between the power segments. 6 AC signal over and undershoot of the input voltages of up to ±2.0 V is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 7 Internal structures will hold the input voltage above –1.0 V if the injection current limit of 2 mA is met. 8 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (25 mA for all pins) and VDDE is within Operating Voltage specifications. 9 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 10 Total injection current for all analog input pins must not exceed 15 mA. 11 Solder profile per CDF-AEC-Q100. 12 Moisture sensitivity per JEDEC test method A112.
4.2
Thermal Characteristics
Table 5. Thermal Characteristics
Value
Spec 1
Characteristic Junction to Ambient Natural Convection (Single layer board)
1, 2
Symbol RθJA
Unit 208 MAPBGA °C/W 39 256 MAPBGA 39
2
Junction to Ambient1, 3 Natural Convection (Four layer board 2s2p) Junction to Ambient1, 3 (@200 ft./min., Single layer board) Junction to Ambient1, 3 (@200 ft./min., Four layer board 2s2p) Junction to Board4 Junction to Case
5
RθJA
°C/W
24
24
3 4 5 6 7
1
RθJMA RθJMA RθJB RθJC
°C/W °C/W °C/W °C/W °C/W
31 20 13 6 2
31 20 13 6 2
Junction to Package Natural Convection
Top6
ΨJT
2 3 4 5 6
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. MPC5668x Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor Preliminary—Subject to Change Without Notice
27
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.2.1
General Notes for Specifications at Maximum Junction Temperature
TJ = TA + (RθJA × PD) Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm2. The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RθJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction to ambient thermal resistance (oC/W)
MPC5668x Microcontroller Data Sheet, Rev. 3 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Eqn. 2
Eqn. 3
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
RθJC = junction to case thermal resistance (oC/W) RθCA = case to ambient thermal resistance (oC/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TT = thermocouple temperature on top of the package (oC) ΨJT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. Eqn. 4
References:
Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. 1. 2. 3. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.3
ESD Characteristics
Table 6. ESD Ratings1, 2
Characteristic Symbol Value 2000 R1 C 1500 100 750 (corner pins) 500 (all other pins) V Unit V Ohm pF
ESD for Human Body Model (HBM) HBM Circuit Description
ESD for Field Induced Charge Model (FDCM)
Number of Pulses per pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses
1 2
— — —
1 1 1
— — second
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
4.4
Spec 1
VRC Electrical Specifications
Table 7. VRC Electrical Specifications Characteristic
Current which can be sourced by VRCCTL Minimum Required Gain from external circuit: IDD / I_VRCCTL (@VDD = 1.32 V)1 –40°C 25°C 150°C
Symbol
I_VRCCTL
Min
6.25 µA
Max
20 mA
Units
—
2
BETA
50 50 50
500
1
Assumes “typical usage” currents which will vary with application.
4.5
Spec 1 2 3 4
DC Electrical Specifications
Table 8. DC Electrical Specifications
Characteristic Maximum Operating Temperature Range — Die Junction Temperature 3.3 V Clock Synthesizer Voltage1 3.3 V I/O Buffer Voltage1 Symbol TJ VDDSYN VDD33 VVRC 3.0 4.5 VDDA maximum of 3.0 V or VVRC – 0.1 3.6 5.5 5.52, 4 V Min –40.0 3.0 3.0 Max 150.0 3.62, 3 3.62, 3 Unit
oC
V V V
3.3–5.0 V Voltage Regulator Reference Voltage1 VRCSEL = VSSA VRCSEL = VDDA 3.3–5.0 V Analog Supply Voltage
5
MPC5668x Microcontroller Data Sheet, Rev. 3 30 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 8. DC Electrical Specifications
Spec 6 Characteristic 3.3–5.0 V External I/O Supply Voltage5 VDDE1 VDDE22 VDDE32 VDDE42 7 8 9 2.5 V – 3.3 V External I/O Supply Voltage (MLB) 3.3 V External I/O Supply Voltage (Nexus) Pad Input High Voltage Hysteresis enabled Hysteresis disabled (IHA/SH/SHA/MH/MHA)6, 7 Hysteresis disabled (F) Pad Input Low Voltage Hysteresis enabled Hysteresis disabled (IHA/SH/SHA/MH/MHA)6, 7 Hysteresis disabled (F) Pad Input Hysteresis Analog (IHA) Input Voltage Pad Output High Voltage8, 9, 10 Pad Output Low Voltage1, 10 Input Capacitance (Digital Pins: Pad type F, MH, SH)6 Input Capacitance (Analog Pins: Pad type IHA)6, 7 Input Capacitance (Shared digital/analog pins: MHA, SHA)6 I/O Weak Pull Up/Down Absolute Current6, 11 Pad F: 2.375 V – 3.6 V Pad SH/MH/IHA: 3.0 V – 3.6 V Pad SH/MH/IHA: 4.5 V – 5.5 V I/O Input Leakage Current12 DC Injection Current (per pin) Analog Input Current, Channel Off13 (Analog pins IHA)6, 7 Analog Reference High Voltage Analog Reference Low Voltage VSS to VSSA Differential Voltage VSSSYN to VSS Differential Voltage Slew rate on VDDA, VDDEx, and VDDR power supply pins Capacitive Supply Load (VDD) Capacitive Supply Load (VDD33, VDDSYN) VDDEMLB2 VDDENEX2 VIH 3.0 3.0 3.0 3.0 2.375 3.0 0.65 × VDDE 0.55 × VDDE 0.55 × VDDE VSS – 0.3 5.52, 5 5.52,5 5.52, 5 5.52, 5 3.61, 2 3.61, 2 VDDE + 0.3 V V V Symbol Min Max Unit V
10
VIL
V 0.35 × VDDE 0.40 × VDDE 0.40 × VDDE V V V V pF pF pF μA
11 12 13 14 15 16 17 18
VHYS VINDC VOH VOL CIN CIN_A CIN_M IACT
0.1 × VDDE VSSA – 0.3 0.8 × VDDE — — — — 25 10 35 VDDA + 0.3 — 0.2 × VDDE 7 10 12 180 95 200 2.5 1.0 150 VDDA VSSA + 500 100 100 100 — —
19 20 21 22 23 24 25 26 27 28
1
IINACT_D IIC IINACT_A VRH VRL VSS – VSSA VSSSYN – VSS VRamp VLoad VLoad
–2.5 –1.0 –150 VDDA – 500 VSSA –100 –100 — 8 1
μA mA nA mV mV mV mV V/ms µF µF
When VRCSEL = VSSA (low), VDDSYN and VDD33 are externally supplied. When VRCSEL = VDDA (high), VDDSYN and VDD33 are generated by internal voltage regulators. When VRCSEL = VSSA (low), VDDSYN and VDD33 cannot be 100 mV higher than VRC.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 31
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
2 3
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 4 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 5 VDDE1 – VDDE4 are separate power segments and may be powered independently with no differential voltage constraints between the power segments. VDDE1 – VDDE3 pad power segments contain ADC analog input channels and thus the input analog signal level may be clamped to the VDDE level, resulting in inaccurate ADC results if the VDDE voltage level is less than VDDA. 6 The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only, M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad. 7 The IHA pads are related to VDDA. 8 Characterization Based Capability: IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE = 3.0 V; IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE = 2.25 V; IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE = 1.62 V. 9 Characterization Based Capability: IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH = 4.5 V; IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH = 3.0 V 10 All V /V OL OH values 100% tested with ±2 mA load. 11 Absolute value of current, measured at V and V . IL IH 12 Weak pull up/down inactive. Measured at V DDE = 5.25 V. Applies to pad types: pad_sh, and pad_mh. 13 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
4.6
Operating Current Specifications
Table 9. Operating Currents
Typ1 25 °C Ambient
—
Spec
Characteristic
Symbol
Max1 –40–150 °C Junction
—
Unit
Equations ITOTAL = IDDE + IDDA + IRH + IDD33 + IDDSYN + IRC + IDD IDDE = IDDE1 + IDDE2 + IDDE3 + IDDE4 + IDDEMLB 1 VDDE Current VDDE(1,2,3,4) @ 3.0 V – 5.5 V VDDEMLB @ 2.375 V – 3.6 V Static2 Dynamic3 VDDA Current VDDA @ 3.0 V – 5.5 V Run mode Sleep mode – Optional 32 kHz osc enabled VRH Current VRH @ 3.0 V – 5.5 V Run mode Sleep mode VDD33 Current VDD33 @ 3.0 V – 3.6 V Run mode Sleep mode
—
—
IDDE μA mA
0 Note 3 IDDA 1 20 +5 IRH 300 1 IDD33 10 10
30 25
2
30 50 +15
mA μA μA
3
700 30
μA μA
4
20 20
mA μA
MPC5668x Microcontroller Data Sheet, Rev. 3 32 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 9. Operating Currents (continued)
Spec 5 Characteristic VDDSYN Current VDD33 @ 3.0 V – 3.6 V Run mode Sleep mode – Optional4 4–40 MHz osc enabled w/ no clock – Optional4 4–40 MHz osc enabled w/ clock VRC Current VRC @ 3.135 V – 5.5 V Run mode Sleep mode – Optional4 16MIRC enabled VDD Current VDD @ 1.08 V – 1.32 V Run mode (Maximum @ 116 MHz) Sleep mode – Optional4 128KIRC enabled – Optional4 16MIRC enabled – Optional4 32 kHz osc enabled – Optional4 4–40 MHz osc enabled w/ no clock – Optional4 4–40 MHz osc enabled w/ clock – Optional4 32 KB RAM – Optional4 64 KB RAM – Optional4 128 KB RAM Typ1 Symbol 25 °C Ambient IDDSYN 5 1 +150 +300 IRC 1 0 +40 IDD 200 100 +5 +200 +5 +5 +150 +10 +20 +40 340 900 +10 +220 +20 +20 +200 +150 +300 +600 mA μA μA μA μA μA μA μA μA μA 10 10 +60 mA μA μA 10 20 +350 +400 mA μA μA μA Max1 –40–150 °C Junction Unit
6
7
1 2
Typ – Nominal voltage levels and functional activity. Max – Maximum voltage levels and functional activity. Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads. 3 Dynamic current from pins is application-specific and depends on active pull devices, switching outputs, output capacitive and current loads, and switching inputs. Refer to Table 10 for more information. 4 Optional currents are values that should be added to their respective current specifications to obtain the actual value for that specification when the optional function is active. The plus sign (+) in the Typ and Max columns indicates these optional currents. For example, VDDSYN in Sleep mode draws 1 .μA (typ). With the optional 4–40 MHz osc enabled w/ no clock, add 150 .μA for a total of 151 .μA (typ).
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 33
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.7
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. Table 10. I/O Pad Average IDDE Specifications1
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Fast 15 16 17 18 19
1 2
Pad Type2
Symbol
Period (ns) 15 30
Load3 (pF) 50 50 50 50 200 50 50 50 50 200 50 30 20 10 50 30 20 10 0.5
VDDE (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 3.6 3.6 3.6 3.6 2.75 2.75 2.75 2.75 5.5
Drive/Slew Rate Select 11 10 01 00 00 11 10 01 00 00 11 10 01 00 11 10 01 00 N/A
IDDE Avg (mA) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 50.4 14.2 16.4 9.8 22.9 6.7 4.5 3 TBD
IDDE RMS (mA) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 101.6 57.3 43.6 15.9 45.3 25.3 17.3 9.6 TBD
Slow
IDRV_SSR_HV
50 300 300 15 30
Medium
IDRV_MSR_HV
50 300 300 10 10 10 10
IDRV_FC
10 10 10 10
Input
IDRV_I_HV
7
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2. 3 All loads are lumped.
MPC5668x Microcontroller Data Sheet, Rev. 3 34 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.7.1
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all Pad F pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all Pad MH pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. I/O Pad Average IDD33 Specifications1
Spec 1 2 Slow 3 4 5 6 Medium 7 8 9
1 2
Pad Type2
Symbol
Period (ns) 100 200
Load3 (pF) 50 50 50 200 50 50 50 200 0.5
Drive Select 11 01 00 00 11 01 00 00 N/A
IDD33 Avg (µA) 0.8 0.04 0.06 0.009 TBD 0.11 0.02 0.01 TBD
IDD33 RMS (µA) 235.7 87.4 47.4 47 TBD 76.5 56.2 56.2 TBD
IDRV_SSR_HV
800 800 40 100
IDRV_MSR_HV
500 500
Input
IDRV_I_HV
7
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2. 3 All loads are lumped.
Table 12. IDD33 Pad Average DC Current1
Spec 1 2 3 4 Fast 5 6 7 8
1 2
Pad Type2
Symbol
Period (ns) 10 10 10 10
Load3 (pF) 50 30 20 10 50 30 20 10
VDD33 (V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
VDDE (V) 3.6 3.6 3.6 3.6 2.75 2.75 2.75 2.75
Drive Select 11 10 01 00 11 10 01 00
IDD33 Avg (µA) 3.32 2.28 1.73 1.39 2.3 1.64 1.37 1.06
IDD33 RMS (µA) 11.77 7.07 5.75 4.77 7.81 4.96 4.31 4.09
IDRV_FC
10 10 10 10
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2. 3 All loads are lumped.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 35
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.8
Spec 1 2
Low Voltage Characteristics
Table 13. Low Voltage Monitors
Characteristic Power-on-Reset Assert Level1 Low Voltage Monitor 3.3 V2 Assert Level De-assert Level Low Voltage Monitor Synthesizer3 Assert Level De-assert Level Low Voltage Monitor 3.0 V Low Threshold1 VRCSEL = VSSA Assert Level De-assert Level VRCSEL = VDDA Assert Level De-assert Level Low Voltage Monitor 5.0 V1, 4 Assert Level De-assert Level Low Voltage Monitor 5.0 V High Threshold1, 5 Assert Level De-assert Level Symbol VPOR VLVI33A VLVI33D VLVISYNA VLVISYND Min 1.5 3.00 3.04 3.00 3.04 Typical — 3.05 3.12 3.05 3.12 Max 2.8 3.10 3.19 V 3.10 3.19 V VLVI_VDDA_LOA VLVI_VDDA_LOD VLVI_VDDA_LOA VLVI_VDDA_LOD VLVI_VDDA_A VLVI_VDDA_D VLVI_VDDA_HA VLVI_VDDA_HD 3.00 3.04 3.25 3.35 4.40 4.50 4.55 4.55 3.05 3.12 3.35 3.45 4.475 4.575 4.65 4.65 3.10 3.19 3.48 3.55 V 4.55 4.65 V 4.75 4.75 Unit V V
3
4
5
6
1 2
Monitors VDDA. Monitors VDD33. 3 Monitors V DDSYN. 4 Disabled when V RCSEL = VSSA.
4.9
Spec 1 2 3
Oscillators Electrical Characteristics
Table 14. 3.3 V High Frequency External Oscillator
Characteristic Frequency Range Duty Cycle of reference EXTAL Input High Voltage External crystal mode2 External clock mode EXTAL Input Low Voltage External crystal mode3 External clock mode XTAL Current4 Total On-chip stray capacitance on XTAL Total On-chip stray capacitance on EXTAL Symbol fref tDC VIHEXT VXTAL + 0.4 0.65 × VDDSYN VILEXT VDDSYN – 0.3 VDDSYN – 0.3 IXTAL CS_XTAL CS_EXTAL 1 — — VXTAL – 0.4 0.35 × VDDSYN 3 3 3 mA pF pF VDDSYN + 0.3 VDDSYN + 0.3 V Min 41 40 Max 40 60 Unit MHz % V
4
5 6 7
MPC5668x Microcontroller Data Sheet, Rev. 3 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 14. 3.3 V High Frequency External Oscillator (continued)
Spec 8 9 10 11
1 2 3 4 5
Characteristic Crystal manufacturer’s recommended capacitive load Discrete load capacitance to be connected to EXTAL Discrete load capacitance to be connected to XTAL Startup Time
Symbol CL CL_EXTAL CL_XTAL tstartup
Min See crystal specification — — —
Max See crystal specification 2×CL – CS_EXTAL – CPCB_EXTAL5 2×CL – CS_XTAL – C
PCB_XTAL 5
Unit pF pF pF ms
10
When PLL frequency modulation is active, reference frequencies less than 8 MHz will distort the modulated waveform and the effects of this on emissions is not characterized. This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal – Vxtal ≥ 400 mV criteria has to be met for oscillator’s comparator to produce output clock. This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vxtal – Vextal ≥ 400 mV criteria has to be met for oscillator’s comparator to produce output clock. Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Table 15. 5 V Low Frequency (32 kHz) External Oscillator
Spec 1 2 3 4 5
1
Characteristic Frequency Range Duty Cycle of reference XTAL32 Current1
Symbol fref32 tdc32 IXTAL32 CL32 tStartup
Min. 32 40 — See crystal specification —
Max 40 60 3 See crystal specification 2
Unit kHz % μA pF s
Crystal manufacturer’s recommended capacitive load Startup Time
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
Table 16. 5 V High Frequency (16 MHz) Internal RC Oscillator
Spec 1 2 3 4 5
1 2
Characteristic Frequency before trim1 Frequency after loading factory Application trim resolution3 step3 trim2
Symbol fut ft ts fs tStartup
Range 35% 5% — — —
Min 10.4 15.2 — — —
Typ 16 16 — 300 —
Max 21.6 16.8 ±0.5 — 500
Unit MHz MHz % kHz ns
Application frequency trim Startup Time
Across process, voltage, and temperature. Across voltage and temperature. 3 Fixed voltage and temperature.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 17. 5V Low Frequency (128 kHz) Internal RC Oscillator
Spec 1 2 3 4 5
1 2
Characteristic Frequency before trim
1
Symbol Fut128 trim2 Ft128 Ts128
3
Range 35% 5% — — —
Min 83.2 121.6 — — —
Typ 128 128 — 1 —
Max 172.8 134.4 ±2 — 100
Unit kHz kHz % kHz μs
Frequency after loading factory Application trim resolution3
Application frequency trim step Startup Time
Fs128 St128
Across process, voltage, and temperature. Across voltage and temperature. 3 Fixed voltage and temperature.
4.10
Spec 1 2 3
FMPLL Electrical Characteristics
Table 18. FMPLL Electrical Specifications1
Characteristic System Frequency2 PLL Reference Frequency Range PLL Frequency Symbol fSYS fREF fPLL Min — 4 f vco ( min ) ----------------------------( ERFD + 1 ) 100 16 — 40 –4.0 –2.0 2000 64 400 60 4.0 2.0 Max 116 40 Unit MHz MHz MHz
4 5 6 7 8 9 10 11 12
Loss of Reference Frequency 3 Self Clocked Mode Frequency PLL Lock Time4 Duty Cycle of Reference Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter,5 Measured at fSYS Max Cycle-to-cycle Jitter CLKOUT Jitter at ≥ 50 µs period Peak-to-Peak Frequency Modulation Range Limit 6,7 (fSYSMax must not be exceeded) FM Depth Tolerance8 VCO Frequency9 Modulation Rate Limits10
fLOR fSCM tLPLL tDC fUL fLCK CJitter CJitter Cmod Cmod_err fVCO fMOD
kHz MHz μs % % fSYS % fSYS %fSYS %fCLKOUT %fSYS %fSYS MHz MHz
–5 –0.5 0 –0.50 192 0.400
5 0.5 4 0.50 600 1
13 14 15
1
VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH.
MPC5668x Microcontroller Data Sheet, Rev. 3 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
2
The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximuum frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded. 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal startup time. 5 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod. 6 Modulation depth selected must not result in fPLL value greater than the fPLL maximum specified value. 7 Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these settings. 8 Depth tolerance is the programmed modulation depth ±0.25% of fSYS. Initial design target pending silicon evaluation. 9 See the Block Guide for VCO frequency synthesis equations. 10 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz will result in reduced calibration accuracy.
4.11
Spec 1 2 3 4 5 6
ADC Electrical Characteristics
Table 19. ADC Conversion Specifications (Operating)
Characteristic Analog High Reference Voltage Analog Low Reference Voltage Analog Input Voltage Sampling Frequency Maximum ADC Clock Frequency Sampling Time VDDA = 3.0 V – 3.6 V VDDA > 3.6 V – 5.5 V Differential Non Linearity Integral Non Linearity Offset Error Gain Error Total Unadjusted Error
1
Symbol VRH VRL AVIN FS FMAX tS
Min VDDA – 0.5 0 VRL — — 250 125
Max VDDA 0.5 VRH 1.53 60 —
Unit V V V MHz MHz ns
7 8 9 10 11
1
DNL INL OFS GNE TUE
–1.0 –1.5 –1.0 –2.0 –2.0
1.0 1.5 1.0 2.0 2.0
LSB LSB LSB LSB LSB
TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding VDDE segment.
4.12
Spec 1 2 3 4 5
Flash Memory Electrical Characteristics
Table 20. Flash Program and Erase Specifications1
Characteristic Symbol tdwprogram Time4 tpprogram t16kpperase t64kpperase Min — — — — Initial Max2 — 160 1000 1800 2600 Max3 500 500 5000 5000 7500 Unit μs μs ms ms ms
Double Word (64 bits) Program Time4 Page (128 bits and 256 bits) Program
16 KB Block Pre-program and Erase Time 64 KB Block Pre-program and Erase Time 128 KB Block Pre-program and Erase Time
t128kpperase —
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 20. Flash Program and Erase Specifications1 (continued)
Spec 6 7 Characteristic 256 KB Block Pre-program and Erase Time Wait States Relative to System PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b010; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b011 – 0b111; PFCRPn[WWSC] = 0b01 Recovery Time Frequency5 Symbol Min Initial Max2 5200 — — — — — Max3 15,000 30 60 90 fSYS max 45 μs Unit ms MHz — — — — tRecover —
t256kpperase — trwsc
8
1 2
Typical program and erase times assume nominal supply values and operation at 25 oC. Initial factory condition: < 100 program/erase cycles, nominal supply values and operation at 25 oC. 3 The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Actual hardware programming time. This does not include software overhead. 5 Wait state timing is based on the system clock frequency and thus is same for all masters.
Table 21. Flash EEPROM Module Life (Full Temperature Range)
Spec 1 2 3 Characteristic Number of Program/Erase cycles per block for 16 KB and 64 KB blocks over the operating temperature range (TJ) Number of Program/Erase cycles per block for 128 KB blocks over the operating temperature range (TJ) Minimum Data Retention at 25 °C ambient temperature2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–10,000 P/E cycles Blocks with 10,001–100,000 P/E cycles Symbol P/E P/E Retention 20 10 1–5 Min 100,000 1,000 Typical1 — Unit cycles
100,000 cycles — years
1
Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
4.13
Spec
Pad AC Specifications
Table 22. Pad AC Specifications (5.0 V, 2.5 V)1
Pad Type2 SRC/DSC3 00 Output Delay4,4 (ns) 318/343 408/431 61/67 80/90 18/18 27/28 Rise/Fall5,6 (ns) 155/173 188/204 30/34 38/44 10/11 15/17 Load Drive (pF) 50 200 50 200 50 200
1
Slow7
01 11
MPC5668x Microcontroller Data Sheet, Rev. 3 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
Table 22. Pad AC Specifications (5.0 V, 2.5 V)1 (continued)
Spec Pad Type2 SRC/DSC3 00 2 Medium 01 11 00 3 Fast8 01 10 11 4
1
Output Delay4,4 (ns) 142/186 195/253 20/35 41/64 12/11 32/34
Rise/Fall5,6 (ns) 65/89 91/122 8.7/16.6 24/35 5.3/5.9 21/23
Load Drive (pF) 50 200 50 200 50 200 10 20 30 50 0.5
2.7
1.5
Input
N/A
1.9/1.9
1.5/1.5
2 3 4 5 6 7 8
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 1.62 – 1.98 V, VDDEH = 4.5 – 5.5 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to TH. Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2. SRC/DSC are bitfields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only), DSC—Drive Strength Control (fast pad type only). This parameter is supplied for reference and is not guaranteed by design and not tested. This parameter is guaranteed by characterization before qualification rather than 100% tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. Add a maximum of one system clock to the output delay for delay with respect to system clock. Output delay is shown in Figure 6. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V)1
Spec Pad Type2 SRC/DSC3 Out Delay4,5 (ns) 408/431 00 533/592 1 Slow7 80/90 01 146/167 27/28 11 81/92 184/240 00 253/330 28/47 2 Medium 01 58/88 18/17 11 46/51 30/35 200 34/49 7.6/8.9 200 50 114/153 11.8/21.8 200 50 57/67 79/107 200 50 82/96 15/17 200 50 250/288 38/44 200 50 Rise/Fall6, (ns) 188/204 Load Drive (pF) 50
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41
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Electrical Characteristics
Table 23. De-rated Pad AC Specifications (3.3 V, 3.3 V)1 (continued)
Spec Pad Type2 SRC/DSC3 00 3 Fast8 01 2.5 10 11 4
1
Out Delay4,5 (ns)
Rise/Fall6, (ns) 1.2 1.2 1.2 1.2
Load Drive (pF) 10 20 30 50 0.5
Input
N/A
3/3
1.5/1.5
2 3 4 5 6 7 8
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 3.0 – 3.6 V, VDDEH = 3.0 – 3.6 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to TH. Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 2. SRC/DSC are bitfields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only), DSC—Drive Strength Control (fast pad type only). This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested. Add a maximum of one system clock to the output delay for delay with respect to system clock. Output delay is shown in Figure 6. Add a maximum of one system clock to the output delay for delay with respect to system clock.
VDD/2 Pad Internal Data Input Signal Rising Edge Out Delay Falling Edge Out Delay VOH
Pad Output
VOL
Figure 6. Pad Output Delay
MPC5668x Microcontroller Data Sheet, Rev. 3 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.14
4.14.1
Spec 1 2 3
AC Timing
Reset and Boot Configuration Pins
Table 24. Reset and Boot Configuration Timing
Characteristic RESET Pulse Width BOOTCFG Setup Time after RESET Valid BOOTCFG Hold Time from RESET Valid Symbol tRPW tRCSU tRCH Min 150 — 0 Max — 100 — Unit ns μs μs
RESET
1
2
BOOTCFG
3
Figure 7. Reset and Boot Configuration Timing
4.14.2
Spec 1 2 3
1
External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins
Table 25. IRQ/NMI Timing
Characteristic Symbol tIPWL TIPWH tICYC Min 3 3 6 Max — — — Unit tSYS tSYS tSYS
IRQ/NMI Pulse Width Low IRQ/NMI Pulse Width High IRQ/NMI Edge to Edge Time1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
IRQ/NMI
1,2 3
1,2
Figure 8. IRQ and NMI Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43
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Electrical Characteristics
4.14.3
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1
JTAG (IEEE 1149.1) Interface
Table 26. JTAG Interface Timing1
Characteristic TCK Cycle Time TCK Clock Pulse Width (Measured at VDDE/2) TCK Rise and Fall Times (40% – 70%) TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance JCOMP Assertion Time JCOMP Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT Min 100 40 — 5 25 — 0 — 100 40 — — — 50 50 Max — 60 3 — — 25 — 20 — — 50 50 50 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11.
TCK 2 3 2
1
3
Figure 9. JTAG Test Clock Input Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
TMS, TDI
TDO TCK
TCK
JCOMP
Freescale Semiconductor 7 5 4 6
9
Figure 11. JTAG JCOMP Timing
Figure 10. JTAG Test Access Port Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 10 8
Preliminary—Subject to Change Without Notice
Electrical Characteristics
45
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Electrical Characteristics
46 TCK Output Signals Output Signals Input Signals 12 11 14 13
Figure 12. JTAG Boundary Scan Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 15
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.14.4
Spec 1 2 3 4 5 6 7 8 9 10
1
Nexus Debug Interface
Table 27. Nexus Debug Port Timing1
Characteristic Symbol tMCYC tMDC
2
Min 15.6 40 –0.1 4.0 1 40 40 8 5 0
Max — 60 0.25 —
Unit ns % tMCYC tTCYC tMCYC ns % ns ns ns
MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO, MSEO, EVTO Data Valid EVTI Pulse Width EVTO Pulse Width TCK Cycle Time TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid
3
tMDOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV
— 60 — — 25
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11. 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3 The system clock frequency needs to be three times faster than the TCK frequency.
1 2 MCKO
3
MDO MSEO EVTO Output Data Valid
5
EVTI
4
Figure 13. Nexus Output Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47
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Electrical Characteristics
48 TCK TMS, TDI TDO 8 9 10
Figure 14. Nexus TDI, TMS, TDO Timing
MPC5668x Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
6
7
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics
4.14.5
Spec 1 2
1 2
Enhanced Modular I/O Subsystem (eMIOS)
Table 28. eMIOS Timing1
Characteristic eMIOS Input Pulse Width eMIOS Output Pulse Width Symbol tMIPW tMOPW Min 4 12 Max — — Unit tCYC tCYC
eMIOS timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
Figure 15. eMIOS Timing
D_CLKOUT
2
eMIOS output
eMIOS input
1
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49
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Electrical Characteristics
4.14.6
Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI Timing
116 MHz1
Spec
Characteristic
Symbol Min. Value Max. Value
Unit
1
DSPI Cycle Time Master (MTFE = 0) Slave (MTFE = 0) Master (MTFE = 1) Slave (MTFE = 1) PCS to SCK Delay2 After SCK Delay3 SCK Duty Cycle Slave Access Time (SS active to SOUT valid) Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) PCSx to PCSS time PCSS to PCSx time Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)4 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)4 Master (MTFE = 1, CPHA = 1) Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1)
tSCK 100 100 50 50 tCSC tASC tSDC tA tDIS tPCSC tPASC tSUI 25 5 10 25 tHI –4 7 12 –4 tSUO — — — — tHO –7 2 1 –7 — — — — ns ns ns ns 8 28 15 8 ns ns ns ns — — — — ns ns ns ns — — — — ns ns ns ns 7 14 0.4 × tSCK — — 0 0 — — — — — — 0.6 × tSCK 25 25 — — ns ns ns ns ns ns ns ns ns ns ns
2 3 4 5 6 7 8 9
10
11
12
1 2
116 MHz timing specified at CL = 50 pF with SRC = 0b11. The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK]. 3 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC]. 4 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
MPC5668x Microcontroller Data Sheet, Rev. 3 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages 51 Preliminary—Subject to Change Without Notice
2 PCSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Figure 16. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Figure 17. DSPI Classic SPI Timing — Master, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor
Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages Freescale Semiconductor Preliminary—Subject to Change Without Notice
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Figure 18. DSPI Classic SPI Timing — Slave, CPHA = 0
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 19. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 3 52
Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages 53 Preliminary—Subject to Change Without Notice
3 PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Figure 20. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Figure 21. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor
Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
SS
2 1
3
SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Figure 22. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 23. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
7 PCSS PCSx 8
Figure 24. DSPI PCS Strobe (PCSS) Timing
MPC5668x Microcontroller Data Sheet, Rev. 3 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
4.14.7
4.14.7.1
MLB Interface
Media Local Bus DC Electrical Characteristics
Table 30. Media Local Bus DC Electrical Characteristics
Parameter Symbol — VIL VIH VOL VOH IL Min — — 1.8
1
Table 30 provides the DC electrical characteristics for the Media Local Bus interface.
Typ — — — — — —
Max 3.6 0.7 — 0.4 — ±1
Unit V V V V V µA
Comments
Maximum Input Voltage Low Level Input Threshold High Level Input Threshold Low Level Output Threshold High Level Output Threshold Input Leakage Current
1
— 2.0 —
IOL = 6 mA IOH = –6 mA 0 < Vin < VDDE4
Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated and assumed by the customer.
4.14.7.2
Media Local Bus (MLB) AC Electrical Characteristics
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs
Table 31 and Table 32 provide the AC electrical characteristics for the Media Local Bus interface.
Spec 1
Parameter MLBCLK Operating Frequency
1
Symbol fmck
Min 11.264 — — — — — — 31.5 30 14.5 14
Typ — 12.288 24.576 — — — — 81 40 37 35.5 17 16.5 38 36.5 17 16.5 — — —
Max — — — 24.6272 25.600 3 3 — — — — — 2 — —
Unit
Comments
256 Fs at 44.0 kHz 256 Fs at 48.0 kHz MHz 512 Fs at 48.0 kHz 512 Fs at 48.1 kHz 512 Fs PLL unlocked ns ns ns ns ns ns ns ns p-p ns ns VIL to VIH VIH to VIL 256 Fs 512 Fs 256 Fs 256 Fs PLL unlocked 512 Fs 512 Fs PLL unlocked 256xFs 256 Fs PLL unlocked 512 Fs 512 Fs PLL unlocked
2 3 4 5
MLBCLK rise time MLBCLK fall time MLBCLK cycle time MLBCLK low time
tmckr tmckf tmckc tmckl
6
MLBCLK high time
tmckh
31.5 30 14.5 14
7 8 9
MLBCLK pulse width variation2 MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low
tmpwv tdsmcf tdhmcf
— 1 0
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 55
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Electrical Characteristics
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs (continued)
Spec 10 11 12 Parameter MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold time3 MLBSIG/MLBDAT output valid from MLBCLK rising Symbol tmcfdz tmdzh tmcrdv Min 0 4 — Typ — — — Max tmckl — 8 Unit ns ns ns Comments
• Ground = 0.0V • Load Capacitance = 60 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b11. • MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz) Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in Table 30.
1 2
The Controller can shut off MLBCLK to place MLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (ns p-p). 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 32. MLB Timing for MLB Speed 1024 Fs
Spec 1 Parameter MLBCLK Operating Frequency1 Symbol fmck Min 45.056 — — — — — — 6.5 6.1 9.7 9.3 — 1 0 0 2 — Typ — 49.152 — — — — 20.3 7.7 7.3 10.6 10.2 — — — — — — Max — — 49.2544 51.200 1 1 — — — 0.7 — — tmckl — 7 Unit Comments
1024 Fs at 44.0 kHz 1024 Fs at 48.0 kHz MHz 1024 Fs at 48.1 kHz 1024 Fs PLL unlocked ns ns ns ns ns ns p-p ns ns ns ns ns VIL to VIH VIH to VIL VIL to VIH 1024 Fs PLL unlocked 1024 Fs PLL unclocked
2 3 4 5 6 7 8 9 10 11 12 • • • •
MLBCLK rise time MLBCLK fall time MLBCLK cycle time MLBCLK low time MLBCLK high time MLBCLK pulse width variation2 MLBSIG/MLBDAT input valid to MLBCLK falling MLBSIG/MLBDAT input hold from MLBCLK low MLBSIG/MLBDAT output high impedance from MLBCLK low Bus Hold time3 MLBSIG/MLBDAT output valid from MLBCLK rising
tmckr tmckf tmckc tmckl tmckh tmpwv tdsmcf tdhmcf tmcfdz tmdzh tmcrdv
Ground = 0.0V Load Capacitance = 40 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b00. MLB speed = 1024Fs (Fs = 48 kHz) Unless otherwise noted, timing parameters are specified from the valid voltage threshold in Table 30.
MPC5668x Microcontroller Data Sheet, Rev. 3 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor
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Electrical Characteristics
1 2
The Controller can shut off MLBCLK to place MLB in a low-power state. Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (ns p-p). 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
MLBSIG/ MLBDAT (input)
valid data
9 8 2 MLBCLK 4 10 12 MLBSIG/ MLBDAT (output)
valid data
6
3 5
11
Figure 25. Media Local Bus (MLB) Timing
4.14.8
Fast Ethernet Interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible. They follow the CMOS electrical characteristics.
4.14.8.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency. Table 33. MII Receive Signal Timing
Spec M1 M2 M3 M4 Characteristic RXD[3:0], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns RX_CLK period RX_CLK period
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57
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Electrical Characteristics Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
M3 RX_CLK (input)
RXD[3:0] (inputs) RX_DV RX_ER M1 M2
M4
Figure 26. MII Receive Signal Timing Diagram
4.14.8.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it. Table 34. MII Transmit Signal Timing1
Spec M5 M6 M7 M8
1
Characteristic TX_CLK to TXD[3:0], TX_EN, TX_ER invalid TX_CLK to TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low
Min 5 — 35% 35%
Max — 25 65% 65%
Unit ns ns TX_CLK period TX_CLK period
Output pads configured with SRC = 0b11.
M7
TX_CLK (input) M5 TXD[3:0] (outputs) TX_EN TX_ER M6 M8
Figure 27. MII Transmit Signal Timing Diagram
MPC5668x Microcontroller Data Sheet, Rev. 3 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor
Electrical Characteristics
4.14.8.3
MII Async Inputs Signal Timing (CRS and COL)
Table 35. MII Async Inputs Signal Timing1
Spec M9
1
Characteristic CRS, COL minimum pulse width
Min 1.5
Max —
Unit TX_CLK period
Output pads configured with SRC = 0b11.
CRS, COL M9
Figure 28. MII Async Inputs Timing Diagram
4.14.8.4
MII Serial Management Channel Timing (MDIO and MDC)
Table 36. MII Serial Management Channel Timing1
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Spec M10 M11 M12 M13 M14 M15
1
Characteristic MDC falling edge to MDIO output invalid (minimum propagation delay) MDC falling edge to MDIO output valid (max prop delay) MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width high MDC pulse width low
Min 0 — 10 0 40% 40%
Max — 25 — — 60% 60%
Unit ns ns ns ns MDC period MDC period
Output pads configured with SRC = 0b11.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59
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Electrical Characteristics
60 MDC (output) MDIO (output) MDIO (input) M12 M13 M14 M10 M11 M15
MPC5668x Microcontroller Data Sheet, Rev. 3
Figure 29. MII Serial Management Channel Timing Diagram
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
5
5.1
Freescale Semiconductor
Package Characteristics
Package Mechanical Data
MPC5668x Microcontroller Data Sheet, Rev. 3
Figure 30. 208 MAPBGA Package Mechanical Drawing
Preliminary—Subject to Change Without Notice
Package Characteristics
61
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Package Characteristics
62
Figure 31. 208 MAPBGA Package Detail
MPC5668x Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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Freescale Semiconductor Package Characteristics
MPC5668x Microcontroller Data Sheet, Rev. 3
Figure 32. 256 MAPBGA Package Mechanical Drawing
Preliminary—Subject to Change Without Notice
63
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Package Characteristics
64
Figure 33. 256 MAPBGA Package Detail
MPC5668x Microcontroller Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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Revision History
6
Revision History
Table 37. Revision History
Revision 0 1 2 3 Date April 2008 June 2008 Jan 2009 Preliminary release. Initial release: Advance Information. Release: Advance Information. Description
Table 37 describes the changes made to this document between revisions.
September 2009 Release: Advance Information, interim updates.
MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
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D ocument Number: MPC5668X
Rev. 3 9/2009
Preliminary—Subject to Change Without Notice
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MPC5668x products in 208 and 256 MAPBGA packages
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