Freescale Semiconductor Data Sheet: Advance Information
Document Number: MPC5674F Rev. 6, 2/2011
MPC5674F
MPC5674F Microcontroller Data Sheet
Covers: MPC5674F and MPC5673F
TEPBGA–416 27mm x 27mm TEPBGA–516 27mm x 27mm
Known Good Die (KGD)
TEPBGA–324 23mm x 23mm
Features: • Dual issue, 32-bit CPU core complex (e200z7) – Compliant with the Power Architecture embedded category – 16 KB I-Cache and 16 KB D-Cache – Includes an instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction – Includes signal processing extension (SPE2) instruction support for digital signal processing (DSP) and single-precision floating point operations • 4 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 256 KB on-chip general-purpose SRAM including 32 KB of standby RAM • Two direct memory access controller (eDMA2) blocks – One supporting 64 channels – One supporting 32 channels • Interrupt controller (INTC) • Frequency modulated phase-locked loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters • External bus interface (EBI) for calibration and application development (not available on all packages) • System integration unit (SIU) • Error correction status module (ECSM) • Boot assist module (BAM) supports serial bootload via CAN or SCI • Two second-generation enhanced time processor units (eTPU2) that share code and data RAM. – 32 standard channels per eTPU2 – 24 KB code RAM – 6 KB parameter (data) RAM
• Enhanced modular input output system supporting 32 unified channels (eMIOS) with each channel capable of single action, double action, pulse width modulation (PWM) and modulus counter operation • Four enhanced queued analog-to-digital converters (eQADC) – Support for 64 analog channels – Includes one absolute reference ADC channel – Includes eight decimation filters • Four deserial serial peripheral interface (DSPI) modules • Three enhanced serial communication interface (eSCI) modules • Four controller area network (FlexCAN) modules • Dual-channel FlexRay controller • Nexus development interface (NDI) per IEEE-ISTO 5001-2003/5001-2008 standard • Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) • On-chip voltage regulator controller regulates supply voltage down to 1.2 V for core logic
© Freescale Semiconductor, Inc., 2008-2011. All rights reserved.
Table of Contents
1 2 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 MPC567xF Family Differences . . . . . . . . . . . . . . . . . . . .4 MPC5674F Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6 3.2 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .9 3.3 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . .14 3.4 SignalProperties and Muxing . . . . . . . . . . . . . . . . . . . .19 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 4.2.1 General Notes for Specifications at Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .23 4.3 EMI (Electromagnetic Interference) Characteristics . . .24 4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .26 4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .29 4.6.1 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.6.3 Power Sequencing and POR Dependent on VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .31 4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .34 4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . .34 4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 36 Oscillator and FMPLL Electrical Characteristics . . . . . 36 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 39 4.9.1 ADC Internal Resource Measurements . . . . . . 40 4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 41 4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 45 4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.12.1 Generic Timing Diagrams . . . . . . . . . . . . . . . . 46 4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 47 4.12.3 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 48 4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.12.5 External Bus Interface (EBI) Timing . . . . . . . . . 54 4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 58 4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1 324-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 74 Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.8 4.9
4
MPC5674F Microcontroller Data Sheet, Rev. 6 2 Freescale Semiconductor
Ordering Information
1
1.1
Ordering Information
Orderable Parts
M PC 5674F M VR
Qualification status Core code
Figure 1 and Table 1 describe and list the orderable part numbers for the MPC5674F. A 264 R
Note: Not all options are available on all devices. Refer to Table 1.
Device number Temperature range Package identifier Revision of Silicon Operating frequency (MHz) Tape and reel status
Temperature Range M = –40 °C to 125 °C
Package Identifier VZ = 324 BGA Pb-free VR = 416 BGA Pb-free VY = 516 BGA Pb-free VV = 516 BGA SnPb
Operating Frequency 150 = 150 MHz 200 = 200 MHz 264 = 264 MHz
Tape and Reel Status R = Tape and reel (blank) = Trays
Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow
Revision of Silicon (blank) = Rev 1 A = Rev 2 (MPC and SPC part numbers will not have this field)
Figure 1. MPC5674F Orderable Part Number Description Table 1. Orderable Part Numbers1
Freescale Part Number2 PPC5674FMVRA264 PPC5674FMVVA264 PPC5674FMVYA264 PPC5674FMVZA264
1 2
Speed (MHz)3 Package Description Nominal 416 package, Pb-free 516 package, SnPb 516 package, Pb-free 324 package, Pb-free 264 264 264 200 Max5 (fMAX) 270 270 270 200
Operating Temperature4 Min (TL) –40 °C –40 °C –40 °C –40 °C Max (TH) 125 °C 125 °C 125 °C 125 °C
3 4 5
This table includes part numbers for sample parts. Refer to the product summary page on http://www.freescale.com for production part numbers. All packaged devices are PPC5674F, rather than MPC5674F or SPC5674F, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. For the operating mode frequency of various blocks on the device, see Table 28. The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system clock + 2% FM.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 3
Ordering Information
1.2
MPC567xF Family Differences
Table 2. MPC567xF Family Differences
Feature Package Flash SRAM External bus Serial eSCI_A eSCI_B eSCI_C SPI DSPI_A DSPI_B DSPI_C DSPI_D eMIOS eTPU2 eTPU_A eTPU_B ADC eQADC_A eQADC_B
1
Table 2 lists the differences between the MPC567xF devices. Refer to the MPC5674F Reference Manual for a full feature list and comparison.
MPC5674F 416 BGA 516 BGA 4 MB 256 KB Yes (516 BGA only) 3 Yes Yes Yes 4 Yes Yes Yes Yes 32 channel 64 channel Yes (32 ch) Yes (32 ch) 64 channel Yes (64 ch)1
MPC5674F 324 BGA 4 MB 256 KB No 2 Yes Yes No 3 No Yes Yes Yes 22 channel 47 channel Yes (26 ch) Yes (21 ch, no TCRCLK) 48 channel Yes (24 ch) Yes (24 ch)
MPC5673F 416 BGA 516 BGA 3 MB 192 KB Yes (516 BGA only) 3 Yes Yes Yes 4 Yes Yes Yes Yes 32 channel 64 channel Yes Yes 64 channel Yes (64 ch)1
MPC5673F 324 BGA 3 MB 192 KB No 2 Yes Yes No 3 No Yes Yes Yes 22 channel 47 channel Yes (26 ch) Yes (21 ch, no TCRCLK) 48 channel Yes (24 ch) Yes (24 ch)
There are are two pairs of 24 channels plus 16 shared channels. This gives 64 channels total: 40 per ADC (since 16 are shared).
MPC5674F Microcontroller Data Sheet, Rev. 6 4 Freescale Semiconductor
MPC5674F Blocks
2
2.1
MPC5674F Blocks
Block Diagram
MPC5674F
Interrupt Controller
Figure 2 shows a top-level block diagram of the MPC5674F device.
Power™ e200z7 Core
SPE2 VLE MMU eDMA2 64 Channel eDMA2 32 Channel 16K I-Cache 16K D-Cache FlexRay EBI (Calibration & Development Use) Nexus JTAG
Crossbar Switch MPU
4MB Flash
I/O Bridge
SIU
256KB SRAM (32K S/B)
Boot Assist Module
I/O Bridge
ECSM
DSPI
DSPI
DSPI
DSPI
eSCI
eSCI
eSCI
ADC
ADC
ADC
24KB Code RAM
AMux
LEGEND ADC ADCi AMux DECFIL DSPI EBI ECSM eDMA2 eMIOS eQADC – Analog to digital convertor – ADC interface – Analog multiplexer – Decimation filter – Deserial/serial peripheral interface – External bus interface – Error correction status module – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued A/D converter module eSCI – Enhanced serial communications interface eTPU2 – Enhanced time processing unit 2 FlexCAN – Controller area network MMU – Memory management unit MPU – Memory protection unit S/B – Stand-by SIU – System integration unit SPE2 – Signal processing engine 2 SRAM – General-purpose static RAM VLE – Variable length instruction encoding
Figure 2. Block Diagram
3
Pin Assignments
The figures in this section show the primary pin function. For the full signal properties and muxing table, see Appendix A, Signal Properties and Muxing.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 5
ADC
eMIOS 32 Channel
eTPU2 32 Channel
6KB Data RAM
DECFILx8
FlexCAN
FlexCAN
FlexCAN
FlexCAN
eQADC eQADC ADCi ADCi
eTPU2 32 Channel
Pin Assignments
3.1
324-ball TEPBGA Pin Assignments
Figure 3 shows the 324-ball TEPBGA pin assignments in one figure. The same information is shown split into to halves in Figure 4 through Figure 5.
1 A VSS 2 VDD VSS 3 4 5 ANA1 ANA2 ANA8 VDD 6 ANA4 ANA3 ANA10 ANA11 7 ANA5 ANA6 ANA9 ANA12 8 9 10 11 12 13 14 15 16 17 ANB2 ANB4 ANB14 ANB18 18 ANB3 ANB5 ANB16 ANB21 19 ANB6 ANB19 ANB20 VSS 20 ANB7 ANB23 VSS 21 ANB22 22 VSS A REF– REF– VDDA_ B0 VRL_B VRH_B ANA15 VDDA_A0 VRH_A VRL_A BYPCB1 BYPCB1 REF– REF– VDDA_ B1 VSSA_ B0 ANB0 ANA7 VDDA_A0 VSSA_A1 BYPCA BYPCB ANA13 ANA14 ANA17 ANA16 ANA19 ANA18 ANA21 ANA20 ANA23 ANA22 ANB10 ANB8 ANB9 ANB13 ANB11 ANB15 ANB1 ANB12 ANB17
RSTOUT ANA0 VDD VSS TEST VDD VSS
B VDDEH1
VSS TCRCLKC B ETPUC0 VDDEH7 C
C ETPUA21 ETPUA26
D ETPUA23 ETPUA25 ETPUA31
ETPUC1 ETPUC3 ETPUC2 D
E ETPUA20 ETPUA22 ETPUA24 ETPUA30 F ETPUA13 ETPUA14 ETPUA15 ETPUA27 G ETPUA10 ETPUA11 ETPUA12 ETPUA17 H ETPUA5 ETPUA6 ETPUA9 ETPUA16 J ETPUA1 ETPUA2 ETPUA3 ETPUA4 K TCRCLKA ETPUA0 L VDD VSTBY VSS VSS VSS VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ETPUC5 ETPUC10 ETPUC11 ETPUC4 E
MPC5674F 324 TEPBGA
(as viewed from top through the package)
ETPUC12 ETPUC14 ETPUC13 ETPUC9 F ETPUC20 ETPUC18 ETPUC19 ETPUC17 G VDDEH7 ETPUC23 ETPUC22 ETPUC21 H ETPUC27 ETPUC28 ETPUC26 ETPUC24 J ETPUC31 ETPUC30 ETPUC29 ETPUC25 K ETPUB12 ETPUB13 ETPUB14 VDDEH7 L ETPUB7 ETPUB10 ETPUB11 ETPUB9 M ETPUB0 VDDEH6 ETPUB8 ETPUB6 N TCRCLKB ETPUB16 ETPUB5 ETPUB4 P ETPUB1 ETPUB17 ETPUB3 ETPUB2 R ETPUB19 ETPUB18 VDDEH6 REGCTL T ETPUB31 ETPUB30 VDDREG VSSSYN U VDD REGSEL VSSFL EXTAL V W
BOOTPLLCFG1 PLLCFG2 VDDEH1 CFG1 RDY EVTI MDO1 MDO5 VDDE2
M JCOMP RESET PLLCFG0 N VDDE2 P EVTO MCKO MSEO0 MDO3 MDO7 MSEO1 MDO0 MDO4 MDO8
VDDE2 VDDE2 VDDE2 VDDE2
R MDO2 T MDO6 U MDO9
MDO10 MDO11 MDO15
V MDO12 VDDE2 MDO14 VDD33_2 W Y TDO TCK MDO13 TDI VSS VDD 2 TMS VSS VDD VSS VDD FR_A_ RX VDD FR_A_ TX FR_B_ RX VDDE2 PCSB2 VDDEH4 FR_B_ TX PCSA5 SCKA SINA SCKB SINB VDD EMIOS8 EMIOS9 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC CNRXC CNRXB
VSS
VDD VDD33_3 XTAL VSS SINC VDD VSS
PCSB0 EMIOS2 EMIOS5 EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNRXD EMIOS0 EMIOS3 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA SCKC
VDDSYN Y VDD VSS 22 AA AB
AA ENGCLK AB VSS 1
FR_B_ FR_A_ VDDE2 TX_EN PCSA0 SOUTA SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA SOUTC PCSC0 VDDEH4 CNTXD TX_EN 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Figure 3. MPC5674F 324-ball TEPBGA (full diagram)
MPC5674F Microcontroller Data Sheet, Rev. 6 6 Freescale Semiconductor
Pin Assignments
1 A VSS 2 VDD VSS 3 RSTOUT VDD VSS 4 ANA0 TEST VDD VSS 5 ANA1 ANA2 ANA8 VDD 6 ANA4 ANA3 ANA10 ANA11 7 ANA5 ANA6 ANA9 ANA12 8 9 10 VRH_A 11 VRL_A A
ANA15 VDDA_A0 ANA7 ANA13 ANA14
B VDDEH1
VDDA_A0 VSSA_A1 ANA17 ANA16 ANA19 ANA18
REF– B BYPCA ANA21 ANA20 C D
C ETPUA21 ETPUA26
D ETPUA23 ETPUA25 ETPUA31
E ETPUA20 ETPUA22 ETPUA24 ETPUA30 F ETPUA13 ETPUA14 ETPUA15 ETPUA27 G ETPUA10 ETPUA11 ETPUA12 ETPUA17 H ETPUA5 ETPUA6 ETPUA9 ETPUA16 J ETPUA1 ETPUA2 ETPUA3 ETPUA4 K TCRCLKA ETPUA0 L BOOTCFG1 VDD VSTBY VSS VSS VSS VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS J K L M N P
MPC5674F 324 TEPBGA
(as viewed from top through the package)
PLLCFG1 PLLCFG2 VDDEH1 RESET PLLCFG0 MCKO MSEO0 MDO3 MDO7 MDO10 VDDE2 MDO13 TDI VSS VDD 2 MSEO1 MDO0 MDO4 MDO8 MDO11 RDY EVTI MDO1 MDO5 VDDE2 MDO15
M JCOMP N P R T U VDDE2 EVTO MDO2 MDO6 MDO9
V MDO12 W Y TDO TCK
MDO14 VDD33_2 TMS VSS VDD FR_A_ TX_EN 3 VSS VDD FR_A_ RX VDDE2 4 VDD FR_A_ TX FR_B_ RX FR_B_ TX_EN 5 VDDE2 FR_B_ TX PCSA5 PCSA0 6 PCSB2 SCKA SINA SOUTA 7 VDDEH4 SCKB SINB SOUTB 8 VDD PCSB0 EMIOS8 EMIOS9 W EMIOS2 EMIOS5 Y
AA ENGCLK AB VSS 1
EMIOS0 EMIOS3 EMIOS10 AA EMIOS1 EMIOS4 EMIOS7 AB 9 10 11
Figure 4. MPC5674F 324-ball TEPBGA (1 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 7
Pin Assignments
12 13 14 15 VRL_B ANB0 ANB11 ANB15 16 VRH_B ANB1 ANB12 ANB17 17 ANB2 ANB4 ANB14 ANB18 18 ANB3 ANB5 ANB16 ANB21 19 ANB6 ANB19 ANB20 VSS 20 ANB7 ANB23 VSS 21 ANB22 VSS 22 VSS A
REF– REF– A VDDA_ B0 BYPCB1 BYPCB1 B C D REF– BYPCB VDDA_ B1 VSSA_ B0 ANA23 ANA22 ANB10 ANB8 ANB9 ANB13
TCRCLKC B
ETPUC0 VDDEH7 C
ETPUC1 ETPUC3 ETPUC2 D
ETPUC5 ETPUC10 ETPUC11 ETPUC4 E
MPC5674F 324 TEPBGA
(as viewed from top through the package)
ETPUC12 ETPUC14 ETPUC13 ETPUC9 F ETPUC20 ETPUC18 ETPUC19 ETPUC17 G VDDEH7 ETPUC23 ETPUC22 ETPUC21 H
J K L M N P
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
ETPUC27 ETPUC28 ETPUC26 ETPUC24 J ETPUC31 ETPUC30 ETPUC29 ETPUC25 K ETPUB12 ETPUB13 ETPUB14 VDDEH7 L ETPUB7 ETPUB10 ETPUB11 ETPUB9 M ETPUB0 VDDEH6 ETPUB8 ETPUB6 N TCRCLKB ETPUB16 ETPUB5 ETPUB4 P ETPUB1 ETPUB17 ETPUB3 ETPUB2 R ETPUB19 ETPUB18 VDDEH6 REGCTL T ETPUB31 ETPUB30 VDDREG VSSSYN U VDD REGSEL VDD VSS SINC VDDEH4 20 VSSFL VDD33_3 VDD VSS CNTXD 21 EXTAL XTAL V W
W EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC
CNRXC
CNRXB
VSS CNRXD SCKC PCSC0 19
Y EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB AA EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA AB EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA 12 13 14 15 16 17 SOUTC 18
VDDSYN Y VDD VSS 22 AA AB
Figure 5. MPC5674F 324-ball TEPBGA (2 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 8 Freescale Semiconductor
Pin Assignments
3.2
416-ball TEPBGA Pin Assignments
Figure 6 shows the 416-ball TEPBGA pin assignments in one figure. The same information is shown split into four quadrants in Figure 7 through Figure 10.
1 A VSS 2 3 4 5 ANA4 ANA1 ANA2 VDD 6 ANA8 ANA5 ANA6 ANA3 7 8 9 10 11 12 13 AN28 AN27 AN26 AN25 14 AN32 AN29 AN30 AN31 15 16 17 18 19 20 21 22 23 24 25 26 VSS A REF– VRL_A VRH_A ANA11 ANA15 VDDA_A0 BYPCA1 REF– ANA10 ANA14 VDDA_A1 VSSA_A1 BYPCA ANA9 ANA7 AN24 AN36 VDDA_B0 REF– VRL_B VRH_B ANB7 BYPCB1 AN33 VDDA_B1 VSSA_B0 REF– ANB6 BYPCB AN34 AN35 AN37 AN39 AN38 ANB1 ANB0 ANB2 ANB4 ANB3 ANB8 ANB5 ANB9
VDD RSTOUT ANA0 VDD TEST VDD
ANB11 ANB14 ANB17 ANB21 ANB23 ANB10 ANB15 ANB18 ANB22 ANB12 ANB16 ANB19 ANB13 ANB20 VSS
B VDDEH1 VSS
VSS TCRCLKC B ETPUC0 ETPUC1 C
C ETPUA30 ETPUA31 VSS
ANA13 ANA17 ANA19 ANA21 ANA23 ANA12 ANA16 ANA18 ANA20 ANA22
D ETPUA27 ETPUA28 ETPUA29 VSS E ETPUA23 ETPUA24 ETPUA25 ETPUA26 F ETPUA19 ETPUA20 ETPUA21 ETPUA22 G ETPUA15 ETPUA16 ETPUA17 ETPUA18 H ETPUA11 ETPUA12 ETPUA14 ETPUA13 J ETPUA7 ETPUA8 ETPUA9 ETPUA10 K ETPUA3 ETPUA4 ETPUA5 ETPUA6 L TCRCLKA ETPUA0 ETPUA1 ETPUA2 M VDD33_1 TXDA RXDA VSTBY
VSS VDDEH7 ETPUC2 ETPUC3 D VDDEH7 ETPUC4 ETPUC5 ETPUC6 E ETPUC7 ETPUC8 ETPUC9 ETPUC10 F
MPC5674F 416-ball TEPBGA
(as viewed from top through the package)
ETPUC11 ETPUC12 ETPUC13 ETPUC14 G ETPUC15 ETPUC16 ETPUC17 ETPUC18 H ETPUC19 ETPUC20 ETPUC21 ETPUC22 J
VSS VSS VSS VDDE2
VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
ETPUC23 ETPUC24 ETPUC25 ETPUC26 K ETPUC27 ETPUC28 ETPUC29 ETPUC30 L ETPUC31 ETPUB15 ETPUB14 VDDEH7 M VDDEH6 ETPUB11 ETPUB12 ETPUB13 N ETPUB7 ETPUB8 ETPUB9 ETPUB10 P ETPUB3 ETPUB4 ETPUB5 ETPUB6 R TCRCLKB ETPUB0 ETPUB1 ETPUB2 T ETPUB19 ETPUB18 ETPUB17 ETPUB16 U ETPUB26 ETPUB22 ETPUB21 ETPUB20 V REGSEL ETPUB25 ETPUB24 ETPUB23 W ETPUB29 ETPUB28 ETPUB27 REGCTL Y VDD33_3 ETPUB30 VDDREG VSSSYN AA VDD ETPUB31 VSSFL EXTAL AB
BOOT– N RXDB CFG1 WKPCFG VDD P TXDB PLLCFG1 PLLCFG2 VDDEH1 R JCOMP RESET PLLCFG0 RDY T VDDE2 MCKO MSEO1 U EVTO MSEO0 MDO0 V MDO2 W MDO6 MDO3 MDO7 MDO4 EVTI MDO1 MDO5
VDDE2 VDDE2 VDDE2 VDDE2
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
MDO8 VDDE2
Y MDO9 MDO10 MDO11 MDO15 AA MDO12 MDO13 MDO14 VDD33_2 AB TDO TCK TDI TMS VDD VSS VDD VSS VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1
AC VDDE2
VSS
VDD VDDEH6 XTAL AC VSS VDD VDDSYN AD VSS VDD AE AF
AD ENGCLK VDD AE AF VDD VSS 1 VSS
FR_A_ FR_B_ PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2 EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC TX TX SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0
RXDC PCSC3 SINC
FR_A_ FR_B_ PCSA4 PCSA0 PCSA3 SCKB RX RX SINA 7
PCSC2 PCSC5
FR_A_ FR_B_ VDDE2 TX_EN TX_EN VDDEH3 PCSB5 2 3 4 5 6
PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 6. MPC5674F 416-ball TEPBGA (full diagram)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 9
Pin Assignments
1 A VSS
2 VDD
3 RSTOUT
4 ANA0
5 ANA4
6 ANA8
7 ANA11
8
9
10 REFBYPCA1
11 VRL_A
12 VRH_A
13 AN28 A
ANA15 VDDA_A0
B VDDEH1
VSS
VDD
TEST
ANA1
ANA5
ANA10
ANA14 VDDA_A1 VSSA_A1 REFBYPCA
AN24
AN27
B
C ETPUA30 ETPUA31
VSS
VDD
ANA2
ANA6
ANA9
ANA13
ANA17
ANA19
ANA21
ANA23
AN26
C
D ETPUA27 ETPUA28 ETPUA29
VSS
VDD
ANA3
ANA7
ANA12
ANA16
ANA18
ANA20
ANA22
AN25
D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26
E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22
F
MPC5674F 416-ball TEPBGA
G ETPUA15 ETPUA16 ETPUA17 ETPUA18
(as viewed from top through the package) (1 of 4)
G
H ETPUA11 ETPUA12 ETPUA14 ETPUA13
H
J ETPUA7 ETPUA8 ETPUA9 ETPUA10
J
K ETPUA3 ETPUA4 ETPUA5 ETPUA6
VSS
VSS
VSS
VSS
K
L TCRCLKA ETPUA0 ETPUA1 ETPUA2
VSS
VSS
VSS
VSS
L
M VDD33_1
TXDA
RXDA
VSTBY
VSS
VSS
VSS
VSS
M
N
RXDB BOOTCFG1 WKPCFG 1 2 3
VDD 4 5 6 7 8 9
VDDE2 10
VSS 11
VSS 12
VSS 13
N
Figure 7. MPC5674F 416-ball TEPBGA (1 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 10 Freescale Semiconductor
Pin Assignments
14 A AN32
15 AN36
16 VDDA_B0
17 REFBYPCB1
18 VRL_B
19 VRH_B
20 ANB7
21 ANB11
22 ANB14
23 ANB17
24 ANB21
25 ANB23
26 VSS A
B
AN29
AN33
VDDA_B1 VSSA_B0 REFBYPCB ANB6
ANB8
ANB10
ANB15
ANB18
ANB22
VSS
TCRCLKC B
C
AN30
AN34
AN37
AN38
ANB0
ANB4
ANB5
ANB12
ANB16
ANB19
VSS
ETPUC0 ETPUC1 C
D
AN31
AN35
AN39
ANB1
ANB2
ANB3
ANB9
ANB13
ANB20
VSS
VDDEH7 ETPUC2 ETPUC3 D
E
VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F
ETPUC7 ETPUC8 ETPUC9 ETPUC10 F
MPC5674F 416-ball TEPBGA
G
(as viewed from top through the package) (2 of 4)
ETPUC11 ETPUC12 ETPUC13 ETPUC14 G
H
ETPUC15 ETPUC16 ETPUC17 ETPUC18 H
J
ETPUC19 ETPUC20 ETPUC21 ETPUC22 J
K
VSS
VSS
VSS
VSS
ETPUC23 ETPUC24 ETPUC25 ETPUC26 K
L
VSS
VSS
VSS
VSS
ETPUC27 ETPUC28 ETPUC29 ETPUC30 L
M
VSS
VSS
VSS
VSS
ETPUC31 ETPUB15 ETPUB14 VDDEH7 M
N
VSS 14
VSS 15
VSS 16
VSS 17 18 19 20 21 22
VDDEH6 ETPUB11 ETPUB12 ETPUB13 N 23 24 25 26
Figure 8. MPC5674F 416-ball TEPBGA (2 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 11
Pin Assignments
1 P TXDB
2
3
4
5
6
7
8
9
10 VDDE2
11 VDDE2
12 VSS
13 VSS P
PLLCFG1 PLLCFG2 VDDEH1
R
JCOMP
RESET PLLCFG0
RDY
VDDE2
VDDE2
VSS
VSS
R
T
VDDE2
MCKO
MSEO1
EVTI
VDDE2
VDDE2
VDDE2
VSS
T
U
EVTO
MSEO0
MDO0
MDO1
VDDE2
VDDE2
VDDE2
VSS
U
V
MDO2
MDO3
MDO4
MDO5
V
W
MDO6
MDO7
MDO8
VDDE2
W
MPC5674F 416-ball TEPBGA
Y MDO9 MDO10 MDO11 MDO15
(as viewed from top through the package) (3 of 4)
Y
AA
MDO12
MDO13
MDO14 VDD33_2
AA
AB
TDO
TCK
TMS
VDD
AB
AC
VDDE2
TDI
VDD
VSS
VDDE2
PCSA1
PCSA2
PCSB4
PCSB1 VDDEH3 VDDEH4
VDD
EMIOS8 AC
AD ENGCLK
VDD
VSS
FR_A_TX FR_B_TX PCSA5
SOUTA
SCKA
PCSB0
PCSB3
EMIOS2 EMIOS5 EMIOS9 AD
AE
VDD
VSS
FR_A_RX FR_B_RX PCSA4 FR_A_ TX_EN 3 FR_B_ TX_EN 4
PCSA0
PCSA3
SCKB
SINB
EMIOS0 EMIOS3 EMIOS6 EMIOS10 AE
AF
VSS 1
VDDE2 2
VDDEH3 5
PCSB5 6
SINA 7
PCSB2 8
SOUTB 9
EMIOS1 EMIOS4 EMIOS7 EMIOS11 AF 10 11 12 13
Figure 9. MPC5674F 416-ball TEPBGA (3 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 12 Freescale Semiconductor
Pin Assignments
14 P VSS
15 VSS
16 VSS
17 VSS
18
19
20
21
22
23
24
25
26
ETPUB7 ETPUB8 ETPUB9 ETPUB10 P
R
VSS
VSS
VSS
VSS
ETPUB3 ETPUB4 ETPUB5 ETPUB6 R
T
VSS
VSS
VSS
VSS
TCRCLKB ETPUB0 ETPUB1 ETPUB2 T
U
VSS
VSS
VSS
VSS
ETPUB19 ETPUB18 ETPUB17 ETPUB16 U
V
ETPUB26 ETPUB22 ETPUB21 ETPUB20 V
W
REGSEL ETPUB25 ETPUB24 ETPUB23 W
MPC5674F 416-ball TEPBGA
Y
(as viewed from top through the package) (4 of 4)
ETPUB29 ETPUB28 ETPUB27 REGCTL Y
AA
VDD33_3 ETPUB30 VDDREG VSSSYN AA
AB
VDD
ETPUB31 VSSFL
EXTAL
AB
AC EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB
CNRXD VDDEH5 PCSC1
VSS
VDD
VDDEH6
XTAL
AC
AD EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB
CNTXD
SCKC
RXDC
PCSC3
VSS
VDD
VDDSYN AD
AE EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA
CNRXC
PCSC0
SINC
PCSC2
PCSC5
VSS
VDD
AE
AF EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA 14 15 16 17 18 19
CNTXC 20
SOUTC VDDEH4 21 22
TXDC 23
PCSC4 VDDEH5 24 25
VSS 26
AF
Figure 10. MPC5674F 416-ball TEPBGA (4 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 13
Pin Assignments
3.3
516-ball TEPBGA Pin Assignments
Figure 11 shows the 516-ball TEPBGA pin assignments in one figure. The same information is shown split into four quadrants in Figure 12 through Figure 15.
1 A 2 3 4 5 ANA4 ANA1 ANA2 VDD 6 ANA9 ANA5 ANA6 ANA3 VDD VDDE8 7 8 9 10 11 12 13 AN28 AN27 AN25 AN26 VSS VSS 14 AN29 AN30 AN31 AN33 VSS VSS 15 16 17 18 19 20 21 ANB9 22 23 24 25 VSS VSS VSS 26 A B REF– VRL_A VRH_A BYPCA1 REF– BYPCA AN24 REF– VRL_B VRH_B ANB5 BYPCB1 REF– ANB4 BYPCB ANB0 ANB2 VSS ANB7 ANB3 VSS VDDE10 ANB8 ANB6
VDD RSTOUT ANA0 VDD TEST VDD
ANA11 ANA15 VDDA_A0
AN36 VDDA_B0
ANB12 ANB18 ANB21
B VDDEH1 VSS
ANA10 ANA14 VDDA_A1 VSSA_A1 ANA7 ANA8 VSS
AN32 VDDA_B1 VSSA_B0 AN34 AN35 VSS AN39 AN38 VSS AN37 ANB1 VSS
ANB10 ANB13 ANB19 ANB22 ANB11 ANB15 ANB20
C ETPUA30 ETPUA31 VSS
ANA13 ANA17 ANA19 ANA21 ANA22 ANA12 ANA16 ANA18 ANA20 ANA23 VSS VDDE8 VSS VSS VSS VSS
VSS ETPUC0 ETPUC1 C
D ETPUA27 ETPUA28 ETPUA29 VSS
ANB14 ANB16 ANB17 ANB23 VSS
VSS VDDEH7 ETPUC2 ETPUC3 D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS F ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18
VSS VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
VDDE8 VDDE8
VDDE10 VDDE10
VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J
MPC5674F 516-ball TEPBGA
(as viewed from top through the package)
H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16 J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12 K TXDB TXDA RXDA TCRCLKA ETPUA6 ETPUA10
VSS VSS VSS VDDE2
VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7 M VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 N VDDE10 ETPUB13 D_OE D_ALE D_DAT0 D_DAT1 P
BOOT– BOOT– L PLLCFG1 PLLCFG2 CFG1 CFG0 RXDB ETPUA0 M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG N D_WE0 D_WE2 D_WE3 VDD RESET VDDE8
P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1 R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16 T VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3 U D_CS2 JCOMP V EVTI EVTO MDO5 RDY MDO0 MCKO MSEO1 MSEO0 MDO2 MDO3 MDO1
VDDE2 VDDE2 VDDE2 VDDE2
D_RD_ ETPUB9 ETPUB12 ETPUB14 ETPUB15 WR R ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
W MDO4 Y MDO7
MDO6 VDDE2 MDO8
MDO9 MDO10 MDO11 MDO12 VSS PCSA5 SINB SOUTB VDD33_4 VDDE9 VDD33_4 EMIOS23 EMIOS31 CNRXB VSS
AA MDO13 MDO14 MDO15 VDD33_1 VDDE8 AB TDO TCK TDI TMS VDD VSS VDD VSS VSS
VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA VSS VDD ETPUB30 VSSFL EXTAL AB VSS VDD VDDEH6 XTAL AC VSS VDD VDDSYN AD VSS VDD AE AF 26
VDDE9 VDDE9 SCKA
D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9
AC VDDE2
VDDE2 PCSA1 SOUTA SCKB PCSB3 VDDEH3 VDDEH4 VDD
EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1
AD ENGCLK VDD AE AF 1 VDD VSS VDDE2 2
FR_A_ FR_B_ PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD SCKC TX TX SINA PCSB1 D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0
RXDC PCSC3 SINC
FR_A_ FR_B_ PCSA4 PCSB5 RX RX
PCSC2 PCSC5
FR_A_ FR_B_ VDDEH3 PCSA2 PCSB4 PCSB0 TX_EN TX_EN 3 4 5 6 7 8
D_ D_TA D_ADD24 D_ADD27 CLKOUT EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Figure 11. MPC5674F 516-ball TEPBGA (full diagram)
MPC5674F Microcontroller Data Sheet, Rev. 6 14 Freescale Semiconductor
Pin Assignments
1 A
2 VDD
3 RSTOUT
4 ANA0
5 ANA4
6 ANA9
7 ANA11
8
9
10 REFBYPCA1
11 VRL_A
12 VRH_A
13 AN28 A
ANA15 VDDA_A0
B VDDEH1
VSS
VDD
TEST
ANA1
ANA5
ANA10
ANA14 VDDA_A1 VSSA_A1 REFBYPCA
AN24
AN27
B
C ETPUA30 ETPUA31
VSS
VDD
ANA2
ANA6
ANA7
ANA13
ANA17
ANA19
ANA21
ANA22
AN25
C
D ETPUA27 ETPUA28 ETPUA29
VSS
VDD
ANA3
ANA8
ANA12
ANA16
ANA18
ANA20
ANA23
AN26
D
E ETPUA23 ETPUA24 ETPUA25 ETPUA26
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E
F ETPUA19 ETPUA20 ETPUA21 ETPUA22
VSS
VDDE8
VDDE8
VDDE8
VDDE8
VSS
F
G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18
MPC5674F 516-ball TEPBGA
(as viewed from top through the package) (1 of 4)
G
H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16
H
J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12
J
K
TXDB
TXDA
RXDA
TCRCLKA ETPUA6 ETPUA10
VSS
VSS
VSS
VSS
K
L PLLCFG1 PLLCFG2 BOOTCFG1 BOOTCFG0 RXDB
ETPUA0
VSS
VSS
VSS
VSS
L
M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG
VSS
VSS
VSS
VSS
M
N
D_WE0 1
D_WE2 2
D_WE3 3
VDD 4
RESET 5
VDDE8 6 7 8 9
VDDE2 10
VSS 11
VSS 12
VSS 13
N
Figure 12. MPC5674F 516-ball TEPBGA (1 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 15
Pin Assignments
14 A AN29
15 AN36
16 VDDA_B0
17 REFBYPCB1
18 VRL_B
19 VRH_B
20 ANB5
21 ANB9
22 ANB12
23 ANB18
24 ANB21
25 VSS
26 A
B
AN30
AN32
VDDA_B1 VSSA_B0 REFBYPCB ANB4
ANB8
ANB10
ANB13
ANB19
ANB22
VSS
VSS
B
C
AN31
AN34
AN39
AN37
ANB0
ANB7
ANB6
ANB11
ANB15
ANB20
VSS
ETPUC0 ETPUC1 C
D
AN33
AN35
AN38
ANB1
ANB2
ANB3
ANB14
ANB16
ANB17
VSS
VDDEH7 ETPUC2 ETPUC3 D
E
VSS
VSS
VSS
VSS
VSS
VSS
ANB23
VSS
VSS
VDDEH7 ETPUC4 ETPUC5 ETPUC6 E
F
VSS
VDDE10 VDDE10
VDDE10
VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F
MPC5674F 516-ball TEPBGA
G
(as viewed from top through the package) (2 of 4)
ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G
H
ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H
J
ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J
K
VSS
VSS
VSS
VSS
ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K
L
VSS
VSS
VSS
VSS
VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L
M
VSS
VSS
VSS
VSS
D_DAT9 D_DAT8
D_DAT7 D_DAT5 VDDEH7 M
N
VSS 14
VSS 15
VSS 16
VSS 17 18 19 20
VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 21 22 23 24 25 26
N
Figure 13. MPC5674F 516-ball TEPBGA (2 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 16 Freescale Semiconductor
Pin Assignments
1
2
3
4
5
6
7
8
9
10 VDDE2
11 VDDE2
12 VSS
13 VSS P
P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1
R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16
VDDE2
VDDE2
VSS
VSS
R
T
VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3
VDDE2
VDDE2
VDDE2
VSS
T
U
D_CS2
JCOMP
RDY
MCKO
MSEO1
MSEO0
VDDE2
VDDE2
VDDE2
VSS
U
V
EVTI
EVTO
MDO0
MDO2
MDO3
MPC5674F 516-ball TEPBGA
MDO1
(as viewed from top through the package) (3 of 4)
V
W
MDO4
MDO5
MDO6
VDDE2
MDO8
W
Y
MDO7
MDO9
MDO10
MDO11
MDO12
Y
AA
MDO13
MDO14
MDO15 VDD33_1 VDDE8
VSS
PCSA5
SOUTB VDD33_4
VDDE9
AA
AB
TDO
TCK
TMS
VDD
VSS
VDDE9
VDDE9
SCKA
SINB
D_CS1 D_ADD21 D_ADD29 EMIOS1 AB
AC
VDDE2
TDI
VDD
VSS
VDDE2
PCSA1
SOUTA
SCKB
PCSB3
VDDEH3 VDDEH4
VDD
EMIOS0 AC
AD ENGCLK
VDD
VSS
FR_A_TX FR_B_TX PCSA0
PCSA3
PCSB2
D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 AD
AE
VDD
VSS
FR_A_RX FR_B_RX PCSA4 FR_A_ TX_EN 3 FR_B_ TX_EN 4
PCSB5
SINA
PCSB1
D_TS
D_ADD23 D_ADD26 D_ADD30 EMIOS3 AE
AF 1
VDDE2 2
VDDEH3 5
PCSA2 6
PCSB4 7
PCSB0 8
D_TA 9
D_ADD24 D_ADD27 D_CLKOUT EMIOS4 AF 10 11 12 13
Figure 14. MPC5674F 516-ball TEPBGA (3 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 17
Pin Assignments
14 P VSS
15 VSS
16 VSS
17 VSS
18
19
20
21
22
23 D_OE
24 D_ALE
25 D_DAT0
26 D_DAT1 P
VDDE10 ETPUB13
R
VSS
VSS
VSS
VSS
ETPUB9 ETPUB12 ETPUB14 ETPUB15 D_RD_WR R
T
VSS
VSS
VSS
VSS
ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T
U
VSS
VSS
VSS
VSS
ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U
V
MPC5674F 516-ball TEPBGA
(as viewed from top through the package) (4 of 4)
ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V
W
ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W
Y
ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y
AA VDD33_4
EMIOS23 EMIOS31
CNRXB
VSS
VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA
AB EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9
VDDE9
VDDE9
VDDE9
VSS
VDD
ETPUB30 VSSSFL
EXTAL
AB
AC EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB
CNRXD VDDEH5 PCSC1
VSS
VDD
VDDEH6
XTAL
AC
AD EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA
CNTXD
SCKC
RXDC
PCSC3
VSS
VDD
VDDSYN AD
AE EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA
CNRXC
PCSC0
SINC
PCSC2
PCSC5
VSS
VDD
AE
AF EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC 14 15 16 17 18 19 20
SOUTC VDDEH4 21 22
TXDC 23
PCSC4 VDDEH5 24 25 26
AF
Figure 15. MPC5674F 516-ball TEPBGA (4 of 4)
MPC5674F Microcontroller Data Sheet, Rev. 6 18 Freescale Semiconductor
Pin Assignments
3.4
SignalProperties and Muxing
See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 19
Electrical Characteristics
4
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5674F. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.
4.1
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Maximum Ratings
Table 3. Absolute Maximum Ratings1
Characteristic 1.2 V Core Supply Voltage3 SRAM Standby Voltage Clock Synthesizer Voltage I/O Supply Voltage (I/O buffers and predrivers) Analog Supply Voltage (reference to VSSA8) I/O Supply Voltage (fast I/O pads) I/O Supply Voltage (medium I/O pads) Voltage Regulator Input Supply Voltage Analog Reference High Voltage (reference to VRL10) VSS to VSSA8 Differential Voltage VREF Differential Voltage VRL to VSSA Differential Voltage VDD33 to VDDSYN Differential Voltage VSSSYN to VSS Differential Voltage Maximum Digital Input Current 12 (per pin, applies to all digital pins) Maximum Analog Input Current 14 (per pin, applies to all analog pins) Maximum Operating Temperature Range 15 – Die Junction Temperature Storage Temperature Range Maximum Solder Temperature 16 Pb-free package SnPb package Moisture Sensitivity Level 17 Symbol VDD VSTBY VDDSYN VDD33 VDDA9 VDDE VDDEH VDDREG VRH11 VSS – VSSA VRH – VRL VRL – VSSA VDD33 – VDDSYN VSSSYN – VSS IMAXD IMAXA TJ Tstg Tsdr — — MSL — 260.0 245.0 3 — Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.1 –0.3 –0.3 –0.1 –0.1 –3 13 –39 –40.0 –55.0 Max2 1.65 4 6.4 5,6 4.5 6,7 4.5 6,7 6.4 5,6 4.5 6,7 6.4
5,6
Unit V V V V V V V V V V V V V V mA mA
oC
6.4 5,6 6.4 5,6 0.1 6.4 5,6 0.3 0.1 0.1 3 13 3 9,13 150.0 150.0
oC o
C
20
MPC5674F Microcontroller Data Sheet, Rev. 6 20 Freescale Semiconductor
Electrical Characteristics
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.2 V ±10% for proper operation. This parameter is specified at a maximum junction temperature of 150 °C. 4 1.65 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 6 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 7 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 8 MPC5674F has two analog power supply pins on the pinout: VDDA_A and VDDA_B. 9 MPC5674F has two analog ground supply pins on the pinout: VSSA_A and VSSA_B. 10 MPC5674F has two analog low reference voltage pins on the pinout: VRL_A and VRL_B. 11 MPC5674F has two analog high reference voltage pins on the pinout: VRH_A and VRH_B. 12 Total injection current for all pins must not exceed 25 mA at maximum operating voltage. 13 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under this stress condition. 14 Total injection current for all analog input pins must not exceed 15 mA. 15 Lifetime operation at these specification limits is not guaranteed. 16 Solder profile per CDF-AEC-Q100. 17 Moisture sensitivity per JEDEC test method A112.
4.2
Thermal Characteristics
Table 4. Thermal Characteristics, 416-pin TEPBGA Package1
Characteristic Junction to Ambient 2,3 Natural Convection (Single layer board) Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) Junction to Ambient (@200 ft./min., Single layer board) Junction to Ambient (@200 ft./min., Four layer board 2s2p) Junction to Board 5 Junction to Case 6 Junction to Package Top
1 2 7
Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC
Value 24 18 19 14 9 6 2
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Natural Convection
ΨJT
3 4 5
Thermal characteristics are targets based on simulation that are subject to change per device characterization. This data is PRELIMINARY based on similar package used on other devices. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 21
Electrical Characteristics
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 7 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
Table 5. Thermal Characteristics, 516-pin TEPBGA Package1
Characteristic Junction to Ambient 2,3 Natural Convection (Single layer board) Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) Junction to Ambient (@200 ft./min., Single layer board) Junction to Ambient (@200 ft./min., Four layer board 2s2p) Junction to Board 5 Junction to Case 6 Junction to Package Top 7 Natural Convection
1 2
Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT
Value 25 18 20 15 10 6 2
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
3 4 5 6
7
Thermal characteristics are targets based on simulation that are subject to change per device characterization. This data is PRELIMINARY based on similar package used on other devices. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
Table 6. Thermal Characteristics, 324-pin Package1
MPC5567 Thermal Characteristic Junction to ambient Junction to ambient
2, 3, 1, 4,
Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT
Value 29 19 23 16 10 7 2
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
natural convection (one-layer board) natural convection (four-layer board 2s2p)
Junction to ambient (@200 ft./min., one-layer board) Junction to ambient (@200 ft./min., four-layer board 2s2p) Junction to board (four-layer board 2s2p) Junction to case
1 6 7, 5
Junction to package top
natural convection
Thermal characteristics are targets based on simulation that are subject to change per device characterization. This data is PRELIMINARY based on similar package used on other devices.
MPC5674F Microcontroller Data Sheet, Rev. 6 22 Freescale Semiconductor
Electrical Characteristics
2
3 4 5 6
7
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
4.2.1
General Notes for Specifications at Maximum Junction Temperature
TJ = TA + (RθJA * PD) Eqn. 1
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction to ambient thermal resistance (oC/W) RθJC = junction to case thermal resistance (oC/W) RθCA = case to ambient thermal resistance (oC/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT x PD) Eqn. 3 Eqn. 2
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 23
Electrical Characteristics
where: TT = thermocouple temperature on top of the package (oC) ΨJT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. • • • C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
4.3
EMI (Electromagnetic Interference) Characteristics
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's radiated emissions operating behaviors. Table 7. EMC Radiated Emissions Operating Behaviors: 416 BGA
Symbol VRE_TEM Description Radiated emissions, electric field and magnetic field Conditions VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 416 BGA EBI off CLK on FM off fOSC fSYS 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 IEC and SAE level Level (max.) 26 30 34 30 I2 —
1, 3
Unit Notes dBμV
1
MPC5674F Microcontroller Data Sheet, Rev. 6 24 Freescale Semiconductor
Electrical Characteristics
Table 7. EMC Radiated Emissions Operating Behaviors: 416 BGA (continued)
Symbol VRE_TEM Description Radiated emissions, electric field and magnetic field Conditions VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 416 BGA EBI off CLK off FM on4 fOSC fSYS 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 IEC and SAE level Level (max.) 24 25 25 21 K5 —
1,3
Unit Notes dBμV
1
1
2 3
4 5
Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. I = 36 dBμV Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. “FM on” = FM depth of ±2% K = 30 dBμV
Table 8. EMC Radiated Emissions Operating Behaviors: 516 BGA
Symbol VRE_TEM Description Radiated emissions, electric field and magnetic field Conditions VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 516 BGA EBI on CLK on FM off VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 516 BGA EBI on CLK on FM on4 fOSC fSYS 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 IEC and SAE level 40 MHz crystal 264 MHz (fEBI_CAL = 66 MHz) 0.15–50 50–150 150–500 500–1000 IEC and SAE level Level (max.) 40 48 48 47 G2 40 44 41 36 G2 —
1, 3
Unit Notes dBμV
1
— dBμV
1, 3
VRE_TEM
Radiated emissions, electric field and magnetic field
1
Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. 2 G = 48 dBμV 3 Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. 4 “FM on” = FM depth of ±2%
1
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 25
Electrical Characteristics
4.4
ESD Characteristics
Table 9. ESD Ratings1,2
Spec 1 2
1
Characteristic ESD for Human Body Model (HBM) ESD for Charged Device Model (CDM)
Symbol VHBM VCDM
Value 2000 750 (corners) 250 (other)
Unit V V
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
4.5
PMC/POR/LVI Electrical Specifications
Note: For ADC internal resource measurements, see Table 21 in Section 4.9.1, “ADC Internal Resource Measurements.”
Table 10. PMC Operating conditions
Name VDDREG VDDREG VDD33 VDD
1
Parameter
Condition
Min 4.5 3.0 3.0 1.14
Typ 5 3.3 3.3 1.2
Max 5.5 3.6 3.6 1.32
Unit V V V V
1
Note
Supply voltage VDDREG LDO5V / SMPS5V mode 5V nominal Supply voltage VDDREG LDO3V mode 3V nominal Supply voltage VDDSYN / LDO3V mode VDD33 3.3V nominal Supply voltage VDD 1.2V nominal —
1
2
3
Voltage should be higher than maximum VLVDREG to avoid LVD event Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33 to avoid LVD event 3 Voltage should be higher than maximum V LVD12 to avoid LVD event
2
NOTE
In the following table, "untrimmed” means “at reset" and "trimmed” means “after reset". Table 11. PMC Electrical Specifications
ID 1 1a 2 Name VBG — VDD12OUT Parameter Nominal bandgap reference voltage Untrimmed bandgap reference voltage Nominal VRC regulated 1.2V output VDD Min — VBG – 5% — Typ 0.620 VBG 1.2 Max — VBG + 5% — Unit V V V
MPC5674F Microcontroller Data Sheet, Rev. 6 26 Freescale Semiconductor
Electrical Characteristics
Table 11. PMC Electrical Specifications (continued)
ID 2a — Name Parameter Untrimmed VRC 1.2V output variation before band gap trim (unloaded) Note: Voltage should be higher than maximum VLVD12 to avoid LVD event Trimmed VRC 1.2V output variation after band gap trim (REGCTL load max. 20mA, VDD load max. 1A)1 Trimming step VDD12OUT POR rising VDD 1.2V POR VDD 1.2V variation POR 1.2V hysteresis Nominal rising LVD 1.2V Note: ~VDD12OUT × 0.87 Untrimmed LVD 1.2V variation before band gap trim Note: Rising VDD Trimmed LVD 1.2V variation after band gap trim Rising VDD LVD 1.2V Hysteresis Trimming step LVD 1.2V VRC DC current output on REGCTL Voltage regulator 1.2V current consumption VDDREG Nominal VREG 3.3V output Untrimmed VREG 3.3V output variation before band gap trim (unloaded) Note: Rising VDDSYN Trimmed VREG 3.3V output variation after band gap trim (max. load 80mA) Trimming step VDDSYN Nominal rising LVD 3.3V Note: ~VDD33OUT × 0.872 Untrimmed LVD 3.3V variation before band gap trim Note: Rising VDDSYN Trimmed LVD 3.3V variation after bad gap trim Note: Rising VDDSYN LVD 3.3V Hysteresis Trimming step LVD 3.3V Min Typ Max Unit V
VDD12OUT – 8% VDD12OUT VDD12OUT + 10%
2b
—
VDD12OUT – 5% VDD12OUT VDD12OUT + 10%
V
2c 3 3a 3b 4 4a 4b 4c 4d 5 6 7 7a
VSTEPV12 VPORC — — VLVD12 — — — VLVDSTEP12 IREGCTL — VDD33OUT —
— — VPORC – 30% — — VLVD12 – 6% VLVD12 – 3% 15 — — — —
10 0.7 VPORC 75 1.100 VLVD12 VLVD12 20 10 — 3 3.3
— — VPORC + 30% — — VLVD12 + 6% VLVD12 + 3% 25 — 20 — —
mV V
mV V V V mV mV mA mA V V
VDD33OUT – 6% VDD33OUT VDD33OUT + 10%
7b 7c 8 8a 8b 8c 8d
— VSTEPV33 VLVD33 — — — VLVDSTEP33
VDD33OUT – 5% VDD33OUT VDD33OUT + 10% — — VLVD33 – 5% VLVD33 – 3% — — 30 2.950 VLVD33 VLVD33 30 30 — — VLVD33 + 5% VLVD33 + 3% — —
V mV V V V mV mV
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 27
Electrical Characteristics
Table 11. PMC Electrical Specifications (continued)
ID 9 Name IDD33 Parameter VREG 3.3V max DC output current Note: Max current supplied by VDDSYN that does not cause it to drop below VLVD33 Voltage regulator 3.3V current consumption VDDREG Note: Except IDD33 POR rising on VDDREG POR VDDREG variation POR VDDREG hysteresis Nominal rising LVD VDDREG (LDO3V / LDO5V mode) Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG LVD VDDREG Hysteresis (LDO3V / LDO5V mode) Min — Typ — Max 60 Unit mA
10
—
—
2
—
mA
11
VPORREG
—
2.00
—
V V mV V V
11a — 11b — 12 VLVDREG
VPORREG – 30% VPORREG VPORREG + 30% — — VLVDREG – 5% 250 2.950 VLVDREG — — VLVDREG + 5%
12a —
12b —
VLVDREG – 3%
VLVDREG
VLVDREG + 3%
V
12c —
— — — VLVDREG – 5%
30 30 4.360 VLVDREG
— — — VLVDREG + 5%
mV mV V V
12d VLVDSTEPREG Trimming step LVD VDDREG (LDO3V / LDO5V mode) 13 VLVDREG Nominal rising LVD VDDREG (SMPS5V mode) Untrimmed LVD VDDREG variation before band gap trim Note: Rising VDDREG Trimmed LVD VDDREG variation after band gap trim Note: Rising VDDREG LVD VDDREG Hysteresis (SMPS5V mode)
13a —
13b —
VLVDREG – 3%
VLVDREG
VLVDREG + 3%
V
13c —
— — — VLVDA – 5% VLVDA – 3% — —
50 50 4.60 VLVDA VLVDA 150 20
— — — VLVDA + 5% VLVDA + 3% — —
mV mV V V V mV mV
13d VLVDSTEPREG Trimming step LVD VDDREG (SMPS5V mode) 14 VLVDA Nominal rising LVD VDDA Untrimmed LVD VDDA variation before band gap trim Trimmed LVD VDDA variation after band gap trim LVD VDDA Hysteresis Trimming step LVD VDDA
14a — 14b — 14c — 14d VLVDASTEP
MPC5674F Microcontroller Data Sheet, Rev. 6 28 Freescale Semiconductor
Electrical Characteristics
Table 11. PMC Electrical Specifications (continued)
ID 15 — Name Parameter SMPS regulator output resistance Note: Pulup to VDDREG when high, pulldown to VSSREG when low. SMPS regulator clock frequency (after reset) SMPS regulator overshoot at start-up2 SMPS maximum output current Voltage variation on current step2 (20% to 80% of maximum current with 4 usec constant time) Min — Typ 15 Max 25 Unit Ohm
16 17 18 19
1
— — — —
1.0 — — —
1.5 1.32 1.0 —
2.0 1.4 — 0.1
MHz V A V
VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 uA. When using the recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core voltage is up to 1A. 2 Parameter cannot be tested; this value is based on simulation and characterization.
4.6
• •
Power Up/Down Sequencing
When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG. When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the internal 3.3V regulator.
There is no power sequencing required among power sources during power up and power down in order to operate within specification as long as the following two rules are met:
The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH supplies. There is no limit on the fall time for the power supplies. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to Table 12 and Table 13. Table 12. Power Sequence Pin States for MH and AE pads
VDD High — VDD33 High Low VDDE High High MH Pad Normal operation Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) Output low, pin unpowered Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) MH+LVDS Pads1 Normal operation Outputs driven high AE/up-down Pads Normal operation Pull-ups enabled, pull-downs disabled Output low, pin unpowered Pull-ups enabled, pull-downs disabled
Low Low
High High
Low High
Outputs disabled Outputs disabled
1
MH+LVDS pads are output-only.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 29
Electrical Characteristics
Table 13. Power Sequence Pin States for F and FS pads
VDD low low high high high high
1
VDD33 low high low low high high
VDDE high — low high low high
F and FS pads Outputs drive high Outputs Disabled Outputs Disabled Outputs drive high Normal operation - except no drive current and input buffer output is unknown.1 Normal Operation
The pad pre-drive circuitry will function normally but since VDDE is unpowered the outputs will not drive high even though the output pmos can be enabled.
4.6.1
Power-Up
If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit the characteristics described in the next paragraph. If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up. The rise times on the power supplies are to be no faster than 25 V/millisecond.
4.6.2
Power-Down
If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before VDDE/VDDEH must power down. If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down. There are no limits on the fall times for the power supplies.
4.6.3
Power Sequencing and POR Dependent on VDDA
During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH is more than 1 V, the following will result: • Triggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created, when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect level. If VDDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part out of reset. Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH – VDDA – 1 V(diode drop)/200 KOhms) up to (VDDEH/2 = VDDA + 1 V).
• •
MPC5674F Microcontroller Data Sheet, Rev. 6 30 Freescale Semiconductor
Electrical Characteristics
•
Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor since VDD = 1.32 V max.
4.7
Spec 1 1a 2 3 4 5 6a 6b 7 8 9
DC Electrical Specifications
Table 14. DC Electrical Specifications1
Characteristic Core Supply Voltage (External Regulation) Core Supply Voltage (Internal Regulation)4 I/O Supply Voltage (fast I/O pads) I/O Supply Voltage (medium I/O pads) 3.3 V I/O Buffer Voltage Analog Supply Voltage SRAM Standby Voltage Keep-out Range: 1.2V–2V SRAM Standby Voltage Keep-out Range: 1.2V–2V Voltage Regulator Control Input Voltage8 Clock Synthesizer Operating Voltage10 Fast I/O Input High Voltage Hysteresis enabled Hysteresis disabled Fast I/O Input Low Voltage Hysteresis enabled Hysteresis disabled Medium I/O Input High Voltage Hysteresis enabled Hysteresis disabled Medium I/O Input Low Voltage Hysteresis enabled Hysteresis disabled Fast I/O Input Hysteresis Medium I/O Input Hysteresis Analog Input Voltage Fast I/O Output High Voltage11 Medium I/O Output High Voltage12 Fast I/O Output Low Voltage11 Medium I/O Output Low Voltage12 Symbol VDD VDD VDDE VDDEH VDD33 VDDA VSTBY_LOW VSTBY_HIGH VDDREG VDDSYN VIH_F 0.65 × VDDE 0.55 × VDDE VIL_F VSS – 0.3 0.35 × VDDE 0.40 × VDDE VIH_S 0.65 × VDDEH 0.55 × VDDEH VIL_S VSS – 0.3 0.35 × VDDEH 0.40 × VDDEH VHYS_F VHYS_S VINDC VOH_F VOH_S VOL_F VOL_S 0.1 × VDDE 0.1 × VDDEH VSSA – 0.1 0.8 × VDDE 0.8 × VDDEH — — — — VDDA + 0.1 — — 0.2 × VDDE 0.2 × VDDEH V V V V V V V V VDDEH + 0.3 V V Min 1.14 1.08 3.0 3.0 3.0 4.75 0.957 2 2.79 3.0 Max 1.322, 3 1.32 3.62, 5 5.252, 6 3.62, 5 5.252, 6 1.2 6 5.52, 6 3.62, 5 VDDE + 0.3 Unit V V V V V V V V V V V
10
11
12
13 14 15 16 17 18 19
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 31
Electrical Characteristics
Table 14. DC Electrical Specifications1 (continued)
Spec 20 Characteristic Load Capacitance (Fast I/O)13 DSC(PCR[8:9]) = 0b00 DSC(PCR[8:9]) = 0b01 DSC(PCR[8:9]) = 0b10 DSC(PCR[8:9]) = 0b11 Input Capacitance (Digital Pins) Input Capacitance (Analog Pins) Input Capacitance (Digital and Analog Pins14) Operating Current 1.2 V Supplies @ fsys = 264 MHz VDD @1.32 V VSTBY15 @1.2 V and 85oC VSTBY @6.0 V and 85oC Operating Current 3.3 V Supplies @ fsys = 264 MHz VDD3317 VDDSYN Operating Current 5.0 V Supplies @ fsys = 264 MHz VDDA Analog Reference Supply Current (Transient) VDDREG Operating Current VDDE/VDDEH20 Supplies VDDE2 VDDEH1 VDDEH3 VDDEH4 VDDEH5 VDDEH6 VDDEH7 Fast I/O Weak Pull Up/Down Current21 3.0 V–3.6 V Medium I/O Weak Pull Up/Down Current22 3.0 V–3.6 V 4.5 V–5.5 V I/O Input Leakage Current23 DC Injection Current (per pin) Analog Input Current, Channel Off24, AN[0:7], AN38, AN39 Analog Input Current, Channel Off, all other analog inputs AN[x] VSS Differential Voltage Analog Reference Low Voltage Symbol CL — — — — CIN CIN_A CIN_M IDD IDDSTBY IDDSTBY6 — — — — — — 10 20 30 50 7 10 12 1.016 0.10 0.15 pF pF pF pF pF pF pF A mA mA Min Max Unit
21 22 23 24
25
IDD33 IDDSYN
— —
note17 718
mA mA
26
IDDA IREF IREG IDD2 IDD1 IDD3 IDD4 IDD5 IDD6 IDD7 IACT_F IACT_S
— — — — — — — — — — 42 15 35
3019 1.0 22
mA mA mA mA mA mA mA mA mA mA μA μA μA μA mA nA nA mV mV
27
note20
28 29
158 95 200 2.5 1.0 250 150 100 VSSA + 100
30 31 32
IINACT_D IIC IINACT_A
–2.5 –1.0 –250 –150
33 34
VSS – VSSA VRL
–100 VSSA
MPC5674F Microcontroller Data Sheet, Rev. 6 32 Freescale Semiconductor
Electrical Characteristics
Table 14. DC Electrical Specifications1 (continued)
Spec 35 36 37 38 39 40
1 2
Characteristic VRL Differential Voltage Analog Reference High Voltage VREF Differential Voltage VSSSYN to VSS Differential Voltage Operating Temperature Range—Ambient (Packaged) Slew rate on power supply pins
Symbol VRL – VSSA VRH VRH – VRL VSSSYN – VSS TA (TL to TH) —
Min –100 VDDA – 100 4.75 –100 –40.0 —
Max 100 VDDA 5.25 100 125.0 25
Unit mV mV V mV
ο
C
V/ms
These specifications are design targets and subject to change per device characterization. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 3 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 4 Assumed with DC load. 5 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 6 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 7V STBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode. 8 Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with V DDREG = 4.5 V (min). 9 2.7 V minimum operating voltage allowed during vehicle crank for system with V = 3.0 V (min). Normal operating voltage DDREG should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected. 10 Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.” 11 I OH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for {00,01,10,11} drive mode with VDDE = 3.0 V 12 I OH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDE = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDE = 3.0 V 13 Applies to D_CLKOUT, external bus pins, and Nexus pins. 14 Applies to the FCK, SDI, SDO, and SDS_B pins. 15 V o STBY current specified at 1.0 V at a junction temperature of 85 C. VSTBY current is 700 µA maximum at a junction temperature oC. of 150 16 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization. 900 mA based on transistor count estimate at Worst Case (wcs) process and temperature condition. 17 Power requirements for the V DD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium (MH) pads. Also refer to Table 16 for values to calculate power dissipation for specific operation. 18 This value is a target that is subject to change. 19 This value allows a 5 V reference to supply ADC + REF. 20 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad power. Also refer to Table 15 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 21 Absolute value of current, measured at VIL and VIH. 22 Absolute value of current, measured at V and V . IL IH 23 Weak pull up/down inactive. Measured at V DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH. 24 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down. See Appendix A, Signal Properties and Muxing.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 33
Electrical Characteristics
4.7.1
I/O Pad Current Specifications
The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 15 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 15. The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.” Table 15. VDDE/VDDEH I/O Pad Average DC Current1
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13
1 2
Pad Type Medium
Symbol IDRV_MH
Frequency (MHz) 50 20 3.0 2.0
Load2 (pF) 50 50 50 200 10 20 30 50 50 50 50 50 200
Voltage (V) 5.25 5.25 5.25 5.25 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Drive/Slew Rate Select 11 01 00 00 00 01 10 11 11 10 01 00 00
Current (mA) 16.0 6.3 1.1 2.4 6.5 9.4 10.8 33.3 12.0 6.2 4.0 2.4 8.9
Fast
IDRV_FC
66 66 66 66
Fast w/ Slew Control
IDRV_FSR
66 50 33.33 20 20
These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only. All loads are lumped.
4.7.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be calculated from Table 16 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium pads can be calculated from Table 16 dependent on voltage and independent on the frequency and load on all MH type pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 16. The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”
MPC5674F Microcontroller Data Sheet, Rev. 6 34 Freescale Semiconductor
Electrical Characteristics
Table 16. VDD33 Pad Average DC Current1
Spec 1 2 3 4 5 6 7 8 9 10
1
Pad Type Medium Fast
Symbol I33_MH I33_FC
Frequency (MHz) — 66 66 66 66
Load2 (pF) — 10 20 30 50 50 50 50 50 200
VDD33 (V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
VDDE (V) 5.5 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Drive/Slew Rate Select — 00 01 10 11 11 10 00 00 00
Current (mA) 0.0007 0.92 1.14 1.50 2.19 0.74 0.52 0.19 0.19 0.19
Fast w/ Slew Control
I33_FSR
66 50 33.33 20 20
These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input pins only for the medium pads. 2 All loads are lumped.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 35
Electrical Characteristics
4.7.3
LVDS Pad Specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI module. Table 17. DSPI LVDS Pad Specification 1, 2
(VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH) Spec Data Rate 1 Data Frequency fLVDSCLK — 40 — MHz Characteristic Symbol Min Typical Max Unit
Driver Specs 2 3 4 5 6 Differential Output Voltage Common Mode Voltage (LVDS), VOS Rise/Fall Time Delay, Z to Normal (High/Low) Differential Skew between Positive and Negative LVDS Pair I tphla – tplhb I or I tplhb – tphla I VOD VOS tR or tF tDZ tSkew 150 1.075 — — — — 1.2 2 500 — 400 1.325 — — 0.5 mV V ns ns ns
Termination 7
1 2
Transmission Line (Differential)
ZO
95
100
105
ohm
These are typical values that are estimated from simulation. These specifications are subject to change per device characterization.
4.8
Oscillator and FMPLL Electrical Characteristics
Table 18. FMPLL Electrical Specifications1
(VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Spec 1
Characteristic PLL Reference Frequency Range2 (Normal Mode) Crystal Reference (PLLCFG2 = 0b0) Crystal Reference (PLLCFG2 = 0b1) External Reference (PLLCFG2 = 0b0) External Reference(PLLCFG2 = 0b1) PLL Frequency 4 Enhanced Mode Loss of Reference Frequency5 Self Clocked Mode Frequency6 PLL Lock Time7
Symbol
Min
Max
Unit MHz
fref_crystal fref_crystal fref_ext fref_ext fPLL fLOR fSCM tLPLL tDC
8 40 8 40 fvco(min) ÷ 64 100 4 — 40
20 403 20 40 fmax 1000 16 0.4 V
Max —
| Vextal – Vxtal | < 0.2 V
Unit V V V V mA pF pF pF pF pF
— ((VDD33/2) + 0.4 V)
—
— (VDD33/2) – 0.4 V 3 1.5 1.5 See crystal spec (2 × CL – CS_EXTAL – CPCB_EXTAL4) (2 × CL – CS_XTAL – CPCB_XTAL4)
1
— —
See crystal spec
—
—
All values given are initial design targets and subject to change. This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal – Vxtal ≥ 400 mV criterion has to be met for oscillator’s comparator to produce output clock. 3I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 4C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
MPC5674F Microcontroller Data Sheet, Rev. 6 38 Freescale Semiconductor
Electrical Characteristics
4.9
Spec 1 2
eQADC Electrical Characteristics
Table 20. eQADC Conversion Specifications (Operating)
Characteristic ADC Clock (ADCLK) Frequency Conversion Cycles Single Ended Conversion Cycles 12 bit resolution Single Ended Conversion Cycles 10 bit resolution Single Ended Conversion Cycles 8 bit resolution Note: Differential conversion (min) is one clock cycle less than the single-ended conversion values listed here. Stop Mode Recovery Time1 Resolution2 INL: 8 MHz ADC Clock3 INL: 16 MHz ADC Clock3 DNL: 8 MHz ADC Clock3 DNL: 16 MHz ADC Clock3 Offset Error without Calibration Offset Error with Calibration Full Scale Gain Error without Calibration Full Scale Gain Error with Calibration Non-Disruptive Input Injection Current
7, 8, 9, 10
Symbol fADCLK CC
Min 2 2 + 14 2 + 12 2 + 10
Max 16 128 + 14 128 + 12 128 + 10
Unit MHz ADCLK cycles
3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
TSR — INL8 INL16 DNL8 DNL16 OFFNC OFFWC GAINNC GAINWC IINJ EINJ TUE8 TUE16
10 1.25 –44 –84 –34 –34 04 –44 –1204 –44,6 –3 — — —
— — 44 84 34 34 1004 44 04 44,6 3 +44 +44,6 +8
μs mV LSB5 LSB LSB LSB LSB LSB LSB LSB mΑ Counts Counts Counts
Incremental Error due to injection current11, 12 TUE value at 8 MHz 13, 14 (with calibration) TUE value at 16 MHz 13, 14 (with calibration)
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. At VRH – VRL = 5.12 V, one count = 1.25 mV without using pregain. INL and DNL are tested from VRL + 50 LSB to VRH – 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy (12 bit resolution selected). New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully included. At VRH – VRL = 5.12 V, one LSB = 1.25 mV. The value is valid at 8 MHz, it is ±8 counts at 16 Mhz. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 39
Electrical Characteristics
9
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pins at injection limits. 11 Performance expected with production silicon. 12 All channels have same 10 kΩ < Rs < 100 kΩ Channel under test has Rs = 10 kΩ, IINJ=IINJMAX,IINJMIN. 13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 14 TUE does not apply to differential conversions.
4.9.1
ADC Internal Resource Measurements
Table 21. Power Management Control (PMC) Specification
Spec PMC Normal Mode 1 2 3 4 5 6 7
Characteristic
Symbol
Min
Typical
Max
Unit
Bandgap 0.62 V ADC0 channel 145 Bandgap 1.2 V ADC0 channel 146 Vreg1p2 Feedback ADC0 channel 147 LVD 1.2 V ADC0 channel 180 Vreg3p3 Feedback ADC0 channel 181 LVD 3.3 V ADC0 channel 182 LVD 5.0 V ADC0 channel 183 — LDO mode — SMPS mode
VADC145 VADC146 VADC147 VADC180 VADC181 VADC182 VADC183
— — — — — — —
0.62 1.22 VDD / 2.045 VDD / 1.774 Vreg3p3 / 5.460 Vreg3p3 / 4.758
— — — — — — —
V V V V V V V
VDDREG / 4.758 VDDREG/7.032
Table 22. Standby RAM Regulator Electrical Specifications
Spec Normal Mode 1 2 Standby Regulator Output ADC1 channel 194 Standby Source Bias 150 mV to 360 mV (30mV Increment @ vref_sel) ADC1 channel 195 Default Value 150 mV (@vref_sel = 1 1 1) Standby Brownout Reference ADC1 channel 195 VADC194 VADC195
—
Characteristic
Symbol
Min
Typ
Max
Unit
1.2
—
—
V mV
150
360
3
VADC195
500
850
mV
MPC5674F Microcontroller Data Sheet, Rev. 6 40 Freescale Semiconductor
Electrical Characteristics
Table 23. ADC Band Gap Reference / LVI Electrical Specifications
Spec 1 2 Characteristic 4.75 LVD (from VDDA) ADC1 channel 196 ADC Bandgap ADC0 channel 45 ADC1 channel 45 Symbol VADC196 VADC45 Min
—
Typ 4.75 1.220
Max
—
Unit V V
—
—
Table 24. Temperature Sensor Electrical Specifications
Spec 1 Characteristic Slope –40 °C to 100 °C ±1.0 °C 100 °C to 150 °C ±1.6 °C ADC0 channel 128 ADC1 channel 128 Accuracy –40 °C to 150 °C ADC0 channel 128 ADC1 channel 128 Symbol VSADC128 1 Min
—
Typ 5.8
Max
—
Unit mV/ °C
2
—
—
—
°C
±10.0
1
Slope is the measured voltage change per °C.
4.10
C90 Flash Memory Electrical Characteristics
Table 25. Flash Program and Erase Specifications1
Spec 1 2 3 4 5 6 7
1
Characteristic Double Word (64 bits) Program Time4 Page Program Time4,5 16 KB Block Pre-program and Erase Time 64 KB Block Pre-program and Erase Time 128 KB Block Pre-program and Erase Time 256 KB Block Pre-program and Erase Time Minimum operating frequency
Symbol tdwprogram tpprogram t16kpperase t64kpperase t128kpperase t256kpperase —
Min — — — — — — 250
Initial Max2 — 160 1000 1800 2600 5200 —
Max3 500 500 5000 5000 7500 15000 —
Unit μs μs ms ms ms ms kHz
Typical program and erase times assume nominal supply values and operation at 25 oC. All times are subject to change pending device characterization. 2 Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 41
Electrical Characteristics
3
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. 5 Page size is 128 bits (4 words).
Table 26. Flash EEPROM Module Life
Spec 1 2 3 Characteristic Number of Program/Erase cycles per block for 16 KB and 64 KB blocks over the operating temperature range (TJ) Number of Program/Erase cycles per block for 128 KB and 256 KB blocks over the operating temperature range (TJ) Minimum Data Retention at 25 °C ambient temperature2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–10,000 P/E cycles Blocks with 10,001–100,000 P/E cycles Symbol P/E P/E Retention 20 10 1–5 — Min 100,000 1,000 Typical1 — 100,000 Unit cycles cycles years
1
Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
Table 27 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 27. PFCPR1 Settings vs. Frequency of Operation1
Maximum Frequency2 (MHz) Core fsys 264 MHz6 Platform fplatf 132 MHz6
Spec
Clock Mode
APC = RWSC
WWSC
DPFEN3
IPFEN3
PFLIM4
BFEN5
1
Enhanced
0b1007
0b01
0b0 0b1 0b0 0b1 0b0 0b1 0b0 0b1 0b00
0b0 0b1 0b0 0b1 0b0 0b1 0b0 0b1 0b00
0b00 0b01 0b1x 0b00 0b01 0b1x 0b00 0b01 0b1x 0b00 0b01 0b1x 0b00
0b0 0b1 0b0 0b1 0b0 0b1 0b0 0b1 0b0
2
Enhanced/ 200 MHz Full Enhanced/ 180 MHz Full Legacy 132 MHz
100 MHz
0b0107
0b01
3
90 MHz
0b0107
0b01
4
132 MHz
0b0117
0b01
Default setting after reset:
1 2
0b111
0b11
Illegal combinations exist. Use entries from the same row in this table. This is the nominal maximum frequency of operation: platform runs at fsys/2 in Enhanced Mode . 3 For maximum flash performance, set to 0b1. 4 For maximum flash performance, set to 0b10.
MPC5674F Microcontroller Data Sheet, Rev. 6 42 Freescale Semiconductor
Electrical Characteristics
5 6
For maximum flash performance, set to 0b1. This is the nominal maximum frequency of operation in Enchanced Mode. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(fsys)+ 2% FM and 132 Mhz platform clock (fplatf)+ 2% FM. 7 Preliminary setting. Final setting pending characterization.
4.11
4.11.1
AC Specifications
Clocking
The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.
PLLCFG[0:1] CORE SYSDIV ÷X fsys ÷2
IPG DIV SEL
EXTAL
PLL
fplatf fperiph
PLATFORM / BLOCKS / FLASH
SIU_SYSDIV[SYSCLKDIV[0:1]] X = 2, 4, 8, or 16 SIU_SYSDIV[BYPASS] X=1 SIU_SYSDIV[IPCLKDIV[0:1]] SIU_ECCR[EBDF[0:1]] Note: tcycsys = 1 / fsys tcyc = 1 / fplatf ÷ 2 = divide-by-2 ÷ X = divide-by-X, depending on SIU_SYSDIV[BYPASS] and SIU_SYSDIV[SYSCLKDIV].
ETPU DIV SEL
fetpu
eTPU / NDEDI
DIV
febi_cal
EBI CAL BUS
D_CLKOUT
(D_CLKOUT is not available on all packages and cannot be programmed for faster than fsys/2.)
Figure 16. MPC5674F Block Operating Frequency Domain Diagram Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see Table 29 and Table 30 for descriptions of bit settings).
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 43
Electrical Characteristics
Table 28. MPC5674F Operating Frequencies1, 2
SIU_ECCR [EBDF[0:1]]3 01 11 01 11 01 11
Mode
fsys
(core) 264 264 200 200 132 132
fplatf
fetpu
(platform and all blocks (eTPU, eTPU RAM, except eTPU) and NDEDI) 132 132 100 100 132 132 132 132 200 200 132 132
febi_cal4,5
66 33 50 25 66 33
Unit
Enhanced Full Legacy
1
MHz MHz MHz
2 3 4 5
The values in the table are specified at: VDD = 1.02 V to 1.32 V VDDE = 3.0 V to 3.6 V VDDEH = 4.5 V to 5.5 V VDD33 and VDDSYN = 3.0 V to 3.6 V TA = TL to TH. Up to the maximum frequency rating of the device (refer to Table 1). The fsys speed is the nominal maximum frequency. 270 Mhz parts allow for 264 Mhz system clock + 2% FM. See the MPC5674F Reference Manual for full description as not all bit combinations are valid. EBI/Calibration bus is not available in all packages. The EBI/Calibration Bus operating frequency, febi_cal , depends on clock divider settings of block’s max allowed frequency of operation. Normally febi_cal = fplatf /2, but can be limited to < fplatf /2 in Full Mode.
Table 29. IPCLKDIV Settings
SIU_SYSDIV [IPCLKDIV[0:1]] 00 01 10 11 Mode Enhanced Full — Legacy Description CPU frequency is doubled (Max 264Mhz). Platform, peripheral, and eTPU clocks are 1/2 of CPU frequency CPU and eTPU frequency is doubled (Max 200Mhz). Platform and peripheral clocks are 1/2 of CPU frequency. Reserved CPU, eTPU, platform, and peripheral’s clocks all run at same speed (Max 132Mhz).
Table 30. SYSCLKDIV Settings
SIU_SYSDIV [SYSCLKDIV[0:1]] 00 01 10 11 Description Divide by 2. Divide by 4. Divide by 8. Divide by 16.
MPC5674F Microcontroller Data Sheet, Rev. 6 44 Freescale Semiconductor
Electrical Characteristics
4.11.2
Pad AC Specifications
Table 31. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)1
Spec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6
Pad Medium5
SRC/DSC 00 01 11
Out Delay2,4 L → H/H → L (ns) 152/165 205/220 28/34 52/59 12/12 32/32
Rise/Fall3,4 (ns) 70/74 96/96 12/15 28/31 5.3/5.9 22/22
Load Drive (pF) 50 200 50 200 50 200 10 20 30 50 50 200 50 200 50 200 50 2.6 50 50
Fast6
00 01 10 11 2.5 1.2
Fast with Slew Rate
00 01 10 11
40/40 50/50 13/13 19/19 8/8 12/12 5/5 8/8 — 6000
16/16 21/21 5/5 8/8 2.4/2.4 5/5 1.1/1/1 2.6 7500 5000/5000
Pull Up/Down (3.6 V max) Pull Up/Down (5.25 V max)
— —
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. This parameter is guaranteed by characterization before qualification rather than 100% tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock. Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 45
Electrical Characteristics
Table 32. Derated Pad AC Specifications (VDDEH = 3.3 V)1
Spec 1 2 3 4 5 6
1 2 3 4 5
Pad Medium5
SRC/DSC 00
Out Delay2,3 L → H/H → L (ns) 200/210 270/285
Rise/Fall4,3 (ns) 86/86 120/120 15.5/19 38/43 7.6/8.5 30/34
Load Drive (pF) 50 200 50 200 50 200
01
37/45 69/82
11
18/17 46/49
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested. Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.
VDDEn / 2 Pad Data Input VDDEHn / 2 Rising Edge Output Delay Falling Edge Output Delay VOH
Pad Output
VOL
Figure 17. Pad Output Delay
4.12
4.12.1
AC Timing
Generic Timing Diagrams
The generic timing diagrams in Figure 18 and Figure 19 apply to all I/O pins with pad types F and MH. See Appendix A, Signal Properties and Muxing, for the pad type for each pin.
MPC5674F Microcontroller Data Sheet, Rev. 6 46 Freescale Semiconductor
Electrical Characteristics
D_CLKOUT
VDDE / 2
A B
I/O Outputs
VDDEn / 2 VDDEHn / 2
A – Maximum Output Delay Time
B – Minimum Output Hold Time
Figure 18. Generic Output Delay/Hold Timing
D_CLKOUT
VDDE / 2
B A
I/O Inputs
VDDEn / 2 VDDEHn / 2
A – Minimum Input Setup Time
B – Minimum Input Hold Time
Figure 19. Generic Input Setup/Hold Timing
4.12.2
Reset and Configuration Pin Timing
Table 33. Reset and Configuration Pin Timing1
Spec 1 2 3 4 RESET Pulse Width
Characteristic
Symbol tRPW tGPW tRCSU tRCH
Min 10 2 10 0
Max — — — —
Unit tcyc2 tcyc2 tcyc2 tcyc2
RESET Glitch Detect Pulse Width PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 47
Electrical Characteristics
1 2
Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH. See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1, “Clocking.”
2 RESET 1
RSTOUT
3
PLLCFG BOOTCFG WKPCFG 4
Figure 20. Reset and Configuration Pin Timing
4.12.3
IEEE 1149.1 Interface Timing
Table 34. JTAG Pin AC Electrical Characteristics1
Spec 1 2 3 4 5 6 7 8 9 10 11 TCK Cycle Time
Characteristic
Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tJCMPPW tJCMPS tBSDV
Min 100 40 — 5 25 — 0 — 100 40 —
Max — 60 3 — — 10 — 20 — — 50
Unit ns ns ns ns ns ns ns ns ns ns ns
TCK Clock Pulse Width (Measured at VDDE / 2) TCK Rise and Fall Times (40%–70%) TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance JCOMP Assertion Time JCOMP Setup Time to TCK Low TCK Falling Edge to Output Valid
MPC5674F Microcontroller Data Sheet, Rev. 6 48 Freescale Semiconductor
Electrical Characteristics
Table 34. JTAG Pin AC Electrical Characteristics1 (continued)
Spec 12 13 14 15
1
Characteristic TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid
Symbol tBSDVZ tBSDHZ tBSDST tBSDHT
Min — — 50 50
Max 50 50 — —
Unit ns ns ns ns
JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 35 for functional specifications.
TCK 2 3 2
1
3
Figure 21. JTAG Test Clock Input Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 49
Electrical Characteristics
TCK
4 5
TMS, TDI
6 7 8
TDO
Figure 22. JTAG Test Access Port Timing
TCK 10 JCOMP
9
Figure 23. JTAG JCOMP Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 50 Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output Signals
12
Output Signals 14 15
Input Signals
Figure 24. JTAG Boundary Scan Timing
4.12.4
Spec 1 2 3 4 5 6 7
Nexus Timing
Table 35. Nexus Debug Port Timing1
Characteristic Symbol tMCYC tMDC Valid4 Valid4 tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW Min 22 40 –0.1 –0.1 –0.1 4.0 1 Max 8 60 0.2 0.2 0.2 — — Unit tCYC3 % tMCYC tMCYC tMCYC tTCYC3 tMCYC
MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO Data MCKO Low to MSEO Data Valid4 MCKO Low to EVTO Data EVTI Pulse Width EVTO Pulse Width
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 51
Electrical Characteristics
Table 35. Nexus Debug Port Timing1 (continued)
Spec 8 9 10 11 12 13
1
Characteristic TCK Cycle Time TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid RDY Valid to MCKO6
Symbol tTCYC tTDC tNTDIS, tNTMSS TNTDIH, tNTMSH tNTDOV —
Min 4
5
Max — 60 — — 10 —
Unit tCYC3 % ns ns ns —
40 8 5 0 —
2 3 4 5 6
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending on the system frequency, not to exceed maximum Nexus AUX port frequency. See Notes on tcyc on Figure 16 and Table 28 in Section Section 4.11.1 Clocking. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. Lower frequency is required to be fully compliant to standard. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid
7 6
EVTI
Figure 25. Nexus Timings
MPC5674F Microcontroller Data Sheet, Rev. 6 52 Freescale Semiconductor
Electrical Characteristics
8
9
TCK
10 11
TMS, TDI
12
TDO
Figure 26. Nexus TCK, TDI, TMS, TDO Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 53
Electrical Characteristics
4.12.5
External Bus Interface (EBI) Timing
Table 36. Bus Operation Timing 1
66 MHz (Ext. Bus Freq)2 3
Spec 1 2 3 4 5
Characteristic D_CLKOUT Period D_CLKOUT Duty Cycle D_CLKOUT Rise Time D_CLKOUT Fall Time D_CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3]
Symbol Min tC tCDC tCRT tCFT tCOH 15.2 45% — — 1.0/1.5 Max — 55% —4 —4 —
Unit ns tC ns ns ns
Notes Signals are measured at 50% VDDE.
Hold time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 1.0 ns EBTS = 1: 1.5 ns
6
D_CLKOUT Posedge to Output Signal Valid (Output Delay) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3]
tCOV
—
7.0/7.5
ns
Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 7.0 ns EBTS = 1: 7.5 ns
7
Input Signal Valid to D_CLKOUT Posedge (Setup Time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS
tCIS
5.0/4.5
—
ns
Input setup time selectable via SIU_ECCR[EBTS] bit: EBTS = 0; 5.0ns EBTS = 1; 4.5ns
8
D_CLKOUT Posedge to Input Signal Invalid (Hold Time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS
tCIH
1.0
—
ns
MPC5674F Microcontroller Data Sheet, Rev. 6 54 Freescale Semiconductor
Electrical Characteristics
Table 36. Bus Operation Timing 1 (continued)
66 MHz (Ext. Bus Freq)2 3 Spec 9 10 Characteristic D_ALE Pulse Width D_ALE Negated to Address Invalid Symbol Min tAPW tAAI 6.5 2.0/1.0 5 Max — — ns ns The timing is for Asynchronous external memory system. The timing is for Asynchronous external memory system. ALE is measured at 50% of VDDE. Unit Notes
1 2 3 4 5
EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system clock + 2% FM. Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz. Refer to Fast pad timing in Table 31 and Table 32. ALE hold time spec is temperature dependant. 1.0ns spec applies for temperature range -40 to 0 C. 2.0ns spec applies to temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit.
VOH_F VDDE / 2 D_CLKOUT VOL_F 3 2 2 4 1
Figure 27. D_CLKOUT Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 55
Electrical Characteristics
D_CLKOUT
VDDE / 2
6 5 5
Output Bus
VDDE / 2
6 5 5 Output Signal
VDDE / 2
6 Output Signal
VDDE / 2
Figure 28. Synchronous Output Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 56 Freescale Semiconductor
Electrical Characteristics
D_CLKOUT
VDDE / 2
7 8
Input Bus
VDDE / 2
7 8
Input Signal
VDDE / 2
Figure 29. Synchronous Input Timing
ipg_clk D_CLKOUT D_ALE D_TS D_ADD/D_DAT ADDR 9 10 DATA
Figure 30. ALE Signal Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 57
Electrical Characteristics
4.12.6
Spec 1 2 3
1
External Interrupt Timing (IRQ Pin)
Table 37. External Interrupt Timing1
Characteristic IRQ Pulse Width Low IRQ Pulse Width High IRQ Edge to Edge Time
3
Symbol tIPWL tIPWH tICYC
Min 3 3 6
Max — — —
Unit tcyc2 tcyc2 tcyc2
IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. 2 See Notes on tcyc on Figure 16 and Table 28 in Section 4.11.1 Clocking. 3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
1 3
2
Figure 31. External Interrupt Timing
4.12.7
Spec 1 2
1
eTPU Timing
Table 38. eTPU Timing1
Characteristic Symbol tICPW tOCPW Min 4 13 Max — — Unit tcyc2 tcyc2
eTPU Input Channel Pulse Width eTPU Output Channel Pulse Width
eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2 See Notes on t cyc on Figure 16 and Table 28 in Section 4.11.1 Clocking. 3 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5674F Microcontroller Data Sheet, Rev. 6 58 Freescale Semiconductor
Electrical Characteristics
eTPU Input and TCRCLK
1 2
eTPU Output
Figure 32. eTPU Timing
4.12.8
Spec 1 2
1
eMIOS Timing
Table 39. eMIOS Timing1
Characteristic Symbol tMIPW tMOPW Min 4 13 Max — — Unit tcyc2 tcyc2
eMIOS Input Pulse Width eMIOS Output Pulse Width
eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2 See Notes on t cyc on Figure 16 and Table 28 in Section 4.11.1 Clocking. 3 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 59
Electrical Characteristics
eMIOS Input
1 2
eMIOS Output
Figure 33. eMIOS Timing
4.12.9
DSPI Timing
Table 40. DSPI Timing1 2
Peripheral Bus Freq: 132 MHz Min Max tSYS*32768*7 ns
Spec
Characteristic
Symbol
Unit
1
DSPI Cycle Time3, 4 Master (MTFE = 0) Slave (MTFE = 0) Master (MTFE = 1) Slave (MTFE = 1) PCS to SCK Delay5 After SCK Delay6 Master mode Slave mode SCK Duty Cycle Slave Access Time (SS active to SOUT valid) Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) PCSx to PCSS time PCSS to PCSx time
tSCK
tSYS * 2
2 3
tCSC tASC
12 tSYS * 2 tSYS *3 – constraints 7
— —
ns ns
4 5 6 7 8
tSDC tA tDIS tPCSC tPASC
0.33 * tSCK — — tSYS * 2 tSYS * 2
0.66 * tSCK 25 25 tSYS * 7 tSYS * 7
ns ns ns ns ns
MPC5674F Microcontroller Data Sheet, Rev. 6 60 Freescale Semiconductor
Electrical Characteristics
Table 40. DSPI Timing1 2 (continued)
Peripheral Bus Freq: 132 MHz Min 9 Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)8 Master (MTFE = 1, CPHA = 1) Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tSUI 20 4 6 20 tHI –3 7 12 –3 tSUO — — — — tHO –5 2.5 3 –5 — — — — ns ns ns ns 5 25 13 5 ns ns ns ns — — — — ns ns ns ns — — — — ns ns ns ns Max
Spec
Characteristic
Symbol
Unit
10
11
12
1 2 3 4 5 6 7 8
DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (fsys) + 2% FM. The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK]. The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC]. For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol. DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high speed operation. Table 41. DSPI LVDS Timing1, 2
Characteristic LVDS Clock to Data/Chip Select Outputs
1 2
Symbol tLVDSDATA
Min –0.25 × tSCYC
Max +0.25 × tSCYC
Unit ns
These are typical values that are estimated from simulation. See DSPI LVDS Pad related data in Table 17.
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 61
Electrical Characteristics
2 PCSx 4 SCK Output (CPOL = 0) 4 1
3
SCK Output (CPOL = 1) 9 SIN 10 Data 12 SOUT First Data Data Last Data 11 Last Data
First Data
Figure 34. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Data Data Last Data 11 Last Data
Figure 35. DSPI Classic SPI Timing — Master, CPHA = 1
MPC5674F Microcontroller Data Sheet, Rev. 6 62 Freescale Semiconductor
Electrical Characteristics
2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 10 Data 12 Data 11 4
3
6
Last Data
First Data
Last Data
Figure 36. DSPI Classic SPI Timing — Slave, CPHA = 0
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 37. DSPI Classic SPI Timing — Slave, CPHA = 1
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 63
Electrical Characteristics
3 PCSx 4 2 SCK Output (CPOL = 0) SCK Output (CPOL = 1) 9 SIN First Data 12 SOUT First Data Data Data 11 Last Data Last Data 4 1
10
Figure 38. DSPI Modified Transfer Format Timing — Master, CPHA = 0
PCSx
SCK Output (CPOL = 0)
SCK Output (CPOL = 1) 9 SIN First Data Data 12 SOUT First Data Data 10
Last Data 11 Last Data
Figure 39. DSPI Modified Transfer Format Timing — Master, CPHA = 1
MPC5674F Microcontroller Data Sheet, Rev. 6 64 Freescale Semiconductor
Electrical Characteristics
SS
2 1
3
SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN First Data Data Data 11 12 Last Data 10 Last Data 6 4
Figure 40. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
SS
SCK Input (CPOL = 0)
SCK Input (CPOL = 1) 5 SOUT
11 12 First Data 9 10 Data Last Data Data Last Data 6
SIN
First Data
Figure 41. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
7 PCSS PCSx
8
Figure 42. DSPI PCS Strobe (PCSS) Timing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 65
Package Information
5
Package Information
The latest package outline drawings are available on the product summary pages on our website: http://www.freescale.com/powerarchitecture. The following table lists the package case number. Use these numbers in the webpage’s keyword search engine to find the latest package outline drawings. Table 42. Package Information
Package Type 324 TEPBGA 416 TEPBGA 516 TEPBGA Case Outline Number 98ASS23840W 98ARE10523D 98ARS10503D
MPC5674F Microcontroller Data Sheet, Rev. 6 66 Freescale Semiconductor
Package Information
5.1
324-Pin Package
The package drawings of the 324-pin TEPBGA package are shown in Figure 43 and Figure 44.
Figure 43. 324 TEPBGA Package (1 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 67
Package Information
Figure 44. 324 TEPBGA Package (2 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 68 Freescale Semiconductor
Package Information
5.2
416-Pin Package
The package drawings of the 416-pin TEPBGA package are shown in Figure 45 and Figure 46.
Figure 45. 416 TEPBGA Package (1 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 69
Package Information
Figure 46. 416 TEPBGA Package (2 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 70 Freescale Semiconductor
Package Information
5.3
516-Pin Package
The package drawings of the 516-pin TEPBGA package are shown in Figure 47 and Figure 48.
Figure 47. 516 TEPBGA Package (1 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 71
Package Information
Figure 48. 516 TEPBGA Package (2 of 2)
MPC5674F Microcontroller Data Sheet, Rev. 6 72 Freescale Semiconductor
Product Documentation
6
Product Documentation
This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. The following documents are required for a complete description of the device and are necessary to design properly with the parts: • MPC5674F Microprocessor Reference Manual (document number MPC5674FRM).
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 73
Signal Properties and Muxing
Appendix A Signal Properties and Muxing
The following table shows the signals properties for each pin on the MPC5674F. For each port pin that has an associated SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 49.
U
Table 2. Signal Properties Summary
GPIO/ PCR1 113 P/ F/ G Pad Type 5V M
Primary Functions are listed First Secondary Functions are alternate functions GPIO Functions are listed Last
Signal Name2
Function3 TCRCLKA IRQ7 — GPIO113
Function Summary eTPU A TCR clock External interrupt request — GPIO
I/O I I — I/O
TCRCLKA_IRQ7_GPIO113 P
A1 A2 G
Function not implemented on this device
Figure 49. Supported Functions Example
MPC5674F Microcontroller Data Sheet, Rev. 6 74 Freescale Semiconductor
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 75
Table 43. Signal Properties and Muxing Summary
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
L1 L2 L3 L4 K1 K2
eTPU_A
113 TCRCLKA_IRQ7_ GPIO113
P A1 A2 G
TCRCLKA IRQ7 — GPIO113 ETPUA0 ETPUA12 — GPIO114 ETPUA1 ETPUA13 — GPIO115 ETPUA2 ETPUA14 — GPIO116 ETPUA3 ETPUA15 — GPIO117 ETPUA4 ETPUA16 — GPIO118
eTPU A TCR clock External interrupt request — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO
I I — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH1
—/Up
—/Up
K1
114 ETPUA0_ETPUA12_ GPIO114
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
K2
115 ETPUA1_ETPUA13_ GPIO115
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
J1
116 ETPUA2_ETPUA14_ GPIO116
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
J2
117 ETPUA3_ETPUA15_ GPIO117
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
J3
H4
118 ETPUA4_ETPUA16_ GPIO118
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
J4
516
K4 L6 J1 J2 J4
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
K3 K4 J1 J2 J3 J4
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 76
119 ETPUA5_ETPUA17_ GPIO119
P A1 A2 G
ETPUA5 ETPUA17 — GPIO119 ETPUA6 ETPUA18 — GPIO120 ETPUA7 ETPUA19 — GPIO121 ETPUA8 ETPUA20 — GPIO122 ETPUA9 ETPUA21 — GPIO123 ETPUA10 ETPUA22 — GPIO124
eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel eTPU A channel (output only) — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
H1
H1
120 ETPUA6_ETPUA18_ GPIO120
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
H2
121 ETPUA7_ETPUA19_ GPIO121
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
H2
122 ETPUA8_ETPUA20_ GPIO122
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
H3
123 ETPUA9_ETPUA21_ GPIO123
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
H3
124 ETPUA10_ETPUA22_ GPIO124
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
G1
516
K5 J3 K6
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
H1 H2 H4 H3 G1 G2
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 77
125 ETPUA11_ETPUA23_ GPIO125
P A1 A2 G
ETPUA11 ETPUA23 — GPIO125 ETPUA12 PCSB1 — GPIO126 ETPUA13 PCSB3 — GPIO127 ETPUA14 PCSB4 — GPIO128 ETPUA15 PCSB5 — GPIO129 ETPUA16 PCSD1 — GPIO130
eTPU A channel eTPU A channel (output only) — GPIO eTPU A channel DSPI B peripheral chip select — GPIO eTPU A channel DSPI B peripheral chip select — GPIO eTPU A channel DSPI B peripheral chip select — GPIO eTPU A channel DSPI B peripheral chip select — GPIO eTPU A channel DSPI D peripheral chip select — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
G2
G1
126 ETPUA12_PCSB1_ GPIO126
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
G3
127 ETPUA13_PCSB3_ GPIO127
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
F1
G2
128 ETPUA14_PCSB4_ GPIO128
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
F2
H5
129 ETPUA15_PCSB5_ GPIO129
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
F3
G3
130 ETPUA16_PCSD1_ GPIO130
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
H4
H6
516
J5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
G3 G4 F1 F2 F3 F4
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 78
131 ETPUA17_PCSD2_ GPIO131
P A1 A2 G
ETPUA17 PCSD2 — GPIO131 ETPUA18 PCSD3 — GPIO132 ETPUA19 PCSD4 — GPIO133 ETPUA20 IRQ8 — GPIO134 ETPUA21 IRQ9 — GPIO135 ETPUA22 IRQ10 — GPIO136
eTPU A channel DSPI D peripheral chip select — GPIO eTPU A channel DSPI D peripheral chip select — GPIO eTPU A channel DSPI D peripheral chip select — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O I — I/O I/O I — I/O I/O I — I/O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
G4
G4
132 ETPUA18_PCSD3_ GPIO132
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
G5
133 ETPUA19_PCSD4_ GPIO133
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
134 ETPUA20_IRQ8_ GPIO134
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
E1
135 ETPUA21_IRQ9_ GPIO135
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
C1
136 ETPUA22_IRQ10_ GPIO136
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
E2
516
F1 F2 F3 F4
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
E1 E2 E3 E4 D1 D2
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 79
137 ETPUA23_IRQ11_ GPIO137
P A1 A2 G
ETPUA23 IRQ11 — GPIO137 ETPUA24 IRQ12 — GPIO138 ETPUA25 IRQ13 — GPIO139 ETPUA26 IRQ14 — GPIO140 ETPUA27 IRQ15 — GPIO141 ETPUA28 PCSC1 — GPIO142
eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel External interrupt request — GPIO eTPU A channel DSPI C peripheral chip select — GPIO
I/O I — I/O I/O I — I/O I/O I — I/O I/O I — I/O I/O I — I/O I/O O — I/O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
D1
138 ETPUA24_IRQ12_ GPIO138
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
E3
139 ETPUA25_IRQ13_ GPIO139
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
D2
140 ETPUA26_IRQ14_ GPIO140
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
C2
141 ETPUA27_IRQ15_ GPIO141
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
F4
D1
142 ETPUA28_PCSC1_ GPIO142
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
D2
516
E1 E2 E3 E4
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
D3 C1 C2 T23 T24 T25
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 80
143 ETPUA29_PCSC2_ GPIO143
P A1 A2 G
ETPUA29 PCSC2 — GPIO143 ETPUA30 PCSC3 — GPIO144 ETPUA31 PCSC4 — GPIO145
eTPU A channel DSPI C peripheral chip select — GPIO eTPU A channel DSPI C peripheral chip select — GPIO eTPU A channel DSPI C peripheral chip select — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH1
—/WKPCFG
—/WKPCFG
—
D3
144 ETPUA30_PCSC3_ GPIO144
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
E4
C1
145 ETPUA31_PCSC4_ GPIO145
P A1 A2 G
MH
VDDEH1
—/WKPCFG
—/WKPCFG
D3
C2
eTPU_B
146 TCRCLKB_IRQ6_ GPIO146
P A1 A2 G
TCRCLKB IRQ6 — GPIO146 ETPUB0 ETPUB16 — GPIO147 ETPUB1 ETPUB17 — GPIO148
eTPU B TCR clock External interrupt request — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO
I I — I/O I/O O — I/O I/O O — I/O
MH
VDDEH6
—/Up
—/Up
P19
V25
147 ETPUB0_ETPUB16_ GPIO147
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
N19
V26
148 ETPUB1_ETPUB17_ GPIO148
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
R19
U22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
T26 R23 R24 R25 R26 P23
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 81
149 ETPUB2_ETPUB18_ GPIO149
P A1 A2 G
ETPUB2 ETPUB18 — GPIO149 ETPUB3 ETPUB19 — GPIO150 ETPUB4 ETPUB20 — GPIO151 ETPUB5 ETPUB21 — GPIO152 ETPUB6 ETPUB22 — GPIO153 ETPUB7 ETPUB23 — GPIO154
eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH6
—/WKPCFG
—/WKPCFG
R22
U23
150 ETPUB3_ETPUB19_ GPIO150
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
R21
T22
151 ETPUB4_ETPUB20_ GPIO151
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
P22
U24
152 ETPUB5_ETPUB21_ GPIO152
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
P21
U25
153 ETPUB6_ETPUB22_ GPIO153
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
N22
U26
154 ETPUB7_ETPUB23_ GPIO154
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
M19
T23
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
P24 P25 P26 N24 N25 N26
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 82
155 ETPUB8_ETPUB24_ GPIO155
P A1 A2 G
ETPUB8 ETPUB24 — GPIO155 ETPUB9 ETPUB25 — GPIO156 ETPUB10 ETPUB26 — GPIO157 ETPUB11 ETPUB27 — GPIO158 ETPUB12 ETPUB28 — GPIO159 ETPUB13 ETPUB29 — GPIO160
eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH6
—/WKPCFG
—/WKPCFG
N21
T24
156 ETPUB9_ETPUB25_ GPIO156
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
M22
R22
157 ETPUB10_ETPUB26_ GPIO157
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
M20
T25
158 ETPUB11_ETPUB27_ GPIO158
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
M21
T26
159 ETPUB12_ETPUB28_ GPIO159
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
L19
R23
160 ETPUB13_ETPUB29_ GPIO160
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
L20
P22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
M25 M24 U26 U25 U24 U23
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 83
161 ETPUB14_ETPUB30_ GPIO161
P A1 A2 G
ETPUB14 ETPUB30 — GPIO161 ETPUB15 ETPUB31 — GPIO162 ETPUB16 PCSA1 — GPIO163 ETPUB17 PCSA2 — GPIO164 ETPUB18 PCSA3 — GPIO165 ETPUB19 PCSA4 — GPIO166
eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel eTPU B channel (output only) — GPIO eTPU B channel DSPI A peripheral chip select — GPIO eTPU B channel DSPI A peripheral chip select — GPIO eTPU B channel DSPI A peripheral chip select — GPIO eTPU B channel DSPI A peripheral chip select — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH6
—/WKPCFG
—/WKPCFG
L21
R24
162 ETPUB15_ETPUB31_ GPIO162
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
R25
163 ETPUB16_PCSA1_ GPIO163
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
P20
V24
164 ETPUB17_PCSA2_ GPIO164
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
R20
T21
165 ETPUB18_PCSA3_ GPIO165
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
T20
W26
166 ETPUB19_PCSA4_ GPIO166
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
T19
W25
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
V26 V25 V24 W26 W25 W24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 84
167 ETPUB20_ GPIO167
P A1 A2 G
ETPUB20 — — GPIO167 ETPUB21 — — GPIO168 ETPUB22 — — GPIO169 ETPUB23 — — GPIO170 ETPUB24 — — GPIO171 ETPUB25 — — GPIO172
eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
W24
168 ETPUB21_ GPIO168
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
V22
169 ETPUB22_ GPIO169
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
V23
170 ETPUB23_ GPIO170
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
U21
171 ETPUB24_ GPIO171
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
Y25
172 ETPUB25_ GPIO172
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
W21
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
V23 Y25 Y24 Y23 AA24 AB24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 85
173 ETPUB26_ GPIO173
P A1 A2 G
ETPUB26 — — GPIO173 ETPUB27 — — GPIO174 ETPUB28 — — GPIO175 ETPUB29 — — GPIO176 ETPUB30 — — GPIO177 ETPUB31 — — GPIO178
eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO eTPU B channel — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
Y23
174 ETPUB27_ GPIO174
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
Y24
175 ETPUB28_ GPIO175
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
AA24
176 ETPUB29_ GPIO176
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
—
W22
177 ETPUB30_ GPIO177
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
U20
AB24
178 ETPUB31_ GPIO178
P A1 A2 G
MH
VDDEH6
—/WKPCFG
—/WKPCFG
U19
Y22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
B26 C25 C26 D25 D26 E24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 86
GPIO, IRQ, FlexRay
440 TCRCLKC_ GPIO4409
P A1 A2 G
— — — GPIO440 — — — GPIO441 — — — GPIO442 — — — GPIO443 — — — GPIO444 — — — GPIO445
— — — GPIO — — — GPIO — — — GPIO — — — GPIO — — — GPIO — — — GPIO
— — — I/O — — — I/O — — — I/O — — — I/O — — — I/O — — — I/O
MH
VDDEH7
—/Up
—/Up
B22
F22
441 ETPUC0_ GPIO4419
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
C21
C25
442 ETPUC1_ GPIO4429
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
D20
C26
443 ETPUC2_ GPIO4439
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
D22
D25
444 ETPUC3_ GPIO4449
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
D21
D26
445 ETPUC4_ GPIO4459
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
E22
E24
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
E25 E26 F23 F24 F25 F26
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 87
446 ETPUC5_ GPIO4469
P A1 A2 G
— — — GPIO446 — — — GPIO447 — — — GPIO448 — — — GPIO449 — IRQ0 — GPIO450 — IRQ1 — GPIO451
— — — GPIO — — — GPIO — — — GPIO — — — GPIO — External interrupt request — GPIO — External interrupt request — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O — I — I/O — I — I/O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
E19
E25
447 ETPUC6_ GPIO4479
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
—
E26
448 ETPUC7_ GPIO4489
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
—
F23
449 ETPUC8_ GPIO4499
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
—
F24
450 ETPUC9_IRQ0_ GPIO4509
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
F22
F25
451 ETPUC10__IRQ1_ GPIO4519
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
E20
F26
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
G23 G24 G25 G26 H23 H24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 88
452 ETPUC11_IRQ2_ GPIO4529
P A1 A2 G
— IRQ2 — GPIO452 — IRQ3 — GPIO453 — IRQ4 — GPIO454 — IRQ5 — GPIO455 — — — GPIO456 — FR_A_TX — GPIO457
— External interrupt request — GPIO — External interrupt request — GPIO — External interrupt request — GPIO — External interrupt request — GPIO — — — GPIO — FlexRay A transfer — GPIO
— I — I/O — I — I/O — I — I/O — I — I/O — — — I/O — O — I/O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
E21
G22
453 ETPUC12_IRQ3_ GPIO4539
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
F19
G23
454 ETPUC13_3_IRQ4_ GPIO4549
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
F21
G24
455 ETPUC14_4_IRQ5_ GPIO4559
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
F20
G25
456 ETPUC15__ GPIO4569
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
—
G26
457 ETPUC16_FR_A_TX_ GPIO4579
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
—
H22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
H25 H26 J23 J24 J25 J26
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 89
458 ETPUC17_FR_A_RX_ GPIO4589
P A1 A2 G
— FR_A_RX — GPIO458 — FR_A_TX_EN — GPIO459 — TXDA — GPIO460 — RXDA — GPIO461 — TXDB — GPIO462 — RXDB — GPIO463
— FlexRay A receive — GPIO — FlexRay A transfer enable — GPIO — eSCI A transmit — GPIO — eSCI A receive — GPIO — eSCI B transmit — GPIO — eSCI B receive — GPIO
— I — I/O — O — I/O — O — I/O — I — I/O — O — I/O — I — I/O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
G22
H23
459 ETPUC18_FR_A_TX_EN_ GPIO4599
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
G20
H24
460 ETPUC19_TXDA_ GPIO4609
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
G21
H21
461 ETPUC20_RXDA _ GPIO4619
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
G19
H25
462 ETPUC21_TXDB_ GPIO4629
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
H22
H26
463 ETPUC22_RXDB_ GPIO4639
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
H21
J22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
K23 K24 K25 K26 L23 L24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 90
464 ETPUC23_PCSD5_ GPIO4649
P A1 A2 A3 G
— PCSD5 MAA0 MAB0 GPIO464 — PCSD4 MAA1 MAB1 GPIO465 — PCSD3 MAA2 MAB2 GPIO466 — PCSD2 — GPIO467 — PCSD1 — GPIO468 — PCSD0 — GPIO469
— DSPI D peripheral chip select ADC A Mux Address 0 ADC B Mux Address 0 GPIO — DSPI D peripheral chip select ADC A Mux Address 1 ADC B Mux Address 1 GPIO — DSPI D peripheral chip select ADC A Mux Address 2 ADC B Mux Address 2 GPIO — DSPI D peripheral chip select — GPIO — DSPI D peripheral chip select — GPIO — DSPI D peripheral chip select — GPIO
— O O O I/O — O O O I/O — O O O I/O — O — I/O — O — I/O — O — I/O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
H20
J23
465 ETPUC24_PCSD4_ GPIO4659
P A1 A2 A4 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
J22
J24
466 ETPUC25_PCSD3_ GPIO4669
P A1 A2 A3 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K22
K21
467 ETPUC26_PCSD2_ GPIO4679
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
J21
J25
468 ETPUC27_PCSD1_ GPIO4689
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
J19
J26
469 ETPUC28_PCSD0_ GPIO4699
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
J20
K22
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
L25 L26 M23 AE10 AF10 AD11
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 91
470 ETPUC29_SCKD_ GPIO4709
P A1 A2 G
— SCKD — GPIO470 — SOUTD — GPIO471 — SIND — GPIO472
— DSPI D clock — GPIO — DSPI D data output — GPIO — DSPI D data input — GPIO
— I/O — I/O — O — I/O — I — I/O
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K21
K23
471 ETPUC30_SOUTD_ GPIO4719
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K20
K24
472 ETPUC31_SIND_ GPIO4729
P A1 A2 G
MH
VDDEH7
—/WKPCFG
—/WKPCFG
K19
K25
eMIOS
179 EMIOS0_ETPUA0_ GPIO179
P A1 A2 G
EMIOS0 ETPUA0 — GPIO179 EMIOS1 ETPUA1 — GPIO180 EMIOS2 ETPUA2 — GPIO181
eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA9
AC13
180 EMIOS1_ETPUA1_ GPIO180
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB9
AB13
181 EMIOS2_ETPUA2_ GPIO181
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y10
AD13
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE11 AF11 AD12 AE12 AF12 AC13
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 92
182 EMIOS3_ETPUA3_ GPIO182
P A1 A2 G
EMIOS3 ETPUA3 — GPIO182 EMIOS4 ETPUA4 — GPIO183 EMIOS5 ETPUA5 — GPIO184 EMIOS6 ETPUA6 — GPIO185 EMIOS7 ETPUA7 — GPIO186 EMIOS8 ETPUA8 — GPIO187
eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO eMIOS channel eTPU A channel — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA10
AE13
183 EMIOS4_ETPUA4_ GPIO183
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB10
AF13
184 EMIOS5_ETPUA5_ GPIO184
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y11
AF14
185 EMIOS6_ETPUA6_ GPIO185
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
—
AE14
186 EMIOS7_ETPUA7_ GPIO186
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB11
AD14
187 EMIOS8_ETPUA8_ GPIO187
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W10
AC14
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AD13 AE13 AF13 AF14 AE14 AC14
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 93
188 EMIOS9_ETPUA9_ GPIO188
P A1 A2 G
EMIOS9 ETPUA9 — GPIO188 EMIOS10 SCKD — GPIO189 EMIOS11 SIND — GPIO190 EMIOS12 SOUTC — GPIO191 EMIOS13 SOUTD — GPIO192 EMIOS14 IRQ0 CNTXD GPIO193
eMIOS channel eTPU A channel — GPIO eMIOS channel DSPI D clock — GPIO eMIOS channel DSPI D data input — GPIO eMIOS channel DSPI C data output — GPIO eMIOS channel DSPI D data output — GPIO eMIOS channel External interrupt request FlexCAN D transmit GPIO
I/O O — I/O I/O O — I/O I/O I — I/O O O — I/O O O — I/O O I O I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W11
AF15
189 EMIOS10_SCKD_ GPIO189
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA11
AE15
190 EMIOS11_SIND_ GPIO190
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB12
AB14
191 EMIOS12_SOUTC_ GPIO191
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB13
AD15
192 EMIOS13_SOUTD_ GPIO192
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA12
AC15
193 EMIOS14_IRQ0_ GPIO193
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y12
AF17
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AD14 AF15 AE15 AC15 AD15 AF16
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 94
194 EMIOS15_IRQ1_ GPIO194
P A1 A2 G
EMIOS15 IRQ1 CNRXD GPIO194 EMIOS16 ETPUB0 FR_DBG[3] GPIO195 EMIOS17 ETPUB1 FR_DBG[2] GPIO196 EMIOS18 ETPUB2 FR_DBG[1] GPIO197 EMIOS19 ETPUB3 FR_DBG[0] GPIO198 EMIOS20 ETPUB4 — GPIO199
eMIOS channel External interrupt request FlexCAN D receive GPIO eMIOS channel eTPU B channel FlexRay debug GPIO eMIOS channel eTPU B channel FlexRay debug GPIO eMIOS channel eTPU B channel FlexRay debug GPIO eMIOS channel eTPU B channel FlexRay debug GPIO eMIOS channel eTPU B channel — GPIO
O I I I/O I/O O O I/O I/O O O I/O I/O O O I/O I/O O O I/O I/O O — I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y13
AE16
195 EMIOS16_ETPUB0_ GPIO195
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB14
AD16
196 EMIOS17_ETPUB1_ GPIO196
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA13
AB15
197 EMIOS18_ETPUB2_ GPIO197
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W12
AD17
198 EMIOS19_ETPUB3_ GPIO198
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y14
AB16
199 EMIOS20_ETPUB4_ GPIO199
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB15
AF16
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE16 AC16 AD16 AF17 AE17 AD17
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 95
200 EMIOS21_ETPUB5_ GPIO200
P A1 A2 G
EMIOS21 ETPUB5 — GPIO200 EMIOS22 ETPUB6 — GPIO201 EMIOS23 ETPUB7 — GPIO202 EMIOS24 PCSB0 — GPIO203 EMIOS25 PCSB1 — GPIO204 EMIOS26 PCSB2 — GPIO432
eMIOS channel eTPU B channel — GPIO eMIOS channel eTPU B channel — GPIO eMIOS channel eTPU B channel — GPIO eMIOS channel DSPI B peripheral chip select — GPIO eMIOS channel DSPI B peripheral chip select — GPIO eMIOS channel DSPI B peripheral chip select — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA14
AE17
201 EMIOS22_ETPUB6_ GPIO201
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W13
AC16
202 EMIOS23_ETPUB7_ GPIO202
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y15
AA16
203 EMIOS24_PCSB0_ GPIO203
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AB16
AC17
204 EMIOS25_PCSB1_ GPIO204
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA15
AF18
432 EMIOS26_PCSB2_ GPIO432
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y16
AE18
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AC17 AF18 AE18 AD18 AC18 A4 B5 C5
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 96
433 EMIOS27_PCSB3_ GPIO433
P A1 A2 G
EMIOS27 PCSB3 — GPIO433 EMIOS28 PCSC0 — GPIO434 EMIOS29 PCSC1 — GPIO435 EMIOS30 PCSC2 — GPIO436 EMIOS31 PCSC5 — GPIO437
eMIOS channel DSPI B peripheral chip select — GPIO eMIOS channel DSPI C peripheral chip select — GPIO eMIOS channel DSPI C peripheral chip select — GPIO eMIOS channel DSPI C peripheral chip select — GPIO eMIOS channel DSPI C peripheral chip select — GPIO
I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O I/O O — I/O
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W14
AD18
434 EMIOS28_PCSC0_ GPIO434
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA16
AC18
435 EMIOS29_PCSC1_ GPIO435
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
AA17
AB17
436 EMIOS30_PCSC2_ GPIO436
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
Y17
AF19
437 EMIOS31_PCSC5_ GPIO437
P A1 A2 G
MH
VDDEH4
—/WKPCFG
—/WKPCFG
W15
AA17
eQADC
— — — ANA0 ANA1 ANA2
P
ANA0 ANA1 ANA2
eQADC A analog input eQADC A analog input eQADC A analog input
I I I
AE/updown AE/updown AE/updown
VDDA_A1 VDDA_A1 VDDA_A1
ANA0 ANA1 ANA2
ANA0 ANA1 ANA2
A4 A5 B5
P
P
C5
516
A4 B5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
D6 A5 B6 C6 D7 A6 C7 B7 A7 D8 C8 B8 A8 D9 C9 D10 C10 D11 C11 D12 C12 B12 D13 C13
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 97
— — — — — — — — — — — — — — — — — — — — — — — —
ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 ANA16 ANA17 ANA18 ANA19 ANA20 ANA21 ANA22 ANA23 AN24 AN25 AN26
P
ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 ANA16 ANA17 ANA18 ANA19 ANA20 ANA21 ANA22 ANA23 AN24 AN25 AN26
eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input
I I I I I I I I I I I I I I I I I I I I I I I I
AE/updown AE/updown AE/updown AE/updown AE/updown AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE
VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A1 VDDA_A0 VDDA_A0 VDDA_A0
ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 ANA16 ANA17 ANA18 ANA19 ANA20 ANA21 ANA22 ANA23 AN24 AN25 AN26
ANA3 ANA4 ANA5 ANA6 ANA7 ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 ANA16 ANA17 ANA18 ANA19 ANA20 ANA21 ANA22 ANA23 AN24 AN25 AN26
B6 A6 A7 B7 B8 C5 C7 C6 D6 D7 C8 D8 A8 D9 C9 D10 C10 D11 C11 D12 C12 — — —
D6 A5 B6 C6 C7 D7 A6 B7 A7 D8 C8 B8 A8 D9 C9 D10 C10 D11 C11 C12 D12 B12 C13 D13
P
P
P
P
P P P P P P P P P P P P P P P P P P P
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
B13 A13 B14 C14 D14 A14 B15 C15 D15 A15 C16 C17 D16 C18 D17 D18 D19 C19 C20 B19 A20 B20
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 98
— — — — — — — — — — — — — — — — — — — — — —
AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 ANB8
P P P P P P P P P P P P P P
AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 ANB8
eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC A and B shared analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input
I I I I I I I I I I I I I I I I I I I I I I
AE AE AE AE AE AE AE AE AE AE AE AE AE AE/updown AE/updown AE/updown AE/updown AE/updown AE/updown AE/updown AE/updown AE
VDDA_A0 VDDA_A0 VDDA_A0 VDDA_B1 VDDA_B1 VDDA_B1 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B1 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0
AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 ANB8
AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 ANB8
— — — — — — — — — — — — — B15 B16 A17 A18 B17 B18 A19 A20 D13
B13 A13 A14 B14 C14 B15 D14 C15 D15 A15 C17 D16 C16 C18 D17 D18 D19 B19 A20 C20 C19 B20
P
P
P
P
P
P
P
P
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
D20 B21 A21 C21 D21 A22 B22 C22 A23 B23 C23 D22 A24 B24 A25 A12 A11 A19 A18 B18 B11 A9 B9 A10 B10 A16 B16
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 99
— — — — — — — — — — — — — — — — — — — — — — — — — — —
ANB9 ANB10 ANB11 ANB12 ANB13 ANB14 ANB15 ANB16 ANB17 ANB18 ANB19 ANB20 ANB21 ANB22 ANB23 VRH_A VRL_A VRH_B VRL_B REFBYPCB REFBYPCA VDDA_A0 VDDA_A1 REFBYPCA1 VSSA_A1 VDDA_B0 VDDA_B1
P P P P P P P P P P P P P P P P P P P P P P P P P P P
ANB9 ANB10 ANB11 ANB12 ANB13 ANB14 ANB15 ANB16 ANB17 ANB18 ANB19 ANB20 ANB21 ANB22 ANB23 VRH_A VRL_A VRH_B VRL_B REFBYPCB REFBYPCA VDDA_A VDDA_A REFBYPCA1 VSSA_A VDDA_B VDDA_B
eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input eQADC B analog input ADC A Voltage reference high ADC A Voltage reference low ADC B Voltage reference high ADC B Voltage reference low ADC B Reference bypass capacitor ADC A Reference bypass capacitor Internal logic supply input Internal logic supply input ADC A Reference bypass capacitor Ground Internal logic supply input Internal logic supply input
I I I I I I I I I I I I I I I I I I I I I I I I I I I
AE AE AE AE AE AE AE AE AE AE AE AE AE AE AE VDDINT VSSINT VDDINT VSSINT AE AE VDDE VDDE AE VSSE VDDE VDDE
VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VDDA_B0 VRH_A VRL_A VRH_B VRL_B VDDA_B0 VDDA_A1 VDDA_A0 VDDA_A1 VDDA_A1 VSSA_A1 VDDA_B0 VDDA_B1
ANB9 ANB10 ANB11 ANB12 ANB13 ANB14 ANB15 ANB16 ANB17 ANB18 ANB19 ANB20 ANB21 ANB22 ANB23 VRH_A VRL_A VRH_B VRL_B REFBYPCB REFBYPCA VDDA_A0 VDDA_A1 REFBYPCA1 VSSA_A1 VDDA_B0 VDDA_B1
ANB9 ANB10 ANB11 ANB12 ANB13 ANB14 ANB15 ANB16 ANB17 ANB18 ANB19 ANB20 ANB21 ANB22 ANB23 VRH_A VRL_A VRH_B VRL_B REFBYPCB REFBYPCA VDDA_A0 VDDA_A1 REFBYPCA1 VSSA_A1 VDDA_B0 VDDA_B1
C14 C13 C15 C16 D14 C17 D15 C18 D16 D17 B19 C19 D18 A21 B20 A10 A11 A16 A15 B12 B11 A9 B9 A12 B10 A13 B13
A21 B21 C21 A22 B22 D20 C22 D21 D22 A23 B23 C23 A24 B24 E20 A12 A11 A19 A18 B18 B11 A9 B9 A10 B10 A16 B16
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
B17 A17 AD4 AE3 AF3 AD5 AE4
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 100
— —
VSSA_B0 REFBYPCB1
P P
VSSA_B REFBYPCB1
Ground ADC B Reference bypass capacitor
I I
VSSE AE
VSSA_B0 VDDA_B0
VSSA_B0 REFBYPCB1
VSSA_B0 REFBYPCB1
B14 A14
B17 A17
FlexRay
248 FR_A_TX_ GPIO248
P A1 A2 G
FR_A_TX — — GPIO248 FR_A_RX — — GPIO249 FR_A_TX_EN — — GPIO250 FR_B_TX — — GPIO251 FR_B_RX — — GPIO252
FlexRay A transfer — — GPIO FlexRay A receive — — GPIO FlexRay A transfer enable — — GPIO FlexRay B transfer — — GPIO FlexRay B receive — — GPIO
O — — I/O I — — I/O O — — I/O O — — I/O I — — I/O
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
Y5
AD4
249 FR_A_RX_ GPIO249
P A1 A2 G
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
AA4
AE3
250 FR_A_TX_EN_ GPIO250
P A1 A2 G
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
AB3
AF3
251 FR_B_TX_ GPIO251
P A1 A2 G
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
Y6
AD5
252 FR_B_RX_ GPIO252
P A1 A2 G
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
AA5
AE4
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AF4 AF19 AE19 AD19 AC19 AF20
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 101
253 FR_B_TX_EN_ GPIO253
P A1 A2 G
FR_B_TX_EN — — GPIO253
FlexRay B transfer enable — — GPIO
O — — I/O
FS
VDDE2
—/Up —/Up (–/– for Rev.1 of (–/– for Rev.1 of the device) the device)
AB5
AF4
FlexCAN
83 CNTXA_TXDA_ GPIO83
P A1 A2 G
CNTXA TXDA — GPIO83 CNRXA RXDA — GPIO84 CNTXB PCSC3 — GPIO85 CNRXB PCSC4 — GPIO86 CNTXC PCSD3 — GPIO87
FlexCAN A transmit eSCI A transmit — GPIO FlexCAN A receive eSCI A receive — GPIO FlexCAN B transmit DSPI C peripheral chip select — GPIO FlexCAN B receive DSPI C peripheral chip select — GPIO FlexCAN C transmit DSPI D peripheral chip select — GPIO
O O — I/O I I — I/O O O — I/O I O — I/O O O — I/O
MH
VDDEH4
—/Up
—/Up
AB17
AE19
84
CNRXA_RXDA_ GPIO84
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
AA18
AD19
85
CNTXB_PCSC3_ GPIO85
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
Y18
AC19
86
CNRXB_PCSC4_ GPIO86
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
W18
AA19
87
CNTXC_PCSD3_ GPIO87
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
W16
AF20
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE20 AD20 AC20 M2 M3 P1
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 102
88
CNRXC_PCSD4_ GPIO88
P A1 A2 G
CNRXC PCSD4 — GPIO88 CNTXD — — GPIO246 CNRXD — — GPIO247
FlexCAN C receive DSPI D peripheral chip select — GPIO FlexCAN D transmit — — GPIO FlexCAN D receive — — GPIO
I O — I/O O — — I/O I — — I/O
MH
VDDEH4
—/Up
—/Up
W17
AE20
246 CNTXD_ GPIO246
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
AB21
AD20
247 CNRXD_ GPIO247
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
Y19
AC20
eSCI
89 TXDA_ GPIO89
P A1 A2 G
TXDA — — GPIO89 RXDA — — GPIO90 TXDB PCSD1 — GPIO91
eSCI A transmit — — GPIO eSCI A receive — — GPIO eSCI B transmit DSPI D peripheral chip select — GPIO
O — — I/O I — — I O O — I/O
MH
VDDEH1
—/Up
—/Up
—
90
RXDA _ GPIO90
P A1 A2 G
MH
VDDEH1
—/Up
—/Up
—
91
TXDB_PCSD1_ GPIO91
P A1 A2 G
MH
VDDEH1
—/Up
—/Up
—
516
K2 K3 K1
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
N1 AF23 AD22 AD8 AF7 AD7
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 103
92
RXDB_PCSD5_ GPIO92
P A1 A2 G
RXDB PCSD5 — GPIO92 TXDC ETRIG0 — GPIO244 RXDC — — GPIO245
eSCI B receive DSPI D peripheral chip select — GPIO eSCI C transmit eQADC trigger input — GPIO eSCI C receive — — GPIO
I O — I/O O I — I/O I — — I/O
MH
VDDEH1
—/Up
—/Up
—
244 TXDC_ETRIG0_ GPIO244
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
—
AF23
245 RXDC_ GPIO245
P A1 A2 G
MH
VDDEH5
—/Up
—/Up
—
AD22
DSPI
93 SCKA_PCSC1_ GPIO93
P A1 A2 G
SCKA PCSC1 — GPIO93 SINA PCSC2 — GPIO94 SOUTA PCSC5 — GPIO95
DSPI A clock DSPI C peripheral chip select — GPIO DSPI A data input DSPI C peripheral chip select — GPIO DSPI A data output DSPI C peripheral chip select — GPIO
I/O O — I/O I O — I/O O O — I/O
MH
VDDEH3
—/Up
—/Up
Y7
AB8
94
SINA_PCSC2_ GPIO94
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
AA7
AE7
95
SOUTA_PCSC5_ GPIO95
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
AB7
AC7
516
L5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE6 AC6 AC7 AE7 AE5 AD6
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 104
96
PCSA0_PCSD2_ GPIO96
P A1 A2 G
PCSA0 PCSD2 — GPIO96 PCSA1 — — GPIO97 PCSA2 — — GPIO98 PCSA3 — — GPIO99 PCSA4 — — GPIO100 PCSA5 ETRIG1 — GPIO101
DSPI A peripheral chip select DSPI D peripheral chip select — GPIO DSPI A peripheral chip select — — GPIO DSPI A peripheral chip select — — GPIO DSPI A peripheral chip select — — GPIO DSPI A peripheral chip select — — GPIO DSPI A peripheral chip select eQADC trigger input — GPIO
I/O O — I/O O — — I/O O — — I/O O — — I/O O — — I/O O I — I/O
MH
VDDEH3
—/Up
—/Up
AB6
AD6
97
PCSA1_ GPIO97
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AC6
98
PCSA2_ GPIO98
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AF6
99
PCSA3_ GPIO99
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AD7
100 PCSA4_ GPIO100
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AE5
101 PCSA5_ETRIG1_ GPIO101
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
AA6
AA8
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE8 AE9 AF9 AD9 AC9 AF8
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 105
102 SCKB_ GPIO102
P A1 A2 G
SCKB — — GPIO102 SINB — — GPIO103 SOUTB — — GPIO104 PCSB0 PCSD2 — GPIO105 PCSB1 PCSD0 — GPIO106 PCSB2 SOUTC — GPIO107
DSPI B clock — — GPIO DSPI B data input — — GPIO DSPI B data output — — GPIO DSPI B peripheral chip select DSPI D peripheral chip select — GPIO DSPI B peripheral chip select DSPI D peripheral chip select — GPIO DSPI B peripheral chip select DSPI C data output — GPIO
I/O — — I/O I — — I/O O — — I/O I/O O — I/O O I/O — I/O O O — I/O
MH
VDDEH3
—/Up
—/Up
Y8
AC8
103 SINB_ GPIO103
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
AA8
AB9
104 SOUTB_ GPIO104
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
AB8
AA10
105 PCSB0_PCSD2_ GPIO105
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
Y9
AF8
106 PCSB1_PCSD0_ GPIO106
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AE8
107 PCSB2_SOUTC_ GPIO107
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
W7
AD8
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AD10 AC8 AF6 AD21 AE22 AF21
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 106
108 PCSB3_SINC_ GPIO108
P A1 A2 G
PCSB3 SINC — GPIO108 PCSB4 SCKC — GPIO109 PCSB5 PCSC0 — GPIO110 SCKC SCK_C_LVDSP — GPIO235 SINC SCK_C_LVDSM — GPIO236 SOUTC SOUT_C_LVDSP — GPIO237
DSPI B peripheral chip select DSPI C data input — GPIO DSPI B peripheral chip select DSPI C clock — GPIO DSPI B peripheral chip select DSPI C peripheral chip select — GPIO DSPI C clock LVDS+ downstream signal positive output clock — GPIO DSPI C data input LVDS– downstream signal negative output clock — GPIO DSPI C data output LVDS+ downstream signal positive output data — GPIO
O I — I/O O I/O — I/O O I/O — I/O I/O O — I/O I O — I/O O O — I/O
MH
VDDEH3
—/Up
—/Up
—
AC9
109 PCSB4_SCKC_ GPIO109
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AF7
110 PCSB5_PCSC0_ GPIO110
P A1 A2 G
MH
VDDEH3
—/Up
—/Up
—
AE6
235 SCKC_SCK_C_LVDSP_ GPIO235
P A1
MH+ LVDS
VDDEH4
—/Up
—/Up
AA19
AD21
A2 G
236 SINC_SCK_C_LVDSM_ GPIO236
P A1
MH+ LVDS
VDDEH4
—/Up
—/Up
AA20
AE22
A2 G
237 SOUTC_SOUT_C_LVDSP_ GPIO237
P A1
MH+ LVDS
VDDEH4
—/Up
—/Up
AB18
AF21
A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AE21 AC22 AE23 AD23 AF24 AE24
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 107
238 PCSC0_SOUT_C_LVDSM_ GPIO238
P A1
PCSC0 SOUT_C_LVDSM — GPIO238 PCSC1 — — GPIO239 PCSC2 — — GPIO240 PCSC3 — — GPIO241 PCSC4 — — GPIO242 PCSC5 — — GPIO243
DSPI C peripheral chip select LVDS– downstream signal negative output data — GPIO DSPI C peripheral chip select — — GPIO DSPI C peripheral chip select — — GPIO DSPI C peripheral chip select — — GPIO DSPI C peripheral chip select — — GPIO DSPI C peripheral chip select — — GPIO
I/O O — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O
MH+ LVDS
VDDEH4
—/Up
—/Up
AB19
AE21
A2 G
239 PCSC1_ GPIO239
P A1 A2 G
MH
VDDEH4
—/Up
—/Up
—
AC22
240 PCSC2_GPIO240
P A1 A2 G
MH
VDDEH5
—/Up
—/Up
—
AE23
241 PCSC3_GPIO241
P A1 A2 G
MH
VDDEH5
—/Up
—/Up
—
AD23
242 PCSC4_GPIO242
P A1 A2 G
MH
VDDEH5
—/Up
—/Up
—
AF24
243 PCSC5_GPIO243
P A1 A2 G
MH
VDDEH5
—/Up
—/Up
—
AE24
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 108
EBI
256 D_CS0_ GPIO256
P A1 A2 G
D_CS0 — — GPIO256 D_CS2 D_ADD_DAT31 — GPIO257 D_CS3 D_TEA — GPIO258 D_ADD12 — — GPIO259 D_ADD13 — — GPIO260 D_ADD14 — — GPIO261
EBI chip select 0 — — GPIO EBI chip select 2 EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI chip select 3 EBI transfer error acknowledge — GPIO EBI address bus — — GPIO EBI address bus — — GPIO EBI address bus — — GPIO
O — — I/O O I/O — I/O O I — I/O I/O — — I/O I/O — — I/O I/O — — I/O
F
VDDE9
—/Up
—/Up
—
AD9
257 D_CS2_D_ADD_DAT31_ GPIO257
P A1
F
VDDE8
—/Up
—/Up
—
U1
A2 G
258 D_CS3_D_TEA_ GPIO258
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
259 D_ADD12_ GPIO259
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
R1
260 D_ADD13_ GPIO260
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
R2
261 D_ADD14_ GPIO261
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
R3
516
T6
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 109
262 D_ADD15_ GPIO262
P A1 A2 G
D_ADD15 — — GPIO262 D_ADD16 D_ADD_DAT16 — GPIO263 D_ADD17 D_ADD_DAT17 — GPIO264 D_ADD18 D_ADD_DAT18 — GPIO265 D_ADD19 D_ADD_DAT19 — GPIO266 D_ADD20 D_ADD_DAT20 — GPIO267
EBI address bus — — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO
I/O — — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O
F
VDDE8
—/Up
—/Up
—
R4
263 D_ADD16_D_ADD_DAT16_ GPIO263
P A1
F
VDDE8
—/Up
—/Up
—
R5
A2 G
264 D_ADD17_D_ADD_DAT17_ GPIO264
P A1
F
VDDE8
—/Up
—/Up
—
A2 G
265 D_ADD18_D_ADD_DAT18_ GPIO265
P A1
F
VDDE8
—/Up
—/Up
—
A2 G
266 D_ADD19_D_ADD_DAT19_ GPIO266
P A1
F
VDDE8
—/Up
—/Up
—
A2 G
267 D_ADD20_D_ADD_DAT20_ GPIO267
P A1
F
VDDE8
—/Up
—/Up
—
A2 G
516
T5 T2 T3 T4
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 110
268 D_ADD21_D_ADD_DAT21_ GPIO268
P A1
D_ADD21 D_ADD_DAT21 — GPIO268 D_ADD22 D_ADD_DAT22 — GPIO269 D_ADD23 D_ADD_DAT23 — GPIO270 D_ADD24 D_ADD_DAT24 — GPIO271 D_ADD25 D_ADD_DAT25 — GPIO272
EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO
I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O
F
VDDE9
—/Up
—/Up
—
AB11
A2 G
269 D_ADD22_D_ADD_DAT22_ GPIO269
P A1
F
VDDE9
—/Up
—/Up
—
AD10
A2 G
270 D_ADD23_D_ADD_DAT23_ GPIO270
P A1
F
VDDE9
—/Up
—/Up
—
AE10
A2 G
271 D_ADD24_D_ADD_DAT24_ GPIO271
P A1
F
VDDE9
—/Up
—/Up
—
AF10
A2 G
272 D_ADD25_D_ADD_DAT25_ GPIO272
P A1
F
VDDE9
—/Up
—/Up
—
AD11
A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 111
273 D_ADD26_D_ADD_DAT26_ GPIO273
P A1
D_ADD26 D_ADD_DAT26 — GPIO273 D_ADD27 D_ADD_DAT27 — GPIO274 D_ADD28 D_ADD_DAT28 — GPIO275 D_ADD29 D_ADD_DAT29 — GPIO276 D_ADD30 D_ADD_DAT30 — GPIO277
EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO EBI address bus EBI data only in non-mux mode. Address and data in mux mode. — GPIO
I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O I/O I/O — I/O
F
VDDE9
—/Up
—/Up
—
AE11
A2 G
274 D_ADD27_D_ADD_DAT27_ GPIO274
P A1
F
VDDE9
—/Up
—/Up
—
AF11
A2 G
275 D_ADD28_D_ADD_DAT28_ GPIO275
P A1
F
VDDE9
—/Up
—/Up
—
AD12
A2 G
276 D_ADD29_D_ADD_DAT29_ GPIO276
P A1
F
VDDE9
—/Up
—/Up
—
AB12
A2 G
277 D_ADD30_D_ADD_DAT30_ GPIO277
P A1
F
VDDE9
—/Up
—/Up
—
AE12
A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 112
278 D_ADD_DAT0_ GPIO278
P
D_ADD_DAT0 — — GPIO278 D_ADD_DAT1 — — GPIO279 D_ADD_DAT2 — — GPIO280 D_ADD_DAT3 — — GPIO281 D_ADD_DAT4 — — GPIO282
EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O
F
VDDE10
—/Up
—/Up
—
P25
A1 A2 G
279 D_ADD_DAT1_ GPIO279
P
F
VDDE10
—/Up
—/Up
—
P26
A1 A2 G
280 D_ADD_DAT2_ GPIO280
P
F
VDDE10
—/Up
—/Up
—
N24
A1 A2 G
281 D_ADD_DAT3_ GPIO281
P
F
VDDE10
—/Up
—/Up
—
N25
A1 A2 G
282 D_ADD_DAT4_ GPIO282
P
F
VDDE10
—/Up
—/Up
—
N26
A1 A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 113
283 D_ADD_DAT5_ GPIO283
P
D_ADD_DAT5 — — GPIO283 D_ADD_DAT6 — — GPIO284 D_ADD_DAT7 — — GPIO285 D_ADD_DAT8 — — GPIO286 D_ADD_DAT9 — — GPIO287
EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O
F
VDDE10
—/Up
—/Up
—
M25
A1 A2 G
284 D_ADD_DAT6_ GPIO284
P
F
VDDE10
—/Up
—/Up
—
N22
A1 A2 G
285 D_ADD_DAT7_ GPIO285
P
F
VDDE10
—/Up
—/Up
—
M24
A1 A2 G
286 D_ADD_DAT8_ GPIO286
P
F
VDDE10
—/Up
—/Up
—
M23
A1 A2 G
287 D_ADD_DAT9_ GPIO287
P
F
VDDE10
—/Up
—/Up
—
M22
A1 A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 114
288 D_ADD_DAT10_ GPIO288
P
D_ADD_DAT10 — — GPIO288 D_ADD_DAT11 — — GPIO289 D_ADD_DAT12 — — GPIO290 D_ADD_DAT13 — — GPIO291 D_ADD_DAT14 — — GPIO292
EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI data only in non-mux mode. Address and data in mux mode. — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O I/O — — I/O
F
VDDE10
—/Up
—/Up
—
L26
A1 A2 G
289 D_ADD_DAT11_ GPIO289
P
F
VDDE10
—/Up
—/Up
—
L25
A1 A2 G
290 D_ADD_DAT12_ GPIO290
P
F
VDDE10
—/Up
—/Up
—
L24
A1 A2 G
291 D_ADD_DAT13 _GPIO291
P
F
VDDE10
—/Up
—/Up
—
L23
A1 A2 G
292 D_ADD_DAT14_GPIO292
P
F
VDDE10
—/Up
—/Up
—
L22
A1 A2 G
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 115
293 D_ADD_DAT15_GPIO293
P
D_ADD_DAT15 — — GPIO293 D_RD_WR — — GPIO294 D_WE0 — — GPIO295 D_WE1 — — GPIO296 D_OE — — GPIO297 D_TS — — GPIO298
EBI data only in non-mux mode. Address and data in mux mode. — — GPIO EBI read/write — — GPIO EBI write enable — — GPIO EBI write enable — — GPIO EBI output enable — — GPIO EBI transfer start — — GPIO
I/O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O
F
VDDE10
—/Up
—/Up
—
K26
A1 A2 G
294 D_RD_WR_GPIO294
P A1 A2 G
F
VDDE10
—/Up
—/Up
—
R26
295 D_WE0_GPIO295
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
N1
296 D_WE1_GPIO296
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
297 D_OE_GPIO297
P A1 A2 G
F
VDDE10
—/Up
—/Up
—
P23
298 D_TS_GPIO298
P A1 A2 G
F
VDDE9
—/Up
—/Up
—
AE9
516
P5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — — — —
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 116
299 D_ALE_GPIO299
P A1 A2 G
D_ALE — — GPIO299 D_TA — — GPIO300 D_CS1 — — GPIO301 D_BDIP — — GPIO302 D_WE2 — — GPIO303 D_WE3 — — GPIO304
EBI Address Latch Enable — — GPIO EBI transfer acknowledge — — GPIO EBI chip select — — GPIO EBI burst data in progress — — GPIO EBI write enable — — GPIO EBI write enable — — GPIO
O — — I/O I/O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O
F
VDDE10
—/Up
—/Up
—
P24
300 D_TA_GPIO300
P A1 A2 G
F
VDDE9
—/Up
—/Up
—
AF9
301 D_CS1_GPIO301
P A1 A2 G
F
VDDE9
—/Up
—/Up
—
AB10
302 D_BDIP_GPIO302
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
M2
303 D_WE2_GPIO303
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
N2
304 D_WE3_GPIO304
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
N3
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
— — — R2 A3 — N2
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 117
305 D_ADD9_GPIO305
P A1 A2 G
D_ADD9 — — GPIO305 D_ADD10 — — GPIO306 D_ADD11 — — GPIO307
EBI address bus — — GPIO EBI address bus — — GPIO EBI address bus — — GPIO
I/O — — I/O I/O — — I/O I/O — — I/O
F
VDDE8
—/Up
—/Up
—
306 D_ADD10_GPIO306
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
307 D_ADD11_GPIO307
P A1 A2 G
F
VDDE8
—/Up
—/Up
—
Reset and Clocks
— RESET
P P
RESET RSTOUT BOOTCFG0 IRQ2 — GPIO211 BOOTCFG1 IRQ3 — GPIO212
External reset input External reset output Boot configuration
I O I I
MH MH MH
VDDEH1 VDDEH1 VDDEH1
RESET/Up RSTOUT/Low BOOTCFG/ Down
RESET/Up RSTOUT/ High BOOTCFG/ Down
M2 A3 —
N5 A3 L4
230 RSTOUT 211 BOOTCFG0_IRQ2_ GPIO211
P A1 A2 G
— GPIO Boot configuration External interrupt request — GPIO
— I/O I I — I/O MH VDDEH1 BOOTCFG/ Down Input/Down L1 L3
212 BOOTCFG1_IRQ3_ GPIO212
P A1 A2 G
516
P1 P2 P3
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
N3 R3 P2 P3 AC26 AB26 — AD1 T4 U1 T2
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 118
213 WKPCFG_NMI_ GPIO213
P A1 A2 G
WKPCFG NMI — GPIO213 PLLCFG0 IRQ4 — GPIO208 PLLCFG1 IRQ5 SOUTD GPIO209 PLLCFG2 XTAL EXTAL D_CLKOUT ENGCLK
Weak pull configuration input Critical interrupt to core10 — GPIO FMPLL mode configuration input External interrupt request — GPIO FMPLL mode configuration input External interrupt request DSPI D data output GPIO FMPLL mode configuration input Crystal oscillator output Crystal oscillator input EBI system clock output EBI engineering clock output Note: EXTCLK (External clock input) selected through SIU register)
I I — I I I — I/O I I O I/O I O I O O
MH
VDDEH1
WKPCFG/Up
Input/Up
—
M5
208 PLLCFG0_IRQ4_ GPIO208
P A1 A2 G
MH
VDDEH1
PLLCFG/Up
Input/Up
M3
M3
209 PLLCFG1_IRQ5_ GPIO209
P A1 A2 G
MH
VDDEH1
PLLCFG/Up
Input/Up (for Rev2 of the device: —/Up)
L2
— — —
PLLCFG2 XTAL EXTAL
P
MH AE AE F F
VDDEH1 VDD33 VDD33 VDDE9 VDDE2
PLLCFG/ Down XTAL EXTAL CLKOUT/ Enabled ENGCLK/ Enabled
PLLCFG/ Down XTAL EXTAL CLKOUT/ Enabled ENGCLK/ Enabled
L3 W22 V22 — AA1
P P P
AC26 AB26 AF12 AD1
229 D_CLKOUT 214 ENGCLK
P
JTAG and Nexus (see footnote11 about resets)
— EVTI
–12 –12
EVTI EVTO
Nexus event in Nexus event out
I O
F F
VDDE2 VDDE2
—/Up ABS/Up
EVTI/Up EVTO/HI
N4 P1
227 EVTO (the BAM uses this pin to select if auto baud rate is on or off) 219 MCKO
–12
MCKO
Nexus message clock out
O
F
VDDE2
O/Low
Disabled13
N2
U4
516
L1 L2 V1 V2
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
U3 U4 V1 V2 V3 V4
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 119
–12 220 MDO0_GPIO220 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G
MDO0 — — GPIO220 MDO1 — — GPIO221 MDO2 — — GPIO222 MDO3 — — GPIO223 MDO4 — — GPIO75 MDO5 — — GPIO76
Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO
O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O
F
VDDE2
O/Low
MDO0/Low
P3
221 MDO1_GPIO221 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G – 222 MDO2_GPIO222 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G – 223 MDO3_GPIO223 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G
–12
F
VDDE2
O/Low
—/Down
P4
W6
12
F
VDDE2
O/Low
—/Down
R1
12
F
VDDE2
O/Low
—/Down
R2
75
MDO4_GPIO75 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G
–12
F
VDDE2
O/Low
—/Down
R3
W1
76
MDO5_GPIO76 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G
–12
F
VDDE2
O/Low
—/Down
R4
W2
516
V3 V4 V5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
W1 W2 W3 Y1 Y2 Y3
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 120
77
–12 MDO6_GPIO77 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G
MDO6 — — GPIO77 MDO7 — — GPIO78 MDO8 — — GPIO79 MDO9 — — GPIO80 MDO10 — — GPIO81 MDO11 — — GPIO82
Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO
O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O O — — I/O
F
VDDE2
O/Low
—/Down
T1
W3
78
MDO7_GPIO78 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G
–12
F
VDDE2
O/Low
—/Down
T2
79
– MDO8_GPIO79 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G
12
F
VDDE2
O/Low
—/Down
T3
W5
80
– MDO9_GPIO80 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2 G
12
F
VDDE2
O/Low
—/Down
U1
81
MDO10_GPIO81 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G
–12
F
VDDE2
O/Low
—/Down
U2
82
MDO11_GPIO82 (GPIO function on this pin is A1 only available on Rev.2 of the device) A2
G
–12
F
VDDE2
O/Low
—/Down
U3
516
Y1 Y2 Y3 Y4
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AA1 AA2 AA3 Y4 U2 T3 R4 AB2 AC2 AB1 AB3 R1 B4 AD26
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 121
231 MDO12_GPIO231
–12 A1 A2 G
MDO12 — — GPIO231 MDO13 — — GPIO232 MDO14 — — GPIO233 MDO15 — — GPIO234 MSEO0 MSEO1 RDY TCK TDI TDO TMS JCOMP TEST VDDSYN
Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message data out — — GPIO Nexus message start/end out Nexus message start/end out Nexus ready output JTAG test clock input JTAG test data input JTAG test data output JTAG test mode select input JTAG TAP controller enable Test mode select (not for customer use) Clock synthesizer power input
O — — I/O O — — I/O O — — I/O O — — I/O O O O I I O I I I I
F
VDDE2
O/Low
—/Down
V1
232 MDO13_GPIO232
–12 A1 A2 G
F
VDDE2
O/Low
—/Down
W2
AA1
233 MDO14_GPIO233
–
12
F
VDDE2
O/Low
—/Down
V3
AA2
A1 A2 G
234 MDO15_GPIO234
–
12
F
VDDE2
O/Low
—/Down
U4
AA3
A1 A2 G
224 MSEO0 225 MSEO1 226 RDY — — TCK TDI
–12 – – –
12 12 12
F F F F F F F F F VDDE
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VDDEH1 VDDSYN
O/Low O/Low O/Low TCK/Down TDI/Up TDO/Up TMS/Up JCOMP/Down TEST/Down VDDSYN
MSEO/HI MSEO/HI RDY/HI TCK/Down TDI/Up TDO/Up TMS/Up JCOMP/Down TEST/Down VDDSYN
P2 N3 M4 Y1 Y2 W1 W3 M1 B4 Y22
U6 U5 U3 AB2 AC2 AB1 AB3 U2 B4 AD26
–12 – –
12 12
228 TDO — — — — TMS JCOMP TEST VDDSYN
–12 —
—
516
Y5
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
Table 43. Signal Properties and Muxing Summary (continued)
GPIO/PCR1 Pad Type5 Direction Voltage6 P/A/G3 Package Location 324 416
AA26 M4 W23 Y26 AB25 AA25
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 122
— — — — — —
1
VSSSYN VSTBY REGSEL REGCTL VSSFL VDDREG
— — —
VSSSYN VSTBY REGSEL REGCTL VSSFL VDDREG
Clock synthesizer ground input SRAM standby power input Selects regulator mode (Linear/Switch mode) Regulator controller output to base/gate of power transistor Tie to VSS Source voltage for on-chip regulators and Low voltage detect circuits
I I I O I I
VSSE VHV AE AE VSS VDDINT
VDDSYN VDDEH1 VDDREG VDDREG VDDREG VDDREG
VSSSYN VSTBY REGSEL REGCTL VSSFL VDDREG
VSSSYN VSTBY REGSEL REGCTL VSSFL VDDREG
U22 K4 V20 T22 V21 U21
AA26 M4 W23 Y26 AB25 AA25
—
— —
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO functionality, this number is the PCR number. 2 The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type. 3 P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO. 4 Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are designated in the PA field of the SIU_PCRn registers except where explicitly noted. 5 MH = High voltage, medium speed F = Fast speed FS = Fast speed with slew AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad) VHV = Very high voltage 6 VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 3.3 V (±10%) power supply. 7 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. 8 The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 9 This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C. 10 NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers. 11 Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO are also dependent on trace (RPM or FPM) being enabled.
516
Signal
Name2
Function4
Function Summary
State during State RESET7 after RESET8
12 The
Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of these pins once enabled. 13 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).
Freescale Semiconductor MPC5674F Microcontroller Data Sheet, Rev. 6 123
Table 44 lists the pin locations of the power and ground signals on the 324 TEPBGA package. Table 44. 324-pin Power Supply Locations
VDD A2 VDD33 W21 VDDE2 AB4 MPC5674F Microcontroller Data Sheet, Rev. 6 VDDEH1 B1 VSS A1 K10 N12 A22 K11 N13 AA2 K12 N14 AA21 K13 P11 AB1 K14 P12 AB22 K9 P13 B2 L10 P14 B21 L11 W19 C20 L12 W4 C3 L13 Y20 D19 L14 Y3 D4 L9 J10 M10 J11 M11 J12 M12 J13 M13 J14 M14 J9 N11 L4 M9 N1 N10 N9 P10 P9 T4 W6 VDDEH6 W8 N20 T21 V2 VDDEH7 C22 H19 L22 V4 B3 C4 D5 K3 V19 W5 W9 W20 Y4 Y21 AA3 AA22 AB2
Freescale Semiconductor 124
VDDEH4 AB20
Signal Properties and Muxing
Table 45 lists the pin locations of the power and ground signals on the 416 TEPBGA package. Table 45. 416-pin Power Supply Locations
VDD A2 VDD33 M1 VDDE2 N10 P10 P11 R10 R11 VDDEH3 P4 AC10 AF5 T1 T10 T11 T12 U10 U11 U12 W4 AC1 AC5 AF2 AA4 AA23 B3 C4 D5 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDDEH1 B1 VDDEH6 N23 VSS A1 L12 N15 T16 A26 L13 N16 T17 B2 L14 N17 U13 B25 L15 P12 U14 AC25
VDDEH4 AC11 AF22
VDDEH5 AC21 AF25
VDDEH7 D24 E23 M26
C3 L16 P13 U15
C24 L17 P14 U16
D4 M10 P15 U17
D23 M11 P16 AC4
K10 M12 P17 AC23
K11 M13 R12 AD3
K12 M14 R13 AD24
K13 M15 R14 AE2
K14 M16 R15 AE25
K15 M17 R16 AF1
K16 N11 R17 AF26
K17 N12 T13
L10 N13 T14
L11 N14 T15
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 125
Signal Properties and Muxing
Table 46 lists the pin locations of the power and ground signals on the 516 TEPBGA package. Table 46. 516-pin Power Supply Locations
VDD A2 VDD33 M1 VDDE2 N10 VDDE8 F6 F8 F10 F11 N6 AA5 P10 P11 R10 R11 T1 T10 T11 T12 VDDE9 AA13 AB6 AB7 AB18 AB19 AB20 AB21 U10 U11 U12 W4 AC1 AC5 AF2 P6 L21 AA4 AA11 AA14 AA23 B3 C4 D5 E6 N4 AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26
VDDE10 F16 F17 F19 F21 N21 P21 AA22
VDDEH1 B1 P4
VDDEH3 AC10 AF5
VDDEH4 AC11 AF22
VDDEH5 AC21 AF25
VDDEH6 N23 AC25 VSS A25 E16 L11 N14 T15 B2 E17 L12 N15 T16 B25 E18 L13 B26 E19 L14
VDDEH7 D24 E23 M26
C3 E21 L15 P12 U14
C24 E22 L16 P13 U15
D4 F5 L17 P14 U16
D23 F13 M10 P15 U17
E5 F14 M11 P16 AA6
E7 K10 M12 P17 AA21
E8 K11 M13 R12 AB5
E9 K12 M14 R13 AB22
E10 K13 M15 R14 AC4
E11 K14 M16 R15 AC23
E12 K15 M17 R16 AD3
E13 K16 N11 R17 AD24
E14 K17 N12 T13 AE2
E15 L10 N13 T14 AE25
N16 N17 T17 U13
MPC5674F Microcontroller Data Sheet, Rev. 6 126 Freescale Semiconductor
Signal Properties and Muxing
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 127
Revision History
Appendix B Revision History
Table 47 describes the changes made to this document between revisions. Table 47. Revision History
Revision (Date) 2 Initial release, NDA Required. (Sept 2008) 3 (Nov 2009) Added 516-pin package figures. Signals table: Updates throughout entire table. Updated Section 4.6, “Power Up/Down Sequencing” Updated features list. Updated flash PFCPR1 settings table. Fixed JTAG Test Clock Input Timing figure so the spec #’s in table matched figure. Updated Orderable Part numbers table. Moved signals table to be an appendix. Added 324-pin package thermals. Updated part numbers in orderable parts table (missing F: MPC5674F). FMPLL Electrical Spec table: Spec #1 changed min values of 4 to 8 Removed last sentence of footnote 2 Added note "Upper tolerance of less than 1% is allowed on 40MHz crystal." Oscillator Electrical Spec table: Moved predivider op. frequency spec from this table to the FMPLL Electrical Spec table Removed footnote #3 (since VDDE9 is an external supply and has no relation to the oscillator, PMC, or PLL). Added maximum solder temperature to Absolute Max Ratings table. PMC Operating Conditions table: Removed JTemp row. Changed VDDR to VDDREG (naming consistency) Changed VDD12 to VDD (naming consistency) PMC Electrical Spec table: Added VDDREG to this parameter “Trimmed bandgap reference voltage / voltage dependence (VDDREG)” Changed VDDSTEP to LVDSTEP12 (naming consistency) Added two conditons to the opening statements of Section 4.6, “Power Up/Down Sequencing.” DC Electrical Specifications table: spec #9 (Fast I/O Input High Voltage) spec #10 (Fast I/O Input Low Voltage) spec #24 (Operating Current 1.2 V Supplies; IDD) spec #25 (Operating Current 3.3 V Supplies; IDDSYN) spec #32 (Analog Input Current, Channel Off; IINACT_A) footnote #12 ("IOH_S = {11.6} mA...") Changes between Rev.2 and Rev. 3: Description of changes
MPC5674F Microcontroller Data Sheet, Rev. 6 128 Freescale Semiconductor
Revision History
Table 47. Revision History (continued)
Revision (Date) 3 (cont.) Description of changes eQADC Conversion Specifications table: Spec #7, 8: both +/-3, no dependency on frequency Spec #15, 16: added "(with calibration)" to both Flash Program and Erase Specifications table: Added footnote 4 to spec #2. Updated all initial max value times. Updated entire AC Specifications: Clocking section. Pad AC Specifications table: updated Medium pad specs Derated Pad AC Specifications table: updated all specs Updated entire Section 4.6, “Power Up/Down Sequencing.” Updated Absolute Maximum Ratings (AMR) specs 1–11, 15, 16. Changed name of IDDC to IREGCTL since it is the REGCTL max drive current. Added two EMC Radiated Emissions Operating Behaviors tables and removed “EMI Testing Specifications” table. PMC Electrical Specifications table: 1b: Changed 1% to 2% 1c: Changed 150 to 300 ppm/C 2b: added footnote 2c: Changed from "Trimming step VDD" to "Trimming step VDD12OUT" DC Electrical Specifications table: 6: Updated min value and added keep-out range Standby RAM Regulator Electrical Specifications table: Added brownout spec PMC electrical spec table, added new specs: SMPS regulator output resistance, SPMS regulator clock frequency, SMPS regulator overshoot at start-up, SMPS max output current, and voltage variation on current step. Added LVD VDDA specs to the PMC electrical spec table. Removed specs for VDDF and VFLASH since those supplies are shorted with others in the package. 4 (Aug 2010) Changes between Rev.3 and Rev.4: Table “Derated Pad AC Specifications”, Spec #1: Changed 20ns to 200ns. Added “324-ball TEPBGA Pin Assignments” section and mechanical drawings. Appendix A (Signals): Added “(the BAM uses this pin to select if auto baud rate is on or off)” to the EVTO pin description. Added 324 pinout column. Changed footnote from “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU DIRER register.“ to “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.” Updated eQADC signals to show that eQADC A and B each have dedicated channels (ANx0-23) and shared channels (AN24-39).
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 129
Revision History
Table 47. Revision History (continued)
Revision (Date) 4 (cont) Description of changes “Temperature Sensor Electrical Specifications” table: Changed spec #2 to have one temperature range (-40 - 150 C) and changed spec value from ±1.0 to ±10.0 C. “eQADC Conversion Specifications (Operating)” table: Changed spec #13 (non-disruptive injection current) values from ±1 to ±3. "IPCLKDIV Settings" table, removed footnote "eMIOS and DMA are not considered peripherals here." 5 Note 4 in Maximum Ratings updated from 2.0 V to 1.65 V. (Feb-2011) Changed I/O Supply Voltage spec in DC Electrical specs, Spec 2, from 1.62 V min to 3.0 V min. Changed the APC=RWSC value in line 1 of PFCPR1 Settings vs. Frequency of Operation table from 0b011 to 0b100 Changed note 1 for Pad AC Specifications table from Vdde = 1.62 V to 1.98 V to read Vdde = 3.0 V to 3.6 V Changed note 6 for Signal Properties and Muxing Summary table by removing the voltage range 1.8 V - 3.3 V to have 3.3 V instead of the range. Spec 2 in Table 9 “ESD Ratings“ the spec for “ESD for Charged Device Model (CDM)” changed to 250 V (other) from 500 V (other) Removed voltage ranges 1.62-1.98 V and 2.25-2.75 V from spec 28 in Table 14
MPC5674F Microcontroller Data Sheet, Rev. 6 130 Freescale Semiconductor
Revision History
MPC5674F Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 131
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Document Number: MPC5674F Rev. 6 2/2011
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