MPC5674K

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5675K Rev. 4, 04/2011 MPC5675K MAPBGA–225 15 mm x 15 mm QFN12 ##_mm_x_##mm MPC5675K Microcontroller Data Sheet 1 Overview 1 SOT-343R ##_mm_x_##mm 473 MAPBGA (19 x 19 mm) TBD PKG-TBD ## mm x ## mm 257 MAPBGA (14 x 14 mm) This document provides electrical specifications, pin assignments, and package diagrams for the MPC5675K series of microcontroller units (MCUs). The MPC5675K microcontroller is a 32-bit embedded controller designed for advanced driver assistance systems with RADAR, CMOS imaging, LIDAR and ultrasonic sensors, and multiple 3-phase motor control applications as in hybrid electric vehicles (HEV) in automotive and high temperature industrial applications. A member of Freescale Semiconductor’s MPC5500/5600 family, it contains the Book E compliant Power Architecture technology core with Variable Length Encoding (VLE). This core complies with the Power Architecture embedded category, and is 100 percent user mode compatible with the original Power PC user instruction set architecture (UISA). It offers system performance up to four times that of its MPC5561 predecessor, while bringing you the reliability and familiarity of the proven Power Architecture technology. A comprehensive suite of hardware and software development tools is available to help simplify and speed system design. Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments. 2 3 4 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 23 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 73 3.3 Recommended operating conditions . . . . . . . . . . . . . . 75 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5 Electromagnetic interference (EMI) characteristics . . . 79 3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 79 3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.8 Power Management Controller (PMC) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 82 3.10 Temperature sensor electrical characteristics . . . . . . . 83 3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 83 3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 84 3.13 16 MHz RC oscillator electrical characteristics . . . . . . 85 3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 85 3.15 Flash memory electrical characteristics . . . . . . . . . . . . 91 3.16 SRAM memory electrical characteristics . . . . . . . . . . . 93 3.17 GP pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 95 3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . 100 3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 106 3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 114 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 136 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 143 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009–2011. All rights reserved. Preliminary—Subject to Change Without Notice Overview 1.1 Device comparison Table 1. MPC5675K family device comparison Features CPU Type Architecture Execution speed Nominal platform frequency (in 1:1, 1:2, and 1:3 modes) MMU Instruction set PPC Instruction set VLE Instruction cache Data cache MPU Buses Core bus Internal periphery bus XBAR Memory Master  slave ports Static RAM (SRAM) Code Flash memory Data Flash memory Modules Analog-to-Digital Converter (ADC) CRC unit Cross Triggering Unit (CTU) Deserial Serial Peripheral Interface (DSPI) Digital I/Os DRAM Controller (DRAMC) Enhanced Direct Memory Access (eDMA) eTimer No 2 modules (3 chip selects)  16 Yes3 2 modules, 32 channels each 3 modules, 6 channels each 256 KB (ECC) 1 MB2 0–150 MHz (+2% FM) 0–75 MHz (+2% FM) MPC5673K MPC5674K MPC5675K 2 × e200z7d (SoR1) in lock-step or decoupled operation Harvard 0–180 MHz (+2% FM) 0–90 MHz (+2% FM) 0–180 MHz (+2% FM) 0–90 MHz (+2% FM) 64 entries (SoR) Yes Yes 16 KB, 4-way with EDC (SoR) 16 KB, 4-way with EDC (SoR) Yes (SoR) 32-bit address, 64-bit data 32-bit address, 32-bit data Yes (SoR) 384 KB (ECC) 1.5 MB2 64 KB2 257 pin pkg: 4 × 12 bit (22 external channels) 473 pin pkg: 4 × 12 bit (up to 34 external channels) 2 (3 contexts each) 2 modules 3 modules (3 chip selects) 512 KB (ECC) 2 MB2 MPC5675K Microcontroller Data Sheet, Rev. 4 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview Table 1. MPC5675K family device comparison (continued) Features Modules (cont.) External Bus Interface (EBI) Fast Ethernet Controller (FEC) Fault Collection and Control Unit (FCCU) FlexCAN FlexPWM FlexRay I2C Interrupt Controller (INTC) LINFlex Parallel Data Interface (PDI) Periodic Interrupt Timer (PIT) Software Watchdog Timer (SWT) System Timer Module (STM) Temperature sensor Wakeup Unit (WKPU) Crossbar switch (XBAR) Clocking Clock monitor unit (CMU) Clock output Frequency-modulated phase-locked loop (FMPLL) IRCOSC – 16 MHz XOSC 4 MHz – 40 MHz Supply Power management unit (PMU) 1.2 V low-voltage detector (LVD12) 1.2 V high-voltage detector (HVD12) 2.7 V low-voltage detector (LVD27) 3 modules 1 module4 2 modules Yes (SoR) 4 modules MPC5673K MPC5674K MPC5675K 1 module3 16-bit Data + Address or 32-bit Data with Address bus muxed4 1 module 1 module 4 modules (32 message buffers each) 3 modules (each 4 × 3 channels) Optional 3 modules 1 module, 4 channels Yes (SoR) Yes (SoR) 1 module Yes 3 modules, 2 are user-configurable 3 modules 2 modules 2 modules (system and auxiliary) 1 1 Yes 1 1 4 MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Overview Table 1. MPC5675K family device comparison (continued) Features Debug Packages Temperature Nexus MAPBGA Ambient MPC5673K MPC5674K Class 3+ (for cores and SRAM ports) 257 pins 473 pins See the TA recommended operating condition in the device data sheet MPC5675K NOTES: 1 Sphere of Replication. 2 Does not include Test or Shadow Flash memory space. 3 Available only on 473-pin package. 4 DDR available only on 473 package. Other modules available as follows: EBI or DDR on 473 package. EBI + PDI on 473 package. DDR + PDI on 473 package PDI only on 257 package. MPC5675K Microcontroller Data Sheet, Rev. 4 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview 1.2 Block diagram Figure 1 shows a top-level block diagram of the MPC5675K device. ECSM_0 STM INTC SEMA4 e200z7d Core_0 JTAG Nexus FlexRay RC e200z7d Core_1 MMU I-CACHE D-CACHE MMU I-CACHE D-CACHE ECSM_1 STM INTC SEMA4 DMA_0 PDI FEC DMA_1 Crossbar switch (XBAR_2) Crossbar switch (XBAR_0) Memory protection unit EBI PFLASHC SRAM with ECC Logic RC mDDR Crossbar switch (XBAR_1) Memory protection unit PFLASHC RC RC RC SRAM with ECC Logic PBRIDGE PBRIDGE Secondary PLL PBRIDGE IRCOSC FMPLL TSENS SSCM CMU CMU CMU BAM CRC CRC DSPI FlexPWM FlexPWM FlexPWM FlexCAN FlexCAN FlexCAN FlexCAN WakeUp LINFlex LINFlex LINFlex LINFlex eTimer eTimer eTimer XOSC SIUL ADC BAM CMU CRC CTU DSPI EBI ECC ECSM eDMA FCCU FEC FlexCAN FlexPWM FMPLL I2 C INTC – Analog-to-digital converter – Boot assist module – Clock monitoring unit – Cyclic redundancy check unit – Cross triggering unit – Deserial serial peripheral interface – External bus interface – Error correction code – Error correction status module – Enhanced direct memory access controller – Fault collection and control unit – Fast Ethernet controller – Controller area network controller – Pulse width modulator module – Frequency-modulated phase-locked loop – Inter-integrated circuit controller – Interrupt controller IRCOSC JTAG MC mDDR PBRIDGE PDI PIT PMU RC RTC SEMA4 SIUL SSCM STM SWT TSENS XOSC – Internal RC oscillator – Joint Test Action Group interface – Mode entry, clock, reset, & power modules – Mobile double data rate dynamic RAM – Peripheral bridge – Parallel data interface – Periodic interrupt timer – Power management unit – Redundancy checker – Real time clock – Semaphore unit – System integration unit Lite – System status and configuration module – System timer module – Software watchdog timer – Temperature sensor – Crystal oscillator Figure 1. MPC5675K block diagram MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 FCCU DSPI DSPI ADC ADC ADC ADC CTU CTU MC I2C I2C I2C PIT Overview 1.3 • Feature list High-performance e200z7d dual core — 32-bit Power Architecture technology CPU — Up to 180 MHz core frequency — Dual-issue core — Variable length encoding (VLE) — Memory management unit (MMU) with 64 entries — 16 KB instruction cache and 16 KB data cache Memory available — Up to 2 MB Code flash memory with ECC — 64 KB Data flash memory with ECC — Up to 512 KB on-chip SRAM with ECC SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection — Sphere of replication (SoR) for key components — Redundancy checking units on outputs of the SoR connected to FCCU — Fault collection and control unit (FCCU) — Boot-time built-in self-test for memory (MBIST) and logic (LBIST) triggered by hardware — Boot-time built-in self-test for ADC and flash memory — Replicated safety-enhanced watchdog timer — Junction temperature sensor — Non-maskable interrupt (NMI) — 16-region memory protection unit (MPU) — Clock monitoring units (CMU) — Power management unit (PMU) — Cyclic redundancy check (CRC) units Decoupled Parallel mode for high-performance use of replicated cores Nexus Class 3+ interface Interrupts — Replicated 16-priority interrupt controller — Replicated 32-channel eDMA controller GPIOs individually programmable as input, output, or special function Three general-purpose eTimer units (6 channels each) Three FlexPWM units with four 16-bit channels per module Communications interfaces — 4 LINFlex modules — 3 DSPI modules with automatic chip select generation — 4 FlexCAN interfaces (2.0B Active) with 32 message objects MPC5675K Microcontroller Data Sheet, Rev. 4 • • • • • • • • • 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview • • • • • • • — FlexRay module (V2.1) with dual channel, up to 128 message objects and up to 10 Mbit/s — Fast Ethernet Controller (FEC) — 3 I2C modules Four 12-bit analog-to-digital converters (ADCs) — 22 input channels — Programmable cross triggering unit (CTU) to synchronize ADC conversion with timer and PWM External bus interface 16-bit external DDR memory controller Parallel digital interface (PDI) On-chip CAN/UART bootstrap loader Capable of operating on a single 3.3 V voltage supply — 3.3 V-only modules: I/O, oscillators, flash memory — 3.3 V or 5 V modules: ADCs, supply to internal VREG — 1.8–3.3 V supply range: DRAM/PDI Operating junction temperature range –40 to 150 °C 1.4 1.4.1 • • • • • • • • Feature details High-performance e200z7d core processor Dual 32-bit Power Architecture processor core Loose or tight core coupling Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction Thirty-two 64-bit general-purpose registers (GPRs) Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB) Branch processing unit Fully pipelined load/store unit 16 KB Instruction and 16 KB Data caches per core with line locking — Four way set associative — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data parity Vectored interrupt support Signal processing engine 2 (SPE2) auxiliary processing unit (APU) operating on 64-bit general purpose registers • • MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Overview • • • • Floating point — IEEE 754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the MPC5675K To reduce latency, long cycle time instructions are aborted upon interrupt requests Extensive system development support through Nexus debug module 1.4.2 • • Crossbar switch (XBAR) 32-bit address bus, 64-bit data bus Simultaneous accesses from different masters to different slaves (there is no clock penalty when a parked master accesses a slave) 1.4.3 Memory Protection Unit (MPU) The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA, FlexRay, CPU) can be assigned different access rights to each region. • 16-region MPU with concurrent checks against each master access • 32-byte granularity for protected address region 1.4.4 • • • • • Enhanced Direct Memory Access (eDMA) controller 32 channels support independent 8-, 16-, 32-bit single value or block transfers Supports variable-sized queues and circular queues Source and destination address registers are independently configured to post-increment or remain constant Each transfer is initiated by a peripheral, CPU, or eDMA channel request Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer 1.4.5 • • • • • Interrupt Controller (INTC) 208 peripheral interrupt requests 8 software settable sources Unique 9-bit vector per interrupt source 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source Priority elevation for shared resources MPC5675K Microcontroller Data Sheet, Rev. 4 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview 1.4.6 Frequency-Modulated Phase-Locked Loop (FMPLL) Two FMPLLs are available on each device. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and output clock divider ratio are software configurable. The FMPLLs have the following major features: • Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator) • Voltage controlled oscillator (VCO) range: 256–512 MHz • Frequency modulation via software control to reduce and control emission peaks — Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register — Modulation frequency: triangular modulation with 25 kHz nominal rate • Option to switch modulation on and off via software interface • Reduced frequency divider (RFD) for reduced frequency operation without re-lock • 2 modes of operation — Normal PLL mode with crystal reference (default) — Normal PLL mode with external reference • Lock monitor circuitry with lock status • Loss-of-lock detection for reference and feedback clocks • Self-clocked mode (SCM) operation • Auxiliary FMPLL — Used for FlexRay due to precise symbol rate requirement by the protocol — Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers as well as jitter-free control — Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop — Allows running motor control periphery at different (precisely lower, equal, or higher ,as required) frequency than the system to ensure higher resolution 1.4.7 • • External Bus Interface (EBI) Available on 473-pin devices Data and address options: — 16-bit data and address (non-muxed) — 32-bit data and address (bus-muxed) MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable to 26-bit address bus. Memory controller with support for various memory types — Non-burst and burst mode SDR flash and SRAM — Asynchronous/legacy flash and SRAM MPC5675K Microcontroller Data Sheet, Rev. 4 • • Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Overview • • • • • Configurable bus speed modes Support for 2 MB address space Chip select and write/byte enable options as presented in the pin-muxing table in Section 2, Package pinouts and signal descriptions Configurable wait states (via chip selects) Optional automatic CLKOUT gating to save power and reduce EMI 1.4.8 • • • • • • • On-chip flash memory Up to 2 MB Code flash memory with ECC 64 KB Data flash memory with ECC Censorship protection scheme to prevent flash content visibility Multiple block sizes to support features such as boot block, operating system block, and EEPROM emulation Read-while-write with multiple partitions Parallel programming mode to support rapid end of line programming Hardware programming state machine 1.4.9 • • • Cache memory Harvard architecture cache 16 KB instruction / 16 KB data Four-way set-associative Harvard (instruction and data) 256-bit long cache — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data parity 1.4.10 • • On-chip internal static RAM (SRAM) Up to 512 KB general-purpose SRAM ECC performs single-bit correction, double-bit error detection — Address included in ECC checkbase 1.4.11 DRAM controller The DRAM controller (available only on 473-pin devices) is a multi-port controller that monitors incoming requests on the three AHB slave ports and decides (at each rising clock edge) what command needs to be sent to the external DRAM. The DRAM controller on this device supports the following types of memories: • Mobile DDR (mDDR) MPC5675K Microcontroller Data Sheet, Rev. 4 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview • • • DDR 1 DDR 2 (optional) SDR The controller has the following features: • Optimized timing for 32-byte bursts and single read accesses on the AHB interface • Optimized timing for 8-byte and 16-byte bursts on the DRAMC interface • Supports priority elevation on the slave ports for single accesses • 16-bit wide DRAM interface • One chip select (CS) • mDDR memory controller — 16-bit external interface — Address range up to 8 MB 1.4.12 • • • • Boot Assist Module (BAM) Enables booting via serial mode (FlexCAN, LINFlex) Handles static mode in case of an erroneous boot procedure Implemented in 8 KB ROM Supports Lock Step Mode (LSM) and Decoupled Parallel Mode (DPM) 1.4.13 • • • • • • • • Parallel Data Interface (PDI) Support for external ADC and CMOS image sensors Parallel interface operation up to MCU system bus frequency Selectable data capture from rising or falling edge Receive FIFO with adjustable trigger thresholds Data width for 8, 10, 12, 14, and 16 bits Data Packing Unit to pack input data on 64-bit words — data packed on 8- or 16- bit boundary, depending on input data width Binary increasing channel select that allows as many as eight channels to be selected Frame synchronization through Vsync, Hsync, PIXCLK 1.4.14 • Deserial Serial Peripheral Interface (DSPI) modules Three Serial Peripheral Interfaces — Full duplex communication ports with interrupt and eDMA request support — Support for all functional modes from QSPI submodule of QSMCM (MPC5xx family) — Support for queues in RAM — Six chip selects, expandable to 64 with external demultiplexers — Programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 Overview • — Modified SPI mode for interfacing to peripherals with longer setup time requirements Support for up to 60 Mbit/s in Slave Only Rx mode 1.4.15 Serial communication interface module (LINFlex) The LINFlex on this device features the following: • Supports LIN Master mode, LIN Slave mode, and UART mode • LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications • Manages LIN frame transmission and reception without CPU intervention • LIN features — Autonomous LIN frame handling — Message buffer to store as many as 8 data bytes — Supports messages as long as 64 bytes — Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and time-out errors) — Classic or extended checksum calculation — Configurable break duration of up to 36-bit times — Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) — Diagnostic features (Loop back, LIN bus stuck dominant detection) — Interrupt-driven operation with 16 interrupt sources • LIN slave mode features — Autonomous LIN header handling — Autonomous LIN response handling • UART mode — Full-duplex operation — Standard non return-to-zero (NRZ) mark/space format — Data buffers with 4-byte receive, 4-byte transmit — Configurable word length (8-bit, 9-bit, or 16-bit words) — Configurable parity scheme: none, odd, even, always 0 — Speed as fast as 2 Mbit/s — Error detection and flagging (parity, noise, and framing errors) — Interrupt-driven operation with four interrupt sources — Separate transmitter and receiver CPU interrupt sources — 16-bit programmable baud-rate modulus counter and 16-bit fractional — Two receiver wake-up methods • Support for DMA-enabled transfers MPC5675K Microcontroller Data Sheet, Rev. 4 12 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview 1.4.16 • • • • • • • • • • • FlexCAN Thirty-two message buffers each Full implementation of the CAN protocol specification, Version 2.0B Programmable acceptance filters Individual Rx filtering per message buffer Short latency time for high priority transmit messages Arbitration scheme according to message ID or message buffer number Listen-only mode capabilities Programmable clock source: system clock or oscillator clock Reception queue possible by setting more than one Rx message buffer with the same ID Backwards compatible with previous FlexCAN modules Safety CAN features on 1 CAN module as implemented on MPC5604P 1.4.17 • • • • • • • Dual-channel FlexRay controller Full implementation of FlexRay Protocol Specification 2.1 Sixty-four configurable message buffers can be handled Message buffers configurable as Tx, Rx, or RxFIFO Message buffer size configurable Message filtering for all message buffers based on FrameID, cycle count, and message ID Programmable acceptance filters for RxFIFO message buffers Dual channel, each at up to 10 Mbit/s data rate 1.4.18 Periodic Interrupt Timer (PIT) The PIT module implements the features below: • Four general-purpose interrupt timers • 32-bit counter resolution • Clocked by system clock frequency • 32-bit counter for real time interrupt, clocked from main external oscillator • Can be used for software tick or DMA trigger operation 1.4.19 System Timer Module (STM) The STM implements the features below: • Duplicated periphery to guarantee that safety targets (SIL3) are achieved • Up-counter with four output compare registers • OS task protection and hardware tick implementation as per current state-of-the-art AUTOSAR requirement MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Overview 1.4.20 Motor control (MOTC) peripherals The peripherals in this section can be used for general-purpose applications, but are specifically designed for motor control (MOTC) applications. 1.4.20.1 FlexPWM The pulse width modulator module (FlexPWM) contains three PWM channels, each of which is configured to control a single half-bridge power stage. There may also be one or more fault channels. This PWM is capable of controlling most motor types: AC induction motors (ACIM), Permanent Magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors. A FlexPWM module implements the following features: • 16 bits of resolution for center, edge aligned, and asymmetrical PWMs • Maximum operating frequency lower than or equal to platform frequency • Clock source not modulated and independent from system clock (generated via auxiliary PLL) • Fine granularity control for enhanced resolution of the PWM period • PWM outputs can operate as complementary pairs or independent channels • Ability to accept signed numbers for PWM generation • Independent control of both edges of each PWM output • Synchronization to external hardware or other PWM is supported • Double-buffered PWM registers — Integral reload rates from 1 to 16 — Half-cycle reload capability • Multiple ADC trigger events can be generated per PWM cycle via hardware • Fault inputs can be assigned to control multiple PWM outputs • Programmable filters for fault inputs • Independently programmable PWM output polarity • Independent top and bottom deadtime insertion • Each complementary pair can operate with its own PWM frequency and deadtime values • Individual software control for each PWM output • All outputs can be forced to a value simultaneously • PWMX pin can optionally output a third signal from each channel • Channels not used for PWM generation can be used for buffered output compare functions • Channels not used for PWM generation can be used for input capture functions • Enhanced dual-edge capture functionality • Option to supply the source for each complementary PWM signal pair from any of the following: — External digital pin — Internal timer channel MPC5675K Microcontroller Data Sheet, Rev. 4 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview • — External ADC input, taking into account values set in ADC high and low limit registers DMA support 1.4.20.2 Cross Triggering Unit (CTU) The CTU provides automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration. The CTU implements the following features: • Cross triggering between ADC, FlexPWM, eTimer, and external pins • Double-buffered trigger generation unit with as many as eight independent triggers generated from external triggers • Maximum operating frequency lower than or equal to platform • Trigger generation unit configurable in sequential mode or in triggered mode • Trigger delay unit to compensate the delay of external low-pass filter • Double-buffered global trigger unit allowing eTimer synchronization and/or ADC command generation • Double-buffered ADC command list pointers to minimize ADC-trigger unit update • Double-buffered ADC conversion command list with as many as twenty-four ADC commands • Each trigger has the capability to generate consecutive commands • ADC conversion command allows controlling ADC channel from each ADC, single or synchronous sampling, independent result queue selection • DMA support with safety features 1.4.20.3 • • • • • • Analog-to-Digital Converter (ADC) Four independent ADCs with 12-bit A/D resolution Common mode conversion range of 0–5 V or 0–3.3 V Twenty-two single-ended input channels Supports eight FIFO queues with fixed priority Queue modes with priority-based preemption; initiated by software command, internal, or external triggers DMA and interrupt request support 1.4.20.4 eTimer module Three 16-bit general purpose up/down timer/counters per module are implemented with the following features: • Ability to operate up to platform frequency • Individual channel capability — Input capture trigger — Output compare MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Overview • • • • • • • • • — Double buffer (to capture rising edge and falling edge) — Separate prescaler for each counter — Selectable clock source — 0–100% pulse measurement — Rotation direction flag (Quad decoder mode) Maximum count rate — Equals peripheral clock/2 for external event counting — Equals peripheral clock for internal clock counting Cascadeable counters Programmable count modulo Quadrature decode capabilities Counters can share available input pins Count once or repeatedly Preloadable counters Pins available as GPIO when timer functionality not in use DMA support 1.4.21 Redundancy Control and Checker Unit (RCCU) The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features: • Duplicated module to guarantee highest possible diagnostic coverage (check of checker) • Replicated IP to be used as checkers on the PBRIDGE output, flash controller output, SRAM Output, DMA Channel Mux inputs 1.4.22 Software Watchdog Timer (SWT) This module implements the features below: • Duplicated periphery to guarantee that safety targets (SIL3) are achieved • Fault-tolerant output • Safe internal RC oscillator as reference clock • Windowed watchdog • Program flow control monitor with 16-bit pseudorandom key generation • Allows high level of safety (SIL3 monitor) 1.4.23 Fault Collection and Control Unit (FCCU) The FCCU module has the following features: • Redundant collection of hardware checker results • Redundant collection of error information and latch of faults from critical modules on the device MPC5675K Microcontroller Data Sheet, Rev. 4 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview • • Collection of test results Configurable and graded fault control — Internal reactions (no internal reaction, NMI, reset, or safe mode) — External reaction (failure is reported to the outside world via configurable output pins) 1.4.24 System Integration Unit Lite (SIUL) The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIUL provides the following features: • Centralized pad control on per-pin basis — Pin function selection — Configurable weak pullup/pulldown — Configurable slew rate control (slow/medium/fast) — Hysteresis on GPIO pins — Configurable automatic safe mode pad control • Input filtering for external interrupts 1.4.25 Cyclic Redundancy Checker (CRC) unit The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to an input register. The CRC unit has the following features: • Three sets of registers to allow three concurrent contexts with possibly different CRC computations, each with a selectable polynomial and seed • Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores the result in an internal register • Implements the following standard CRC polynomials: — x16 + x12 + x5 + 1 [16-bit CRC-CCITT] — x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 [32-bit CRC-ethernet(32)] • Key engine to be coupled with communication periphery where CRC application is added to allow implementation of safe communication protocol • Offloads the core from cycle-consuming CRC and helps in checking the configuration signature for safe start-up or periodic procedures • Connected as a peripheral on the internal peripheral bus • Provides DMA support MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 Overview 1.4.26 Non-maskable interrupt (NMI) The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions. 1.4.27 System Status and Configuration Module (SSCM) The SSCM on the MPC5675K features the following: • System configuration and status • Debug port status and debug port enable • Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word • Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code (default) or as Freescale VLE code out of flash • Supports serial bootloading of either Classic PowerPC Book E code (default) or Freescale VLE code • Detection of user boot code • Automatic switch to serial boot mode if internal flash is blank or invalid 1.4.28 • • • • • • • • Nexus Development Interface (NDI) Per IEEE-ISTO 5001-2008 Real-time development support for Power Architecture core through Nexus class 3 (some class 4 support) Nexus support to snoop system SRAM traffic Data trace of FlexRay accesses Read and write access Configured via the IEEE 1149.1 (JTAG) port High bandwidth mode for fast message transmission Reduced bandwidth mode for reduced pin usage 1.4.29 • • • • • IEEE 1149.1 JTAG controller (JTAGC) • IEEE 1149.1-2001 Test Access Port (TAP) interface JCOMP input that provides the ability to share the TAP —selectable modes of operation include JTAGC/debug or normal system operation 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions 5-bit instruction register that supports additional public instructions Three test data registers: — Bypass register — Boundary scan register — Device identification register TAP controller state machine that controls the operation of the data registers, instruction register, and associated circuitry MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor 18 Package pinouts and signal descriptions 2 2.1 Package pinouts and signal descriptions Package pinouts Figure 2 shows the MPC5675K in the 257 MAPBGA package. Figure 3 through Figure 6 show the MPC5675K in the 473 MAPBGA package. 1 A VSS_ HV_IO VSS_ HV_IO VDD_ HV_IO nexus MDO [2] nexus MDO [0] nexus MDO[6] nexus MDO [4] nexus MDO [10] nexus MCKO 2 VSS_ HV_IO VSS_ HV_IO nexus MDO [15] nexus MDO [3] nexus MDO [1] nexus MDO [11] VDD_ HV_IO VSS_ HV_IO nexus MDO[8] 3 VDD_ HV_IO mc_cgl clk_out VSS_ HV_IO can1 RXD flexray CA_RX dspi1 SOUT dspi0 SCK dspi0 CS0 dspi2 CS0 nexus RDY_B dspi2 SCK dspi1 CS2 dspi0 CS3 dspi0 CS2 4 5 6 nexus nexus nexus MDO[5] MDO[7] MDO[9] can1 TXD FCCU_ F[1] dspi0 SOUT NMI dspi1 SIN dspi1 SCK dspi1 CS0 dspi2 CS2 dspi0 SIN nexus MDO [13] nexus MDO [12] VSS_ LV_PLL VDD_ LV_PLL dspi1 CS3 adc3 AN[0] adc3 AN[1] etimer1 ETC[1] adc2 AN[0] adc3 AN[3] adc3 AN[2] etimer1 ETC[2] adc2 AN[3] adc2 AN[2] adc2 AN[1] VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR nexus MDO [14] flexray CB_RX dspi2 CS1 etimer0 ETC[0] 7 8 flexray flexray CA_TR_ CB_TX EN flexray flexray CB_TR_ CA_TX EN etimer0 ETC[1] etimer0 ETC[2] 9 VDD_ HV_IO VSS_ HV_IO etimer0 ETC[3] 10 fec RXD[2] fec RXD[3] JCOMP 11 fec RX_ CLK fec RX_ER fec CRS fec TXD[1] 12 fec RXD[0] fec RXD[1] fec TXD[0] fec RX_DV 13 fec MDIO fec TX_ER fec COL fec MDC 14 fec TX_EN fec TX_ CLK can0 RXD VDD_ HV_PDI pdi LINE_V 15 fec TXD[3] can0 TXD VSS_ HV_PDI VSS_ HV_IO pdi DATA [2] pdi DATA [6] pdi DATA [10] pdi DATA [13] pdi DATA [15] 16 VSS_ HV_IO VDD_ HV_IO pdi DATA [5] pdi DATA [0] pdi DATA [3] pdi DATA [7] pdi DATA [11] VDD_ HV_ PDI VSS_ HV_ PDI 17 VSS_ A HV_IO VSS_ B HV_IO B C C pdi CLOCK pdi DATA [1] pdi DATA [4] pdi DATA [8] D RESERV etimer0 ED ETC[5] etimer0 VDD_ VSS_ fec ETC[4] HV_FLA HV_FLA TXD[2] D E E F VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR mc_cgl clk_out pdi DATA [9] pdi DATA [12] pdi DATA [14] F G pdi G FRAME_ V flexpwm H 0 X[0] flexpwm J 0 X[1] H J K nexus nexus MSEO_ MSEO_ B[0] B[1] nexus nexus EVTO_B EVTI_B VDD_ HV_IO VSS_ HV_IO RESET flexpwm flexpwm flexpwm flexpwm K 0 0 0 0 X[2] X[3] A[1] B[0] VDD_HV _DRAM_ VREF flexpwm 0 B[2] TCK flexpwm 0 B[1] TMS TDO L L M VDD_ HV_ OSC N XTALIN VSS_ HV_ OSC XTAL OUT VSS_ HV_IO VSS_ HV_IO TDI flexpwm M 1 A[1] flexpwm flexpwm flexpwm flexpwm N 0 0 1 1 B[3] A[2] A[0] B[0] adc0 AN[0] VDD_ HV_ ADR_13 VSS_ HV_ ADR_13 adc2_ adc3 AN[11] etimer1 ETC[3] VSS_ HV_IO VDD_ HV_IO adc0 AN[2] adc0 AN[1] VSS_ HV_ ADV adc0_ adc1 AN[14] adc0_ adc1 AN[13] adc0_ adc1 AN[12] adc0_ adc1 AN[11] etimer1 ETC[4] adc1 AN[1] adc1 AN[0] etimer1 ETC[5] VREG_C TRL adc1 AN[2] VDD_ HV_IO lin0 TXD lin0 RXD flexpwm flexpwm flexpwm P 0 0 1 A[3] A[0] B[1] VSS_ HV_IO etimer1 ETC[0] VSS_ HV_ PMU flexpwm flexpwm R 1 1 A[2] B[2] VDD_ HV_IO VSS_ HV_IO VSS_ T HV_IO VSS_ U HV_IO P R FCCU_ VSS_HV F[0] _IO VDD_ HV_IO VSS_ HV_IO dspi2 SOUT dspi2 SIN adc2_ VDD_ adc3 HV_ AN[14] ADR_02 adc2_ VSS_ adc3 HV_ AN[13] ADR_02 adc2_ adc3 AN[12] VDD_ HV_ ADV T U VREG_ RESET_ VDD_HV INT_EN SUP _PMU ABLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 2. MPC5675K 257 MAPBGA pinout (top view) MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 Package pinouts and signal descriptions 1 A 2 3 4 5 6 7 8 9 10 11 12 VSS_ HV_IO VSS_ HV_IO VDD_ HV_IO nexus MDO[1] nexus MDO[0] nexus MDO[10] nexus MCKO nexus EVTO_B nexus RDY_B dspi0 SCK dspi0 CS0 flexpwm0 X[0] VSS_ HV_IO VSS_ HV_IO nexus MDO[15] nexus MDO[3] nexus MDO[2] nexus MDO[11] VDD_ HV_IO VSS_ HV_IO nexus MDO[13] dspi1 CS0 dspi2 CS2 VDD_ HV_IO VDD_ HV_IO mc_cgl clk_out VSS_ HV_IO can1 RXD flexray CA_RX nexus MDO[6] nexus MDO[8] nexus MSEO_B[0] nexus MDO[12] dspi1 SCK dspi2 CS0 dspi0 SIN nexus MDO[5] can1 TXD FCCU_ F[1] dspi0 SOUT NMI nexus MDO[4] nexus MSEO_B[1] nexus EVTI_B dspi1 SIN dspi1 SOUT VSS_ HV_IO VDD_ HV_IO nexus MDO[7] nexus MDO[14] flexray CB_RX RESERVED nexus MDO[9] dspi2 CS1 etimer0 ETC[4] etimer0 ETC[5] flexray CB_TX flexray CB_TR_EN etimer0 ETC[1] etimer0 ETC[0] flexray CA_TR_EN flexray CA_TX etimer0 ETC[2] VDD_ HV_IO fec RX_DV fec RXD[3] etimer0 ETC[3] VSS_ HV_IO fec MDIO fec RX_ER fec TXD[2] JCOMP fec TX_CLK fec TXD[0] fec TXD[1] VSS_ HV_IO fec TX_EN fec RXD[0] fec CRS VSS_ HV_FLA B C D E F VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR G H J K L M Figure 3. MPC5675K 473 MAPBGA pinout (northwest, viewed from above) N P R T U V W Y AA AB AC flexpwm0 A[0] flexpwm0 B[0] flexpwm0 X[2] flexpwm0 B[3] flexpwm1 B[0] VDD_ HV_OSC XTALIN VSS_ HV_OSC XTALOUT VSS_ HV_IO VSS_ HV_IO 1 VSS_ HV_IO flexpwm0 B[1] flexpwm0 X[3] flexpwm1 A[0] flexpwm1 B[1] VDD_ HV_IO VSS_ HV_IO RESET FCCU_ F[0] VDD_ HV_IO VSS_ HV_IO 2 flexpwm0 X[1] flexpwm0 A[2] flexpwm0 A[1] flexpwm1 A[1] flexpwm1 A[2] flexpwm1 B[2] dspi0 CS3 dspi0 CS2 VSS_ HV_IO dspi2 SOUT dspi2 SIN 3 flexpwm0 B[2] flexpwm0 A[3] VSS_ HV_IO VDD_ HV_IO dspi2 SCK dspi1 CS2 VSS_ LV_PLL VDD_ LV_PLL dspi1 CS3 flexpwm1 X[2] flexpwm1 A[3] 4 VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR flexpwm1 X[0] flexpwm1 X[1] flexpwm1 X[3] flexpwm1 B[3] 5 adc3 AN[0] adc3 AN[1] adc3 AN[2] adc3 AN[3] 6 adc2_adc3 AN[11] adc2_adc3 AN[12] adc2_adc3 AN[13] VDD_HV_ ADR_23 7 adc2_adc3 AN[14] adc2 AN[0] adc2 AN[1] VSS_HV_ ADR_23 8 etimer1 ETC[1] VDD_ HV_ADV adc2 AN[2] adc2 AN[3] 9 etimer1 ETC[2] VSS_ HV_ADV adc0 AN[0] adc0 AN[1] 10 etimer1 ETC[3] adc0 AN[2] adc0 AN[4] adc0 AN[3] 11 VSS_ HV_IO adc0 AN[5] adc0 AN[6] VDD_ HV_ADR_0 12 Figure 4. MPC5675K 473 MAPBGA pinout (southwest, viewed from above) MPC5675K Microcontroller Data Sheet, Rev. 4 20 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions 13 14 15 16 17 18 19 20 21 22 23 fec TXD[3] fec TX_ER fec RX_CLK VDD_ HV_FLA VDD_ HV_IO VSS_ HV_IO fec RXD[1] fec RXD[2] pdi DATA[3] pdi DATA[6] fec COL fec MDC pdi DATA[1] pdi DATA[4] pdi DATA[5] VDD_ HV_PDI pdi CLOCK pdi DATA[0] pdi DATA[2] VSS_ HV_PDI pdi DATA[7] pdi LINE_V pdi DATA[8] pdi DATA[11] pdi DATA[10] pdi DATA[9] pdi DATA[12] pdi FRAME_V pdi DATA[13] pdi DATA[14] can0 RXD VDD_ HV_PDI mc_cgl clk_out pdi DATA[15] can0 TXD VSS_ HV_PDI dramc BA[1] siul GPIO[149] siul GPIO[194] dramc DQS[0] VDD_HV_ DRAM_VTT dramc D[1] dramc D[4] VDD_HV_ DRAM_VTT dramc WEB VSS_ HV_IO VDD_ HV_IO siul GPIO[197] siul GPIO[195] dramc CS0 siul GPIO[148] dramc DM[0] VDD_HV_ DRAM dramc D[3] dramc D[8] VSS_HV_ DRAM dramc D[11] VSS_ HV_IO VSS_ HV_IO dramc CAS dramc BA[0] dramc BA[2] dramc D[5] dramc D[7] VSS_HV_ DRAM dramc D[6] dramc D[9] VDD_HV_ DRAM dramc D[10] A B C D E F G H J K L M VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR dramc RAS siul GPIO[196] dramc D[2] dramc D[0] VSS_ HV_IO VDD_ HV_IO dramc ODT Figure 5. MPC5675K 473 MAPBGA pinout (northeast, viewed from above) VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR dramc DQS[1] dramc D[14] VDD_HV_ DRAM_VREF dramc ADD[8] dramc ADD[6] lin0 TXD lin0 RXD VDD_ HV_IO adc0 AN[8] adc0 AN[7] VSS_ HV_ADR_0 13 dramc DM[1] dramc D[15] dramc ADD[3] dramc ADD[9] dramc ADD[12] dramc ADD[13] dramc ADD[14] dramc ADD[15] VSS_HV_IO lin1 RXD VREG_INT_ ENABLE 21 dramc D[13] VSS_HV_ DRAM dramc CKE dramc ADD[1] VDD_HV_ DRAM VSS_HV_ DRAM dramc ADD[7] dramc ADD[11] lin1 TXD VDD_ HV_IO VSS_ HV_IO 22 dramc D[12] VDD_HV_ DRAM dramc CLKB dramc CLK dramc ADD[0] dramc ADD[2] dramc ADD[4] dramc ADD[5] dramc ADD[10] VSS_ HV_IO VSS_ HV_IO 23 N P R T U V W Y AA AB AC adc0_adc1 AN[11] adc0_adc1 AN[12] adc0_adc1 AN[13] adc0_adc1 AN[14] 14 etimer1 ETC[5] adc1 AN[0] adc1 AN[1] VDD_ HV_ADR_1 15 etimer1 ETC[4] adc1 AN[2] adc1 AN[3] VSS_ HV_ADR_1 16 adc1 AN[8] adc1 AN[5] adc1 AN[4] VDD_ HV_PMU 17 adc1 AN[6] adc1 AN[7] TDO VREG_CTRL 18 TCK TDI TMS VSS_ HV_PMU 19 VDD_HV_IO etimer1 ETC[0] RESERVED RESET_ SUP 20 Figure 6. MPC5675K 473 MAPBGA pinout (southeast, viewed from above) MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 21 Package pinouts and signal descriptions 2.2 Pin descriptions The following sections provide signal descriptions and related information about the functionality and configuration for this device. 2.2.1 Pad types Table 2. Pad types Pad Type GP Slow GP Slow/Fast GP Slow/Medium Description Slow buffer with CMOS Schmitt trigger and pullup/pulldown. Programmable slow/fast buffer with CMOS Schmitt trigger, pullup/pulldown. Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown. Programmable slow/medium buffer with CMOS Schmitt trigger, pullup/pulldown and Injection proof analog switch. Table 2 lists the pad types used on the MPC5675K. GP Slow/Symmetric Programmable slow/symmetric buffer with CMOS Schmitt trigger, pullup/pulldown. PDI Medium PDI Fast DRAM ACC DRAM CLK DRAM DQ Medium slew-rate output with four selectable slew rates. Contains an input buffer and weak pullup/pulldown. Fast slew-rate output with four selectable slew rates. Contains an input buffer and weak pullup/pulldown. Bidirectional DDR pad. Can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR. Differential clock driver Bidirectional DDR pad with integrated ODT. Can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full strength, and SDR. Enable On Die Termination control CMOS Schmitt trigger cell with injection proof analog switch. CMOS Schmitt trigger cell with two injection-proof analog switches. DRAM ODT CTL Analog Analog Shared MPC5675K Microcontroller Data Sheet, Rev. 4 22 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions 2.2.2 Power supply and reference voltage pins Table 3 shows the supply pins for the MPC5675K in the 257 MAPBGA package. Table 5 shows the supply pins for the MPC5675K in the 473 MAPBGA package. Table 4 and Table 6 show the pins not populated on the MPC5675K 257 MAPBGA and 473 MAPBGA packages, respectively. Table 3. 257 MAPBGA supply pins Ball Number Ball Name Pad Type Ball Number VDD A3 A9 B16 C1 G2 M2 P10 P14 T2 T16 L14 D8 M1 D14 H16 U14 R7 R9 U9 F6 F7 F8 VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_DRAM_VREF VDD_HV_FLA VDD_HV_OSC VDD_HV_PDI VDD_HV_PDI VDD_HV_PMU VDD_HV_ADR_13 VDD_HV_ADR_02 VDD_HV_ADV VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV_A VDD_HV_A VDD_HV_A VDD_LV VDD_LV VDD_LV VSS A1 A2 A16 A17 VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV VSS_HV VSS_HV VSS_HV G7 G8 G9 G10 VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV VSS_LV VSS_LV VSS_LV F9 F10 F11 F12 G6 G12 H6 H12 J6 J12 K6 K12 L6 L12 M6 M7 M8 M9 M10 M11 M12 P4 VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_PLL VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV Ball Name Pad Type MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 23 Package pinouts and signal descriptions Ball Number B1 B2 B9 B17 C3 D15 H2 N2 P9 R3 R15 T1 T17 U1 U2 U16 U17 D9 P1 C15 J16 T9 T7 U10 Table 3. 257 MAPBGA supply pins (continued) Pad Type VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV_A VSS_HV_A VSS_HV_A Ball Number G11 H7 H8 H9 H10 H11 J7 J8 J9 J10 J11 K7 K8 K9 K10 K11 L7 L8 L9 L10 L11 N4 U15 Ball Name VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_PLL VSS_HV_PMU Pad Type VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV Ball Name VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_FLA VSS_HV_OSC VSS_HV_PDI VSS_HV_PDI VSS_HV_ADR_02 VSS_HV_ADR_13 VSS_HV_ADV Table 4. 257 MAPBGA Balls not populated on package E5 E13 J13 N6 E6 F5 K5 N7 E7 F13 K13 N8 E8 G5 L5 N9 E9 G13 L13 N10 E10 H5 M5 N11 E11 H13 M13 N12 E12 J5 N5 N13 MPC5675K Microcontroller Data Sheet, Rev. 4 24 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins Ball Number Ball Name Pad Type Ball Number VDD A3 A14 B22 C1 D8 G2 L20 M2 M4 T4 V2 Y13 Y20 AB2 AB22 AC12 AC15 AC7 AA9 H22 L23 P23 U22 R20 H21 L21 D13 V1 D16 D20 AC17 F6 F7 VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_ADR_0 VDD_HV_ADR_1 VDD_HV_ADR_23 VDD_HV_ADV VDD_HV_DRAM VDD_HV_DRAM VDD_HV_DRAM VDD_HV_DRAM VDD_HV_DRAM_VREF VDD_HV_DRAM_VTT VDD_HV_DRAM_VTT VDD_HV_FLA VDD_HV_OSC VDD_HV_PDI VDD_HV_PDI VDD_HV_PMU VDD_LV_COR VDD_LV_COR VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_HV VDD_LV VDD_LV F15 F16 F17 F18 G6 G18 H6 H18 J6 J18 K6 K18 L6 L18 M6 M18 N6 N18 P6 P18 R6 R18 T6 T18 U6 U18 V6 V7 V8 V9 V10 V11 V12 VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV Ball Name Pad Type MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 25 Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins (continued) Ball Number F8 F9 F10 F11 F12 F13 F14 Ball Name VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR Pad Type VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VSS A2 A22 A23 B1 B2 B14 B23 C3 D9 D11 H2 K20 L4 N2 A1 R4 W2 Y12 AA3 AA21 AB1 AB23 AC1 AC2 AC22 AC23 VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV_IO VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 N7 N8 N9 N10 VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV Ball Number V13 V14 V15 V16 V17 V18 Y4 Ball Name VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_COR VDD_LV_PLL Pad Type VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV MPC5675K Microcontroller Data Sheet, Rev. 4 26 Preliminary—Subject to Change Without Notice Freescale Semiconductor Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins (continued) Ball Number AC13 AC16 AC8 AA10 H23 L22 P22 V22 D12 Y1 C21 D17 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 Ball Name VSS_HV_ADR_0 VSS_HV_ADR_1 VSS_HV_ADR_23 VSS_HV_ADV VSS_HV_DRAM VSS_HV_DRAM VSS_HV_DRAM VSS_HV_DRAM VSS_HV_FLA VSS_HV_OSC VSS_HV_PDI VSS_HV_PDI VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR Pad Type VSS_HV_A VSS_HV_A VSS_HV_A VSS_HV_A VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV Ball Number N11 N12 N13 N14 N15 N16 N17 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T7 T8 T9 T10 T11 Ball Name VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR Pad Type VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 27 Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins (continued) Ball Number J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 Ball Name VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR Pad Type VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV Ball Number T12 T13 T14 T15 T16 T17 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 W4 AC19 D5 AB20 Ball Name VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_COR VSS_LV_PLL VSS_HV_PMU RESERVED RESERVED Pad Type VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_LV VSS_HV VSS_HV Table 6. 473 MAPBGA Balls not populated on package E5 E13 F19 K19 P19 V19 W12 E6 E14 G5 L5 R5 W5 W13 E7 E15 G19 L19 R19 W6 W14 E8 E16 H5 M5 T5 W7 W15 E9 E17 H19 M19 T19 W8 W16 E10 E18 J5 N5 U5 W9 W17 E11 E19 J19 N19 U19 W10 W18 E12 F5 K5 P5 V5 W11 W19 MPC5675K Microcontroller Data Sheet, Rev. 4 28 Preliminary—Subject to Change Without Notice Freescale Semiconductor 2.2.3 System pins Package pinouts and signal descriptions Table 7 shows the system pins for the MPC5675K in the 257 MAPBGA package. Table 8 shows the system pins for the MPC5675K in the 473 MAPBGA package. Table 7. 257 MAPBGA system pins Ball Number C4 C10 E1 E4 L15 M16 N1 P2 R1 R2 R13 U12 U13 Ball Name FCCU_F[1] JCOMP Nexus MDO[0] NMI TCK TMS XTALIN RESET XTALOUT FCCU_F[0] VREG_CTRL VREG_INT_ENABLE RESET_SUP 1 Weak pull Safe Mode during reset default condition disabled pull down — pull up pull up pull up — pull down — disabled — — pull down not available not available not available not available not available not available not available not available not available not available — — — Pad Type GP Slow/Medium GP Slow GP Slow/Fast GP Slow GP Slow GP Slow Analog Feedthrough Reset Analog Feedthrough GP Slow/Medium Analog Feedthrough Analog Feedthrough Analog Feedthrough Power Domain VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_REG VDD_HV_IO VDD_HV_IO NOTES: 1 Do not connect pin directly to a power supply or ground. Table 8. 473 MAPBGA system pins Ball Number C4 D10 E1 E4 R23 T23 W1 Y2 Y19 AA1 AA2 AB19 AC18 AC20 AC21 Ball Name FCCU_F[1] JCOMP Nexus NMI dramc CLKB dramc CLK XTALIN RESET TCK XTALOUT FCCU_F[0] TMS VREG_CTRL RESET_SUP VREG_INT_ENABLE MDO[0]1 Weak pull Safe Mode during reset default condition disabled pull down — pull up — disabled — pull down pull up — disabled pull up — pull down — not available not available not available not available — — not available not available not available not available not available not available — — — Pad Type GP Slow/Medium GP Slow GP Slow/Fast GP Slow DRAM CLK DRAM CLK Analog Feedthrough Reset GP Slow Analog Feedthrough GP Slow/Medium GP Slow Analog Feedthrough Analog Feedthrough Analog Feedthrough Power Domain VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_DRAM VDD_HV_DRAM VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_HV_IO VDD_REG VDD_HV_IO VDD_HV_IO NOTES: 1 Do not connect pin directly to a power supply or ground. MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 29 Package pinouts and signal descriptions 30 2.2.4 Multiplexed pins Table 9shows the pin multiplexing for the MPC5675K in the 257 MAPBGA package. Table 10 shows the pin multiplexing for the MPC5675K in the 473 MAPBGA package. Table 9. 257 MAPBGA pin multiplexing Ball Ball Number Type A4 Preliminary—Subject to Change Without Notice Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Ball Name Alternate I/O A0: siul_GPIO[114] A1: _ A2: npc_wrapper_MDO[5] A3: _ A0: siul_GPIO[112] A1: _ A2: npc_wrapper_MDO[7] A3: _ A0: siul_GPIO[110] A1: _ A2: npc_wrapper_MDO[9] A3: _ A0: siul_GPIO[51] A1: flexray_CB_TX A2: _ A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: ctu0_EXT_IN I: flexpwm0_EXT_SYNC I: _ I: fec_RXD[2] I: _ I: siul_EIRQ[21] I: fec_RX_CLK I: _ I: siul_EIRQ[25] Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Fast Power Domain VDD_HV_IO GPIO nexus MDO[5]1 A5 GPIO nexus MDO[7]1 — disabled GP Slow/ Fast VDD_HV_IO A6 GPIO nexus MDO[9]1 — disabled GP Slow/ Fast VDD_HV_IO A7 GPIO flexray CB_TX — disabled GP Slow/ Symmetric VDD_HV_IO A8 GPIO flexray A0: siul_GPIO[47] CA_TR_EN A1: flexray_CA_TR_EN A2: _ A3: _ GPIO fec RXD[2] A0: siul_GPIO[213] A1: _ A2: _ A3: dspi2_SOUT A0: siul_GPIO[209] A1: flexray_DBG2 A2: etimer2_ETC[2] A3: dspi0_CS6 — disabled GP Slow/ Symmetric VDD_HV_IO A10 — disabled GP Slow/ Medium VDD_HV_IO A11 GPIO fec RX_CLK — disabled GP Slow/ Medium VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type A12 Ball Name Alternate I/O A0: siul_GPIO[211] A1: i2c1_clock A2: _ A3: _ A0: siul_GPIO[198] A1: fec_MDIO A2: _ A3: dspi2_CS0 A0: siul_GPIO[200] A1: fec_TX_EN A2: _ A3: lin0_TXD A0: siul_GPIO[204] A1: fec_TXD[3] A2: _ A3: dspi2_CS2 A0: siul_GPIO[22] A1: mc_cgl_clk_out A2: etimer2_ETC[5] A3: _ A0: siul_GPIO[14] A1: can1_TXD A2: _ A3: _ A0: siul_GPIO[219] A1: _ A2: npc_wrapper_MDO[14] A3: can3_TXD A0: siul_GPIO[9] A1: dspi2_CS1 A2: _ A3: _ Additional Inputs I: fec_RXD[0] I: _ I: siul_EIRQ[27] I: _ I: _ I: siul_EIRQ[28] I: _ I: _ I: _ I: flexpwm1_FAULT[2] I: _ I: siul_EIRQ[29] I: _ I: _ I: siul_EIRQ[18] I: _ I: _ I: siul_EIRQ[13] I: _ I: _ I: _ I: flexpwm0_FAULT[0] I: lin3_RXD I: can2_RXD I: _ I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 31 GPIO fec RXD[0] A13 GPIO fec MDIO — disabled GP Slow/ Medium VDD_HV_IO A14 GPIO fec TX_EN — disabled GP Slow/ Medium VDD_HV_IO A15 GPIO fec TXD[3] — disabled GP Slow/ Medium VDD_HV_IO B3 GPIO mc_cgl clk_out — disabled GP Slow/ Fast VDD_HV_IO B4 GPIO can1 TXD — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions B5 GPIO nexus MDO[14]1 — disabled GP Slow/ Fast VDD_HV_IO B6 GPIO dspi2 CS1 — disabled GP Slow/ Medium VDD_HV_IO B7 GPIO flexray A0: siul_GPIO[52] CB_TR_EN A1: flexray_CB_TR_EN A2: _ A3: _ — disabled GP Slow/ Symmetric VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type B8 Ball Name Alternate I/O A0: siul_GPIO[48] A1: flexray_CA_TX A2: _ A3: _ A0: siul_GPIO[214] A1: i2c1_data A2: _ A3: _ A0: siul_GPIO[215] A1: _ A2: _ A3: dspi0_CS1 A0: siul_GPIO[212] A1: dspi1_CS1 A2: etimer2_ETC[5] A3: _ A0: siul_GPIO[205] A1: fec_TX_ER A2: dspi2_CS3 A3: _ A0: siul_GPIO[207] A1: flexray_DBG0 A2: etimer2_ETC[4] A3: dspi0_CS4 A0: siul_GPIO[16] A1: can0_TXD A2: _ A3: sscm_DEBUG[0] A0: siul_GPIO[220] A1: _ A2: npc_wrapper_MDO[15] A3: _ A0: siul_GPIO[50] A1: _ A2: ctu1_EXT_TGR A3: _ Additional Inputs I: ctu1_EXT_IN I: _ I: _ I: fec_RXD[3] I: _ I: _ I: fec_RX_ER I: _ I: _ I: fec_RXD[1] I: _ I: _ I: flexpwm1_FAULT[3] I: lin0_RXD I: _ I: fec_TX_CLK I: _ I: _ I: _ I: _ I: siul_EIRQ[15] I: can3_RXD I: can2_RXD I: _ I: flexray_CB_RX I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Symmetric Power Domain VDD_HV_IO Package pinouts and signal descriptions 32 GPIO flexray CA_TX B10 GPIO fec RXD[3] Preliminary—Subject to Change Without Notice Freescale Semiconductor B11 GPIO fec RX_ER MPC5675K Microcontroller Data Sheet, Rev. 4 B12 GPIO fec RXD[1] B13 GPIO fec TX_ER B14 GPIO fec TX_CLK B15 GPIO can0 TXD C2 GPIO nexus MDO[15]1 C5 GPIO flexray CB_RX — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type C6 Ball Name Alternate I/O A0: siul_GPIO[0] A1: etimer0_ETC[0] A2: _ A3: _ A0: siul_GPIO[1] A1: etimer0_ETC[1] A2: _ A3: _ A0: siul_GPIO[2] A1: etimer0_ETC[2] A2: _ A3: _ A0: siul_GPIO[3] A1: etimer0_ETC[3] A2: _ A3: _ A0: siul_GPIO[208] A1: flexray_DBG1 A2: etimer2_ETC[3] A3: dspi0_CS5 A0: siul_GPIO[201] A1: fec_TXD[0] A2: etimer2_ETC[1] A3: _ A0: siul_GPIO[206] A1: fec_COL A2: _ A3: lin1_TXD A0: siul_GPIO[17] A1: _ A2: _ A3: sscm_DEBUG[1] A0: siul_GPIO[136] A1: flexpwm2_A[0] A2: _ A3: etimer1_ETC[0] Additional Inputs I: dspi2_SIN I: _ I: siul_EIRQ[0] I: _ I: _ I: siul_EIRQ[1] I: _ I: _ I: siul_EIRQ[2] I: _ I: mc_rgm_ABS[2] I: siul_EIRQ[3] I: fec_CRS I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can0_RXD I: can1_RXD I: siul_EIRQ[16] I: pdi_DATA[5] I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 33 GPIO etimer0 ETC[0] C7 GPIO etimer0 ETC[1] — disabled GP Slow/ Medium VDD_HV_IO C8 GPIO etimer0 ETC[2] — disabled GP Slow/ Medium VDD_HV_IO C9 GPIO etimer0 ETC[3] — pull down GP Slow/ Medium VDD_HV_IO C11 GPIO fec CRS — disabled GP Slow/ Medium VDD_HV_IO C12 GPIO fec TXD[0] — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions C13 GPIO fec COL — disabled GP Slow/ Medium VDD_HV_IO C14 GPIO can0 RXD — disabled GP Slow/ Medium VDD_HV_IO C16 GPIO pdi DATA[5] — disabled PDI Medium VDD_HV_PDI Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type C17 Ball Name Alternate I/O A0: siul_GPIO[128] A1: flexpwm2_B[1] A2: _ A3: etimer1_ETC[3] A0: siul_GPIO[85] A1: _ A2: npc_wrapper_MDO[2] A3: _ A0: siul_GPIO[84] A1: _ A2: npc_wrapper_MDO[3] A3: _ A0: siul_GPIO[15] A1: _ A2: _ A3: _ A0: siul_GPIO[38] A1: dspi0_SOUT A2: _ A3: sscm_DEBUG[6] A0: siul_GPIO[44] A1: etimer0_ETC[5] A2: _ A3: _ A0: siul_GPIO[43] A1: etimer0_ETC[4] A2: _ A3: _ A0: siul_GPIO[203] A1: fec_TXD[2] A2: _ A3: _ A0: siul_GPIO[202] A1: fec_TXD[1] A2: _ A3: dspi2_SCK Additional Inputs I: pdi_CLOCK I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can1_RXD I: can0_RXD I: siul_EIRQ[14] I: _ I: _ I: siul_EIRQ[24] I: _ I: _ I: _ I: _ I: mc_rgm_ABS[0] I: _ I: flexpwm1_FAULT[1] I: _ I: _ I: flexpwm1_FAULT[0] I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type PDI Medium Power Domain VDD_HV_PDI Package pinouts and signal descriptions 34 GPIO pdi CLOCK D1 GPIO nexus MDO[2]1 Preliminary—Subject to Change Without Notice Freescale Semiconductor D2 GPIO nexus MDO[3]1 MPC5675K Microcontroller Data Sheet, Rev. 4 D3 GPIO can1 RXD D4 GPIO dspi0 SOUT D6 GPIO etimer0 ETC[5] D7 GPIO etimer0 ETC[4] D10 GPIO fec TXD[2] D11 GPIO fec TXD[1] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — pull down GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type D12 Ball Name Alternate I/O A0: siul_GPIO[210] A1: flexray_DBG3 A2: etimer2_ETC[0] A3: dspi0_CS7 A0: siul_GPIO[199] A1: fec_MDC A2: _ A3: _ A0: siul_GPIO[131] A1: _ A2: lin3_TXD A3: _ A0: siul_GPIO[132] A1: flexpwm2_B[3] A2: _ A3: _ A0: siul_GPIO[86] A1: _ A2: npc_wrapper_MDO[1] A3: _ A0: siul_GPIO[49] A1: _ A2: ctu0_EXT_TGR A3: _ A0: siul_GPIO[129] A1: _ A2: lin2_TXD A3: _ A0: siul_GPIO[133] A1: flexpwm2_A[1] A2: _ A3: etimer1_ETC[2] A0: siul_GPIO[134] A1: flexpwm2_X[1] A2: _ A3: _ Additional Inputs I: fec_RX_DV I: _ I: _ I: _ I: lin1_RXD I: _ I: pdi_DATA[0] I: _ I: flexpwm2_FAULT[2] I: pdi_DATA[1] I: _ I: _ I: _ I: _ I: _ I: flexray_CA_RX I: _ I: _ I: pdi_LINE_V I: _ I: flexpwm2_FAULT[0] I: pdi_DATA[2] I: _ I: _ I: pdi_DATA[3] I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 35 GPIO fec RX_DV D13 GPIO fec MDC — disabled GP Slow/ Medium VDD_HV_IO D16 GPIO pdi DATA[0] — disabled PDI Medium VDD_HV_PDI D17 GPIO pdi DATA[1] — disabled PDI Medium VDD_HV_PDI E2 GPIO nexus MDO[1]1 — disabled GP Slow/ Fast VDD_HV_IO E3 GPIO flexray CA_RX — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions E14 GPIO pdi LINE_V — disabled PDI Medium VDD_HV_PDI E15 GPIO pdi DATA[2] — disabled PDI Medium VDD_HV_PDI E16 GPIO pdi DATA[3] — disabled PDI Medium VDD_HV_PDI Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type E17 Ball Name Alternate I/O A0: siul_GPIO[135] A1: flexpwm2_A[2] A2: _ A3: etimer1_ETC[4] A0: siul_GPIO[113] A1: _ A2: npc_wrapper_MDO[6] A3: _ A0: siul_GPIO[108] A1: _ A2: npc_wrapper_MDO[11] A3: _ A0: siul_GPIO[7] A1: dspi1_SOUT A2: _ A3: _ A0: siul_GPIO[8] A1: _ A2: _ A3: _ A0: siul_GPIO[233] A1: mc_cgl_clk_out A2: etimer2_ETC[5] A3: _ A0: siul_GPIO[137] A1: flexpwm2_B[0] A2: _ A3: etimer1_ETC[1] A0: siul_GPIO[138] A1: flexpwm2_B[2] A2: _ A3: etimer1_ETC[5] A0: siul_GPIO[139] A1: flexpwm2_A[3] A2: _ A3: _ Additional Inputs I: pdi_DATA[4] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[7] I: dspi1_SIN I: _ I: siul_EIRQ[8] I: _ I: _ I: _ I: pdi_DATA[6] I: _ I: _ I: pdi_DATA[7] I: _ I: _ I: pdi_DATA[8] I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type PDI Medium Power Domain VDD_HV_PDI Package pinouts and signal descriptions 36 GPIO pdi DATA[4] F1 GPIO nexus MDO[6]1 Preliminary—Subject to Change Without Notice Freescale Semiconductor F2 GPIO nexus MDO[11]1 MPC5675K Microcontroller Data Sheet, Rev. 4 F3 GPIO dspi1 SOUT F4 GPIO dspi1 SIN F14 GPIO mc_cgl clk_out F15 GPIO pdi DATA[6] F16 GPIO pdi DATA[7] F17 GPIO pdi DATA[8] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled PDI Fast VDD_HV_PDI — disabled PDI Medium VDD_HV_PDI — disabled PDI Medium VDD_HV_PDI — disabled PDI Medium VDD_HV_PDI Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type G1 Ball Name Alternate I/O A0: siul_GPIO[115] A1: _ A2: npc_wrapper_MDO[4] A3: _ A0: siul_GPIO[37] A1: dspi0_SCK A2: _ A3: sscm_DEBUG[5] A0: siul_GPIO[6] A1: dspi1_SCK A2: _ A3: _ A0: siul_GPIO[140] A1: flexpwm2_X[2] A2: _ A3: _ A0: siul_GPIO[141] A1: flexpwm2_X[3] A2: _ A3: _ A0: siul_GPIO[142] A1: flexpwm2_X[0] A2: _ A3: _ A0: siul_GPIO[130] A1: _ A2: _ A3: _ A0: siul_GPIO[109] A1: _ A2: npc_wrapper_MDO[10] A3: _ A0: siul_GPIO[36] A1: dspi0_CS0 A2: _ A3: sscm_DEBUG[4] I: _ I: _ I: _ I: flexpwm0_FAULT[3] I: _ I: siul_EIRQ[23] I: _ I: _ I: siul_EIRQ[6] I: pdi_DATA[9] I: _ I: _ I: pdi_DATA[10] I: _ I: _ I: pdi_DATA[11] I: _ I: _ I: pdi_FRAME_V I: lin2_RXD I: flexpwm2_FAULT[1] I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[22] Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Fast Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 37 GPIO nexus MDO[4]1 G3 GPIO dspi0 SCK — disabled GP Slow/ Medium VDD_HV_IO G4 GPIO dspi1 SCK — disabled GP Slow/ Medium VDD_HV_IO G14 GPIO pdi DATA[9] — disabled PDI Medium VDD_HV_PDI G15 GPIO pdi DATA[10] — disabled PDI Medium VDD_HV_PDI G16 GPIO pdi DATA[11] — disabled PDI Medium VDD_HV_PDI Package pinouts and signal descriptions G17 GPIO pdi FRAME_V — disabled PDI Medium VDD_HV_PDI H1 GPIO nexus MDO[10]1 — disabled GP Slow/ Fast VDD_HV_IO H3 GPIO dspi0 CS0 — disabled GP Slow/ Medium VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type H4 Ball Name Alternate I/O A0: siul_GPIO[5] A1: dspi1_CS0 A2: _ A3: dspi0_CS7 A0: siul_GPIO[143] A1: _ A2: _ A3: _ A0: siul_GPIO[144] A1: pdi_SENS_SEL[2] A2: ctu1_EXT_TGR A3: _ A0: siul_GPIO[194] A1: flexpwm0_X[0] A2: ebi_D28 A3: _ A0: siul_GPIO[87] A1: _ A2: npc_wrapper_MCKO A3: _ A0: siul_GPIO[111] A1: _ A2: npc_wrapper_MDO[8] A3: _ A0: siul_GPIO[10] A1: dspi2_CS0 A2: _ A3: can3_TXD A0: siul_GPIO[42] A1: dspi2_CS2 A2: lin3_TXD A3: can2_TXD A0: siul_GPIO[145] A1: pdi_SENS_SEL[1] A2: i2c2_clock A3: _ Additional Inputs I: _ I: _ I: siul_EIRQ[5] I: pdi_DATA[12] I: lin3_RXD I: flexpwm2_FAULT[3] I: pdi_DATA[13] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[9] I: flexpwm0_FAULT[1] I: _ I: _ I: pdi_DATA[14] I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 38 GPIO dspi1 CS0 H14 GPIO pdi DATA[12] Preliminary—Subject to Change Without Notice Freescale Semiconductor H15 GPIO pdi DATA[13] MPC5675K Microcontroller Data Sheet, Rev. 4 H17 GPIO flexpwm0 X[0] J1 GPIO nexus MCKO J2 GPIO nexus MDO[8]1 J3 GPIO dspi2 CS0 J4 GPIO dspi2 CS2 J14 GPIO pdi DATA[14] — disabled PDI Medium VDD_HV_PDI — disabled PDI Medium VDD_HV_PDI — disabled DRAM ACC VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled PDI Medium VDD_HV_PDI Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type J15 Ball Name Alternate I/O A0: siul_GPIO[146] A1: pdi_SENS_SEL[0] A2: i2c2_data A3: _ A0: siul_GPIO[195] A1: flexpwm0_X[1] A2: ebi_D29 A3: _ Additional Inputs I: pdi_DATA[15] I: ctu1_EXT_IN I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: dspi0_SIN I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ Analog Inputs — Weak pull during reset disabled Pad Type PDI Medium Power Domain VDD_HV_PDI Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 39 GPIO pdi DATA[15] J17 GPIO flexpwm0 X[1] — disabled DRAM ACC VDD_HV_IO K1 GPIO nexus A0: siul_GPIO[89] MSEO_B[0]1 A1: _ A2: npc_wrapper_MSEO_B[0] A3: _ GPIO nexus A0: siul_GPIO[88] MSEO_B[1]1 A1: _ A2: npc_wrapper_MSEO_B[1] A3: _ GPIO nexus RDY_B A0: siul_GPIO[216] A1: _ A2: nexus_RDY_B A3: _ A0: siul_GPIO[39] A1: _ A2: _ A3: sscm_DEBUG[7] A0: siul_GPIO[196] A1: flexpwm0_X[2] A2: ebi_D30 A3: _ A0: siul_GPIO[197] A1: flexpwm0_X[3] A2: ebi_D31 A3: _ A0: siul_GPIO[149] A1: _ A2: ebi_RD_WR A3: flexpwm0_A[1] — disabled GP Slow/ Fast VDD_HV_IO K2 — disabled GP Slow/ Fast VDD_HV_IO K3 — disabled GP Slow/ Fast VDD_HV_IO K4 GPIO dspi0 SIN — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions K14 GPIO flexpwm0 X[2] — disabled DRAM ACC VDD_HV_IO K15 GPIO flexpwm0 X[3] — disabled DRAM ACC VDD_HV_IO K16 GPIO flexpwm0 A[1] — disabled DRAM ACC VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type K17 Ball Name Alternate I/O A0: siul_GPIO[148] A1: _ A2: ebi_CLKOUT A3: flexpwm0_B[0] A0: siul_GPIO[90] A1: _ A2: npc_wrapper_EVTO_B A3: _ A0: siul_GPIO[91] A1: _ A2: leo_sor_proxy_EVTI_B A3: _ A0: siul_GPIO[11] A1: dspi2_SCK A2: _ A3: _ A0: siul_GPIO[218] A1: _ A2: npc_wrapper_MDO[13] A3: _ A0: siul_GPIO[150] A1: dramc_CS0 A2: ebi_TS A3: flexpwm0_B[1] A0: siul_GPIO[20] A1: jtagc_TDO A2: _ A3: _ A0: siul_GPIO[56] A1: dspi1_CS2 A2: _ A3: dspi0_CS5 A0: siul_GPIO[217] A1: _ A2: npc_wrapper_MDO[12] A3: can2_TXD I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can3_RXD I: _ I: siul_EIRQ[10] I: can2_RXD I: can3_RXD I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[3] I: lin2_RXD I: _ I: _ I: _ I: _ Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type DRAM ACC Power Domain VDD_HV_IO Package pinouts and signal descriptions 40 GPIO flexpwm0 B[0] L1 GPIO nexus EVTO_B Preliminary—Subject to Change Without Notice Freescale Semiconductor L2 GPIO nexus EVTI_B MPC5675K Microcontroller Data Sheet, Rev. 4 L3 GPIO dspi2 SCK L4 GPIO nexus MDO[13]1 L16 GPIO flexpwm0 B[1] L17 GPIO TDO M3 GPIO dspi1 CS2 M4 GPIO nexus MDO[12]1 — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled DRAM ACC VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type M14 Ball Name Alternate I/O A0: siul_GPIO[152] A1: dramc_CAS A2: ebi_WE_BE_1 A3: flexpwm0_B[2] A0: siul_GPIO[21] A1: _ A2: _ A3: _ A0: siul_GPIO[157] A1: dramc_ODT A2: ebi_CS1 A3: flexpwm1_A[1] A0: siul_GPIO[53] A1: dspi0_CS3 A2: i2c2_clock A3: _ A0: siul_GPIO[154] A1: dramc_BA[0] A2: ebi_WE_BE_3 A3: flexpwm0_B[3] A0: siul_GPIO[151] A1: dramc_RAS A2: ebi_WE_BE_0 A3: flexpwm0_A[2] A0: siul_GPIO[155] A1: dramc_BA[1] A2: ebi_BDIP A3: flexpwm1_A[0] A0: siul_GPIO[156] A1: dramc_BA[2] A2: ebi_CS0 A3: flexpwm1_B[0] A0: siul_GPIO[54] A1: dspi0_CS2 A2: i2c2_data A3: _ I: _ I: _ I: _ I: jtagc_TDI I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[2] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[1] I: _ I: _ Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type DRAM ACC Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 41 GPIO flexpwm0 B[2] M15 GPIO TDI — pull up GP Slow/ Medium VDD_HV_IO M17 GPIO flexpwm1 A[1] — disabled DRAM ACC VDD_HV_IO N3 GPIO dspi0 CS3 — disabled GP Slow/ Medium VDD_HV_IO N14 GPIO flexpwm0 B[3] — disabled DRAM ACC VDD_HV_IO N15 GPIO flexpwm0 A[2] — disabled DRAM ACC VDD_HV_IO Package pinouts and signal descriptions N16 GPIO flexpwm1 A[0] — disabled DRAM ACC VDD_HV_IO N17 GPIO flexpwm1 B[0] — disabled DRAM ACC VDD_HV_IO P3 GPIO dspi0 CS2 — disabled GP Slow/ Medium VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type P5 Ball Name Alternate I/O A0: siul_GPIO[45] A1: etimer1_ETC[1] A2: _ A3: _ A0: siul_GPIO[46] A1: etimer1_ETC[2] A2: ctu0_EXT_TGR A3: _ — Additional Inputs I: ctu0_EXT_IN I: flexpwm0_EXT_SYNC I: ctu1_EXT_IN I: _ I: _ I: _ siul_GPI[23] lin0_RXD P8 GPIO etimer1 ETC[3] A0: siul_GPIO[92] A1: etimer1_ETC[3] A2: _ A3: _ — I: ctu1_EXT_IN I: mc_rgm_FAB I: siul_EIRQ[30] siul_GPI[28] — pull down GP Slow/ Medium VDD_HV_IO Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 42 GPIO etimer1 ETC[1] P6 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO etimer1 ETC[2] P7 ANA adc0 AN[0] MPC5675K Microcontroller Data Sheet, Rev. 4 P11 ANA adc0_adc1 AN[14] GPIO etimer1 ETC[4] P12 P13 GPIO etimer1 ETC[5] P15 GPIO flexpwm0 A[3] A0: siul_GPIO[153] A1: dramc_WEB A2: ebi_WE_BE_2 A3: flexpwm0_A[3] A0: siul_GPIO[147] A1: dramc_CKE A2: ebi_OE A3: flexpwm0_A[0] P16 GPIO flexpwm0 A[0] — disabled GP Slow/ Medium VDD_HV_IO AN: adc0_AN[0] Analog VDD_HV_ADR02 AN: adc0_adc1_AN[14] Analog Shared disabled GP Slow/ Medium VDD_HV_ADR02 A0: siul_GPIO[93] A1: etimer1_ETC[4] A2: ctu1_EXT_TGR A3: _ A0: siul_GPIO[78] A1: etimer1_ETC[5] A2: _ A3: _ I: _ I: _ I: siul_EIRQ[31] I: _ I: _ I: siul_EIRQ[26] I: _ I: _ I: _ I: _ I: _ I: _ — VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM ACC VDD_HV_IO — disabled DRAM ACC VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type P17 Ball Name Alternate I/O A0: siul_GPIO[163] A1: dramc_ADD[5] A2: ebi_ADD13 A3: flexpwm1_B[1] A0: siul_GPIO[55] A1: dspi1_CS3 A2: lin2_TXD A3: dspi0_CS4 — I: _ I: _ I: _ I: _ I: _ I: _ siul_GPI[221] Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type DRAM ACC Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 43 GPIO flexpwm1 B[1] R4 GPIO dspi1 CS3 — disabled GP Slow/ Medium VDD_HV_IO R5 ANA adc2 AN[0] ANA adc2 AN[3] ANA adc2_adc3 AN[14] ANA adc0 AN[2] ANA adc0_adc1 AN[13] ANA adc1 AN[1] AN: adc2_AN[0] — Analog VDD_HV_ADR02 R6 — siul_GPI[224] AN: adc2_AN[3] — Analog VDD_HV_ADR02 R8 — siul_GPI[228] AN: adc2_adc3_AN[14] — Analog Shared Analog VDD_HV_ADR13 R10 — siul_GPI[33] AN: adc0_AN[2] — VDD_HV_ADR02 R11 — siul_GPI[27] AN: adc0_adc1_AN[13] — Analog Shared Analog VDD_HV_ADR02 Package pinouts and signal descriptions R12 — siul_GPI[30] etimer0_ETC[4] siul_EIRQ[19] AN: adc1_AN[1] — VDD_HV_ADR13 R14 GPIO lin0 TXD A0: siul_GPIO[18] A1: lin0_TXD A2: i2c0_clock A3: sscm_DEBUG[2] A0: siul_GPIO[164] A1: dramc_ADD[6] A2: ebi_ADD14 A3: flexpwm1_A[2] I: _ I: _ I: siul_EIRQ[17] I: _ I: _ I: _ — disabled GP Slow/ Medium VDD_HV_IO R16 GPIO flexpwm1 A[2] — disabled DRAM ACC VDD_HV_IO Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type R17 Ball Name Alternate I/O A0: siul_GPIO[165] A1: dramc_ADD[7] A2: ebi_ADD15 A3: flexpwm1_B[2] A0: siul_GPIO[12] A1: dspi2_SOUT A2: _ A3: _ — I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[11] siul_GPI[229] Additional Inputs Analog Inputs — Weak pull during reset disabled Pad Type DRAM ACC Power Domain VDD_HV_IO Package pinouts and signal descriptions 44 GPIO flexpwm1 B[2] T3 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO dspi2 SOUT T4 ANA adc3 AN[0] ANA adc3 AN[3] ANA adc2 AN[2] ANA adc2_adc3 AN[13] ANA adc0 AN[1] ANA adc0_adc1 AN[12] ANA adc1 AN[0] ANA adc1 AN[2] MPC5675K Microcontroller Data Sheet, Rev. 4 T5 — T6 — T8 — T10 — T11 — T12 — T13 — — disabled GP Slow/ Medium VDD_HV_IO AN: adc3_AN[0] — Analog VDD_HV_ADR13 siul_GPI[232] AN: adc3_AN[3] — Analog VDD_HV_ADR13 siul_GPI[223] AN: adc2_AN[2] — Analog VDD_HV_ADR02 siul_GPI[227] AN: adc2_adc3_AN[13] — Analog Shared Analog VDD_HV_ADR02 siul_GPI[24] etimer0_ETC[5] siul_GPI[26] AN: adc0_AN[1] — VDD_HV_ADR02 AN: adc0_adc1_AN[12] — Analog Shared Analog VDD_HV_ADR02 siul_GPI[29] lin1_RXD siul_GPI[31] AN: adc1_AN[0] — VDD_HV_ADR13 AN: adc1_AN[2] — Analog VDD_HV_ADR13 siul_EIRQ[20] Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Number Type T14 Ball Name Alternate I/O A0: siul_GPIO[19] A1: _ A2: i2c0_data A3: sscm_DEBUG[3] A0: siul_GPIO[4] A1: etimer1_ETC[0] A2: _ A3: _ A0: siul_GPIO[13] A1: _ A2: _ A3: _ — Additional Inputs I: lin0_RXD I: _ I: _ I: _ I: _ I: siul_EIRQ[4] I: dspi2_SIN I: flexpwm0_FAULT[0] I: siul_EIRQ[12] siul_GPI[230] Analog Inputs — Weak pull during reset disabled Pad Type GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 45 GPIO lin0 RXD T15 GPIO etimer1 ETC[0] — disabled GP Slow/ Medium VDD_HV_IO U3 GPIO dspi2 SIN — disabled GP Slow/ Medium VDD_HV_IO U4 ANA adc3 AN[1] ANA adc3 AN[2] ANA adc2 AN[1] ANA adc2_adc3 AN[11] ANA adc2_adc3 AN[12] ANA adc0_adc1 AN[11] AN: adc3_AN[1] — Analog VDD_HV_ADR13 U5 — siul_GPI[231] AN: adc3_AN[2] — Analog VDD_HV_ADR13 U6 — siul_GPI[222] AN: adc2_AN[1] — Analog VDD_HV_ADR02 U7 — siul_GPI[225] AN: adc2_adc3_AN[11] — Analog Shared Analog Shared Analog Shared VDD_HV_ADR13 Package pinouts and signal descriptions U8 — siul_GPI[226] AN: adc2_adc3_AN[12] — VDD_HV_ADR13 U11 — siul_GPI[25] AN: adc0_adc1_AN[11] — VDD_HV_ADR02 END OF 257 MAPBGA PIN MULTIPLEXING TABLE NOTES: 1 Do not connect pin directly to a power supply or ground. Package pinouts and signal descriptions 46 Ball Ball Ball Name Number Type A4 GPIO nexus MDO[5]1 Alternate I/O A5 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO nexus MDO[7]1 A6 GPIO nexus MDO[9]1 MPC5675K Microcontroller Data Sheet, Rev. 4 A7 GPIO flexray CB_TX A0: siul_GPIO[51] A1: flexray_CB_TX A2: _ A3: _ A8 GPIO flexray A0: siul_GPIO[47] CA_TR_EN A1: flexray_CA_TR_EN A2: _ A3: _ GPIO fec RX_DV A0: siul_GPIO[210] A1: flexray_DBG3 A2: etimer2_ETC[0] A3: dspi0_CS7 A0: siul_GPIO[198] A1: fec_MDIO A2: _ A3: dspi2_CS0 A0: siul_GPIO[207] A1: flexray_DBG0 A2: etimer2_ETC[4] A3: dspi0_CS4 A0: siul_GPIO[200] A1: fec_TX_EN A2: _ A3: lin0_TXD A9 A10 GPIO fec MDIO A11 GPIO fec TX_CLK A12 GPIO fec TX_EN Table 10. 473 MAPBGA pin multiplexing Additional Inputs I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: ctu0_EXT_IN I: flexpwm0_EXT_SYNC I: _ I: fec_RX_DV I: _ I: _ I: _ I: _ I: siul_EIRQ[28] I: fec_TX_CLK I: _ I: _ I: _ I: _ I: _ Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Fast Power Domain VDD_HV_IO A0: siul_GPIO[114] A1: _ A2: npc_wrapper_MDO[5] A3: _ A0: siul_GPIO[112] A1: _ A2: npc_wrapper_MDO[7] A3: _ A0: siul_GPIO[110] A1: _ A2: npc_wrapper_MDO[9] A3: _ — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Symmetric VDD_HV_IO — disabled GP Slow/ Symmetric VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type A13 GPIO fec TXD[3] Alternate I/O A0: siul_GPIO[204] A1: fec_TXD[3] A2: _ A3: dspi2_CS2 A0: siul_GPIO[134] A1: flexpwm2_X[1] A2: _ A3: _ A0: siul_GPIO[132] A1: flexpwm2_B[3] A2: _ A3: _ A0: siul_GPIO[128] A1: flexpwm2_B[1] A2: _ A3: etimer1_ETC[3] A0: siul_GPIO[138] A1: flexpwm2_B[2] A2: _ A3: etimer1_ETC[5] A0: siul_GPIO[141] A1: flexpwm2_X[3] A2: _ A3: _ A0: siul_GPIO[144] A1: pdi_SENS_SEL[2] A2: ctu1_EXT_TGR A3: _ A0: siul_GPIO[146] A1: pdi_SENS_SEL[0] A2: i2c2_data A3: _ A0: siul_GPIO[22] A1: mc_cgl_clk_out A2: etimer2_ETC[5] A3: _ Additional Inputs I: flexpwm1_FAULT[2] I: _ I: siul_EIRQ[29] I: pdi_DATA[3] I: _ I: _ I: pdi_DATA[1] I: _ I: _ I: pdi_CLOCK I: _ I: _ I: pdi_DATA[7] I: _ I: _ I: pdi_DATA[10] I: _ I: _ I: pdi_DATA[13] I: _ I: _ I: pdi_DATA[15] I: ctu1_EXT_IN I: _ I: _ I: _ I: siul_EIRQ[18] Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 47 A15 GPIO pdi DATA[3] — disabled PDI Medium VDD_HV_PDI A16 GPIO pdi DATA[1] — disabled PDI Medium VDD_HV_PDI A17 GPIO pdi CLOCK — disabled PDI Medium VDD_HV_PDI A18 GPIO pdi DATA[7] — disabled PDI Medium VDD_HV_PDI A19 GPIO pdi DATA[10] — disabled PDI Medium VDD_HV_PDI Package pinouts and signal descriptions A20 GPIO pdi DATA[13] — disabled PDI Medium VDD_HV_PDI A21 GPIO pdi DATA[15] — disabled PDI Medium VDD_HV_PDI B3 GPIO mc_cgl clk_out — disabled GP Slow/ Fast VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type B4 GPIO can1 TXD Alternate I/O A0: siul_GPIO[14] A1: can1_TXD A2: _ A3: _ A0: siul_GPIO[219] A1: _ A2: npc_wrapper_MDO[14] A3: can3_TXD A0: siul_GPIO[9] A1: dspi2_CS1 A2: _ A3: _ Additional Inputs I: _ I: _ I: siul_EIRQ[13] I: _ I: _ I: _ I: flexpwm0_FAULT[0] I: lin3_RXD I: can2_RXD I: _ I: _ I: _ I: ctu1_EXT_IN I: _ I: _ I: fec_RXD[3] I: _ I: _ I: fec_RX_ER I: _ I: _ I: _ I: _ I: _ I: fec_RXD[0] I: _ I: siul_EIRQ[27] Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 48 B5 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO nexus MDO[14]1 B6 GPIO dspi2 CS1 MPC5675K Microcontroller Data Sheet, Rev. 4 B7 B8 GPIO flexray CA_TX B9 GPIO fec RXD[3] B10 GPIO fec RX_ER B11 GPIO fec TXD[0] B12 GPIO fec RXD[0] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO GPIO flexray A0: siul_GPIO[52] CB_TR_EN A1: flexray_CB_TR_EN A2: _ A3: _ A0: siul_GPIO[48] A1: flexray_CA_TX A2: _ A3: _ A0: siul_GPIO[214] A1: i2c1_data A2: _ A3: _ A0: siul_GPIO[215] A1: _ A2: _ A3: dspi0_CS1 A0: siul_GPIO[201] A1: fec_TXD[0] A2: etimer2_ETC[1] A3: _ A0: siul_GPIO[211] A1: i2c1_clock A2: _ A3: _ — disabled GP Slow/ Symmetric VDD_HV_IO — disabled GP Slow/ Symmetric VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type B13 GPIO fec TX_ER Alternate I/O A0: siul_GPIO[205] A1: fec_TX_ER A2: dspi2_CS3 A3: _ A0: siul_GPIO[137] A1: flexpwm2_B[0] A2: _ A3: etimer1_ETC[1] A0: siul_GPIO[135] A1: flexpwm2_A[2] A2: _ A3: etimer1_ETC[4] A0: siul_GPIO[131] A1: _ A2: lin3_TXD A3: _ A0: siul_GPIO[129] A1: _ A2: lin2_TXD A3: _ A0: siul_GPIO[140] A1: flexpwm2_X[2] A2: _ A3: _ A0: siul_GPIO[145] A1: pdi_SENS_SEL[1] A2: i2c2_clock A3: _ A0: siul_GPIO[16] A1: can0_TXD A2: _ A3: sscm_DEBUG[0] A0: siul_GPIO[220] A1: _ A2: npc_wrapper_MDO[15] A3: _ Additional Inputs I: flexpwm1_FAULT[3] I: lin0_RXD I: _ I: pdi_DATA[6] I: _ I: _ I: pdi_DATA[4] I: _ I: _ I: pdi_DATA[0] I: _ I: flexpwm2_FAULT[2] I: pdi_LINE_V I: _ I: flexpwm2_FAULT[0] I: pdi_DATA[9] I: _ I: _ I: pdi_DATA[14] I: _ I: _ I: _ I: _ I: siul_EIRQ[15] I: can3_RXD I: can2_RXD I: _ Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 49 B15 GPIO pdi DATA[6] — disabled PDI Medium VDD_HV_PDI B16 GPIO pdi DATA[4] — disabled PDI Medium VDD_HV_PDI B17 GPIO pdi DATA[0] — disabled PDI Medium VDD_HV_PDI B18 GPIO pdi LINE_V — disabled PDI Medium VDD_HV_PDI B19 GPIO pdi DATA[9] — disabled PDI Medium VDD_HV_PDI Package pinouts and signal descriptions B20 GPIO pdi DATA[14] — disabled PDI Medium VDD_HV_PDI B21 GPIO can0 TXD — disabled GP Slow/ Medium VDD_HV_IO C2 GPIO nexus MDO[15]1 — disabled GP Slow/ Fast VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type C5 GPIO flexray CB_RX Alternate I/O A0: siul_GPIO[50] A1: _ A2: ctu1_EXT_TGR A3: _ A0: siul_GPIO[43] A1: etimer0_ETC[4] A2: _ A3: _ A0: siul_GPIO[1] A1: etimer0_ETC[1] A2: _ A3: _ A0: siul_GPIO[2] A1: etimer0_ETC[2] A2: _ A3: _ A0: siul_GPIO[3] A1: etimer0_ETC[3] A2: _ A3: _ A0: siul_GPIO[203] A1: fec_TXD[2] A2: _ A3: _ A0: siul_GPIO[202] A1: fec_TXD[1] A2: _ A3: dspi2_SCK A0: siul_GPIO[208] A1: flexray_DBG1 A2: etimer2_ETC[3] A3: dspi0_CS5 A0: siul_GPIO[209] A1: flexray_DBG2 A2: etimer2_ETC[2] A3: dspi0_CS6 Additional Inputs I: flexray_CB_RX I: _ I: _ I: _ I: mc_rgm_ABS[0] I: _ I: _ I: _ I: siul_EIRQ[1] I: _ I: _ I: siul_EIRQ[2] I: _ I: mc_rgm_ABS[2] I: siul_EIRQ[3] I: flexpwm1_FAULT[1] I: _ I: _ I: flexpwm1_FAULT[0] I: _ I: _ I: fec_CRS I: _ I: _ I: fec_RX_CLK I: _ I: siul_EIRQ[25] Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 50 C6 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO etimer0 ETC[4] C7 GPIO etimer0 ETC[1] MPC5675K Microcontroller Data Sheet, Rev. 4 C8 GPIO etimer0 ETC[2] C9 GPIO etimer0 ETC[3] C10 GPIO fec TXD[2] C11 GPIO fec TXD[1] C12 GPIO fec CRS C13 GPIO fec RX_CLK — pull down GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — pull down GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type C14 GPIO fec RXD[1] Alternate I/O A0: siul_GPIO[212] A1: dspi1_CS1 A2: etimer2_ETC[5] A3: _ A0: siul_GPIO[206] A1: fec_COL A2: _ A3: lin1_TXD A0: siul_GPIO[136] A1: flexpwm2_A[0] A2: _ A3: etimer1_ETC[0] A0: siul_GPIO[133] A1: flexpwm2_A[1] A2: _ A3: etimer1_ETC[2] A0: siul_GPIO[139] A1: flexpwm2_A[3] A2: _ A3: _ A0: siul_GPIO[143] A1: _ A2: _ A3: _ A0: siul_GPIO[17] A1: _ A2: _ A3: sscm_DEBUG[1] A0: siul_GPIO[197] A1: flexpwm0_X[3] A2: ebi_D31 A3: _ A0: siul_GPIO[152] A1: dramc_CAS A2: ebi_WE_BE_1 A3: flexpwm0_B[2] Additional Inputs I: fec_RXD[1] I: _ I: _ I: _ I: _ I: _ I: pdi_DATA[5] I: _ I: _ I: pdi_DATA[2] I: _ I: _ I: pdi_DATA[8] I: _ I: _ I: pdi_DATA[12] I: lin3_RXD I: flexpwm2_FAULT[3] I: can0_RXD I: can1_RXD I: siul_EIRQ[16] I: _ I: _ I: _ I: _ I: _ I: _ Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 51 C15 GPIO fec COL — disabled GP Slow/ Medium VDD_HV_IO C16 GPIO pdi DATA[5] — disabled PDI Medium VDD_HV_PDI C17 GPIO pdi DATA[2] — disabled PDI Medium VDD_HV_PDI C18 GPIO pdi DATA[8] — disabled PDI Medium VDD_HV_PDI C19 GPIO pdi DATA[12] — disabled PDI Medium VDD_HV_PDI Package pinouts and signal descriptions C20 GPIO can0 RXD — disabled GP Slow/ Medium VDD_HV_IO C22 GPIO siul GPIO[197] — disabled DRAM ACC VDD_HV_DRAM C23 GPIO dramc CAS — disabled DRAM ACC VDD_HV_DRAM Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type D1 GPIO nexus MDO[1]1 Alternate I/O A0: siul_GPIO[86] A1: _ A2: npc_wrapper_MDO[1] A3: _ A0: siul_GPIO[84] A1: _ A2: npc_wrapper_MDO[3] A3: _ A0: siul_GPIO[15] A1: _ A2: _ A3: _ A0: siul_GPIO[38] A1: dspi0_SOUT A2: _ A3: sscm_DEBUG[6] A0: siul_GPIO[44] A1: etimer0_ETC[5] A2: _ A3: _ A0: siul_GPIO[0] A1: etimer0_ETC[0] A2: _ A3: _ A0: siul_GPIO[213] A1: _ A2: _ A3: dspi2_SOUT A0: siul_GPIO[199] A1: fec_MDC A2: _ A3: _ A0: siul_GPIO[142] A1: flexpwm2_X[0] A2: _ A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can1_RXD I: can0_RXD I: siul_EIRQ[14] I: _ I: _ I: siul_EIRQ[24] I: _ I: _ I: _ I: dspi2_SIN I: _ I: siul_EIRQ[0] I: fec_RXD[2] I: _ I: siul_EIRQ[21] I: _ I: lin1_RXD I: _ I: pdi_DATA[11] I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Fast Power Domain VDD_HV_IO Package pinouts and signal descriptions 52 D2 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO nexus MDO[3]1 D3 GPIO can1 RXD MPC5675K Microcontroller Data Sheet, Rev. 4 D4 GPIO dspi0 SOUT D6 GPIO etimer0 ETC[5] D7 GPIO etimer0 ETC[0] D14 GPIO fec RXD[2] D15 GPIO fec MDC D18 GPIO pdi DATA[11] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled PDI Medium VDD_HV_PDI Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type D19 GPIO pdi FRAME_V Alternate I/O A0: siul_GPIO[130] A1: _ A2: _ A3: _ A0: siul_GPIO[155] A1: dramc_BA[1] A2: ebi_BDIP A3: flexpwm1_A[0] A0: siul_GPIO[195] A1: flexpwm0_X[1] A2: ebi_D29 A3: _ A0: siul_GPIO[154] A1: dramc_BA[0] A2: ebi_WE_BE_3 A3: flexpwm0_B[3] A0: siul_GPIO[85] A1: _ A2: npc_wrapper_MDO[2] A3: _ A0: siul_GPIO[49] A1: _ A2: ctu0_EXT_TGR A3: _ A0: siul_GPIO[233] A1: mc_cgl_clk_out A2: etimer2_ETC[5] A3: _ A0: siul_GPIO[149] A1: _ A2: ebi_RD_WR A3: flexpwm0_A[1] A0: siul_GPIO[150] A1: dramc_CS0 A2: ebi_TS A3: flexpwm0_B[1] Additional Inputs I: pdi_FRAME_V I: lin2_RXD I: flexpwm2_FAULT[1] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: flexray_CA_RX I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ Analog Inputs — Weak pull Pad Type during reset disabled PDI Medium Power Domain VDD_HV_PDI Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 53 D21 GPIO dramc BA[1] — disabled DRAM ACC VDD_HV_DRAM D22 GPIO siul GPIO[195] — disabled DRAM ACC VDD_HV_DRAM D23 GPIO dramc BA[0] — disabled DRAM ACC VDD_HV_DRAM E2 GPIO nexus MDO[2]1 — disabled GP Slow/ Fast VDD_HV_IO E3 GPIO flexray CA_RX — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions E20 GPIO mc_cgl clk_out — disabled PDI Fast VDD_HV_PDI E21 GPIO siul GPIO[149] — disabled DRAM ACC VDD_HV_DRAM E22 GPIO dramc CS0 — disabled DRAM ACC VDD_HV_DRAM Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type E23 GPIO dramc BA[2] Alternate I/O A0: siul_GPIO[156] A1: dramc_BA[2] A2: ebi_CS0 A3: flexpwm1_B[0] A0: siul_GPIO[109] A1: _ A2: npc_wrapper_MDO[10] A3: _ A0: siul_GPIO[108] A1: _ A2: npc_wrapper_MDO[11] A3: _ A0: siul_GPIO[113] A1: _ A2: npc_wrapper_MDO[6] A3: _ A0: siul_GPIO[115] A1: _ A2: npc_wrapper_MDO[4] A3: _ A0: siul_GPIO[151] A1: dramc_RAS A2: ebi_WE_BE_0 A3: flexpwm0_A[2] A0: siul_GPIO[194] A1: flexpwm0_X[0] A2: ebi_D28 A3: _ A0: siul_GPIO[148] A1: _ A2: ebi_CLKOUT A3: flexpwm0_B[0] A0: siul_GPIO[179] A1: dramc_D[5] A2: ebi_D13 A3: ebi_ADD29 I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled DRAM ACC Power Domain VDD_HV_DRAM Package pinouts and signal descriptions 54 F1 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO nexus MDO[10]1 F2 GPIO nexus MDO[11]1 MPC5675K Microcontroller Data Sheet, Rev. 4 F3 GPIO nexus MDO[6]1 F4 GPIO nexus MDO[4]1 F20 GPIO dramc RAS F21 GPIO siul GPIO[194] F22 GPIO siul GPIO[148] F23 GPIO dramc D[5] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type G1 GPIO nexus MCKO Alternate I/O A0: siul_GPIO[87] A1: _ A2: npc_wrapper_MCKO A3: _ A0: siul_GPIO[111] A1: _ A2: npc_wrapper_MDO[8] A3: _ I: _ I: _ I: _ I: _ I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Fast Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 55 G3 GPIO nexus MDO[8]1 — disabled GP Slow/ Fast VDD_HV_IO G4 GPIO nexus A0: siul_GPIO[88] I: _ MSEO_B[1]1 A1: _ I: _ A2: npc_wrapper_MSEO_B[1] I: _ A3: _ GPIO siul GPIO[196] A0: siul_GPIO[196] A1: flexpwm0_X[2] A2: ebi_D30 A3: _ A0: siul_GPIO[190] A1: dramc_DQS[0] A2: ebi_D24 A3: _ A0: siul_GPIO[192] A1: dramc_DM[0] A2: ebi_D26 A3: _ A0: siul_GPIO[181] A1: dramc_D[7] A2: ebi_D15 A3: ebi_ADD31 A0: siul_GPIO[90] A1: _ A2: npc_wrapper_EVTO_B A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ — disabled GP Slow/ Fast VDD_HV_IO G20 — disabled DRAM ACC VDD_HV_DRAM G21 GPIO dramc DQS[0] — disabled DRAM DQ VDD_HV_DRAM G22 GPIO dramc DM[0] — disabled DRAM DQ VDD_HV_DRAM Package pinouts and signal descriptions G23 GPIO dramc D[7] — disabled DRAM DQ VDD_HV_DRAM H1 GPIO nexus EVTO_B — disabled GP Slow/ Fast VDD_HV_IO H3 GPIO nexus A0: siul_GPIO[89] MSEO_B[0]1 A1: _ A2: npc_wrapper_MSEO_B[0] A3: _ — disabled GP Slow/ Fast VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type H4 GPIO nexus EVTI_B Alternate I/O A0: siul_GPIO[91] A1: _ A2: leo_sor_proxy_EVTI_B A3: _ A0: siul_GPIO[176] A1: dramc_D[2] A2: ebi_D10 A3: ebi_ADD26 A0: siul_GPIO[216] A1: _ A2: nexus_RDY_B A3: _ A0: siul_GPIO[218] A1: _ A2: npc_wrapper_MDO[13] A3: _ A0: siul_GPIO[217] A1: _ A2: npc_wrapper_MDO[12] A3: can2_TXD A0: siul_GPIO[8] A1: _ A2: _ A3: _ A0: siul_GPIO[174] A1: dramc_D[0] A2: ebi_D8 A3: ebi_ADD24 A0: siul_GPIO[175] A1: dramc_D[1] A2: ebi_D9 A3: ebi_ADD25 A0: siul_GPIO[177] A1: dramc_D[3] A2: ebi_D11 A3: ebi_ADD27 I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can2_RXD I: can3_RXD I: _ I: _ I: _ I: _ I: dspi1_SIN I: _ I: siul_EIRQ[8] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 56 H20 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO dramc D[2] J1 GPIO nexus RDY_B MPC5675K Microcontroller Data Sheet, Rev. 4 J2 GPIO nexus MDO[13]1 J3 GPIO nexus MDO[12]1 J4 GPIO dspi1 SIN J20 GPIO dramc D[0] J21 GPIO dramc D[1] J22 GPIO dramc D[3] — disabled DRAM DQ VDD_HV_DRAM — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM DQ VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type J23 GPIO dramc D[6] Alternate I/O A0: siul_GPIO[180] A1: dramc_D[6] A2: ebi_D14 A3: ebi_ADD30 A0: siul_GPIO[37] A1: dspi0_SCK A2: _ A3: sscm_DEBUG[5] A0: siul_GPIO[5] A1: dspi1_CS0 A2: _ A3: dspi0_CS7 A0: siul_GPIO[6] A1: dspi1_SCK A2: _ A3: _ A0: siul_GPIO[7] A1: dspi1_SOUT A2: _ A3: _ A0: siul_GPIO[178] A1: dramc_D[4] A2: ebi_D12 A3: ebi_ADD28 A0: siul_GPIO[182] A1: dramc_D[8] A2: ebi_D16 A3: _ A0: siul_GPIO[183] A1: dramc_D[9] A2: ebi_D17 A3: _ A0: siul_GPIO[36] A1: dspi0_CS0 A2: _ A3: sscm_DEBUG[4] I: _ I: _ I: _ I: flexpwm0_FAULT[3] I: _ I: siul_EIRQ[23] I: _ I: _ I: siul_EIRQ[5] I: _ I: _ I: siul_EIRQ[6] I: _ I: _ I: siul_EIRQ[7] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[22] Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled Power Domain Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 57 DRAM DQ VDD_HV_DRAM K1 GPIO dspi0 SCK — disabled GP Slow/ Medium VDD_HV_IO K2 GPIO dspi1 CS0 — disabled GP Slow/ Medium VDD_HV_IO K3 GPIO dspi1 SCK — disabled GP Slow/ Medium VDD_HV_IO K4 GPIO dspi1 SOUT — disabled GP Slow/ Medium VDD_HV_IO K21 GPIO dramc D[4] — disabled DRAM DQ VDD_HV_DRAM Package pinouts and signal descriptions K22 GPIO dramc D[8] — disabled DRAM DQ VDD_HV_DRAM K23 GPIO dramc D[9] — disabled DRAM DQ VDD_HV_DRAM L1 GPIO dspi0 CS0 — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type L2 GPIO dspi2 CS2 Alternate I/O A0: siul_GPIO[42] A1: dspi2_CS2 A2: lin3_TXD A3: can2_TXD A0: siul_GPIO[10] A1: dspi2_CS0 A2: _ A3: can3_TXD A0: siul_GPIO[57] A1: flexpwm0_X[0] A2: lin2_TXD A3: _ A0: siul_GPIO[39] A1: _ A2: _ A3: sscm_DEBUG[7] A0: siul_GPIO[157] A1: dramc_ODT A2: ebi_CS1 A3: flexpwm1_A[1] A0: siul_GPIO[153] A1: dramc_WEB A2: ebi_WE_BE_2 A3: flexpwm0_A[3] A0: siul_GPIO[185] A1: dramc_D[11] A2: ebi_D19 A3: _ A0: siul_GPIO[184] A1: dramc_D[10] A2: ebi_D18 A3: _ A0: siul_GPIO[58] A1: flexpwm0_A[0] A2: _ A3: _ Additional Inputs I: flexpwm0_FAULT[1] I: _ I: _ I: _ I: _ I: siul_EIRQ[9] I: _ I: _ I: _ I: dspi0_SIN I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: etimer0_ETC[0] I: _ Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 58 L3 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO dspi2 CS0 M1 GPIO flexpwm0 X[0] MPC5675K Microcontroller Data Sheet, Rev. 4 M3 GPIO dspi0 SIN M20 GPIO dramc ODT M21 GPIO dramc WEB M22 GPIO dramc D[11] M23 GPIO dramc D[10] N1 GPIO flexpwm0 A[0] — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type N3 GPIO flexpwm0 X[1] Alternate I/O A0: siul_GPIO[60] A1: flexpwm0_X[1] A2: _ A3: _ A0: siul_GPIO[100] A1: flexpwm0_B[2] A2: _ A3: _ A0: siul_GPIO[191] A1: dramc_DQS[1] A2: ebi_D25 A3: _ A0: siul_GPIO[193] A1: dramc_DM[1] A2: ebi_D27 A3: _ A0: siul_GPIO[187] A1: dramc_D[13] A2: ebi_D21 A3: _ A0: siul_GPIO[186] A1: dramc_D[12] A2: ebi_D20 A3: _ A0: siul_GPIO[59] A1: flexpwm0_B[0] A2: _ A3: _ A0: siul_GPIO[62] A1: flexpwm0_B[1] A2: _ A3: _ A0: siul_GPIO[99] A1: flexpwm0_A[2] A2: _ A3: _ Additional Inputs I: lin2_RXD I: _ I: _ I: _ I: etimer0_ETC[5] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: etimer0_ETC[1] I: _ I: _ I: etimer0_ETC[3] I: _ I: _ I: etimer0_ETC[4] I: _ Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 59 N4 GPIO flexpwm0 B[2] — disabled GP Slow/ Medium VDD_HV_IO N20 GPIO dramc DQS[1] — disabled DRAM DQ VDD_HV_DRAM N21 GPIO dramc DM[1] — disabled DRAM DQ VDD_HV_DRAM N22 GPIO dramc D[13] — disabled DRAM DQ VDD_HV_DRAM N23 GPIO dramc D[12] — disabled DRAM DQ VDD_HV_DRAM Package pinouts and signal descriptions P1 GPIO flexpwm0 B[0] — disabled GP Slow/ Medium VDD_HV_IO P2 GPIO flexpwm0 B[1] — disabled GP Slow/ Medium VDD_HV_IO P3 GPIO flexpwm0 A[2] — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type P4 GPIO flexpwm0 A[3] Alternate I/O A0: siul_GPIO[102] A1: flexpwm0_A[3] A2: _ A3: _ A0: siul_GPIO[188] A1: dramc_D[14] A2: ebi_D22 A3: _ A0: siul_GPIO[189] A1: dramc_D[15] A2: ebi_D23 A3: _ A0: siul_GPIO[98] A1: flexpwm0_X[2] A2: lin3_TXD A3: _ A0: siul_GPIO[101] A1: flexpwm0_X[3] A2: _ A3: _ A0: siul_GPIO[80] A1: flexpwm0_A[1] A2: _ A3: _ A0: siul_GPIO[161] A1: dramc_ADD[3] A2: ebi_ADD11 A3: ebi_TEA A0: siul_GPIO[147] A1: dramc_CKE A2: ebi_OE A3: flexpwm0_A[0] A0: siul_GPIO[103] A1: flexpwm0_B[3] A2: _ A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: lin3_RXD I: _ I: _ I: _ I: etimer0_ETC[2] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 60 P20 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO dramc D[14] P21 GPIO dramc D[15] MPC5675K Microcontroller Data Sheet, Rev. 4 R1 GPIO flexpwm0 X[2] R2 GPIO flexpwm0 X[3] R3 GPIO flexpwm0 A[1] R21 GPIO dramc ADD[3] R22 GPIO dramc CKE T1 GPIO flexpwm0 B[3] — disabled DRAM DQ VDD_HV_DRAM — disabled DRAM DQ VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type T2 GPIO flexpwm1 A[0] Alternate I/O A0: siul_GPIO[117] A1: flexpwm1_A[0] A2: _ A3: can2_TXD A0: siul_GPIO[120] A1: flexpwm1_A[1] A2: _ A3: can3_TXD A0: siul_GPIO[166] A1: dramc_ADD[8] A2: ebi_D0 A3: ebi_ADD16 A0: siul_GPIO[167] A1: dramc_ADD[9] A2: ebi_D1 A3: ebi_ADD17 A0: siul_GPIO[159] A1: dramc_ADD[1] A2: ebi_ADD9 A3: ebi_CS3 A0: siul_GPIO[118] A1: flexpwm1_B[0] A2: _ A3: _ A0: siul_GPIO[121] A1: flexpwm1_B[1] A2: _ A3: _ A0: siul_GPIO[123] A1: flexpwm1_A[2] A2: _ A3: _ A0: siul_GPIO[11] A1: dspi2_SCK A2: _ A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: can2_RXD I: can3_RXD I: _ I: can3_RXD I: can2_RXD I: _ I: _ I: _ I: _ I: can3_RXD I: _ I: siul_EIRQ[10] Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 61 T3 GPIO flexpwm1 A[1] — disabled GP Slow/ Medium VDD_HV_IO T20 GPIO dramc ADD[8] — disabled DRAM ACC VDD_HV_DRAM T21 GPIO dramc ADD[9] — disabled DRAM ACC VDD_HV_DRAM T22 GPIO dramc ADD[1] — disabled DRAM ACC VDD_HV_DRAM U1 GPIO flexpwm1 B[0] — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions U2 GPIO flexpwm1 B[1] — disabled GP Slow/ Medium VDD_HV_IO U3 GPIO flexpwm1 A[2] — disabled GP Slow/ Medium VDD_HV_IO U4 GPIO dspi2 SCK — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type U20 GPIO dramc ADD[6] Alternate I/O A0: siul_GPIO[164] A1: dramc_ADD[6] A2: ebi_ADD14 A3: flexpwm1_A[2] A0: siul_GPIO[170] A1: dramc_ADD[12] A2: ebi_D4 A3: ebi_ADD20 A0: siul_GPIO[158] A1: dramc_ADD[0] A2: ebi_ADD8 A3: ebi_CS2 A0: siul_GPIO[124] A1: flexpwm1_B[2] A2: _ A3: _ A0: siul_GPIO[56] A1: dspi1_CS2 A2: _ A3: dspi0_CS5 A0: siul_GPIO[18] A1: lin0_TXD A2: i2c0_clock A3: sscm_DEBUG[2] A0: siul_GPIO[171] A1: dramc_ADD[13] A2: ebi_D5 A3: ebi_ADD21 A0: siul_GPIO[160] A1: dramc_ADD[2] A2: ebi_ADD10 A3: ebi_TA A0: siul_GPIO[53] A1: dspi0_CS3 A2: i2c2_clock A3: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[3] I: lin2_RXD I: _ I: _ I: _ I: siul_EIRQ[17] I: _ I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[2] I: _ I: _ Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled DRAM ACC Power Domain VDD_HV_DRAM Package pinouts and signal descriptions 62 U21 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO dramc ADD[12] U23 GPIO dramc ADD[0] MPC5675K Microcontroller Data Sheet, Rev. 4 V3 GPIO flexpwm1 B[2] V4 GPIO dspi1 CS2 V20 GPIO lin0 TXD V21 GPIO dramc ADD[13] V23 GPIO dramc ADD[2] W3 GPIO dspi0 CS3 — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM ACC VDD_HV_DRAM — disabled DRAM ACC VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type W20 GPIO lin0 RXD Alternate I/O A0: siul_GPIO[19] A1: _ A2: i2c0_data A3: sscm_DEBUG[3] A0: siul_GPIO[172] A1: dramc_ADD[14] A2: ebi_D6 A3: ebi_ADD22 A0: siul_GPIO[165] A1: dramc_ADD[7] A2: ebi_ADD15 A3: flexpwm1_B[2] A0: siul_GPIO[162] A1: dramc_ADD[4] A2: ebi_ADD12 A3: ebi_ALE A0: siul_GPIO[54] A1: dspi0_CS2 A2: i2c2_data A3: _ A0: siul_GPIO[116] A1: flexpwm1_X[0] A2: etimer2_ETC[0] A3: dspi0_CS1 — Additional Inputs I: lin0_RXD I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: flexpwm0_FAULT[1] I: _ I: _ I: ctu0_EXT_IN I: ctu1_EXT_IN I: _ siul_GPI[229] Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 63 W21 GPIO dramc ADD[14] — disabled DRAM ACC VDD_HV_DRAM W22 GPIO dramc ADD[7] — disabled DRAM ACC VDD_HV_DRAM W23 GPIO dramc ADD[4] — disabled DRAM ACC VDD_HV_DRAM Y3 GPIO dspi0 CS2 — disabled GP Slow/ Medium VDD_HV_IO Y5 GPIO flexpwm1 X[0] — disabled GP Slow/ Medium VDD_HV_IO Package pinouts and signal descriptions Y6 ANA adc3 AN[0] adc2_adc3 AN[11] adc2_adc3 AN[14] AN: adc3_AN[0] — Analog VDD_HV_ADR23 Y7 ANA — siul_GPI[225] AN: adc2_adc3_AN[11] — Analog Shared Analog Shared VDD_HV_ADR23 Y8 ANA — siul_GPI[228] AN: adc2_adc3_AN[14] — VDD_HV_ADR23 Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type Y9 GPIO etimer1 ETC[1] Alternate I/O A0: siul_GPIO[45] A1: etimer1_ETC[1] A2: _ A3: _ A0: siul_GPIO[46] A1: etimer1_ETC[2] A2: ctu0_EXT_TGR A3: _ A0: siul_GPIO[92] A1: etimer1_ETC[3] A2: _ A3: _ — Additional Inputs I: ctu0_EXT_IN I: flexpwm0_EXT_SYNC I: ctu1_EXT_IN I: _ I: _ I: _ I: ctu1_EXT_IN I: mc_rgm_FAB I: siul_EIRQ[30] siul_GPI[25] Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Package pinouts and signal descriptions 64 Y10 Preliminary—Subject to Change Without Notice Freescale Semiconductor GPIO etimer1 ETC[2] Y11 GPIO etimer1 ETC[3] MPC5675K Microcontroller Data Sheet, Rev. 4 Y14 ANA adc0_adc1 AN[11] Y15 GPIO etimer1 ETC[5] Y16 GPIO etimer1 ETC[4] Y17 ANA adc1 AN[8] adc1 AN[6] — Y18 ANA — Y21 GPIO dramc ADD[15] — disabled GP Slow/ Medium VDD_HV_IO — pull down GP Slow/ Medium VDD_HV_IO AN: adc0_adc1_AN[11] — Analog Shared GP Slow/ Medium VDD_HV_ADR0 A0: siul_GPIO[78] A1: etimer1_ETC[5] A2: _ A3: _ A0: siul_GPIO[93] A1: etimer1_ETC[4] A2: ctu1_EXT_TGR A3: _ I: _ I: _ I: siul_EIRQ[26] I: _ I: _ I: siul_EIRQ[31] siul_GPI[74] — disabled VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO AN: adc1_AN[8] — Analog VDD_HV_ADR1 siul_GPI[76] AN: adc1_AN[6] — Analog VDD_HV_ADR1 A0: siul_GPIO[173] A1: dramc_ADD[15] A2: ebi_D7 A3: ebi_ADD23 I: _ I: _ I: _ — disabled DRAM ACC VDD_HV_DRAM Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type Y22 GPIO dramc ADD[11] Alternate I/O A0: siul_GPIO[169] A1: dramc_ADD[11] A2: ebi_D3 A3: ebi_ADD19 A0: siul_GPIO[163] A1: dramc_ADD[5] A2: ebi_ADD13 A3: flexpwm1_B[1] A0: siul_GPIO[55] A1: dspi1_CS3 A2: lin2_TXD A3: dspi0_CS4 A0: siul_GPIO[119] A1: flexpwm1_X[1] A2: etimer2_ETC[1] A3: dspi0_CS4 — I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ siul_GPI[230] Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled DRAM ACC Power Domain VDD_HV_DRAM Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 65 Y23 GPIO dramc ADD[5] — disabled DRAM ACC VDD_HV_DRAM AA4 GPIO dspi1 CS3 — disabled GP Slow/ Medium VDD_HV_IO AA5 GPIO flexpwm1 X[1] — disabled GP Slow/ Medium VDD_HV_IO AA6 ANA adc3 AN[1] adc2_adc3 AN[12] adc2 AN[0] adc0 AN[2] adc0 AN[5] adc0 AN[8] AN: adc3_AN[1] — Analog VDD_HV_ADR23 AA7 ANA — siul_GPI[226] AN: adc2_adc3_AN[12] — Analog Shared Analog VDD_HV_ADR23 AA8 ANA — siul_GPI[221] AN: adc2_AN[0] — VDD_HV_ADR23 Package pinouts and signal descriptions AA11 ANA — siul_GPI[33] AN: adc0_AN[2] — Analog VDD_HV_ADR0 AA12 ANA — siul_GPI[66] AN: adc0_AN[5] — Analog VDD_HV_ADR0 AA13 ANA — siul_GPI[69] AN: adc0_AN[8] — Analog VDD_HV_ADR0 Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type AA14 ANA adc0_adc1 AN[12] adc1 AN[0] adc1 AN[2] Alternate I/O — Additional Inputs siul_GPI[26] Analog Inputs AN: adc0_adc1_AN[12] Weak pull Pad Type during reset — Analog Shared Analog Power Domain VDD_HV_ADR0 Package pinouts and signal descriptions 66 AA15 ANA — Preliminary—Subject to Change Without Notice Freescale Semiconductor AA16 MPC5675K Microcontroller Data Sheet, Rev. 4 ANA — AA17 ANA adc1 AN[5] adc1 AN[7] — AA18 ANA — AA19 GPIO TDI AA20 GPIO etimer1 ETC[0] AA22 GPIO lin1 TXD AA23 GPIO dramc ADD[10] AB3 GPIO dspi2 SOUT siul_GPI[29] lin1_RXD siul_GPI[31] AN: adc1_AN[0] — VDD_HV_ADR1 AN: adc1_AN[2] — Analog VDD_HV_ADR1 siul_EIRQ[20] siul_GPI[64] AN: adc1_AN[5] — Analog VDD_HV_ADR1 siul_GPI[73] AN: adc1_AN[7] — Analog VDD_HV_ADR1 A0: siul_GPIO[21] A1: _ A2: _ A3: _ A0: siul_GPIO[4] A1: etimer1_ETC[0] A2: _ A3: _ A0: siul_GPIO[94] A1: lin1_TXD A2: i2c1_clock A3: _ A0: siul_GPIO[168] A1: dramc_ADD[10] A2: ebi_D2 A3: ebi_ADD18 A0: siul_GPIO[12] A1: dspi2_SOUT A2: _ A3: _ I: jtagc_TDI I: _ I: _ I: _ I: _ I: siul_EIRQ[4] I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: _ I: siul_EIRQ[11] — pull up GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled DRAM ACC VDD_HV_DRAM — disabled GP Slow/ Medium VDD_HV_IO Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type AB4 GPIO flexpwm1 X[2] Alternate I/O A0: siul_GPIO[122] A1: flexpwm1_X[2] A2: etimer2_ETC[2] A3: dspi0_CS5 A0: siul_GPIO[125] A1: flexpwm1_X[3] A2: etimer2_ETC[3] A3: dspi0_CS6 — I: _ I: _ I: _ I: _ I: _ I: _ siul_GPI[231] Additional Inputs Analog Inputs — Weak pull Pad Type during reset disabled GP Slow/ Medium Power Domain VDD_HV_IO Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 67 AB5 GPIO flexpwm1 X[3] — disabled GP Slow/ Medium VDD_HV_IO AB6 ANA adc3 AN[2] adc2_adc3 AN[13] adc2 AN[1] adc2 AN[2] adc0 AN[0] adc0 AN[4] adc0 AN[6] adc0 AN[7] adc0_adc1 AN[13] AN: adc3_AN[2] — Analog VDD_HV_ADR23 AB7 ANA — siul_GPI[227] AN: adc2_adc3_AN[13] — Analog Shared Analog VDD_HV_ADR23 AB8 ANA — siul_GPI[222] AN: adc2_AN[1] — VDD_HV_ADR23 AB9 ANA — siul_GPI[223] AN: adc2_AN[2] — Analog VDD_HV_ADR23 AB10 ANA — siul_GPI[23] lin0_RXD AN: adc0_AN[0] — Analog VDD_HV_ADR0 Package pinouts and signal descriptions AB11 ANA — siul_GPI[70] AN: adc0_AN[4] — Analog VDD_HV_ADR0 AB12 ANA — siul_GPI[71] AN: adc0_AN[6] — Analog VDD_HV_ADR0 AB13 ANA — siul_GPI[68] AN: adc0_AN[7] — Analog VDD_HV_ADR0 AB14 ANA — siul_GPI[27] AN: adc0_adc1_AN[13] — Analog Shared VDD_HV_ADR0 Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type AB15 ANA adc1 AN[1] Alternate I/O — Additional Inputs siul_GPI[30] etimer0_ETC[4] siul_EIRQ[19] AB16 ANA adc1 AN[3] adc1 AN[4] — siul_GPI[32] AN: adc1_AN[3] — Analog VDD_HV_ADR1 Analog Inputs AN: adc1_AN[1] Weak pull Pad Type during reset — Analog Power Domain VDD_HV_ADR1 Package pinouts and signal descriptions 68 Preliminary—Subject to Change Without Notice Freescale Semiconductor AB17 MPC5675K Microcontroller Data Sheet, Rev. 4 ANA — AB18 GPIO TDO AB21 GPIO lin1 RXD AC3 GPIO dspi2 SIN AC4 GPIO flexpwm1 A[3] AC5 GPIO flexpwm1 B[3] AC6 ANA adc3 AN[3] adc2 AN[3] — AC9 ANA — siul_GPI[75] AN: adc1_AN[4] — Analog VDD_HV_ADR1 A0: siul_GPIO[20] A1: jtagc_TDO A2: _ A3: _ A0: siul_GPIO[95] A1: _ A2: i2c1_data A3: _ A0: siul_GPIO[13] A1: _ A2: _ A3: _ A0: siul_GPIO[126] A1: flexpwm1_A[3] A2: etimer2_ETC[4] A3: dspi0_CS7 A0: siul_GPIO[127] A1: flexpwm1_B[3] A2: etimer2_ETC[5] A3: _ I: _ I: _ I: _ I: lin1_RXD I: _ I: _ I: dspi2_SIN I: flexpwm0_FAULT[0] I: siul_EIRQ[12] I: _ I: _ I: _ I: _ I: _ I: _ siul_GPI[232] — disabled GP Slow/ Fast VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO — disabled GP Slow/ Medium VDD_HV_IO AN: adc3_AN[3] — GP Slow/ VDD_HV_ADR23 Medium Analog VDD_HV_ADR23 siul_GPI[224] AN: adc2_AN[3] — Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Number Type AC10 ANA adc0 AN[1] adc0 AN[3] adc0_adc1 AN[14] Alternate I/O — Additional Inputs siul_GPI[24] etimer0_ETC[5] siul_GPI[34] Analog Inputs AN: adc0_AN[1] Weak pull Pad Type during reset — Analog Power Domain VDD_HV_ADR0 Freescale Semiconductor MPC5675K Microcontroller Data Sheet, Rev. 4 Preliminary—Subject to Change Without Notice 69 AC11 ANA — AN: adc0_AN[3] — Analog VDD_HV_ADR0 AC14 ANA — siul_GPI[28] AN: adc0_adc1_AN[14] — Analog Shared VDD_HV_ADR0 END OF 473 MAPBGA PIN MULTIPLEXING TABLE NOTES: 1 Do not connect pin directly to a power supply or ground. Package pinouts and signal descriptions Electrical characteristics 3 3.1 Electrical characteristics Introduction This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. The “Symbol” column of the electrical parameter and timings tables may contain an additional column containing “SR”, “CC”, “P”, “C”, “T” or “D”. • “SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An example is the input voltage of a voltage regulator. • “CC” identifies specifications that define normal device operation. Where available, the letters “P”, “C”, “T” or “D” replace the letter “CC” and apply to these controller characteristics. They specify how each characteristic is guaranteed. — P: parameter is guaranteed by production testing of each individual device. — C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process variations. — T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category. — D: parameters are derived mainly from simulations. 3.2 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Absolute maximum ratings Table 11. Absolute maximum ratings1 Symbol VDD_HV_PMU VSS_HV_PMU VDD_HV_IO VSS_HV_IO VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC VDD_HV_PDI VSS_HV_PDI VDD_HV_DRAM VSS_HV_DRAM VDD_HV_ADRx 6 Parameter SR Voltage regulator supply voltage SR Voltage regulator supply ground SR Input/output supply voltage SR Input/output supply ground SR Flash supply voltage SR Flash supply ground SR Crystal oscillator amplifier supply voltage SR Crystal oscillator amplifier supply ground SR PDI interface supply voltage SR PDI interface supply ground SR DRAM interface supply voltage SR DRAM interface supply ground SR ADCx high reference voltage SR ADCx low reference voltage Conditions — — — — — — — — — — — — — — Min –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 Max2 5.53 0.1 3.64,5 0.1 3.64,5 0.1 3.64,5 0.1 3.64,5 0.1 3.64,5 0.1 6.0 0.1 Unit V V V V V V V V V V V V V V VSS_HV_ADRx MPC5675K Microcontroller Data Sheet, Rev. 4 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 11. Absolute maximum ratings1 (continued) No. 15 16 17 18 19 20 21 22 23 24 25 26 27 Symbol VDD_HV_ADV VSS_HV_ADV VDD_LV_COR VSS_LV_COR VDD_LV_PLL VSS_LV_PLL TVDD VIN IINJPAD IINJPADA IINJSUM TSTG TSDR Parameter SR ADC supply voltage SR ADC supply ground SR Core supply voltage digital logic SR Core supply voltage ground digital logic SR PLL supply voltage SR PLL reference voltage SR Slope characteristics on all VDD during power up Conditions — — — — — — — Min –0.3 –0.1 –0.3 –0.1 –0.3 –0.1 — –0.3 –10 –3 –50 –55 — — — — Max2 3.64,5 0.1 1.32 0.1 1.4 0.1 25 VDD_HV_xxx + 0.38 10 3 50 150 260 245 3 — 7 Unit V V V V V V mV/µs V mA mA mA °C °C SR Voltage on any pin with respect to its supply rail Relative to VDD_HV_xxx VDD_HV_xxx SR Injected input current on any pin during overload condition (incl. analog pins TBD) SR Injected input current on any analog pin during overload condition SR Absolute sum of all injected input currents during overload condition SR Storage temperature SR Maximum Solder Temperature9 Pb-free package SnPb package SR Moisture Sensitivity Level10 — — — — — 28 MSL NOTES: 1 Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 TBD V for 10 hours cumulative time, 5.0 V + 10% for time remaining. 4 5.3 V for 10 hours cumulative over lifetime of device, 3.63 V for time remaining. 5 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 6 All VDD_HV_ADRx rails must be operated at the same supply voltage. 7 2.0 V for 10 hours cumulative time, 1.2 V + 10% for time remaining. 8 Only when V DD_HV_xxx < 5.2 V. 9 Solder profile per CDF-AEC-Q100. 10 Moisture sensitivity per JEDEC test method A112. 3.3 No. 1 Recommended operating conditions Table 12. Recommended operating conditions1 Symbol VDD_HV_PMU Parameter SR Voltage regulator supply voltage Conditions — Min 3.0 Max 5.5 Unit V MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71 Electrical characteristics Table 12. Recommended operating conditions1 (continued) No. 2 3 4 5 6 7 8 9 10 11 12 13 Symbol VSS_HV_PMU VDD_HV_IO VSS_HV_IO VDD_HV_FLA VSS_HV_FLA VDD_HV_OSC VSS_HV_OSC VDD_HV_PDI VSS_HV_PDI VDD_HV_DRAM VSS_HV_DRAM VDD_HV_ADRx Parameter SR Voltage regulator supply ground SR Input/output supply voltage SR Input/output supply ground SR Flash supply voltage SR Flash supply ground SR Crystal oscillator amplifier supply voltage SR Crystal oscillator amplifier supply ground SR PDI interface supply voltage SR PDI interface supply ground SR DRAM interface supply voltage SR DRAM interface supply ground SR ADCx high reference voltage Conditions — — — — — — — — — — — — Alternate input voltage 14 15 16 17 17a 18 19 19a 20 21 VSS_LV_PLL TA VSS_LV_COR VDD_LV_PLL VSS_HV_ADRx VDD_HV_ADV VSS_HV_ADV VDD_LV_COR SR ADCx low reference voltage SR ADC supply voltage SR ADC supply ground SR Core supply voltage digital logic2 CC SR Core supply voltage ground digital logic SR PLL supply CC SR PLL reference voltage SR Ambient temperature under bias3 voltage2 — — — External VREG mode Internal VREG Mode — External VREG mode Internal VREG Mode — 257 MAPBGA 473 MAPBGA 22 TJ SR Junction temperature under bias 257 MAPBGA 473 MAPBGA Min 0 3.0 0 3.0 0 3.0 0 1.62 0 1.62 0 3.0 4.5 0 3.0 0 1.14 1.14 0 1.14 1.14 0 –40 –40 –40 –40 Max 0 3.6 0 3.6 0 3.6 0 3.6 0 3.6 0 3.6 5.5 0 3.6 0 1.32 1.32 0 1.32 1.32 0 1054 125 150 150 V V V V V V V V V °C °C °C Unit V V V V V V V V V V V V NOTES: 1 These specifications are design targets and are subject to change per device characterization. 2 The jitter specifications for both PLLs holds true only up to 50 mV noise (peak to peak) on V DD_LV_COR and VDD_LV_PLL. 3 See Table 1 for available frequency and package options. 4 Preliminary data. MPC5675K Microcontroller Data Sheet, Rev. 4 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.4 Thermal characteristics Table 13. Thermal characteristics for package options1 Value No. Symbol Parameter Conditions BGA 257  40  22  32  18  10 6 2 BGA 473  34  20  26  17  10 6 2 Unit 1 2 3 4 5 6 7 RJA RJA RJMA RJMA RJB RJC JT CC Thermal resistance junction-to-ambient Single layer board – 1s natural convection2 CC Thermal resistance junction-to-ambient Four layer board – 2s2p natural convection2 CC Thermal resistance junction-to-moving-air ambient2 CC Thermal resistance junction-to-moving-air ambient2 CC Thermal resistance junction-to-board3 CC Thermal resistance junction-to-case4 @ 200 ft./min., single layer board – 1s @ 200 ft./min., four layer board – 2s2p — — — °C/W °C/W °C/W °C/W °C/W °C/W °C/W CC Junction-to-package-top natural convection5 NOTES: 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. 2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3.4.1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from Equation 1: TJ = TA + (RJA × PD) Eqn. 1 where: = ambient temperature for the package (oC) TA RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73 Electrical characteristics board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (°C/W) RJC = junction to case thermal resistance (°C/W) RCA = case to ambient thermal resistance (°C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: TJ = TT + (JT × PD) Eqn. 3 Eqn. 2 where: TT = thermocouple temperature on top of the package (°C) JT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. See [6] to [10] in Section 6, Reference documents, for more information. 3.5 3.5.1 Electromagnetic interference (EMI) characteristics Test Setup Electromagnetic emission tests are performed by TEM cell [2] and via direct coupling [3] (150 Ohm) measurements. Electromagnetic immunity are measured by DPI [4]. MPC5675K Microcontroller Data Sheet, Rev. 4 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics See Section 6, Reference documents, for more information. 3.5.2 Test parameters Table 14. EMC test parameters Receiver Method 150 Ohm TEM Frequency Range BW 1 MHz to 1000 MHz 1 MHz Step Size 500 kHz The following test parameters shall be used: In case of only narrow band disturbances the maximum of the results will not change. In case of broadband signals the emission has to be below the limits. 3.6 Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. Table 15. ESD ratings1, 2 No. 1 2 3 Symbol VESD(HBM) VESD(MM) VESD(CDM) Parameter SR Electrostatic discharge (Human Body Model) SR Electrostatic discharge (Machine Model) Conditions TA = 25 °C conforming to AEC-Q100-002 TA = 25 °C conforming to AEC-Q100-003 Class H1C M2 C3A Max value3 2000 200 750 (corners) 500 Unit V V V SR Electrostatic discharge TA = 25 °C (Charged Device Model) conforming to AEC-Q100-011 NOTES: 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3 Data based on characterization results, not tested in production. 3.7 • • Static latch-up (LU) A supply over voltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. Two complementary static tests are required on six parts to assess the latch-up performance: These tests are compliant with the EIA/JESD 78 IC latch-up standard. MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 75 Electrical characteristics Table 16. Latch-up results No. 1 Symbol LU CC Parameter Static latch-up class Conditions TA = 125 °C conforming to JESD 78 Class II level A 3.8 3.8.1 Power Management Controller (PMC) electrical characteristics PMC electrical specifications Table 17. PMC electrical specifications No. 2 3 Symbol Parameter Min — — PorC – 30% — — — LvdC – 3.5% LvdC – 3% 10 — — HvdC – 3.5% HvdC – 3% 10 — — PorReg – 30% — Typ 1.28 0.7 PorC 75 1.1751 1.2151 LvdC1 LvdC1 15 1.321 1.441 HvdC1 HvdC1 15 5 2.00 PorReg 250 Max — — PorC + 30% — — — LvdC + 3.5% LvdC + 3% 20 — — HvdC + 3.5% HvdC + 3% 20 — — PorReg + 30% — Unit V V V mV V V V V mV V V V mV mV V V mV This section contains electrical characteristics for the PMC. VDD_LV_COR CC Nominal VRC regulated 1.2 V output VDD_HV_PMU PorC CC POR rising VDD 1.2 V • POR VDD variation • POR 1.2 V hysteresis CC Nominal LVD 1.2 V • LVD 1.2 V at reset (LVDCR) • LVD 1.2 V variation at reset • LVD 1.2 V variation after reset • LVD 1.2 V hysteresis CC Nominal HVD 1.2 V • HVD 1.2 V at reset (HVDCR) • HVD 1.2 V variation at reset • HVD 1.2 V variation after reset • HVD 1.2 V hysteresis CC Trimming step LVD 1.2 V, HVD 1.2 V, VRC 1.2 V CC POR rising on VDDREG • POR VDDREG variation • POR VDDREG hysteresis 4 LvdC 5 HvdC 6 7 VddStepC PorReg 8 LvdReg CC Nominal rising LVD 3.3 V on VDDREG, — — 2.865 V VDDIO, VDDFLASH, and VDDADC • LVD 3.3 V variation at reset LvdReg – 3.5% LvdReg1 LvdReg + 3.5% V • LVD 3.3 V variation after reset LvdReg – 3% LvdReg1 LvdReg + 3% V 30 • LVD 3.3 V hysteresis — — mV 50 • Minimum slew rate — — mV/ms 25 • Maximum slew rate — — mV/µs — 30 — mV 9 LvdStepReg CC Trimming step LVD 3.3 V NOTES: 1 Rising V . DD MPC5675K Microcontroller Data Sheet, Rev. 4 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.8.2 PMC board schematic and components VDD_HV_PMU Cd R Q L VDD_LV_COR D Cl Ce VSS_LV_COR Ca Cb VSS_HV_PMU Figure 7 shows a sample application for the PMC. VREG_CTRL Figure 7. PMU mandatory external components Table 18. VRC SMPS recommended external devices Reference Designator Ca Cb Cd Ce Cl D L Q Part Description — — — — — SS8P3L — SUD50P04/SQD50P04 Part Type Nominal Description Filter capacitor capacitor 20 µF, 20 V capacitor 0.1 µF, 20 V Filter capacitor capacitor 20 µF, 20 V Supply decoupling cap, ESR < 50 m, as close to p-MOS source as possible capacitor 0.1 µF, 16 V Ceramic capacitor 20 µF, 16 V Schottky — Buck capacitor, total ESR < 100 m, as close to the coil as possible Vishay low Vf Schottky diode Buck shielded coil low ESR Vishay low threshold p-MOS, Vth < 2.5 V, Rdson@4.5 V < 20 m, Cg < 5 nF Pull up for power p-MOS gate inductor 4 µH, 1.5 A pMOS 2 A, 40 V R — resistor 50–100 k MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 77 Electrical characteristics 3.9 No. 1 Supply current characteristics Table 19. Current consumption characteristics1 Symbol IDD_LV Parameter CC Maximum run IDD (incl. digital core logic and analog block of the LV rail) Conditions VDD_LV = 1.36 V, fCore = 180 MHz, 1:2 Mode, DPM, both cores executing EMC test code, internal VREG mode, all caches enabled, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1, FMPLL_1 active at 120 MHz. Min Typ Max Unit — 600 900 mA 2 3 IDD_LV_PLL IDD_HV_FLA CC Maximum run IDD for VDD_LV_PLL = 1.36 V, fVCO running at each PLL2 maximum frequency. CC Maximum run IDD Flash VDD_HV_FLA = 3.6 V, DPM, both cores executing EMC test code, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1. fOSC 4 MHz to 40 MHz, VDD_HV_OSC 3.6 V — — 1.5 20 2 30 mA mA 4 5 6 IDD_HV_OSC IDD_HV_ADV CC Maximum run IDD OSC — — — — — — — — — — 1 2 — — — — — — — — 3 4 2 1.2 1.2 1.2 2 1.2 1.2 1.2 mA mA mA mA mA mA mA mA mA mA CC Maximum run IDD for VDD_HV_ADV = 3.6 V each ADC3 ADC0 powered on6 ADC2 powered on ADC1 powered on ADC3 powered on ADC0 powered on6 IDD_HV_ADR024 CC Maximum reference IDD5 IDD_HV_ADR134 CC Maximum reference IDD5 IDD_HV_ADR07 CC Maximum reference IDD 7 8 9 IDD_HV_ADR17 CC Maximum reference IDD ADC1 powered on ADC2 powered on ADC3 powered on 10 IDD_HV_ADR237 CC Maximum reference IDD5 NOTES: 1 Applies to T = –40 °C to 150 °C. J 2 Total current on I DD_LV_PLL needs to be multiplied with the number of active PLLs. 3 Total current on IDD_HV_ADV needs to be multiplied with the number of active ADCs. 4 257 MAPBGA only. 5 Total current on IDD_HV_ADRxx is the sum of both references if both ADCs are powered on. 6 ADC0 includes 0.7 mA dissipation for the temperature sensor (TSENS). 7 473 MAPBGA only. 3.10 Temperature sensor electrical characteristics Table 20. Temperature sensor electrical characteristics Symbol Parameter P Accuracy Conditions TJ = –40 °C to TA = 125 °C Min –10 Max 10 Unit °C 1 — MPC5675K Microcontroller Data Sheet, Rev. 4 78 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics Table 20. Temperature sensor electrical characteristics (continued) Symbol 2 TS Parameter D Minimum sampling period Conditions — Min 4 Max — Unit µs 3.11 × Main oscillator electrical characteristics Table 21. Main oscillator electrical characteristics The MPC5675K provides an oscillator/resonator driver. No. 1 2 3 4 Symbol FXOSCHS Parameter SR Oscillator frequency Conditions1 Min — 4.0 — 0.65 × VDD –0.4 Value Unit Typ — TBD — — Max 40.0 TBD VDD + 0.4 0.35 × VDD MHz µs V V TXOSCHSSU CC Oscillator start-up time fOSC = 4 MHz to 40 MHz VIH VIL SR Input high level CMOS Oscillator bypass mode Schmitt Trigger SR Input low level CMOS Schmitt Trigger Oscillator bypass mode NOTES: 1V DD = 3.0 V to 3.6 V, TJ = –40 to 150 °C, unless otherwise specified. 3.12 FMPLL electrical characteristics Table 22. FMPLL electrical characteristics Symbol Parameter Conditions Crystal reference — Min TBD TBD 16 Typ — — — Max TBD TBD 256 Unit MHz MHz MHz fREF_CRYSTAL D FMPLL reference frequency fREF_EXT range1 fPLL_IN D Phase detector input frequency range (after pre-divider) fFMPLLOUT D Clock frequency range in normal See Chapter 30, mode “Frequency-Modulated Phase-Locked Loop (FMPLL),” in the MPC5675K Reference Manual (MPC5675KRM) for more details on PLL configuration. fFREE fsys tCYC fLORL fLORH fSCM P Free running frequency D On-chip FMPLL frequency2 D System clock period D Loss of reference frequency window2 D Self-clocked mode frequency3,4 Lower limit Upper limit — Measured using clock division (typically 16) — — TBD TBD — TBD TBD TBD — — — — — — TBD TBD 1 / fsys TBD TBD TBD MHz MHz ns MHz MHz MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 79 Electrical characteristics Table 22. FMPLL electrical characteristics (continued) Symbol tLOCK tlpll tdc CJITTER P Lock time D FMPLL lock time 5, 6 D Duty cycle of reference T CLKOUT period jitter7,8,9,10 Parameter Conditions Stable oscillator (fPLLIN = 4 MHz), stable VDD — — Peak-to-peak (clock edge to clock edge), fSYS maximum Long-term jitter (avg. over 2 ms interval), fSYS maximum Min — — 40 TBD TBD — — TBD TBD TBD TBD — TBD Typ — — — — — — — — — — — — Max 200 TBD 60 TBD TBD ±500 ±6 TBD TBD TBD TBD TBD Unit µs s % ps ns ps ns % fsys % fsys % fsys kHz tPKJIT tLTJIT fLCK fUL fCS fDS fMOD T Single period jitter (peak to peak) PHI @ 16 MHz, Input clock @ 4 MHz T Long term jitter D Frequency LOCK range D Frequency un-LOCK range D Modulation Depth Center spread Down Spread D Modulation frequency11 PHI @ 16 MHz, Input clock @ 4 MHz — — NOTES: 1 Considering operation with FMPLL not bypassed. 2 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode. 3 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the fLOR window. 4f VCO is the frequency at the output of the VCO; its range is 256–512 MHz. fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz. fSYS = fVCOODF 5 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this FMPLL, load capacitors should not exceed these limits. 6 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). 7 This value is determined by the crystal manufacturer and board design. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER percentage for a given interval. 9 Proper PC board layout procedures must be followed to achieve specifications. 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either fCS or fDS (depending on whether center spread or down spread modulation is enabled). 11 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz. MPC5675K Microcontroller Data Sheet, Rev. 4 80 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics 3.13 No. 1 2 16 MHz RC oscillator electrical characteristics Table 23. RC oscillator electrical characteristics Symbol fRC Parameter CC RC oscillator frequency CC Frequency spread: The variation in output frequency from PTF1 across temperature and supply voltage range CC Internal RC oscillator trimming step Conditions 27 °C, 1.2 V trimmed — Min — — Typ 16 — Max — ±5 Unit MHz % RCMVAR IRCTRIM 3 TA = 25 °C — 1.6 — % NOTES: 1 PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and temperature. 3.14 ADC electrical characteristics The MPC5675K provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3 V/ 4096 = 0.806 mV Total Unadjusted Error TUE = ±6 LSB = ±4.84 mV ( 1) 6 5 4 3 2 1 0 1 2 3 4 5 6 7 4089 40904091 40924093 40944095 code out 7 (5) (4) (3) 1 LSB (ideal) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve Vin(A) (LSBideal) Offset Error OSE Figure 8. ADC characteristics and error definitions MPC5675K Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Preliminary—Subject to Change Without Notice 81 Electrical characteristics 3.14.1 Input impedance and ADC accuracy To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fC  CS), where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 9: R S + R F + R L + R SW + R AD -1 V A  --------------------------------------------------------------------------  -- LSB R EQ 2 Eqn. 9 Equation 9 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS Filter RF Current Limiter RL Channel Selection RSW1 Sampling RAD VA CF CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 10. Input equivalent circuit MPC5675K Microcontroller Data Sheet, Rev. 4 82 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical characteristics A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1, and CP2 are initially charged at the source voltage VA (please see the equivalent circuit in Figure 10): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch is closed). VCS VA VA2 Voltage Transient on CS V