MPC8270

MPC8280 PowerQUICC™ II Family Reference Manual Supports MPC8270 MPC8275 MPC8280 MPC8280RM Rev. 1, 12/2005 How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 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Document Number: MPC8280RM Rev. 1, 12/2005 Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA) I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA) ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index 35 36 37 38 39 40 41 A B GLO IND 35 36 37 38 39 40 41 A B GLO IND ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index Contents Paragraph Number Title About This Book Before Using this Manual—Important Note ................................................................ lxxxi Audience ....................................................................................................................... lxxxi Organization................................................................................................................. lxxxii Suggested Reading...................................................................................................... lxxxiv Conventions ................................................................................................................. lxxxv Acronyms and Abbreviations ..................................................................................... lxxxvi PowerPC Architecture Terminology Conventions...................................................... lxxxix Part I Overview Chapter 1 Overview 1.1 1.2 1.2.1 1.2.2 1.2.3 1.3 1.3.1 1.4 1.5 1.6 1.6.1 1.6.2 1.7 1.7.1 1.7.1.1 1.7.1.2 1.7.1.3 1.7.1.4 1.7.1.5 1.7.1.6 1.7.2 1.7.2.1 Features ............................................................................................................................ 1-1 Architecture Overview..................................................................................................... 1-5 G2_LE Core................................................................................................................. 1-6 System Interface Unit (SIU) ........................................................................................ 1-7 Communications Processor Module (CPM) ................................................................ 1-7 Software Compatibility Issues ......................................................................................... 1-8 Signals.......................................................................................................................... 1-8 Differences Between MPC860 and MPC8280 .............................................................. 1-10 Serial Protocol Table...................................................................................................... 1-10 MPC8280 Configurations .............................................................................................. 1-11 Pin Configurations ..................................................................................................... 1-11 Serial Performance..................................................................................................... 1-11 Application Examples.................................................................................................... 1-12 Communication Systems ........................................................................................... 1-12 Remote Access Server ........................................................................................... 1-13 Regional Office Router.......................................................................................... 1-14 LAN-to-WAN Bridge Router ................................................................................ 1-14 Cellular Base Station ............................................................................................. 1-15 Telecommunications Switch Controller ................................................................ 1-16 SONET Transmission Controller........................................................................... 1-17 Bus Configurations .................................................................................................... 1-17 Basic System.......................................................................................................... 1-17 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor vii Contents Page Number Contents Paragraph Number 1.7.2.2 1.7.2.3 1.7.2.4 1.7.2.5 1.7.2.6 Title Page Number High-Performance Communication....................................................................... 1-18 High-Performance System Microprocessor........................................................... 1-19 PCI ......................................................................................................................... 1-20 PCI with 155-Mbps ATM ...................................................................................... 1-20 The MPC8280 as PCI Agent ................................................................................. 1-21 Chapter 2 G2_LE Core 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.5 2.2.6 2.2.6.1 2.2.6.2 2.3 2.3.1 2.3.1.1 2.3.1.2 2.3.1.2.1 2.3.1.2.2 2.3.1.2.3 2.3.1.2.4 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.4 2.4.1 2.4.2 2.4.2.1 2.4.2.2 2.4.2.3 Overview.......................................................................................................................... 2-1 G2_LE Core Features ..................................................................................................... 2-3 Instruction Unit ............................................................................................................ 2-5 Instruction Queue and Dispatch Unit........................................................................... 2-5 Branch Processing Unit (BPU) .................................................................................... 2-6 Independent Execution Units....................................................................................... 2-6 Integer Unit (IU) ...................................................................................................... 2-6 Floating-Point Unit (FPU) ....................................................................................... 2-6 Load/Store Unit (LSU) ............................................................................................ 2-7 System Register Unit (SRU).................................................................................... 2-7 Completion Unit .......................................................................................................... 2-7 Memory Subsystem Support........................................................................................ 2-7 Memory Management Units (MMUs)..................................................................... 2-8 Cache Units.............................................................................................................. 2-8 Programming Model ........................................................................................................ 2-8 Register Set .................................................................................................................. 2-8 PowerPC Register Set.............................................................................................. 2-9 MPC8280-Specific Registers................................................................................. 2-11 Hardware Implementation-Dependent Register 0 (HID0) ................................ 2-11 Hardware Implementation-Dependent Register 1 (HID1) ................................ 2-14 Hardware Implementation-Dependent Register 2 (HID2) ................................ 2-14 Processor Version Register (PVR)..................................................................... 2-15 PowerPC Instruction Set and Addressing Modes ...................................................... 2-15 Calculating Effective Addresses............................................................................ 2-15 PowerPC Instruction Set........................................................................................ 2-16 MPC8280 Implementation-Specific Instruction Set.............................................. 2-17 Cache Implementation ................................................................................................... 2-18 PowerPC Cache Model.............................................................................................. 2-18 MPC8280 Implementation-Specific Cache Implementation..................................... 2-18 Data Cache............................................................................................................. 2-19 Instruction Cache ................................................................................................... 2-20 Cache Locking ....................................................................................................... 2-20 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 viii Freescale Semiconductor Contents Paragraph Number 2.4.2.3.1 2.4.2.3.2 2.5 2.5.1 2.5.2 2.6 2.6.1 2.6.2 2.7 2.8 Title Page Number Entire Cache Locking ........................................................................................ 2-20 Way Locking...................................................................................................... 2-20 Exception Model............................................................................................................ 2-21 PowerPC Exception Model........................................................................................ 2-21 Implementation-Specific Exception Model ............................................................... 2-22 Memory Management.................................................................................................... 2-25 PowerPC Memory Management................................................................................ 2-25 Implementation-Specific MMU Features .................................................................. 2-25 Instruction Timing.......................................................................................................... 2-26 Differences Between the MPC8280 G2_LE Embedded Core and the MPC603e............................................................................ 2-27 Chapter 3 Memory Map 3.1 Internal Memory Map...................................................................................................... 3-2 Part II Configuration and Reset Chapter 4 System Interface Unit (SIU) 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.2 4.2.1 4.2.1.1 4.2.1.2 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.3 4.2.4 4.2.4.1 4.3 System Configuration and Protection .............................................................................. 4-2 Bus Monitor ................................................................................................................. 4-3 Timers Clock................................................................................................................ 4-3 Time Counter (TMCNT).............................................................................................. 4-4 Periodic Interrupt Timer (PIT)..................................................................................... 4-5 Software Watchdog Timer ........................................................................................... 4-6 Interrupt Controller .......................................................................................................... 4-7 Interrupt Configuration................................................................................................ 4-8 Machine Check Interrupt ......................................................................................... 4-9 INT Interrupt............................................................................................................ 4-9 Interrupt Source Priorities............................................................................................ 4-9 SCC, FCC, and MCC Relative Priority ................................................................. 4-12 PIT, TMCNT, PCI, and IRQ Relative Priority ...................................................... 4-13 Highest Priority Interrupt....................................................................................... 4-13 Masking Interrupt Sources......................................................................................... 4-13 Interrupt Vector Generation and Calculation ............................................................. 4-14 Port C External Interrupts...................................................................................... 4-16 Programming Model ...................................................................................................... 4-17 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor ix Contents Paragraph Number 4.3.1 4.3.1.1 4.3.1.2 4.3.1.3 4.3.1.4 4.3.1.5 4.3.1.6 4.3.1.7 4.3.2 4.3.2.1 4.3.2.2 4.3.2.3 4.3.2.4 4.3.2.5 4.3.2.6 4.3.2.7 4.3.2.8 4.3.2.9 4.3.2.10 4.3.2.11 4.3.2.12 4.3.2.13 4.3.2.14 4.3.2.15 4.3.2.16 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 4.3.4 4.3.4.1 4.3.4.2 4.4 Title Page Number Interrupt Controller Registers .................................................................................... 4-17 SIU Interrupt Configuration Register (SICR)........................................................ 4-17 SIU Interrupt Priority Register (SIPRR)................................................................ 4-18 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) ............................. 4-19 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) ................................ 4-21 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)........................................ 4-22 SIU Interrupt Vector Register (SIVEC) ................................................................. 4-24 SIU External Interrupt Control Register (SIEXR)................................................. 4-25 System Configuration and Protection Registers ........................................................ 4-26 Bus Configuration Register (BCR)........................................................................ 4-26 60x Bus Arbiter Configuration Register (PPC_ACR)........................................... 4-29 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)......................... 4-30 Local Bus Arbiter Configuration Register (LCL_ACR) ....................................... 4-31 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL) .............. 4-32 SIU Module Configuration Register (SIUMCR)................................................... 4-33 Internal Memory Map Register (IMMR)............................................................... 4-36 System Protection Control Register (SYPCR) ...................................................... 4-37 Software Service Register (SWSR) ....................................................................... 4-38 60x Bus Transfer Error Status and Control Register 1 (TESCR1) ........................ 4-39 60x Bus Transfer Error Status and Control Register 2 (TESCR2) ........................ 4-41 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)................. 4-42 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)................. 4-43 Time Counter Status and Control Register (TMCNTSC)...................................... 4-43 Time Counter Register (TMCNT) ......................................................................... 4-44 Time Counter Alarm Register (TMCNTAL) ......................................................... 4-45 Periodic Interrupt Registers ....................................................................................... 4-46 Periodic Interrupt Status and Control Register (PISCR) ....................................... 4-46 Periodic Interrupt Timer Count Register (PITC) ................................................... 4-47 Periodic Interrupt Timer Register (PITR).............................................................. 4-48 PCI Control Registers ................................................................................................ 4-48 PCI Base Register (PCIBRx)................................................................................. 4-49 PCI Mask Register (PCIMSKx) ............................................................................ 4-50 SIU Pin Multiplexing..................................................................................................... 4-50 Chapter 5 Reset 5.1 5.1.1 5.1.2 5.1.3 Reset Causes .................................................................................................................... 5-1 Reset Actions ............................................................................................................... 5-2 Power-On Reset Flow.................................................................................................. 5-2 HRESET Flow ............................................................................................................. 5-3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 x Freescale Semiconductor Contents Paragraph Number 5.1.4 5.2 5.3 5.4 5.4.1 5.4.2 5.4.2.1 5.4.2.2 5.4.2.3 5.4.2.4 Title Page Number SRESET Flow.............................................................................................................. 5-3 Reset Status Register (RSR) ............................................................................................ 5-4 Reset Mode Register (RMR) ........................................................................................... 5-5 Reset Configuration ......................................................................................................... 5-6 Hard Reset Configuration Word .................................................................................. 5-8 Hard Reset Configuration Examples ......................................................................... 5-10 Single MPC8280 with Default Configuration ....................................................... 5-10 Single MPC8280 Configured from Boot EPROM ................................................ 5-10 Multiple MPC8280s Configured from Boot EPROM ........................................... 5-11 Multiple MPC8280s in a System with No EPROM .............................................. 5-13 Part III The Hardware Interface Chapter 6 External Signals 6.1 6.2 Functional Pinout ............................................................................................................. 6-1 Signal Descriptions .......................................................................................................... 6-2 Chapter 7 60x Signals 7.1 7.2 7.2.1 7.2.1.1 7.2.1.1.1 7.2.1.1.2 7.2.1.2 7.2.1.2.1 7.2.1.2.2 7.2.1.3 7.2.1.3.1 7.2.1.3.2 7.2.2 7.2.2.1 7.2.2.1.1 7.2.2.2 7.2.3 7.2.3.1 Signal Configuration........................................................................................................ 7-2 Signal Descriptions .......................................................................................................... 7-2 Address Bus Arbitration Signals.................................................................................. 7-3 Bus Request (BR)—Output ..................................................................................... 7-3 Address Bus Request (BR)—Output ................................................................... 7-3 Address Bus Request (BR)—Input...................................................................... 7-3 Bus Grant (BG)........................................................................................................ 7-4 Bus Grant (BG)—Input ....................................................................................... 7-4 Bus Grant (BG)—Output..................................................................................... 7-4 Address Bus Busy (ABB)........................................................................................ 7-5 Address Bus Busy (ABB)—Output..................................................................... 7-5 Address Bus Busy (ABB)—Input ....................................................................... 7-5 Address Transfer Start Signal ...................................................................................... 7-5 Transfer Start (TS) ................................................................................................... 7-5 Transfer Start (TS)—Output ................................................................................ 7-5 Transfer Start (TS)—Input....................................................................................... 7-6 Address Transfer Signals ............................................................................................. 7-6 Address Bus (A[0–31])............................................................................................ 7-6 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xi Contents Paragraph Number 7.2.3.1.1 7.2.3.1.2 7.2.4 7.2.4.1 7.2.4.1.1 7.2.4.1.2 7.2.4.2 7.2.4.3 7.2.4.4 7.2.4.4.1 7.2.4.4.2 7.2.4.5 7.2.4.6 7.2.5 7.2.5.1 7.2.5.1.1 7.2.5.1.2 7.2.5.2 7.2.5.2.1 7.2.5.2.2 7.2.6 7.2.6.1 7.2.6.1.1 7.2.6.1.2 7.2.6.2 7.2.6.2.1 7.2.6.2.2 7.2.7 7.2.7.1 7.2.7.1.1 7.2.7.1.2 7.2.7.2 7.2.7.2.1 7.2.7.2.2 7.2.8 7.2.8.1 7.2.8.1.1 7.2.8.1.2 7.2.8.2 7.2.8.2.1 7.2.8.2.2 Title Page Number Address Bus (A[0–31])—Output......................................................................... 7-6 Address Bus (A[0–31])—Input ........................................................................... 7-7 Address Transfer Attribute Signals.............................................................................. 7-7 Transfer Type (TT[0–4]).......................................................................................... 7-7 Transfer Type (TT[0–4])—Output....................................................................... 7-7 Transfer Type (TT[0–4])—Input ......................................................................... 7-7 Transfer Size (TSIZ[0–3]) ....................................................................................... 7-7 Transfer Burst (TBST)............................................................................................. 7-8 Global (GBL)........................................................................................................... 7-8 Global (GBL)—Output........................................................................................ 7-8 Global (GBL)—Input .......................................................................................... 7-8 Caching-Inhibited (CI)—Output ............................................................................. 7-9 Write-Through (WT)—Output ................................................................................ 7-9 Address Transfer Termination Signals......................................................................... 7-9 Address Acknowledge (AACK) .............................................................................. 7-9 Address Acknowledge (AACK)—Output........................................................... 7-9 Address Acknowledge (AACK)—Input ........................................................... 7-10 Address Retry (ARTRY)........................................................................................ 7-10 Address Retry (ARTRY)—Output .................................................................... 7-10 Address Retry (ARTRY)—Input ....................................................................... 7-10 Data Bus Arbitration Signals ..................................................................................... 7-11 Data Bus Grant (DBG) .......................................................................................... 7-11 Data Bus Grant (DBG)—Input.......................................................................... 7-11 Data Bus Grant (DBG)—Output ....................................................................... 7-11 Data Bus Busy (DBB) ........................................................................................... 7-12 Data Bus Busy (DBB)—Output ........................................................................ 7-12 Data Bus Busy (DBB)—Input ........................................................................... 7-12 Data Transfer Signals................................................................................................. 7-12 Data Bus (D[0–63]) ............................................................................................... 7-13 Data Bus (D[0–63])—Output ............................................................................ 7-13 Data Bus (D[0–63])—Input............................................................................... 7-13 Data Bus Parity (DP[0–7])..................................................................................... 7-13 Data Bus Parity (DP[0–7])—Output ................................................................. 7-14 Data Bus Parity (DP[0–7])—Input .................................................................... 7-14 Data Transfer Termination Signals ............................................................................ 7-14 Transfer Acknowledge (TA) .................................................................................. 7-14 Transfer Acknowledge (TA)—Input ................................................................. 7-15 Transfer Acknowledge (TA)—Output............................................................... 7-15 Transfer Error Acknowledge (TEA)...................................................................... 7-16 Transfer Error Acknowledge (TEA)—Input ..................................................... 7-16 Transfer Error Acknowledge (TEA)—Output................................................... 7-16 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xii Freescale Semiconductor Contents Paragraph Number 7.2.8.3 7.2.8.3.1 7.2.8.3.2 Title Page Number Partial Data Valid Indication (PSDVAL) ............................................................... 7-16 Partial Data Valid (PSDVAL)—Input................................................................ 7-17 Partial Data Valid (PSDVAL)—Output ............................................................. 7-17 Chapter 8 The 60x Bus 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.3.1 8.4.3.2 8.4.3.3 8.4.3.4 8.4.3.5 8.4.3.6 8.4.3.7 8.4.3.8 8.4.4 8.4.4.1 8.4.4.2 8.4.5 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.6 8.7 8.7.1 Terminology..................................................................................................................... 8-1 Bus Configuration............................................................................................................ 8-2 Single-MPC8280 Bus Mode........................................................................................ 8-2 60x-Compatible Bus Mode.......................................................................................... 8-3 60x Bus Protocol Overview ............................................................................................. 8-4 Arbitration Phase ......................................................................................................... 8-5 Address Pipelining and Split-Bus Transactions........................................................... 8-6 Address Tenure Operations.............................................................................................. 8-7 Address Arbitration...................................................................................................... 8-7 Address Pipelining....................................................................................................... 8-8 Address Transfer Attribute Signals.............................................................................. 8-9 Transfer Type Signal (TT[0–4]) Encoding .............................................................. 8-9 Transfer Code Signals TC[0–2] ............................................................................. 8-12 TBST and TSIZ[0–3] Signals and Size of Transfer .............................................. 8-12 Burst Ordering During Data Transfers .................................................................. 8-13 Effect of Alignment on Data Transfers.................................................................. 8-14 Effect of Port Size on Data Transfers .................................................................... 8-15 60x-Compatible Bus Mode—Size Calculation ..................................................... 8-17 Extended Transfer Mode ....................................................................................... 8-18 Address Transfer Termination ................................................................................... 8-21 Address Retried with ARTRY ............................................................................... 8-21 Address Tenure Timing Configuration .................................................................. 8-23 Pipeline Control ......................................................................................................... 8-23 Data Tenure Operations ................................................................................................. 8-24 Data Bus Arbitration.................................................................................................. 8-24 Data Streaming Mode ................................................................................................ 8-25 Data Bus Transfers and Normal Termination ............................................................ 8-25 Effect of ARTRY Assertion on Data Transfer and Arbitration ................................. 8-26 Port Size Data Bus Transfers and PSDVAL Termination.......................................... 8-26 Data Bus Termination by Assertion of TEA .............................................................. 8-28 Memory Coherency—MEI Protocol ............................................................................. 8-29 Processor State Signals .................................................................................................. 8-30 Support for the lwarx/stwcx. Instruction Pair ........................................................... 8-31 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xiii Contents Paragraph Number 8.7.2 8.8 Title Page Number TLBISYNC Input ...................................................................................................... 8-31 Little-Endian Mode........................................................................................................ 8-31 Chapter 9 PCI Bridge 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.9.1 9.9.1.1 9.9.1.2 9.9.1.2.1 9.9.1.2.2 9.9.1.2.3 9.9.1.2.4 9.9.1.3 9.9.1.3.1 9.9.1.3.2 9.9.1.4 9.9.1.4.1 9.9.1.4.2 9.9.1.4.3 9.9.1.4.4 9.9.1.4.5 9.9.1.4.6 9.9.1.4.7 9.9.1.5 9.9.1.5.1 9.9.1.5.2 9.9.2 9.9.2.1 9.9.2.2 9.9.2.3 9.10 Signals.............................................................................................................................. 9-3 Clocking........................................................................................................................... 9-3 PCI Bridge Initialization.................................................................................................. 9-3 SDMA Interface............................................................................................................... 9-3 Interrupts from PCI Bridge .............................................................................................. 9-4 60x Bus Arbitration Priority ............................................................................................ 9-4 60x Bus Masters............................................................................................................... 9-4 CompactPCI Hot Swap Specification Support ................................................................ 9-5 PCI Interface .................................................................................................................... 9-5 PCI Interface Operation ............................................................................................... 9-6 Bus Commands........................................................................................................ 9-6 PCI Protocol Fundamentals ..................................................................................... 9-7 Basic Transfer Control......................................................................................... 9-8 Addressing ........................................................................................................... 9-8 Byte Enable Signals............................................................................................. 9-9 Bus Driving and Turnaround ............................................................................... 9-9 Bus Transactions...................................................................................................... 9-9 Read and Write Transactions ............................................................................... 9-9 Transaction Termination .................................................................................... 9-11 Other Bus Operations ............................................................................................ 9-13 Device Selection ................................................................................................ 9-13 Fast Back-to-Back Transactions ........................................................................ 9-14 Data Streaming .................................................................................................. 9-14 Host Mode Configuration Access...................................................................... 9-15 Agent Mode Configuration Access ................................................................... 9-16 Special Cycle Command ................................................................................... 9-16 Interrupt Acknowledge ...................................................................................... 9-17 Error Functions ...................................................................................................... 9-17 Parity.................................................................................................................. 9-17 Error Reporting.................................................................................................. 9-18 PCI Bus Arbitration ................................................................................................... 9-19 Bus Parking............................................................................................................ 9-19 Arbitration Algorithm............................................................................................ 9-19 Master Latency Timer............................................................................................ 9-20 Address Map .................................................................................................................. 9-21 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xiv Freescale Semiconductor Contents Paragraph Number 9.10.1 9.10.2 9.10.2.1 9.10.2.2 9.10.3 9.11 9.11.1 9.11.1.1 9.11.1.2 9.11.1.3 9.11.1.4 9.11.1.5 9.11.1.6 9.11.1.7 9.11.1.8 9.11.1.9 9.11.1.10 9.11.1.11 9.11.1.12 9.11.1.13 9.11.1.14 9.11.1.15 9.11.1.16 9.11.1.17 9.11.2 9.11.2.1 9.11.2.2 9.11.2.3 9.11.2.4 9.11.2.5 9.11.2.6 9.11.2.7 9.11.2.8 9.11.2.9 9.11.2.10 9.11.2.11 9.11.2.12 9.11.2.13 9.11.2.14 9.11.2.15 Title Page Number Address Map Programming ....................................................................................... 9-24 Address Translation ................................................................................................... 9-24 PCI Inbound Translation........................................................................................ 9-25 PCI Outbound Translation ..................................................................................... 9-26 SIU Registers ............................................................................................................. 9-26 Configuration Registers ................................................................................................. 9-27 Memory-Mapped Configuration Registers................................................................ 9-27 Message Unit (I2O) Registers................................................................................ 9-30 DMA Controller Registers..................................................................................... 9-30 PCI Outbound Translation Address Registers (POTARx) .................................... 9-30 PCI Outbound Base Address Registers (POBARx) .............................................. 9-31 PCI Outbound Comparison Mask Registers (POCMRx) ..................................... 9-32 Discard Timer Control Register (PTCR) .............................................................. 9-33 General Purpose Control Register (GPCR) .......................................................... 9-33 PCI General Control Register (PCI_GCR) ........................................................... 9-35 Error Status Register (ESR) .................................................................................. 9-35 Error Mask Register (EMR) ................................................................................. 9-37 Error Control Register (ECR) ............................................................................... 9-38 PCI Error Address Capture Register (PCI_EACR) .............................................. 9-39 PCI Error Data Capture Register (PCI_EDCR) .................................................... 9-40 PCI Error Control Capture Register (PCI_ECCR) ............................................... 9-40 PCI Inbound Translation Address Registers (PITARx) ........................................ 9-42 PCI Inbound Base Address Registers (PIBARx) .................................................. 9-42 PCI Inbound Comparison Mask Registers (PICMRx) .......................................... 9-43 PCI Bridge Configuration Registers ........................................................................ 9-45 Vendor ID Register ............................................................................................... 9-47 Device ID Register ............................................................................................... 9-47 PCI Bus Command Register ................................................................................. 9-47 PCI Bus Status Register ........................................................................................ 9-48 Revision ID Register ............................................................................................. 9-50 PCI Bus Programming Interface Register ............................................................ 9-50 Subclass Code Register ......................................................................................... 9-51 PCI Bus Base Class Code Register ....................................................................... 9-51 PCI Bus Cache Line Size Register ....................................................................... 9-52 PCI Bus Latency Timer Register .......................................................................... 9-52 Header Type Register ........................................................................................... 9-53 BIST Control Register .......................................................................................... 9-53 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR) .................................................................................................. 9-53 General Purpose Local Access Base Address Registers (GPLABARx) .............. 9-54 Subsystem Vendor ID Register ............................................................................. 9-55 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xv Contents Paragraph Number 9.11.2.16 9.11.2.17 9.11.2.18 9.11.2.19 9.11.2.20 9.11.2.21 9.11.2.22 9.11.2.23 9.11.2.24 9.11.2.25 9.11.2.26 9.11.2.27 9.11.2.27.1 9.11.2.27.2 9.11.2.28 9.12 9.12.1 9.12.1.1 9.12.1.2 9.12.2 9.12.2.1 9.12.2.2 9.12.3 9.12.3.1 9.12.3.2 9.12.3.2.1 9.12.3.2.2 9.12.3.3 9.12.3.3.1 9.12.3.3.2 9.12.3.4 9.12.3.4.1 9.12.3.4.2 9.12.3.4.3 9.12.3.4.4 9.12.3.4.5 9.12.3.4.6 Title Page Number Subsystem Device ID Register ............................................................................. 9-56 PCI Bus Capabilities Pointer Register .................................................................. 9-56 PCI Bus Interrupt Line Register ........................................................................... 9-57 PCI Bus Interrupt Pin Register ............................................................................. 9-57 PCI Bus MIN GNT ............................................................................................... 9-58 PCI Bus MAX LAT .............................................................................................. 9-58 PCI Bus Function Register ................................................................................... 9-59 PCI Bus Arbiter Configuration Register ............................................................... 9-60 PCI Hot Swap Register Block .............................................................................. 9-61 PCI Hot Swap Control Status Register ................................................................. 9-61 PCI Configuration Register Access from the Core ............................................... 9-62 PCI Configuration Register Access in Big-Endian Mode .................................... 9-62 Additional Information on Endianess ............................................................... 9-63 Notes on GPCR[LE_MODE] ........................................................................... 9-63 Initializing the PCI Configuration Registers ........................................................ 9-64 Message Unit (I2O) ....................................................................................................... 9-66 Message Registers...................................................................................................... 9-66 Inbound Message Registers (IMRx) ..................................................................... 9-67 Outbound Message Registers (OMRx) ................................................................. 9-67 Door Bell Registers ................................................................................................... 9-68 Outbound Doorbell Register (ODR) ..................................................................... 9-68 Inbound Doorbell Register (IDR) ......................................................................... 9-69 I2O Unit .................................................................................................................... 9-70 PCI Configuration Identification .......................................................................... 9-71 Inbound FIFOs ...................................................................................................... 9-71 Inbound Free_FIFO Head Pointer Register (IFHPR) and Inbound Free_FIFO Tail Pointer Register (IFTPR) .................................................... 9-72 Inbound Post_FIFO Head Pointer Register (IPHPR) and Inbound Post_FIFO Tail Pointer Register (IPTPR) .................................................... 9-73 Outbound FIFOs ................................................................................................... 9-75 Outbound Free_FIFO Head Pointer Register (OFHPR) and Outbound Free_FIFO Tail Pointer Register (OFTPR) .................................................. 9-75 Outbound Post_FIFO Head Pointer Register (OPHPR) and Outbound Post_FIFO Tail Pointer Register (OPTPR) ................................................... 9-76 I2O Registers.......................................................................................................... 9-78 Inbound FIFO Queue Port Register (IFQPR) ................................................... 9-78 Outbound FIFO Queue Port Register (OFQPR) ............................................... 9-79 Outbound Message Interrupt Status Register (OMISR) ................................... 9-80 Outbound Message Interrupt Mask Register (OMIMR) .................................. 9-81 Inbound Message Interrupt Status Register (IMISR) ....................................... 9-82 Inbound Message Interrupt Mask Register (IMIMR) ....................................... 9-83 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xvi Freescale Semiconductor Contents Paragraph Number 9.12.3.4.7 9.12.3.4.8 9.13 9.13.1 9.13.1.1 9.13.1.2 9.13.1.3 9.13.1.4 9.13.1.5 9.13.1.6 9.13.1.6.1 9.13.1.6.2 9.13.1.6.3 9.13.1.6.4 9.13.1.6.5 9.13.1.6.6 9.13.1.6.7 9.13.2 9.13.2.1 9.13.2.2 9.14 9.14.1 9.14.1.1 9.14.1.1.1 9.14.1.1.2 9.14.1.1.3 9.14.1.2 9.14.1.3 9.14.1.3.1 9.14.1.3.2 9.14.1.3.3 9.14.1.3.4 9.14.1.3.5 9.14.1.4 9.14.1.4.1 9.14.1.4.2 9.14.1.4.3 Title Page Number Messaging Unit Control Register (MUCR) ...................................................... 9-84 Queue Base Address Register (QBAR) ............................................................ 9-85 DMA Controller............................................................................................................. 9-86 DMA Operation ......................................................................................................... 9-86 DMA Direct Mode................................................................................................. 9-87 DMA Chaining Mode ............................................................................................ 9-87 DMA Coherency.................................................................................................... 9-88 Halt and Error Conditions...................................................................................... 9-88 DMA Transfer Types ............................................................................................. 9-88 DMA Registers ...................................................................................................... 9-89 DMA Mode Registers 0–3 (DMAMRx) .......................................................... 9-89 DMA Status Registers 0–3 (DMASRx) ............................................................ 9-91 DMA Current Descriptor Address Registers 0–3 (DMACDARx) ................... 9-92 DMA Source Address Registers 0–3 (DMASARx) ......................................... 9-93 DMA Destination Address Registers 0–3 (DMADARx) ................................. 9-94 DMA Byte Count Registers 0–3 (DMABCRx) ................................................ 9-94 DMA Next Descriptor Address Registers 0–3 (DMANDARx) ....................... 9-95 DMA Segment Descriptors........................................................................................ 9-96 Descriptor in Big-Endian Mode............................................................................. 9-97 Descriptor in Little-Endian Mode.......................................................................... 9-98 Error Handling ............................................................................................................... 9-98 Interrupt and Error Signals ........................................................................................ 9-99 PCI Bus Error Signals............................................................................................ 9-99 System Error (SERR) ........................................................................................ 9-99 Parity Error (PERR)........................................................................................... 9-99 Error Reporting.................................................................................................. 9-99 Illegal Register Access Error ................................................................................. 9-99 PCI Interface........................................................................................................ 9-100 Address Parity Error ........................................................................................ 9-100 Data Parity Error.............................................................................................. 9-100 Master-Abort Transaction Termination ........................................................... 9-100 Target-Abort Error ........................................................................................... 9-101 NMI ................................................................................................................. 9-101 Embedded Utilities .............................................................................................. 9-101 Outbound Free Queue Overflow ..................................................................... 9-101 Inbound Post Queue Overflow ........................................................................ 9-101 Inbound DoorBell Machine Check.................................................................. 9-101 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xvii Contents Paragraph Number Title Chapter 10 Clocks and Power Control 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.2 10.3 10.4 10.5 10.5.1 10.6 MPC8280 Clock Block Diagram ................................................................................... 10-1 Main PLL................................................................................................................... 10-1 Core PLL.................................................................................................................... 10-2 Skew Elimination....................................................................................................... 10-2 Dividers...................................................................................................................... 10-2 Internal Clock Signals................................................................................................ 10-2 PCI Bridge as an Agent Operating from the PCI System Clock ............................... 10-4 PCI Bridge as a Host Generating the PCI System Clock .......................................... 10-4 External Clock Inputs .................................................................................................... 10-5 PLL Pins ....................................................................................................................... 10-5 System Clock Control Register (SCCR)........................................................................ 10-6 System Clock Mode Register (SCMR).......................................................................... 10-7 Core PLL Configurations........................................................................................... 10-8 Clock Configuration Modes........................................................................................... 10-9 Chapter 11 Memory Controller 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.2.9 11.2.10 11.2.11 11.2.12 11.2.13 11.2.14 11.3 11.3.1 11.3.2 11.3.3 Features .......................................................................................................................... 11-3 Basic Architecture.......................................................................................................... 11-4 Address and Address Space Checking....................................................................... 11-7 Page Hit Checking ..................................................................................................... 11-8 Error Checking and Correction (ECC) ...................................................................... 11-8 Parity Generation and Checking ................................................................................ 11-8 Transfer Error Acknowledge (TEA) Generation ....................................................... 11-8 Machine Check Interrupt (MCP) Generation ............................................................ 11-9 Data Buffer Controls (BCTLx and LWR) ................................................................. 11-9 Atomic Bus Operation ............................................................................................... 11-9 Data Pipelining ......................................................................................................... 11-9 External Memory Controller Support ...................................................................... 11-10 External Address Latch Enable Signal (ALE) ......................................................... 11-10 ECC/Parity Byte Select (PBSE) .............................................................................. 11-10 Partial Data Valid Indication (PSDVAL) ..................................................................11-11 BADDR[27:31] Signal Connections ....................................................................... 11-12 Register Descriptions ................................................................................................... 11-12 Base Registers (BRx) ............................................................................................... 11-13 Option Registers (ORx) ........................................................................................... 11-15 60x SDRAM Mode Register (PSDMR) .................................................................. 11-20 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xviii Freescale Semiconductor Page Number Contents Paragraph Number 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 11.3.10 11.3.11 11.3.12 11.3.13 11.3.14 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.5.1 11.4.5.2 11.4.6 11.4.6.1 11.4.6.2 11.4.6.3 11.4.6.4 11.4.6.5 11.4.6.6 11.4.6.7 11.4.6.8 11.4.7 11.4.8 11.4.9 11.4.10 11.4.11 11.4.12 11.4.12.1 11.4.13 11.5 11.5.1 11.5.1.1 11.5.1.2 11.5.1.3 Title Page Number Local Bus SDRAM Mode Register (LSDMR)........................................................ 11-24 Machine A/B/C Mode Registers (MxMR)............................................................... 11-26 Memory Data Register (MDR) ................................................................................ 11-28 Memory Address Register (MAR) .......................................................................... 11-29 60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30 Local Bus-Assigned UPM Refresh Timer (LURT) ................................................. 11-30 60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-31 Local Bus-Assigned SDRAM Refresh Timer (LSRT) ............................................ 11-32 Memory Refresh Timer Prescaler Register (MPTPR) ............................................. 11-32 60x Bus Error Status and Control Registers (TESCRx) .......................................... 11-33 Local Bus Error Status and Control Registers (L_TESCRx) .................................. 11-33 SDRAM Machine ........................................................................................................ 11-33 Supported SDRAM Configurations......................................................................... 11-35 SDRAM Power-On Initialization ............................................................................ 11-35 JEDEC-Standard SDRAM Interface Commands .................................................... 11-35 Page-Mode Support and Pipeline Accesses............................................................. 11-36 Bank Interleaving .................................................................................................... 11-36 Using BNKSEL Signals in Single-MPC8280 Bus Mode.................................... 11-37 SDRAM Address Multiplexing (SDAM and BSMA)......................................... 11-37 SDRAM Device-Specific Parameters...................................................................... 11-38 Precharge-to-Activate Interval............................................................................. 11-39 Activate to Read/Write Interval ........................................................................... 11-39 Column Address to First Data Out—CAS Latency............................................. 11-40 Last Data Out to Precharge.................................................................................. 11-41 Last Data In to Precharge—Write Recovery ....................................................... 11-41 Refresh Recovery Interval (RFRC) ..................................................................... 11-42 External Address Multiplexing Signal................................................................. 11-42 External Address and Command Buffers (BUFCMD)........................................ 11-42 SDRAM Interface Timing ....................................................................................... 11-43 SDRAM Read/Write Transactions........................................................................... 11-46 SDRAM Mode-Set Command Timing .................................................................... 11-47 SDRAM Refresh...................................................................................................... 11-47 SDRAM Refresh Timing ......................................................................................... 11-48 SDRAM Configuration Examples ........................................................................... 11-48 SDRAM Configuration Example (Page-Based Interleaving).............................. 11-49 SDRAM Configuration Example (Bank-Based Interleaving) ................................. 11-50 General-Purpose Chip-Select Machine (GPCM)......................................................... 11-52 Timing Configuration .............................................................................................. 11-53 Chip-Select Assertion Timing ............................................................................. 11-54 Chip-Select and Write Enable Deassertion Timing ............................................. 11-55 Relaxed Timing.................................................................................................... 11-56 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xix Contents Paragraph Number 11.5.1.4 11.5.1.5 11.5.1.6 11.5.2 11.5.3 11.5.4 11.6 11.6.1 11.6.1.1 11.6.1.2 11.6.1.3 11.6.1.4 11.6.2 11.6.3 11.6.4 11.6.4.1 11.6.4.1.1 11.6.4.1.2 11.6.4.1.3 11.6.4.1.4 11.6.4.1.5 11.6.4.2 11.6.4.3 11.6.4.4 11.6.4.5 11.6.4.6 11.6.5 11.6.6 11.7 11.7.0.1 11.8 11.8.1 11.8.2 11.9 11.9.1 11.9.2 11.9.3 11.9.4 11.9.5 11.9.5.1 Title Page Number Output Enable (OE) Timing ................................................................................ 11-58 Programmable Wait State Configuration ............................................................. 11-59 Extended Hold Time on Read Accesses .............................................................. 11-59 External Access Termination ................................................................................... 11-61 Boot Chip-Select Operation..................................................................................... 11-62 Differences Between the MPC8xx GPCM and MPC82xx GPCM .......................... 11-63 User-Programmable Machines (UPMs)....................................................................... 11-63 Requests ................................................................................................................... 11-65 Memory Access Requests.................................................................................... 11-66 UPM Refresh Timer Requests ............................................................................. 11-66 Software Requests—run Command .................................................................... 11-67 Exception Requests.............................................................................................. 11-67 Programming the UPMs .......................................................................................... 11-67 Clock Timing ........................................................................................................... 11-68 The RAM Array....................................................................................................... 11-70 RAM Words......................................................................................................... 11-71 Chip-Select Signals (CxTx) ............................................................................. 11-75 Byte-Select Signals (BxTx) ............................................................................. 11-76 General-Purpose Signals (GxTx, GOx) ........................................................... 11-77 Loop Control.................................................................................................... 11-77 Repeat Execution of Current RAM Word (REDO) ........................................ 11-77 Address Multiplexing .......................................................................................... 11-78 Data Valid and Data Sample Control................................................................... 11-78 Signals Negation.................................................................................................. 11-79 The Wait Mechanism ........................................................................................... 11-79 Extended Hold Time on Read Accesses ............................................................. 11-80 UPM DRAM Configuration Example ..................................................................... 11-80 Differences Between the MPC8xx UPM and MPC82xx UPM ............................... 11-81 Memory System Interface Example Using UPM ........................................................ 11-82 EDO Interface Example....................................................................................... 11-93 Handling Devices with Slow or Variable Access Times............................................ 11-101 Hierarchical Bus Interface Example ...................................................................... 11-101 Slow Devices Example .......................................................................................... 11-101 External Master Support (60x-Compatible Mode) .................................................... 11-101 60x-Compatible External Masters (non-MPC8280).............................................. 11-102 MPC8280 External Masters................................................................................... 11-102 Extended Controls in 60x-Compatible Mode ........................................................ 11-102 Address Incrementing for External Bursting Masters ........................................... 11-102 External Masters Timing........................................................................................ 11-103 Example of External Master Using the SDRAM Machine ............................... 11-105 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xx Freescale Semiconductor Contents Paragraph Number Title Chapter 12 Secondary (L2) Cache Support 12.1 12.1.1 12.1.2 12.1.3 12.2 12.3 12.4 12.5 L2 Cache Configurations ............................................................................................... 12-1 Copy-Back Mode....................................................................................................... 12-1 Write-Through Mode ................................................................................................. 12-2 ECC/Parity Mode....................................................................................................... 12-4 L2 Cache Interface Parameters ...................................................................................... 12-6 System Requirements When Using the L2 Cache Interface.......................................... 12-7 L2 Cache Operation ....................................................................................................... 12-7 Timing Example............................................................................................................. 12-7 Chapter 13 IEEE 1149.1 Test Access Port 13.1 13.2 13.3 13.4 13.5 13.6 Overview........................................................................................................................ 13-1 TAP Controller............................................................................................................... 13-2 Boundary Scan Register................................................................................................. 13-3 Instruction Register........................................................................................................ 13-5 MPC8280 Restrictions ................................................................................................... 13-7 Nonscan Chain Operation .............................................................................................. 13-7 Part IV Communications Processor Module Chapter 14 Communications Processor Module Overview 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 Features .......................................................................................................................... 14-1 Serial Configurations ..................................................................................................... 14-3 Communications Processor (CP) ................................................................................... 14-4 CPM Performance Evaluation ................................................................................... 14-4 Features...................................................................................................................... 14-4 CP Block Diagram ..................................................................................................... 14-5 G2_LE Core Interface................................................................................................ 14-7 Peripheral Interface.................................................................................................... 14-7 Execution from RAM ................................................................................................ 14-8 RISC Controller Configuration Register (RCCR) ..................................................... 14-9 RISC Time-Stamp Control Register (RTSCR) ........................................................ 14-10 RISC Time-Stamp Register (RTSR) ........................................................................ 14-11 RISC Microcode Revision Number......................................................................... 14-11 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxi Page Number Contents Paragraph Number 14.4 14.4.1 14.4.1.1 14.4.2 14.4.3 14.5 14.5.1 14.5.2 14.6 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.6.7 14.6.8 14.6.9 14.6.10 Title Page Number Command Set............................................................................................................... 14-12 CP Command Register (CPCR)............................................................................... 14-12 CP Commands ..................................................................................................... 14-14 Command Register Example ................................................................................... 14-17 Command Execution Latency.................................................................................. 14-17 Dual-Port RAM............................................................................................................ 14-17 Buffer Descriptors (BDs)......................................................................................... 14-21 Parameter RAM ....................................................................................................... 14-21 RISC Timer Tables....................................................................................................... 14-23 RISC Timer Table Parameter RAM......................................................................... 14-23 RISC Timer Command Register (TM_CMD) ......................................................... 14-25 RISC Timer Table Entries........................................................................................ 14-25 RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 14-25 set timer Command.................................................................................................. 14-26 RISC Timer Initialization Sequence ........................................................................ 14-26 RISC Timer Initialization Example ......................................................................... 14-27 RISC Timer Interrupt Handling ............................................................................... 14-27 RISC Timer Table Scan Algorithm.......................................................................... 14-27 Using the RISC Timers to Track CP Loading ......................................................... 14-28 Chapter 15 Serial Interface with Time-Slot Assigner 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.5 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.6 15.6.1 15.6.2 Features .......................................................................................................................... 15-3 Overview........................................................................................................................ 15-4 Enabling Connections to TSA ....................................................................................... 15-7 Serial Interface RAM..................................................................................................... 15-8 One Multiplexed Channel with Static Frames ........................................................... 15-9 One Multiplexed Channel with Dynamic Frames ..................................................... 15-9 Programming SIx RAM Entries .............................................................................. 15-10 SIx RAM Programming Example............................................................................ 15-14 Static and Dynamic Routing .................................................................................... 15-15 Serial Interface Registers ............................................................................................. 15-17 SI Global Mode Registers (SIxGMR) ..................................................................... 15-17 SI Mode Registers (SIxMR) .................................................................................... 15-17 SIx RAM Shadow Address Registers (SIxRSR) ..................................................... 15-24 SI Command Register (SIxCMDR)......................................................................... 15-24 SI Status Registers (SIxSTR)................................................................................... 15-25 Serial Interface IDL Interface Support ........................................................................ 15-25 IDL Interface Example ............................................................................................ 15-26 IDL Interface Programming..................................................................................... 15-29 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxii Freescale Semiconductor Contents Paragraph Number 15.7 15.7.1 15.7.2 15.7.2.1 15.7.2.2 Title Page Number Serial Interface GCI Support ....................................................................................... 15-30 SI GCI Activation/Deactivation Procedure ............................................................. 15-32 Serial Interface GCI Programming .......................................................................... 15-32 Normal Mode GCI Programming........................................................................ 15-32 SCIT Programming.............................................................................................. 15-33 Chapter 16 CPM Multiplexing 16.1 16.2 16.3 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 Features .......................................................................................................................... 16-2 Enabling Connections to TSA or NMSI ........................................................................ 16-3 NMSI Configuration ...................................................................................................... 16-4 CMX Registers .............................................................................................................. 16-7 CMX UTOPIA Address Register (CMXUAR) ......................................................... 16-7 CMX SI1 Clock Route Register (CMXSI1CR)....................................................... 16-12 CMX SI2 Clock Route Register (CMXSI2CR)....................................................... 16-13 CMX FCC Clock Route Register (CMXFCR) ........................................................ 16-13 CMX SCC Clock Route Register (CMXSCR) ........................................................ 16-16 CMX SMC Clock Route Register (CMXSMR) ...................................................... 16-19 Chapter 17 Baud-Rate Generators (BRGs) 17.1 17.2 17.3 BRG Configuration Registers 1–8 (BRGCx) ................................................................ 17-2 Autobaud Operation on a UART ................................................................................... 17-4 UART Baud Rate Examples .......................................................................................... 17-5 Chapter 18 Timers 18.1 18.2 18.2.1 18.2.2 18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 Features .......................................................................................................................... 18-1 General-Purpose Timer Units ........................................................................................ 18-2 Cascaded Mode.......................................................................................................... 18-3 Timer Global Configuration Registers (TGCR1 and TGCR2).................................. 18-3 Timer Mode Registers (TMR1–TMR4)..................................................................... 18-5 Timer Reference Registers (TRR1–TRR4) ............................................................... 18-6 Timer Capture Registers (TCR1–TCR4) ................................................................... 18-7 Timer Counters (TCN1–TCN4)................................................................................. 18-7 Timer Event Registers (TER1–TER4)....................................................................... 18-7 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxiii Contents Paragraph Number Title Chapter 19 SDMA Channels and IDMA Emulation 19.1 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.3 19.4 19.5 19.5.1 19.5.1.1 19.5.1.2 19.5.1.3 19.5.2 19.5.2.1 19.5.2.1.1 19.5.2.1.2 19.5.2.2 19.5.2.2.1 19.5.2.2.2 19.5.3 19.5.4 19.6 19.7 19.7.1 19.7.1.1 19.7.1.2 19.7.2 19.8 19.8.1 19.8.2 19.8.2.1 19.8.2.2 19.8.2.3 19.8.3 19.8.4 19.8.5 19.9 SDMA Bus Arbitration and Bus Transfers .................................................................... 19-2 SDMA Registers ............................................................................................................ 19-3 SDMA Status Register (SDSR) ................................................................................. 19-3 SDMA Mask Register (SDMR)................................................................................. 19-4 SDMA Transfer Error Address Registers (PDTEA and LDTEA)............................. 19-4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) ......................... 19-4 IDMA Emulation ........................................................................................................... 19-5 IDMA Features .............................................................................................................. 19-5 IDMA Transfers............................................................................................................. 19-6 Memory-to-Memory Transfers .................................................................................. 19-6 External Request Mode.......................................................................................... 19-8 Normal Mode......................................................................................................... 19-9 Working with a PCI Bus ........................................................................................ 19-9 Memory to/from Peripheral Transfers ....................................................................... 19-9 Dual-Address Transfers ....................................................................................... 19-10 Peripheral to Memory ...................................................................................... 19-10 Memory to Peripheral ...................................................................................... 19-10 Single Address (Fly-By) Transfers ...................................................................... 19-10 Peripheral-to-Memory Fly-By Transfers ......................................................... 19-11 Memory-to-Peripheral Fly-By Transfers ......................................................... 19-11 Controlling 60x Bus Bandwidth .............................................................................. 19-11 PCI Burst Length and Latency Control ................................................................... 19-12 IDMA Priorities ........................................................................................................... 19-12 IDMA Interface Signals............................................................................................... 19-13 DREQx and DACKx ............................................................................................... 19-13 Level-Sensitive Mode.......................................................................................... 19-14 Edge-Sensitive Mode........................................................................................... 19-14 DONEx .................................................................................................................... 19-14 IDMA Operation.......................................................................................................... 19-14 Auto Buffer and Buffer Chaining ............................................................................ 19-15 IDMAx Parameter RAM ......................................................................................... 19-16 DMA Channel Mode (DCM)............................................................................... 19-18 Data Transfer Types as Programmed in DCM..................................................... 19-20 Programming DTS and STS ................................................................................ 19-20 IDMA Performance ................................................................................................. 19-22 IDMA Event Register (IDSR) and Mask Register (IDMR) .................................... 19-22 IDMA BDs............................................................................................................... 19-23 IDMA Commands........................................................................................................ 19-26 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxiv Freescale Semiconductor Page Number Contents Paragraph Number 19.9.1 19.9.2 19.10 19.10.1 19.11 19.12 19.12.1 19.12.2 19.12.3 Title Page Number start_idma Command............................................................................................... 19-26 stop_idma Command ............................................................................................... 19-26 IDMA Bus Exceptions................................................................................................. 19-27 Externally Recognizing IDMA Operand Transfers ................................................. 19-27 Programming the Parallel I/O Registers ...................................................................... 19-28 IDMA Programming Examples ................................................................................... 19-29 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2 ............................ 19-29 Memory-to-Peripheral Fly-By Mode—IDMA3 ...................................................... 19-30 Memory-to-Memory (PCI Bus to 60x Bus)—IDMA1 ............................................ 19-32 Chapter 20 Serial Communications Controllers (SCCs) 20.1 20.1.1 20.1.2 20.1.3 20.1.4 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.5.1 20.3.5.2 20.3.6 20.3.6.1 20.3.7 20.3.7.1 20.3.7.2 20.3.7.3 20.3.7.4 20.3.7.5 20.3.8 Features .......................................................................................................................... 20-2 The General SCC Mode Registers (GSMR1–GSMR4) ............................................ 20-3 Protocol-Specific Mode Register (PSMR) ................................................................ 20-9 Data Synchronization Register (DSR)....................................................................... 20-9 Transmit-on-Demand Register (TODR) .................................................................. 20-10 SCC Buffer Descriptors (BDs) .................................................................................... 20-10 SCC Parameter RAM................................................................................................... 20-13 SCC Base Addresses................................................................................................ 20-14 Function Code Registers (RFCR and TFCR) .......................................................... 20-15 Handling SCC Interrupts ......................................................................................... 20-16 Initializing the SCCs................................................................................................ 20-16 Controlling SCC Timing with RTS, CTS, and CD.................................................. 20-17 Synchronous Protocols ........................................................................................ 20-17 Asynchronous Protocols ...................................................................................... 20-20 Digital Phase-Locked Loop (DPLL) Operation....................................................... 20-21 Encoding Data with a DPLL................................................................................ 20-23 Reconfiguring the SCCs .......................................................................................... 20-24 General Reconfiguration Sequence for an SCC Transmitter............................... 20-24 Reset Sequence for an SCC Transmitter.............................................................. 20-25 General Reconfiguration Sequence for an SCC Receiver ................................... 20-25 Reset Sequence for an SCC Receiver.................................................................. 20-25 Switching Protocols ............................................................................................. 20-25 Saving Power ........................................................................................................... 20-25 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxv Contents Paragraph Number Title Chapter 21 SCC UART Mode 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13 21.14 21.15 21.16 21.17 21.18 21.19 21.20 21.21 21.22 Features .......................................................................................................................... 21-2 Normal Asynchronous Mode......................................................................................... 21-2 Synchronous Mode ........................................................................................................ 21-3 SCC UART Parameter RAM ......................................................................................... 21-3 Data-Handling Methods: Character- or Message-Based ............................................... 21-5 Error and Status Reporting............................................................................................. 21-5 SCC UART Commands ................................................................................................. 21-6 Multidrop Systems and Address Recognition ............................................................... 21-7 Receiving Control Characters ........................................................................................ 21-7 Hunt Mode (Receiver) ................................................................................................... 21-9 Inserting Control Characters into the Transmit Data Stream......................................... 21-9 Sending a Break (Transmitter)..................................................................................... 21-10 Sending a Preamble (Transmitter) ............................................................................... 21-10 Fractional Stop Bits (Transmitter) ............................................................................... 21-11 Handling Errors in the SCC UART Controller ............................................................ 21-12 UART Mode Register (PSMR).................................................................................... 21-13 SCC UART Receive Buffer Descriptor (RxBD) ......................................................... 21-15 SCC UART Transmit Buffer Descriptor (TxBD) ........................................................ 21-18 SCC UART Event Register (SCCE) and Mask Register (SCCM) .............................. 21-19 SCC UART Status Register (SCCS)............................................................................ 21-21 SCC UART Programming Example ............................................................................ 21-22 S-Records Loader Application..................................................................................... 21-23 Chapter 22 SCC HDLC Mode 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 SCC HDLC Features ..................................................................................................... 22-1 SCC HDLC Channel Frame Transmission .................................................................... 22-2 SCC HDLC Channel Frame Reception ......................................................................... 22-2 SCC HDLC Parameter RAM......................................................................................... 22-3 Programming the SCC in HDLC Mode......................................................................... 22-5 SCC HDLC Commands................................................................................................. 22-5 Handling Errors in the SCC HDLC Controller.............................................................. 22-6 HDLC Mode Register (PSMR)...................................................................................... 22-7 SCC HDLC Receive Buffer Descriptor (RxBD) ........................................................... 22-8 SCC HDLC Transmit Buffer Descriptor (TxBD)........................................................ 22-12 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ................................. 22-13 SCC HDLC Status Register (SCCS)............................................................................ 22-15 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxvi Freescale Semiconductor Page Number Contents Paragraph Number 22.13 22.13.1 22.13.2 22.14 22.14.1 22.14.2 22.14.3 22.14.4 22.14.5 22.14.6 22.14.6.1 22.14.6.2 Title Page Number SCC HDLC Programming Examples .......................................................................... 22-16 SCC HDLC Programming Example #1................................................................... 22-16 SCC HDLC Programming Example #2................................................................... 22-18 HDLC Bus Mode with Collision Detection................................................................. 22-18 HDLC Bus Features................................................................................................. 22-20 Accessing the HDLC Bus ........................................................................................ 22-20 Increasing Performance ........................................................................................... 22-21 Delayed RTS Mode.................................................................................................. 22-22 Using the Time-Slot Assigner (TSA) ...................................................................... 22-23 HDLC Bus Protocol Programming.......................................................................... 22-23 Programming GSMR and PSMR for the HDLC Bus Protocol ........................... 22-23 HDLC Bus Controller Programming Example.................................................... 22-24 Chapter 23 SCC BISYNC Mode 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.14 23.15 23.16 23.17 Features .......................................................................................................................... 23-2 SCC BISYNC Channel Frame Transmission ................................................................ 23-2 SCC BISYNC Channel Frame Reception ..................................................................... 23-3 SCC BISYNC Parameter RAM ..................................................................................... 23-3 SCC BISYNC Commands ............................................................................................. 23-4 SCC BISYNC Control Character Recognition.............................................................. 23-5 BISYNC SYNC Register (BSYNC).............................................................................. 23-7 SCC BISYNC DLE Register (BDLE) ........................................................................... 23-8 Sending and Receiving the Synchronization Sequence ................................................. 23-9 Handling Errors in the SCC BISYNC ........................................................................... 23-9 BISYNC Mode Register (PSMR)................................................................................ 23-10 SCC BISYNC Receive BD (RxBD) ............................................................................ 23-12 SCC BISYNC Transmit BD (TxBD)........................................................................... 23-14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).......................... 23-15 SCC Status Registers (SCCS)...................................................................................... 23-16 Programming the SCC BISYNC Controller ................................................................ 23-17 SCC BISYNC Programming Example ........................................................................ 23-18 Chapter 24 SCC Transparent Mode 24.1 24.2 24.3 24.4 Features .......................................................................................................................... 24-1 SCC Transparent Channel Frame Transmission Process............................................... 24-2 SCC Transparent Channel Frame Reception Process .................................................... 24-2 Achieving Synchronization in Transparent Mode ......................................................... 24-3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxvii Contents Paragraph Number 24.4.1 24.4.1.1 24.4.1.2 24.4.1.2.1 24.4.1.3 24.4.2 24.4.2.1 24.4.2.2 24.4.3 24.5 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13 24.14 Title Page Number Synchronization in NMSI Mode................................................................................ 24-3 In-Line Synchronization Pattern............................................................................ 24-3 External Synchronization Signals.......................................................................... 24-3 External Synchronization Example ................................................................... 24-4 Transparent Mode without Explicit Synchronization............................................ 24-5 Synchronization and the TSA .................................................................................... 24-5 Inline Synchronization Pattern .............................................................................. 24-5 Inherent Synchronization....................................................................................... 24-5 End of Frame Detection............................................................................................. 24-5 CRC Calculation in Transparent Mode.......................................................................... 24-6 SCC Transparent Parameter RAM................................................................................. 24-6 SCC Transparent Commands......................................................................................... 24-6 Handling Errors in the Transparent Controller .............................................................. 24-7 Transparent Mode and the PSMR.................................................................................. 24-8 SCC Transparent Receive Buffer Descriptor (RxBD) ................................................... 24-8 SCC Transparent Transmit Buffer Descriptor (TxBD)................................................ 24-10 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)............................. 24-11 SCC Status Register in Transparent Mode (SCCS) ..................................................... 24-12 SCC2 Transparent Programming Example.................................................................. 24-13 Chapter 25 SCC Ethernet Mode 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.10 25.11 25.12 25.13 25.14 25.15 25.16 25.17 25.18 Ethernet on the MPC8280.............................................................................................. 25-1 Features .......................................................................................................................... 25-2 Connecting the MPC8280 to Ethernet ........................................................................... 25-4 SCC Ethernet Channel Frame Transmission ................................................................. 25-5 SCC Ethernet Channel Frame Reception....................................................................... 25-6 The Content-Addressable Memory (CAM) Interface.................................................... 25-6 SCC Ethernet Parameter RAM ...................................................................................... 25-7 Programming the Ethernet Controller............................................................................ 25-9 SCC Ethernet Commands .............................................................................................. 25-9 SCC Ethernet Address Recognition............................................................................. 25-11 Hash Table Algorithm.................................................................................................. 25-12 Interpacket Gap Time................................................................................................... 25-12 Handling Collisions ..................................................................................................... 25-12 Internal and External Loopback................................................................................... 25-13 Full-Duplex Ethernet Support...................................................................................... 25-13 Handling Errors in the Ethernet Controller.................................................................. 25-13 Ethernet Mode Register (PSMR) ................................................................................. 25-14 SCC Ethernet Receive BD ........................................................................................... 25-16 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxviii Freescale Semiconductor Contents Paragraph Number 25.19 25.20 25.21 Title Page Number SCC Ethernet Transmit Buffer Descriptor................................................................... 25-18 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) .................................. 25-20 SCC Ethernet Programming Example ......................................................................... 25-22 Chapter 26 SCC AppleTalk Mode 26.1 26.2 26.3 26.4 26.4.1 26.4.2 26.4.3 26.4.4 Operating the LocalTalk Bus ......................................................................................... 26-1 Features .......................................................................................................................... 26-2 Connecting to AppleTalk ............................................................................................... 26-2 Programming the SCC in AppleTalk Mode................................................................... 26-3 Programming the GSMR ........................................................................................... 26-3 Programming the PSMR............................................................................................ 26-4 Programming the TODR............................................................................................ 26-4 SCC AppleTalk Programming Example.................................................................... 26-4 Chapter 27 Universal Serial Bus Controller 27.1 27.2 27.2.1 27.3 27.3.1 27.4 27.4.1 27.5 27.5.1 27.5.1.1 27.5.1.2 27.5.2 27.5.3 27.5.4 27.5.5 27.5.6 27.5.7 27.5.7.1 27.5.7.2 27.5.7.3 27.5.7.4 27.5.7.5 USB Integration in the MPC8280.................................................................................. 27-1 Overview........................................................................................................................ 27-1 USB Controller Key Features .................................................................................... 27-2 Host Controller Limitations ........................................................................................... 27-2 USB Controller Pin Functions and Clocking............................................................. 27-2 USB Function Description............................................................................................. 27-4 USB Function Controller Transmit/Receive.............................................................. 27-5 USB Host Description ................................................................................................... 27-7 USB Host Controller Transmit/Receive .................................................................... 27-8 Packet-Level Interface ........................................................................................... 27-9 Transaction-Level Interface ................................................................................... 27-9 SOF Transmission for USB Host Controller ........................................................... 27-12 USB Function and Host Parameter RAM Memory Map......................................... 27-12 Endpoint Parameters Block Pointer (EPxPTR) ....................................................... 27-13 Frame Number (FRAME_N)................................................................................... 27-15 USB Function Code Registers (RFCR and TFCR) ................................................. 27-16 USB Function Programming Model ........................................................................ 27-17 USB Mode Register (USMOD)........................................................................... 27-17 USB Slave Address Register (USADR) .............................................................. 27-18 USB Endpoint Registers (USEP1–USEP4)......................................................... 27-18 USB Command Register (USCOM).................................................................... 27-20 USB Event Register (USBER) ............................................................................ 27-20 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxix Contents Paragraph Number 27.5.7.6 27.5.7.7 27.5.7.8 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.7 27.7.1 27.7.2 27.8 27.9 27.10 27.10.1 27.11 27.11.1 Title Page Number USB Mask Register (USBMR)............................................................................ 27-21 USB Status Register (USBS)............................................................................... 27-21 USB Start of Frame Timer (USSFT) ................................................................... 27-22 USB Buffer Descriptor Ring........................................................................................ 27-22 USB Receive Buffer Descriptor (Rx BD) for Host and Function ........................... 27-24 USB Transmit Buffer Descriptor (Tx BD) for Function.......................................... 27-26 USB Transmit Buffer Descriptor (Tx BD) for Host ................................................ 27-27 USB Transaction Buffer Descriptor (TrBD) for Host.............................................. 27-29 USB CP Commands..................................................................................................... 27-32 STOP Tx Command................................................................................................. 27-32 RESTART Tx Command ......................................................................................... 27-33 USB Controller Errors ................................................................................................. 27-33 USB Function Controller Initialization Example ........................................................ 27-34 Programming the USB Host Controller (Packet-Level) .............................................. 27-35 USB Host Controller Initialization Example ........................................................... 27-35 Programming the USB Host Controller (Transaction-Level) ...................................... 27-37 USB Host Controller Initialization Example ........................................................... 27-37 Chapter 28 Serial Management Controllers (SMCs) 28.1 28.2 28.2.1 28.2.2 28.2.3 28.2.3.1 28.2.4 28.2.4.1 28.2.4.2 28.2.4.3 28.2.4.4 28.2.4.5 28.2.5 28.2.6 28.3 28.3.1 28.3.2 28.3.3 28.3.4 28.3.5 Features .......................................................................................................................... 28-2 Common SMC Settings and Configurations ................................................................. 28-2 SMC Mode Registers (SMCMR1/SMCMR2)........................................................... 28-2 SMC Buffer Descriptor Operation............................................................................. 28-4 SMC Parameter RAM................................................................................................ 28-5 SMC Function Code Registers (RFCR/TFCR) ..................................................... 28-8 Disabling SMCs On-the-Fly ...................................................................................... 28-8 SMC Transmitter Full Sequence............................................................................ 28-9 SMC Transmitter Shortcut Sequence .................................................................... 28-9 SMC Receiver Full Sequence................................................................................ 28-9 SMC Receiver Shortcut Sequence......................................................................... 28-9 Switching Protocols ............................................................................................... 28-9 Saving Power ........................................................................................................... 28-10 Handling Interrupts in the SMC............................................................................... 28-10 SMC in UART Mode ................................................................................................... 28-10 Features.................................................................................................................... 28-11 SMC UART Channel Transmission Process ........................................................... 28-11 SMC UART Channel Reception Process................................................................. 28-11 Programming the SMC UART Controller ............................................................... 28-11 SMC UART Transmit and Receive Commands ...................................................... 28-12 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxx Freescale Semiconductor Contents Paragraph Number 28.3.6 28.3.7 28.3.8 28.3.9 28.3.10 28.3.11 28.3.12 28.4 28.4.1 28.4.2 28.4.3 28.4.4 28.4.5 28.4.6 28.4.7 28.4.8 28.4.9 28.4.10 28.4.11 28.5 28.5.1 28.5.2 28.5.2.1 28.5.2.2 28.5.3 28.5.3.1 28.5.3.2 28.5.4 28.5.5 28.5.6 28.5.7 28.5.8 28.5.9 Title Page Number Sending a Break ....................................................................................................... 28-12 Sending a Preamble ................................................................................................. 28-13 Handling Errors in the SMC UART Controller ....................................................... 28-13 SMC UART RxBD .................................................................................................. 28-14 SMC UART TxBD .................................................................................................. 28-17 SMC UART Event Register (SMCE)/Mask Register (SMCM) .............................. 28-18 SMC UART Controller Programming Example...................................................... 28-19 SMC in Transparent Mode........................................................................................... 28-20 Features.................................................................................................................... 28-20 SMC Transparent Channel Transmission Process ................................................... 28-21 SMC Transparent Channel Reception Process ........................................................ 28-21 Using SMSYN for Synchronization ........................................................................ 28-22 Using the Time-Slot Assigner (TSA) for Synchronization...................................... 28-23 SMC Transparent Commands.................................................................................. 28-25 Handling Errors in the SMC Transparent Controller............................................... 28-25 SMC Transparent RxBD.......................................................................................... 28-26 SMC Transparent TxBD .......................................................................................... 28-27 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)...................... 28-28 SMC Transparent NMSI Programming Example.................................................... 28-29 The SMC in GCI Mode ............................................................................................... 28-30 SMC GCI Parameter RAM...................................................................................... 28-30 Handling the GCI Monitor Channel ........................................................................ 28-31 SMC GCI Monitor Channel Transmission Process ............................................. 28-31 SMC GCI Monitor Channel Reception Process .................................................. 28-31 Handling the GCI C/I Channel ................................................................................ 28-31 SMC GCI C/I Channel Transmission Process ..................................................... 28-31 SMC GCI C/I Channel Reception Process .......................................................... 28-32 SMC GCI Commands.............................................................................................. 28-32 SMC GCI Monitor Channel RxBD ......................................................................... 28-32 SMC GCI Monitor Channel TxBD.......................................................................... 28-33 SMC GCI C/I Channel RxBD ................................................................................. 28-33 SMC GCI C/I Channel TxBD.................................................................................. 28-34 SMC GCI Event Register (SMCE)/Mask Register (SMCM).................................. 28-34 Chapter 29 Multi-Channel Controllers (MCCs) 29.1 29.1.1 29.2 29.3 MCC Operation Overview............................................................................................. 29-2 MCC Data Structure Organization............................................................................. 29-2 Global MCC Parameters ................................................................................................ 29-4 Channel-Specific Parameters ......................................................................................... 29-5 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxxi Contents Paragraph Number 29.3.1 29.3.1.1 29.3.1.2 29.3.1.3 29.3.1.4 29.3.2 29.3.2.1 29.3.2.2 29.3.2.3 29.3.2.4 29.3.3 29.3.3.1 29.3.3.1.1 29.3.3.2 29.3.4 29.3.4.1 29.3.4.2 29.3.4.2.1 29.3.4.3 29.3.4.3.1 29.3.4.3.2 29.3.4.3.3 29.3.4.4 29.3.4.4.1 29.3.4.4.2 29.3.4.4.3 29.3.4.4.4 29.3.4.5 29.4 29.5 29.5.1 29.5.2 29.5.3 29.5.4 29.6 29.7 29.8 29.8.1 29.8.1.1 29.8.1.2 Title Page Number Channel-Specific HDLC Parameters ......................................................................... 29-5 Internal Transmitter State (TSTATE)—HDLC Mode ........................................... 29-7 Interrupt Mask (INTMSK)—HDLC Mode ........................................................... 29-8 Channel Mode Register (CHAMR)—HDLC Mode.............................................. 29-8 Internal Receiver State (RSTATE)—HDLC Mode ............................................. 29-10 Channel-Specific Transparent Parameters ............................................................... 29-11 Internal Transmitter State (TSTATE)—Transparent Mode ................................. 29-12 Interrupt Mask (INTMSK)—Transparent Mode ................................................. 29-12 Channel Mode Register (CHAMR)—Transparent Mode.................................... 29-12 Internal Receiver State (RSTATE)—Transparent Mode ..................................... 29-14 MCC Parameters for AAL1 CES Usage.................................................................. 29-14 Channel-Specific Parameters—AAL1 CES ........................................................ 29-14 Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES............................................................................ 29-15 Channel Mode Register (CHAMR)—AAL1 CES .............................................. 29-15 Channel-Specific SS7 Parameters ........................................................................... 29-17 Extended Channel Mode Register (ECHAMR)—SS7 Mode.............................. 29-20 Signal Unit Error Monitor (SUERM)—SS7 Mode ............................................. 29-22 SUERM in Japanese SS7................................................................................. 29-23 SS7 Configuration Register—SS7 Mode ............................................................ 29-23 AERM Implementation ................................................................................... 29-24 AERM in Japanese SS7................................................................................... 29-24 Disabling SUERM ........................................................................................... 29-25 SU Filtering—SS7 Mode..................................................................................... 29-25 Comparison Mask............................................................................................ 29-25 Comparison State Machine.............................................................................. 29-25 Filtering Limitations ........................................................................................ 29-26 Resetting the SU Filtering Mechanism............................................................ 29-26 Octet Counting Mode—SS7 Mode...................................................................... 29-27 Channel Extra Parameters............................................................................................ 29-27 Superchannels .............................................................................................................. 29-28 Superchannel Table.................................................................................................. 29-28 Superchannels and Receiving .................................................................................. 29-29 Transparent Slot Synchronization............................................................................ 29-29 Superchannelling Programming Examples.............................................................. 29-29 MCC Configuration Registers (MCCFx) .................................................................... 29-32 MCC Commands ......................................................................................................... 29-33 MCC Exceptions.......................................................................................................... 29-34 MCC Event Register (MCCE)/Mask Register (MCCM) ........................................ 29-36 Interrupt Circular Table Entry ............................................................................. 29-37 Global Transmitter Underrun (GUN) .................................................................. 29-38 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxxii Freescale Semiconductor Contents Paragraph Number 29.8.1.2.1 29.8.1.2.2 29.8.1.2.3 29.8.1.2.4 29.8.1.2.5 29.8.1.2.6 29.8.1.2.7 29.8.1.3 29.8.1.4 29.9 29.9.1 29.9.2 29.10 29.10.1 29.10.2 29.11 Title Page Number TDM Clock...................................................................................................... 29-39 Synchronization Pulse ..................................................................................... 29-39 SIRAM Programming...................................................................................... 29-39 MCC Initialization........................................................................................... 29-40 CPM Bandwidth .............................................................................................. 29-40 CPM Priority.................................................................................................... 29-40 Bus Latency ..................................................................................................... 29-41 Recovery from GUN Errors................................................................................. 29-41 Global Overrun (GOV)........................................................................................ 29-41 MCC Buffer Descriptors.............................................................................................. 29-41 Receive Buffer Descriptor (RxBD) ......................................................................... 29-42 Transmit Buffer Descriptor (TxBD) ........................................................................ 29-44 MCC Initialization and Start/Stop Sequence ............................................................... 29-46 Stopping and Restarting a Single-Channel .............................................................. 29-47 Stopping and Restarting a Superchannel ................................................................. 29-47 MCC Latency and Performance .................................................................................. 29-48 Chapter 30 Fast Communications Controllers (FCCs) 30.1 30.2 30.2.1 30.3 30.4 30.5 30.6 30.7 30.7.1 30.8 30.8.1 30.8.2 30.8.3 30.9 30.10 30.10.1 30.10.1.1 30.10.1.2 30.10.1.3 30.11 30.12 Overview........................................................................................................................ 30-1 General FCC Mode Registers (GFMRx) ....................................................................... 30-3 General FCC Expansion Mode Register (GFEMR) .................................................. 30-7 FCC Protocol-Specific Mode Registers (FPSMRx) ...................................................... 30-8 FCC Data Synchronization Registers (FDSRx)............................................................. 30-8 FCC Transmit-on-Demand Registers (FTODRx).......................................................... 30-9 FCC Buffer Descriptors ............................................................................................... 30-10 FCC Parameter RAM................................................................................................... 30-12 FCC Function Code Registers (FCRx) .................................................................... 30-14 Interrupts from the FCCs ............................................................................................. 30-14 FCC Event Registers (FCCEx) ................................................................................ 30-15 FCC Mask Registers (FCCMx) ............................................................................... 30-15 FCC Status Registers (FCCSx)................................................................................ 30-15 FCC Initialization ........................................................................................................ 30-15 FCC Interrupt Handling ............................................................................................... 30-16 FCC Transmit Errors................................................................................................ 30-16 Re-Initialization Procedure.................................................................................. 30-17 Recovery Sequence.............................................................................................. 30-17 Adjusting Transmitter BD Handling.................................................................... 30-17 FCC Timing Control .................................................................................................... 30-17 Disabling the FCCs On-the-Fly ................................................................................... 30-20 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxxiii Contents Paragraph Number 30.12.1 30.12.2 30.12.3 30.12.4 30.12.5 30.13 Title Page Number FCC Transmitter Full Sequence............................................................................... 30-21 FCC Transmitter Shortcut Sequence ....................................................................... 30-21 FCC Receiver Full Sequence................................................................................... 30-21 FCC Receiver Shortcut Sequence............................................................................ 30-21 Switching Protocols ................................................................................................. 30-22 Saving Power ............................................................................................................... 30-22 Chapter 31 ATM Controller and AAL0, AAL1, and AAL5 31.1 31.2 31.2.1 31.2.1.1 31.2.1.2 31.2.1.2.1 31.2.1.3 31.2.1.4 31.2.1.5 31.2.2 31.2.2.1 31.2.2.2 31.2.2.2.1 31.2.2.3 31.2.2.4 31.2.3 31.2.4 31.3 31.3.1 31.3.2 31.3.3 31.3.3.1 31.3.3.2 31.3.4 31.3.5 31.3.5.1 31.3.5.2 31.3.5.3 31.3.5.3.1 31.3.5.3.2 Features .......................................................................................................................... 31-1 ATM Controller Overview............................................................................................. 31-5 Transmitter Overview ................................................................................................ 31-5 AAL5 Transmitter Overview................................................................................. 31-5 AAL1 Transmitter Overview................................................................................. 31-5 AAL1 CES Transmitter Overview .................................................................... 31-6 AAL0 Transmitter Overview................................................................................. 31-6 AAL2 Transmitter Overview................................................................................. 31-6 Transmit External Rate and Internal Rate Modes.................................................. 31-6 Receiver Overview .................................................................................................... 31-6 AAL5 Receiver Overview ..................................................................................... 31-7 AAL1 Receiver Overview ..................................................................................... 31-7 AAL1 CES Receiver Overview......................................................................... 31-8 AAL0 Receiver Overview ..................................................................................... 31-8 AAL2 Receiver Overview ..................................................................................... 31-8 Performance Monitoring............................................................................................ 31-8 ABR Flow Control..................................................................................................... 31-8 ATM Pace Control (APC) Unit...................................................................................... 31-8 APC Modes and ATM Service Types ........................................................................ 31-8 APC Unit Scheduling Mechanism ............................................................................. 31-9 Determining the Scheduling Table Size................................................................... 31-10 Determining the Cells Per Slot (CPS) in a Scheduling Table.............................. 31-10 Determining the Number of Slots in a Scheduling Table .................................... 31-10 Determining the Time-Slot Scheduling Rate of a Channel ..................................... 31-11 ATM Traffic Type .................................................................................................... 31-11 Peak Cell Rate Traffic Type................................................................................. 31-11 Determining the PCR Traffic Type Parameters ................................................... 31-11 Peak and Sustain Traffic Type (VBR) ................................................................. 31-12 Example for Using VBR Traffic Parameters ................................................... 31-12 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2 .......................... 31-13 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxxiv Freescale Semiconductor Contents Paragraph Number 31.3.5.4 31.3.6 31.4 31.4.1 31.4.2 31.4.2.1 31.4.2.2 31.4.3 31.4.4 31.5 31.5.1 31.5.1.1 31.5.1.2 31.5.1.3 31.5.2 31.5.2.1 31.5.3 31.6 31.6.1 31.6.2 31.6.3 31.6.4 31.6.5 31.6.6 31.6.6.1 31.6.6.2 31.6.6.3 31.6.6.4 31.7 31.7.1 31.8 31.9 31.9.1 31.9.2 31.9.3 31.9.4 31.9.5 31.9.6 31.9.7 31.9.8 31.10 Title Page Number Peak and Minimum Cell Rate Traffic Type (UBR+)........................................... 31-13 Determining the Priority of an ATM Channel ......................................................... 31-13 VCI/VPI Address Lookup Mechanism........................................................................ 31-13 External CAM Lookup ............................................................................................ 31-14 Address Compression .............................................................................................. 31-15 VP-Level Address Compression Table (VPLT) .................................................. 31-16 VC-Level Address Compression Tables (VCLTs)............................................... 31-17 Misinserted Cells ..................................................................................................... 31-18 Receive Raw Cell Queue ......................................................................................... 31-18 Available Bit Rate (ABR) Flow Control...................................................................... 31-19 The ABR Model....................................................................................................... 31-20 ABR Flow Control Source End-System Behavior .............................................. 31-20 ABR Flow Control Destination End-System Behavior ....................................... 31-21 ABR Flowcharts .................................................................................................. 31-21 RM Cell Structure.................................................................................................... 31-26 RM Cell Rate Representation .............................................................................. 31-26 ABR Flow Control Setup......................................................................................... 31-27 OAM Support .............................................................................................................. 31-27 ATM-Layer OAM Definitions ................................................................................. 31-27 Virtual Path (F4) Flow Mechanism ......................................................................... 31-28 Virtual Channel (F5) Flow Mechanism ................................................................... 31-28 Receiving OAM F4 or F5 Cells............................................................................... 31-28 Transmitting OAM F4 or F5 Cells........................................................................... 31-28 Performance Monitoring.......................................................................................... 31-29 Running a Performance Block Test ..................................................................... 31-30 PM Block Monitoring.......................................................................................... 31-30 PM Block Generation .......................................................................................... 31-31 BRC Performance Calculations........................................................................... 31-32 User-Defined Cells (UDC) .......................................................................................... 31-32 UDC Extended Address Mode (UEAD).................................................................. 31-32 ATM Layer Statistics ................................................................................................... 31-33 ATM-to-TDM Interworking ........................................................................................ 31-33 Automatic Data Forwarding .................................................................................... 31-33 Using Interrupts in Automatic Data Forwarding ..................................................... 31-34 Timing Issues ........................................................................................................... 31-35 Clock Synchronization (SRTS and Adaptive FIFOs) .............................................. 31-35 Mapping TDM Time Slots to VCs........................................................................... 31-35 CAS Support ............................................................................................................ 31-35 Trunk Condition....................................................................................................... 31-36 ATM-to-ATM Data Forwarding............................................................................... 31-36 ATM Memory Structure............................................................................................... 31-36 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxxv Contents Paragraph Number 31.10.1 31.10.1.1 31.10.1.2 31.10.1.3 31.10.2 31.10.2.1 31.10.2.2 31.10.2.2.1 31.10.2.2.2 31.10.2.2.3 31.10.2.2.4 31.10.2.2.5 31.10.2.2.6 31.10.2.3 31.10.2.3.1 31.10.2.3.2 31.10.2.3.3 31.10.2.3.4 31.10.2.3.5 31.10.2.3.6 31.10.2.3.7 31.10.2.3.8 31.10.3 31.10.4 31.10.4.1 31.10.4.2 31.10.4.3 31.10.5 31.10.5.1 31.10.5.2 31.10.5.2.1 31.10.5.2.2 31.10.5.2.3 31.10.5.2.4 31.10.5.3 31.10.5.4 31.10.5.5 31.10.5.6 31.10.5.7 31.10.5.8 31.10.5.9 Title Page Number Parameter RAM ....................................................................................................... 31-36 Determining UEAD_OFFSET (UEAD Mode Only) .......................................... 31-39 VCI Filtering (VCIF) ........................................................................................... 31-39 Global Mode Entry (GMODE)............................................................................ 31-40 Connection Tables (RCT, TCT, and TCTE) ............................................................ 31-41 ATM Channel Code ............................................................................................. 31-41 Receive Connection Table (RCT)........................................................................ 31-43 AAL5 Protocol-Specific RCT ......................................................................... 31-46 AAL5-ABR Protocol-Specific RCT................................................................ 31-47 AAL1 Protocol-Specific RCT ......................................................................... 31-47 AAL0 Protocol-Specific RCT ......................................................................... 31-49 AAL1 CES Protocol-Specific RCT ................................................................. 31-50 AAL2 Protocol-Specific RCT ......................................................................... 31-50 Transmit Connection Table (TCT)....................................................................... 31-50 AAL5 Protocol-Specific TCT ......................................................................... 31-53 AAL1 Protocol-Specific TCT ......................................................................... 31-54 AAL0 Protocol-Specific TCT ......................................................................... 31-55 AAL1 CES Protocol-Specific TCT ................................................................. 31-55 AAL2 Protocol-Specific TCT ......................................................................... 31-55 VBR Protocol-Specific TCTE ......................................................................... 31-56 UBR+ Protocol-Specific TCTE....................................................................... 31-57 ABR Protocol-Specific TCTE ......................................................................... 31-57 OAM Performance Monitoring Tables .................................................................... 31-60 APC Data Structure ................................................................................................. 31-61 APC Parameter Tables ......................................................................................... 31-62 APC Priority Table .............................................................................................. 31-63 APC Scheduling Tables ....................................................................................... 31-63 ATM Controller Buffer Descriptors (BDs) .............................................................. 31-64 Transmit Buffer Operation................................................................................... 31-64 Receive Buffer Operation .................................................................................... 31-65 Static Buffer Allocation ................................................................................... 31-65 Global Buffer Allocation ................................................................................. 31-66 Free Buffer Pools............................................................................................. 31-67 Free Buffer Pool Parameter Tables.................................................................. 31-68 ATM Controller Buffers....................................................................................... 31-69 AAL5 RxBD........................................................................................................ 31-69 AAL1 RxBD........................................................................................................ 31-71 AAL0 RxBD........................................................................................................ 31-72 AAL1 CES RxBD................................................................................................ 31-73 AAL2 RxBD........................................................................................................ 31-73 AAL5, AAL1 CES User-Defined Cell—RxBD Extension ................................. 31-73 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxxvi Freescale Semiconductor Contents Paragraph Number 31.10.5.10 31.10.5.11 31.10.5.12 31.10.5.13 31.10.5.14 31.10.5.15 31.10.6 31.10.7 31.11 31.11.1 31.11.2 31.11.3 31.12 31.12.1 31.12.1.1 31.12.2 31.12.2.1 31.12.2.2 31.12.2.3 31.12.3 31.13 31.13.1 31.13.2 31.13.3 31.14 31.15 31.15.1 31.15.1.1 31.15.1.2 31.15.1.3 31.15.1.4 31.15.1.5 31.15.1.6 31.16 31.17 31.17.1 31.17.2 31.17.3 Title Page Number AAL5 TxBDs....................................................................................................... 31-74 AAL1 TxBDs....................................................................................................... 31-75 AAL0 TxBDs....................................................................................................... 31-76 AAL1 CES TxBDs .............................................................................................. 31-77 AAL2 TxBDs....................................................................................................... 31-77 AAL5, AAL1 User-Defined Cell—TxBD Extension.......................................... 31-77 AAL1 Sequence Number (SN) Protection Table..................................................... 31-77 UNI Statistics Table ................................................................................................. 31-78 ATM Exceptions .......................................................................................................... 31-79 Interrupt Queues ...................................................................................................... 31-79 Interrupt Queue Entry .............................................................................................. 31-80 Interrupt Queue Parameter Tables ........................................................................... 31-80 The UTOPIA Interface ................................................................................................ 31-81 UTOPIA Interface Master Mode ............................................................................. 31-81 UTOPIA Master Multiple PHY Operation.......................................................... 31-82 UTOPIA Interface Slave Mode ............................................................................... 31-83 UTOPIA Slave Multiple PHY Operation ............................................................ 31-84 UTOPIA Clocking Modes ................................................................................... 31-84 UTOPIA Loop-Back Modes................................................................................ 31-84 Extended Number of PHYs ..................................................................................... 31-85 ATM Registers ............................................................................................................. 31-85 General FCC Mode Register (GFMR)..................................................................... 31-85 FCC Protocol-Specific Mode Register (FPSMR).................................................... 31-85 ATM Event Register (FCCE)/Mask Register (FCCM)............................................ 31-88 ATM Transmit Command ............................................................................................ 31-89 Transmission Rate Modes—External, Internal, and Expanded Internal...................... 31-90 FCC Transmit Internal Rate Mode .......................................................................... 31-91 FCC Transmit Internal Rate Register (FTIRRx) ................................................. 31-91 Example ............................................................................................................... 31-92 Internal Rate Programming Model ...................................................................... 31-93 FCC Transmit Internal Rate Port Enable Registers (FIRPERx).......................... 31-93 FCC Internal Rate Event Registers (FIRERx) ..................................................... 31-94 FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO) ................... 31-95 SRTS Generation and Clock Recovery Using External Logic .................................... 31-97 Configuring the ATM Controller for Maximum CPM Performance........................... 31-98 Using Transmit Internal Rate Mode ........................................................................ 31-98 APC Configuration .................................................................................................. 31-99 Buffer Configuration................................................................................................ 31-99 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxxvii Contents Paragraph Number Title Chapter 32 ATM AAL1 Circuit Emulation Service 32.1 32.2 32.2.1 32.2.2 32.3 32.4 32.4.1 32.4.1.1 32.4.1.2 32.4.2 32.4.3 32.4.4 32.4.5 32.4.6 32.4.7 32.4.7.1 32.4.7.2 32.4.7.2.1 32.4.7.3 32.4.7.3.1 32.5 32.5.1 32.6 32.6.1 32.7 32.8 32.8.1 32.9 32.9.1 32.9.1.1 32.9.2 32.9.2.1 32.10 32.11 32.11.1 32.11.2 32.12 32.12.1 Features .......................................................................................................................... 32-1 AAL1 CES Transmitter Overview................................................................................. 32-3 Data Path.................................................................................................................... 32-3 Signaling Path ............................................................................................................ 32-3 AAL1 CES Receiver Overview ..................................................................................... 32-4 Interworking Functions.................................................................................................. 32-6 Automatic Data Forwarding ...................................................................................... 32-6 ATM-to-TDM ........................................................................................................ 32-7 TDM-to-ATM ........................................................................................................ 32-7 Timing Issues ............................................................................................................. 32-8 Clock Synchronization (SRTS, Adaptive FIFO) ....................................................... 32-9 Mapping TDM Time Slots to VCs............................................................................. 32-9 Trunk Condition....................................................................................................... 32-10 Channel Associated Signaling (CAS) Support ........................................................ 32-10 Mapping VC Signaling to CAS Blocks ................................................................... 32-11 CAS Routing Table.............................................................................................. 32-12 TDM-to-ATM CAS Support................................................................................ 32-13 CAS Mapping Using the Core (Optional) ....................................................... 32-14 ATM-to-TDM CAS Support................................................................................ 32-14 CAS Updates Using the Core (Optional) ........................................................ 32-15 ATM-to-TDM Adaptive Slip Control .......................................................................... 32-15 CES Adaptive Threshold Tables.............................................................................. 32-16 3-Step-SN Algorithm ................................................................................................... 32-20 The Three States of the Algorithm .......................................................................... 32-20 Pointer Verification Mechanism .................................................................................. 32-21 AAL-1 Memory Structure............................................................................................ 32-22 AAL1 CES Parameter RAM.................................................................................... 32-22 Receive and Transmit Connection Tables (RCT, TCT) ............................................... 32-25 Receive Connection Table (RCT)............................................................................ 32-26 AAL1 CES Protocol-Specific RCT ..................................................................... 32-29 Transmit Connection Table (TCT)........................................................................... 32-32 AAL1 CES Protocol-Specific TCT ..................................................................... 32-34 Outgoing CAS Status Register (OCASSR) ................................................................ 32-36 Buffer Descriptors........................................................................................................ 32-36 Transmit Buffer Operation....................................................................................... 32-36 Receive Buffer Operation ........................................................................................ 32-37 ATM Controller Buffers............................................................................................... 32-38 AAL1 CES RxBD.................................................................................................... 32-39 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xxxviii Freescale Semiconductor Page Number Contents Paragraph Number 32.12.2 32.13 32.13.1 32.14 32.15 32.16 32.17 32.18 Title Page Number AAL1 CES TxBDs .................................................................................................. 32-40 AAL1 CES Exceptions ................................................................................................ 32-41 AAL1 CES Interrupt Queue Entry........................................................................... 32-41 AAL1 Sequence Number (SN) Protection Table ........................................................ 32-42 Internal AAL1 CES Statistics Tables........................................................................... 32-43 External AAL1 CES Statistics Tables.......................................................................... 32-44 CES-Specific Additions to the MCC ........................................................................... 32-44 Application Considerations.......................................................................................... 32-44 Chapter 33 ATM AAL2 33.1 33.2 33.3 33.3.1 33.3.2 33.3.2.1 33.3.2.2 33.3.3 33.3.4 33.3.5 33.3.5.1 33.3.5.2 33.3.5.3 33.3.5.4 33.3.5.5 33.4 33.4.1 33.4.2 33.4.3 33.4.4 33.4.4.1 33.4.4.2 33.4.4.3 33.4.4.4 33.4.4.5 33.4.4.6 33.4.4.7 33.4.4.8 33.5 Introduction.................................................................................................................... 33-1 Features .......................................................................................................................... 33-3 AAL2 Transmitter.......................................................................................................... 33-5 Transmitter Overview ................................................................................................ 33-5 Transmit Priority Mechanism .................................................................................... 33-6 Round Robin Priority............................................................................................. 33-6 Fixed Priority ......................................................................................................... 33-7 Partial Fill Mode (PFM) ............................................................................................ 33-7 No STF Mode ............................................................................................................ 33-8 AAL2 Tx Data Structures .......................................................................................... 33-9 AAL2 Protocol-Specific TCT................................................................................ 33-9 CPS Tx Queue Descriptor ................................................................................... 33-12 CPS Buffer Structure ........................................................................................... 33-14 SSSAR Tx Queue Descriptor .............................................................................. 33-16 SSSAR Transmit Buffer Descriptor..................................................................... 33-18 AAL2 Receiver ............................................................................................................ 33-19 Receiver Overview .................................................................................................. 33-19 Mapping of PHY | VP | VC | CID............................................................................ 33-20 AAL2 Switching...................................................................................................... 33-21 AAL2 RX Data Structures ....................................................................................... 33-22 AAL2 Protocol-Specific RCT ............................................................................. 33-23 CID Mapping Tables and RxQDs........................................................................ 33-26 CPS Rx Queue Descriptors.................................................................................. 33-26 CPS Receive Buffer Descriptor (RxBD) ............................................................. 33-27 CPS Switch Rx Queue Descriptor ....................................................................... 33-28 SWITCH Receive/Transmit Buffer Descriptor (RxBD)...................................... 33-29 SSSAR Rx Queue Descriptor .............................................................................. 33-30 SSSAR Receive Buffer Descriptor ...................................................................... 33-32 AAL2 Parameter RAM ................................................................................................ 33-34 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xxxix Contents Paragraph Number 33.6 33.7 Title Page Number User-Defined Cells in AAL2 ....................................................................................... 33-37 AAL2 Exceptions ........................................................................................................ 33-38 Chapter 34 Inverse Multiplexing for ATM (IMA) 34.1 34.1.1 34.1.2 34.1.3 34.1.4 34.1.5 34.1.6 34.2 34.2.1 34.2.2 34.2.3 34.2.3.1 34.2.3.2 34.3 34.3.1 34.3.1.1 34.3.1.2 34.3.2 34.3.2.1 34.3.2.1.1 34.3.2.2 34.3.2.3 34.3.2.4 34.3.3 34.3.3.1 34.3.3.2 34.3.3.2.1 34.3.3.2.2 34.3.3.3 34.4 34.4.1 34.4.2 34.4.2.1 34.4.2.1.1 34.4.2.1.2 Features .......................................................................................................................... 34-1 References.................................................................................................................. 34-3 IMA Versions Supported ........................................................................................... 34-3 MPC8280 Versions Supported................................................................................... 34-3 PHY-Layer Devices Supported.................................................................................. 34-4 ATM Features Not Supported .................................................................................... 34-4 Additional Impact on MPC8280 Features ................................................................. 34-4 IMA Protocol Overview ............................................................................................... 34-4 Introduction................................................................................................................ 34-4 IMA Frame Overview................................................................................................ 34-5 Overview of IMA Cells ............................................................................................. 34-7 IMA Control Cells ................................................................................................. 34-7 IMA Filler Cells..................................................................................................... 34-8 IMA Microcode Architecture ........................................................................................ 34-8 IMA Function Partitioning......................................................................................... 34-8 User Plane Functions Performed by Microcode.................................................... 34-9 Plane Management Functions Performed by Microcode....................................... 34-9 Transmit Architecture ................................................................................................ 34-9 TRL Operation..................................................................................................... 34-10 TRL Service Latency....................................................................................... 34-11 Non-TRL Operation............................................................................................. 34-11 Transmit Queue Operation Examples (ITC mode).............................................. 34-12 Differences in CTC Operation ............................................................................. 34-14 Receive Architecture................................................................................................ 34-15 Cell Reception Task ............................................................................................. 34-15 Cell Processing Activation Function ................................................................... 34-18 On-Demand Cell Processing ........................................................................... 34-18 IDCR-Regulated Cell Processing .................................................................... 34-19 Cell Processing Task............................................................................................ 34-20 IMA Programming Model ........................................................................................... 34-20 Data Structure Organization .................................................................................... 34-20 IMA FCC Programming .......................................................................................... 34-22 FCC Registers ..................................................................................................... 34-22 FPSMRx .......................................................................................................... 34-22 FTIRRx ............................................................................................................ 34-22 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xl Freescale Semiconductor Contents Paragraph Number 34.4.2.2 34.4.2.2.1 34.4.2.2.2 34.4.2.3 34.4.3 34.4.3.1 34.4.4 34.4.4.1 34.4.4.1.1 34.4.4.1.2 34.4.4.1.3 34.4.4.1.4 34.4.4.2 34.4.4.2.1 34.4.4.2.2 34.4.4.2.3 34.4.4.2.4 34.4.5 34.4.5.1 34.4.5.1.1 34.4.5.1.2 34.4.5.1.3 34.4.5.2 34.4.5.2.1 34.4.5.2.2 34.4.5.3 34.4.6 34.4.6.1 34.4.6.2 34.4.7 34.4.7.1 34.4.7.2 34.4.8 34.4.8.1 34.4.8.2 34.4.8.2.1 34.4.8.2.2 34.4.8.2.3 34.4.8.3 34.4.8.4 34.4.8.5 Title Page Number FCC Parameters ................................................................................................... 34-22 TCELL_TMP_BASE and RCELL_TMP_BASE ........................................... 34-22 GMODE........................................................................................................... 34-22 IMA-Specific FCC Parameters............................................................................ 34-22 IMA Root Table ....................................................................................................... 34-23 IMA Control (IMACNTL) .................................................................................. 34-25 IMA Group Tables ................................................................................................... 34-25 IMA Group Transmit Table Entry ....................................................................... 34-25 IMA Group Transmit Control (IGTCNTL) .................................................... 34-27 IMA Group Transmit State (IGTSTATE) ....................................................... 34-27 Transmit Group Order Table............................................................................ 34-28 ICP Cell Templates .......................................................................................... 34-29 IMA Group Receive Table Entry......................................................................... 34-31 IMA Group Receive Control (IGRCNTL) ..................................................... 34-34 IMA Group Receive State (IGRSTATE) ........................................................ 34-34 IMA Receive Group Frame Size .................................................................... 34-35 Receive Group Order Tables ........................................................................... 34-35 IMA Link Tables...................................................................................................... 34-36 IMA Link Transmit Table Entry .......................................................................... 34-36 IMA Link Transmit Control (ILTCNTL) ....................................................... 34-37 IMA Link Transmit State (ILTSTATE) .......................................................... 34-38 IMA Transmit Interrupt Status (ITINTSTAT) ................................................ 34-39 IMA Link Receive Table Entry ........................................................................... 34-40 IMA Link Receive Control (ILRCNTL) ........................................................ 34-41 IMA Link Receive State (ILRSTATE) ........................................................... 34-42 IMA Link Receive Statistics Table...................................................................... 34-43 Structures in External Memory................................................................................ 34-43 Transmit Queues .................................................................................................. 34-44 Delay Compensation Buffers (DCB)................................................................... 34-44 IMA Exceptions....................................................................................................... 34-45 IMA Interrupt Queue Entry ................................................................................. 34-45 ICP Cell Reception Exceptions ........................................................................... 34-46 IDCR Timer Programming ...................................................................................... 34-47 IDCR Master Clock ............................................................................................. 34-47 IDCR FCC Parameter Shadow ............................................................................ 34-47 MPC8280 Features Unavailable if IDCR is Used ........................................... 34-47 Programming the FCC Parameter Shadow...................................................... 34-48 On-the-Fly Changes of FCC Parameters ......................................................... 34-48 IDCR_Init Command........................................................................................... 34-49 IDCR Root Parameters ........................................................................................ 34-49 IDCR Table Entry ................................................................................................ 34-49 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xli Contents Paragraph Number 34.4.8.6 34.4.8.7 34.4.9 34.4.9.1 34.4.9.2 34.4.10 34.5 34.5.1 34.5.2 34.5.3 34.5.3.1 34.5.3.2 34.5.3.3 34.5.3.4 34.5.3.5 34.5.3.6 34.5.3.7 34.5.3.8 34.5.3.9 34.5.3.10 34.5.3.11 34.5.3.12 34.5.3.13 34.5.4 34.5.4.1 34.5.4.2 34.5.4.3 34.5.4.3.1 34.5.4.3.2 34.5.4.4 34.5.4.4.1 34.5.4.4.2 34.5.4.5 34.5.4.5.1 34.5.4.5.2 34.5.4.6 34.5.4.7 34.5.4.8 34.5.4.9 34.5.4.10 34.5.4.11 Title Page Number IDCR Counter Algorithm .................................................................................... 34-50 IDCR Events........................................................................................................ 34-50 APC Programming for IMA .................................................................................... 34-51 Programming for CBR, UBR, VBR, and UBR+ ................................................. 34-52 Programming for ABR ........................................................................................ 34-52 Changing IMA Version............................................................................................ 34-53 IMA Software Interface and Requirements ................................................................. 34-53 Software Model........................................................................................................ 34-53 Initialization Procedure............................................................................................ 34-54 Software Responsibilities ........................................................................................ 34-54 System Definition ................................................................................................ 34-54 General Operation................................................................................................ 34-55 Receive Link State Machine Control................................................................... 34-55 Receive Group State Machine Control ................................................................ 34-55 Transmit Link State Machine Control ................................................................. 34-55 Transmit Group State Machine Control............................................................... 34-56 Group Symmetry Control .................................................................................... 34-56 ICP End-to-End Channel Transmission............................................................... 34-56 Link Addition and Slow Recovery (LASR) Procedure ....................................... 34-56 Failure Alarms ..................................................................................................... 34-56 Test Pattern Control ............................................................................................. 34-57 Performance Parameter Measurement and Reporting ......................................... 34-57 SNMP MIBs ........................................................................................................ 34-57 IMA Software Procedures ....................................................................................... 34-57 Transmit ICP Cell Signalling............................................................................... 34-57 Receive Link Start-up Procedure......................................................................... 34-57 Group Start-up Procedure ................................................................................... 34-58 As Initiator (TX).............................................................................................. 34-59 As Responder (RX) ......................................................................................... 34-60 Link Addition Procedure ..................................................................................... 34-60 Rx Steps ........................................................................................................... 34-61 TX Parameters ................................................................................................. 34-61 Link Removal Procedure ..................................................................................... 34-62 Rx Steps ........................................................................................................... 34-62 TX Parameters ................................................................................................. 34-63 Link Receive Deactivation Procedure ................................................................. 34-63 Link Receive Reactivation Procedure ................................................................. 34-64 TRL On-the-Fly Change Procedure..................................................................... 34-64 Transmit Event Response Procedures.................................................................. 34-65 Receive Event Response Procedures ................................................................... 34-65 Test Pattern Procedure ......................................................................................... 34-67 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xlii Freescale Semiconductor Contents Paragraph Number 34.5.4.11.1 34.5.4.11.2 34.5.4.12 34.5.4.12.1 34.5.4.12.2 34.5.4.13 34.5.4.13.1 34.5.4.13.2 Title Page Number As Initiator (NE).............................................................................................. 34-67 As Responder (FE) .......................................................................................... 34-67 IDCR Operation................................................................................................... 34-68 IDCR Start-up.................................................................................................. 34-68 Activating a Group in IDCR Mode ................................................................. 34-69 End-to-End Channel Signalling Procedure.......................................................... 34-69 Transmit ........................................................................................................... 34-69 Receive ............................................................................................................ 34-70 Chapter 35 ATM Transmission Convergence Layer 35.1 35.2 35.2.1 35.2.1.1 35.2.2 35.2.2.1 35.2.3 35.2.4 35.3 35.4 35.4.1 35.4.1.1 35.4.1.2 35.4.1.3 35.4.1.4 35.4.2 35.4.2.1 35.4.2.2 35.4.3 35.4.3.1 35.4.3.2 35.4.3.3 35.4.3.4 35.4.3.5 35.4.3.6 35.4.4 35.4.5 35.4.5.1 35.4.5.2 Features .......................................................................................................................... 35-2 Functionality .................................................................................................................. 35-3 Receive ATM Cell Functions..................................................................................... 35-3 Receive ATM 2-Cell FIFO .................................................................................... 35-5 Transmit ATM Cell Functions ................................................................................... 35-5 Transmit ATM 2-Cell FIFO................................................................................... 35-6 Receive UTOPIA Interface........................................................................................ 35-6 Transmit UTOPIA Interface ...................................................................................... 35-6 Signals............................................................................................................................ 35-6 TC Layer Programming Mode ...................................................................................... 35-6 TC Layer Registers .................................................................................................... 35-6 TC Layer Mode Registers 1–8 (TCMODEx) ........................................................ 35-7 Cell Delineation State Machine Registers 1–8 (CDSMRx)................................... 35-8 TC Layer Event Registers 1–8 (TCERx) ............................................................... 35-9 TC Layer Mask Register (TCMRx)..................................................................... 35-10 TC Layer General Registers .................................................................................... 35-10 TC Layer General Event Register (TCGER)....................................................... 35-10 TC Layer General Status Register (TCGSR)....................................................... 35-11 TC Layer Cell Counters........................................................................................... 35-11 Received Cell Counters 1–8 (TC_RCCx)............................................................ 35-11 Transmitted Cell Counters 1–8 (TC_TCCx)........................................................ 35-11 Errored Cell Counters 1–8 (TC_ECCx)............................................................... 35-12 Corrected Cell Counters 1–8 (TC_CCCx) ........................................................... 35-12 Transmitted IDLE Cell Counters 1–8 (TC_ICCx)............................................... 35-12 Filtered Cell Counters 1–8 (TC_FCCx)............................................................... 35-12 Programming FCC2................................................................................................. 35-12 Programming and Operating the TC Layer ............................................................. 35-12 Receive ................................................................................................................ 35-12 Transmit ............................................................................................................... 35-13 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xliii Contents Paragraph Number 35.5 35.5.1 35.5.2 35.5.3 35.5.4 35.5.5 35.5.6 35.5.7 35.5.8 35.5.9 Title Page Number Implementation Example ............................................................................................. 35-15 Operating the TC Layer at Higher Frequencies....................................................... 35-15 Programming a T1 Application ............................................................................... 35-15 Step 1 ....................................................................................................................... 35-16 Step 2 ....................................................................................................................... 35-16 Step 3 ....................................................................................................................... 35-16 Step 4 ....................................................................................................................... 35-16 Step 5 ....................................................................................................................... 35-17 Step 6 ....................................................................................................................... 35-17 Step 7 ....................................................................................................................... 35-17 Chapter 36 Fast Ethernet Controller 36.1 36.2 36.3 36.3.1 36.4 36.5 36.6 36.7 36.8 36.9 36.10 36.11 36.12 36.13 36.14 36.15 36.16 36.17 36.18 36.18.1 36.18.2 36.19 36.20 Fast Ethernet on the MPC8280...................................................................................... 36-2 Features .......................................................................................................................... 36-2 Connecting the MPC8280 to Fast Ethernet ................................................................... 36-4 Connecting the MPC8280 to Ethernet (RMII) .......................................................... 36-5 Ethernet Channel Frame Transmission .......................................................................... 36-5 Ethernet Channel Frame Reception ............................................................................... 36-6 Flow Control .................................................................................................................. 36-7 CAM Interface ............................................................................................................... 36-8 Ethernet Parameter RAM............................................................................................... 36-8 Programming Model .................................................................................................... 36-12 Ethernet Command Set ................................................................................................ 36-12 RMON Support............................................................................................................ 36-14 Ethernet Address Recognition ..................................................................................... 36-15 Hash Table Algorithm.................................................................................................. 36-17 Interpacket Gap Time................................................................................................... 36-18 Handling Collisions ..................................................................................................... 36-18 Internal and External Loopback................................................................................... 36-18 Ethernet Error-Handling Procedure ............................................................................. 36-18 Fast Ethernet Registers ................................................................................................ 36-19 FCC Ethernet Mode Registers (FPSMRx)............................................................... 36-19 Ethernet Event Register (FCCE)/Mask Register (FCCM) ...................................... 36-21 Ethernet RxBDs ........................................................................................................... 36-23 Ethernet TxBDs ........................................................................................................... 36-26 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xliv Freescale Semiconductor Contents Paragraph Number Title Chapter 37 FCC HDLC Controller 37.1 37.2 37.3 37.4 37.5 37.5.1 37.5.2 37.6 37.7 37.8 37.9 37.10 Key Features .................................................................................................................. 37-1 HDLC Channel Frame Transmission Processing .......................................................... 37-2 HDLC Channel Frame Reception Processing ............................................................... 37-3 HDLC Parameter RAM ................................................................................................. 37-3 Programming Model ...................................................................................................... 37-5 HDLC Command Set................................................................................................. 37-5 HDLC Error Handling ............................................................................................... 37-6 HDLC Mode Register (FPSMR) ................................................................................... 37-8 HDLC Receive Buffer Descriptor (RxBD).................................................................... 37-9 HDLC Transmit Buffer Descriptor (TxBD) ................................................................ 37-12 HDLC Event Register (FCCE)/Mask Register (FCCM) ............................................. 37-14 FCC Status Register (FCCS) ....................................................................................... 37-16 Chapter 38 FCC Transparent Controller 38.1 38.2 38.3 38.3.1 38.3.2 38.3.3 Features .......................................................................................................................... 38-1 Transparent Channel Operation ..................................................................................... 38-2 Achieving Synchronization in Transparent Mode ......................................................... 38-2 In-Line Synchronization Pattern................................................................................ 38-2 External Synchronization Signals.............................................................................. 38-3 Transparent Synchronization Example ...................................................................... 38-4 Chapter 39 Serial Peripheral Interface (SPI) 39.1 39.2 39.3 39.3.1 39.3.2 39.3.3 39.4 39.4.1 39.4.1.1 39.4.2 39.4.3 39.5 Features .......................................................................................................................... 39-1 SPI Clocking and Signal Functions ............................................................................... 39-2 Configuring the SPI Controller...................................................................................... 39-2 The SPI as a Master Device....................................................................................... 39-3 The SPI as a Slave Device ......................................................................................... 39-4 The SPI in Multimaster Operation............................................................................. 39-4 Programming the SPI Registers ..................................................................................... 39-6 SPI Mode Register (SPMODE) ................................................................................. 39-6 SPI Examples with Different SPMODE[LEN] Values.......................................... 39-8 SPI Event/Mask Registers (SPIE/SPIM) ................................................................... 39-9 SPI Command Register (SPCOM) .......................................................................... 39-10 SPI Parameter RAM .................................................................................................... 39-10 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xlv Page Number Contents Paragraph Number 39.5.1 39.6 39.7 39.7.1 39.7.1.1 39.7.1.2 39.8 39.9 39.10 Title Page Number Receive/Transmit Function Code Registers (RFCR/TFCR).................................... 39-12 SPI Commands ............................................................................................................ 39-12 The SPI Buffer Descriptor (BD) Table ........................................................................ 39-13 SPI Buffer Descriptors (BDs) .................................................................................. 39-13 SPI Receive BD (RxBD) ..................................................................................... 39-14 SPI Transmit BD (TxBD) .................................................................................... 39-15 SPI Master Programming Example ............................................................................. 39-16 SPI Slave Programming Example................................................................................ 39-17 Handling Interrupts in the SPI ..................................................................................... 39-17 I2C 40.1 40.2 40.3 40.3.1 40.3.2 40.3.3 40.3.4 40.4 40.4.1 40.4.2 40.4.3 40.4.4 40.4.5 40.5 40.6 40.7 40.7.1 40.7.1.1 40.7.1.2 Chapter 40 Controller Features .......................................................................................................................... 40-2 I2C Controller Clocking and Signal Functions.............................................................. 40-2 I2C Controller Transfers ................................................................................................ 40-2 I2C Master Write (Slave Read).................................................................................. 40-3 I2C Loopback Testing................................................................................................ 40-4 I2C Master Read (Slave Write).................................................................................. 40-4 I2C Multi-Master Considerations .............................................................................. 40-5 2C Registers .................................................................................................................. 40-5 I I2C Mode Register (I2MOD) .................................................................................... 40-6 I2C Address Register (I2ADD) ................................................................................. 40-7 I2C Baud Rate Generator Register (I2BRG) ............................................................. 40-7 I2C Event/Mask Registers (I2CER/I2CMR) ............................................................. 40-7 I2C Command Register (I2COM) ............................................................................. 40-8 2C Parameter RAM....................................................................................................... 40-9 I I2C Commands............................................................................................................. 40-11 The I2C Buffer Descriptor (BD) Table ........................................................................ 40-11 I2C Buffer Descriptors (BDs).................................................................................. 40-12 I2C Receive Buffer Descriptor (RxBD) .............................................................. 40-12 I2C Transmit Buffer Descriptor (TxBD) ............................................................. 40-13 Chapter 41 Parallel I/O Ports 41.1 41.2 41.2.1 41.2.2 41.2.3 Features .......................................................................................................................... 41-1 Port Registers ................................................................................................................. 41-1 Port Open-Drain Registers (PODRA–PODRD) ........................................................ 41-2 Port Data Registers (PDATA–PDATD) ..................................................................... 41-2 Port Data Direction Registers (PDIRA–PDIRD)....................................................... 41-3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xlvi Freescale Semiconductor Contents Paragraph Number 41.2.4 41.2.5 41.3 41.4 41.4.1 41.4.2 41.5 41.6 Title Page Number Port Pin Assignment Register (PPAR)....................................................................... 41-4 Port Special Options Registers A–D (PSORA–PSORD) .......................................... 41-4 Port Block Diagram ....................................................................................................... 41-6 Port Pins Functions ........................................................................................................ 41-6 General Purpose I/O Pins........................................................................................... 41-7 Dedicated Pins ........................................................................................................... 41-7 Ports Tables .................................................................................................................... 41-7 Interrupts from Port C.................................................................................................. 41-20 Appendix A Register Quick Reference Guide A.1 A.2 A.3 PowerPC Registers—User Registers .............................................................................. A-1 PowerPC Registers—Supervisor Registers .................................................................... A-1 MPC8280-Specific SPRs ................................................................................................ A-3 Appendix B Revision History MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xlvii Contents Paragraph Number Title Page Number MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xlviii Freescale Semiconductor Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 Title Figures Page Number MPC8280 Block Diagram....................................................................................................... 1-6 MPC8280 External Signals ..................................................................................................... 1-9 Remote Access Server Configuration ................................................................................... 1-13 Regional Office Router Configuration.................................................................................. 1-14 LAN-to-WAN Bridge Router Configuration ........................................................................ 1-15 Cellular Base Station Configuration ..................................................................................... 1-15 Telecommunications Switch Controller Configuration ........................................................ 1-16 SONET Transmission Controller Configuration .................................................................. 1-17 Basic System Configuration.................................................................................................. 1-18 High-Performance Communication ...................................................................................... 1-18 High-Performance System Microprocessor Configuration................................................... 1-19 PCI Configuration ................................................................................................................. 1-20 PCI with 155-Mbps ATM Configuration .............................................................................. 1-20 MPC8280 as PCI Agent ........................................................................................................ 1-21 MPC8280 Integrated Processor Core Block Diagram ............................................................ 2-2 MPC8280 Programming Model—Registers ......................................................................... 2-10 Hardware Implementation Register 0 (HID0) ...................................................................... 2-11 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-14 Hardware Implementation-Dependent Register 2 (HID2).................................................... 2-14 Data Cache Organization ...................................................................................................... 2-19 Internal Memory ..................................................................................................................... 3-1 SIU Block Diagram................................................................................................................. 4-1 System Configuration and Protection Logic ........................................................................... 4-3 Timers Clock Generation ........................................................................................................ 4-4 TMCNT Block Diagram ......................................................................................................... 4-5 PIT Block Diagram ................................................................................................................. 4-5 Software Watchdog Timer Service State Diagram.................................................................. 4-6 Software Watchdog Timer Block Diagram ............................................................................. 4-7 MPC8280 Interrupt Structure.................................................................................................. 4-8 Interrupt Request Masking.................................................................................................... 4-14 SIU Interrupt Configuration Register (SICR) ....................................................................... 4-17 SIU Interrupt Priority Register (SIPRR) ............................................................................... 4-18 CPM High Interrupt Priority Register (SCPRR_H).............................................................. 4-19 CPM Low Interrupt Priority Register (SCPRR_L)............................................................... 4-20 SIPNR_H .............................................................................................................................. 4-21 SIPNR_L ............................................................................................................................... 4-22 SIMR_H ................................................................................................................................ 4-23 SIMR_L ................................................................................................................................ 4-23 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor xlix Figures Figure Number 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 Title Page Number SIU Interrupt Vector Register (SIVEC) ................................................................................ 4-24 Interrupt Table Handling Example........................................................................................ 4-25 SIU External Interrupt Control Register (SIEXR) ................................................................ 4-26 Bus Configuration Register (BCR) ....................................................................................... 4-27 PPC_ACR ............................................................................................................................. 4-29 PPC_ALRH........................................................................................................................... 4-30 PPC_ALRL ........................................................................................................................... 4-31 LCL_ACR............................................................................................................................. 4-31 LCL_ALRH .......................................................................................................................... 4-32 LCL_ALRL........................................................................................................................... 4-33 SIU Model Configuration Register (SIUMCR) .................................................................... 4-33 Internal Memory Map Register (IMMR) .............................................................................. 4-36 System Protection Control Register (SYPCR)...................................................................... 4-37 60x Bus Transfer Error Status and Control Register 1 (TESCR1) ....................................... 4-39 60x Bus Transfer Error Status and Control Register 2 (TESCR2) ....................................... 4-41 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) ................................ 4-42 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) ................................ 4-43 Time Counter Status and Control Register (TMCNTSC) ..................................................... 4-44 Time Counter Register (TCMCNT)...................................................................................... 4-45 Time Counter Alarm Register (TMCNTAL) ........................................................................ 4-45 Periodic Interrupt Status and Control Register (PISCR)....................................................... 4-46 Periodic interrupt Timer Count Register (PITC) .................................................................. 4-47 Periodic Interrupt Timer Register (PITR) ............................................................................. 4-48 PCI Base Registers (PCIBRx)............................................................................................... 4-49 PCI Mask Register (PCIMSKx)............................................................................................ 4-50 Power-on Reset Flow .............................................................................................................. 5-3 Reset Status Register (RSR).................................................................................................... 5-4 Reset Mode Register (RMR)................................................................................................... 5-5 Hard Reset Configuration Word.............................................................................................. 5-8 Single Chip with Default Configuration ............................................................................... 5-10 Configuring a Single Chip from EPROM............................................................................. 5-11 Configuring Multiple Chips .................................................................................................. 5-12 MPC8280 External Signals ..................................................................................................... 6-2 Signal Groupings..................................................................................................................... 7-2 Single-MPC8280 Bus Mode ................................................................................................... 8-3 60x-Compatible Bus Mode ..................................................................................................... 8-4 Basic Transfer Protocol........................................................................................................... 8-5 Address Bus Arbitration with External Bus Master................................................................ 8-8 Address Pipelining .................................................................................................................. 8-9 Interface to Different Port Size Devices ............................................................................... 8-16 Retry Cycle ........................................................................................................................... 8-22 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 l Freescale Semiconductor Figures Figure Number 8-8 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 Title Page Number Single-Beat and Burst Data Transfers................................................................................... 8-26 28-Bit Extended Transfer to 32-Bit Port Size ....................................................................... 8-27 Burst Transfer to 32-Bit Port Size......................................................................................... 8-28 Data Tenure Terminated by Assertion of TEA ..................................................................... 8-29 MEI Cache Coherency Protocol—State Diagram (WIM = 001) .......................................... 8-30 PCI Bridge in the MPC8280 ................................................................................................... 9-2 PCI Bridge Structure ............................................................................................................... 9-2 Single Beat Read Example.................................................................................................... 9-10 Burst Read Example.............................................................................................................. 9-10 Single Beat Write Example ................................................................................................... 9-11 Burst Write Example............................................................................................................. 9-11 Target-Initiated Terminations................................................................................................ 9-12 PCI Configuration Type 0 Translation (Top = CONFIG_ADDR) (Bottom = PCI Address Lines) .............................................. 9-15 PCI Parity Operation ............................................................................................................. 9-18 PCI Arbitration Example ...................................................................................................... 9-20 Address Decode Flow Chart for 60x Bus Mastered Transactions ........................................ 9-21 Address Decode Flow Chart for PCI Mastered Transactions ............................................... 9-22 Address Decode Flow Chart for Embedded Utilities (DMA, Message Unit) Mastered Transactions................................................................. 9-23 Address Map Example .......................................................................................................... 9-24 Inbound PCI Memory Address Translation .......................................................................... 9-25 Outbound PCI Memory Address Translation ....................................................................... 9-26 PCI Outbound Translation Address Registers (POTARx) .................................................... 9-30 PCI Outbound Base Address Registers (POBARx).............................................................. 9-31 PCI Outbound Comparison Mask Registers (POCMRx) ..................................................... 9-32 Discard Timer Control register (PTCR) ................................................................................ 9-33 General Purpose Control Register (GPCR) .......................................................................... 9-34 PCI General Control Register (PCI_GCR) ........................................................................... 9-35 Error Status Register (ESR) .................................................................................................. 9-36 Error Mask Register (EMR).................................................................................................. 9-37 Error Control Register (ECR) ............................................................................................... 9-38 PCI Error Address Capture Register (PCI_EACR) .............................................................. 9-39 PCI Error Data Capture Register (PCI_EDCR) .................................................................... 9-40 PCI Error Control Capture Register (PCI_ECCR) ............................................................... 9-41 PCI Inbound Translation Address Registers (PITARx) ........................................................ 9-42 PCI Inbound Base Address Registers (PIBARx) .................................................................. 9-43 PCI Inbound Comparison Mask Registers (PICMRx).......................................................... 9-44 PCI Bridge PCI Configuration Registers .............................................................................. 9-46 Vendor ID Register................................................................................................................ 9-47 Device ID Register................................................................................................................ 9-47 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor li Figures Figure Number 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 9-55 9-56 9-57 9-58 9-59 9-60 9-61 9-62 9-63 9-64 9-65 9-66 9-67 9-68 9-69 9-70 9-71 9-72 9-73 9-74 Title Page Number PCI Bus Command Register ................................................................................................. 9-48 PCI Bus Status Register ........................................................................................................ 9-49 Revision ID Register ............................................................................................................. 9-50 PCI Bus Programming Interface Register............................................................................. 9-50 Subclass Code Register ......................................................................................................... 9-51 PCI Bus Base Class Code Register ....................................................................................... 9-51 PCI Bus Cache Line Size Register........................................................................................ 9-52 PCI Bus Latency Timer Register .......................................................................................... 9-52 Header Type Register ............................................................................................................ 9-53 BIST Control Register .......................................................................................................... 9-53 PCI Bus Internal Memory-Mapped Registers Base Address Register (PIMMRBAR).................................................................................................................. 9-54 General Purpose Local Access Base Address Registers (GPLABARx)............................... 9-55 Subsystem Vendor ID Register ............................................................................................. 9-55 Subsystem Device ID Register ............................................................................................. 9-56 PCI Bus Capabilities Pointer Register .................................................................................. 9-56 PCI Bus Interrupt Line Register............................................................................................ 9-57 PCI Bus Interrupt Pin Register.............................................................................................. 9-57 PCI Bus MIN GNT ............................................................................................................... 9-58 PCI Bus MAX LAT............................................................................................................... 9-58 PCI Bus Function Register.................................................................................................... 9-59 PCI Bus Arbiter Configuration Register ............................................................................... 9-60 Hot Swap Register Block ...................................................................................................... 9-61 Hot Swap Control Status Register......................................................................................... 9-61 Data Structure for Register Initialization .............................................................................. 9-64 PCI Configuration Data Structure for the EEPROM ............................................................ 9-66 Inbound Message Registers (IMRx) ..................................................................................... 9-67 Outbound Message Registers (OMRx) ................................................................................. 9-68 Outbound Doorbell Register (ODR) ..................................................................................... 9-69 Inbound Doorbell Register (IDR) ......................................................................................... 9-69 I2O Message Queue .............................................................................................................. 9-71 Inbound Free_FIFO Head Pointer Register (IFHPR) ........................................................... 9-72 Inbound Free_FIFO Tail Pointer Register (IFTPR) .............................................................. 9-73 Inbound Post_FIFO Head Pointer Register (IPHPR) ........................................................... 9-74 Inbound Post_FIFO Tail Pointer Register (IPTPR) .............................................................. 9-74 Outbound Free_FIFO Head Pointer Register (OFHPR) ....................................................... 9-75 Outbound Free_FIFO Tail Pointer Register (OFTPR).......................................................... 9-76 Outbound Post_FIFO Head Pointer Register (OPHPR) ....................................................... 9-77 Outbound Post_FIFO Tail Pointer Register (OPTPR) .......................................................... 9-78 Inbound FIFO Queue Port Register (IFQPR) ....................................................................... 9-79 Outbound FIFO Queue Port Register (OFQPR) ................................................................... 9-79 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lii Freescale Semiconductor Figures Figure Number 9-75 9-76 9-77 9-78 9-79 9-80 9-81 9-82 9-83 9-84 9-85 9-86 9-87 9-88 9-89 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 Title Page Number Outbound Message Interrupt Status Register (OMISR) ....................................................... 9-80 Outbound Message Interrupt Mask Register (OMIMR)....................................................... 9-81 Inbound Message Interrupt Status Register (IMISR)............................................................ 9-82 Inbound Message Interrupt Mask Register (IMIMR) ........................................................... 9-83 Messaging Unit Control Register (MUCR) .......................................................................... 9-84 Queue Base Address Register (QBAR) ................................................................................ 9-85 DMA Controller Block Diagram .......................................................................................... 9-86 DMA Mode Registers 0–3 (DMAMRx) ............................................................................... 9-89 DMA Status Registers 0–3 (DMASRx) ................................................................................ 9-91 DMA Current Descriptor Address Registers 0–3 (DMACDARx) ....................................... 9-92 DMA Source Address Registers 0–3 (DMASARx).............................................................. 9-93 DMA Destination Address Registers 0–3 (DMADARx)...................................................... 9-94 DMA Byte Count Registers 0–3 (DMABCRx) .................................................................... 9-95 DMA Next Descriptor Address Registers 0–3 (DMANDARx)............................................ 9-95 DMA Chain of Segment Descriptors .................................................................................... 9-97 MPC8280 System Clock Architecture.................................................................................. 10-3 PCI Bridge as an Agent, Operating from the PCI System Clock ......................................... 10-4 PCI Bridge as a Host, Generating the PCI System Clock..................................................... 10-5 PLL Filtering Circuit............................................................................................................. 10-5 System Clock Control Register (SCCR) ............................................................................... 10-6 System Clock Mode Register (SCMR) ................................................................................. 10-7 Dual-Bus Architecture .......................................................................................................... 11-2 Memory Controller Machine Selection................................................................................. 11-5 Simple System Configuration ............................................................................................... 11-6 Basic Memory Controller Operation..................................................................................... 11-7 Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............................11-11 Base Registers (BRx) .......................................................................................................... 11-13 Option Registers (ORx)—SDRAM Mode .......................................................................... 11-15 ORx —GPCM Mode........................................................................................................... 11-17 ORx—UPM Mode .............................................................................................................. 11-19 60x/Local SDRAM Mode Register (PSDMR/LSDMR) .................................................... 11-20 Machine x Mode Registers (MxMR) .................................................................................. 11-26 Memory Data Register (MDR) ........................................................................................... 11-29 Memory Address Register (MAR)...................................................................................... 11-29 60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30 Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-30 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31 Local Bus-Assigned SDRAM Refresh Timer (LSRT)........................................................ 11-32 Memory Refresh Timer Prescaler Register (MPTPR) ........................................................ 11-32 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) ......................... 11-34 PRETOACT = 2 (2 Clock Cycles)...................................................................................... 11-39 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor liii Figures Figure Number 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 11-43 11-44 11-45 11-46 11-47 11-48 11-49 11-50 11-51 11-52 11-53 11-54 11-55 11-56 11-57 11-58 11-59 11-60 Title Page Number ACTTORW = 2 (2 Clock Cycles)....................................................................................... 11-40 CL = 2 (2 Clock Cycles) ..................................................................................................... 11-40 LDOTOPRE = 2 (–2 Clock Cycles).................................................................................... 11-41 WRC = 2 (2 Clock Cycles) ................................................................................................. 11-41 RFRC = 4 (6 Clock Cycles) ................................................................................................ 11-42 EAMUX = 1........................................................................................................................ 11-42 BUFCMD = 1...................................................................................................................... 11-43 SDRAM Single-Beat Read, Page Closed, CL = 3 .............................................................. 11-43 SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 11-44 SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 11-44 SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 11-44 SDRAM Single-Beat Write, Page Hit................................................................................. 11-45 SDRAM Three-Beat Burst Write, Page Closed .................................................................. 11-45 SDRAM Read-after-Read Pipeline, Page Hit, CL = 3........................................................ 11-45 SDRAM Write-after-Write Pipelined, Page Hit.................................................................. 11-46 SDRAM Read-after-Write Pipelined, Page Hit .................................................................. 11-46 SDRAM Mode-Set Command Timing ............................................................................... 11-47 Mode Data Bit Settings ....................................................................................................... 11-47 SDRAM Bank-Staggered CBR Refresh Timing................................................................. 11-48 GPCM-to-SRAM Configuration......................................................................................... 11-52 GPCM Peripheral Device Interface .................................................................................... 11-54 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................................. 11-55 GPCM Memory Device Interface ....................................................................................... 11-55 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)....................... 11-56 GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)....................... 11-56 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) .................... 11-57 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1) .................... 11-57 GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1) ................... 11-58 GPCM Read Followed by Read (ORx[29–30] = 00, Fastest Timing) ................................ 11-59 GPCM Read Followed by Read (ORx[29–30] = 01).......................................................... 11-60 GPCM Read Followed by Write (ORx[29–30] = 01) ......................................................... 11-60 GPCM Read Followed by Write (ORx[29–30] = 10) ......................................................... 11-61 External Termination of GPCM Access.............................................................................. 11-62 User-Programmable Machine Block Diagram.................................................................... 11-64 RAM Array Indexing .......................................................................................................... 11-65 Memory Refresh Timer Request Block Diagram ............................................................... 11-66 Memory Controller UPM Clock Scheme for Integer Clock Ratios.................................... 11-68 Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios ................................................................................................................... 11-69 UPM Signals Timing Example ........................................................................................... 11-70 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 liv Freescale Semiconductor Figures Figure Number 11-61 11-62 11-63 11-64 11-65 11-66 11-67 11-68 11-69 11-70 11-71 11-72 11-73 11-74 11-75 11-76 11-77 11-78 11-79 11-80 11-81 11-82 11-83 11-84 11-85 11-86 12-1 12-2 12-3 12-4 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 14-3 14-4 Title Page Number RAM Array and Signal Generation .................................................................................... 11-71 The RAM Word................................................................................................................... 11-71 CS Signal Selection............................................................................................................. 11-76 BS Signal Selection............................................................................................................. 11-76 UPM Read Access Data Sampling...................................................................................... 11-79 Wait Mechanism Timing for Internal and External Synchronous Masters ......................... 11-80 DRAM Interface Connection to the 60x Bus (64-Bit Port Size) ........................................ 11-82 Single-Beat Read Access to FPM DRAM .......................................................................... 11-84 Single-Beat Write Access to FPM DRAM ......................................................................... 11-85 Burst Read Access to FPM DRAM (No LOOP) ................................................................ 11-86 Burst Read Access to FPM DRAM (LOOP) ...................................................................... 11-87 Burst Write Access to FPM DRAM (No LOOP)................................................................ 11-88 Refresh Cycle (CBR) to FPM DRAM ................................................................................ 11-89 Exception Cycle .................................................................................................................. 11-90 FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)................. 11-92 MPC8280/EDO Interface Connection to the 60x Bus ........................................................ 11-93 Single-Beat Read Access to EDO DRAM.......................................................................... 11-94 Single-Beat Write Access to EDO DRAM ......................................................................... 11-95 Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States ...................................................................................................................... 11-96 Burst Read Access to EDO DRAM .................................................................................... 11-97 Burst Write Access to EDO DRAM ................................................................................... 11-98 Refresh Cycle (CBR) to EDO DRAM................................................................................ 11-99 Exception Cycle For EDO DRAM ................................................................................... 11-100 Pipelined Bus Operation and Memory Access in 60x-Compatible Mode ........................ 11-104 External Master Access (GPCM)...................................................................................... 11-105 External Master Configuration with SDRAM Device...................................................... 11-106 L2 Cache in Copy-Back Mode.............................................................................................. 12-2 External L2 Cache in Write-Through Mode ......................................................................... 12-4 External L2 Cache in ECC/Parity Mode............................................................................... 12-6 Read Access with L2 Cache.................................................................................................. 12-8 Test Logic Block Diagram .................................................................................................... 13-2 TAP Controller State Machine .............................................................................................. 13-3 Output Pin Cell (O.Pin)......................................................................................................... 13-4 Observe-Only Input Pin Cell (I.Obs) .................................................................................... 13-4 Output Control Cell (IO.CTL) .............................................................................................. 13-5 General Arrangement of Bidirectional Pin Cells .................................................................. 13-5 CPM Block Diagram............................................................................................................. 14-3 Communications Processor (CP) Block Diagram................................................................. 14-6 RISC Controller Configuration Register (RCCR.................................................................. 14-9 RISC Time-Stamp Control Register (RTSCR) ................................................................... 14-11 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lv Figures Figure Number 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 Title Page Number RISC Time-Stamp Register (RTSR) ................................................................................... 14-11 CP Command Register (CPCR).......................................................................................... 14-12 Internal RAM Block Diagram............................................................................................. 14-18 Internal Data RAM Memory Map ...................................................................................... 14-19 Instruction RAM Partitioning ............................................................................................. 14-20 RISC Timer Table RAM Usage .......................................................................................... 14-24 RISC Timer Command Register (TM_CMD) .................................................................... 14-25 RISC Timer Event Register (RTER)/Mask Register (RTMR)............................................ 14-26 SI Block Diagram.................................................................................................................. 15-2 Various Configurations of a Single TDM Channel ............................................................... 15-5 Dual TDM Channel Example ............................................................................................... 15-6 Enabling Connections to the TSA......................................................................................... 15-8 One TDM Channel with Static Frames and Independent Rx and Tx Routes ....................... 15-9 One TDM Channel with Shadow RAM for Dynamic Route Change................................. 15-10 SIx RAM Entry Fields ........................................................................................................ 15-10 Using the SWTR Feature .................................................................................................... 15-12 Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size .................... 15-16 SI Global Mode Registers (SIxGMR)................................................................................. 15-17 SI Mode Registers (SIxMR) ............................................................................................... 15-18 One-Clock Delay from Sync to Data (xFSD = 01)............................................................. 15-20 No Delay from Sync to Data (xFSD = 00).......................................................................... 15-20 Falling Edge (FE) Effect When CE = 1 and xFSD = 01..................................................... 15-21 Falling Edge (FE) Effect When CE = 0 and xFSD = 01..................................................... 15-21 Falling Edge (FE) Effect When CE = 1 and xFSD = 00..................................................... 15-22 Falling Edge (FE) Effect When CE = 0 and xFSD = 00..................................................... 15-23 SIx RAM Shadow Address Registers (SIxRSR) ................................................................ 15-24 SI Command Register (SIxCMDR) .................................................................................... 15-24 SI Status Registers (SIxSTR) .............................................................................................. 15-25 Dual IDL Bus Application Example ................................................................................... 15-26 IDL Terminal Adaptor......................................................................................................... 15-27 IDL Bus Signals .................................................................................................................. 15-28 GCI Bus Signals.................................................................................................................. 15-31 CPM Multiplexing Logic (CMX) Block Diagram................................................................ 16-2 Enabling Connections to the TSA......................................................................................... 16-4 Bank of Clocks...................................................................................................................... 16-5 CMX UTOPIA Address Register (CMXUAR) .................................................................... 16-7 Connection of the Master Address........................................................................................ 16-9 Connection of the Slave Address .......................................................................................... 16-9 Multi-PHY Receive Address Multiplexing......................................................................... 16-11 CMX SI1 Clock Route Register (CMXSI1CR) .................................................................. 16-12 CMX SI2 Clock Route Register (CMXSI2CR) .................................................................. 16-13 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lvi Freescale Semiconductor Figures Figure Number 16-10 16-11 16-12 17-1 17-2 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 21-1 Title Page Number CMX FCC Clock Route Register (CMXFCR) ................................................................... 16-14 CMX SCC Clock Route Register (CMXSCR) ................................................................... 16-16 CMX SMC Clock Route Register (CMXSMR) ................................................................. 16-19 Baud-Rate Generator (BRG) Block Diagram ....................................................................... 17-1 Baud-Rate Generator Configuration Registers (BRGCx)..................................................... 17-2 Timer Block Diagram ........................................................................................................... 18-1 Timer Cascaded Mode Block Diagram................................................................................. 18-3 Timer Global Configuration Register 1 (TGCR1) ................................................................ 18-4 Timer Global Configuration Register 2 (TGCR2) ................................................................ 18-5 Timer Mode Registers (TMR1–TMR4)................................................................................ 18-6 Timer Reference Registers (TRR1–TRR4)........................................................................... 18-7 Timer Capture Registers (TCR1–TCR4) .............................................................................. 18-7 Timer Counter Registers (TCN1–TCN4).............................................................................. 18-7 Timer Event Registers (TER1–TER4) .................................................................................. 18-8 SDMA Data Paths ................................................................................................................. 19-1 SDMA Bus Arbitration (Transaction Steal).......................................................................... 19-3 SDMA Status Register (SDSR) ............................................................................................ 19-3 SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM) ........................................... 19-4 IDMA Transfer Buffer in the Dual-Port RAM ..................................................................... 19-7 Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer (Size = 128 Bytes) ............................................................................................................ 19-8 IDMAx Channel BD Table.................................................................................................. 19-15 DCM Parameters................................................................................................................. 19-18 IDMA Event/Mask Registers (IDSR/IDMR) ..................................................................... 19-23 IDMA BD Structure............................................................................................................ 19-23 SCC Block Diagram.............................................................................................................. 20-2 GSMR_H—General SCC Mode Register (High Order)....................................................... 20-3 GSMR_L—General SCC Mode Register (Low Order)........................................................ 20-5 Data Synchronization Register (DSR) .................................................................................. 20-9 Transmit-on-Demand Register (TODR) ............................................................................. 20-10 SCC Buffer Descriptors (BDs)............................................................................................ 20-11 SCC BD and Buffer Memory Structure .............................................................................. 20-12 Function Code Registers (RFCR and TFCR) ..................................................................... 20-15 Output Delay from RTS Asserted for Synchronous Protocols ........................................... 20-18 Output Delay from CTS Asserted for Synchronous Protocols ........................................... 20-18 CTS Lost in Synchronous Protocols ................................................................................... 20-19 Using CD to Control Synchronous Protocol Reception...................................................... 20-20 DPLL Receiver Block Diagram .......................................................................................... 20-21 DPLL Transmitter Block Diagram...................................................................................... 20-22 DPLL Encoding Examples.................................................................................................. 20-23 UART Character Format ....................................................................................................... 21-1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lvii Figures Figure Number 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 22-12 22-13 22-14 22-15 22-16 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 24-1 24-2 24-3 24-4 24-5 Title Page Number Two UART Multidrop Configurations.................................................................................. 21-7 Control Character Table ........................................................................................................ 21-8 Transmit Out-of-Sequence Register (TOSEQ) ................................................................... 21-10 Asynchronous UART Transmitter ...................................................................................... 21-11 Protocol-Specific Mode Register for UART (PSMR) ........................................................ 21-13 SCC UART Receiving using RxBDs.................................................................................. 21-16 SCC UART Receive Buffer Descriptor (RxBD) ................................................................ 21-17 SCC UART Transmit Buffer Descriptor (TxBD) ............................................................... 21-18 SCC UART Interrupt Event Example ................................................................................. 21-20 SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................................... 21-20 SCC Status Register for UART Mode (SCCS) ................................................................... 21-21 HDLC Framing Structure...................................................................................................... 22-2 HDLC Address Recognition ................................................................................................. 22-4 HDLC Mode Register (PSMR)............................................................................................. 22-7 SCC HDLC Receive Buffer Descriptor (RxBD) .................................................................. 22-8 SCC HDLC Receiving Using RxBDs................................................................................. 22-11 SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 22-12 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................................ 22-13 SCC HDLC Interrupt Event Example................................................................................. 22-15 CC HDLC Status Register (SCCS) ..................................................................................... 22-15 Typical HDLC Bus Multi-Master Configuration................................................................ 22-19 Typical HDLC Bus Single-Master Configuration............................................................... 22-20 Detecting an HDLC Bus Collision...................................................................................... 22-21 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................................... 22-21 HDLC Bus Transmission Line Configuration .................................................................... 22-22 Delayed RTS Mode............................................................................................................. 22-22 HDLC Bus TDM Transmission Line Configuration .......................................................... 22-23 Classes of BISYNC Frames.................................................................................................. 23-1 Control Character Table and RCCM..................................................................................... 23-6 BISYNC SYNC (BSYNC) ................................................................................................... 23-7 BISYNC DLE (BDLE) ......................................................................................................... 23-8 Protocol-Specific Mode Register for BISYNC (PSMR) .................................................... 23-10 SCC BISYNC RxBD .......................................................................................................... 23-12 SCC BISYNC Transmit BD (TxBD) .................................................................................. 23-14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ................................. 23-16 SCC Status Registers (SCCS) ............................................................................................. 23-16 Sending Transparent Frames between MPC8280s ............................................................... 24-4 SCC Transparent Receive Buffer Descriptor (RxBD) .......................................................... 24-8 SCC Transparent Transmit Buffer Descriptor (TxBD) ....................................................... 24-10 SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 24-11 SCC Status Register in Transparent Mode (SCCS) ............................................................ 24-12 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lviii Freescale Semiconductor Figures Figure Number 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 25-10 26-1 26-2 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 27-17 27-18 27-19 27-20 27-21 28-1 28-2 28-3 28-4 28-5 28-6 28-7 28-8 Title Page Number Ethernet Frame Structure ...................................................................................................... 25-1 Ethernet Block Diagram........................................................................................................ 25-2 Connecting the MPC8280 to Ethernet .................................................................................. 25-4 Ethernet Address Recognition Flowchart ........................................................................... 25-11 Ethernet Mode Register (PSMR) ........................................................................................ 25-14 SCC Ethernet RxBD ........................................................................................................... 25-16 Ethernet Receiving using RxBDs ....................................................................................... 25-18 SCC Ethernet TxBD............................................................................................................ 25-19 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................................... 25-20 Ethernet Interrupt Events Example ..................................................................................... 25-21 LocalTalk Frame Format....................................................................................................... 26-1 Connecting the MPC8280 to LocalTalk................................................................................ 26-3 USB Interface........................................................................................................................ 27-3 USB Function Block Diagram ............................................................................................. 27-5 USB Controller Operating Modes......................................................................................... 27-6 USB Controller Block Diagram ........................................................................................... 27-8 USB Controller Operating Modes......................................................................................... 27-9 Endpoint Pointer Registers (EPxPTR) ................................................................................ 27-13 Frame Number (FRAME_N) in Function Mode—Updated by USB Controller................ 27-15 Frame Number (FRAME_N) in Host Mode—Updated by Application Software ............. 27-15 USB Function Code Registers (RFCR and TFCR)............................................................. 27-16 USB Mode Register (USMOD) .......................................................................................... 27-17 USB Slave Address Register (USADR) ............................................................................. 27-18 USB Endpoint Registers (USEP1–USEP4) ........................................................................ 27-18 USB Command Register (USCOM) ................................................................................... 27-20 USB Event Register (USBER)............................................................................................ 27-20 USB Status Register (USBS) .............................................................................................. 27-21 USB Start of Frame Timer (USSFT)................................................................................... 27-22 USB Memory Structure....................................................................................................... 27-23 USB Receive Buffer Descriptor (Rx BD),.......................................................................... 27-24 USB Transmit Buffer Descriptor (Tx BD),......................................................................... 27-26 USB Transmit Buffer Descriptor (Tx BD),......................................................................... 27-28 USB Transaction Buffer Descriptor (TrBD), ...................................................................... 27-30 SMC Block Diagram............................................................................................................. 28-1 SMC Mode Registers (SMCMR1/SMCMR2)...................................................................... 28-3 SMC Memory Structure........................................................................................................ 28-5 SMC Function Code Registers (RFCR/TFCR)..................................................................... 28-8 SMC UART Frame Format................................................................................................. 28-10 SMC UART RxBD ............................................................................................................. 28-14 RxBD Example ................................................................................................................... 28-16 SMC UART TxBD.............................................................................................................. 28-17 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lix Figures Figure Number 28-9 28-10 28-11 28-12 28-13 28-14 28-15 28-16 28-17 28-18 28-19 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 30-1 30-2 30-3 30-4 30-5 30-6 30-7 30-8 Title Page Number SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 28-18 SMC UART Interrupts Example......................................................................................... 28-19 Synchronization with SMSYNx .......................................................................................... 28-23 Synchronization with the TSA............................................................................................ 28-24 SMC Transparent RxBD ..................................................................................................... 28-26 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 28-28 SMC Monitor Channel RxBD............................................................................................. 28-32 SMC Monitor Channel TxBD............................................................................................. 28-33 SMC C/I Channel RxBD..................................................................................................... 28-33 SMC C/I Channel TxBD..................................................................................................... 28-34 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 28-35 BD Structure for One MCC .................................................................................................. 29-3 TSTATE High Byte ............................................................................................................... 29-7 INTMSK Mask Bits .............................................................................................................. 29-8 Channel Mode Register (CHAMR) ...................................................................................... 29-8 Rx Internal State (RSTATE) High Byte .............................................................................. 29-10 Channel Mode Register (CHAMR)—Transparent Mode ................................................... 29-12 INTMSK Mask Bits ............................................................................................................ 29-15 Channel Mode Register (CHAMR)—CES Mode............................................................... 29-15 Extended Channel Mode Register (ECHAMR).................................................................. 29-21 SS7 Configuration Register (SS7_OPT) ............................................................................. 29-23 Mask1 Format ..................................................................................................................... 29-25 Mask2 Format ..................................................................................................................... 29-25 Super Channel Table Entry ................................................................................................. 29-28 Transmitter Super Channel Example .................................................................................. 29-30 Receiver Super Channel with Slot Synchronization Example............................................ 29-31 Receiver Super Channel without Slot Synchronization Example....................................... 29-32 SI MCC Configuration Register (MCCF)........................................................................... 29-32 Interrupt Circular Table....................................................................................................... 29-35 MCC Event Register (MCCE)/Mask Register (MCCM).................................................... 29-36 Interrupt Circular Table Entry............................................................................................. 29-37 MCC Receive Buffer Descriptor (RxBD)........................................................................... 29-42 MCC Transmit Buffer Descriptor (TxBD).......................................................................... 29-44 FCC Block Diagram.............................................................................................................. 30-3 General FCC Mode Register (GFMR).................................................................................. 30-4 General FCC Expansion Mode Register (GFEMR) ............................................................. 30-8 FCC Data Synchronization Register (FDSR) ....................................................................... 30-9 FCC Transmit-on-Demand Register (FTODR)..................................................................... 30-9 FCC Memory Structure....................................................................................................... 30-10 Buffer Descriptor Format.................................................................................................... 30-11 Function Code Register (FCRx) ......................................................................................... 30-14 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lx Freescale Semiconductor Figures Figure Number 30-9 30-10 30-11 30-12 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 31-11 31-12 31-13 31-14 31-15 31-16 31-17 31-18 31-19 31-20 31-21 31-22 31-23 31-24 31-25 31-26 31-27 31-28 31-29 31-30 31-31 31-32 31-33 31-34 31-35 31-36 31-37 Title Page Number Output Delay from RTS Asserted ....................................................................................... 30-18 Output Delay from CTS Asserted....................................................................................... 30-18 CTS Lost ............................................................................................................................. 30-19 Using CD to Control Reception .......................................................................................... 30-20 APC Scheduling Table Mechanism ...................................................................................... 31-9 VBR Pacing Using the GCRA (Leaky Bucket Algorithm) ................................................ 31-12 External CAM Data Input Fields ........................................................................................ 31-14 External CAM Output Fields .............................................................................................. 31-14 Address Compression Mechanism...................................................................................... 31-15 General VCOFFSET Formula for Contiguous VCLTs ....................................................... 31-16 VP Pointer Address Compression....................................................................................... 31-17 VC Pointer Address Compression ...................................................................................... 31-18 ATM Address Recognition Flowchart ................................................................................ 31-19 MPC8280’s ABR Basic Model ........................................................................................... 31-20 ABR Transmit Flow ............................................................................................................ 31-22 ABR Transmit Flow (continued) ........................................................................................ 31-23 ABR Transmit Flow (continued) ........................................................................................ 31-24 ABR Receive Flow ............................................................................................................. 31-25 Rate Format for RM Cells................................................................................................... 31-26 Rate Formula for RM Cells................................................................................................. 31-26 Performance Monitoring Cell Structure (FMCs and BRCs)............................................... 31-29 FMC, BRC Insertion ........................................................................................................... 31-31 Format of User-Defined Cells............................................................................................. 31-32 External CAM Address in UDC Extended Address Mode................................................. 31-33 ATM-to-TDM Interworking................................................................................................ 31-34 VCI Filtering Enable Bits ................................................................................................... 31-39 Global Mode Entry (GMODE) ........................................................................................... 31-40 Example of a 1024-Entry Receive Connection Table ......................................................... 31-42 Receive Connection Table (RCT) Entry ............................................................................. 31-43 AAL5 Protocol-Specific RCT............................................................................................. 31-46 AAL5-ABR Protocol-Specific RCT ................................................................................... 31-47 AAL1 Protocol-Specific RCT............................................................................................. 31-47 AAL0 Protocol-Specific RCT............................................................................................. 31-49 Transmit Connection Table (TCT) Entry ............................................................................ 31-50 AAL5 Protocol-Specific TCT ............................................................................................. 31-53 AAL1 Protocol-Specific TCT ............................................................................................. 31-54 AAL0 Protocol-Specific TCT ............................................................................................. 31-55 Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific ......................... 31-56 UBR+ Protocol-Specific TCTE .......................................................................................... 31-57 ABR Protocol-Specific TCTE ............................................................................................ 31-58 OAM Performance Monitoring Table................................................................................. 31-60 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxi Figures Figure Number 31-38 31-39 31-40 31-41 31-42 31-43 31-44 31-45 31-46 31-47 31-48 31-49 31-50 31-51 31-52 31-53 31-54 31-55 31-56 31-57 31-58 31-59 31-60 31-61 31-62 31-63 31-64 31-65 31-66 31-67 31-68 31-69 32-1 32-2 32-3 32-4 32-5 32-6 32-7 32-8 32-9 Title Page Number ATM Pace Control Data Structure ...................................................................................... 31-62 The APC Scheduling Table Structure ................................................................................. 31-63 Control Slot ......................................................................................................................... 31-64 Transmit Buffers and BD Table Example ........................................................................... 31-65 Receive Static Buffer Allocation Example ......................................................................... 31-66 Receive Global Buffer Allocation Example ....................................................................... 31-67 Free Buffer Pool Structure .................................................................................................. 31-67 Free Buffer Pool Entry ........................................................................................................ 31-68 AAL5 RxBD ....................................................................................................................... 31-69 AAL1 RxBD ....................................................................................................................... 31-71 AAL0 RxBD ....................................................................................................................... 31-72 User-Defined Cell—RxBD Extension ................................................................................ 31-73 AAL5 TxBD ....................................................................................................................... 31-74 AAL1 TxBD ....................................................................................................................... 31-75 AAL0 TxBDs ...................................................................................................................... 31-76 User-Defined Cell—TxBD Extension ................................................................................ 31-77 AAL1 Sequence Number (SN) Protection Table ................................................................ 31-78 Interrupt Queue Structure.................................................................................................... 31-79 Interrupt Queue Entry ......................................................................................................... 31-80 UTOPIA Master Mode Signals........................................................................................... 31-81 UTOPIA Slave Mode Signals ............................................................................................. 31-83 FCC ATM Mode Register (FPSMR) .................................................................................. 31-86 ATM Event Register (FCCE)/FCC Mask Register (FCCM) .............................................. 31-88 COMM_INFO Field ........................................................................................................... 31-89 FCC Transmit Internal Rate Register (FTIRR)................................................................... 31-92 FCC Transmit Internal Rate Clocking ................................................................................ 31-92 FCC Transmit Internal Rate Port Enable Register (FIRPERx)........................................... 31-94 FCC Internal Rate Event Register (FIRERx)...................................................................... 31-95 FCC Internal Rate Selection Register HI (FIRSRx_HI) ..................................................... 31-96 FCC Internal Rate Selection Register LO (FIRSRx_LO)................................................... 31-96 AAL1 CES SRTS Generation Using External Logic.......................................................... 31-97 AAL1 CES SRTS Clock Recovery Using External Logic ................................................. 31-98 AAL1 Transmit Cell Format ................................................................................................. 32-3 AAL1 SDT Cell Types.......................................................................................................... 32-3 AAL1 Framing Formats........................................................................................................ 32-4 AAL1 CES Receiver Data flow ............................................................................................ 32-6 ATM-to-TDM Interworking.................................................................................................. 32-7 TDM-to-ATM Interworking.................................................................................................. 32-8 Mapping CAS Data on a Serial Interface............................................................................ 32-10 Internal CAS Block Formats............................................................................................... 32-11 Mapping CAS Entry............................................................................................................ 32-12 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxii Freescale Semiconductor Figures Figure Number 32-10 32-11 32-12 32-13 32-14 32-15 32-16 32-17 32-18 32-19 32-20 32-21 32-22 32-23 32-24 32-25 32-26 32-27 32-28 32-29 32-30 32-31 32-32 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 33-13 33-14 33-15 33-16 33-17 33-18 Title Page Number AAL1 CES CAS Routing Table (CRT) .............................................................................. 32-12 AAL1 CES CAS Routing Table Entry................................................................................ 32-12 CAS Flow TDM-to-ATM.................................................................................................... 32-13 CAS Flow ATM-to-TDM.................................................................................................... 32-14 Data Structure for ATM-to-TDM Adaptive Slip Control ................................................... 32-16 CES Adaptive Threshold Table........................................................................................... 32-17 Pre-Underrun Sequence ...................................................................................................... 32-18 Pre-Overrun Sequence ........................................................................................................ 32-19 Recoverable Sync Fail Sequence Options .......................................................................... 32-20 3-Step-SN-Algorithm .......................................................................................................... 32-21 Pointer Verification Mechanism.......................................................................................... 32-22 Receive Connection Table (RCT) Entry ............................................................................. 32-26 AAL1 CES Protocol-Specific RCT .................................................................................... 32-29 Transmit Connection Table (TCT) Entry ........................................................................... 32-32 AAL1 CES Protocol-Specific TCT..................................................................................... 32-34 Outgoing CAS Status Register (OCASSR)......................................................................... 32-36 Transmit Buffers and BD Table Example ........................................................................... 32-37 Receive Buffers and BD Table Example ............................................................................ 32-38 AAL1 CES RxBD............................................................................................................... 32-39 AAL1 CES TxBD ............................................................................................................... 32-40 AAL1 CES Interrupt Queue Entry...................................................................................... 32-41 AAL1 Sequence Number (SN) Protection Table ................................................................ 32-43 TDM-to-ATM Timing Issue................................................................................................ 32-45 AAL2 Data Units .................................................................................................................. 33-1 AAL2 Sublayer Structure...................................................................................................... 33-2 AAL2 Switching Example .................................................................................................... 33-3 Round Robin Priority ............................................................................................................ 33-6 Fixed Priority Mode .............................................................................................................. 33-7 AAL2 Protocol-Specific Transmit Connection Table (TCT)................................................ 33-9 CPS Tx Queue Descriptor (TxQD) ..................................................................................... 33-13 Buffer Structure Example for CPS Packets......................................................................... 33-14 CPS TxBD........................................................................................................................... 33-15 CPS Packet Header Format................................................................................................. 33-16 SSSAR Tx Queue Descriptor.............................................................................................. 33-16 SSSAR TxBD ..................................................................................................................... 33-18 CID Mapping Process ......................................................................................................... 33-21 AAL2 Switching ................................................................................................................. 33-22 AAL2 Protocol-Specific Receive Connection Table (RCT) ............................................... 33-23 CPS Rx Queue Descriptor................................................................................................... 33-26 CPS Receive Buffer Descriptor .......................................................................................... 33-27 CPS Switch Rx Queue Descriptor ...................................................................................... 33-29 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxiii Figures Figure Number 33-19 33-20 33-21 33-22 33-23 33-24 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 34-11 34-12 34-13 34-14 34-15 34-16 34-17 34-18 34-19 34-20 34-21 34-22 34-23 34-24 34-25 34-26 34-27 34-28 34-29 34-30 34-31 34-32 34-33 35-1 Title Page Number Switch Receive/Transmit Buffer Descriptor ....................................................................... 33-29 SSSAR Rx Queue Descriptor ............................................................................................. 33-31 SSSAR Receive Buffer Descriptor ..................................................................................... 33-32 UDC Header Table.............................................................................................................. 33-37 AAL2 Interrupt Queue Entry CID ≠ 0 ................................................................................ 33-38 AAL2 Interrupt Queue Entry CID = 0 ................................................................................ 33-39 Basic Concept of IMA .......................................................................................................... 34-5 Illustration of IMA Frames ................................................................................................... 34-6 IMA Microcode Overview.................................................................................................... 34-7 IMA Frame and ICP Cell Formats........................................................................................ 34-8 IMA Transmit Task Interaction........................................................................................... 34-10 Transmit Queue Normal Operating State............................................................................ 34-12 Transmit Queue Behavior: Link Clock Rate Same as TRL ................................................ 34-12 Transmit Queue Behavior: Link Clock Rate Slower than TRL .......................................... 34-13 Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence ...... 34-14 IMA Receive Task Interaction ............................................................................................ 34-15 IMA Microcode: Receive Process ...................................................................................... 34-17 IMA Root Table Data Structures......................................................................................... 34-21 IMA Control (IMACNTL).................................................................................................. 34-25 IMA Group Transmit Control (IGTCNTL)......................................................................... 34-27 IMA Group Transmit State (IGTSTATE)............................................................................ 34-27 Transmit Group Order Table Entry ..................................................................................... 34-28 IMA Group Receive Control (IGRCNTL).......................................................................... 34-34 IMA Group Receive State (IGRSTATE)............................................................................. 34-34 IMA Receive Group Frame Size (IGRSTATE) .................................................................. 34-35 Receive Group Order Table Entry....................................................................................... 34-36 IMA Link Transmit Control (ILTCNTL)............................................................................ 34-38 IMA Link Transmit State (ILTSTATE) ............................................................................... 34-38 IMA Transmit Interrupt Status (ITINTSTAT)..................................................................... 34-39 IMA Link Receive Control (ILRCNTL)............................................................................. 34-41 IMA Link Receive State (ILRSTATE)................................................................................ 34-42 IMA Transmit Queue .......................................................................................................... 34-44 Cell Buffer in Delay Compensation Buffer......................................................................... 34-44 IMA Delay Compensation Buffer ....................................................................................... 34-45 IMA Interrupt Queue Entry................................................................................................. 34-45 IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR) ............................................ 34-50 COMM_INFO Field ........................................................................................................... 34-53 IMA Microcode/Software Interaction................................................................................. 34-54 Near-End versus Far-End .................................................................................................... 34-60 Serial ATM Using FCC2 and TC Blocks (Single Channel).................................................. 35-1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxiv Freescale Semiconductor Figures Figure Number 35-2 35-3 35-4 35-5 35-6 35-7 35-8 35-9 35-10 35-11 35-12 36-1 36-2 36-3 36-4 36-5 36-6 36-7 36-8 36-9 36-10 36-11 37-1 37-2 37-3 37-4 37-5 37-6 37-7 37-8 37-9 38-1 38-2 39-1 39-2 39-3 39-4 39-5 39-6 39-7 39-8 Title Page Number TC Layer Block Diagram...................................................................................................... 35-3 TC Cell Delineation State Machine ...................................................................................... 35-4 HEC: Receiver Modes of Operation ..................................................................................... 35-5 TC Layer Mode Registers (TCMODEx)............................................................................... 35-7 Cell Delineation State Machine Registers (CDSMRx) ......................................................... 35-8 TC Layer Event Registers (TCERx) ..................................................................................... 35-9 TC Layer General Event Register (TCGER) ...................................................................... 35-10 TC Layer General Status Register (TCGSR) ...................................................................... 35-11 TC Operation in FCC External Rate Mode......................................................................... 35-14 TC Operation in FCC Internal Rate Mode (Sub Rate Mode) ............................................. 35-14 Example of Serial ATM Application .................................................................................. 35-15 Ethernet Frame Structure ...................................................................................................... 36-1 Ethernet Block Diagram ....................................................................................................... 36-2 Connecting the MPC8280 to Ethernet .................................................................................. 36-4 Connecting the MPC8280 to Ethernet (RMII)...................................................................... 36-5 Ethernet Address Recognition Flowchart ........................................................................... 36-16 FCC Ethernet Mode Registers (FPSMRx) .......................................................................... 36-20 Ethernet Event Register (FCCE)/Mask Register (FCCM).................................................. 36-22 Ethernet Interrupt Events Example ..................................................................................... 36-23 Fast Ethernet Receive Buffer (RxBD) ................................................................................ 36-24 Ethernet Receiving Using RxBDs....................................................................................... 36-26 Fast Ethernet Transmit Buffer (TxBD) ............................................................................... 36-27 HDLC Framing Structure...................................................................................................... 37-2 HDLC Address Recognition Example.................................................................................. 37-5 HDLC Mode Register (FPSMR)........................................................................................... 37-8 FCC HDLC Receiving Using RxBDs................................................................................. 37-10 FCC HDLC Receive Buffer Descriptor (RxBD) ................................................................ 37-11 FCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 37-12 HDLC Event Register (FCCE)/Mask Register (FCCM) .................................................... 37-14 HDLC Interrupt Event Example ......................................................................................... 37-16 FCC Status Register (FCCS)............................................................................................... 37-16 In-Line Synchronization Pattern ........................................................................................... 38-2 Sending Transparent Frames between MPC8280s ............................................................... 38-4 SPI Block Diagram ............................................................................................................... 39-1 Single-Master/Multi-Slave Configuration ............................................................................ 39-3 Multi-Master Configuration.................................................................................................. 39-5 SPMODE—SPI Mode Register ............................................................................................ 39-6 SPI Transfer Format with SPMODE[CP] = 0....................................................................... 39-7 SPI Transfer Format with SPMODE[CP] = 1....................................................................... 39-8 SPIE/SPIM—SPI Event/Mask Registers .............................................................................. 39-9 SPCOM—SPI Command Register ..................................................................................... 39-10 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxv Figures Figure Number 39-9 39-10 39-11 39-12 40-1 40-2 40-3 40-4 40-5 40-6 40-7 40-8 40-9 40-10 40-11 40-12 40-13 40-14 41-1 41-2 41-3 41-4 41-5 41-6 41-7 Title Page Number RFCR/TFCR—Function Code Registers............................................................................ 39-12 SPI Memory Structure......................................................................................................... 39-13 SPI RxBD............................................................................................................................ 39-14 SPI TxBD ............................................................................................................................ 39-15 I2C Controller Block Diagram .............................................................................................. 40-1 I2C Master/Slave General Configuration.............................................................................. 40-2 I2C Transfer Timing .............................................................................................................. 40-3 I2C Master Write Timing ...................................................................................................... 40-3 I2C Master Read Timing ....................................................................................................... 40-4 I2C Mode Register (I2MOD) ................................................................................................ 40-6 I2C Address Register (I2ADD) ............................................................................................. 40-7 I2C Baud Rate Generator Register (I2BRG)......................................................................... 40-7 I2C Event/Mask Registers (I2CER/I2CMR)......................................................................... 40-8 I2C Command Register (I2COM) ......................................................................................... 40-8 I2C Function Code Registers (RFCR/TFCR)...................................................................... 40-10 I2C Memory Structure......................................................................................................... 40-12 I2C RxBD............................................................................................................................ 40-13 I2C TxBD ............................................................................................................................ 40-14 Port Open-Drain Registers (PODRA–PODRD) ................................................................... 41-2 Port Data Registers (PDATA–PDATD) ................................................................................ 41-3 Port Data Direction Register (PDIR) .................................................................................... 41-3 Port Pin Assignment Register (PPARA–PPARD)................................................................. 41-4 Special Options Registers (PSORA–POSRD) ...................................................................... 41-5 Port Functional Operation ..................................................................................................... 41-6 Primary and Secondary Option Programming ...................................................................... 41-8 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxvi Freescale Semiconductor Tables Table Number 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 5-1 5-2 Title Tables Page Number MPC8280 Serial Protocols.................................................................................................... 1-10 Serial Performance ................................................................................................................ 1-11 MPC8270 Serial Performance .............................................................................................. 1-12 HID0 Field Descriptions ....................................................................................................... 2-11 HID1 Field Descriptions ....................................................................................................... 2-14 HID2 Field Descriptions ....................................................................................................... 2-15 Exception Classifications for the Processor Core ................................................................. 2-22 Exceptions and Conditions.................................................................................................... 2-23 Differences Between G2_LE Core and MPC603e................................................................ 2-27 Internal Memory Map ............................................................................................................. 3-2 System Configuration and Protection Functions .................................................................... 4-2 Interrupt Source Priority Levels............................................................................................ 4-10 Encoding the Interrupt Vector ............................................................................................... 4-14 SICR Field Descriptions ....................................................................................................... 4-18 SIPRR Field Descriptions ..................................................................................................... 4-19 SCPRR_H Field Descriptions ............................................................................................... 4-20 SCPRR_L Field Descriptions ............................................................................................... 4-21 SIEXR Field Descriptions..................................................................................................... 4-26 BCR Field Descriptions ........................................................................................................ 4-27 PPC_ACR Field Descriptions ............................................................................................... 4-30 LCL_ACR Field Descriptions .............................................................................................. 4-31 SIUMCR Register Field Descriptions................................................................................... 4-34 IMMR Field Descriptions ..................................................................................................... 4-37 SYPCR Field Descriptions.................................................................................................... 4-38 TESCR1 Field Descriptions.................................................................................................. 4-39 TESCR2 Field Descriptions.................................................................................................. 4-41 L_TESCR1 Field Descriptions ............................................................................................. 4-42 L_TESCR2 Field Descriptions ............................................................................................. 4-43 TMCNTSC Field Descriptions ............................................................................................. 4-44 TMCNTAL Field Descriptions ............................................................................................. 4-45 PISCR Field Descriptions ..................................................................................................... 4-46 PITC Field Descriptions........................................................................................................ 4-47 PITR Field Descriptions........................................................................................................ 4-48 PCIBRx Field Descriptions................................................................................................... 4-49 PCIMSKx Field Descriptions ............................................................................................... 4-50 SIU Pins Multiplexing Control ............................................................................................. 4-51 Reset Causes ........................................................................................................................... 5-1 Reset Actions for Each Reset Source...................................................................................... 5-2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxvii Tables Table Number 5-3 5-4 5-5 5-6 5-7 6-1 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 Title Page Number RSR Field Descriptions........................................................................................................... 5-4 RMR Field Descriptions ......................................................................................................... 5-6 RSTCONF Connections in Multiple-MPC8280 Systems....................................................... 5-7 Configuration EPROM Addresses .......................................................................................... 5-7 Hard Reset Configuration Word Field Descriptions ............................................................... 5-8 External Signals ...................................................................................................................... 6-3 Data Bus Lane Assignments ................................................................................................. 7-13 DP[0–7] Signal Assignments ................................................................................................ 7-14 Terminology ............................................................................................................................ 8-1 Transfer Type Encoding ........................................................................................................ 8-10 Transfer Code Encoding for 60x Bus.................................................................................... 8-12 Transfer Size Signal Encoding.............................................................................................. 8-12 Burst Ordering....................................................................................................................... 8-13 Aligned Data Transfers ......................................................................................................... 8-14 Unaligned Data Transfer Example (4-Byte Example) .......................................................... 8-15 Data Bus: Read Cycle Requirements and Write Cycle Content ........................................... 8-17 Address and Size State Calculations ..................................................................................... 8-18 Data Bus Contents for Extended Write Cycles ..................................................................... 8-19 Data Bus Requirements for Extended Read Cycles.............................................................. 8-19 Address and Size State for Extended Transfers .................................................................... 8-20 PCI Terminology..................................................................................................................... 9-6 PCI Command Definitions...................................................................................................... 9-7 Internal Memory Map ........................................................................................................... 9-27 POTARx Field Descriptions ................................................................................................. 9-31 POBARx Field Descriptions ................................................................................................. 9-31 POCMRx Field Descriptions ................................................................................................ 9-32 PTCR Field Descriptions ...................................................................................................... 9-33 GPCR Field Descriptions...................................................................................................... 9-34 PCI_GCR Field Descriptions................................................................................................ 9-35 ESR Field Descriptions ......................................................................................................... 9-36 EMR Field Descriptions........................................................................................................ 9-37 ECR Field Descriptions ........................................................................................................ 9-39 PCI_EACR Field Descriptions ............................................................................................. 9-40 PCI_EDCR Field Description ............................................................................................... 9-40 PCI_ECCR Field Descriptions.............................................................................................. 9-41 PITARx Field Descriptions ................................................................................................... 9-42 PIBARx Field Descriptions .................................................................................................. 9-43 PICMRx Field Descriptions.................................................................................................. 9-44 PCI Bridge PCI Configuration Registers .............................................................................. 9-45 Vendor ID Register Description............................................................................................ 9-47 Device ID Register Description ............................................................................................ 9-47 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxviii Freescale Semiconductor Tables Table Number 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 9-49 9-50 9-51 9-52 9-53 9-54 9-55 9-56 9-57 9-58 9-59 9-60 9-61 9-62 Title Page Number PCI Bus Command Register Description.............................................................................. 9-48 PCI Bus Status Register Description..................................................................................... 9-49 Revision ID Register Description ......................................................................................... 9-50 PCI Bus Programming Interface Register Description ......................................................... 9-50 Subclass Code Register Description ..................................................................................... 9-51 PCI Bus Base Class Code Register Description ................................................................... 9-51 PCI Bus Cache Line Size Register Description .................................................................... 9-52 PCI Bus Latency Timer Register Description....................................................................... 9-52 Header Type Register Description ........................................................................................ 9-53 BIST Control Register Description....................................................................................... 9-53 PIMMRBAR Field Descriptions........................................................................................... 9-54 GPLABARx Field Descriptions............................................................................................ 9-55 Subsystem Vendor ID Register Description.......................................................................... 9-56 Subsystem Device ID Description Register.......................................................................... 9-56 PCI Bus Capabilities Pointer Register Description............................................................... 9-56 PCI Bus Interrupt Line Register Description........................................................................ 9-57 PCI Bus Interrupt Pin Register Description.......................................................................... 9-57 PCI Bus MIN GNT Description............................................................................................ 9-58 PCI Bus MAX LAT Description ........................................................................................... 9-58 PCI Bus Function Register Field Descriptions ..................................................................... 9-59 PCI Bus Arbiter Configuration Register Field Description .................................................. 9-60 Hot Swap Register Block Field Descriptions ....................................................................... 9-61 Hot Swap Control Status Register Field Descriptions .......................................................... 9-62 Bit Settings for Register Initialization Data Structure .......................................................... 9-65 IMRx Field Descriptions....................................................................................................... 9-67 OMRx Field Descriptions ..................................................................................................... 9-68 ODR Field Descriptions........................................................................................................ 9-69 IDR Field Descriptions ......................................................................................................... 9-70 IFHPR Field Descriptions ..................................................................................................... 9-72 IFTPR Field Descriptions ..................................................................................................... 9-73 IPHPR Field Descriptions ..................................................................................................... 9-74 IPTPR Field Descriptions...................................................................................................... 9-75 OFHPR Field Descriptions ................................................................................................... 9-76 OFTPR Field Descriptions.................................................................................................... 9-76 OPHPR Field Descriptions ................................................................................................... 9-77 OPTPR Field Descriptions .................................................................................................... 9-78 IFQPR Field Descriptions ..................................................................................................... 9-79 OFQPR Field Descriptions ................................................................................................... 9-80 OMISR Field Descriptions.................................................................................................... 9-80 OMIMR Field Descriptions .................................................................................................. 9-81 IMISR Field Descriptions ..................................................................................................... 9-82 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxix Tables Table Number 9-63 9-64 9-65 9-66 9-67 9-68 9-69 9-70 9-71 9-72 9-73 10-1 10-2 10-3 10-4 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 Title Page Number IMIMR Field Descriptions.................................................................................................... 9-83 MUCR Field Descriptions .................................................................................................... 9-85 QBAR Field Descriptions ..................................................................................................... 9-85 DMAMRx Field Descriptions............................................................................................... 9-90 DMASRx Field Descriptions ................................................................................................ 9-92 DMACDARx Field Descriptions .......................................................................................... 9-93 DMASARx Field Descriptions ............................................................................................. 9-93 DMADARx Field Descriptions............................................................................................. 9-94 DMABCRx Field Descriptions ............................................................................................. 9-95 DMANDARx Field Descriptions.......................................................................................... 9-96 DMA Segment Descriptor Fields.......................................................................................... 9-96 Dedicated PLL Pins .............................................................................................................. 10-5 SCCR Field Descriptions ...................................................................................................... 10-6 SCMR Field Descriptions ..................................................................................................... 10-7 60x Bus-to-Core Frequency .................................................................................................. 10-8 Number of PSDVAL Assertions Needed for TA Assertion .................................................11-11 BADDR Connections.......................................................................................................... 11-12 60x Bus Memory Controller Registers ............................................................................... 11-12 BRx Field Descriptions ....................................................................................................... 11-13 ORx Field Descriptions (SDRAM Mode) .......................................................................... 11-16 ORx—GPCM Mode Field Descriptions ............................................................................. 11-17 Option Register (ORx)—UPM Mode ................................................................................. 11-19 PSDMR Field Descriptions................................................................................................. 11-21 LSDMR Field Descriptions ................................................................................................ 11-24 Machine x Mode Registers (MxMR) .................................................................................. 11-27 MDR Field Descriptions ..................................................................................................... 11-29 MAR Field Description....................................................................................................... 11-30 60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30 Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-31 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31 LSRT Field Descriptions..................................................................................................... 11-32 MPTPR Field Descriptions ................................................................................................. 11-32 SDRAM Interface Signals .................................................................................................. 11-33 SDRAM Interface Commands ............................................................................................ 11-35 SDRAM Address Multiplexing (A0–A15) ......................................................................... 11-38 SDRAM Address Multiplexing (A16–A31) ....................................................................... 11-38 60x Address Bus Partition................................................................................................... 11-49 SDRAM Device Address Port during activate Command.................................................. 11-49 SDRAM Device Address Port during read/write Command .............................................. 11-49 Register Settings (Page-Based Interleaving)....................................................................... 11-50 60x Address Bus Partition................................................................................................... 11-50 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxx Freescale Semiconductor Tables Table Number 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 11-43 11-44 13-1 13-2 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 Title Page Number SDRAM Device Address Port During activate Command ................................................. 11-51 SDRAM Device Address Port During read/write Command ............................................. 11-51 Register Settings (Bank-Based Interleaving) ...................................................................... 11-51 GPCM Interfaces Signals.................................................................................................... 11-52 GPCM Strobe Signal Behavior ........................................................................................... 11-53 TRLX and EHTR Combinations......................................................................................... 11-59 Boot Bank Field Values after Reset .................................................................................... 11-62 UPM Interfaces Signals ...................................................................................................... 11-63 UPM Routines Start Addresses........................................................................................... 11-66 RAM Word Bit Settings ...................................................................................................... 11-72 MxMR Loop Field Usage ................................................................................................... 11-77 UPM Address Multiplexing ................................................................................................ 11-78 60x Address Bus Partition................................................................................................... 11-81 DRAM Device Address Port during an activate command ................................................ 11-81 Register Settings ................................................................................................................. 11-81 UPMs Attributes Example .................................................................................................. 11-83 UPMs Attributes Example .................................................................................................. 11-91 EDO Connection Field Value Example .............................................................................. 11-93 TAP Signals........................................................................................................................... 13-2 Instruction Decoding............................................................................................................. 13-6 Possible MPC8280 Applications .......................................................................................... 14-3 Peripheral Prioritization ........................................................................................................ 14-7 RISC Controller Configuration Register Field Descriptions ................................................ 14-9 RTSCR Field Descriptions.................................................................................................. 14-11 RISC Microcode Revision Number .................................................................................... 14-12 CP Command Register Field Descriptions ......................................................................... 14-13 CP Command Opcodes ....................................................................................................... 14-14 Command Descriptions....................................................................................................... 14-15 Buffer Descriptor Format.................................................................................................... 14-21 Parameter RAM .................................................................................................................. 14-22 RISC Timer Table Parameter RAM .................................................................................... 14-24 TM_CMD Field Descriptions ............................................................................................. 14-25 SIx RAM Entry (MCC = 0) ................................................................................................ 15-11 SIx RAM Entry (MCC = 1) ................................................................................................ 15-13 SIx RAM Entry Descriptions.............................................................................................. 15-14 SIxGMR Field Descriptions................................................................................................ 15-17 SIxMR Field Descriptions .................................................................................................. 15-18 SIxRSR Field Descriptions ................................................................................................. 15-24 SIxCMDR Field Description .............................................................................................. 15-25 SIxSTR Field Descriptions ................................................................................................. 15-25 IDL Signal Descriptions...................................................................................................... 15-27 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxi Tables Table Number 15-10 15-11 15-12 16-1 16-2 16-3 16-4 16-5 16-6 16-7 17-1 17-2 17-3 18-1 18-2 18-3 18-4 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 20-1 20-2 20-3 20-4 20-5 20-6 20-7 Title Page Number SIx RAM Entries for an IDL Interface ............................................................................... 15-29 GCI Signals ......................................................................................................................... 15-31 SIx RAM Entries for a GCI Interface (SCIT Mode) .......................................................... 15-33 Clock Source Options ........................................................................................................... 16-6 CMXUAR Field Descriptions............................................................................................... 16-7 CMXSI1CR Field Descriptions .......................................................................................... 16-12 CMXSI2CR Field Descriptions .......................................................................................... 16-13 CMXFCR Field Descriptions.............................................................................................. 16-14 CMXSCR Field Descriptions.............................................................................................. 16-16 CMXSMR Field Descriptions............................................................................................. 16-19 BRGCx Field Descriptions ................................................................................................... 17-3 BRG External Clock Source Options.................................................................................... 17-4 Typical Baud Rates for Asynchronous Communication....................................................... 17-5 TGCR1 Field Descriptions.................................................................................................... 18-4 TGCR2 Field Descriptions.................................................................................................... 18-5 TMR1–TMR4 Field Descriptions ......................................................................................... 18-6 TER Field Descriptions......................................................................................................... 18-8 SDSR Field Descriptions ...................................................................................................... 19-3 PDTEM and LDTEM Field Descriptions ............................................................................. 19-5 IDMA Transfer Parameters................................................................................................... 19-7 IDMAx Parameter RAM..................................................................................................... 19-16 DCM Field Descriptions ..................................................................................................... 19-18 IDMA Channel Data Transfer Operation............................................................................ 19-20 Valid Memory-to-Memory STS/DTS Values...................................................................... 19-21 Valid STS/DTS Values for Peripherals ............................................................................... 19-21 IDSR/IDMR Field Descriptions.......................................................................................... 19-23 IDMA BD Field Descriptions ............................................................................................. 19-24 IDMA Bus Exceptions ........................................................................................................ 19-27 Parallel I/O Register Programming—Port C ...................................................................... 19-28 Parallel I/O Register Programming—Port A ...................................................................... 19-28 Parallel I/O Register Programming—Port D ...................................................................... 19-29 Example: Peripheral-to-Memory Mode—IDMA2 ............................................................. 19-29 Example: Memory-to-Peripheral Fly-By Mode (on 60x)–IDMA3 .................................... 19-30 Programming Example: Memory-to-Memory (PCI-to-60x)—IDMA1.............................. 19-32 GSMR_H Field Descriptions ................................................................................................ 20-3 GSMR_L Field Descriptions ................................................................................................ 20-5 TODR Field Descriptions ................................................................................................... 20-10 SCC Parameter RAM Map for All Protocols...................................................................... 20-13 Parameter RAM—SCC Base Addresses............................................................................. 20-15 RFCRx /TFCRx Field Descriptions.................................................................................... 20-15 SCCx Event, Mask, and Status Registers ........................................................................... 20-16 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxii Freescale Semiconductor Tables Table Number 20-8 20-9 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 23-12 23-13 23-14 23-15 Title Page Number Preamble Requirements ...................................................................................................... 20-22 DPLL Codings .................................................................................................................... 20-24 UART-Specific SCC Parameter RAM Memory Map ........................................................... 21-4 Transmit Commands ............................................................................................................. 21-6 Receive Commands............................................................................................................... 21-6 Control Character Table, RCCM, and RCCR Descriptions.................................................. 21-8 TOSEQ Field Descriptions ................................................................................................. 21-10 DSR Fields Descriptions ..................................................................................................... 21-11 Transmission Errors ............................................................................................................ 21-12 Reception Errors ................................................................................................................. 21-12 PSMR UART Field Descriptions........................................................................................ 21-13 SCC UART RxBD Status and Control Field Descriptions ................................................. 21-17 SCC UART TxBD Status and Control Field Descriptions ................................................. 21-18 SCCE/SCCM Field Descriptions for UART Mode ........................................................... 21-21 UART SCCS Field Descriptions......................................................................................... 21-22 UART Control Characters for S-Records Example ............................................................ 21-24 HDLC-Specific SCC Parameter RAM Memory Map .......................................................... 22-3 Transmit Commands ............................................................................................................. 22-5 Receive Commands .............................................................................................................. 22-5 Transmit Errors ................................................................................................................... 22-6 Receive Errors....................................................................................................................... 22-6 PSMR HDLC Field Descriptions.......................................................................................... 22-7 SCC HDLC RxBD Status and Control Field Descriptions................................................... 22-9 SCC HDLC TxBD Status and Control Field Descriptions ................................................. 22-12 SCCE/SCCM Field Descriptions ....................................................................................... 22-13 HDLC SCCS Field Descriptions......................................................................................... 22-16 SCC BISYNC Parameter RAM Memory Map ..................................................................... 23-3 Transmit Commands ............................................................................................................. 23-5 Receive Commands............................................................................................................... 23-5 Control Character Table and RCCM Field Descriptions ...................................................... 23-7 BSYNC Field Descriptions ................................................................................................... 23-8 BDLE Field Descriptions...................................................................................................... 23-9 Receiver SYNC Pattern Lengths of the DSR........................................................................ 23-9 Transmit Errors ................................................................................................................... 23-10 Receive Errors..................................................................................................................... 23-10 PSMR Field Descriptions.................................................................................................... 23-11 SCC BISYNC RxBD Status and Control Field Descriptions ............................................. 23-12 SCC BISYNC TxBD Status and Control Field Descriptions ............................................. 23-14 SCCE/SCCM Field Descriptions ........................................................................................ 23-16 SCCS Field Descriptions .................................................................................................... 23-17 Control Characters .............................................................................................................. 23-18 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxiii Tables Table Number 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 27-11 27-12 27-13 27-14 27-15 27-16 27-17 27-18 27-19 27-20 27-21 28-1 Title Page Number Receiver SYNC Pattern Lengths of the DSR........................................................................ 24-3 SCC Transparent Parameter RAM Memory Map................................................................. 24-6 Transmit Commands ............................................................................................................. 24-6 Receive Commands............................................................................................................... 24-7 Transmit Errors ..................................................................................................................... 24-7 Receive Errors....................................................................................................................... 24-8 SCC Transparent RxBD Status and Control Field Descriptions........................................... 24-9 SCC Transparent TxBD Status and Control Field Descriptions ......................................... 24-10 SCCE/SCCM Field Descriptions ....................................................................................... 24-11 SCCS Field Descriptions .................................................................................................... 24-12 SCC Ethernet Parameter RAM Memory Map ...................................................................... 25-7 Transmit Commands ........................................................................................................... 25-10 Receive Commands............................................................................................................. 25-10 Transmission Errors ............................................................................................................ 25-13 Reception Errors ................................................................................................................. 25-14 PSMR Field Descriptions.................................................................................................... 25-15 SCC Ethernet RxBD Status and Control Field Descriptions .............................................. 25-16 SCC Ethernet TxBD Status and Control Field Descriptions .............................................. 25-19 SCCE/SCCM Field Descriptions ........................................................................................ 25-20 USB Pins Functions .............................................................................................................. 27-3 USB Tokens .......................................................................................................................... 27-6 USB Tokens ........................................................................................................................ 27-10 USB Parameter RAM Memory Map .................................................................................. 27-12 Endpoint Parameter Block .................................................................................................. 27-13 FRAME_N Field Descriptions............................................................................................ 27-15 FRAME_N Field Descriptions............................................................................................ 27-16 RFCR and TFCR Fields...................................................................................................... 27-16 USMOD Fields ................................................................................................................... 27-17 USADR Fields .................................................................................................................... 27-18 USEPx Field Descriptions .................................................................................................. 27-18 USCOM Fields.................................................................................................................... 27-20 USBER Fields ..................................................................................................................... 27-21 USBS Fields ........................................................................................................................ 27-22 USSFT Fields ...................................................................................................................... 27-22 USB Rx BD Fields .............................................................................................................. 27-24 USB Function Tx BD Fields ............................................................................................... 27-26 USB Host Tx BD Fields...................................................................................................... 27-28 USB Host TrBD Fields ....................................................................................................... 27-30 USB Controller Transmission Errors .................................................................................. 27-33 USB Controller Reception Errors ....................................................................................... 27-33 SMCMR1/SMCMR2 Field Descriptions.............................................................................. 28-3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxiv Freescale Semiconductor Tables Table Number 28-2 28-3 28-4 28-5 28-6 28-7 28-8 28-9 28-10 28-11 28-12 28-13 28-14 28-15 28-16 28-17 28-18 28-19 28-20 28-21 28-22 28-23 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 29-18 29-19 Title Page Number SMC UART and Transparent Parameter RAM Memory Map ............................................. 28-6 RFCR/TFCR Field Descriptions ........................................................................................... 28-8 Transmit Commands ........................................................................................................... 28-12 Receive Commands............................................................................................................. 28-12 SMC UART Errors.............................................................................................................. 28-13 SMC UART RxBD Field Descriptions ............................................................................... 28-14 SMC UART TxBD Field Descriptions ............................................................................... 28-17 SMCE/SMCM Field Descriptions ...................................................................................... 28-18 SMC Transparent Transmit Commands.............................................................................. 28-25 SMC Transparent Receive Commands ............................................................................... 28-25 SMC Transparent Error Conditions .................................................................................... 28-25 SMC Transparent RxBD Field Descriptions....................................................................... 28-26 SMC Transparent TxBD ..................................................................................................... 28-27 SMC Transparent TxBD Field Descriptions....................................................................... 28-27 SMCE/SMCM Field Descriptions ...................................................................................... 28-28 SMC GCI Parameter RAM Memory Map.......................................................................... 28-30 SMC GCI Commands ......................................................................................................... 28-32 SMC Monitor Channel RxBD Field Descriptions .............................................................. 28-32 SMC Monitor Channel TxBD Field Descriptions .............................................................. 28-33 SMC C/I Channel RxBD Field Descriptions ...................................................................... 28-34 SMC C/I Channel TxBD Field Descriptions ...................................................................... 28-34 SMCE/SMCM Field Descriptions ...................................................................................... 28-35 Global MCC Parameters ....................................................................................................... 29-4 Channel-Specific Parameters for HDLC............................................................................... 29-6 TSTATE High-Byte Field Descriptions ................................................................................ 29-7 CHAMR Field Descriptions.................................................................................................. 29-9 RSTATE High-Byte Field Descriptions .............................................................................. 29-10 Channel-Specific Parameters for Transparent Operation.................................................... 29-11 CHAMR Field Descriptions—Transparent Mode .............................................................. 29-13 CES-Specific Global MCC Parameters .............................................................................. 29-14 CHAMR Field Descriptions—CES Mode.......................................................................... 29-15 Channel-Specific Parameters for SS7 ................................................................................. 29-18 ECHAMR Fields Description ............................................................................................. 29-21 Parameter Values for SUERM in Japanese SS7.................................................................. 29-23 SS7 Configuration Register Fields Description .................................................................. 29-23 Channel Extra Parameters ................................................................................................... 29-27 MCCF Field Descriptions ................................................................................................... 29-32 Group Channel Assignments .............................................................................................. 29-33 MCC Commands................................................................................................................. 29-34 MCCE/MCCM Register Field Descriptions ....................................................................... 29-36 Interrupt Circular Table Entry Field Descriptions .............................................................. 29-37 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxv Tables Table Number 29-20 29-21 29-22 30-1 30-2 30-3 30-4 30-5 30-6 31-1 31-2 31-3 31-4 31-5 31-6 31-7 31-8 31-9 31-10 31-11 31-12 31-13 31-14 31-15 31-16 31-17 31-18 31-19 31-20 31-21 31-22 31-23 31-24 31-25 31-26 31-27 31-28 31-29 31-30 31-31 31-32 Title Page Number GUN Error Recovery .......................................................................................................... 29-41 RxBD Field Descriptions .................................................................................................... 29-42 TxBD Field Descriptions .................................................................................................... 29-44 Internal Clocks to CPM Clock Frequency Ratio .................................................................. 30-3 GFMR Register Field Descriptions....................................................................................... 30-4 GFEMRx Field Descriptions ................................................................................................ 30-8 FTODR Field Descriptions ................................................................................................. 30-10 FCC Parameter RAM Common to All Protocols Except ATM .......................................... 30-12 FCRx Field Descriptions..................................................................................................... 30-14 ATM Service Types............................................................................................................... 31-9 External CAM Input and Output Field Descriptions .......................................................... 31-14 Field Descriptions for Address Compression ..................................................................... 31-16 VCOFFSET Calculation Examples for Contiguous VCLTs ............................................... 31-16 VP-Level Table Entry Address Calculation Example......................................................... 31-17 VC-Level Table Entry Address Calculation Example ........................................................ 31-17 Fields and their Positions in RM Cells................................................................................ 31-26 Pre-Assigned Header Values at the UNI ............................................................................. 31-27 Pre-Assigned Header Values at the NNI ............................................................................. 31-28 Performance Monitoring Cell Fields................................................................................... 31-30 ATM Parameter RAM Map................................................................................................. 31-36 UEAD_OFFSETs for Extended Addresses in the UDC Extra Header ............................... 31-39 VCI Filtering Enable Field Descriptions ............................................................................ 31-39 GMODE Field Descriptions................................................................................................ 31-40 Receive and Transmit Connection Table Sizes ................................................................... 31-41 RCT Field Descriptions ...................................................................................................... 31-44 RCT Settings (AAL5 Protocol-Specific) ............................................................................ 31-46 ABR Protocol-Specific RCT Field Descriptions ................................................................ 31-47 AAL1 Protocol-Specific RCT Field Descriptions .............................................................. 31-48 AAL0-Specific RCT Field Descriptions............................................................................. 31-49 TCT Field Descriptions....................................................................................................... 31-51 AAL5-Specific TCT Field Descriptions ............................................................................. 31-53 AAL1 Protocol-Specific TCT Field Descriptions .............................................................. 31-54 AAL0-Specific TCT Field Descriptions ............................................................................. 31-55 VBR-Specific TCTE Field Descriptions............................................................................. 31-56 UBR+ Protocol-Specific TCTE Field Descriptions............................................................ 31-57 ABR-Specific TCTE Field Descriptions............................................................................. 31-58 OAM—Performance Monitoring Table Field Descriptions ............................................... 31-61 APC Parameter Table.......................................................................................................... 31-62 APC Priority Table Entry.................................................................................................... 31-63 Control Slot Field Description ............................................................................................ 31-64 Free Buffer Pool Entry Field Descriptions.......................................................................... 31-68 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxvi Freescale Semiconductor Tables Table Number 31-33 31-34 31-35 31-36 31-37 31-38 31-39 31-40 31-41 31-42 31-43 31-44 31-45 31-46 31-47 31-48 31-49 31-50 31-51 31-52 31-53 31-54 32-1 32-2 32-3 32-4 32-5 32-6 32-7 32-8 32-9 32-10 32-11 32-12 32-13 32-14 32-15 33-1 33-2 33-3 33-4 Title Page Number Free Buffer Pool Parameter Table....................................................................................... 31-68 Receive and Transmit Buffers............................................................................................. 31-69 AAL5 RxBD Field Descriptions......................................................................................... 31-70 AAL1 RxBD Field Descriptions......................................................................................... 31-71 AAL0 RxBD Field Descriptions......................................................................................... 31-72 AAL5 TxBD Field Descriptions ......................................................................................... 31-74 AAL1 TxBD Field Descriptions ......................................................................................... 31-75 AAL0 TxBD Field Descriptions ......................................................................................... 31-76 UNI Statistics Table ............................................................................................................ 31-78 Interrupt Queue Entry Field Description ............................................................................ 31-80 Interrupt Queue Parameter Table ........................................................................................ 31-81 UTOPIA Master Mode Signal Descriptions ....................................................................... 31-82 UTOPIA Slave Mode Signals ............................................................................................. 31-83 UTOPIA Loop-Back Modes ............................................................................................... 31-85 FCC ATM Mode Register (FPSMR) .................................................................................. 31-86 FCCE/FCCM Field Descriptions ........................................................................................ 31-89 COMM_INFO Field Descriptions ...................................................................................... 31-90 FTIRRx Field Descriptions................................................................................................. 31-92 FIRPERx Field Descriptions (TIREM=1) .......................................................................... 31-94 FIRERx Field Descriptions (TIREM=1)............................................................................. 31-95 IRSRx_HI Field Descriptions (TIREM=1)......................................................................... 31-96 FIRSRx_LO Field Descriptions (TIREM=1) ..................................................................... 31-97 CAS Routing Table Entry Field Descriptions..................................................................... 32-13 CES Adaptive Threshold Table Field Descriptions ............................................................ 32-17 AAL1 CES Field Descriptions............................................................................................ 32-22 AAL1 CES Parameters ....................................................................................................... 32-25 RCT Field Descriptions ...................................................................................................... 32-27 AAL1 CES Protocol-Specific RCT Field Descriptions ...................................................... 32-29 TCT Field Descriptions....................................................................................................... 32-32 AAL1 CES Protocol-Specific TCT Field Descriptions ...................................................... 32-35 OCASSR Field Descriptions............................................................................................... 32-36 Receive and Transmit Buffers............................................................................................. 32-38 AAL1 CES RxBD Field Descriptions ................................................................................ 32-39 AAL1 CES TxBD Field Descriptions................................................................................. 32-40 AAL1 CES Interrupt Queue Entry Field Descriptions ....................................................... 32-41 AAL1 CES DPR Statistics Table ........................................................................................ 32-43 AAL1 CES External Statistics Table .................................................................................. 32-44 AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions ................. 33-9 CPS TxQD Field Descriptions............................................................................................ 33-13 CPS TxBD Field Descriptions ............................................................................................ 33-15 SSSAR TxQD Field Descriptions....................................................................................... 33-17 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxvii Tables Table Number 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 33-13 33-14 33-15 34-1 34-2 34-3 34-4 34-5 34-6 34-7 34-8 34-9 34-10 34-11 34-12 34-13 34-14 34-15 34-16 34-17 34-18 34-19 34-20 34-21 34-22 34-23 34-24 34-25 34-26 34-27 34-28 34-29 35-1 Title Page Number SSSAR TxBD Field Descriptions ....................................................................................... 33-18 AAL2 Protocol-Specific RCT Field Descriptions .............................................................. 33-23 CPS RxQD Field Descriptions............................................................................................ 33-27 CPS RxBD Field Descriptions............................................................................................ 33-28 CPS Switch RxQD Field Descriptions................................................................................ 33-29 Switch RxBD Field Descriptions........................................................................................ 33-30 SSSAR RxQD Field Descriptions....................................................................................... 33-31 SSSAR RxBD Field Descriptions....................................................................................... 33-33 AAL2 Parameter RAM ....................................................................................................... 33-34 AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions.................................................. 33-38 AAL2 Interrupt Queue Entry CID = 0 Field Descriptions.................................................. 33-39 IMA Sublayer in Layer Reference Model............................................................................. 34-2 FCC Parameter RAM Additions ......................................................................................... 34-22 IMA Root Table .................................................................................................................. 34-23 IMACNTL Field Descriptions ............................................................................................ 34-25 IMA Group Transmit Table Entry ...................................................................................... 34-25 IGTCNTL Field Descriptions ............................................................................................. 34-27 IGTSTATE Field Descriptions ............................................................................................ 34-28 Transmit Group Order Table Entry Field Descriptions....................................................... 34-28 ICP Cell Template .............................................................................................................. 34-29 IMA Group Receive Table Entry ....................................................................................... 34-31 IGRCNTL Field Descriptions ............................................................................................. 34-34 IGRSTATE Field Descriptions............................................................................................ 34-35 IRGFS Field Descriptions ................................................................................................... 34-35 Receive Group Order Table Entry Field Descriptions ........................................................ 34-36 IMA Link Transmit Table Entry ........................................................................................ 34-36 ILTCNTL Field Descriptions .............................................................................................. 34-38 ILTSTATE Field Descriptions............................................................................................. 34-38 ITINTSTAT Field Descriptions........................................................................................... 34-39 IMA Link Receive Table Entry........................................................................................... 34-40 ILRCNTL Field Descriptions ............................................................................................. 34-41 ILRSTATE Field Descriptions ............................................................................................ 34-42 IMA Link Receive Statistics Table Entry ........................................................................... 34-43 IMA Interrupt Queue Entry Field Descriptions .................................................................. 34-46 Unavailable Features when DREQx used as IDCR Master Clock ..................................... 34-48 IDCR IMA Root Parameters............................................................................................... 34-49 IDCR Table Entry ............................................................................................................... 34-49 IDSR/IDMR Field Descriptions.......................................................................................... 34-50 Examples of APC Programming for IMA .......................................................................... 34-51 COMM_INFO Field Descriptions ...................................................................................... 34-53 TC Layer Signals .................................................................................................................. 35-6 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxviii Freescale Semiconductor Tables Table Number 35-2 35-3 35-4 35-5 35-6 35-7 35-8 35-9 35-10 35-11 35-12 36-1 36-2 36-3 36-4 36-5 36-6 36-7 36-8 36-9 36-10 36-11 37-1 37-2 37-3 37-4 37-5 37-6 37-7 37-8 37-9 37-10 39-1 39-2 39-3 39-4 39-5 39-6 39-7 39-8 39-9 Title Page Number TCMODEx Field Descriptions.............................................................................................. 35-7 CDSMRx Field Descriptions ................................................................................................ 35-9 TCERx Field Descriptions .................................................................................................... 35-9 TCGER Field Descriptions ................................................................................................. 35-10 TCGSR Field Descriptions ................................................................................................. 35-11 Programming GFMR and FPSMR to Setup the FCC2 ....................................................... 35-16 Enable FCC2 ....................................................................................................................... 35-16 Programming the CPM MUX for a TI Application............................................................ 35-16 Programming the TC Layer Block...................................................................................... 35-17 Programming the SI RAM (Rx or Tx) for a T1 Application .............................................. 35-17 Programming SI Registers to Enable TDM ........................................................................ 35-17 Flow Control Frame Structure .............................................................................................. 36-7 Ethernet-Specific Parameter RAM ....................................................................................... 36-9 Transmit Commands ........................................................................................................... 36-13 Receive Commands............................................................................................................. 36-13 RMON Statistics and Counters ........................................................................................... 36-14 Transmission Errors ............................................................................................................ 36-19 Reception Errors ................................................................................................................. 36-19 FPSMR Ethernet Field Descriptions................................................................................... 36-20 FCCE/FCCM Field Descriptions ........................................................................................ 36-22 RxBD Field Descriptions .................................................................................................... 36-24 Ethernet TxBD Field Definitions........................................................................................ 36-27 FCC HDLC-Specific Parameter RAM Memory Map .......................................................... 37-3 Transmit Commands ............................................................................................................. 37-5 Receive Commands............................................................................................................... 37-6 HDLC Transmission Errors .................................................................................................. 37-6 HDLC Reception Errors ....................................................................................................... 37-7 FPSMR Field Descriptions .................................................................................................. 37-8 RxBD field Descriptions ..................................................................................................... 37-11 HDLC TxBD Field Descriptions ....................................................................................... 37-13 FCCE/FCCM Field Descriptions ........................................................................................ 37-15 FCCS Register Field Descriptions ...................................................................................... 37-17 SPMODE Field Descriptions ................................................................................................ 39-6 Example Conventions ........................................................................................................... 39-8 SPIE/SPIM Field Descriptions.............................................................................................. 39-9 SPCOM Field Descriptions................................................................................................. 39-10 SPI Parameter RAM Memory Map .................................................................................... 39-11 RFCR/TFCR Field Descriptions ......................................................................................... 39-12 SPI Commands.................................................................................................................... 39-12 SPI RxBD Status and Control Field Descriptions............................................................... 39-14 SPI TxBD Status and Control Field Descriptions............................................................... 39-15 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxix Tables Table Number 40-1 40-2 40-3 40-4 40-5 40-6 40-7 40-8 40-9 40-10 41-1 41-2 41-3 41-4 41-5 41-6 41-7 41-8 Title Page Number II2MOD Field Descriptions .................................................................................................. 40-6 I2ADD Field Descriptions .................................................................................................... 40-7 I2BRG Field Descriptions..................................................................................................... 40-7 I2CER/I2CMR Field Descriptions........................................................................................ 40-8 I2COM Field Descriptions.................................................................................................... 40-9 I2C Parameter RAM Memory Map....................................................................................... 40-9 RFCR/TFCR Field Descriptions ......................................................................................... 40-11 I2C Transmit/Receive Commands....................................................................................... 40-11 I2C RxBD Status and Control Bits...................................................................................... 40-13 I2C TxBD Status and Control Bits...................................................................................... 40-14 PODRx Field Descriptions ................................................................................................... 41-2 PDIR Field Descriptions ....................................................................................................... 41-3 PPAR Field Descriptions....................................................................................................... 41-4 PSORx Field Descriptions .................................................................................................... 41-5 Port A—Dedicated Pin Assignment (PPARA = 1) ............................................................... 41-8 Port B Dedicated Pin Assignment (PPARB = 1) ................................................................ 41-12 Port C Dedicated Pin Assignment (PPARC = 1) ................................................................ 41-15 Port D Dedicated Pin Assignment (PPARD = 1) .............................................................. 41-17 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxx Freescale Semiconductor About This Book The MPC8280 is a versatile communications processor that integrates on one chip a high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The primary objective of this manual is to help communications system designers build systems using any member of the MPC8280 PowerQUICC II™ family of communications processors and to help software designers provide operating systems and user-level applications to take complete advantage of the MPC8280. NOTE: Devices Supported by This Manual This manual supports the MPC8280, the MPC8275, and the MPC8270, which are collectively called either the MPC8280 or the PowerQUICC II throughout this manual. Device numbers are cited only if information does not pertain to all devices. Although this book describes aspects of the PowerPC architecture that are critical for understanding the MPC8280 core, it does not contain a complete description of the architecture. Where additional information might help the reader, references are made to Programming Environments Manual for 32-Bit Implementation of the PowerPC Architecture, Rev. 2. Refer to “Architecture Documentation” for ordering information. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers’ responsibility to use the most recent version of the documentation. For more information, contact your sales representative. Before Using this Manual—Important Note Before using this manual, determine whether it is the latest revision and if there are errata or addenda. To locate any published errata or updates for this document, refer to the worldwide web at www.freescale.com. Audience This manual is intended for software and hardware developers and application programmers who want to develop products for the MPC8280. It is assumed that the reader has a basic understanding of computer networking, OSI layers, RISC architecture, and communications protocols described herein. Where useful, additional sources provide in-depth discussions of such topics. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxxi Organization Following is a summary and a brief description of the chapters of this manual: • Part I, “Overview,” provides a high-level description of the MPC8280, describing general operation and listing basic features. — Chapter 1, “Overview,” provides a high-level description of MPC8280 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information. — Chapter 2, “G2_LE Core,” provides an overview of the MPC8280 core, summarizing topics described in further detail in subsequent chapters. — Chapter 3, “Memory Map,” presents a table showing where MPC8280 registers are mapped in memory. It includes cross references that indicate where the registers are described in detail. • Part II, “Configuration and Reset,” describes start-up behavior of the MPC8280. — Chapter 4, “System Interface Unit (SIU),” describes the system configuration and protection functions that provide various monitors and timers, and the 60x bus configuration. — Chapter 5, “Reset,” describes the behavior of the MPC8280 at reset and start-up. • Part III, “The Hardware Interface,” describes external signals, clocking, memory control, and power management of the MPC8280. — Chapter 6, “External Signals,” shows a functional pinout of the MPC8280 and describes the MPC8280 signals. — Chapter 7, “60x Signals,” describes signals on the 60x bus. — Chapter 8, “The 60x Bus,” describes the operation of the bus used by processors that implement the PowerPC architecture. — Chapter 9, “PCI Bridge,” describes how the PCI bridge enables the MPC8280 to gluelessly bridge PCI agents to a host processor that implements the PowerPC architecture and how it is compliant with PCI Specification Revision 2.2. — Chapter 10, “Clocks and Power Control,” describes the clocking architecture of the MPC8280. — Chapter 11, “Memory Controller,” describes the memory controller, which controls a maximum of eight memory banks shared among a general-purpose chip-select machine (GPCM) and three user-programmable machines (UPMs). — Chapter 12, “Secondary (L2) Cache Support,” provides information about implementation and configuration of a level-2 cache. — Chapter 13, “IEEE 1149.1 Test Access Port,” describes the dedicated user-accessible test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. • Part IV, “Communications Processor Module,” describes the configuration, clocking, and operation of the various communications protocols that the MPC8280 supports. — Chapter 14, “Communications Processor Module Overview,” provides a brief overview of the CPM. — Chapter 15, “Serial Interface with Time-Slot Assigner,” describes the SIU, which controls system start-up, initialization and operation, protection, as well as the external system bus. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxxii Freescale Semiconductor — Chapter 16, “CPM Multiplexing,” describes the CPM multiplexing logic (CMX) that connects the physical layer—UTOPIA, MII, modem lines. — Chapter 17, “Baud-Rate Generators (BRGs),” describes the eight independent, identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. — Chapter 18, “Timers,” describes the timer implementation, which can be configured as four identical 16-bit or two 32-bit general-purpose timers. — Chapter 19, “SDMA Channels and IDMA Emulation,” describes the two physical serial DMA (SDMA) channels on the MPC8280. — Chapter 20, “Serial Communications Controllers (SCCs),” describes the four serial communications controllers (SCC), which can be configured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks. — Chapter 21, “SCC UART Mode,” describes the MPC8280 implementation of universal asynchronous receiver transmitter (UART) protocol that sends low-speed data between devices. — Chapter 22, “SCC HDLC Mode,” describes the MPC8280 implementation of HDLC protocol. — Chapter 23, “SCC BISYNC Mode,” describes the MPC8280 implementation of byte-oriented BISYNC protocol developed by IBM for use in networking products. — Chapter 24, “SCC Transparent Mode,” describes the MPC8280 implementation of transparent mode (also called totally transparent mode), which provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. — Chapter 25, “SCC Ethernet Mode,” describes the MPC8280 implementation of Ethernet protocol. — Chapter 26, “SCC AppleTalk Mode,” describes the MPC8280 implementation of AppleTalk. — Chapter 27, “Universal Serial Bus Controller,” describes the MPC8280’s USB controller, including basic operation, the parameter RAM, and registers. — Chapter 28, “Serial Management Controllers (SMCs),” describes two serial management controllers, full-duplex ports that can be configured independently to support one of three protocols—UART, transparent, or general-circuit interface (GCI). — Chapter 29, “Multi-Channel Controllers (MCCs),” describes the MPC8280’s multi-channel controller (MCC), which handles up to 128 serial, full-duplex data channels. — Chapter 30, “Fast Communications Controllers (FCCs),” describes the MPC8280’s fast communications controllers (FCCs), which are SCCs optimized for synchronous high-rate protocols. — Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5,” describes the MPC8280 ATM controller, which provides the ATM and AAL layers of the ATM protocol. The ATM controller performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and AAL0, and most of the common parts convergence sublayer (CP-CS) of these protocols. — Chapter 32, “ATM AAL1 Circuit Emulation Service,” describes the implementation of circuit emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the MPC8280. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxxiii • • • — Chapter 33, “ATM AAL2,” describes the functionality and data structures of ATM adaptation layer type 2 (AAL2) CPS, CPS switching, and SSSAR. — Chapter 34, “Inverse Multiplexing for ATM (IMA),” describes specifications for the inverse multiplexing for ATM (IMA) microcode. — Chapter 35, “ATM Transmission Convergence Layer,” describes how the MPC8280 can support applications that receive ATM traffic over the standard serial protocols like E1, T1, and xDSL via its serial interface (SIx TDMx and NMSI) ports because of its internally implemented TC-layer functionality. — Chapter 36, “Fast Ethernet Controller,” describes the MPC8280’s implementation of the Ethernet IEEE 802.3 protocol. — Chapter 37, “FCC HDLC Controller,” describes the FCC implementation of the HDLC protocol. — Chapter 38, “FCC Transparent Controller,” describes the FCC implementation of the transparent protocol. — Chapter 39, “Serial Peripheral Interface (SPI),” describes the serial peripheral interface, which allows the MPC8280 to exchange data between other PowerQUICC II chips, the MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. — Chapter 40, “I2C Controller,” describes the MPC8280 implementation of the inter-integrated circuit (I2C®) controller, which allows data to be exchanged with other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters. — Chapter 41, “Parallel I/O Ports,” describes the four general-purpose I/O ports A–D. Each signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated to supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs. Appendix A, “Register Quick Reference Guide,” provides a quick reference to the registers incorporated in the G2_LE core. Appendix B, “Revision History,” provides a list of the major differences between revisions of the MPC8280 PowerQUICC II Family Reference Manual. This book also includes an index and a glossary. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC82xx Documentation Supporting documentation for the MPC8280 can be accessed through the world-wide web at www.freescale.com. This documentation includes technical specifications, reference materials, and detailed applications notes. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxxiv Freescale Semiconductor Architecture Documentation Architecture documentation is organized in the following types of documents: • Manuals—These books provide details about individual implementations of the PowerPC architecture and are intended to be used with the Programming Environments Manual. These include the G2 Core Reference Manual (Freescale order #: G2CORERM). • Programming environments manuals—These books provide information about resources defined by the PowerPC architecture that are common to processors that implement the PowerPC architecture. The two versions include one that describes the functionality of the combined 32- and 64-bit architecture models and one that describes only the 32-bit model. The MPC8280 adheres to the 32-bit architecture definition. — Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture (Freescale order #: MPCFPE32B) • The Programmer’s Pocket Reference Guide for the PowerPC Architecture: MPCPRGREF/D—This guide provides an overview of registers, instructions, and exceptions for 32-bit implementations. • Application notes—These short documents contain useful information about specific design issues useful to programmers and engineers working with Freescale’s processors. For a current list of documentation, refer to www.freescale.com. Conventions This document uses the following notational conventions: Table 1: Bold entries in figures and tables showing registers and parameter RAM should be initialized by the user. B ld mnemonics Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters, for example, bcctrx. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number rA, rB Instruction syntax used to identify a source GPR rD Instruction syntax used to identify a destination GPR REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. x In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. n Used to express an undefined numerical value ¬ NOT logical operator MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxxv & | AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table i. Acronyms and Abbreviated Terms Term A/D ALU ATM BD BIST BPU BRI BUID CAM CEPT CMX CPM CR CRC CTR DABR DAR DEC DMA DPLL DRAM DSISR DTLB EA EEST Analog-to-digital Arithmetic logic unit Asynchronous transfer mode Buffer descriptor Built-in self test Branch processing unit Basic rate interface. Bus unit ID Content-addressable memory Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations). CPM multiplexing logic Communication processor module Condition register Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Register used for determining the source of a DSI exception Data translation lookaside buffer Effective address Enhanced Ethernet serial transceiver Meaning MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxxvi Freescale Semiconductor Table i. Acronyms and Abbreviated Terms (continued) Term EPROM FPR FPSCR FPU GCI GPCM GPR GUI HDLC I2C IDL IEEE IrDA ISDN ITLB IU JTAG LIFO LR LRU LSB lsb LSU MAC MESI MMU MSB msb MSR NaN NIA NMSI No-op Erasable programmable read-only memory Floating-point register Floating-point status and control register Floating-point unit General circuit interface General-purpose chip-select machine General-purpose register Graphical user interface High-level data link control Inter-integrated circuit Inter-chip digital link Institute of Electrical and Electronics Engineers Infrared Data Association Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Last-in-first-out Link register Least recently used Least-significant byte Least-significant bit Load/store unit Multiply accumulate Modified/exclusive/shared/invalid—cache coherency protocol Memory management unit Most-significant byte Most-significant bit Machine state register Not a number Next instruction address Nonmultiplexed serial interface No operation Meaning MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxxvii Table i. Acronyms and Abbreviated Terms (continued) Term OEA OSI PCI PCMCIA PIR PRI PVR RISC RTOS RWITM Rx SCC SCP SDLC SDMA SI SIMM SIU SMC SNA SPI SPR SPRG n SRAM SRR0 SRR1 TAP TB TDM TLB TSA Tx UART Operating environment architecture Open systems interconnection Peripheral component interconnect Personal Computer Memory Card International Association Processor identification register Primary rate interface Processor version register Reduced instruction set computing Real-time operating system Read with intent to modify Receive Serial communication controller Serial control port Synchronous data link control Serial DMA Serial interface Signed immediate value System interface unit Serial management controller Systems network architecture Serial peripheral interface Special-purpose register Registers available for general purposes Static random access memory Machine status save/restore register 0 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter Meaning MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 lxxxviii Freescale Semiconductor Table i. Acronyms and Abbreviated Terms (continued) Term UIMM UISA UPM USART USB VA VEA XER Unsigned immediate value User instruction set architecture User-programmable machine Universal synchronous/asynchronous receiver/transmitter Universal serial bus Virtual address Virtual environment architecture Register used primarily for indicating conditions such as carries and overflows for integer operations Meaning PowerPC Architecture Terminology Conventions Table ii lists certain terms used in this manual that differ from the architecture terminology conventions. Table ii. Terminology Conventions The Architecture Specification Data storage interrupt (DSI) Extended mnemonics Instruction storage interrupt (ISI) Interrupt Privileged mode (or privileged state) Problem mode (or problem state) Real address Relocation Storage (locations) Storage (the act of) This Manual DSI exception Simplified mnemonics ISI exception Exception Supervisor-level privilege User-level privilege Physical address Translation Memory Access MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor lxxxix Table iii describes instruction field notation conventions used in this manual. Table iii. Instruction Field Conventions The Architecture Specification BA, BB, BT BF, BFA D DS FLM FXM RA, RB, RT, RS SI U UI /, //, /// Equivalent to: crbA, crbB, crbD (respectively) crfD, crfS (respectively) d ds FM CRM rA, rB, rD, rS (respectively) SIMM IMM UIMM 0...0 (shaded) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 xc Freescale Semiconductor Part I Overview Intended Audience Part I is intended for readers who need a high-level understanding of the MPC8280. Contents Part I provides a high-level description of the MPC8280, describing general operation and listing basic features. • Chapter 1, “Overview,” provides a high-level description of MPC8280 functions and features. It roughly follows the structure of this book, summarizing the relevant features and providing references for the reader who needs additional information. • Chapter 2, “G2_LE Core,” provides an overview of the MPC8280 core. • Chapter 3, “Memory Map,” presents a table showing where MPC8280 registers are mapped in memory. It includes cross references that indicate where the registers are described in detail. Conventions Part I uses the following notational conventions: mnemonics Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters, for example, bcctrx. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number rA, rB Instruction syntax used to identify a source GPR rD Instruction syntax used to identify a destination GPR REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine state register. x In certain contexts, such as in a signal encoding or a bit field, indicates a don’t care. n Indicates an undefined numerical value MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor I-1 Acronyms and Abbreviations Table I-1 contains acronyms and abbreviations that are used in this document. Table I-1. Acronyms and Abbreviated Terms Term ATM BD BPU COP CP CPM CRC CTR DABR DAR DEC DMA DPLL DRAM DTLB EA FCC‘ FPR GPCM GPR HDLC I2C IEEE ISDN ITLB IU JTAG LRU LSU MCC Asynchronous Mode Buffer descriptor Branch processing unit Common on-chip processor Communications processor Communications processor module Cyclic redundancy check Count register Data address breakpoint register Data address register Decrementer register Direct memory access Digital phase-locked loop Dynamic random access memory Data translation lookaside buffer Effective address Fast communications controller Floating-point register General-purpose chip-select machine General-purpose register High-level data link control Inter-integrated circuit Institute of Electrical and Electronics Engineers Integrated services digital network Instruction translation lookaside buffer Integer unit Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Multi-channel controller Meaning MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 I-2 Freescale Semiconductor Table I-1. Acronyms and Abbreviated Terms (continued) Term MII MMU MSR NMSI OEA OSI PCI RISC RTC RTOS Rx SCC SDLC SDMA SI SIU SMC SPI SPR SRAM TAP TB TDM TLB TSA Tx UART UISA UPM VEA Media-independent interface Memory management unit Machine state register Nonmultiplexed serial interface Operating environment architecture Open systems interconnection Peripheral component interconnect Reduced instruction set computing Real-time clock Real-time operating system Receive Serial communications controller Synchronous data link control Serial DMA Serial interface System interface unit Serial management controller Serial peripheral interface Special-purpose register Static random access memory Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit Universal asynchronous receiver/transmitter User instruction set architecture User-programmable machine Virtual environment architecture Meaning MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor I-3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 I-4 Freescale Semiconductor Chapter 1 Overview The MPC8280 is a versatile communications processor that integrates on one chip a high-performance PowerPC™ RISC microprocessor, a very flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems. The MPC8280 core—a G2_LE—is an embedded variant of the MPC603e microprocessor with 16 Kbytes of instruction cache and 16 Kbytes of data cache. The system interface unit (SIU) consists of a flexible memory controller that interfaces to almost any user-defined memory system, a 60x-to-PCI bus bridge, and many other peripherals making this device a complete system on a chip. The MPC8280 communications processor module (CPM) includes all the peripherals found in the MPC8260 PowerQUICC II family. In addition, the MPC8280 offers USB functionality. This manual describes the functional operation of MPC8280, with an emphasis on peripheral functions. Chapter 2, “G2_LE Core,” is an overview of the microprocessor core; detailed information about the core can be found in the G2 Core Reference Manual (order number: G2CORERM). 1.1 Features The following is an overview of the MPC8280 feature set: • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 166–450 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for data cache coherency — Floating-point unit (FPU) • Separate power supply for internal logic and for I/O • Separate PLLs for G2_LE core and for the CPM — G2_LE core and CPM can run at different frequencies for power/performance optimization MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 1-1 Overview • • • • — Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 6:1, 7:1, 8:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1 ratios 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs — Supports single- and four-beat burst transfers — 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller — Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus — Single-master bus, supports external slaves — Eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge — Programmable host bridge and agent — 32-bit data bus, 66.67/83.3/100 MHz, 3.3 V — Synchronous and asynchronous 60x and PCI clock modes — All internal address space available to external PCI host — DMA for memory block transfers — PCI-to-60x address remapping PCI bridge — PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz — On-chip arbitration — Support for PCI-to-60x-memory and 60x-memory-to-PCI streaming — PCI host bridge or peripheral capabilities — Includes 4 DMA channels for the following transfers: – PCI-to-60x to 60x-to-PCI – 60x-to-PCI to PCI-to-60x – PCI-to-60x to PCI-to-60x – 60x-to-PCI to 60x-to-PCI — Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8280) required by the PCI standard as well as message and doorbell registers — Supports the I2O standard — Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66.67/83.33/100 MHz, 3.3 V specification MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 1-2 Freescale Semiconductor Overview • • • • — 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port — Uses the local bus signals, removing need for additional pins System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE 1149.1 JTAG test access port 12-bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals — Byte write enables and selectable parity generation — 32-bit address decodes with programmable bank size — Three user-programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local) — Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2_LE core through an on-chip 32-Kbyte dual-port data RAM, an on-chip 32-Kbyte dual-port instruction RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols: – 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) or reduced media independent interface (RMII) – ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64 K external connections (no ATM support for the MPC8270) – Transparent – HDLC—Up to T3 rates (clear channel) – FCC2 can also be connected to the TC layer (MPC8280 only) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 1-3 Overview — Two multichannel controllers (MCCs) (one MCC on the MPC8270) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Universal serial bus (USB) controller – USB 2.0 full/low rate compatible – USB host mode –Supports control, bulk, interrupt, and isochronous data transfers –CRC16 generation and checking –NRZI encoding/decoding with bit stuffing –Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. –Flexible data buffers with multiple buffers per frame –Supports local loopback mode for diagnostics (12 Mbps only) – Supports USB slave mode –Four independent endpoints support control, bulk, interrupt, and isochronous data transfers –CRC16 generation and checking –CRC5 checking –NRZI encoding/decoding with bit stuffing –12- or 1.5-Mbps data rate –Flexible data buffers with multiple buffers per frame –Automatic retransmission upon transmit error — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 1-4 Freescale Semiconductor Overview — — — — — — — – Transparent – UART (low-speed operation) One serial peripheral interface identical to the MPC860 SPI One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes Up to eight TDM interfaces (four on the MPC8270) – Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270 and the MPC8275) – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels Four independent 16-bit timers that can be interconnected as two 32-bit timers Transmission convergence (TC) layer (MPC8280 only) Inverse multiplexing for ATM capabilities (IMA) (MPC8280 only). Supported by eight TC layers between the TDMs and FCC2. 1.2 Architecture Overview The MPC8280 has two external buses to accommodate bandwidth requirements from the high-speed system core and the very fast communications channels. Figure 1-1 shows the block diagram of the superset MPC8280 device. Features that are device- or package-specific are noted. For package information, refer to the MPC8280 PowerQUICC II Family Hardware Specifications (order number: MPC8280EC). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 1-5 Overview 16 Kbytes I-Cache I-MMU G2_LE Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Serial DMAs 4 Virtual IDMAs Clock Counter System Functions 60x Bus PCI Bus 32 bits, up to 66 MHz or Local Bus 32 bits, up to 100 MHz Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators Interrupt Controller 32 KB Instruction RAM 32 KB Data RAM 32-bit RISC Microcontroller and Program ROM IMA 1 Microcode MCC11 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ USB SMC1 SMC2 SPI I2C TC Layer Hardware1 Time Slot Assigner Serial Interface2 8 TDM Ports2 3 MII or RMII Ports 2 UTOPIA Ports3 Non-Multiplexed I/O Notes: 1 MPC8280 only (not on MPC8270, the VR package, nor the ZQ package) 2 MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have only 1 SI block and 4 TDM ports (TDM2[A–D]). 3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ) Figure 1-1. MPC8280 Block Diagram Both the system core and the CPM have an internal PLL, which allows independent optimization of the frequencies at which they run. The system core and CPM are both connected to the 60x bus. 1.2.1 G2_LE Core The G2_LE core is derived from the MPC603e microprocessor with power management modifications. The core is a high-performance low-power implementation of the family of reduced instruction set computer (RISC) microprocessors. The G2_LE core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits. The G2_LE cache provides snooping to ensure data coherency with other masters. This helps ensure coherency between the CPM and system core. The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit split-transaction external data bus, which is connected directly to the external MPC8280 pins. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 1-6 Freescale Semiconductor Overview The G2_LE core has an internal common on-chip (COP) debug processor. This processor allows access to internal scan chains for debugging purposes. It is also used as a serial connection to the core for emulator support. The G2_LE core can be disabled. In this mode, the MPC8280 functions as a slave peripheral to an external core or to another PowerQUICC II device with its core enabled. 1.2.2 System Interface Unit (SIU) The SIU consists of the following: • A 60x-compatible parallel system bus configurable to 64-bit data width. The MPC8280 supports 64-, 32-, 16-, and 8-bit port sizes. The MPC8280 internal arbiter arbitrates between internal components that can access the bus (system core, PCI bridge, CPM, and one external master). This arbiter can be disabled, and an external arbiter can be used if necessary. • A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to enhance the operation of the very high-speed communication controllers. Without requiring extensive manipulation by the core, the bus can be used to store connection tables for ATM or buffer descriptors (BDs) for the communication channels or raw data that is transmitted between channels. The local bus is synchronous to the 60x bus and runs at the same frequency. • The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus. In PCI mode the bus can be programmed as a host or as an agent. The PCI bus can be configured to run synchronously or asynchronously to the 60x bus. The MPC8280 has an internal PCI bridge with an efficient 60x-to-PCI DMA for memory block transfers. • Applications that require both the local bus and PCI bus need to connect an external PCI bridge. • Memory controller supporting 12 memory banks that can be allocated for either the system or the local bus. The memory controller is an enhanced version of the MPC860 memory controller. It supports three user-programmable machines. Besides all MPC860 features, the memory controller also supports SDRAM with page mode and address data pipeline. • Supports JTAG controller IEEE 1149.1 test access port (TAP). • A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer, and other system functions useful in embedded applications. • Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/MCM69C432). 1.2.3 Communications Processor Module (CPM) The CPM contains features that allow the MPC8280 to excel in a variety of applications targeted mainly for networking and telecommunication markets. The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP performance and additional hardware and microcode routines that support high bit rate protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full-duplex). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 1-7 Overview The following list summarizes the major features of the CPM: • The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM local bus) from the 60x bus (used by the system core). With this separate bus, the CP does not affect the performance of the G2_LE core. The CP handles the lower layer tasks and DMA control activities, leaving the G2_LE core free to handle higher layer activities. The CP has an instruction set optimized for communications, but can also be used for general-purpose applications, relieving the system core of small often repeated tasks. • Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst transfers to the 60x bus and to the local bus. • Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the MPC8280), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and totally transparent operation. Each FCC can be configured to transmit fully transparent and receive HDLC or vice-versa. (Note that the MPC8270 does not support ATM (155 Mbps) protocol.) • Two multichannel controllers (MCCs) that can handle an aggregate of 256 X 64 Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also supports super-channels of rates higher than 64 Kbps and subchanneling of the 64-Kbps channels. • Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/Ethernet, highlevel synchronous data link control, HDLC, local talk, UART, synchronous UART, BISYNC, and transparent. • Two full-duplex serial management controllers (SMC) supporting GCI, UART, and transparent operations • Serial peripheral interface (SPI) and I2C bus controllers • Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs, three FCCs, and two SMCs. 1.3 Software Compatibility Issues As much as possible, the MPC8280 CPM features were made similar to those of the previous MPC860 PowerQUICC family devices and the MPC8260 PowerQUICC II family devices. The code flow ports easily from previous devices to the MPC8280, except for new protocols supported by the MPC8280. Although many registers are new, most registers retain the old status and event bits, so an understanding of the programming models of the MC68360, MPC860, or MPC85015 is helpful. Note that the MPC8280 initialization code requires changes from the MPC860 initialization code (Freescale provides reference code). 1.3.1 Signals Figure 1-2 shows MPC8280 signals grouped by function. Note that many of these signals are multiplexed and this figure does not indicate how these signals are multiplexed. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 1-8 Freescale Semiconductor Overview NOTE A bar over a signal name indicates that the signal is active low—for example, BB (bus busy). Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as TSIZ[0–3] (transfer size signals) are referred to as asserted when they are high and negated when they are low. VCCSYN/GNDSYN/VCCSYN1//VDDH/ ⎯⎯⎯> 100 VDD/VSS PCI_PAR/L_A14 1 SMI/PCI_FRAME/L_A15 1 PCI_TRDY/L_A16 1 CKSTOP_OUT/PCI_IRDY/L_A17 1 PCI_STOP/L_A18 1 PCI_DEVSEL/L_A19 1 PCI_IDSEL/L_A20 1 PCI_PERR/L_A21 1 PCI_SERR/L_A22 1 PCI_REQ0/L_A23 1 CPCI_HS_ES/PCI_REQ1/L_A24 1 PCI_GNT0/L_A25 1 CPCI_HS_LED/PCI_GNT1/L_A26 NC ⎯⎯⎯> R S T C L K J T A G TT[0–4] TSIZ[0–3] TBST GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 CPU_DBG ⎯⎯⎯> CPU_BR BR BG ABB/IRQ2 TS AACK ARTRY DBG DBB/IRQ3 D[0–63] NC/DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3/CINT IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA IRQ0/NMI_OUT IRQ7/INT_OUT/APE ⎯⎯⎯> CS[0–9] CS[10] /BCTL1 CS[11] /AP[0] ⎯⎯⎯> BADDR[27–28] ⎯⎯⎯> ALE ⎯⎯⎯> BCTL0 ⎯⎯⎯> PWE[0–7] /PSDDQM[0–7]/PBS[0–7] ⎯⎯⎯> PSDA10/PGPL0 ⎯⎯⎯> PSDWE/PGPL1 ⎯⎯⎯> POE/PSDRAS/PGPL2 ⎯⎯⎯> PSDCAS/PGPL3 PGTA /PUPMWAIT/PGPL4/PPBS ⎯⎯⎯> PSDAMUX/PGPL5 CPU_BR BR BG ABB/IRQ2 TS AACK ARTRY DBG DBB/IRQ3 D[0–63] NC/DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3/CINT IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA IRQ0/NMI_OUT IRQ7/INT_OUT/APE ⎯⎯⎯> CS[0–9] CS[10] /BCTL1 CS[11] /AP[0] ⎯⎯⎯> BADDR[27–28] ⎯⎯⎯> ALE ⎯⎯⎯> BCTL0 ⎯⎯⎯> PWE[0–7] /PSDDQM[0–7]/PBS[0–7] ⎯⎯⎯> PSDA10/PGPL0 ⎯⎯⎯> PSDWE/PGPL1 ⎯⎯⎯> POE/PSDRAS/PGPL2 ⎯⎯⎯> PSDCAS/PGPL3 PGTA /PUPMWAIT/PGPL4/PPBS ⎯⎯⎯> PSDAMUX/PGPL5 15, then 15 or more retries were required. The controller writes this field after it successfully sends the buffer. Underrun. Set when the Ethernet controller encounters a transmitter underrun while sending the buffer. The Ethernet controller writes UN after it finishes sending the buffer. Carrier sense lost. Set when carrier sense is lost during frame transmission. The Ethernet controller writes CSL after it finishes sending the buffer. 10–13 RC 14 15 UN CSL Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” 25.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) The SCC event register (SCCE) is used as the Ethernet event register to generate interrupts and report events recognized by the Ethernet channel. When an event is recognized, the Ethernet controller sets the corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the equivalent bits in the Ethernet mask register (SCCM). SCCE bits are cleared by writing ones; writing zeros has no effect. All unmasked bits must be cleared before the CPM clears the internal interrupt request. The SCCE/SCCM registers are displayed in Figure 25-9. 0 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr — GRA 0000_0000_0000_0000 R/W — TXE RXF BSY TXB RXB 0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4) 0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4) Figure 25-9. SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) Table 25-9 describes SCCE and SCCM fields. Table 25-9. SCCE/SCCM Field Descriptions Bits 0–7 8 9–10 11 12 Name — GRA — TXE RXF Reserved, should be cleared. Graceful stop complete. Set as soon the transmitter finishes any frame that was in progress when a GRACEFUL STOP TRANSMIT command was issued. It is set immediately if no frame was in progress. Reserved, should be cleared. Set when an error occurs on the transmitter channel. This event is not maskable via the TxBD[I] bit. Rx frame. Set when a complete frame has been received on the Ethernet channel. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 25-20 Freescale Semiconductor SCC Ethernet Mode Table 25-9. SCCE/SCCM Field Descriptions (continued) Bits 13 14 15 Name BSY TXB RXB Description Busy condition. Set when a frame is received and discarded due to a lack of buffers. Tx buffer. Set when a buffer has been sent on the Ethernet channel. Rx buffer. Set when a buffer that was not a complete frame was received on the Ethernet channel. Figure 25-10 shows an example of interrupts that can be generated in Ethernet protocol. Frame Received in Ethernet Time RXD RENA Ethernet SCCE Events Line Idle Stored in Rx Buffer P SFD DA SA T/L D CR Line Idle RXB RXF NOTES: 1. RXB event assumes receive buffers are 64 bytes each. 2. The RENA events, if required, must be programmed in the parallel I/O ports, not in the SCC itself. 3. The RxF interrupt may occur later than RENA due to receive FIFO latency. Frame Transmitted by Ethernet TXD TENA CLSN Ethernet SCCE Events Line Idle Stored in Tx Buffer P SFD DA SA T/L D CR Line Idle TXB TXB, GRA NOTES: 1. TXB events assume the frame required two transmit buffers. 2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission. 3. The TENA or CLSN events, if required, must be programmed in the parallel I/O ports, not in the SCC itself. LEGEND: P = Preamble, SFD = Start frame delimiter, DA and SA = Source/Destination address, T/L = Type/Length, D = Data, CR = CRC bytes Figure 25-10. Ethernet Interrupt Events Example Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The current state of the RENA and CLSN signals can be found in the parallel I/O ports. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 25-21 SCC Ethernet Mode 25.21 SCC Ethernet Programming Example The following is an initialization sequence for the SCC2 in Ethernet mode. The CLK3 pin is used for the Ethernet receiver and CLK4 is used for the transmitter. 1. Configure port D pins to enable TXD2 and RXD2. Set PPARD[27,28] and PDIRD[27] and clear PDIRD[28] and PSORD[27,28]. 2. Configure ports C and D pins to enable TENA2 (RTS2), CLSN2 (CTS2) and RENA2 (CD2). Set PPARD[26], PPARC[12,13] and PDIRD[26] and clear PDIRC[12,13], PSORC[12,13] and PSORD[26]. 3. Configure port C pins to enable CLK3 and CLK4. Set PPARC[28,29] and clear PDIRC[28,29] and PSORC[28,29]. 4. Connect CLK3 to the SCC2 receiver and CLK4 to the transmitter using the CPM mux. Program CMXSCR[R2CS] to 0b110 and CMXSCR[T2CS] to 0b111. 5. Connect the SCC2 to the NMSI and clear CMXSCR[SC2]. 6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM and one TxBD following that RxBD, write RBASE with 0x0000 and TBASE with 0x0008. 7. Write 0x04A1_0000 to the CPCR to execute an INIT RX AND TX PARAMETERS command for this channel. 8. Clear CRCEC, ALEC, and DISFC for clarity. 9. Write PAD with 0x8888 for the PAD value. 10. Write RET_LIM with 0x000F. 11. Write MFLR with 0x05EE to make the maximum frame size 1518 bytes. 12. Write MINFLR with 0x0040 to make the minimum frame size 64 bytes. 13. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520 bytes. 14. Clear GADDR1–GADDR4. The group hash table is not used. 15. Write PADDR1_H with 0x0000, PADDR1_M with 0x0000, and PADDR1_L with 0x0040 to configure the physical address. 16. Clear P_PER. It is not used. 17. Clear IADDR1–IADDR4. The individual hash table is not used. 18. Clear TADDR_H, TADDR_M, and TADDR_L for clarity. 19. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 20. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main memory and contains fourteen 8-bit characters (destination and source addresses plus the type field). Write 0xFC00 to TxBD[Status and Control], add PAD to the frame and generate a CRC. Then write 0x000D to TxBD[Data Length] and 0x0000_2000 to TxBD[Buffer Pointer]. 21. Write 0xFFFF to the SCCE register to clear any previous events. 22. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 25-22 Freescale Semiconductor SCC Ethernet Mode 23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing 0xFFFF_FFFF to it. 24. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes. 25. Write 0x1088_000C to the GSMR_L2 register to configure CTS (CLSN) and CD (RENA) to automatically control transmission and reception (DIAG bits) and the Ethernet mode. TCI is set to allow more setup time for the EEST to receive the MPC8280 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL is not used with Ethernet. Note that the ENT and ENR are not enabled yet. 26. Write 0xD555 to the DSR. 27. Set the PSMR2 to 0x0A0A to configure 32-bit CRC, promiscuous mode, and begin searching for the start frame delimiter 22 bits after RENA2 (CD2). 28. Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write ensures that ENT and ENR are enabled last. After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 25-23 SCC Ethernet Mode MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 25-24 Freescale Semiconductor Chapter 26 SCC AppleTalk Mode AppleTalk is a set of protocols developed by Apple Computer, Inc. to provide a LAN service between Macintosh computers and printers. Although AppleTalk can be implemented over a variety of physical and link layers, including Ethernet, AppleTalk protocols have been most closely associated with the LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps. In this manual, the term ‘AppleTalk controller’ refers to the support that the MPC8280 provides for LocalTalk protocol. The AppleTalk controller provides required frame synchronization, bit sequence, preamble, and postamble onto standard HDLC frames. These capabilities, with the use of the HDLC controller in conjunction with DPLL operation in FM0 mode, provide the proper connection formats to the LocalTalk bus. 26.1 Operating the LocalTalk Bus A LocalTalk frame, shown in Figure 26-1, is basically a modified HDLC frame. Sync Sequence > 3 b its HDLC Flags 2 or more bytes Destination Address 1 byte Source Address 1 byte Control Byte 1 byte Data (Optional) 0-600 bytes CRC-16 2 bytes Closing Flag 1 byte Abort Sequence 12–18 ones Figure 26-1. LocalTalk Frame Format First, a synchronization sequence of more than three bits is sent. This sequence consists of at least one logical one bit (FM0 encoded) followed by two bit times or more of line idle with no particular maximum time specified. The idle time allows LocalTalk equipment to sense a carrier by detecting a missing clock on the line. The remainder of the frame is a typical half-duplex HDLC frame. Two or more flags are sent, allowing bit, byte, and frame delineation or detection. Two bytes of address, destination, and source are sent next, followed by a byte of control and 0–600 data bytes. Next, two bytes of CRC (the common 16-bit CRC-CCITT polynomial referenced in the HDLC standard protocol) are sent. The LocalTalk frame is then terminated by a flag and a restricted HDLC abort sequence. Then the transmitter’s driver is disabled. The control byte within the LocalTalk frame indicates the type of frame. Control byte values from 0x01–0x7F are data frames; control byte values from 0x80–0xFF are control frames. Four control frames are defined: • ENQ—Enquiry • ACK—Enquiry acknowledgment • RTS—Request to send a data frame • CTS—Clear to send a data frame Frames are sent in groups known as dialogs, which are handled by the software. For instance, to transfer a data frame, three frames are sent over the network. An RTS frame (not to be confused with the RS-232 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 26-1 SCC AppleTalk Mode RTS pin) is sent to request the network, a CTS frame is sent by the destination node, and the data frame is sent by the requesting node. These three frames comprise one possible type of dialog. After a dialog begins, other nodes cannot start sending until the dialog is complete. Frames within a dialog are sent with a maximum interframe gap (IFG) of 200 µs. Although the LocalTalk specification does not state it, there is also a minimum recommended IFG of 50 µs. Dialogs must be separated by a minimum interdialog gap (IDG) of 400 µs. In general, these gaps are implemented by the software. Depending on the protocol, collisions should be encountered only during RTS and ENQ frames. Once frame transmission begins, it is fully sent, regardless of whether it collides with another frame. ENQ frames are infrequent and are sent only when a node powers up and enters the network. A higher-level protocol controls the uniqueness and transmission of ENQ frames. In addition to the frame fields, LocalTalk requires that the frame be FM0 (differential Manchester space) encoded, which requires one level transition on every bit boundary. If the value to be encoded is a logical zero, FM0 requires a second transition in the middle of the bit time. The purpose of FM0 encoding is to avoid having to transmit clocking information on a separate wire. With FM0, the clocking information is present whenever valid data is present. 26.2 Features The following list summarizes the features of the SCC in AppleTalk mode: • Superset of the HDLC controller features • FM0 encoding/decoding • Programmable transmission of sync sequence • Automatic postamble transmission • Reception of sync sequence does not cause extra SCCE[DCC] interrupts • Reception is automatically disabled while sending a frame • Transmit-on-demand feature expedites frames • Connects directly to an RS-422 transceiver 26.3 Connecting to AppleTalk As shown in Figure 26-2, the MPC8280 connects to LocalTalk, and, using TXD, RTS, and RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 26-2 Freescale Semiconductor SCC AppleTalk Mode MPC8280 RS-422 SCC TXD RTS RXD Tx Data Tx Enable Rx Data MINI-DIN 8 Connection Stored in Receive Buffer Stored in Transmit Buffer TXD RTS Standard HDLC frame handling 6-Bit Sync Two HDLC Destination Source Sequence Flags Address Address Control Byte Data CRC-16 Closing Flag 16 Ones (Abort) Figure 26-2. Connecting the MPC8280 to LocalTalk The 16× overspeed of a 3.686-MHz clock can be generated from an external frequency source or from one of the baud rate generators if the resulting output frequency is close to a multiple of the 3.686 MHz frequency. The MPC8280 asserts RTS throughout the duration of the frame so that RTS can be used to enable the RS-422 transmit driver. 26.4 Programming the SCC in AppleTalk Mode The AppleTalk controller is implemented by setting certain bits in the HDLC controller. Otherwise, Chapter 22, “SCC HDLC Mode,” describes how to program the HDLC controller. Use GSMR, PSMR, or TODR to program the AppleTalk controller. 26.4.1 Programming the GSMR Program the GSMR as described below: 1. Set MODE to 0b0010 (AppleTalk). 2. Set DIAG to 0b00 for normal operation, with CD and CTS grounded or configured for parallel I/O. This causes CD and CTS to be internally asserted to the SCC. 3. Set RDCR and TDCR to (0b10) a 16× clock. 4. Set the TENC and RENC bits to 0b010 (FM0). 5. Clear TEND for default operation. 6. Set TPP to 0b11 for a preamble pattern of all ones. 7. Set TPL to 0b000 to transmit the next frame with no synchronization sequence and to 001 to transmit the next frame with the LocalTalk synchronization sequence. For example, data frames do not require a preceding synchronization sequence. These bits may be modified on-the-fly if the AppleTalk protocol is selected. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 26-3 SCC AppleTalk Mode 8. Clear TINV and RINV so data will not be inverted. 9. Set TSNC to 1.5 bit times (0b10). 10. Clear EDGE. Both the positive and negative edges are used to change the sample point (default). 11. Clear RTSM (default). 12. Set all other bits to zero or default. 13. Set ENT and ENR as the last step to begin operation. 26.4.2 Programming the PSMR Follow these steps to program the protocol-specific mode register: 1. Set NOF to 0b0001 giving two flags before frames (one opening flag, plus one additional flag). 2. Set CRC 16-bit CRC-CCITT. 3. Set DRT. 4. Set all other bits to zero or default. For the PSMR definition, see Section 22.8, “HDLC Mode Register (PSMR).” 26.4.3 Programming the TODR Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 20.1.4, “Transmit-on-Demand Register (TODR).” 26.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 22.14.6, “HDLC Bus Protocol Programming.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 26-4 Freescale Semiconductor Chapter 27 Universal Serial Bus Controller The universal serial bus (USB) controller allows the MPC8280 to communicate with other devices via a USB connection. This chapter describes the MPC8280’s USB controller, including basic operation, the parameter RAM, and registers. It also provides programming examples for initializing host mode and function mode of the USB controller. 27.1 USB Integration in the MPC8280 The following restrictions apply when enabling the USB controller in the MPC8280: • The USB peripheral and SCC4 are mutually exclusive: it is not legal to enable both peripherals at the same time. • The USB controller pins are multiplexed with SCC4 pins in the parallel I/O. Refer to Chapter 41, “Parallel I/O Ports.” The user programs the parallel I/O registers as if scc4 was being used. If the USB controller is enabled, the signals are automatically routed to the USB controller instead of SCC4. • The USB controller uses the transmit clock of SCC4 as its clock. The user must program CMXSCR[T4CS] (refer to Section 16.4.6, “CMX SMC Clock Route Register (CMXSMR)”) to the desired source for USB when the USB controller is enabled. • The user must clear CMXSCR[SC4] (refer to Section 16.4.5, “CMX SCC Clock Route Register (CMXSCR)) when the USB controller is enabled. 27.2 Overview The universal serial bus (USB) is an industry-standard extension to the PC architecture. The USB controller on the MPC8280 supports data exchange between a wide range of simultaneously accessible peripherals. Attached peripherals share USB bandwidth through a host-scheduled, token-based protocol. The USB physical interconnect is a tiered-star topology, and the center of each star is a hub. Each wire segment is a point-to-point connection between the host and a hub or function, or a hub connected to another hub or a function. The USB transfers signal and power over a four-wire cable, and the signaling occurs over two wires and point-to-point segments. The USB full speed signaling bit rate is 12 Mbps. Also, a limited capability low-speed signaling mode is defined at 1.5 Mbps. Refer to the USB Specification Revision 2.0 for further details. It can be downloaded from http://www.usb.org. The MPC8280 USB controller consists of a transmitter module, receiver module, and two protocol state machines. The protocol state machines control the receiver and transmitter modules. One state machine implements the function state diagram and the other implements the host state diagram. The USB controller can implement a USB function endpoint, a USB host, or both for testing purposes (loop-back diagnostics). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-1 Universal Serial Bus Controller 27.2.1 USB Controller Key Features The USB function mode features are as follows: • Four independent endpoints support control, bulk, interrupt, and isochronous data transfers • CRC16 generation and checking • CRC5 checking • NRZI encoding/decoding with bit stuffing • 12- or 1.5-Mbps data rate • Flexible data buffers with multiple buffers per frame • Automatic retransmission upon transmit error The USB host controller features are as follows: • Supports control, bulk, interrupt, and isochronous data transfers • CRC16 generation and checking • NRZI encoding/decoding with bit stuffing • Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. • Flexible data buffers with multiple buffers per frame • Supports local loopback mode for diagnostics (12 Mbps only) 27.3 Host Controller Limitations The following tasks are not supported by the hardware and must be implemented in software: • Scheduling the various transfers within and between frames • Retransmission after an error and error recovery • Incrementing the frame number and generating CRC5 for the SOF (Start of Frame) token once per frame (1 ms) Additionally, when using the packet-level interface described in Section 27.5.1.1, “Packet-Level Interface,” the tokens must be prepared by the software. Because the MPC8280 USB host controller does not integrate the root hub, an external hub is required when more than one device is connected to the host. Also note that the host controller programming model does not conform to the open host controller interface (OHCI) or universal host controller interface (UHCI) standards in which software drivers are hardware-independent. 27.3.1 USB Controller Pin Functions and Clocking The USB controller interfaces to the USB bus through a differential line driver and differential line receiver. The OE (output enable) signal enables the line driver when the USB controller transmits on the bus. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-2 Freescale Semiconductor Universal Serial Bus Controller MPC8280 USB transceiver USBOE USBTXP USBTXN D+ D– + USBRXD – USBRXP USBRXN Figure 27-1. USB Interface The reference clock for the USB controller (USBCLK) is used by the DPLL circuitry to recover the bit rate clock. The source for USBCLK is selected in CMXSCR[TS4CS] (refer to Section 16.4.3, “CMX SI2 Clock Route Register (CMXSI2CR)”). The MPC8280 can run at different frequencies, but the USB reference clock must be four times the USB bit rate. Thus, USBCLK must be 48 MHz for a 12-Mbps full-speed transfer or 6 MHz for a 1.5-Mbps low-speed transfer. There are six I/O pins associated with the USB port. Their functionality is described in Table 27-1. Additional control lines that might be needed by some transceivers (e.g., speed select, low power control) may be supported by general purpose output lines. Table 27-1. USB Pins Functions Signal USBTXN, USBTXP I/O O . Function Outputs from the USB transmitter, inputs to the differential driver TP 0 0 1 1 TN 0 1 0 1 Result Single ended “0” Logic “0” Logic “1” — USBOE O Output enable. Enables the transceiver to send data on the bus. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-3 Universal Serial Bus Controller Table 27-1. USB Pins Functions (continued) Signal USBRXD USBRXP, USBRXN I/O I I Function Receive data. Input to the USB receiver from the differential line receiver. Gated version of D+ and D–. Used to detect single-ended zeros and the interconnect speed. RP 0 1 0 1 RN 0 0 1 1 Result Single ended “0” Full speed Low speed — 27.4 USB Function Description As shown in Figure 27-2, the USB function consists of transmitter and receiver sections and a control unit. The USB transmitter contains four independent FIFOs, each containing 16 bytes. There is a dedicated FIFO for each of the four supported endpoints. The USB receiver has a single 16-byte FIFO. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-4 Freescale Semiconductor Universal Serial Bus Controller Peripheral bus U-bus Port control Tx data FIFO 16-byte Mode register Command register Rx FIFO 16-byte USB function state machine Receiver DPLL/ Bus Interface External transceiver 27.4.1 USB Function Controller Transmit/Receive After reset condition, the USB function is addressable at the default address (0x00). During the enumeration process the USB function is assigned by the host with a unique address. The USB slave address register (refer to Section 27.5.7.2, “USB Slave Address Register (USADR)”) should be programmed with the assigned address. The USB function controller supports four independent endpoints. Each endpoint can be configured to support either control, interrupt, bulk, or isochronous transfers modes. This is done by programming the endpoint registers (refer to Section 27.5.7.3, “USB Endpoint Registers (USEP1–USEP4)”). NOTE It is mandatory that endpoint 0 be configured as a control transfer type. This endpoint is used by the USB system software as a control pipe. Additional control pipes may be provided by other endpoints. Once enabled, the USB function controller looks for valid token packets. Figure 27-3 and Table 27-2 describe the behavior of the USB controller for each token. Tokens that are not valid (that is, PID check fails or CRC check fails or packet length is not 3 bytes) are ignored by the USB function controller. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-5 tx data fifo tx data fifo tx data fifo Transmitter Port configuration Address register mode register m ode register Endpoint registers Figure 27-2. USB Function Block Diagram Universal Serial Bus Controller Reset Unenumerated Enumeration process IDLE SETUP token IN token Setup Transmit Receive OUT token Start of frame SOF token Figure 27-3. USB Controller Operating Modes Table 27-2. USB Tokens Token OUT Description Reception begins when an OUT token is received. The USB controller fetches the next BD associated with the endpoint; if the BD is empty, the controller starts sending the incoming packet to the buffer. After the buffer is full, the USB controller clears RxBD[E] and generates an interrupt if RxBD[I] = 1. If the incoming packet is larger than the buffer, the USB controller fetches the next BD, and, if it is empty, sends the rest of the packet to its buffer. The entire packet, including the DATA0/DATA1 PID, are written to the receive buffers. Software must check data packet synchronization by monitoring the DATA0/DATA1 PID sequence toggle. If the packet reception has no CRC or bit stuff errors, the USB receiver sends the handshake selected in the endpoint configuration register USEPn[RHS] (see table below) to the host. If an error occurs, no handshake packet is returned and error status bits are set in the last RxBD associated with this packet. USB Out Token Reception USEPn[RHS] xx 00 (Normal) 01 (Ignore) 10 (NAK) 11 (STALL) Data Packet Corrupted Yes No No No No Handshake Sent to Host None (data discarded) ACK None NAK STALL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-6 Freescale Semiconductor Universal Serial Bus Controller Table 27-2. USB Tokens (continued) Token IN Description To guarantee a transfer, the control software must preload the endpoint FIFO with a data packet before receiving an IN token. Software should set up the endpoint TxBD table and set USCOM[STR]. The USB controller fills the transmit FIFO and waits for the IN token. Once the token is received and the FIFO has been loaded with the last data byte or with at least four bytes, transmission begins. The four-byte minimum is a threshold to prevent underruns in the FIFO. If data is not ready in the transmit FIFO or if USEPn[THS] is set to respond with NAK, a NAK handshake is returned. If USEPn[THS] was set to respond with STALL, a STALL handshake is returned. (See table below.) When the end of the last buffer is reached (TxBD[L] is set), the CRC is appended. After the frame is sent, the USB controller waits for a handshake packet. If the host fails to acknowledge the packet, the timeout status bit TxBD[TO] is set. Software must set the proper DATA0/DATA1 PID in the transmitted packet. USB In Token Reception USEPn[THS] 00 (Normal) FIFO Loaded No Yes 01 (Ignore) 10 (NAK) 11 (STALL) — — — Handshake Sent to Host NAK (data discarded) Data packet is sent. None NAK (data discarded) STALL SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP token is recognized only by a control endpoint. When a SETUP token is received, setup reception begins. The USB controller fetches the next BD associated with the endpoint; if it is empty, the controller starts transferring the incoming packet to the buffer. When the buffer is full, the USB controller clears RxBD[E] and generates an interrupt if RxBD[I] = 1. If the incoming packet is larger than the buffer, the USB controller fetches the next BD and, if it is empty, continues transferring the rest of the packet to this buffer. The entire data packet including the DATA0 PID is written to the receive buffers. If the packet was received without CRC or bit stuff errors, an ACK handshake is sent to the host. If an error occurs, no handshake packet is returned and error status bits are set in the last RxBD associated with this packet. When an SOF packet is received, the USB controller issues a SOF maskable interrupt and the frame number entry in the parameter RAM is updated. Start of frame (SOF) Preamble The PRE token signals the hub that a low-speed transaction is about to occur. The PRE token is read (PRE) only by the hub. The USB controller ignores the PRE token function in function mode. 27.5 USB Host Description When programmed as a host, the USB controller supports a limited host functionality. The following sections describe the available host functionality, its limitations, and the programming model. Figure 27-4 illustrates the functionality of the USB controller in host mode. The USB controller consists of transmitter and receiver sections, host control unit, and a function control unit, which is used for testing MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-7 Universal Serial Bus Controller purposes. The USB transmitter contains four independent FIFOs, each containing 16 bytes. Endpoint 1 is dedicated for host transactions; endpoints 2-4 are for function transactions in test mode. There is a dedicated FIFO for each of the four supported endpoints; endpoint 1 FIFO is for host transactions. The USB receiver has a single 16-byte FIFO. Peripheral bus U-bus Port control Tx data FIFO 16-byte Mode register Command register Rx FIFO 16-byte Tx data FIFO EP0 USB host state machine USB function state machine Receiver Transmitter DPLL/ Bus Interface External transceiver Figure 27-4. USB Controller Block Diagram 27.5.1 USB Host Controller Transmit/Receive The USB host controller initiates all USB transactions in the system. After the reset condition, the HOST bit in USB mode register should be set (refer to Section 27.5.7.1, “USB Mode Register (USMOD)”) to enable host operation. USEP1 should be programmed for host operation as described in Section 27.5.7.3, “USB Endpoint Registers (USEP1–USEP4).” Once enabled by setting the USMOD[EN] bit, the USB host controller waits for a packet in its transmit FIFO. When the FIFO contains data for transmission, the host transaction begins. Figure 27-3 and Table 27-2 describe the behavior of the USB host controller for each transaction. Low speed transactions start with a preamble that is generated by the USB host controller state machine when the LSP bit in the TxBD is set. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-8 Freescale Semiconductor tx data fifo tx data fifo Port configuration Address register mode register mode register Endpoint registers Universal Serial Bus Controller When USMOD[TEST] is programmed, both the host state machine and function state machine are active. End points 2-4 receive/transmit data according to tokens received from host. The programming model and functional description are described in Section 27.5.7, “USB Function Programming Model.” Reset IDLE Low Speed Full Speed PREAMBLE SETUP token OUT token Setup Transmit Receive IN token Figure 27-5. USB Controller Operating Modes 27.5.1.1 Packet-Level Interface If USEP1[RTE] is 0, the USB host controller uses a packet-level interface to communicate with the user. Each transmit packet is prepared in a buffer and referenced by a TxBD as described in Section 27.6.3, “USB Transmit Buffer Descriptor (Tx BD) for Host.” Each receive packet is stored in a buffer referenced by a RxBD as described in Section 27.6.1, “USB Receive Buffer Descriptor (Rx BD) for Host and Function.” A SETUP or OUT transaction requires at least two TxBDs, one for the token and one or more for the data packet. An IN transaction requires one TxBD for the token and one or more RxBDs for the data packet. Tokens are not checked for validity and are transmitted as is. The user is responsible for token validity as well as CRC5 generation. 27.5.1.2 Transaction-Level Interface NOTE The transaction-level interface described in this section is available only on .13 µm (HiP7) Revision A.0 and future devices. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-9 Universal Serial Bus Controller If USEP1[RTE] is 1, the USB host controller uses a transaction-level interface to communicate with the user. Each transaction uses one TrBD as described in Section 27.6.4, “USB Transaction Buffer Descriptor (TrBD) for Host.” The USB host controller generates the token based on the TOK field in the TrBD. For SETUP and OUT transactions, the TrBD points to a single buffer containing the data packet to be transmitted. For IN transactions, the TrBD points to a single buffer which is used for the receive data packet. Table 27-3. USB Tokens Token OUT Packet-Level Interface Transmission begins when the USB host controller fetches a TxBD containing OUT token and a data TxBD and loads them to the host FIFO. The token and data are transmitted and a handshake is expected. If a handshake is not received within the expected time interval, the USB controller clears TxBD[R] of data BD, sets the TxBD[TO] indication and generates a TXE1 interrupt. When STALL or NAK is received within the expected time interval, the USB controller clears TxBD[R] of data BD, sets the TxBD[STALL] or TXBD[NAK] indication and generates a TXE1 interrupt. When ACK is received within the expected time interval, the USB controller clears TxBD[R] of data BD, and generates an interrupt if TxBD[I] = 1.No indication is set. The token TxBD[R] is cleared right after the OUT token transmission. Description Transaction-Level Interface Transmission begins when the USB host controller fetches a TrBD with the TOK field indicating an OUT transaction. The token is generated and then the data packet from the buffer is transmitted and a handshake is expected. If a handshake is not received within the expected time interval, the USB controller clears TrBD[R], sets the TrBD[TO] indication and generates a TXE1 interrupt. When STALL or NAK is received within the expected time interval, the USB controller clears TrBD[R], sets the TrBD[STALL] or TrBD[NAK] indication and generates a TXE1 interrupt. When ACK is received within the expected time interval, the USB controller clears TrBD[R], and generates a TXB interrupt if TrBD[I] = 1.No indication is set. USB Out Transaction Token OUT Data Sent by host Handshake Received by Function None ACK NAK STALL Indication on TxBD/TrBD TO None NAK STALL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-10 Freescale Semiconductor Universal Serial Bus Controller Table 27-3. USB Tokens (continued) Token IN Packet-Level Interface Transmission begins when the USB host controller fetches a TxBD containing an IN token and loads the token to FIFO. After the IN token is transmitted the USB host controller waits for reception of data within expected time interval. On reception of a correct DATA PID an RxBD is fetched. The received data and DATA PID are stored in receive FIFO. If RxBD[E] is set PID and data will be moved to the buffer. While receiving the data the USB host controller calculates CRC16, performs bit un-stuffing. On end of reception calculated CRC is compared to received and octet alignment is checked, RxBD[E] is cleared, RxBD[PID] is set according to received DATA PID and error indications are set if required:RxBD[CR] for failed CRC check, RxBD[NO] for non-octet sized data and RxBD[AB] if bit stuffing error occurred. If no correct DATA PID or no data at all received during the expected time interval a TO indication in the token TxBD is set. Description Transaction-Level Interface Transmission begins when the USB host controller fetches a TrBD with the TOK field indicating an IN transaction. After the IN token is generated and transmitted, the USB host controller waits for reception of data within the expected time interval. The received data packet is stored in buffer reference by the TrBD. While receiving the data the USB host controller calculates CRC16 and performs bit un-stuffing. At end of the packet, the calculated CRC is compared to the received value and octet alignment is checked, TrBD[R] is cleared, TrBD[PID] is set according to the received DATA PID and error indications are set if required:TrBD[CR] for failed CRC check, TrBD[NO] for non-octet sized data and TrBD[AB] if bit stuffing error occurred. If any of the above errors are reported, TrBD[RXER] is also set, and a TXE1 interrupt is generated. If no correct DATA PID or no data at all received during the expected time interval, a TrBD[TO] is set and a TXE1 interrupt is generated. If no errors occurred and TrBD[I] is set, a TXB interrupt is generated to indicate successful completion of the transaction. USB In Transaction Token IN Data Transmitted by Function Received correctly Received corrupted Handshake Generated by Host ACK None Indication on BD RxBD[E]/TrBD[R] is cleared RxBD[CR]/TrBD[CR} or RxBD[AB]/TrBD[AB] or RxBD[NO]/TrBD[NO] TxBD[TO]/TrBD[TO] None None SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP token is recognized only by a control endpoint and cannot be answered with NAK or STALL, therefore, the host expects either an ACK or no handshake at all. SOF is generated every 1 ms. The timing must be exact and is controlled by an internal timer. From the host state machine point of view it is a packet to transmit, placed in its FIFO, transmitted as is. Start of Frame (SOF) Preamble The PRE token signals the hub that a low-speed transaction is about to occur. The PRE token is read only (PRE) by the hub. The USB host controller generates a full-speed PRE token before sending a packet to a low-speed peripheral. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-11 Universal Serial Bus Controller 27.5.2 SOF Transmission for USB Host Controller The following section describes the mechanism used by the USB Host Controller to support the automatic transmission of SOF tokens. This mechanism is enabled by setting USMOD[SFTE]. SOF packets should be transmitted every 1 ms. Since the time interval between two SOF packets must be more precise than could be accomplished by software, a hardware timer is used to assert an interrupt to the CP. When the interrupt is serviced by the CP, it prepares a SOF token and loads it to the host endpoint. Once the SOF token is loaded to the FIFO, it is transmitted like any other packet. Before each SOF transmission, the software should prepare a value for the frame number and CRC5 to be transmitted in SOF token and place it in the parameter RAM (for further details please refer to Section 27.5.5, “Frame Number (FRAME_N)”. One possible implementation would be to use the SOF interrupt (see Section 27.5.7.5, “USB Event Register (USBER)”) to prepare the frame number for the next SOF packet. The SFT interrupt should not be used for this purpose since it is generated before the SOF packet is actually transmitted. The application software should also guarantee that the USB host has completed all pending transactions prior to the 1 ms tick so that the transmit FIFO is empty at this point. The current value of the SOF timer may be read at any time to synchronize the software with the USB frames. See Section 27.5.7.8, “USB Start of Frame Timer (USSFT)” for more information. 27.5.3 USB Function and Host Parameter RAM Memory Map The USB controller parameter RAM area, shown in Table 27-4, begins at the USB base address, 0x8B00 (offset from RAM_Base). Note that the user must initialize certain parameter RAM values before the USB controller is enabled. Table 27-4. USB Parameter RAM Memory Map Address USB Base + 00 USB Base + 02 USB Base + 04 USB Base + 06 USB Base + 08 Name1 EP1PTR EP2PTR EP3PTR EP4PTR RSTATE Width Half word Half word Half word Half word Word Word Half word Description Endpoint pointer registers 1–4. The endpoint parameter block pointers are index pointers to each endpoint’s parameter block. Parameter blocks can be allocated to any address divisible by 32 in the dual port RAM. See Figure 27-6. The map of the endpoint parameter block is shown in Table 27-5 Note: When USB host mode is set EP1PTR must be used for the host endpoint. Receive internal state. Reserved for CP use only. Should be cleared before enabling the USB controller. Receive internal data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed. Frame number. See Figure 27-7 Note: The definition of this parameter is different for host mode and function mode. Receive internal byte count. A down-count value that is initialized with the MRBLR value and decremented with every byte written by the SDMA channels. Receive temp. Reserved for CP use only. USB Base + 0C RPTR USB Base + 10 FRAME_ N RBCNT USB Base + 12 Half word USB Base + 14 RTEMP Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-12 Freescale Semiconductor Universal Serial Bus Controller Table 27-4. USB Parameter RAM Memory Map (continued) Address USB Base + 18 Name1 RXUSB_ Data Width Word Half word Rx Data temp Rx microcode return address temp Description USB Base + 1C RXUPTR 1 The items in boldface should be initialized by the user before the USB controller is enabled; other values are initialized by the CP. Once initialized, the parameter RAM values do not normally need to be accessed by user software. They should only be modified when no USB activity is in progress. 27.5.4 Endpoint Parameters Block Pointer (EPxPTR) The endpoint parameter block pointers (EPxPTR) are DPRAM indices to an endpoint’s parameter block. The parameter block can be allocated to any address that is divisible by 32. The format of the endpoint pointer registers (EPxPTR) is shown in Figure 27-6. 0 10 11 15 Field R/W Reset Addr Endpoint Index Pointer R/W — — USB base + 0x00 (EP1PTR), 0x02 (EP2PTR), 0x04 (EP3PTR), 0x06 (EP4PTR) Figure 27-6. Endpoint Pointer Registers (EPxPTR) The map of the endpoint parameter block is shown in Table 27-5. Table 27-5. Endpoint Parameter Block Offset1 0x00 0x02 Name2 RBASE TBASE Width Description 16 bits RxBD/TxBD base addresses. Define the starting location in dual-port RAM for the USB controller’s TxBDs and RxBDs. This provides flexibility in how BDs are 16 bits partitioned. Setting W in the last BD in each list determines how many BDs to allocate for the controller’s send and receive sides. These entries must be initialized before the controller is enabled. Overlapping USB BD tables with another serial controller’s BDs causes erratic operation. RBASE and TBASE values should be divisible by 8. When using the transaction-level interface in host mode, TBASE points to the TrBD ring, and RBASE is unused. 8 bits 8 bits Rx/Tx function code. Controls the value to appear on AT[1–3] when the associated SDMA channel accesses memory and the byte-ordering convention. 0x04 0x05 RFCR TFCR MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-13 Universal Serial Bus Controller Table 27-5. Endpoint Parameter Block (continued) Offset1 0x06 Name2 MRBLR Width Description 16 bits Maximum receive buffer length. Defines the maximum number of bytes the MPC8280 writes to the USB receive buffer before moving to the next buffer. MRBLR must be divisible by 4. The MPC8280 can write fewer data bytes to the buffer than the MRBLR value if a condition such as an error or end-of-packet occurs, but it never exceeds MRBLR. Therefore, user-supplied buffers should never be smaller than MRBLR. MRBLR is not designed to be changed dynamically for the currently active RxBD during USB operation; however, MRBLR can be modified safely for the next and subsequent RxBDs using a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). Transmit buffers for the USB controller are not affected by the MRBLR value. Transmit buffer lengths can vary individually, as needed. The number of bytes to be sent is chosen by programming TxBD[Data Length]. When using the transaction-level interface in host mode, this field is used by the CP and does not have to be initialized by the user. 16 bits RxBD pointer. Points to the next BD the receiver will transfer data to when it is in an idle state or to the current BD while processing a frame. Software should initialize RBPTR after reset. When the end of the BD table is reached, the CP initializes this pointer to the value programmed in RBASE. Although the user does not need to write RBPTR in most applications (except initialization), it can be changed when the receiver is disabled or when no receive buffer is being used. When using the transaction-level interface in host mode, this field is unused. 16 bits TxBD pointer. Points to the next BD that the transmitter will transfer data from when it is in an idle state or to the current BD during frame transmission. TBPTR should be initialized by the software after reset. When the end of BD table is reached, the CP initializes this pointer to the value programmed in the TBASEn entry. Although the user never needs to write TBPTR, in most applications (except initialization), it can be changed when the transmitter is disabled or when no transmit buffer is being used. 32 bits Transmit internal state. Reserved for CP use only. Should be cleared before enabling the USB controller. 32 bits Transmit internal data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed. 0x08 RBPTR 0X0A TBPTR 0X0C 0x10 0x14 0x16 0x18 0x1C 0x1E 1 2 TSTATE3 TPTR3 TCRC3 TBCNT3 TTEMP TXUSBU _PTR HIMMR 16 bits Transmit temp CRC. Reserved for CP use only. 16 bits Transmit internal byte count. A down-count value that is initialized with the TxBD data length and decremented with every byte read by the SDMA channels. 32 bits Tx temp 16 bits Tx microcode return address temp 16 bits When using the transaction-based interface in host mode, this field must be programmed to match the high 16 bits of the IMMR. Otherwise, this field is unused. Offset from endpoint parameter block base. Note that the items in boldface should be initialized by the user. 3 These parameters need not be accessed in normal operation but may be helpful for debugging. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-14 Freescale Semiconductor Universal Serial Bus Controller 27.5.5 Frame Number (FRAME_N) This entry is used for frame number updates both in function mode and in host mode. In function mode it is written by the USB controller; in host mode it is written by the application software and the USB controller. This entry is updated by the USB controller in function mode whenever a SOF (start of frame) token is received—including the SOF token it transmitted in host mode. The entry contains 11 bits that represent the frame number. An SOF interrupt is issued upon an update of this entry. 0 1 4 5 15 Field Reset R/W Addr 1 V 1 — FRAME NUMBER — R/W USB base + 0x10 Figure 27-7. Frame Number (FRAME_N) in Function Mode—Updated by USB Controller This bit is set if the SOF token was received error free. Table 27-6 describes FRAME_N fields. Table 27-6. FRAME_N Field Descriptions Bits 0 1–4 5–15 Name V — Description The valid bit is set if the SOF token is received without error. Reserved, should be cleared. FRAME The frame number is loaded with the value received in the SOF packet. Be sure the frame NUMBER number is cleared before beginning USB operation. In Host Mode, this entry must be updated by the application software between the transmission of one SOF (start of frame) token and the next. See Section 27.5.1.2, “Transaction-Level Interface” for details. The software should prepare the frame number and the CRC and place it in FRAME_N field. 0 1 4 5 15 Field Reset R/W Addr CRC5 FRAME NUMBER — R/W USB base + 0x10 Figure 27-8. Frame Number (FRAME_N) in Host Mode—Updated by Application Software MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-15 Universal Serial Bus Controller Table 27-6 describes FRAME_N fields. Table 27-7. FRAME_N Field Descriptions Bits 0–4 5–11 Name CRC5 FRAME NUMBER CRC5 calculated on frame number The frame number is inserted by the application software. Description 27.5.6 USB Function Code Registers (RFCR and TFCR) RFCR and TFCR control the value that the user would like to appear on the Address Type pins (AT1–AT3) when the associated SDMA channel accesses memory. 0 1 2 3 4 5 6 7 Field — GBL BO TC2 DTB — Figure 27-9. USB Function Code Registers (RFCR and TFCR) Table 27-8 describes RFCR and TFCR fields. Table 27-8. RFCR and TFCR Fields Bits 0–1 2 Name — GBL Reserved, should be cleared. Global 0 Snooping disabled 1 Snooping enabled Byte ordering. This bit field should be set by the user to select the required byte ordering for the data buffer. If this bit field is modified on the fly, it will take effect at the beginning of the next frame. 00 DEC (and Intel) convention is used for byte ordering—swapped operation. It is also called little-endian byte ordering. The transmission order of bytes within a buffer word is reversed as compared to the Freescale mode. This mode is supported only for 32-bit port size memory. 01 PowerPC little-endian byte ordering. As data is transmitted onto the serial line from the data buffer, the least significant byte of the buffer double-word contains data to be transmitted earlier than the most-significant byte of the same buffer double-word. 1X Freescale byte ordering—normal operation. It is also called big-endian byte ordering. As data is transmitted onto the serial line from the data buffer, the most-significant byte of the buffer word contains data to be transmitted earlier than the least-significant byte of the same buffer word. Transfer code. Contains the transfer code value of TC[2] used during this SDMA channel memory access.TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access Data bus Indicator 0 Use 60x bus for SDMA operation 1 Reserved Reserved, should be cleared. Description 3–4 BO 5 6 TC2 DTB 7 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-16 Freescale Semiconductor Universal Serial Bus Controller 27.5.7 USB Function Programming Model The following sections describe USB controller registers. 27.5.7.1 USB Mode Register (USMOD) USMOD, shown in Figure 27-10, controls the USB controller operation mode. 0 1 2 3 4 5 6 7 Field Reset R/W Addr LSS RESUME — SFTE 0000_0000 R/W 0x11B60 TEST HOST EN Figure 27-10. USB Mode Register (USMOD) Table 27-9 describes USMOD fields. Table 27-9. USMOD Fields Bits 0 Name LSS Description Low-speed signaling. Selects the signaling speed. The actual bit rate depends on the USB clock source. 0 Full-speed (12-Mbps) signaling. Normal operation. 1 Low-speed (1.5-Mbps) signaling. For a point-to-point connection with a low-speed device or for local loopback testing. Generate resume condition. When set, this bit generates a resume condition on the USB. This bit should be used if the function wants to exit the suspend state. Reserved, should be cleared. Start-of-Frame Timer Enable. Setting this bit enables the Start-of-Frame timer and automatic SOF transmission. See Section 27.5.7.8, “USB Start of Frame Timer (USSFT)" and Section 27.5.2, “SOF Transmission for USB Host Controller" for more information. 0 SOF timer is disabled 1 SOF timer is enabled Note: When SFTE is 1, the PC21 pin cannot be used as CP_INT since the CP interrupt is used internally for generating the SOF packet. USB controller test (loopback) mode 0 Test mode is disabled 1 Test mode is enabled Note: This bit may be set only when HOST is set (USB host mode) USB host mode 0 USB host is disabled 1 USB host is enabled Enable USB. When the EN bit is cleared, the USB is in a reset state 0 USB is disabled 1 USB is enabled Note: Setting this bit automatically disables SCC4. Note: Other bits of the USMOD should not be modified by the user while EN is set. 1 2–3 4 RESUME — SFTE 5 TEST 6 HOST 7 EN MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-17 Universal Serial Bus Controller 27.5.7.2 USB Slave Address Register (USADR) The USB address register is an 8-bit, memory-mapped register. It holds the address for this USB port when operating as function. 0 1 7 Field Reset R/W Addr — SADx 0000_0000 R/W 0x11B61 Figure 27-11. USB Slave Address Register (USADR) Table 27-10 describes USADR fields. Table 27-10. USADR Fields Bits 0 1–7 Name — SADx Reserved, should be cleared. Slave address 0–6. Holds the slave address for the USB port, when configured as function Description 27.5.7.3 USB Endpoint Registers (USEP1–USEP4) There are four memory-mapped endpoint configuration registers. 0 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr EPN — TM — MF RTE THS RHS 0000_0000_0000_0000 R/W 0x11B64 (USEP1); 0x11B66 (USEP2); 0x11B68 (USEP3); 0x11B6A (USEP4) Figure 27-12. USB Endpoint Registers (USEP1–USEP4) Table 27-11 describes the fields of USEP1–USEP4. The setting for USB host controller should be set only in USEP1, when USMOD[HOST] is set. Table 27-11. USEPx Field Descriptions Bits 0–3 4–5 6–7 Name EPN — TM USB Function Mode Endpoint number. For USB function controller defines the supported endpoint number. Reserved, should be cleared Transfer mode for USB function controller 00 Control 01 Interrupt 10 Bulk 11 Isochronous Reserved, should be cleared. USB Host Mode For USB host controller, should be cleared Reserved, should be cleared Transfer mode for USB host controller 00 Control /interrupt/bulk 11 Isochronous 8–9 — Reserved, should be cleared MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-18 Freescale Semiconductor Universal Serial Bus Controller Table 27-11. USEPx Field Descriptions (continued) Bits 10 Name MF USB Function Mode USB Host Mode Enable multi-frame. For USB function controller Enable multi-frame for USB host controller. Should allows loading of the next transmit packet into the be always set. FIFO before transmission completion of the previous packet. 0 Transmit FIFO may hold only one packet 1 Transmit FIFO may hold more than one packet Note: For USB function configuration: Should be cleared unless the endpoint is configured for ISO transfer mode. Transaction-level interface for USB host controller. Retransmit enable for USB function controller 0 Packet-level interface as described in 0 No retransmission Section 27.5.1.1, “Packet-Level Interface.” 1 Automatic frame retransmission is enabled. The 1 Transaction-level interface as described in frame will be retransmitted if transmit error Section 27.5.1.2, “Transaction-Level Interface.” occurred (time-out). Note: May be set only if the transmit packet is contained in a single buffer. If it is not, retransmission should be handled by software intervention. Note: Should be set to zero for endpoint which is configured for ISO transfer mode Transmit hand shake for USB function controller. Transmit hand shake for USB host controller 00 Normal handshake This field determines the response to an IN transaction. 00 Normal handshake 01 Ignore IN token 10 Force NACK handshake. Not allowed for control endpoint. 11 Force STALL handshake. On a control endpoint this value is used to generate a protocol stall; in this case THS will be cleared by the USB function controller when a SETUP token is received. Receive hand shake for USB function controller. Receive hand shake for USB host controller 00 Normal handshake This field determines the response to an OUT transaction. 00 Normal handshake 01 Ignore OUT token 10 Force NACK handshake and discard the data. This value may be used for flow control. Not allowed for control endpoint. 11 Force STALL handshake. On a control endpoint this value is used to generate a protocol stall; in this case RHS will be cleared by the USB function controller when a SETUP token is received. 11 RTE 12–13 THS 14–15 RHS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-19 Universal Serial Bus Controller 27.5.7.4 USB Command Register (USCOM) USCOM is used to start the USB transmit operation. 0 1 2 3 4 5 6 7 Field Reset R/W Addr STR FLUSH ISFT DSFT 0000_0000 R/W 0x11B62 — EP Figure 27-13. USB Command Register (USCOM) Table 27-12 describes USCOM fields. Table 27-12. USCOM Fields Bits 0 Name STR Description Start FIFO fill. Setting the STR bit to one causes the USB controller to start the filling the corresponding end point transmit FIFO with data. Transmission will begin once the IN token for this end-point is received. The STR bit is read always as a zero. Flush FIFO. Setting the FLUSH bit to one causes the USB controller to flush the corresponding end point transmit FIFO. Before flushing the FIFO, the user should issue the Stop_Tx command. After flushing the FIFO the user should issue the Restart_Tx command (Refer to Section 27.7, “USB CP Commands.”). FLUSH is always read as a zero. Increment Start-of-Frame Time. Setting the ISFT bit increments the start-of-frame time by one. This bit could be used to synchronize the USB frames to an external timing source. Decrement Start-of-Frame Time. Setting the DSFT bit decrements the start-of-frame time by one. This bit could be used to synchronize the USB frames to an external timing source. Reserved, should be cleared. End point. Selects one of the four supported end points. 1 FLUSH 2 3 4–5 6–7 ISFT DSFT — EP 27.5.7.5 USB Event Register (USBER) The USBER reports events recognized by the USB channel and generates interrupts. Upon recognition of an event, the USB sets its corresponding bit in the USBER. Interrupts generated by this register may be masked in the USB mask register. The USBER may be read at any time. A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit may be cleared at a time. All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr — SFT RESET IDLE TXE4 TXE3 TXE2 TXE1 SOF 0000_0000_0000_0000 R/W 0x11B70 BSY TXB RXB Figure 27-14. USB Event Register (USBER) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-20 Freescale Semiconductor Universal Serial Bus Controller Table 27-13 describes USBER fields. Table 27-13. USBER Fields Bit 0–4 5 6 7 8–11 12 13 14 Name — SFT RESET IDLE TXEx SOF BSY TXB Reserved, should be cleared. The start-of-frame timer (USSFT[SFT]) wrapped from 11,999 to 0. Reset condition detected. USB reset condition was detected asserted. IDLE status changed. A change in the status of the serial line was detected. The real time suspend status is reflected in the USB status register. Tx error. An error occurred during transmission for End Point x (packet not acknowledged or underrun). Start of frame. A start of frame packet was received. The packet is stored in the FRAME_N parameter ram entry. Busy condition. Received data has been discarded due to a lack of buffers. This bit is set after the first character is received for which there is no receive buffer available. Tx buffer. A buffer has been transmitted. This bit is set once the transmit data of the last character in the buffer was written to the transmit FIFO (if L=0 (last bit)) or after the last character was transmitted on the line (if L=1). Rx buffer. A buffer has been received. This bit is set after the last character has been written to the receive buffer and the Rx BD is closed. Description 15 RXB 27.5.7.6 USB Mask Register (USBMR) The USBMR is a 16-bit read/write register (0x11B74) that has the same bit formats as the USB event register. If a bit in the USBMR is one, the corresponding interrupt in the USBER is enabled. If the bit is zero, the corresponding interrupt in the USBER will be masked. This register is cleared at reset. 27.5.7.7 USB Status Register (USBS) The USB status register, described in Figure 27-15 and Table 27-14, is a read-only register that allows the user to monitor real-time status condition on the USB lines. 0 6 7 Field Reset R/W Addr — 0000_0000 R 0x11B77 IDLE Figure 27-15. USB Status Register (USBS) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-21 Universal Serial Bus Controller Table 27-14 describes USBS fields. Table 27-14. USBS Fields Bit 0–6 7 Name — IDLE Reserved Idle status. IDLE is set when an idle condition is detected on the USB lines, it is cleared when the bus is not idle. Description 27.5.7.8 USB Start of Frame Timer (USSFT) NOTE The USSFT described in this section is available only on .13 µm (HiP7) Revision A.0 and future devices. When enabled by USMOD[SFTE], the USSFT contains the current time within the frame with a resolution of one bit time. When the value of USSFT wraps from 11,999 to 0, a CP interrupt is asserted to trigger the transmission of a SOF packet, and USBER[SFT] is set The USSFT may be read at any time. 0 1 2 15 Field Reset R/W Addr SFT 0010_1110_1101_1000 R 0x11B78 Figure 27-16. USB Start of Frame Timer (USSFT) Table 27-13 describes USSFT fields. Table 27-15. USSFT Fields Bit 0–1 2–15 Name — SFT Reserved, should be cleared. Start of Frame Time. This field contains the number of bit times since the last SOF trigger. Note that the actual SOF transmission occurs slightly later. Description 27.6 USB Buffer Descriptor Ring The data associated with the USB channel is stored in buffers that are referenced by BDs organized in BD rings located in the dual-port RAM (refer to Figure 27-17). These rings have the same basic configuration as those used by the SCCs and SMCs. There are up to four separate transmit BD rings and four separate receive BD rings, one for each endpoint. The BD ring allows the user to define buffers for transmission and buffers for reception. Each BD ring forms a circular queue. The CP confirms reception and transmission or indicates error conditions using the BDs to inform the processor that the buffers have been serviced. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-22 Freescale Semiconductor Universal Serial Bus Controller The buffers may reside in either external or internal memory. DUAL- PORT RAM TX BUFFER DESCRIPTORS EXTERNAL MEMORY FRAME STATUS USB ENDPOINT 1 ENDPOINT 1 TX BD TABLE DATA LENGTH DATA POINTER TX DATA BUFFER TX BUFFER DESCRIPTORS ENDPOINT 4 TX BD TABLE FRAME STATUS DATA LENGTH DATA POINTER TX DATA BUFFER ENDPOINT 1 RX BD TABLE RX BUFFER DESCRIPTORS FRAME STATUS DATA LENGTH DATA POINTER ENDPOINT 4 RX BD TABLE RX DATA BUFFER EP1 RX BD TABLE POINTER EP1 TX BD TABLE POINTER RX BUFFER DESCRIPTORS FRAME STATUS DATA LENGTH EP4 RX BD TABLE POINTER EP4 TX BD TABLE POINTER RX DATA BUFFER DATA POINTER Figure 27-17. USB Memory Structure MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-23 Universal Serial Bus Controller 27.6.1 USB Receive Buffer Descriptor (Rx BD) for Host and Function The CP reports information about each buffer of received data using Rx BDs. The CP closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current buffer is full. Additionally, it closes the buffer on the following conditions: • End of packet detected • Overrun error occurred • Bit stuff violation detected As shown in Figure 27-18, the first word of the Rx BD contains status and control bits. These bits are prepared by the user before reception and are set by the CP after the buffer has been closed. The second word contains the data length—in bytes—that was received. The third and fourth words contain a pointer that always points to the beginning of the received data buffer. The RxBD is identical for both the host mode (when using the packet-level interface) and the function mode. There are no RxBDs in host mode when using the transaction-level interface. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET + 0 OFFSET + 2 OFFSET + 4 OFFSET + 6 E — W I L F — PID — NO AB CR OV — DATA LENGTH RX DATA BUFFER POINTER Figure 27-18. USB Receive Buffer Descriptor (Rx BD)1,2 1 2 Entries in boldface must be initialized by the user. All fields should be written by the CPU core before enabling the USB. Table 27-16 describes USB receive buffer descriptor fields. Table 27-16. USB Rx BD Fields Offset 0x00 Bit 0 Name E Description Empty 0 The data buffer associated with this Rx BD has been filled with received data, or data reception has been aborted due to an error condition. The CPU core is free to examine or write to any fields of this Rx BD. The CP will not use this BD again while the E-bit remains zero. 1 The data buffer associated with this BD is empty, or reception is currently in progress. This Rx BD and its associated receive buffer are owned by the CP. Once the E-bit is set, the CPU core should not write any fields of this Rx BD. Reserved, should be cleared Wrap (Final BD in table) 0 This is not the last BD in the Rx BD table. 1 This is the last BD in the Rx BD table. After this buffer has been used, the CP will receive incoming data into the first BD in the table (the BD pointed to by RBASE). The number of Rx BDs in this table is programmable and is determined only by the W-bit and the overall space constraints of the dual-port RAM. 1 2 — W MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-24 Freescale Semiconductor Universal Serial Bus Controller Table 27-16. USB Rx BD Fields (continued) Offset Bit 3 Name I Description Interrupt 0 No interrupt is generated after this buffer has been filled. 1 The RXB bit in the USB event register will be set when this buffer has been completely filled by the CP, indicating the need for the CPU core to process the buffer. The RXB bit can cause an interrupt if it is enabled. Last. This bit is set by the USB controller when the buffer is closed due to detection of end-of-packet condition on the bus, or as a result of error. Written by the USB controller after the received data has been placed into the associated data buffer. 0 Buffer does not contain the last byte of the message. 1 Buffer contains the last byte of the message. First. This bit is set by the USB controller when the buffer contains the first byte of a packet. Written by the USB controller after the received data has been placed into the associated data buffer. 0 Buffer does not contain the first byte of the message 1 Buffer contains the first byte of the message Reserved, should be cleared Packet ID. This bit field is set by the USB controller to indicate the type of the packet. This bit is valid only if the USB RXBD[F] is set. Written by the USB controller after the received data has been placed into the associated data buffer. 00 Buffer contains DATA0 packet 01 Buffer contains DATA1 packet 10 Buffer contains SETUP packet. This option can never be set on host RxBD Reserved, should be cleared Rx non-octet aligned packet. A packet that contained a number of bits not exactly divisible by eight was received. Written by the USB controller after the received data has been placed into the associated data buffer. Frame aborted. Bit stuff error occurred during reception. Written by the USB controller after the received data has been placed into the associated data buffer. CRC error. This frame contains a CRC error. The received CRC bytes are always written to the receive buffer. Written by the USB controller after the received data has been placed into the associated data buffer. Overrun. A receiver overrun occurred during reception. Written by the USB controller after the received data has been placed into the associated data buffer. Reserved, should be cleared 4 L 5 F 6–7 8–9 — PID 10 11 — NO 12 13 AB CR 14 15 0x02 0–15 OV — Data length Data length is the number of octets that the CP has written into this BD’s data buffer. It is written once by the CP as the BD is closed. Note: The actual amount of memory allocated for this buffer should be greater than or equal to the contents of the MRBLR. Rx data buffer pointer The receive buffer pointer, which always points to the first location of the associated data buffer, must be divisible by 4. The buffer may reside in either internal or external memory 0x04 0–31 Data length represents the number of octets that the CP has written into this BD’s buffer. It is written once by the CP as the BD is closed. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-25 Universal Serial Bus Controller The receive buffer pointer always points to the first location of the associated buffer. The pointer must be divisible by 4. The buffer may reside in either internal or external memory. 27.6.2 USB Transmit Buffer Descriptor (Tx BD) for Function Data that the USB function wishes to transmit to the host is arranged in buffers referenced by the Tx BD ring. The first word of the Tx BD contains the status and control bits. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET + 0 OFFSET + 2 OFFSET + 4 OFFSET + 6 R — W I L TC CNF PID — TO UN — DATA LENGTH TX DATA BUFFER POINTER Figure 27-19. USB Transmit Buffer Descriptor (Tx BD)1,2 1 2 Entries in boldface must be initialized by the user. All fields should be prepared by the user before transmission. Table 27-17 describes USB TxBD fields. Table 27-17. USB Function Tx BD Fields Offset 0x00 Bit 0 Name R Description Ready 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. No fields of this BD may be written by the user once this bit is set. Reserved, should be cleared Wrap (Final BD in table) 0 This is not the last BD in the Tx BD table. 1 This is the last BD in the Tx BD table. After this buffer has been used, the CP will send data using the first BD in the table (the BD pointed to by TBASEx). The number of Tx BDs in this table is programmable, and is determined only by the Tx BD[W] and the overall space constraints of the dual-port RAM. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1The TXB or TXE bit in the event register is set when this buffer is serviced. TXB and TXE can cause interrupts if they are enabled. Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message Transmit CRC. Valid only when the L bit is set; otherwise it is ignored. Prepare TC before sending data. 0 Transmit end-of-packet after the last data byte. This setting can be used for testing purposes to send a bad CRC after the data. 1 Transmit the CRC sequence after the last data byte. 1 2 — W 3 I 4 L 5 TC MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-26 Freescale Semiconductor Universal Serial Bus Controller Table 27-17. USB Function Tx BD Fields (continued) Offset Bit 6 Name CNF Description Transmit confirmation. Valid only when the L bit is set; otherwise it is ignored. Applies to multi-frame enabled endpoints (USEPn[MF] = 1); refer to Section 27.5.7.3, “USB Endpoint Registers (USEP1–USEP4).” 0 Continue to load the transmit FIFO with the next packet. Several packets may be loaded to the FIFO. 1 Last packet that is loaded to FIFO. No more packets will be loaded to fifo after a packet marked CNF, till it transmitted. Reserved, should be cleared PID Packet ID. This bit field is valid for the first BD of a packet; otherwise it is ignored. 0X Do not append PID to the data. 10 Transmit DATA0 PID before sending the data. 11 Transmit DATA1 PID before sending the data. Reserved, should be cleared Time out. Indicates that the host failed to acknowledge the packet. Underrun. Indicates that the USB encountered a transmitter underrun condition while sending the buffer. Reserved, should be cleared 7 8–9 10–12 13 14 15 0x02 0–15 — TO UN — Data length The data length is the number of octets that the CP should transmit from this BD’s data buffer. It is never modified by the CP. This value should normally be greater than zero. Tx data buffer pointer The transmit buffer pointer, which always points to the first location of the associated data buffer, may be even or odd.The buffer may reside in either internal or external memory. 0x04 0–31 Data length (the second half word of a TxBD) is the number of octets the CP should send from this BD’s data buffer. It is never modified by the CP. Tx buffer pointer (the third and fourth half words of a TxBD) always points to the first location of the buffer in internal or external memory. The pointer may be even or odd. 27.6.3 USB Transmit Buffer Descriptor (Tx BD) for Host The Tx BD described in this section is used when the packet-level interface is active. See Section 27.5.1.1, “Packet-Level Interface,” for more information. Data to be transmitted with the USB to the CP by is arranged in buffers referenced by the Tx BD ring. The first word of the Tx BD contains status and control bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-27 Universal Serial Bus Controller 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET + 0 OFFSET + 2 OFFSET + 4 OFFSET + 6 R — W I L TC CNF LSP PID — NAK STAL TO UN — DATA LENGTH TX DATA BUFFER POINTER Figure 27-20. USB Transmit Buffer Descriptor (Tx BD)1,2 1 2 Entries in boldface must be initialized by the user. All fields should be prepared by the user before transmission. Table 27-17 describes USB TxBD fields. Table 27-18. USB Host Tx BD Fields Offset 0x00 Bit 0 Name R Description Ready 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. No fields of this BD may be written by the user once this bit is set. Reserved, should be cleared Wrap (Final BD in Table) 0 This is not the last BD in the Tx BD table. 1 This is the last BD in the Tx BD table. After this buffer has been used, the CP will send data using the first BD in the table (the BD pointed to by TBASEx). The number of Tx BDs in this table is programmable, and is determined only by the Tx BD[W] and the overall space constraints of the dual-port RAM. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt if it is enabled. Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message Transmit CRC. Valid only when the L bit is set; otherwise it is ignored. Prepare TC before sending data. 0 Transmit end-of-packet after the last data byte. This setting can be used for testing purposes to send a bad CRC after the data. 1 Transmit the CRC sequence after the last data byte. Transmit confirmation. Valid only when the L bit is set; otherwise it is ignored. Applies to multi-frame enabled endpoints (USEPn[MF] = 1); see Section 27.5.7.3, “USB Endpoint Registers (USEP1–USEP4).” 0 Continue to load the transmit FIFO with the next packet. No handshake or response is expected from the function for this packet. 1 Wait for handshake or response from the function before starting the next packet, or this is the last packet. Do not clear CNF for a token preceding a data packet unless the data packet’s BD is ready. 1 2 — W 3 I 4 L 5 TC 6 CNF MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-28 Freescale Semiconductor Universal Serial Bus Controller Table 27-18. USB Host Tx BD Fields (continued) Offset Bit 7 Name LSP Description Low-speed transaction. Use for tokens only. 0 The following transaction is with the host or a full-speed device. 1 The following transaction is with a low-speed device. Required only for tokens. Note that LSP should always be cleared in slave mode. Packet ID. This bit field is valid for the first BD of a packet; otherwise it is ignored. 0X Do not append PID to the data. 10 Transmit DATA0 PID before sending the data. 11 Transmit DATA1 PID before sending the data. Reserved, should be cleared NAK received. Indicates that the endpoint has responded with a NAK handshake. The packet was received error-free; however, the endpoint could not accept it. STALL received. Indicates that the endpoint has responded with a STALL handshake. The endpoint needs attention through the control pipe. Time out. Indicates that the endpoint failed to acknowledge the packet. Underrun. Indicates that the USB encountered a transmitter underrun condition while sending the buffer. Reserved, should be cleared 8–9 PID 10 11 12 13 14 15 0x02 0–15 — NAK1 STAL1 TO1 UN1 — Data length The data length is the number of octets that the CP should transmit from this BD’s data buffer. It is never modified by the CP. This value should normally be greater than zero. Tx data buffer pointer The transmit buffer pointer, which always points to the first location of the associated data buffer, may be even or odd.The buffer may reside in either internal or external memory. 0x04 0–31 1 Written by the USB controller after it finishes sending the associated data buffer. Data length (the second half word of a TxBD) is the number of octets the CP should send from this BD’s data buffer. It is never modified by the CP. Tx buffer pointer (the third and fourth half words of a TxBD) always points to the first location of the buffer in internal or external memory. The pointer may be even or odd. 27.6.4 USB Transaction Buffer Descriptor (TrBD) for Host The TrBD described in this section is used when the transaction-level interface is active. See Section 27.5.1.2, “Transaction-Level Interface” for more information. Data to be transmitted with the USB to the CP by is arranged in buffers referenced by the TrBD ring. The first word of the TrBD contains status and control bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-29 Universal Serial Bus Controller 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET + 0x0 OFFSET + 0x2 OFFSET + 0x4 OFFSET + 0x6 OFFSET + 0x8 OFFSET + 0xA 1 2 R — W I L TC CNF LSP PID RXER NAK STAL TO UN BOV DATA LENGTH DATA BUFFER POINTER TOK — ISO — ENDP Reserved ADDR Figure 27-21. USB Transaction Buffer Descriptor (TrBD)1,2 Entries in boldface must be initialized by the user. All fields should be prepared by the user before transmission. Table 27-17 describes USB TrBD fields. Table 27-19. USB Host TrBD Fields Offset 0x00 Bit 0 Name R Description Ready 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. No fields of this BD may be written by the user once this bit is set. Reserved, should be cleared. Wrap (Final BD in Table) 0 This is not the last BD in the TrBD table. 1 This is the last BD in the TrBD table. After this buffer has been used, the CP will send data using the first BD in the table (the BD pointed to by TBASE). The number of TrBDs in this table is programmable, and is determined only by the TrBD[W] and the overall space constraints of the dual-port RAM. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt if it is enabled. Last This bit should always be 1 since each TrBD represents an entire transaction. Transmit CRC. Append CRC to transmitted data packet. 0 Transmit end-of-packet after the last data byte. This setting can be used for testing purposes to send a bad CRC after the data. 1 Transmit the CRC sequence after the last data byte. Transmit confirmation. This bit should always be set to 1 to obtain confirmation for each transaction. Low-speed transaction. 0 This transaction is with the host or a full-speed device. 1 This transaction is with a low-speed device. Transmit a PRE packet before the token. 1 2 — W 3 I 4 5 L TC 6 7 CNF LSP MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-30 Freescale Semiconductor Universal Serial Bus Controller Table 27-19. USB Host TrBD Fields (continued) Offset Bit 8–9 Name PID Packet ID. For OUT/SETUP transactions, this field is prepared by the user with the following values: 0X Do not append PID to the data packet. 10 Transmit DATA0 PID before sending the data packet. 11 Transmit DATA1 PID before sending the data packet. For IN transactions, this field is provided by the USB host controller with the following values: 00 Buffer contains DATA0 packet. 01 Buffer contains DATA1 packet. 10 RXER1 Receive Error. This bit indicates that an error was detected while receiving the data packet of an IN transaction. If RXER is 1, bits 11-15 have a different meaning as explained below. RXER=0: NAK received. Indicates that the endpoint has responded with a NAK handshake (OUT transaction). The packet was received error-free; however, the endpoint could not accept it. RXER=1: Rx non-octet aligned packet. A packet that contained a number of bits not exactly divisible by eight was received. Written by the USB controller after the received data has been placed into the associated data buffer. RXER=0: STALL received. Indicates that the endpoint has responded with a STALL handshake (OUT transaction). The endpoint needs attention through the control pipe. RXER=1: Frame aborted. Bit stuff error occurred during reception. Written by the USB controller after the received data has been placed into the associated data buffer. RXER=0: Time out. Indicates that the endpoint failed to acknowledge the token (IN transaction) or the data packet (OUT/SETUP transaction). RXER=1: CRC error. This frame contains a CRC error. The received CRC bytes are always written to the receive buffer. Written by the USB controller after the received data has been placed into the associated data buffer. RXER=0: Underrun. Indicates that the USB encountered a transmit FIFO underrun condition while sending the data packet (OUT/SETUP transaction). RXER=1: Overrun. An internal receive FIFO overrun occurred during reception. Written by the USB controller after the received data has been placed into the associated data buffer. Buffer Overflow. IN transactions only. Indicates that the number of received bytes is larger than the buffer size as provided in the Data Length field. For OUT/SETUP transactions, the user prepares this field with the number of bytes to be sent from the data buffer. It will not be modified by the CP. For IN transactions, the user prepares this field with the size of the data buffer, which must be divisible by 4. The CP will return the actual number of bytes written to the data buffer. If the number of received bytes, including the 2-byte CRC, is larger than the data buffer, the BOV bit will be set by the CP. Description 11 NAK/NO 1 12 STAL/AB 1 13 TO/CR1 14 UN/OV1 15 0x02 0–15 BOV1 Data Length MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-31 Universal Serial Bus Controller Table 27-19. USB Host TrBD Fields (continued) Offset 0x04 Bit 0–31 Name Description Data Buffer Pointer The data buffer pointer. The buffer may reside in either internal or external memory. For OUT/SETUP transactions, this points to the buffer containing the data packet to transmit. It may have any alignment. For IN transactions, this points to the buffer into which the data packet should be received, The pointer must be divisible by 4. TOK Token Type This field determines the type of token to be transmitted and the type of transaction. 00 SETUP 01 OUT 10 IN 11 Reserved Reserved, should be cleared. Isochronous This bit indicates that the transaction is isochronous, so no handshake is required. 0 Bulk/Control/Interrupt. The handshake packet is automatically expected or generated by the USB Host Controller. 1 Isochronous. No handshake packets are expected or generated. This bit actually controls the value that is written to USEP1[TM] before processing this transaction. Reserved, should be cleared. Endpoint This field indicates the endpoint number to be included in the token. Address This field indicates the device address to be included in the token. Reserved, should be cleared. 0x08 0–1 2 3 — ISO 5 5–8 9–15 0x0A 1 — ENDP ADDR — 0–15 Written by the USB controller after it finishes sending or receiving the associated data buffer. 27.7 USB CP Commands The following transmit commands are issued to the CP command register (CPCR). Refer to Section 14.4.1, “CP Command Register (CPCR).” 27.7.1 STOP Tx Command This command disables the transmission of data on the selected endpoint. After issuing the command the corresponding Endpoint FIFO should be flushed. No further transmissions will take place until the Restart Tx Command is issued. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-32 Freescale Semiconductor Universal Serial Bus Controller 27.7.2 RESTART Tx Command This command enables the transmission of data from the corresponding endpoint on the USB. This command is expected by the USB controller after a STOP Tx Command, or after transmission error (underrun or time-out). 27.8 USB Controller Errors The USB controller reports frame reception and transmission error conditions using the BDs and the USB event register (USBER). Transmission errors are shown in Table 27-20. Errors that exist exclusively in host mode or function mode are marked as such. Table 27-20. USB Controller Transmission Errors Error Transmit underrun Transmit timeout Description If an underrun occurs, the transmitter forces a bit stuffing violation, terminates buffer transmission, closes the buffer, sets TxBD[UN] and the corresponding USBER[TXEn]. The endpoint resumes transmission after the RESTART TX ENDPOINT command is received. Transmit packet not acknowledged. If a timeout occurs, the controller tries to retransmit if USEPn[RTE] = 1. If RTE = 0 or the second attempt fails, the controller closes the buffer and sets TxBD[TO] and USBER[TXEn]. The endpoint resumes transmission after receiving a RESTART TX ENDPOINT command. For USB function mode only. This error occurs if an IN token is received, but the corresponding endpoint’s transmit FIFO is empty, or if the target endpoint is configured to NAK or STALL. The controller sets USBER[TXEn]. For USB host mode only. If this error occurs, the channel closes the buffer, sets the corresponding status bit in the Tx BD (NAK or STAL), and sets the TXE bit in the USB event register. When using the packet-level interface, the host will resume transmission after reception of the RESTART TRANSMIT command. Tx data not ready Reception of NAK or STALL hand shake Table 27-21 describes the USB controller reception errors. Table 27-21. USB Controller Reception Errors Error Overrun Error Description If the 16-byte receive FIFO overruns, the previously received byte is overwritten. The controller closes the buffer and sets both RxBD[OV] and USBER[RXB]. For USB function mode the NAK handshake is sent after the end of the received packet if the packet was received error-free. A frame was received and discarded due to lack of buffers. The controller sets USBER[BSY]. If this error occurs, the controller writes the received data to the buffer, closes the buffer and sets both RxBD[NO] and USBER[RXB]. When a CRC error occurs, the controller closes the buffer, and sets both RxBD[CR] and USBER[RXB]. In isochronous mode (USEPn[TM] = 0b11), the USB controller reports a CRC error; however, there are no handshake packets (ACK) and the transfer continues normally when an error occurs. For USB host mode packet-level interface only. If the received data packet is larger than the allocated buffer, the remaining data is discarded, and TrBD[BOV] is set. The TXE1 interrupt bit is set. Busy Error Non Octet-Aligned Packet CRC Error Buffer Overflow MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-33 Universal Serial Bus Controller 27.9 USB Function Controller Initialization Example The following is an example initialization sequence for the USB controller operating in function mode. It can be used to set up two function endpoints to fill transmit FIFOs so that data is ready for transmission when an IN token is received from the USB. The tokens can be generated using a USB traffic generator. 1. Program CMXSCR to provide a 48 MHz clock to the USB controller. 2. Program the Port Registers to select USBRXD, USBRXP, USBRXN, USBTXP, USBTXN, and USBOE. 3. Clear FRAME_N. 4. Write (DPRAM+0x500) to EP1PTR, and (DPRAM+0x520) to EP2PTR to set up the endpoint pointers. 5. Write 0xBC80_0004 to DPRAM+0x20 to set up the TxBD[Status and Control, Data Length] fields of endpoint 1. 6. Write DPRAM+0x200 to DPRAM+0x24 to set up the TxBD[Buffer Pointer] field of endpoint 1. 7. Write 0xBCC0_0004 to DPRAM+0x28 to set up the TxBD[Status and Control, Data Length] fields of endpoint 2. 8. Write DPRAM+0x210 to DPRAM+0x2C to set up the TxBD[Buffer Pointer] field of endpoint 2. 9. Write 0xCAFE_CAFE to DPRAM+0x200 to set up the endpoint 1 Tx data pattern. 10. Write 0xFACE_FACE to DPRAM+0x210 to set up the endpoint 2 Tx data pattern. 11. Write 0x0000_0020 to DPRAM+0x500 to set up the RBASE and TBASE fields of the endpoint 1 parameter RAM. 12. Write 0x1818_0100 to DPRAM+0x504 to set up the RFCR, TFCR, and MRBLR fields of the endpoint 1 parameter RAM. 13. Write 0x0000_0020 to DPRAM+0x508 to set up the RBPTR and TBPTR fields of the endpoint 1 parameter RAM. 14. Clear the TSTATE field of the endpoint 1 parameter RAM. 15. Write 0x0008_0028 to DPRAM+0x520 to set up the RBASE and TBASE fields of the endpoint 2 parameter RAM. 16. Write 0x1818_0100 to DPRAM+0x524 to set up the RFCR, TFCR, and MRBLR fields of the endpoint 2 parameter RAM. 17. Write 0x0008_0028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of the endpoint 2 parameter RAM. 18. Clear the TSTATE field of the endpoint 2 parameter RAM. 19. Write 0x0000 to USEP1: Endpoint Number 0, control transfer, one packet only, and normal handshake. 20. Write 0x7200 to USEP2: Endpoint Number 7, bulk transfer, one packet only, and normal handshake. 21. Write 0x00 to the USMOD for full-speed 12 Mbps function endpoint mode and disable the USB. 22. Write 0x05 to the USAD for slave address 5. 23. Set USMOD[EN] to enable the USB controller. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-34 Freescale Semiconductor Universal Serial Bus Controller 24. Write 0x80 to USCOM to start filling the Tx FIFO with endpoint 1 data ready for transmission when an IN token is received. 25. Write 0x81 to USCOM to start filling the Tx FIFO with endpoint 2 data ready for transmission when an IN token is received. 26. Generate an IN token to address 5, endpoint number 0, control. 27. Generate an IN token to address 5, endpoint number 7, bulk. 27.10 Programming the USB Host Controller (Packet-Level) The MPC8280 implementation of a USB host uses the endpoint represented by USEP1 to control the host transmission and reception. The other endpoints are typically not used, except for testing purposes (loop-back). Programming the USB controller to act as host is similar to configuring an endpoint for function operation. A general outline of how to program the host controller follows. (A more detailed example can be found in Section 27.10.1, “USB Host Controller Initialization Example.”) • Set the host bit in the mode register (USBMOD[HOST] = 1) to configure the controller as a host. • Set the multi-frame bit in the endpoint configuration register (USEP1[MF] = 1) to allow SETUP/OUT tokens and DATA0/DATA1 packets to be sent back-to-back. • Prepare tokens in separate BDs. • Using software, append the CRC5 as part of the transmitted data because the CPM does not support automatic CRC5 generation. • Clock the USB host controller as a high speed function (48-MHz reference clock). • For low-speed transactions with an external hub, set TxBD[LSP] in the token’s BD. This causes the USB host controller to generate a preamble (PRE token) at full speed before changing the transmit rate to low speed and sending the data packet. After completion of the transaction, the host returns to full-speed operation. Note that LSP should be set only for token BDs. 27.10.1 USB Host Controller Initialization Example The following is a local loopback example initialization sequence for the USB controller operating as a host. It can be used to set up the host endpoint and one function endpoint to demonstrate an IN token transaction. 1. Program CMXSCR to provide a 48 MHz clock to the USB controller. 2. Program the Port Registers to select USBRXD, USBRXP, USBRXN, USBTXP, USBTXN, and USBOE. 3. Write (DPRAM+0x500) to EP1PTR, (DPRAM+0x520) to EP2PTR to set up the endpoint pointers. 4. Write 0x0000_0020 to DPRAM+0x500 to set up the RBASE and TBASE fields of the host endpoint parameter RAM. 5. Write 0x1818_0100 to DPRAM+0x504 to set up the RFCR, TFCR, and MRBLR fields of the host endpoint parameter RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-35 Universal Serial Bus Controller 6. Write 0x0000_0020 to DPRAM+0x508 to set up the RBPTR and TBPTR fields of the host endpoint parameter RAM. 7. Clear the TSTATE field of the host endpoint parameter RAM. 8. Write 0x0008_0028 to DPRAM+0x520 to set up the RBASE and TBASE fields of the endpoint 2 parameter RAM. 9. Write 0x1818_0100 to DPRAM+0x524 to set up the RFCR, TFCR, and MRBLR fields of the endpoint 2 parameter RAM. 10. Write 0x0008_0028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of the endpoint 2 parameter RAM. 11. Clear the TSTATE field of the endpoint 2 parameter RAM. 12. Write 0xB000_0000 to DPRAM+0x00 to set up the RxBD[Status and Control, Data Length] fields of the host endpoint. 13. Write DPRAM+0x100 to DPRAM+0x04 to set up the RxBD[Buffer Pointer] field of the host endpoint. 14. Write 0xB800_0003 to DPRAM+0x20 to set up the TxBD[Status and Control, Data Length] fields of the host endpoint. 15. Write DPRAM+0x200 to DPRAM+0x24 to set up the TxBD[Buffer Pointer] field of the host endpoint. 16. Write 0xBC80_0003 to DPRAM+0x28 to set up the TxBD[Status and Control, Data Length] fields of the function endpoint. 17. Write DPRAM+0x210 to DPRAM+0x2C to set up the TxBD[Buffer Pointer] field of the function endpoint. 18. Write 0x698560 to DPRAM+0x200 to set up the host endpoint Tx data pattern. This pattern consists of the IN token and the CRC5. 19. Write 0xABCD_1234 to DPRAM+0x210 to set up the function endpoint Tx data pattern. 20. Write 0x0020 to USEP1 for the host: non-isochronous transfer, multi-packet, packet-level interface. 21. Write 0x1100 to USEP2 for the function: interrupt transfer, one packet only. 22. Write 0x06 to USMOD for full-speed 12 Mbps signaling, local loopback configuration (test and host modes set), and disable the USB. 23. Write 0x05 to the USAD for slave address 5. 24. Set USMOD[EN] to enable the USB controller. 25. Write 0x81 to the USCOM to start filling the Tx FIFO with endpoint 2 data to be ready for transmission when an IN token is received. 26. Write 0x80 to the USCOM to start transmitting the IN token. The expected results are as follows: • TxBD[Status and Control] of the host endpoint should contain 0x3800. • TxBD[Data Length] of the host endpoint should contain 0x0003. • TxBD[Status and Control] of endpoint 2 should contain 0x3C80. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-36 Freescale Semiconductor Universal Serial Bus Controller • • • TxBD[Data Length] of endpoint 2 should contain 0x0003. RxBD[Status and Control] of the host endpoint should contain 0x3C00. RxBD[Data Length] of the host endpoint should contain 0x0005. • The receive buffer of the host endpoint should contain 0xABCD_122B, 0x42xx_xxxx. 27.11 Programming the USB Host Controller (Transaction-Level) The MPC8280 implementation of a USB host uses the endpoint represented by USEP1 to control the host transmission and reception. The other endpoints are typically not used, except for testing purposes (loop-back). Programming the USB controller to act as host is similar to configuring an endpoint for function operation. A general outline of how to program the host controller follows. (A more detailed example can be found in Section 27.11.1, “USB Host Controller Initialization Example.”) • Set the host bit in the mode register (USBMOD[HOST] = 1) to configure the controller as a host. • Set the multi-frame bit in the endpoint configuration register (USEP1[MF] = 1) to allow SETUP/OUT tokens and DATA0/DATA1 packets to be sent back-to-back. • Set USEP1[RTE] to enable the transaction-level interface. • Clock the USB host controller as a high speed function (48-MHz reference clock). • For low-speed transactions with an external hub, set TrBD[LSP]. This causes the USB host controller to generate a preamble (PRE token) at full speed before changing the transmit rate to low speed and sending the token. After completion of the transaction, the host returns to full-speed operation. 27.11.1 USB Host Controller Initialization Example The following is a local loopback example initialization sequence for the USB controller operating as a host. It can be used to set up the host endpoint and one function endpoint to demonstrate an IN token transaction. 1. Program CMXSCR to provide a 48 MHz clock to the USB controller. 2. Program the Port Registers to select USBRXD, USBRXP, USBRXN, USBTXP, USBTXN, and USBOE. 3. Write (DPRAM+0x500) to EP1PTR, (DPRAM+0x520) to EP2PTR to set up the endpoint pointers. 4. Write 0x0020 to DPRAM+0x502 to set up the TBASE field of the host endpoint parameter RAM. 5. Write 0x1818 to DPRAM+0x504 to set up the RFCR and TFCR fields of the host endpoint parameter RAM. 6. Write 0x0020 to DPRAM+0x50a to set up the TBPTR field of the host endpoint parameter RAM. 7. Clear the TSTATE field of the host endpoint parameter RAM. 8. Initialize the HIMMR field of the host endpoint parameter RAM. 9. Write 0x0008_0028 to DPRAM+0x520 to set up the RBASE and TBASE fields of the endpoint 2 parameter RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 27-37 Universal Serial Bus Controller 10. Write 0x1818_0100 to DPRAM+0x524 to set up the RFCR, TFCR, and MRBLR fields of the endpoint 2 parameter RAM. 11. Write 0x0008_0028 to DPRAM+0x528 to set up the RBPTR and TBPTR fields of the endpoint 2 parameter RAM. 12. Clear the TSTATE field of the endpoint 2 parameter RAM. 13. Write 0xB800_0040 to DPRAM+0x20 to set up the TrBD[Status and Control, Data Length] fields of the host endpoint. 14. Write DPRAM+0x100 to DPRAM+0x24 to set up the TrBD[Buffer Pointer] field of the host endpoint. 15. Write 0x8085 to DPRAM+0x28 to set up the TrBD token fields of the host endpoint. 16. Write 0xBC80_0003 to DPRAM+0x28 to set up the TxBD[Status and Control, Data Length] fields of the function endpoint. 17. Write DPRAM+0x210 to DPRAM+0x2C to set up the TxBD[Buffer Pointer] field of the function endpoint. 18. Write 0xABCD_1234 to DPRAM+0x210 to set up the function endpoint Tx data pattern. 19. Write 0x0030 to USEP1 for the host: non-isochronous transfer, multi-packet, transaction-level interface. 20. Write 0x1100 to USEP2 for the function: interrupt transfer, one packet only. 21. Write 0x06 to USMOD for full-speed 12 Mbps signaling, local loopback configuration (test and host modes set), and disable the USB. 22. Write 0x05 to the USAD for slave address 5. 23. Set USMOD[EN] to enable the USB controller. 24. Write 0x81 to the USCOM to start filling the Tx FIFO with endpoint 2 data to be ready for transmission when an IN token is received. 25. Write 0x80 to the USCOM to start transmitting the IN token. The expected results are as follows: • TrBD[Status and Control] of the host endpoint should contain 0x3800. • TrBD[Data Length] of the host endpoint should contain 0x0005. • TxBD[Status and Control] of endpoint 2 should contain 0x3C80. • TxBD[Data Length] of endpoint 2 should contain 0x0003. • The receive buffer of the host endpoint should contain 0xABCD_122B, 0x42xx_xxxx. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 27-38 Freescale Semiconductor Chapter 28 Serial Management Controllers (SMCs) The two serial management controllers (SMCs) are full-duplex ports that can be configured independently to support one of three protocols or modes—UART, transparent, or general-circuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in an application, which allows the SCCs to be free for other purposes. The SMC in UART mode is not as complex as that of the SCC in UART mode. The SMC clock can be derived from one of the internal baud rate generators or from an external clock signal. However, the clock should be a 16× clock. In totally transparent mode, the SMC can be connected to a TDM channel (such as a T1 line) or directly to its own set of signals. The receive and transmit clocks are derived from the TDM channel, the internal baud rate generators, or from an external 1× clock. The transparent protocol allows the transmitter and receiver to use the external synchronization signal. The SMC in transparent mode is not as complex as that of the SCC in transparent mode. Each SMC supports the C/I and monitor channels of the GCI bus, for which the SMC connects to a time-division multiplex (TDM) channel in a serial interface (SIx). SMCs support loopback and echo modes for testing. The SMC receiver and transmitter are double-buffered, corresponding to an effective FIFO size (latency) of two characters. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes GCI interface configuration. Figure 28-1 shows the SMC block diagram. 60x Bus Control Registers Peripheral Bus Control Logic SYNC CLK Rx Data Register Tx Data Register RXD Shifter Shifter TXD Figure 28-1. SMC Block Diagram MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-1 Serial Management Controllers (SMCs) The receive data source can be L1RXD if the SMC is connected to a TDM channel of an SIx, or SMRXD if it is connected to the NMSI. The transmit data source can be L1TXD if the SMC is connected to a TDM or SMTXD if it is connected to the NMSI. If the SMC is connected to a TDM, the SMC receive and transmit clocks can be independent from each other, as defined in Chapter 15, “Serial Interface with Time-Slot Assigner.” However, if the SMC is connected to the NMSI, receive and transmit clocks must be connected to a single clock source (SMCLK), an internal signal name for a clock generated from the bank of clocks. SMCLK originates from an external signal or one of the four internal baud rate generators. An SMC connected to a TDM derives a synchronization pulse from the TSA. An SMC connected to the NMSI using transparent protocol can use SMSYN for synchronization to determine when to start a transfer. SMSYN is not used when the SMC is in UART mode. 28.1 Features The following is a list of the SMC’s main features: • Each SMC can implement the UART protocol on its own signals • Each SMC can implement a totally transparent protocol on a multiplexed or nonmultiplexed line. This mode can also be used for a fast connection between MPC8280s. • Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications • Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0 and 1 • Full-duplex operation • Local loopback and echo capability for testing 28.2 Common SMC Settings and Configurations The following sections describe settings and configurations that are common to the SMCs. 28.2.1 SMC Mode Registers (SMCMR1/SMCMR2) The SMC mode registers (SMCMR1 and SMCMR2), shown in Figure 28-2, selects the SMC mode as well as mode-specific parameters. The functions of SMCMR[8–15] are the same for each protocol. Bits 0–7 vary according to protocol selected by the SM bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-2 Freescale Semiconductor Serial Management Controllers (SMCs) Bit Field: UART Transparent GCI Reset R/W Addr 0 — 1 2 3 4 5 SL — ME 6 PEN BS — 7 PM REVD C# 8 — 9 10 SM 11 12 DM 13 14 15 CLEN TEN REN 0000_0000_0000_0000 R/W 0x11A82 (SMCMR1), 0x11A92 (SMCMR2) Figure 28-2. SMC Mode Registers (SMCMR1/SMCMR2) Table 28-1 describes SMCMR fields. Table 28-1. SMCMR1/SMCMR2 Field Descriptions Bits 0 1–4 Name — CLEN Reserved, should be cleared Character length (UART). Number of bits in the character minus one. The total is the sum of 1 (start bit always present) + number of data bits (5–14) + number of parity bits (0 or 1) + number of stop bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the character is 1 + 8 + 0 + 1 = 10. So, CLEN should be programmed to 9. Characters range from 5–14 bits. If the data bit length is less than 8, the msbs of each byte in memory are not used on transmit and are written with zeros on receive. If the length is more than 8, the msbs of each 16-bit word are not used on transmit and are written with zeros on receive. The character must not exceed 16 bits. For a 14-bit data length, set SL to one stop bit and disable parity. For a 13-bit data length with parity enabled, set SL to one stop bit. Writing values 0 to 3 to CLEN causes erratic behavior. Character length (transparent). The values 3–15 specify 4–16 bits per character. If a character is less than 8 bits, the most-significant bits of the byte in buffer memory are not used on transmit and are written with zeros on receive. If character length is more than 8 bits but less than 16, the most-significant bits of the half-word in buffer memory are not used on transmit and are written with zeros on receive. Note: Using values 0–2 causes erratic behavior. Larger character lengths increase an SMC channel’s potential performance and lowers the performance impact of other channels. For instance, using 16- rather than 8-bit characters is encouraged if 16-bit characters are acceptable in the end application. Character length (GCI). Number of bits in the C/I and monitor channels of the SCIT channels 0 or 1. (values 0–15 correspond to 1–16 bits) CLEN should be 13 for SCIT channel 0 or GCI (8 data bits, plus A and E bits, plus 4 C/I bits = 14 bits). It should be 15 for the SCIT channel 1 (8 data, bits, plus A and E bits, plus 6 C/I bits = 16 bits). 5 SL Stop length. (UART) 0 One stop bit. 1 Two stop bits. Reserved, should be cleared. (transparent) Monitor enable. (GCI) 0 The SMC does not support the monitor channel. 1 The SMC supports the monitor channel. Description — ME MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-3 Serial Management Controllers (SMCs) Table 28-1. SMCMR1/SMCMR2 Field Descriptions (continued) Bits 6 Name PEN Description Parity enable. (UART) 0 No parity. 1 Parity is enabled for the transmitter and receiver as determined by the PM bit. Byte sequence(transparent). Controls the byte transmission sequence if REVD is set for a character length greater than 8 bits. Clear BS to maintain behavior compatibility with MC68360 QUICC. 0 Normal mode. This should be selected if the character length is not larger than 8 bits. 1 Transmit lower address byte first. Reserved, should be cleared. (GCI) Parity mode. (UART) 0 Odd parity. 1 Even parity. BS — 7 PM REVD Reverse data. (transparent) 0 Normal mode. 1 Reverse the character bit order. The msb is sent first. C# SCIT channel number. (GCI) 0 SCIT channel 0 1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips. Reserved, should be cleared. SMC mode. 00 GCI or SCIT support. 01 Reserved. 10 UART (must be selected for SMC UART operation). 11 Totally transparent operation. Diagnostic mode. 00 Normal operation. 01 Local loopback mode. 10 Echo mode. 11 Reserved. SMC transmit enable. 0 SMC transmitter disabled. 1 SMC transmitter enabled. SMC receive enable. 0 SMC receiver disabled. 1 SMC receiver enabled. 8–9 10–11 — SM 12–13 DM 14 TEN 15 REN 28.2.2 SMC Buffer Descriptor Operation In UART and transparent modes, the SMC’s memory structure is like the SCC’s, except that SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized in a BD table located in the dual-port RAM. See Figure 28-3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-4 Freescale Semiconductor Serial Management Controllers (SMCs) Dual-Port RAM External Memory TxBD Table Status and Control SMC TxBD Table Data Length Buffer Pointer Tx Data Buffer RxBD Table SMC RxBD Table Status and Control Data Length Buffer Pointer Rx Data Buffer Pointer to SMCx RxBD Table Pointer to SMCx TxBD Table Figure 28-3. SMC Memory Structure The BD table allows buffers to be defined for transmission and reception. Each table forms a circular queue. The CP uses BDs to confirm reception and transmission so that the processor knows buffers have been serviced. The data resides in external or internal buffers. When SMCs are configured to operate in GCI mode, their memory structure is predefined to be one half-word long for transmit and one half-word long for receive. For more information on these half-word structures, see Section 28.5, “The SMC in GCI Mode.” 28.2.3 SMC Parameter RAM The CP accesses each SMC’s parameter table using a user-programmed pointer (SMCx_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” Each SMC parameter RAM table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). The protocol-specific portions of the SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM shared by the UART and transparent protocols is shown in Table 28-2. Parameter RAM for GCI protocol is described in Table 28-17. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-5 Serial Management Controllers (SMCs) Table 28-2. SMC UART and Transparent Parameter RAM Memory Map Offset 1 0x00 0x02 Name RBASE TBASE Width Description Hword RxBDs and TxBDs base address. (BD table pointer) Define starting points in the dual-port RAM of the set of BDs for the SMC send and receive functions. They allow Hword flexible partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs and by setting W in the last BD in each list, BDs are allocated for the send and receive side of every SMC. Initialize these entries before enabling the corresponding channel. Configuring BD tables of two enabled SMCs to overlap causes erratic operation. RBASE and TBASE should be a multiple of eight. Byte Byte Rx/Tx function code. See Section 28.2.3.1, “SMC Function Code Registers (RFCR/TFCR).” 0x04 0x05 0x06 RFCR TFCR MRBLR Hword Maximum receive buffer length. The most bytes the MPC8280 writes to a receive buffer before moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error or end-of-frame occurs, but it cannot exceed MRBLR. MPC8280 buffers should not be smaller than MRBLR. SMC transmit buffers are unaffected by MRBLR. Transmit buffers can be individually given varying lengths through the data length field. MRBLR can be changed while an SMC is operating only if it is done in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). This occurs when the CP shifts control to the next RxBD, so the change does not take effect immediately. To guarantee the exact RxBD on which the change occurs, change MRBLR only while the SMC receiver is disabled. MRBLR should be greater than zero and should be even if character length exceeds 8 bits. Word Word Rx internal state. 2 Can be used only by the CP. Rx internal data pointer. 2 Updated by the SDMA channels to show the next address in the buffer to be accessed. 0x08 0x0C 0x10 RSTATE — RBPTR Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers data to when it is in idle state, or to the current BD during frame processing. After a reset or when the end of the BD table is reached, the CP initializes RBPTR to the value in RBASE. Most applications never need to write RBPTR, but it can be written when the receiver is disabled or when no receive buffer is in use. Hword Rx internal byte count. 2 A down-count value initialized with the MRBLR value and decremented with every byte the SDMA channels write. Word Word Word Rx temp 2 Can be used only by the CP. Tx internal state. 2 Can be used only by the CP. Tx internal data pointer. 2 U pdated by the SDMA channels to show the next address in the buffer to be accessed. 0x12 0x14 0x18 0x1C 0x20 — — TSTATE — TBPTR Hword TxBD pointer. Points to the next BD for each SMC channel the transmitter transfers data from when it is in idle state or to the current BD during frame transmission. After reset or when the end of the table is reached, the CP initializes TBPTR to the TBASE value. Most applications never need to write TBPTR, but it can be written when the transmitter is disabled or when no transmit buffer is in use. For instance, after a STOP TRANSMIT or GRACEFUL STOP TRANSMIT command is issued and the frame completes its transmission. Hword Tx internal byte count. 2 A down-count value initialized with the TxBD data length and decremented with every byte the SDMA channels read. Word Tx temp. 2 Can be used only by the CP. 0x22 0x24 — — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-6 Freescale Semiconductor Serial Management Controllers (SMCs) Table 28-2. SMC UART and Transparent Parameter RAM Memory Map (continued) Offset 1 0x28 Name MAX_IDL Width Description Hword Maximum idle characters. (UART protocol-specific parameter) When a character is received on the line, the SMC starts counting idle characters received. If MAX_IDL idle characters arrive before the next character, an idle time-out occurs and the buffer closes, which sends an interrupt request to the core to receive data from the buffer. MAX_IDL demarcates frames in UART mode. Clearing MAX_IDL disables the function so the buffer never closes, regardless of how many idle characters are received. An idle character is calculated as follows: 1 + data length (5 to 14) + 1 (if parity bit is used) + number of stop bits (1 or 2). For example, for 8 data bits, no parity, and 1 stop bit, character length is 10 bits. Hword Temporary idle counter. (UART protocol-specific parameter) Down-counter in which the CP stores the current idle counter value in the MAX_IDL time-out process. Hword Last received break length. (UART protocol-specific parameter) Holds the length of the last received break character sequence measured in character units. For example, if the receive signal is low for 20 bit times and the defined character length is 10 bits, BRKLN = 0x002, indicating that the break sequence is at least 2 characters long. BRKLN is accurate to within one character length. Hword Receive break condition counter. (UART protocol-specific parameter) Counts break conditions on the line. A break condition may last for hundreds of bit times, yet BRKEC increments only once during that period. Hword Break count register (transmit). (UART protocol-specific parameter) Determines the number of break characters the UART controller sends. Set when the SMC sends a break character sequence after a STOP TRANSMIT command. For 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character is 10 zeros. Hword Temporary bit mask. (UART protocol-specific parameter) Word SDMA Temp 0x2A 0x2C IDLC BRKLN 0x2E BRKEC 0x30 BRKCR 0x32 0x34 1 2 R_MASK — From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at IMMR + 0x88FC. Not accessed for normal operation. May hold helpful information for experienced users and for debugging. To extract data from a partially full receive buffer, issue a CLOSE RXBD command. Certain parameter RAM values must be initialized before the SMC is enabled. Other values are initialized or written by the CP. Once values are initialized, software typically does not need to update them because activity centers mostly around transmit and receive BDs rather than parameter RAM. However, note the following: • Parameter RAM can be read at any time. • Values that pertain to the SMC transmitter can be written only if SMCMR[TEN] is zero or between the STOP TRANSMIT and RESTART TRANSMIT commands. • Values for the SMC receiver can be written only when SMCMR[REN] is zero, or, if the receiver is previously enabled, after an ENTER HUNT MODE command is issued but before the CLOSE RXBD command is issued and REN is set. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-7 Serial Management Controllers (SMCs) 28.2.3.1 SMC Function Code Registers (RFCR/TFCR) The function code registers contain the transaction specification associated with SDMA channel accesses to external memory. Figure 28-4 shows the register format. 0 Field R/W Addr 1 2 GBL 3 BO R/W SMC base + 0x04 (RFCR)/SMC base + 0x05 (TFCR) 4 5 TC2 6 DTB 7 — Figure 28-4. SMC Function Code Registers (RFCR/TFCR) Table 28-3 describes FCR fields. Table 28-3. RFCR/TFCR Field Descriptions Bit 0–1 2 Name — GBL Reserved, should be cleared. Global access bit 0 Disable memory snooping 1 Enable memory snooping Byte ordering. Selects byte ordering of the data buffer. 00 The DEC/Intel convention (swapped operation or little-endian). The transmission order of bytes within a buffer word is opposite of Freescale mode. (32-bit port size memory only). 01 Munged little-endian. As data is sent onto the serial line from the buffer, the LSB of the buffer double word contains data to be sent earlier than the MSB of the same double word. 1x Freescale (big-endian) byte ordering (normal operation). As data is sent onto the serial line from the buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same word. Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Data bus indicator. 0 Use 60x bus for SDMA operation. 1 Use local bus for SDMA operation. Reserved, should be cleared. Description 3–4 BO 5 6 TC2 DTB 7 — 28.2.4 Disabling SMCs On-the-Fly An SMC can be disabled and reenabled later by ensuring that buffers are closed properly and new data is transferred to or from a new buffer. Such a sequence is required if the parameters to be changed are not dynamic. If the register or bit description states that dynamic changes are allowed, the sequences need not be followed and the register or bits may be changed immediately. NOTE The SMC does not have to be fully disabled for parameter RAM to be modified. Table 28-2 describes when parameter RAM values can be modified. To disable all SCCs, SMCs, the SPI, and the I2C, use the CPCR to reset the CPM with a single command. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-8 Freescale Semiconductor Serial Management Controllers (SMCs) 28.2.4.1 SMC Transmitter Full Sequence Follow these steps to fully enable or disable the SMC transmitter: 1. If the SMC is sending data, issue a STOP TRANSMIT command to stop transmission smoothly. If the SMC is not sending, if TBPTR is overwritten, or if an INIT TX PARAMETERS command is executed, this command is not required. 2. Clear SMCMR[TEN] to disable the SMC transmitter and put it in reset state. 3. Update SMC transmit parameters, including the parameter RAM. To switch protocols or reinitialize parameters, issue an INIT TX PARAMETERS command. 4. Issue a RESTART TRANSMIT if an INIT TX PARAMETERS was issued in step 3. 5. Set SMCMR[TEN]. Transmission now begins using the TxBD that the TBPTR value pointed to as soon as the R bit is set in the TxBD. 28.2.4.2 SMC Transmitter Shortcut Sequence This shorter sequence reinitializes transmit parameters to the state they had after reset. 1. Clear SMCMR[TEN]. 2. Issue an INIT TX PARAMETERS command and make any additional changes. 3. Set SMCMR[TEN]. 28.2.4.3 SMC Receiver Full Sequence Follow these steps to fully enable or disable the receiver: 1. Clear SMCMR[REN]. Reception is aborted immediately, which disables the SMC receiver and puts it in a reset state. 2. Modify SMC receive parameters, including parameter RAM. To switch protocols or reinitialize SMC receive parameters, issue an INIT RX PARAMETERS command. 3. Issue a CLOSE RXBD command if INIT RX PARAMETERS was not issued in step 2. 4. Set SMCMR[REN]. Reception immediately uses the RxBD that RBPTR pointed to if E is set in the RxBD. 28.2.4.4 SMC Receiver Shortcut Sequence This shorter sequence reinitializes receive parameters to their state after reset. 1. Clear SMCMR[REN]. 2. Issue an INIT RX PARAMETERS command and make any additional changes. 3. Set SMCMR[REN]. 28.2.4.5 Switching Protocols To switch the protocol that the SMC is executing without resetting the board or affecting any other SMC, use one command and follow these steps: 1. Clear SMCMR[REN] and SMCMR[TEN]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-9 Serial Management Controllers (SMCs) 2. Issue an INIT TX AND RX PARAMETERS COMMAND to initialize transmit and receive parameters. Make any additional SMCMR changes. 3. Set SMCMR[REN, TEN]. The SMC is now enabled with the new protocol. 28.2.5 Saving Power When SMCMR[TEN, REN] are cleared, the SMC consumes little power. 28.2.6 Handling Interrupts in the SMC Follow these steps to handle an interrupt in the SMC: 1. Once an interrupt occurs, read SMCE to identify the interrupt source. The SMCE bits are usually cleared at this time. 2. Process the TxBD to reuse it if SMCE[TXB] is set. Extract data from the RxBD if SMCE[RXB] is set. To send another buffer, set TxBD[R]. 3. Execute the rfi instruction. 28.3 SMC in UART Mode SMCs generally offer less functionality and performance in UART mode than do SCCs, which makes them more suitable for simpler debug/monitor ports instead of full-featured UARTs. SMCs do not support the following features in UART mode. • RTS, CTS, and CD signals • Receive and transmit sections clocked at different rates • Fractional stop bits • Built-in multidrop modes • Freeze mode for implementing flow control • Isochronous (1× clock) operation (A 16× clock is required for UART operation.) • Interrupts on special control character reception • Ability to transmit data on demand using the TODR • SCCS register to determine idle status of the receive signal • Other features for the SCCs as described in the GSMR However, SMCs allow a data length of up to 14 bits; SCCs support up to 8 bits. SMCLK 16x (not to scale) SMTXD Start Bit 5 to 14 Data Bits with the Least Significant Bit First Parity Bit (Optional) 1 or 2 Stop Bits Figure 28-5. SMC UART Frame Format MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-10 Freescale Semiconductor Serial Management Controllers (SMCs) 28.3.1 Features The following list summarizes the main features of the SMC in UART mode: • Flexible message-oriented data structure • Programmable data length (5–14 bits) • Programmable 1 or 2 stop bits • Even/odd/no parity generation and checking • Frame error, break, and idle detection • Transmit preamble and break sequences • Received break character length indication • Continuous receive and transmit modes 28.3.2 SMC UART Channel Transmission Process The UART transmitter is designed to work with almost no intervention from the core. When the core enables the SMC transmitter, it starts sending idles. The SMC immediately polls the first BD in the transmit channel BD table and once every character time after that, depending on character length. When there is a message to transmit, the SMC fetches data from memory and starts sending the message. When a BD data is completely written to the transmit FIFO, the SMC writes the message status bits into the BD and clears R. An interrupt is issued if the I bit in the BD is set. If the next TxBD is ready, the data from its buffer is appended to the previous data and sent over the transmit signal without any gaps between buffers. If the next TxBD is not ready, the SMC starts sending idles and waits for the next TxBD to be ready. By appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a specific buffer, or each block is sent. The SMC then proceeds to the next BD. If the CM bit is set in the TxBD, the R bit is not cleared, allowing a buffer to be automatically resent next time the CP accesses this buffer. For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R is cleared in the BD. 28.3.3 SMC UART Channel Reception Process When the core enables the SMC receiver, it enters hunt mode and waits for the first character. The CP then checks the first RxBD to see if it is empty and starts storing characters in the buffer. When the buffer is full or the MAX_IDL timer expires (if enabled), the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If incoming data exceeds the buffer’s length, the SMC fetches the next BD, and, if it is empty, continues transferring data to this BD’s buffer. If CM is set in the RxBD, the E bit is not cleared, so the CP can overwrite this buffer on its next access. 28.3.4 Programming the SMC UART Controller UART mode is selected by setting SMCMR[SM] to 0b10. See Section 28.2.1, “SMC Mode Registers (SMCMR1/SMCMR2).” UART mode uses the same data structure as other modes. This structure supports multibuffer operation and allows break and preamble sequences to be sent. Overrun, parity, and framing MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-11 Serial Management Controllers (SMCs) errors are reported via the BDs. At its simplest, the SMC UART controller functions in a character-oriented environment, whereas each character is sent with the selected stop bits and parity. They are received into separate 1-byte buffers. A maskable interrupt can be generated when each buffer is received. Many applications can take advantage of the message-oriented capabilities that the SMC UART supports through linked buffers for sending or receiving. Data is handled in a message-oriented environment, so entire messages can be handled instead of individual characters. A message can span several linked buffers; each one can be sent and received as a linked list of buffers without core intervention, which simplifies programming and saves processor overhead. In a message-oriented environment, an idle sequence is used as the message delimiter. The transmitter can generate an idle sequence before starting a new message and the receiver can close a buffer when an idle sequence is found. 28.3.5 SMC UART Transmit and Receive Commands Table 28-4. Transmit Commands Table 28-4 describes transmit commands issued to the CPCR. Command STOP TRANSMIT Description Disables transmission of characters on the transmit channel. If the SMC UART controller receives this command while sending a message, it stops sending. The SMC UART controller finishes sending any data that has already been sent to its FIFO and shift register and then stops sending data. The TBPTR is not advanced when this command is issued. The SMC UART controller sends a programmable number of break sequences and then sends idles. The number of break sequences, which can be zero, should be written to the BRKCR before this command is issued to the SMC UART controller. Enables characters to be sent on the transmit channel. The SMC UART controller expects it after disabling the channel in its SMCMR and after issuing the STOP TRANSMIT command. The SMC UART controller resumes transmission from the current TBPTR in the channel’s TxBD table. Initializes transmit parameters in this serial channel’s parameter RAM to their reset state and should only be issued when the transmitter is disabled. The INIT TX and RX PARAMETERS command can also be used to reset the transmit and receive parameters. RESTART TRANSMIT INIT TX PARAMETERS Table 28-5 describes receive commands issued to the CPCR. Table 28-5. Receive Commands Command ENTER HUNT MODE CLOSE RXBD Description Use the CLOSE RXBD command instead ENTER HUNT MODE for an SMC UART channel. Forces the SMC to close the current receive BD if it is currently being used and to use the next BD in the list for any subsequently received data. If the SMC is not receiving data, no action is taken. Initializes receive parameters in this serial channel parameter RAM to reset state. Issue it only if the receiver is disabled. INIT TX AND RX PARAMETERS resets both receive and transmit parameters. INIT RX PARAMETERS 28.3.6 Sending a Break A break is an all-zeros character without stop bits. It is sent by issuing a STOP TRANSMIT command. After sending any outstanding data, the SMC sends a character of consecutive zeros, the number of which is the sum of the character length, plus the number of start, parity, and stop bits. The SMC sends a programmable MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-12 Freescale Semiconductor Serial Management Controllers (SMCs) number of break characters according to BRKCR and then reverts to idle or sends data if a RESTART TRANSMIT is issued before completion. When the break completes, the transmitter sends at least one idle character before sending any data to guarantee recognition of a valid start bit. 28.3.7 Sending a Preamble A preamble sequence provides a way to ensure that the line is idle before a new message transfer begins. The length of the preamble sequence is constructed of consecutive ones that are one-character long. If the preamble bit in a BD is set, the SMC sends a preamble sequence before sending that buffer. For 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the buffer. If no preamble sequence is sent, data from two ready transmit buffers can be sent on the transmit signal with no delay between them. 28.3.8 Handling Errors in the SMC UART Controller The SMC UART controller reports character reception error conditions via the channel BDs and the SMCE. Table 28-6 describes the reception errors. The SMC UART controller has no transmission errors. Table 28-6. SMC UART Errors Error Overrun Description The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the first character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the received character into the internal FIFO. It then writes the character to the buffer, closes it, sets the OV bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal. Overrun errors that occasionally occur when the line is idle can be ignored. The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal. An idle is found when a character of all ones is received, at which point the channel counts consecutive idle characters. If the count reaches MAX_IDL, the buffer is closed and an RXB interrupt is generated. If no receive buffer is open, this does not generate an interrupt or any status information. The idle counter is reset each time a character is received. The SMC received a character with no stop bit. When it occurs, the channel writes the received character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is enabled. When this error occurs, parity is not checked for the character. The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC, generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled. Parity Idle Sequence Receive Framing Break Sequence MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-13 Serial Management Controllers (SMCs) 28.3.9 SMC UART RxBD Using the BDs, the CP reports information about the received data on a per-buffer basis. Then it closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following occurs: • An error is received during message processing • A full receive buffer is detected • A programmable number of consecutive idle characters are received Figure 28-6 shows the format of the SMC UART RxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I — CM ID — BR FR PR — OV — Data Length Rx Data Buffer Pointer Figure 28-6. SMC UART RxBD Table 28-7 describes RxBD fields. Table 28-7. SMC UART RxBD Field Descriptions Bit 0 Name E Description Empty. 0 The buffer is full or data reception stopped due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD while E is zero. 1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (last BD in RxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is filled. 1 The SMCE[RXB] is set when this buffer is completely filled by the CP, indicating the need for the core to process the buffer. RXB can cause an interrupt if it is enabled. Reserved, should be cleared. Continuous mode. 0 Normal operation. 1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception, regardless of how CM is set. Buffer closed on reception of idles. Set when the buffer has closed because a programmable number of consecutive idle sequences is received. The CP writes ID after received data is in the buffer. 1 2 — W 3 I 4–5 6 — CM 7 ID MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-14 Freescale Semiconductor Serial Management Controllers (SMCs) Table 28-7. SMC UART RxBD Field Descriptions (continued) Bit 8–9 10 11 Name — BR FR Reserved, should be cleared. Buffer closed on reception of break. Set when the buffer closes because a break sequence was received. The CP writes BR after the received data is in the buffer. Framing error. Set when a character with a framing error is received and located in the last byte of this buffer. A framing error is a character with no stop bit. A new receive buffer is used to receive additional data. The CP writes FR after the received data is in the buffer. Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new buffer is used for additional data. The CP writes PR after received data is in the buffer. Reserved, should be cleared. Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received data is in the buffer. Reserved, should be cleared. Description 12 13 14 15 PR — OV — Data length represents the number of octets the CP writes into the buffer. After data is received in buffer, the CP only writes them once as the BD closes. Note that the memory allocated for this buffer should be no smaller than MRBLR. The Rx data buffer pointer points to the first location of the buffer and must be even. The buffer can be in internal or external memory. Figure 28-7 shows the UART RxBD process, showing RxBDs after they receive 10 characters, an idle period, and five characters (one with a framing error). The example assumes that MRBLR = 8. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-15 Serial Management Controllers (SMCs) E Status Length Pointer 0 Receive BD 0 ID 0 0008 32-Bit Buffer Pointer Buffer Full MRBLR = 8 Bytes for this SMC Buffer Byte 1 Byte 2 8 Bytes etc. Byte 8 E Status Length Pointer 0 Receive BD 1 ID 1 0002 32-Bit Buffer Pointer Idle Time-Out Occurred Buffer Byte 9 Byte 10 Empty 8 Bytes E Status Length Pointer 0 Receive BD 2 ID FR 0 0004 32-Bit Buffer Pointer Byte 4 has Framing Error 1 Buffer Byte 1 Byte 2 Byte 3 Byte 4 Error! Empty 8 Bytes Receive BD 3 E Status Length Pointer 1 XXXX 32-Bit Buffer Pointer Reception Still in Progress with this Buffer Buffer Byte 5 Additional Bytes are Stored Unless Idle Count Expires (MAX_IDL) 8 Bytes 10 Characters Long Idle Period Characters Received by UART Time 5 Characters Fourth Character Present has Framing Error! Time Figure 28-7. RxBD Example MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-16 Freescale Semiconductor Serial Management Controllers (SMCs) 28.3.10 SMC UART TxBD Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the channel TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. An SMC UART TxBD is displayed in Figure 28-8. 0 1 2 3 4 5 6 7 8 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R — W I — CM P Data Length — Tx Data Buffer Pointer Figure 28-8. SMC UART TxBD Table 28-8 describes SMC UART TxBD fields. Table 28-8. SMC UART TxBD Field Descriptions Bits 0 Name R Description Ready 0 The buffer is not ready for transmission; BD and its buffer can be altered. The CP clears R after the buffer has been sent or an error occurs. 1 The buffer has not been completely sent. This BD cannot updated while R is set. Reserved, should be cleared. Wrap (final BD in the TxBD table) 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that TBASE points to. The number of TxBDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt 0 No interrupt is generated after this buffer is serviced. 1 The SMCE[TXB] is set when this buffer is serviced. TXB can cause an interrupt if it is enabled. Reserved, should be cleared. Continuous mode 0 Normal operation. 1 The CP does not clear R after this BD is closed and automatically retransmits the buffer when it accesses this BD next. Preamble 0 No preamble sequence is sent. 1 The UART sends one all-ones character before it sends the data so that the other end detects an idle line before the data is received. If this bit is set and the data length of this BD is zero, only a preamble is sent. Reserved, should be cleared. 1 2 — W 3 I 4–5 6 — CM 7 P 8–15 — Data length represents the number of octets that the CP should transmit from this BD data buffer. However, it is never modified by the CP and normally is greater than zero. It can be zero if P is set and only a preamble is sent. If there are more than 8 bits in the UART character, data length should be even. For example, to transmit three UART characters of 8-bit data, 1 start, and 1 stop, initialize the data length field MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-17 Serial Management Controllers (SMCs) to 3. To send three UART characters of 9-bit data, 1 start, and 1 stop, the data length field should 6, because the three 9-bit data fields occupy three half words in memory (the 9 least-significant bits of each half word). Tx data buffer pointer points to the first location of the buffer. It can be even or odd, unless the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer must be even. For instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. The buffer can reside in internal or external memory. 28.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM) The SMC event register (SMCE) generates interrupts and report events recognized by the SMC UART channel. When an event is recognized, the SMC UART controller sets the corresponding SMCE bit. Bits are cleared by writing a 1; writing 0 has no effect. The SMC mask register (SMCM) has the same bit format as SMCE. Setting an SMCM bit enables, and clearing it disables, the corresponding interrupt. All unmasked bits must be cleared before the CP clears the internal interrupt request. Figure 28-9 represents the SMCE/SMCM registers. 0 1 2 3 4 5 6 7 Field Reset R/W Addr — BRKE — BRK 0 R/W — BSY TXB RXB 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2) Figure 28-9. SMC UART Event Register (SMCE)/Mask Register (SMCM) Table 28-9 describes SMCE/SMCM fields. Table 28-9. SMCE/SMCM Field Descriptions Bits 0 1 2 3 4 5 Name — Reserved, should be cleared. Description BRKE Break end. Set no sooner than after one idle bit is received after the break sequence. — BRK — BSY Reserved, should be cleared. Break character received. Set when a break character is received. If a very long break sequence occurs, this interrupt occurs only once after the first all-zeros character is received. Reserved, should be cleared. Busy condition. Set when a character is received and discarded due to a lack of buffers. Set no sooner than the middle of the last stop bit of the first receive character for which there is no available buffer. Reception resumes when an empty buffer is provided. Tx buffer. Set when the transmit data of the last character in the buffer is written to the transmit FIFO. Wait two character times to ensure that data is completely sent over the transmit signal. Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the middle of the last stop bit of the last character that is written to the receive buffer. 6 7 TXB RXB MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-18 Freescale Semiconductor Serial Management Controllers (SMCs) Figure 28-10 shows an example of the timing of various events in the SMCE. Characters Received by SMC UART Time RXD Line Idle 10 Characters Line Idle Break SMC UART SMCE Events RX RX BRK BRKE NOTES: 1. The first RX event assumes receive buffers are 6 bytes each. 2. The second RX event position is programmable based on the MAX_IDL value. 3. The BRK event occurs after the first break character is received. Characters Transmitted by SMC UART TXD Line Idle 7 Characters Line Idle SMC UART SMCE Events TX NOTES: 1. The TX event assumes all seven characters were put into a single buffer, and the TX event occurred when the seventh character was written to the SMC transmit FIFO. Figure 28-10. SMC UART Interrupts Example 28.3.12 SMC UART Controller Programming Example The following initialization sequence assumes 9,600 baud, 8 data bits, no parity, and 1 stop bit in a 66-MHz system. BRG1 and SMC1 are used. (The SMC transparent programming example uses an external clock configuration; see Section 28.4.11, “SMC Transparent NMSI Programming Example.”) 1. Configure the port D pins to enable SMTXD1 and SMRXD1. Set PPARD[8,9] and PDIRD[9]. Clear PDIRD[8] and PSORD[8,9]. 2. Configure the BRG1. Write BRGC1 with 0x0001_035A. The DIV16 bit is not used and the divider is 429 (decimal). The resulting BRG1 clock is 16× the preferred bit rate. 3. Connect BRG1 to SMC1 using the CPM mux by clearing CMXSMR[SMC1, SMC1CS]. 4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM. 5. Assuming one RxBD at the beginning of dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command. 7. Write RFCR and TFCR with 0x10 for normal operation. 8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16 bytes, so MRBLR = 0x0010. 9. Write MAX_IDL with 0x0000 in the SMC UART-specific parameter RAM to disable the MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC UART-specific parameter RAM. 11. Set BRKCR to 0x0001; if a STOP TRANSMIT COMMAND is issued, one break character is sent. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-19 Serial Management Controllers (SMCs) 12. Initialize the RxBD. Assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (not required), and 0x0000_1000 to RxBD[Buffer Pointer]. 13. Assuming the Tx data buffer is at 0x0000_2000 in main memory and contains five 8-bit characters, write 0xB000 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 14. Write 0xFF to the SMCE1 register to clear any previous events. 15. Write 0x57 to the SMCM1 register to enable all possible SMC1 interrupts. 16. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to clear events. 17. Write 0x4820 to SMCMR to configure normal operation (not loopback), 8-bit characters, no parity, 1 stop bit. The transmitter and receiver are not yet enabled. 18. Write 0x4823 to SMCMR to enable the SMC transmitter and receiver. This additional write ensures that the TEN and REN bits are enabled last. After 5 bytes are sent, the TxBD is closed. The receive buffer closes after receiving 16 bytes. Subsequent data causes a busy (out-of-buffers) condition since only one RxBD is ready. 28.4 SMC in Transparent Mode Compared to the SCC in transparent mode, the SMCs generally offer less functionality, which helps them provide simpler functions and slower speeds. Transparent mode is selected by programming SMCMR[SM] to 0b10. Section 28.2.1, “SMC Mode Registers (SMCMR1/SMCMR2)” describes other protocol-specific bits in the SMCMR. The SMC in transparent mode does not support the following features: • Independent transmit and receive clocks, unless connected to a TDM channel of an SIx • CRC generation and checking • Full RTS, CTS, and CD signals (supports only one SMSYN signal) • Ability to transmit data on demand using the TODR • Receiver/transmitter in transparent mode while executing another protocol • 4-, 8-, or 16-bit SYNC recognition • Internal DPLL support However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to as the SMC transparent controller. 28.4.1 Features The following list summarizes the features of the SMC in transparent mode: • Flexible data buffers • Connects to a TDM bus using the TSA in an SIx MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-20 Freescale Semiconductor Serial Management Controllers (SMCs) • • • • • Transmits and receives transparently on its own set of signals using a sync signal to synchronize the beginning of transmission and reception to an external event Programmable character length (4–16) Reverse data mode Continuous transmission and reception modes Four commands 28.4.2 SMC Transparent Channel Transmission Process The transparent transmitter is designed to work with almost no core intervention. When the core enables the SMC transmitter in transparent mode, it starts sending idles. The SMC immediately polls the first BD in the transmit channel BD table and once every character time, depending on the character length (every 4 to 16 serial clocks). When there is a message to transmit, the SMC fetches the data from memory and starts sending the message when synchronization is achieved. Synchronization can be achieved in two ways. First, when the transmitter is connected to a TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the transmitter waits for the first bit of its time slot before it starts transmitting. Data is sent only during the time slots defined by the TSA. Secondly, when working with its own set of signals, the transmitter starts sending when SMSYNx is asserted. When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is set, the SMC writes the message status bits into the BD and clears the R bit. It then starts transmitting idles. When the end of the current BD is reached and the L bit is not set, only R is cleared. In both cases, an interrupt is issued according to the I bit in the BD. By appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a specific buffer, or each block is sent. The SMC then proceeds to the next BD. If no additional buffers have been presented to the SMC for transmission and the L bit was cleared, an underrun is detected and the SMC begins sending idles. If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer on its next access. For instance, if a single TxBD is initialized with the CM and W bits set, the buffer is sent continuously until R is cleared in the BD. 28.4.3 SMC Transparent Channel Reception Process When the core enables the SMC receiver in transparent mode, it waits for synchronization before receiving data. Once synchronization is achieved, the receiver transfers the incoming data into memory according to the first RxBD in the table. Synchronization can be achieved in two ways. First, when the receiver is connected to a TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the receiver waits for the first bit of its time slot to occur before reception begins. Data is received only during the time slots defined by the TSA. Secondly, when working with its own set of signals, the receiver starts reception when SMSYNx is asserted. When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If incoming data exceeds the data buffer length, the SMC fetches the next BD; if it is empty, the MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-21 Serial Management Controllers (SMCs) SMC continues transferring data to this BD’s buffer. If the CM bit is set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the buffer on its next access. 28.4.4 Using SMSYN for Synchronization The SMSYN signal offers a way to externally synchronize the SMC channel. This method differs somewhat from the synchronization options available in the SCCs and should be studied carefully. See Figure 28-11 for an example. Once SMCMR[REN] is set, the first rising edge of SMCLK that finds SMSYN low causes the SMC receiver to achieve synchronization. Data starts being received or latched on the same rising edge of SMCLK that latched SMSYN. This is the first bit of data received. The receiver does not lose synchronization again, regardless of the state of SMSYN, until REN is cleared. Once SMCMR[TEN] is set, the first rising edge of SMCLK that finds SMSYN low synchronizes the SMC transmitter which begins sending ones asynchronously from the falling edge of SMSYN. After one character of ones is sent, if the transmit FIFO is loaded (the TxBD is ready with data), data starts being send on the next falling edge of SMCLK after one character of ones is sent. If the transmit FIFO is loaded later, data starts being sent after some multiple number of all-ones characters is sent. Note that regardless of whether the transmitter or receiver uses SMSYN, it must make glitch-free transitions from high-to-low or low-to-high. Glitches on SMSYN can cause errant behavior of the SMC. The transmitter never loses synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an ENTER HUNT MODE command is issued. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-22 Freescale Semiconductor Serial Management Controllers (SMCs) SMCLK SMSYN SMTXD 1s are sent Five 1s are sent SMC1 Transmit Data TEN set here Five 1s SMSYN Tx FIFO assume loaded detected low here approximatelycharacter length here equals 5 First bit of first 5-bit transmit character (lsb) Transmission could begin here if Tx FIFO not loaded in time SMCLK SMSYN SMRXD SMC1 Receive Data REN set SMSYN First bit here or detected of receive data enter hunt low here (lsb) mode command issued NOTES: 1. SMCLK is an internal clock derived from an external CLKx or a baud rate generator. 2. This example shows the SMC receiver and transmitter enabled separately. If the REN and TEN bits were set at the same time, a single falling edge of SMSYN would synchronize both. Figure 28-11. Synchronization with SMSYNx If both SMCMR[REN] and SMCMR[TEN] are set, the first falling edge of SMSYN causes both the transmitter and receiver to achieve synchronization. The SMC transmitter can be disabled and reenabled and SMSYN can be used again to resynchronize the transmitter itself. Section 28.2.4, “Disabling SMCs On-the-Fly,” describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may be insufficient. The receiver can also be resynchronized this way. 28.4.5 Using the Time-Slot Assigner (TSA) for Synchronization The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel. This method is similar, except that the synchronization event is the first time-slot for this SMC receiver/transmitter after the frame sync indication rather than the falling edge of SMSYN. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes how to configure time slots. The TSA allows the SMC receiver and transmitter to be enabled simultaneously and synchronized separately; SMSYN does not provide this capability. Figure 28-12 shows synchronization using the TSA. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-23 Serial Management Controllers (SMCs) TDM Tx CLK TDM Tx SYNC SMC1 TDM Tx SMC1 After TEN is set, transmission begins here. TDM Rx CLK If SMC runs out of Tx buffers and new ones are provided later, transmission begins at the beginning of either time slot. TDM Rx SYNC TDM Rx SMC1 SMC1 After REN is set or after enter hunt mode command, reception begins here. Figure 28-12. Synchronization with the TSA Once SMCMR[REN] is set, the first time-slot after the frame sync causes the SMC receiver to achieve synchronization. Data is received immediately, but only during defined receive time slots. The receiver continues receiving data during its defined time slots until REN is cleared. If an ENTER HUNT MODE command is issued, the receiver loses synchronization, closes the buffer, and resynchronizes to the first time slot after the frame sync. Once SMCMR[TEN] is set, the SMC waits for the transmit FIFO to be loaded before trying to achieve synchronization. When the transmit FIFO is loaded, synchronization and transmission begins depending on the following: • If a buffer is made ready when the SMC2 is enabled, the first byte is placed in time slot 1 if CLSN is 8 and to slot 2 if CLSN is 16. • If a buffer has its SMC enabled, then the first byte in the next buffer can appear in any time slot associated with this channel. • If a buffer is ended with the L bit set, then the next buffer can appear in any time slot associated with this channel. If the SMC runs out of transmit buffers and a new buffer is provided later, idles are sent in the gap between buffers. Data transmission from the later buffer begins at the start of an SMC time slot, but not necessarily the first time slot after the frame sync. So, to maintain a certain bit alignment beginning with the first time slot, make sure that at least one TxBD is always ready and that underruns do not occur. Otherwise, the SMC transmitter should be disabled and reenabled. Section 28.2.4, “Disabling SMCs On-the-Fly,” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-24 Freescale Semiconductor Serial Management Controllers (SMCs) describes how to safely disable and reenable the SMC. Simply clearing and setting TEN may not be enough. 28.4.6 SMC Transparent Commands Table 28-10. SMC Transparent Transmit Commands Table 28-10 describes transmit commands issued to the CPCR. Command STOP TRANSMIT Description After hardware or software is reset and the channel is enabled in the SMCM, the channel is in transmit enable mode and polls the first BD. This command disables transmission of frames on the transmit channel. If the transparent controller receives this command while sending a frame, it stops after the contents of the FIFO are sent (up to 2 characters). The TBPTR is not advanced to the next BD, no new BD is accessed, and no new buffers are sent for this channel. The transmitter sends idles until a RESTART TRANSMIT command is issued. Starts or resumes transmission from the current TBPTR in the channel TxBD table. When the channel receives this command, it polls the R bit in this BD. The SMC expects this command after a STOP TRANSMIT is issued. The channel in its mode register is disabled or after a transmitter error occurs. Initializes transmit parameters in this serial channel to reset state. Use only if the transmitter is disabled. The INIT TX AND RX PARAMETERS command resets transmit and receive parameters. RESTART TRANSMIT INIT TX PARAMETERS Table 28-11 describes receive commands issued to the CPCR. Table 28-11. SMC Transparent Receive Commands Command ENTER HUNT MODE Description Forces the SMC to close the current receive BD if it is in use and to use the next BD for subsequent data. If the SMC is not receiving data, the buffer is not closed. Additionally, this command causes the receiver to wait for a resynchronization before reception resumes. Forces the SMC to close the current receive BD if it in use and to use the next BD in the list for subsequent received data. If the SMC is not in the process of receiving data, no action is taken. Initializes receive parameters in this serial channel to reset state. Use only if the receiver is disabled. The INIT TX AND RX PARAMETERS command resets receive and transmit parameters. CLOSE RXBD iNIT RX PARAMETERS 28.4.7 Handling Errors in the SMC Transparent Controller Table 28-12. SMC Transparent Error Conditions The SMC uses BDs and the SMCE to report message send and receive errors. Error Underrun Descriptions The channel stops sending the buffer, closes it, sets UN in the BD, and generates a TXE interrupt if it is enabled. The channel resumes sending after a RESTART TRANSMIT command. Underrun cannot occur between frames. The SMC maintains an internal FIFO for receiving data. If the buffer is in external memory, the CP begins programming the SDMA channel when the first character is received into the FIFO. If a FIFO overrun occurs, the SMC writes the received data character over the previously received character. The previous character and its status bits are lost. Then the channel closes the buffer, sets OV in the BD, and generates the RXB interrupt if it is enabled. Reception continues as normal. Overrun MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-25 Serial Management Controllers (SMCs) 28.4.8 SMC Transparent RxBD Using BDs, the CP reports information about the received data for each buffer and closes the current buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the following events: • An overrun error occurs. • A full receive buffer is detected. • The ENTER HUNT MODE command is issued. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I — CM Data Length Rx Data Buffer Pointer — OV — Figure 28-13. SMC Transparent RxBD Table 28-13 describes SMC transparent RxBD fields. Table 28-13. SMC Transparent RxBD Field Descriptions Bits 0 Name E Description Empty. 0 The buffer is full or reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD while E = 0. 1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (last BD in RxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to. The number of RxBDs is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is filled. 1 SMCE[RXB] is set when the CP completely fills this buffer indicating that the core must process the buffer. The RXB bit can cause an interrupt if it is enabled. Reserved, should be cleared. Continuous mode. 0 Normal operation. 1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the CP next accesses this BD. However, E is cleared if an error occurs during reception, regardless of how CM is set. Reserved, should be cleared. Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received data is placed into the buffer. Reserved, should be cleared. 1 2 — W 3 I 4–5 6 — CM 7–13 14 15 — OV — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-26 Freescale Semiconductor Serial Management Controllers (SMCs) Data length and buffer pointer fields are described in Section 20.2, “SCC Buffer Descriptors (BDs).” 28.4.9 SMC Transparent TxBD Data is sent to the CP for transmission on an SMC channel by arranging it in buffers referenced by the channel TxBD table. The CP uses BDs to confirm transmission or indicate error conditions so the processor knows buffers have been serviced. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R — W I L — CM Data Length Tx Data Buffer Pointer — UN — Table 28-14. SMC Transparent TxBD Table 28-15 describes SMC transparent TxBD fields. Table 28-15. SMC Transparent TxBD Field Descriptions Bits Name 0 R Description Ready. 0 The buffer is not ready for transmission. The BD and buffer can be updated. The CP clears R after the buffer is sent or after an error occurs. 1 The user-prepared data buffer is not sent or is being sent. BD fields cannot be updated if R is set. Reserved, should be cleared. Wrap (final BD in table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that TBASE points to. The number of TxBDs in this table is programmable and determined by theW bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is serviced; SMCE[TXE] is unaffected. 1 SMCE[TXB] or SMCE[TXE] are set when the buffer is serviced. They can cause interrupts if they are enabled. Last in message. 0 The last byte in the buffer is not the last byte in the transmitted transparent frame. Data from the next transmit buffer (if ready) is sent immediately after the last byte of this buffer. 1 The last byte in this buffer is the last byte in the transmitted transparent frame. After this buffer is sent, the transmitter requires synchronization before the next buffer is sent. Reserved, should be cleared. Continuous mode. 0 Normal operation. 1 The CP does not clear R after this BD is closed, allowing the buffer to be automatically resent when the CP accesses this BD again. However, the R bit is cleared if an error occurs during transmission, regardless of how CM is set. Reserved, should be cleared. 1 2 — W 3 I 4 L 5 6 — CM 7–13 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-27 Serial Management Controllers (SMCs) Table 28-15. SMC Transparent TxBD Field Descriptions (continued) Bits Name 14 15 UM — Description Underrun. Set when the SMC encounters a transmitter underrun condition while sending the buffer. Reserved, should be cleared. Data length represents the number of octets the CP should transmit from this buffer. It is never modified by the CP. The data length can be even or odd, but if the number of bits in the transparent character is greater than 8, the data length should be even. For example, to transmit three transparent 8-bit characters, the data length field should be initialized to 3. However, to transmit three transparent 9-bit characters, the data length field should be initialized to 6 because the three 9-bit characters occupy three half words in memory. The data buffer pointer points to the first byte of the buffer. They can be even or odd, unless character length is greater than 8 bits, in which case the transmit buffer pointer must be even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. The buffer can reside in internal or external memory. 28.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) The SMC event register (SMCE) generates interrupts and reports events recognized by the SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit. Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing a 1 (writing 0 has no effect). Unmasked bits must be cleared before the CP clears the internal interrupt request. The SMCE and SMCM registers are displayed in Figure 28-14. 0 1 2 3 4 5 6 7 Field Reset R/W Addr — TXE 0 R/W — BSY TXB RXB 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2) Figure 28-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM) Table 28-16 describes SMCE/SMCM fields. Table 28-16. SMCE/SMCM Field Descriptions Bits 0–2 3 4 5 Name — TXE — BSY Reserved, should be cleared. Tx error. Set when an underrun error occurs on the transmitter channel. This event is not maskable via the TxBD[I] bit. Reserved, should be cleared. Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception begins after a new buffer is provided. Executing an ENTER HUNT MODE command makes the receiver wait for resynchronization. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-28 Freescale Semiconductor Serial Management Controllers (SMCs) Table 28-16. SMCE/SMCM Field Descriptions (continued) Bits 6 Name TXB Description Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character starts being sent. A one character-time delay is required to ensure that data is completely sent over the transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written to the transmit FIFO. A two character-time delay is required to ensure that data is completely sent. Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its associated RxBD is now closed. 7 RXB 28.4.11 SMC Transparent NMSI Programming Example The following example initializes the SMC1 transparent channel over its own set of signals. The CLK9 signal supplies the transmit and receive clocks; the SMSYNx signal is used for synchronization. (The SMC UART programming example uses a BRG configuration; see Section 28.3.12, “SMC UART Controller Programming Example.”) 1. Configure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set PPARD[7,8,9] and PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9]. 2. Configure the port C pins to enable CLK9. Set PPARC[23]. Clear PDIRC[23] and PSORC[23]. 3. Connect CLK9 to SMC1 using the CPM mux. Clear CMXSMR[SMC1] and program CMXSMR[SMC1CS] to 0b11. 4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM. 5. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 6. Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command. 7. Write RFCR and TFCR with 0x10 for normal operation. 8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes MRBLR = 0x0010. 9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 10. Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 11. Write 0xFF to SMCE1 to clear any previous events. 12. Write 0x13 to SMCM1 to enable all possible SMC1 interrupts. 13. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending register low (SIPNR_L) to clear events. 14. Write 0x3830 to the SMCMR to configure 8-bit characters, unreversed data, and normal operation (not loopback). The transmitter and receiver are not enabled yet. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-29 Serial Management Controllers (SMCs) 15. Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This additional write ensures that TEN and REN are enabled last. After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. 28.5 The SMC in GCI Mode The SMC can control the C/I and monitor channels of the GCI frame. When using the SCIT configuration of a GCI, one SMC can handle SCIT channel 0 and the other can handle SCIT channel 1. The main features of the SMC in GCI mode are as follows: • Each SMC channel supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications • Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1 • Full-duplex operation • Local loopback and echo capability for testing To use the SMC GCI channels properly, the TSA must be configured to route the monitor and C/I channels to the preferred SMC. Chapter 15, “Serial Interface with Time-Slot Assigner,” describes how to program this configuration. GCI mode is selected by setting SMCMR[SM] to 0b10. Section 28.2.1, “SMC Mode Registers (SMCMR1/SMCMR2)” describes other protocol-specific SMCMR bits. 28.5.1 SMC GCI Parameter RAM The GCI parameter RAM differs from that for UART and transparent mode. The CP accesses each SMC’s GCI parameter table using a user-programmed pointer (SMCx_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” Each SMC GCI parameter RAM table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). In GCI mode, parameter RAM contains the BDs instead of pointers to them. Compare Table 28-17 with Table 28-2 on page 28-6 to see the differences. (In GCI mode, the SMC has no extra protocol-specific parameter RAM.) Table 28-17. SMC GCI Parameter RAM Memory Map Offset 1 0x00 0x02 0x04 0x06 0x08 0x0C Name M_RxBD M_TxBD CI_RxBD CI_TxBD RSTATE2 M_RxD 2 Width Half word Half word Half word Half word Word Half word Description Monitor channel RxBD. See Section 28.5.5, “SMC GCI Monitor Channel RxBD.” Monitor channel TxBD. See Section 28.5.6, “SMC GCI Monitor Channel TxBD.” C/I channel RxBD. See Section 28.5.7, “SMC GCI C/I Channel RxBD.” C/I channel TxBD. See Section 28.5.8, “SMC GCI C/I Channel TxBD.” Rx/Tx Internal State Monitor Rx Data MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-30 Freescale Semiconductor Serial Management Controllers (SMCs) Table 28-17. SMC GCI Parameter RAM Memory Map (continued) Offset 1 0x0E 0x10 0x12 1 2 Name M_TxD 2 CI_RxD 2 CI_TxD 2 Width Half word Half word Half word Monitor Tx Data C/I Rx Data C/I Tx Data Description From the pointer value programmed in SMCx_BASE: SMC1_BASE at 0x87FC, SMC2_BASE at 0x88FC. RSTATE, M_RxD, M_TxD, CI_RxD, and CI_TxD do not need to be accessed by the user in normal operation, and are reserved for RISC use only. 28.5.2 Handling the GCI Monitor Channel The following sections describe how the GCI monitor channel is handled. 28.5.2.1 SMC GCI Monitor Channel Transmission Process Monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers and transferring of the S and Q bits). Monitor channel 1 is used for programming and controlling voice/data modules such as CODECs. The core writes the byte into the TxBD. The SMC sends the data on the monitor channel and handles the A and E control bits according to the GCI monitor channel protocol. The TIMEOUT command resolves deadlocks when errors in the A and E bit states occur on the data line. 28.5.2.2 SMC GCI Monitor Channel Reception Process The SMC receives data and handles the A and E control bits according to the GCI monitor channel protocol. When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated. A TRANSMIT ABORT REQUEST command causes the MPC8280 to send an abort request on the E bit. 28.5.3 Handling the GCI C/I Channel The C/I channel is used to control the layer 1 device. The layer 2 device in the TE sends commands and receives indication to or from the upstream layer 1 device through C/I channel 0. In the SCIT configuration, C/I channel 1 is used to convey real-time status information between the layer 2 device and nonlayer 1 peripheral devices (CODECs). 28.5.3.1 SMC GCI C/I Channel Transmission Process The core writes the data byte into the C/I TxBD and the SMC transmits the data continuously on the C/I channel to the physical layer device. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-31 Serial Management Controllers (SMCs) 28.5.3.2 SMC GCI C/I Channel Reception Process The SMC receiver continuously monitors the C/I channel. When it recognizes a change in the data and this value is received in two successive frames, it is interpreted as valid data. This is called the double last-look method. The CP stores the received data byte in the C/I RxBD and a maskable interrupt is generated. If the SMC is configured to support SCIT channel 1, the double last-look method is not used. 28.5.4 SMC GCI Commands Table 28-18. SMC GCI Commands The commands in Table 28-18 are issued to the CPCR. Command INIT TX AND RX PARAMETERS TRANSMIT ABORT REQUEST TIMEOUT Description Initializes transmit and receive parameters in the parameter RAM to their reset state. It is especially useful when switching protocols on a given serial channel. This receiver command can be issued when the MPC8280 implements the monitor channel protocol. When it is issued, the MPC8280 sends an abort request on the A bit. This transmitter command can be issued when the MPC8280 implements the monitor channel protocol. It is usually issued because the device is not responding or A bit errors are detected. The MPC8280 sends an abort request on the E bit at the time this command is issued. 28.5.5 SMC GCI Monitor Channel RxBD This BD, seen in Figure 28-15, is used by the CP to report information about the monitor channel receive byte. 0 1 2 3 4 7 8 15 Offset + 0 E l ER MS — DATA Figure 28-15. SMC Monitor Channel RxBD Table 28-19 describes SMC monitor channel RxBD fields. Table 28-19. SMC Monitor Channel RxBD Field Descriptions Bits 0 Name E Description Empty. 0 The CP clears E when the byte associated with this BD is available to the core. 1 The core sets E when the byte associated with this BD has been read. Last (EOM). Valid only for monitor channel protocol and is set when the EOM indication is received on the E bit. Note that when this bit is set, the data byte is invalid. Error condition. Valid only for monitor channel protocol. Set when an error occurs on the monitor channel protocol. A new byte is sent before the SMC acknowledges the previous byte. Data mismatch. Valid only for monitor channel protocol. Set when two different consecutive bytes are received; cleared when the last two consecutive bytes match. The SMC waits for the reception of two identical consecutive bytes before writing new data to the RxBD. 1 2 3 L ER MS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-32 Freescale Semiconductor Serial Management Controllers (SMCs) Table 28-19. SMC Monitor Channel RxBD Field Descriptions Bits 4–7 8–15 Name — DATA Reserved, should be cleared. Data field. Contains the monitor channel data byte that the SMC received. Description 28.5.6 SMC GCI Monitor Channel TxBD The CP uses this BD, shown in Figure 28-16, to report about the monitor channel transmit byte. 0 1 2 3 7 8 15 Offset + 0 R L AR — DATA Figure 28-16. SMC Monitor Channel TxBD Table 28-20 describes SMC monitor channel TxBD fields. Table 28-20. SMC Monitor Channel TxBD Field Descriptions Bits 0 Name R Description Ready. 0 Cleared by the CP after transmission. The TxBD is now available to the core. 1 Set by the core when the data byte associated with this BD is ready for transmission. Last (EOM). Valid only for monitor channel protocol. When L = 1, the SMC first transmits the buffer data and then transmits the EOM indication on the E bit. Abort request. Valid only for monitor channel protocol. Set by the SMC when an abort request is received on the A bit. The transmitter sends the EOM on the E bit after receiving an abort request. Reserved, should be cleared. Data field. Contains the data to be sent by the SMC on the monitor channel. 1 2 3–7 8–15 L AR — DATA 28.5.7 SMC GCI C/I Channel RxBD The CP uses this BD, seen in Figure 28-17, to report information about the C/I channel receive byte. 0 1 7 8 13 14 15 Offset + 0 E — C/I DATA — Figure 28-17. SMC C/I Channel RxBD MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-33 Serial Management Controllers (SMCs) Table 28-21 describes SMC C/I channel RxBD fields. Table 28-21. SMC C/I Channel RxBD Field Descriptions Bits 0 Name E Description Empty. 0 Cleared by the CP to indicate that the byte associated with this BD is available to the core. 1 The core sets E to indicate that the byte associated with this BD has been read. Note that additional data received is discarded until E bit is set. Reserved, should be cleared. Command/indication data bits. For C/I channel 0, bits 10–13 contain the 4-bit data field and bits 8–9 are always written with zeros. For C/I channel 1, bits 8–13 contain the 6-bit data field. Reserved, should be cleared. 1–7 8–13 14–15 — C/I DATA — 28.5.8 SMC GCI C/I Channel TxBD The CP uses this BD, as seen in Figure 28-18, to report about the C/I channel transmit byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 R — C/I DATA — Figure 28-18. SMC C/I Channel TxBD Table 28-22 describes SMC C/I channel TxBD fields. Table 28-22. SMC C/I Channel TxBD Field Descriptions Bits 0 Name R Description Ready. 0 Cleared by the CP after transmission to indicate that the BD is available to the core. 1 Set by the core when data associated with this BD is ready for transmission. Reserved, should be cleared. Command/indication data bits. For C/I channel 0, bits 10–13 hold the 4-bit data field (bits 8 and 9 are always written with zeros). For C/I channel 1, bits 8–13 contain the 6-bit data field. Reserved, should be cleared. 1–7 8–13 14–15 — C/I DATA — 28.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM) The SMCE generates interrupts and report events recognized by the SMC channel. When an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared by writing ones; writing zeros has no effect. SMCM has the same bit format as SMCE. Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding interrupt. Unmasked bits must be cleared before the CP clears the internal interrupt request to the SIU interrupt controller. Figure 28-19 displays the SMCE/SMCM registers. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-34 Freescale Semiconductor Serial Management Controllers (SMCs) 0 1 2 3 4 5 6 7 Field Reset R/W Addr — CTXB 0000_0000 R/W CRXB MTXB MRXB 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2) Figure 28-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM) Table 28-23 describes SMCE/SMCM fields. Table 28-23. SMCE/SMCM Field Descriptions Bits 0–3 4 5 6 7 Name — CTXB Reserved, should be cleared. C/I channel buffer transmitted. Set when the C/I transmit buffer is now empty. Description CRXB C/I channel buffer received. Set when the C/I receive buffer is full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer is full. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 28-35 Serial Management Controllers (SMCs) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 28-36 Freescale Semiconductor Chapter 29 Multi-Channel Controllers (MCCs) NOTE The MPC8270 and the MPC8275 have only one MCC. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. A multi-channel controller (MCC) allows the MPC8280 to support up to 128 separate time-division serial channels on one peripheral. The MPC8280 has two MCCs. Each MCC is paired with a serial interface (SI), allowing the MCC to communicate over any of that SI’s 4 time-division multiplexed streams (TDM). An MCC’s channels are assigned to a particular TDM in subgroups of 32 channels. MCC1’s channels (0-127) may not be programmed to work with SI2, nor MCC2’s channels (128-255) to work with SI1. Each channel of an MCC can be programmed to perform in a mode separate from the other channels of that MCC. Proper programming of the SI and SIRAM is responsible for the routing of timeslots within a TDM stream to the appropriate MCC channel at the desired time. Programming the SI is covered in Chapter 15, “Serial Interface with Time-Slot Assigner.” Users should be familiar with the information there before proceeding. Each MCC has the following features: • Up to 128 independent HDLC or transparent communication channels or up to 64 SS7 channels • Independent mapping for receive/transmit • Supports HDLC, transparent, or SS7 protocols on a per-channel basis • Supports additional circuit emulation service functionality when used in conjunction with ATM AAL1 • Supports interworking with AAL0 • Up to 256 DMA channels with independent buffer descriptor (BD) tables • Five interrupt circular tables with programmable size and overflow identification. One for transmit and four for receive. • Global loop mode • Individual channel loop mode • Efficient bus usage (no bus usage for inactive channel or for active channels with nothing to transmit) • Efficient control of the interrupts to the core • Uses external BD tables. • Uses on-chip dual-port RAM (DPRAM) for parameter storage MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-1 Multi-Channel Controllers (MCCs) • • • • • Uses 64-bit data transactions for reading and writing data in BDs Supports automatic routing in transparent mode using negative empty polarity Supports inverted data per channel Supports super channel synchronization in transparent mode (slot synchronization) Supports in-line synchronization in transparent mode (synchronization on a pattern of 1 or 2 bytes) 29.1 MCC Operation Overview Each MCC relies upon its corresponding SI block as its physical interface to a TDM. Once an SI’s TDM has been programmed to contain MCC-related timeslots (accomplished via SIRAM programming) and has been enabled, the SI clocks data out of an MCC channel's TX FIFO or clocks data into an MCC channel's RX FIFO as appropriate. Note that the SI contains no data buffering; data moving to or from an MCC channel’s FIFO is clocked directly through the SI to or from the TDM data lines. Activity in an MCC channel’s FIFO triggers a request to the CPM. The CPM then uses a variety of MCC-related data structures to handle that channel’s traffic. MCC global parameters govern the overall state of the MCC block and also contain some threshold settings and base pointers used by all channels for their operation. There is also one set of channel-specific parameters and channel-extra parameters per MCC channel, containing protocol state information for that channel and pointers to that particular channel's receive and transmit buffer descriptors. These parameter RAM areas are described in more detail in the following sections. Note that the channel-specific parameter area may be interpreted differently depending on what protocol is being used on that particular channel, whether it is HDLC, transparent, or SS7. If an MCC channel is being used in conjunction with AAL1 CES, there are additional programming model changes that take place. Also, if a TDM is programmed to make use of superchannelled MCC timeslots, a structure called the Superchannel Table is also used. All these parameter RAM areas are described in more detail in the following sections. 29.1.1 MCC Data Structure Organization Each MCC uses the following data structures: • Global MCC parameters (common to all the 128 channels of that MCC) placed in the DPRAM from the offset (relative to the DPRAM base address) defined in Table 14-10 on page 14-22. • Channel-specific parameters. In HDLC and transparent modes each channel uses 64 bytes of specific parameters placed in the DPRAM at offset 64*CH_NUM (relative to the DPRAM base address). In SS7 mode each channel uses 128 bytes of specific parameters placed DPRAM at offset 128*CH_NUM. CH_NUM is the channel number (0–127 for MCC1 and 128–255 for MCC2). Channel-specific parameters are described in the following sections: — Section 29.3.1, “Channel-Specific HDLC Parameters” — Section 29.3.2, “Channel-Specific Transparent Parameters” — Section 29.3.4, “Channel-Specific SS7 Parameters” Note that the DPRAM memory corresponding to the inactive channels can be used for other purposes. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-2 Freescale Semiconductor Multi-Channel Controllers (MCCs) • • • • • Channel extra parameters. Each channel use 8 bytes of extra parameters placed in the DPRAM at offset XTRABASE + 8*CH_NUM (relative to the DPRAM base address). XTRABASE is one of the global MCC parameters. Refer to Section 29.4, “Channel Extra Parameters.” Note that the DPRAM memory corresponding to the inactive channels can be used for other purposes. Superchannel table (used only if superchannelled timeslots are defined in SIRAM programming). This table is placed in the DPRAM from the offset SCTPBASE (relative to the DPRAM base address). SCTPBASE is one of the global MCC parameters. The super channel table is described in Section 29.5.1, “Superchannel Table.” BD tables placed in the external memory. All the BD tables associated with one MCC must reside in a 512-KByte segment. The absolute base addresses of a channel BD table is MCCBASE + 8*RBASE (for the receiver) and MCCBASE + 8*TBASE (for the transmitter). MCCBASE is one of the global MCC parameters and RBASE/TBASE are channel extra parameters. Each BD table is a circular queue. One BD includes status bits, start address and length of a data buffer. Figure 29-1 shows the BD structure for one MCC. Circular interrupt tables placed in the external memory. There is one table for the transmitter interrupts (base address TINTBASE) and between one and four tables for receiver interrupts (base address RINTBASE0–RINTBASE4). TINTBASE and RINTBASE0–RINTBASE4 are global MCC parameters. Three registers (MCCE, MCCM, and MCCF) at described in Section 29.8.1, “MCC Event Register (MCCE)/Mask Register (MCCM),” and Section 29.6, “MCC Configuration Registers (MCCFx).” DPRAM Buffer Descriptor Table Base Address External Memory DPRAM_base Channel 0 Parameter Channel 1 Parameter Channel j Extra Parameter RBASE TBASE x8 + Channel j RxBD Table 512 Kbytes Global MCC Parameters MCCBASE x8 + Channel j TxBD Table Figure 29-1. BD Structure for One MCC MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-3 Multi-Channel Controllers (MCCs) 29.2 Global MCC Parameters Table 29-1. Global MCC Parameters The global MCC parameters are described in Table 29-1. Offset1 0x00 0x04 0x06 Name MCCBASE Width Word Description MCC base pointer. User-initialized parameter points to the starting address of a 512-Kbyte BD segment in external memory. MCCSTATE Hword MCC state. Used by the CP for global state definition. Should be cleared during initialization. MRBLR Hword Maximum receive buffer length (user-initialized). Defines the maximum number of bytes written to a receive buffer before moving to the next buffer for this channel. This value must be a multiple of 8. Hword Global receive frame threshold. Used to reduce interrupt overhead that would otherwise occur when many short HDLC frames arrive that each cause an RXF interrupt. Programming GRFTHR can be used to limit the frequency of RXF interrupts. In normal operation, an unmasked RXF event is written to the interrupt table on each received frame. However, a user may choose to mask the RXF event and program GRFTHR instead. If the user places a non-zero value in GRFTHR, RINTx is asserted in the MCC event register when the number of RXF events reaches the GRFTHR value. Therefore, note that in addition to indicating new interrupt queue entries, the assertion of RINTx could then also be due to the threshold of received frames being reached due to activity on any of this MCC’s receive channels. Therefore, software should look for frames in all active buffer descriptor rings. This parameter does not need to be reset after an interrupt. Hword Global receive frame count. A down counter used to implement the GRFTHR feature. It should be initialized to the GRFTHR value. The CP writes an entry in a circular interrupt table and decrements GRFCNT each time a frame is received. When GRFCNT reaches zero, the CP generates an interrupt and re-initializes GRFCNT with GRFTHR. This parameter does not need to be reset after an interrupt. Word Word Word Word Temporary location for holding the receive interrupt queue entry, used by the CP (reserved) Temporary location for holding data, used by the CP (reserved) Temporary location for holding data, used by the CP (reserved) Multi-channel transmitter circular interrupt table base address. The interrupt circular table is a cyclic table (FIFO-like). Each table entry contains information about an interrupt request generated by the MCC to the host. Pointer to the transmitter circular interrupt table. The CP writes the next interrupt information to this entry when an exception occurs. The user must copy the TINTBASE value to TINTPTR before enabling interrupts. Further updates of the TINTPTR are done by the CP. Temporary location for holding the transmit interrupt queue entry, used by the CP. The 60x initializes this field before initializing the MCC. The user must clear it before enabling interrupts. 0x08 GRFTHR 0x0A GRFCNT 0x0C 0x10 0x14 0x18 RINTTMP DATA0 DATA1 TINTBASE 0x1C TINTPTR Word 0x20 TINTTMP Word 0x24 0x26 SCTPBASE Hword Internal pointer for the super channel transmit table, offset from the DPRAM address — Hword MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-4 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-1. Global MCC Parameters (continued) Offset1 0x28 Name C_MASK32 Width Word Description CRC constant (user initialized to 0xDEBB20E3). Used for 32-bit CRC-CCITT calculation if HDLC mode is chosen for a selected channel. (This option is programmable. For each HDLC channel, one of two CRC-CCITT can be selected through the CHAMR.) 0x2C 0x2E XTRABASE Hword Pointer the beginning of the extra parameters information, offset from the DPRAM address C_MASK16 Hword CRC constant (user initialized to 0xF0B8). Used for 16-bit CRC-CCITT calculation if HDLC mode is chosen for a selected channel. This option is programmable. For each HDLC channel, one of two CRC-CCITT can be selected through the CHAMR. Word Word Word Word RINTBASEx—Multi-channel receiver circular interrupt table base address. The interrupt circular table is a cyclic table (FIFO-like). Each table entry contains information about an interrupt request generated by the MCC to the host. RINTPTRx—Pointer to the receiver circular interrupt table. The CP writes the next interrupt information to this entry when an exception occurs. The user must copy the RINTBASEx value to RINTPTRx before enabling interrupts. Further updates of the RINTPTRx are done by the CP. RINTTMPx. Temporary location for holding a receive circular interrupt circular table entry (for tables 0–4), used by the CP. The user must clear it before enabling interrupts. See Section 29.8, “MCC Exceptions.” 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 1 RINTTMP0 RINTTMP1 RINTTMP2 RINTTMP3 RINTBASE0 Word RINTPTR0 Word RINTBASE1 Word RINTPTR1 Word RINTBASE2 Word RINTPTR2 Word RINTBASE3 Word RINTPTR3 TS_TMP Word Word Temporary place for time stamp Offset to MCC Base 29.3 Channel-Specific Parameters Each FIFO in the MCC is managed by a set of channel-specific parameters. These parameters can change based upon what protocol is being used on that channel. The following sections describe the various programming models used for an MCC channel. 29.3.1 Channel-Specific HDLC Parameters Table 29-2 describes channel-specific parameters for HDLC. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-5 Multi-Channel Controllers (MCCs) Table 29-2. Channel-Specific Parameters for HDLC Offset1 0x00 Name TSTATE Width Description Word Tx internal state. To start a transmitter channel the user must write to TSTATE 0xHH80_0000. HH is the TSTATE high byte described in Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” Word Zero-insertion machine state. User-initialized to one of the following values: 0x10000207 for regular channel transmitting all 1s before first frame of data 0x00000207 for regular channel transmitting flags before first frame of data 0x30000207 for inverted channel transmitting all 1s before first frame of data 0x20000207 for inverted channel transmitting flags before first frame of data Note: Used in conjunction with ZIDATA0 and ZIDATA1. Word Zero-insertion high word data buffer. User-initialized to one of the following values: 0xFFFFFFFF allows transmission of all 1s before first frame of data 0x7E7E7E7E allows transmission of flags before first frame of data Note: Used in conjunction with ZISTATE and ZIDATA1. Word Zero-insertion low word data buffer. User-initialized to one of the following values: 0xFFFFFFFF allows transmission of all 1s before first frame of data 0x7E7E7E7E allows transmission of flags before first frame of data Note: Used in conjunction with ZISTATE and ZIDATA0. 0x04 ZISTATE 0x08 ZIDATA0 0x0C ZIDATA1 0x10 0x12 0x14 0x18 0x1A 0x1C 0x20 TBDFlags Hword TxDB flags, used by the CP (read-only for the user) TBDCNT TBDPTR INTMSK CHAMR TCRC RSTATE Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Word Tx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) Hword Channel’s interrupt mask flag. See Section 29.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES.” Hword Channel mode register. See Section 29.3.1.3, “Channel Mode Register (CHAMR)—HDLC Mode.” Word Temp transmit CRC. Temp value of CRC calculation result, used by the CP (read-only for the user) Word Rx internal state. To start a receiver channel the user must write to RSTATE 0xHH80_0000. HH is the RSTATE high byte described in Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” Word Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel and 0x20FFFFE0 for inverted channel) Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF) Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF) 0x24 0x28 0x2C 0x30 0x32 0x34 ZDSTATE ZDDATA0 ZDDATA1 RBDFlags Hword RxBD flags, used by the CP (read-only for the user) RBDCNT RBDPTR Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Word Rx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-6 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-2. Channel-Specific Parameters for HDLC (continued) Offset1 0x38 Name MFLR Width Description Hword Maximum frame length register. Defines the longest expectable frame for this channel. (64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded and the LG flag is set in the last frame’s BD. An interrupt request might be generated (RXF and RXB) depending on the interrupt mask. A frame’s length is considered to be everything between flags, including CRC. No more data is written into the current buffer when the MFLR violation is detected. 0x3A 0x3C 1 MAX_CNT Hword Max_length counter, used by the CP (read-only for the user) RCRC Word Temp receive CRC, used by the CP (read-only for the user) The offset is relative to dual-port RAM (DPRAM) base address + 64*CH_NUM 29.3.1.1 Internal Transmitter State (TSTATE)—HDLC Mode Internal transmitter state (TSTATE) is a 4-byte register provides transaction parameters associated with SDMA channel accesses (like function code registers) and starts the transmitter channel. To start the channel, write 0xHH800000 to TSTATE, where HH is the TSTATE high byte (see Figure 29-2). When the channel is active, the CP changes the value of the three LSBs, hence these 3 bytes must be masked if the user reads back the TSTATE. 0 1 2 3 4 5 6 7 Field Reset R/W — GBL BO — R/W TC2 DTB BDB Figure 29-2. TSTATE High Byte TSTATE high-byte fields are described in Table 29-3. Table 29-3. TSTATE High-Byte Field Descriptions Bits 0–1 2 3–4 Name — GBL BO Reserved, should be cleared. Global. Setting GBL activates snooping (only the 60X bus can be snooped, this parameter is ignored for local bus transactions). Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next BD. 00 Reserved 01 Munged little-endian. 1x Big-endian Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Description 5 TC2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-7 Multi-Channel Controllers (MCCs) Table 29-3. TSTATE High-Byte Field Descriptions (continued) Bits 6 Name DTB Description Data bus indicator. Selects the bus that handles transfers to and from data buffers. 0 60x bus SDMA 1 Local bus SDMA BD bus. Selects the bus that handles transfers to/from BD and interrupt circular tables. 0 60x bus SDMA used for accessing BDs 1 Local bus SDMA used for accessing BDs 7 BDB 29.3.1.2 Interrupt Mask (INTMSK)—HDLC Mode The interrupt mask (INTMSK) provides bits for enabling/disabling the reporting of each possible event defined in the interrupt circular table entry. For descriptions of each event bit, refer to Section 29.8.1.1, “Interrupt Circular Table Entry.” 0 5 6 7 8 9 10 11 12 13 14 15 Interrupt Entry INTMSK — — UN TXB — — NID IDL MRF RXF BSY RXB Mask Bits Mask Bits Figure 29-3. INTMSK Mask Bits To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and no new entry is written in the circular interrupt table. The user must initialize INTMSK prior to operation. Reserved bits should remain cleared. 29.3.1.3 Channel Mode Register (CHAMR)—HDLC Mode The channel mode register (CHAMR) is a user-initialized register, shown in Figure 29-4. For a descriptions of CHAMR in transparent and SS7 modes, refer to Section 29.3.2.3 and Section 29.3.4.1 respectively. For channels that are used in conjunction with CES functionality, the user should refer to Section 29.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 Field MODE POL Reset R/W Offset 1 IDLM — RD — — CRC — TS RQN NOF R/W 0x1A Figure 29-4. Channel Mode Register (CHAMR) CHAMR fields are described in Table 29-4. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-8 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-4. CHAMR Field Descriptions Bits 0 Name Description MODE This mode bit determines whether the HDLC or transparent mode is used. It also determines how other CHAMR bits are interpreted. 0 Transparent mode. See Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.” 1 HDLC mode POL Enable polling. POL enables the transmitter to poll the TxBDs. 0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD). 1 Polling is enabled. POL is used to optimize the use of the external bus. Software should always set POL at the beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the end of a multi-frame transmission). To minimize useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Must be set. Idle mode. 0 No idle patterns are sent between frames. After sending NOF+1 flags, the transmitter starts sending the data of the frame. If the transmission is between frames and the frame buffers are not ready, the transmitter sends flags until it can start transmitting the data. 1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller than the PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in HDLC. Mode flags precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent frames. If the transmission is between frames and the frame buffer is not ready, the transmitter sends idle characters. When data is ready, the NOF+1 flags are sent followed by the data frame. If IDLE mode is selected and NOF = 1, the following sequence is sent: ......init value, FF, FF, flag, flag, data, ........ The init value before the idle will be ones. This bit must be cleared. 0 Normal bit order (transmit/receive the lsb of each octet first) 1 Reversed bit order (transmit/receive the msb of each octet first) These bits must be cleared. Selects the type of CRC when HDLC channel mode is used. 0 16-bit CCITT-CRC 1 32-bit CCITT-CRC This bit must be cleared. Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4 (n is any integer larger than 0). Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. Number of flags. NOF defines the minimum number of flags before frames: 000 At least 1 flag 001 At least 2 flags .... 111 At least 8 flags 1 2 3 1 IDLM 4 5 6–7 8 — RD — CRC 9 10 — TS 11–12 RQN 13–15 NOF MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-9 Multi-Channel Controllers (MCCs) 29.3.1.4 Internal Receiver State (RSTATE)—HDLC Mode Internal receiver state (RSTATE) is a 4-byte register that provides transaction parameters associated with SDMA channel accesses (like function code registers) and starts the receiver channel. To start the channel the user must write 0xHH800000 to RSTATE, where HH is the RSTATE high byte (see Figure 29-5). When the channel is active the CP changes the value of the 3 LSBs, hence these 3 bytes must be masked if the user reads back the RSTATE. 0 1 2 3 4 5 6 7 Field Reset R/W Addr — GBL BO — R/W 0x20 TC2 DTB BDB Figure 29-5. Rx Internal State (RSTATE) High Byte RSTATE high-byte fields are described in Table 29-5. Table 29-5. RSTATE High-Byte Field Descriptions Bits 0–1 2 3–4 Name — GBL BO Reserved, should be cleared. Global. Setting GBL activates snooping (only the 60x bus can be snooped, this parameter is ignored for local bus transactions). Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly, it takes effect at the beginning of the next frame or at the beginning of the next BD. 00 Reserved 01 Munged little-endian. 1x Big-endian Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Data bus indicator. The transfers to data buffers are handled by the: 0 60x bus SDMA 1 Local bus SDMA BD and interrupt circular tables bus indicator. The transfers to/from BD and interrupt circular tables are handled by the: 0 60x bus SDMA 1 Local bus SDMA Note: The following restrictions result from the fact that there is a common bus selection bit for BDs and interrupt circular tables: • The RxBDs of all the channels that use a particular interrupt table must reside on the same bus (60x or local). • All TxBDs must reside on the same bus (60x or local). Description 5 6 TC2 DTB 7 BDB MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-10 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.3.2 Channel-Specific Transparent Parameters Table 29-6. Channel-Specific Parameters for Transparent Operation Table 29-6 describes channel-specific parameters for transparent operation. Offset1 0x00 Name TSTATE Width Description Word Tx internal state. To start a transmitter channel the user must write to TSTATE 0xHH80_0000. HH is the TSTATE high byte described in Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” Word Zero-insertion machine state.(User-initialized to 0x10000207 for regular channel, and 0x30000207 for inverted channel) Word Zero-insertion high word data buffer (User-initialized to 0xFFFFFFFF) Word Zero-insertion low word data buffer (User-initialized to 0xFFFFFFFF) 0x04 0x08 0x0C 0x10 0x12 0x14 0x18 0x1A 0x1C 0x20 ZISTATE ZIDATA0 ZIDATA1 TBDFlags Hword TxDB flags, used by the CP (read-only for the user) TBDCNT TBDPTR INTMSK CHAMR — RSTATE Hword Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Word Tx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) Hword Channel’s interrupt mask flag. See Section 29.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES.” Hword Channel mode register. See Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.” Word Reserved Word Rx internal state. To start a receiver channel the user must write to RSTATE 0xHH80_0000. HH is the RSTATE high byte described in Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” Word Zero-deletion machine state. Initialize ZDSTATE as in the following table: ZDSTATE Initial Programmed Value 0x24 ZDSTATE Channel Type RCVSYNC If pattern synchronization is used (CHAMR[SYNC] = 1x), then… Regular 0bxxxx_xxxx_xxxx_xxx0 0bxxxx_xxxx_xxxx_xxx1 Inverted 0bxxxx_xxxx_xxxx_xxx0 0bxxxx_xxxx_xxxx_xxx1 0x00FF_FFE0 0x0000_0000 0x20FF_FFE0 0x2000_0000 If pattern synchronization is not used (CHAMR[SYNC] = 00), then… Regular Inverted 0x28 0x2C ZDDATA0 ZDDATA1 0x0000 0x0000 0x50FF_FFE0 0x70FF_FFE0 Word Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF) Word Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-11 Multi-Channel Controllers (MCCs) Table 29-6. Channel-Specific Parameters for Transparent Operation (continued) Offset1 0x30 0x32 0x34 0x38 Name Width Description RBDFlags Hword RxBD flags, used by the CP (read-only for the user) RBDCNT RBDPTR TMRBLR Hword Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Word Rx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) Hword Transparent maximum receive buffer length. Defines the maximum number of bytes written to a receiver buffer before moving to the next buffer for the respective channel. This value must be 8 byte aligned. 0x3A RCVSYNC Hword Receive synchronization pattern. Defines the synchronization pattern when CHAMR[SYNC] is 0b1x. The two bytes are checked in reverse order (byte from address 0x3B first and byte from address 0x3A last). Non-inverted data is used for synchronization even if the channel is programmed to invert the data. Clear RCVSYNC when CHAMR[SYNC] = 0b0x. — Word Reserved 0x3C 1 The offset is relative to dual-port RAM address 64*CH_NUM 29.3.2.1 Internal Transmitter State (TSTATE)—Transparent Mode In transparent mode, TSTATE functions the same as in HDLC mode. For a description, refer to Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” 29.3.2.2 Interrupt Mask (INTMSK)—Transparent Mode In transparent mode, INTMSK functions the same as in HDLC mode. For a description, refer to Section 29.3.2.2. 29.3.2.3 Channel Mode Register (CHAMR)—Transparent Mode Figure 29-6 shows the user-initialized channel mode register, CHAMR, for transparent mode. For channels that are used in conjunction with CES functionality, the user should refer to Section 29.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 Field MODE POL Reset R/W Offset 1 1 EP RD SYNC — R/W 0x1A — TS RQN — Figure 29-6. Channel Mode Register (CHAMR)—Transparent Mode MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-12 Freescale Semiconductor Multi-Channel Controllers (MCCs) CHAMR fields are described in Table 29-4. Table 29-7. CHAMR Field Descriptions—Transparent Mode Bits 0 Name MODE Description Channel mode. Selects either HDLC or transparent mode. 0 Transparent mode. 1 HDLC mode Enable polling. POL enables the transmitter to poll the TxBDs. 0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD). 1 Polling is enabled. POL is used to optimize the use of the external bus. Software should always set POL at the beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the end of a multi-frame transmission). To prevent a significant number of useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Must be set. Empty polarity and enable polling. 0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only if POL is set. 1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs disregarding the value of POL. 0 Normal bit order (transmit/receive the lsb of each octet first) 1 Reversed bit order (transmit/receive the msb of each octet first) Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode. SYNC 00 Receive Transmit None None Description Transmitter and receiver operate with no synchronization algorithm. RCVSYNC should be cleared or erroneous behavior may occur. If data synchronization is not used, the beginning of receive data may contain an arbitrary amount of bytes before actual data appears in the receive buffer. These unrelated bytes can be data or idles that were in the receive FIFO when reception began or can be data that was on the line previous to the arrival of the intended data. The first data is sent/received in the slot defined in the slot assignment table (for super channels only). RCVSYNC should be cleared or received data may be shifted. Receive data synchronization uses an 8-bit pattern specified by the 8 msb of RCVSYNC. The sync bytes are not written to the receive buffer. Receive data synchronization uses a 16-bit pattern specified by RCVSYNC. The first byte of the sync pattern will not be written to the receive buffer. The second byte of the sync pattern will be written to the receive buffer (first and second represent the order in which the two bytes of the sync pattern are received on the serial channel). 1 POL 2–3 4 0b11 EP 5 6–7 RD SYNC 01 Slot Slot 10 8-bit None 11 16-bit None 8–9 — Reserved, must be cleared. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-13 Multi-Channel Controllers (MCCs) Table 29-7. CHAMR Field Descriptions—Transparent Mode (continued) Bits 10 Name TS Description Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is any number larger than 0). Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. Reserved, must be cleared. 11–12 RQN 13–15 — 29.3.2.4 Internal Receiver State (RSTATE)—Transparent Mode In transparent mode, RSTATE functions the same as in HDLC mode. For a description, refer to Section 29.3.1.4. 29.3.3 MCC Parameters for AAL1 CES Usage When using AAL1 CES, the structured and unstructured data are transferred between the ATM and MCC automatically without CPU intervention. Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.” The following subsections describe the additional parameters required for AAL1 CES. 29.3.3.1 Channel-Specific Parameters—AAL1 CES The following are changes that occur in the channel-specific parameter RAM when using AAL1 CES. Table 29-8 describes the additional global MCC parameters specific to CES operation. Table 29-8. CES-Specific Global MCC Parameters Offset1 0x00 Name CATB Width Hword Description CES adaptive threshold tables base address. Points to the dual-port RAM area containing the CES slip control thresholds and the adaptive counter See Section 32.5, “ATM-to-TDM Adaptive Slip Control.” Should be 8-byte aligned (8 octets for each AAL1-MCC channel). User-defined and should match the CATB value programmed in the AAL-1 parameter RAM; see Section 32.8.1, “AAL1 CES Parameter RAM.” Reserved, should be cleared during initialization. Underrun template address for TDMx. Points to the dual-port RAM area containing the user-defined template to be sent during an MCC transmitter pre-underrun condition. 0x02 0x04, 0x08, 0x0C, 0x10 0x06, 0x0A, 0x0E, 0x12 1 — UTAa, UTAb, UTAc, UTAd, UTSa, UTSb, UTSc, UTSd, Hword Hword Hword Underrun template size for TDMx. This is the size in bytes of the underrun template buffer. The offset to the CES-specific global MCC parameter RAM for MCC1 is 0x8780. For MCC2, it is 0x8880. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-14 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.3.3.1.1 Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES Interrupt circular table entries contain information about channel-specific events. The interrupt mask (INTMSK) provides bits for enabling/disabling the reporting of each possible event defined in the interrupt circular table entry. Note that two CES-related interrupts provide slip indications for the MCC transmitter; these interrupts are reflected in both the interrupt circular table entries and the INTMSK fields. They are described in Table 29-19. 0 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Entry INTMSK — — SLIPE SLIPS UN TXB — — NID IDL MRF RXF BSY RXB Mask Bits CES Mask Bits Mask Bits Figure 29-7. INTMSK Mask Bits To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and no new entry is written in the interrupt circular table. The user must initialize INTMSK prior to operation. Reserved bits are cleared. 29.3.3.2 Channel Mode Register (CHAMR)—AAL1 CES Figure 29-6 shows the user-initialized channel mode register, CHAMR, for CES operation. It is the same as the CHAMR in transparent mode with three extra CES fields in bits 13–15. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field MODE Reset R/W Offset POL 1 1 EP RD SYNC — R/W 0x1A — TS RQN CESM UDC UTM Figure 29-8. Channel Mode Register (CHAMR)—CES Mode The CHAMR in CES mode fields are described in Table 29-7. Table 29-9. CHAMR Field Descriptions—CES Mode Bits 0 Name Description MODE Channel mode. Selects either HDLC or transparent mode. Must be cleared for CES operation. 0 Transparent mode. 1 HDLC mode POL Enable polling. POL enables the transmitter to poll the TxBDs. 0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD). 1 Polling is enabled. POL is used to optimize the use of the external bus. Software should always set POL at the beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the end of a multi-frame transmission). To prevent a significant number of useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. 1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-15 Multi-Channel Controllers (MCCs) Table 29-9. CHAMR Field Descriptions—CES Mode (continued) Bits 2–3 4 Name 0b11 EP Must be set. Empty polarity and enable polling. 0 The E bit in the RxBD is handled in positive logic (1 = empty; 0 = not empty). Polling occurs only if POL is set. 1 The E bit in the RxBD is handled in negative logic (0 = empty, 1 = not empty). Polling occurs disregarding the value of POL. 0 Normal bit order (transmit/receive the lsb of each octet first) 1 Reversed bit order to be reversed (transmit/receive the msb of each octet first). Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode. SYNC 00 01 10 Receive Transmit None Slot 8-bit None Slot None Description Transmitter and receiver operate with no synchronization algorithm The first data is sent/received in the slot defined in the slot assignment table (for super channels only) Receive data synchronization uses an 8-bit pattern specified by the 8 msb of RCVSYNC. The sync bytes will not be written to the receive buffer Receive data synchronization uses a 16-bit pattern specified by RCVSYNC. The first byte of the sync pattern will not be written to the receive buffer. The second byte of the sync pattern will be written to the receive buffer (first and second represent the order in which the two bytes of the sync pattern are received on the serial channel). Description 5 6–7 RD SYNC 11 16-bit None 8–9 10 — TS Reserved, should be cleared during initialization. Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4 (N is any number larger than 0). Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0 01 Queue number 1 10 Queue number 2 11 Queue number 3 Circuit emulation service mode. 0 Normal mode 1 CES mode User-defined cell support. 0 User-defined ATM cells are not supported. 1 User-defined ATM cells are supported. Underrun template mode. 0 Retransmit the last buffer. 1 Send the user-defined template. 11–12 RQN 13 CESM 14 UDC 15 UTM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-16 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.3.4 Channel-Specific SS7 Parameters Based on the HDLC protocol, the signalling system #7 (SS7) protocol is used to manage public service networks. The SS7 protocol operates on signal units (SU), which are analogous to HDLC frames. The physical, data link, and network layer functions of the SS7 protocol are called the message transfer part (MTP). Implementing the MTP layer 2 (data link) functions in host software is difficult with multiple performance issues. The MPC8280 SS7 microcode enables applications requiring multi-channel SS7 processing. The SS7 controller is implemented using the MCC hardware with microcode running on the CPM. Each MCC implements the following layer 2 portions of the MTP: • Signal unit (SU) retransmission • Automatic fill-in signal unit (FISU) transmission • Short SU filtering • Duplicate fill-in and link-status signal unit (FISU/LSSU) filtering • Octet counting • Signal unit error rate monitoring • Good frame counter and bad frame counting • Initial alignment (supports alignment error rate monitoring) Host software, however, is needed to handle the following higher-level functions of the MTP layer 2 not supported by the SS7 controller: • Link state control • Flow control SS7 features are as follows: • Up to 128 independent communication channels (64 channels per MCC) • Independent mapping for receive and transmit • Standard HDLC features — Flag/Abort/Idle generation/detection — Zero insertion/deletion — 16-bit CRC-CCITT generation/checking — Detection of non-octet aligned signal units — Programmable number of flags between signal units • Maintenance of signal unit error monitor (SUERM) • Maintenance of alignment error rate monitor (AERM) • Maintenance of separate counters for error-free and bad frames • Detection and stripping of long signal units • Discard of short signal units (less than 5 octets) • Transmission of signal units with a programmable delay (applies to JT-Q.703 standard) • Automatic transmission of fill-in signal units (FISU) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-17 Multi-Channel Controllers (MCCs) • • • • • • • • • • Automatic retransmission of signal units (for link-status signal unit (LSSU) retransmission) Automatic discard of identical FISUs and LSSUs using a user-defined mask Octet counting mode in case of long signal units and receiver overrun Five circular interrupt tables with programmable size and overflow identification—one for transmit and four for receive. Global or individual channel loop modes Efficient bus usage (no bus usage for inactive channels or for active channels with nothing to send) Efficient control of interrupts to the CPU Supports external BD tables Uses on-chip dual-port RAM for parameter storage Uses 64-bit data transactions for reading and writing data in BDs Table 29-10 describes channel-specific parameters for SS7. Note that a given parameter location may have a different definition depending on the standard used (ITU-T/ANSI or Japanese standard). Table 29-10. Channel-Specific Parameters for SS7 Offset1 0x00 0x04 Name2 TSTATE ZISTATE Width Word Word Description Tx internal state. The user must write to TSTATE 0xHH80_0000. HH is the TSTATE High Byte. Refer to Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” Zero-insertion machine state. User-initialized to one of the following values: 0x10000207 for regular channel transmitting all 1s before first frame of data 0x00000207 for regular channel transmitting flags before first frame of data 0x30000207 for inverted channel transmitting all 1s before first frame of data 0x20000207 for inverted channel transmitting flags before first frame of data Note: Used in conjunction with ZIDATA0 and ZIDATA1. Zero-insertion high word data buffer. User-initialized to one of the following values: 0xFFFFFFFF allows transmission of all 1s before first frame of data 0x7E7E7E7E allows transmission of flags before first frame of data Note: Used in conjunction with ZISTATE and ZIDATA1. Zero-insertion low word data buffer. User-initialized to one of the following values: 0xFFFFFFFF allows transmission of all 1s before first frame of data 0x7E7E7E7E allows transmission of flags before first frame of data Note: Used in conjunction with ZISTATE and ZIDATA0. TxBD flags, used by the CP (read-only for the user) Tx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Tx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) Extended channel mode register. See 29.3.4.1, “Extended Channel Mode Register (ECHAMR)—SS7 Mode.” Temporary transmit CRC. Temporary value of CRC calculation result, used by the CP (read-only for the user) 0x08 ZIDATA0 Word 0x0C ZIDATA1 Word 0x10 0x12 0x14 0x18 0x1C TBDFlags TBDCNT TBDPTR ECHAMR TCRC Hword Hword Word Word Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-18 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-10. Channel-Specific Parameters for SS7 (continued) Offset1 0x20 Name2 RSTATE Width Word Description Rx internal state. To start a receiver channel the user must write to RSTATE 0xHH80_0000. HH is the RSTATE High Byte. Refer to Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” Zero-deletion machine state (User-initialized to 0x00FFFFE0 for regular channel, and 0x20FFFFE0 for reversed bit order channel) Zero-deletion high word data buffer (User-initialized to 0xFFFFFFFF) Zero-deletion low word data buffer (User-initialized to 0xFFFFFFFF) RxBD flags, used by the CP (read-only for the user) Rx internal byte count. Number of remaining bytes in buffer, used by the CP (read-only for the user) Rx internal data pointer. Points to current absolute data address of channel, used by the CP (read-only for the user) Maximum frame length register. Defines the longest expected frame for this channel. (64-Kbyte maximum). The remainder of a frame that is larger than MFLR is discarded and the LG flag is set in the last frame’s BD. An interrupt request might be generated (RXF and RXB) depending on the interrupt mask. A frame’s length is considered to be everything between flags, including CRC. No more data is written into the current buffer when the MFLR violation is detected. Max_length counter, used by the CP (read-only for the user) Temporary receive CRC, used by the CP (read-only for the user) Applies to ITU-T/ANSI SS7 only. Interrupt threshold in octet counting mode (N=16). See Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode Applies to ITU-T/ANSI SS7 only. Temporary down counter for N (user initialized to the value of N). Applies to Japanese SS7 only. Temporary storage for Time-Stamp Register Value. Used by the CP to implement a 24-ms delay before sending FISU. Signal unit to signal unit error ratio (SUERM parameter, user initialized to 256). See Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode Applies to ITU-T/ANSI SS7 only. Temporary down-counter for D (user initialized to the value of D). D_cnt is decremented only when receive buffers are available. Applies to Japanese SS7 only. FISU retransmission delay (specified in units of 512¨µs). According to the Japanese SS7 standard, the delay should be 24 ms and thus JTTDelay should be programmed to 24 ms/512 µs = 46.875 (approximately 47). Hence, the user should program JTTDelay to 0x2F and the RTSCR to generate a 1 µs time stamp period. Refer to Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR)”. Word Hword Hword Word Mask for SU filtering, bytes 0-3. See 29.3.4.4, “SU Filtering—SS7 Mode Mask for SU filtering, byte 4. See 29.3.4.4, “SU Filtering—SS7 Mode SS7 configuration register. See Section 29.3.4.3, “SS7 Configuration Register—SS7 Mode.” Temporary storage, used by CP for SU filtering. 0x24 0x28 0x2C 0x30 0x32 0x34 0x38 ZDSTATE ZDDATA0 ZDDATA1 RBDFlags RBDCNT RBDPTR MFLR Word Word Word Hword Hword Word Hword 0x3A 0x3C 0x40 MAX_cnt RCRC N N_cnt JTSTTmp Hword Word Hword Hword Word Hword Hword 0x44 0x46 D D_cnt JTTDelay 0x48 0x4C 0x4E 0x50 Mask1 Mask2 SS7_OPT LRB1_Tmp MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-19 Multi-Channel Controllers (MCCs) Table 29-10. Channel-Specific Parameters for SS7 (continued) Offset1 0x54 0x56 0x58 0x5C 0x5E 0x60 0x64 0x68 Name2 LRB2_Tmp SUERM LRB1 LRB2 T LHDR Width Hword Hword Word Hword Hword Word Description Temporary storage, used by CP for SU filtering. Signal unit error rate monitor counter (user initialized to 0). See Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode.” Four first bytes of last received signal unit. Used by CP for SU filtering. See 29.3.4.4, “SU Filtering—SS7 Mode.” Fifth byte of last received signal unit. Used by CP for SU filtering. See 29.3.4.4, “SU Filtering—SS7 Mode SUERM threshold value (user initialized to 64). See Section 29.3.4.2, “Signal Unit Error Monitor (SUERM)—SS7 Mode.” The BSN, BIB, FSN, FIB fields of last transmitted signal unit and result of CRC. Used by CP for automatic FISU transmission. Temporary storage, used by CP for automatic FISU transmission. Error-free signal unit counter, user initialized to 0. The counter is incremented whenever an error-free (no CRC error, no non-octet aligned error, no short or long frame errors) signal unit is received. Signal unit error counter, user initialized to 0. Incremented each time an SU is received that contains an error. These errors are: short frame, long frame, CRC error, and non-octet aligned error. Internal state of SS7 controller, user initialized to 0. Temporary storage for time-stamp register value. Applies to Japanese SS7 only; otherwise should be cleared. Used by the CP to implement the 24-ms delay for signal unit error rate monitoring in Japanese SS7. FISU transmit delay (specified in units of 512us). Applies to Japanese SS7 only; otherwise should be cleared. According to the Japanese SS7 standard, the delay should be 24 ms and thus JTRDelay should be programmed to 24 ms/512 µs = 46.875 (approximately 47). Hence, the user should program JTRDelay to 0x2F and the RTSCR to generate a 1 µs time stamp period. Refer to Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR)”. ITU threshold for AERM. If M_cnt reaches M, an AERM interrupt is generated. Note that M is normally programmed to 5. Up-counter for M. Should be cleared during initialization. LHDR_Tmp Word EFSUC Word 0x6C SUEC Word 0x70 0x74 SS7STATE JTSRTmp Word Word 0x78 JTRDelay Hword 0x7A 0x7C 1 M M_cnt Hword Hword The offset is relative to the dual-port RAM address + 64*CH_NUM. SS7 channel specific parameters require twice the amount of dual-port RAM required for HDLC or Transparent channel specific parameters. Therefore for SS7 even channel numbers (0, 2, 4, etc.) must be used and odd channel number must be left unused. 2 Items in boldface must be initialized by the user. Unless otherwise stated, all other items are managed by microcode and should be initialized to zero. 29.3.4.1 Extended Channel Mode Register (ECHAMR)—SS7 Mode The extended channel mode register (ECHAMR) is a user-initialized register, shown in Figure 29-9 It includes both the interrupt mask bits and channel configuration bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-20 Freescale Semiconductor Multi-Channel Controllers (MCCs) The interrupt mask provides bits for enabling/disabling each event defined in the interrupt circular table entry. Other bits provide various channel configuration options. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field MODE0 Reset R/W Offset 16 — OCT SUERM FISU — UN TXB — AERM NID IDL MRF RXF BSY RXB No reset value R/W 0x18 17 18 19 20 25 26 27 28 29 31 Field MODE1 POL Reset R/W Offset 1 IDLM — No reset value R/W 0x1A TS RQN NOF Figure 29-9. Extended Channel Mode Register (ECHAMR) ECHAMR fields are described in Table 29-11. Table 29-11. ECHAMR Fields Description Bits 0,16 Name MODE0 MODE1 00 01 10 11 Description Transparent mode HDLC mode Reserved SS7 mode (This is the required bit setting for an MCC to perform SS7.) 1, 5, 8 2–4 6–7 9–15 17 0 Reserved, should be cleared during initialization. INTMSK Interrupt mask bits. These bits are used for enabling/disabling the reporting of each possible event defined in the interrupt circular table entry. See Section 29.8.1.1, “Interrupt Circular Table Entry.” 0 Disabled 1 Enable POL Enable polling. POL enables the transmitter to poll the TxBDs. 0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD). 1 Polling is enabled. POL is used to optimize the use of the external bus. Software should always set POL at the beginning of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the end of a multi-frame transmission). To prevent a significant number of useless transactions on the external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before enabling polling. Reserved, must be set. 18 1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-21 Multi-Channel Controllers (MCCs) Table 29-11. ECHAMR Fields Description (continued) Bits 19 Name IDLM Description Idle mode. 0 No idle patterns are transmitted between frames. After transmitting NOF+1 flags, the transmitter starts sending the data of the frame. If the transmission is between frames and the frame buffers are not ready, the transmitter sends flags until it can start transmitting the data received for SS7 operation. 1 At least one idle pattern is sent between adjacent frames. The NOF value shall be no smaller than the PAD setting, see TxBD. If NOF = 0, this is identical to flag sharing in SS7. Mode flags precede the actual data. When IDLM = 1, at least one idle pattern is sent between adjacent frames. If the transmission is between frames and the frame buffer is not ready, the transmitter sends idle characters. When data is ready, the NOF+1 flags are sent followed by the data frame. If IDLE mode is selected and NOF = 1, the following sequence is sent: ......init value, FF, FF, flag, flag, data, ........ The init value before the idle will be ones. Reserved, should be cleared during initialization. Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*n-4 (n is any integer larger than 0). Receive queue number. Specifies the receive interrupt queue number. 00 Queue number 0. 01 Queue number 1. 10 Queue number 2. 11 Queue number 3. Number of flags. NOF defines the minimum number of flags before frames: 000 - at least 1 flag 001 - at least 2 flags .... 111 - at least 8 flags 20–25 10 — TS 11–12 RQN 13–15 NOF Note that items in bold must be initialized by the user. 29.3.4.2 Signal Unit Error Monitor (SUERM)—SS7 Mode The microcode maintains the signal unit error rate monitor as described in ITU-T Q.703 paragraph 10, and ANSI T1.111-1996 paragraph 10. The microcode uses SUERM, N, N_cnt, D, D_cnt and T parameters for the leaky-bucket implementation of the SU error monitor. • After every N octets received while in octet counting mode, SUERM is incremented and an interrupt request can be generated (SUERM) depending on the interrupt mask. • After D error-free frames have been received, SUERM is decremented. SUERM will not be decremented below zero. • If SUERM reaches T, the SUERM is cleared and an interrupt is generated. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-22 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.3.4.2.1 SUERM in Japanese SS7 The Japanese SS7 uses a time interval to monitor errors. If an error is present, it checks every 24 ms. • An error flag is set that indicates whether current frame is errored or not. • For every JTRDelay an error flag is checked. • If there is no error, decrement the counter SUERM by 1 (not below zero). • If there is an error, increment the counter SUERM by D. • If SUERM reaches T, the counter SUERM is cleared and a “signal unit error rate monitor” interrupt is generated. Table 29-12. Parameter Values for SUERM in Japanese SS7 Parameter T D JTRDelay Threshold Upcount Length of interval (24ms) Definition Value 285 16 0x2F 29.3.4.3 SS7 Configuration Register—SS7 Mode The SS7 configuration register, shown on Figure 29-10 contains additional SS7 parameters. 0 3 4 5 6 7 8 9 10 11 12 15 Field Reset R/W — AERM SUERM_DIS STD SF_DIS SU_FIL SEN_FIS O_ORN O_ITUT FISU_PAD R/W Figure 29-10. SS7 Configuration Register (SS7_OPT) Table 29-13 describes SS7 configuration register fields. Table 29-13. SS7 Configuration Register Fields Description Bits 0–3 4 Name — AERM Description Reserved, should be cleared during initialization. Alignment error rate monitor enable. See Section 29.3.4.3.1, “AERM Implementation.” 0 Do not enable AERM. 1 Enable AERM. Disable the SU error rate monitor. See Section 29.3.4.3.3, “Disabling SUERM.” 0 Enable SUERM. 1 Disables both SUERM and AERM. Standard compliance 0 ITU-T/ANSI compliant 1 Japanese SS7 compliant Discard short frames (less than 5 octets) 0 Do not discard short frames. 1 Discard short frames. 5 SUERM_DIS 6 STD 7 SF_DIS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-23 Multi-Channel Controllers (MCCs) Table 29-13. SS7 Configuration Register Fields Description (continued) Bits 8 Name SU_FIL SU Filtering 0 Disable SU filtering. 1 Enable SU filtering. Send FISU if first BD of frame is not ready. 0 Flags are sent if the current BD, which is the first BD of the frame, does not have its ready bit set. 1 FISUs are automatically sent if the current BD, which is the first BD of the frame, does not have its ready bit set. Enter octet counting mode (OCM) on overrun. Should be cleared if using the Japanese standard. 0 Disable entering OCM if there are no receive BDs available. 1 Enter OCM if there are no receive BDs available. Note that when STD = 1, O_ORN = 1, and no receive buffers are ready, a ny received signal unit is treated as an erred signal unit. Enter octet counting mode (OCM) on ITU-T conditions (after an abort sequence or when an SU is too long). Should be cleared if using the Japanese standard. 0 Disable entering OCM on ITU-T conditions. 1 Enable entering OCM on ITU-T conditions. Padding of the automatically transmitted FISUs. If the SEN_FISU bit is set, the CP will use the value of FISU_PAD as a number of pad character. Please refer to PAD parameter in Section 29.9.2, “Transmit Buffer Descriptor (TxBD).” Description 9 SEN_FIS 10 O_ORN 11 O_ITUT 12–15 FISU_PAD 29.3.4.3.1 AERM Implementation The SS7 microcode implements the ITU Q.703 alignment error rate monitor (AERM). The microcode uses the T, SUERM, M and M_cnt parameters. The M_cnt parameter is incremented for every T errored frames. If M_cnt reaches M, an AERM interrupt is generated to layer 3. Note that in AERM mode no SUERM interrupt is generated. Also, the algorithm associated with D and D_cnt is disabled as per the ITU specification. 29.3.4.3.2 AERM in Japanese SS7 To meet the Japanese AERM requirements the user must change the parameters T and D. Note that the interrupt generated is not AERM but SUERM. During proving, do the following: 1. Set SS7_OPT register to 0b0000 001X XX00 XXXX. The value of X doesn’t matter because these bits do not affect the operation of the error counter. 2. Clear JTRdelay parameter to'0.' 3. Set parameters T (threshold) and D (up counter) to'1.' 4. Clear parameter SUERM (error counter) to'0.' 5. Set JTTDelay to value required to generate 24ms delay. These settings allow FISU or LSSU transmission to be delayed by the required 24ms (JTTDelay). They also allow the correct operation of the JT Q703 error counter and ensure that an SUERM interrupt is generated on the first SU received in error. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-24 Freescale Semiconductor Multi-Channel Controllers (MCCs) After proving period, set the parameters (T and D) to values according to the Japanese SUERM. See section Table 29-12. To disable AERM and enter SUERM, do the following: 1. Set SUERM_DIS bit in SS7_OPT. 2. Set parameters (T, D & SUERM) for Japanese SUERM. 3. Clear SUERM_DIS bit in SS7_OPT. 29.3.4.3.3 Disabling SUERM When SS7_OPT[SUERM_DIS] is set, the N_cnt and D_cnt parameters are not decremented by the microcode and no SUERM interrupt is generated. This allows these parameters to be updated, for example, at the end of the proving period in alignment error monitoring. Note: If the SS7 controller is in the octet counting mode (OCM) when SUERM_DIS is set, then if no idles (only flags/data) are received while SUERM_DIS is set, then after the host updates N_cnt and D_cnt and clears SUERM_DIS the receiver will start in OCM. However if SUERM_DIS is set while in OCM and idles are then received then the OCM state is left. 29.3.4.4 SU Filtering—SS7 Mode To reduce the overhead to the user software, a filtering algorithm has been adopted to allow superfluous frames to be discarded. This algorithm compares the first 3–5 bytes (depending on the type) of the current FISU or LSSU to the last SU received and discards the current SU if it has already been received twice. 29.3.4.4.1 Comparison Mask A user programmable 5-byte mask exists in the parameter RAM map. When an SU is received, the controller checks the contents of the LI field. If LI is between 0 and 2, the SU (except for the CRC portion) will be masked according to the user programmable mask and will then be compared to the last SU received. The state machine for the matching algorithm is in Subsection 29.3.4.4.2, “Comparison State Machine”. The Mask1 and Mask2 channel-specific parameters construct the 5-byte user mask. The exact format and byte ordering are shown on Figure 29-11 and Figure 29-12. msb Byte 1 Byte 2 Byte 3 Byte 4 lsb Figure 29-11. Mask1 Format msb Reserved, should be cleared. lsb Byte 5 Figure 29-12. Mask2 Format 29.3.4.4.2 Comparison State Machine The following state machine exists for filtering. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-25 Multi-Channel Controllers (MCCs) • • • State 0—The first 3-5 bytes (depending on the contents of the LI field) are masked and then compared with the first 3-5 bytes of the last SU. If there is a match, go to State 1, else remain in State 0. The current SU will be received into a buffer descriptor. State 1—The first 3-5 bytes (depending on the contents of the LI field) are masked and then compared with the first 3-5 bytes of the last SU. If there is a match, go to State 2, else go to State 0. The current SU will be received into a buffer descriptor. State 2—The first 3-5 bytes (depending on the contents of the LI field) are masked and then compared with the first 3-5 bytes of the last SU. If there is a match, the current SU will be discarded (unless there is an error), the channel will remain in state 2 and SU error monitor will be adjusted accordingly. If the frames do not match, the current SU will be received into a buffer descriptor and the channel will return to State 0. Filtering Limitations 29.3.4.4.3 Because the algorithm is purely checking identical SUs, two FISUs will be received after each MSU rather than merely one, even though they have the same sequence numbers. Reception of an MSU resets the filtering algorithm. Also, reception of a short frame resets the filtering algorithm when SS7_OPT[SF_DIS] = 0; however, when SS7_OPT[SF_DIS] = 1 (short frames are discarded), the filtering algorithm remains unchanged. 29.3.4.4.4 Resetting the SU Filtering Mechanism This command resets the filtering algorithm to ensure that the next SU will be received, even if it would normally have been filtered. This command could be issued periodically so that the 603e core can check to make sure that the link is really up and not simply receiving flags. To issue this MCC command, refer to Section 14.4, “Command Set.” Use opcode 1110 (0xE). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-26 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.3.4.5 Octet Counting Mode—SS7 Mode When entering the octet counting mode (OCM), the CP will load the user defined N register to its internal octet counter. While in the octet counting mode the CP will decrement its internal counter for every unstuffed octet received. When the internal counter is decremented to zero, the CP increment the SUERM register and reload the N register into the internal count register. In addition an interrupt (OCT) might be generated depending on the interrupt mask. The SS7 controller will enter octet counting mode under the following circumstances: • An ABORT character is received at any time and SS7_OPT[O_ITUT] is set. • The SU currently being received has exceeded the length programmed in the MFLR register and SS7_OPT[O_ITUT] is set. • The receiver overruns and SS7_OPT[O_ORN] is set. Note that when no receive buffers are available, only octets are counted; that is, D_cnt is not decremented after receiving the frame. The SS7 controller will leave octet counting mode when a valid signal unit is detected (with a valid CRC and a length less than MFLR and greater than 4). NOTE Octet counting mode applies only to the ITU-T and ANSI standards. The SS7 microcode will not work if both the Japanese standard and OCM features are selected. 29.4 Channel Extra Parameters In addition to the information kept in the channel-specific parameter ram, a channel also has a set of pointers used to index its transmit and receive buffer descriptors. This information is kept in a set of channel-extra parameters. Table 29-14 describes the channel-extra parameters. These parameters are indexed using the channel number, as described in the table. Table 29-14. Channel Extra Parameters Offset1 0x00 0x02 Name Width Description TBASE Hword TxBD base address. Used to calculate offset of the channel’s TxBD table relative to the MCCBASE (The base address of the BD table for this channel MCCBASE+8*TBASE) TBPTR Hword TxBD pointer. Used to calculate offset of the current BD relative to the MCCBASE. TBPTR is user-initialized to TBASE before enabling the channel or after a fatal error before reinitializing the channel. (The address of the BD in use for this channel MCCBASE+8*TBPTR) RBASE Hword RxBD base address. Used to calculate offset of the channel’s RxBD table relative to the MCCBASE. (The base address of the BD table for this channel MCCBASE+8*RBASE) RBPTR Hword RxBD pointer. Used to calculate offset of the current BD relative to the MCCBASE. RBPTR is user-initialized to RBASE before enabling the channel or after a fatal error before reinitializing the channel. (The address of the BD in use for this channel MCCBASE+8*RTBPTR) 0x04 0x06 1 The offset relative to dual-port RAM base address + XTRABASE + 8*CH_NUM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-27 Multi-Channel Controllers (MCCs) 29.5 Superchannels A TDM may not be programmed to contiguously transmit more than one byte of data from the same MCC channel. This is true whether the user wants to program more than one byte in the same SI entry or have back-to-back SI entries for the same channel. Instead, superchannelling is used to achieve sending multiple back-to-back bytes from the same MCC channel. Refer to Section 15.4.3, “Programming SIx RAM Entries,” for information about how to program SIRAM entries as superchannelled timeslots. A single MCC channel is the combination of one MCC FIFO and one set of related channel parameters and buffer descriptors. A superchannel is the combination of multiple MCC TX channels’ FIFOs and one set of an MCC channel’s parameters and buffer descriptors. In this case, the one set of parameters and buffer descriptors is used to manage this group of FIFOs. In effect, this provides the ability to construct a larger overall FIFO than that of a single normal MCC TX channel. MCC TX channels whose numbers appear in superchannelled SIRAM entries are dedicating their TX FIFOs to that superchannel and may not be used for any other purpose (i.e. cannot also be used elsewhere in a TDM as a normal channel). The FIFO of the channel whose parameters are used to control a superchannel may still be used as part of the superchannel. Although a timeslot for a normal MCC channel may be of any length up to 8 bits, a superchannelled timeslot must always be 8 bits. Although a normal MCC transmit FIFO is 4 bytes, one that is used as part of a superchannel is 2 bytes. Note that an MCC channel whose FIFO is in superchannel mode consumes twice as much CPM bandwidth as a normal channel. 29.5.1 Superchannel Table When the SI encounters an SIRAM entry that is programmed to be part of a superchannel, the channel number in that SIRAM entry represents which MCC channel’s FIFO is to be used during that timeslot. Later, when that FIFO requires service from the CPM, a lookup occurs using the Superchannel Table (SCT). The SCT serves as a mapping between the FIFOs being used as part of a superchannel (as programmed in SIRAM) and which channel’s parameters are being used to manage that superchannel. The MCC channel FIFO number used in the MCSEL field of the superchannelled SIRAM entry is used to calculate an offset to a superchannel table entry that contains the MCC channel number whose parameters and buffer descriptors are being used to control that superchannel (see Figure 29-13). The only entries in the superchannel table which must be initialized are those whose numbers appear in superchannelled entries in the SIRAM. 0 1 2 9 10 11 12 13 14 15 Field Addr 0 0 Channel Number 0 0 0 0 0 0 DPRAM_base_address+SCTPBASE+2*MCC_FIFO_number (MCC_FIFO_number is the number written in the MCSEL field of the corresponding SI RAM entry) Figure 29-13. Super Channel Table Entry MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-28 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.5.2 Superchannels and Receiving The restrictions stated in Section 29.5 regarding using back-to-back timeslots with the same channel do not apply to the receive side of the MCC. A user does not have to mark receive timeslots as superchannelled in SIRAM programming unless transparent slot synchronization is being used (see Section 29.5.3, “Transparent Slot Synchronization”). Note that no SCT is used for the receive side and the channel numbers used when programming receive SIRAM timeslots should always be that of the actual intended MCC receive channel FIFO. A normal MCC receive FIFO is 2 bytes and a superchannelled MCC receive FIFO is 1 byte. 29.5.3 Transparent Slot Synchronization Transparent slot synchronization (TSS) is used to ensure that data transmission and reception for a transparent superchannel begins on the intended timeslot of that superchannel. It is not required that the first timeslot that appears in the SIRAM programming for a transparent superchannel be the first to send or receive when the superchannel first starts. The user indicates which timeslot in a superchannel should be the first to send or receive by programming the CNT and BYT fields of the superchannelled timeslots as described in Section 15.4.3, “Programming SIx RAM Entries.” 29.5.4 Superchannelling Programming Examples The example in Figure 29-14 shows the SI RAM programming and the super-channel table for two different transmitter superchannels running on the same TDM interface. One superchannel includes TDM timeslots 1, 6, and 7, which also happen to be programmed to use MCC FIFO numbers 1, 6, and 7. The second superchannel in this example is comprised of timeslots 2, 3, and 4 using MCC FIFOs 2, 3, and 4. This approach of using a FIFO number which is the same as the timeslot number is arbitrary and no a requirement. Note that entries in the superchannel table for MCC FIFOs 1, 6 and 7 all are programmed to point to the channel-specific and channel-extra parameters for channel 1. Superchannel table entries for MCC FIFOs 2, 3 and 4 are programmed such that these FIFOs are managed by the parameters of channel 2. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-29 Multi-Channel Controllers (MCCs) SI RAM 0 MCC 1 2 3–10 MCSEL 11–13 CNT 14 BYT 15 LST Super Channel Table 0–1 2–9 CHANNEL NO DPRAM_Base + SCTPBASE + 0x0 0x01 0x01 0x72 0x72 0x0 0x72 0x72 0x0 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE 0x10 — 0x1 0x2 0x2 0x2 — 0x1 0x1 — 10–15 LOOP SUPER SI RAM Address 1 1 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 First slot of the super channel Regular (not first) slot of the super channel . The super channel BD tables are associated with channels 1 and 2 (no BD tables are necessary for channels 3, 4, 6, and 7) Figure 29-14. Transmitter Super Channel Example In this example, data is expected to be sent on the first timeslots allocated for each superchannel. Thus for the first superchannel, timeslot 1 has CNT=0 and BYT=1, the “first byte” condition described in Table 15-2 and the remaining timeslots that are part of this superchannel—timeslots 6 and 7, have CNT=0x7 and BYT=1. This indicates to the MCC that when this transparent superchannel becomes active it should begin sending data on timeslot 1. If the application required that data not be sent on this superchannel until timeslot 7, for example, then timeslots 1 and 6 have CNT=0x7 and BYT=1 and timeslot 7 would be programmed with CNT=0 and BYT=1. Similarly, the second superchannel in this example sends data beginning with its first timeslot, timeslot 2. It contains the “first byte” condition of CNT=0 and BYT=1. If the application required a different timeslot in this superchannel, either timeslot 3 or 4, that channel could be programmed to have the “first byte” condition instead. Figure 29-15 shows the SI RAM programming for transparent receiver superchannels which uses the slot synchronization. This example assumes a timeslot configuration similar to the transmit example in Figure 29-14. For this receive example, to guarantee that reception begins on the first timeslots for each superchannel, all timeslots that correspond to superchannels are programmed as superchannelled timeslots and the first timeslot for each superchannel is programmed with the “first byte” CNT and BYT conditions. Note that the receive examples do not include a superchannel table because a superchannel table is only used on the transmit side. Receive SIRAM entries should always be programmed using the FIFO number MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-30 Freescale Semiconductor Multi-Channel Controllers (MCCs) of the managing MCC channel for that superchannel (the same MCC channel number used in the superchannel table entries corresponding to the transmit FIFOs for that superchannel). SI RAM 0 MCC 1 2 3–10 MCSEL 11–13 CNT 14 BYT 15 LST LOOP SUPER SI RAM Address 1 1 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0x0 0x1 0x2 0x2 0x2 0x5 0x1 0x1 0x8 0x0 0x01 0x01 0x72 0x72 0x0 0x72 0x72 0x0 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 Regular Channel Super Channel 1 Super Channel 2 Super Channel 2 Super Channel 2 Regular Channel Super Channel 1 Super Channel 1 Regular Channel First slot of the super channel Regular (not first) slot of the super channel The super channel BD tables are associated with channels 1 and 2 Figure 29-15. Receiver Super Channel with Slot Synchronization Example Figure 29-16 shows the SI RAM programming for the same overall configuration as the previous examples, but in this case it does not matter to the application what timeslot of a superchannel reception begins on. Thus, slot synchronization is not necessary and the timeslots do not need to be programmed as superchannelled timeslots and the CNT and BYT fields may be programed normally. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-31 Multi-Channel Controllers (MCCs) SI RAM 0 MCC 1 2 3–10 MCSEL 11–13 CNT 14 BYT 15 LST LOOP SUPER SI RAM Address 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x1 0x2 0x2 0x2 0x5 0x1 0x1 0x8 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 Regular Channel Super Channel 1 Super Channel 2 Super Channel 2 Super Channel 2 Regular Channel Super Channel 1 Super Channel 1 Regular Channel The super channel BD tables are associated with channels 1 and 2 Figure 29-16. Receiver Super Channel without Slot Synchronization Example 29.6 MCC Configuration Registers (MCCFx) The MCC configuration register (MCCF), shown in Figure 29-17, defines the mapping of the MCC channels to the TDM channels. MCC1 can be connected to SI1 and MCC2 can be connected to SI2. For each MCCx-SIx pair, each of the four 32 channels subgroups can be connected to one of the four TDM highways (TDMA, TDMB, TDMC, and TDMD). 0 1 2 3 4 5 6 7 Field Reset R/W Addr Group 1 Group 2 0000_0000 R/W Group 3 Group 4 0x11B38 (MCCF1), 0x11B58 (MCCF2) Figure 29-17. SI MCC Configuration Register (MCCF) Table 29-15 describes MCCF fields. Table 29-15. MCCF Field Descriptions Bits 0–1, 2–3, 4–5, 6–7 Name Description GROUP x Group x of channels is used by TDM y as shown in Table 29-16. 00 Group x is used by TDM A. 01 Group x is used by TDM B. 10 Group x is used by TDM C. 11 Group x is used by TDM D. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-32 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-16 describes group assignments. Table 29-16. Group Channel Assignments Group Group1 in MCCF11 Group2 in MCCF11 Group3 in MCCF11 Group4 in MCCF11 Group1 in MCCF2 Group2 in MCCF2 Group3 in MCCF2 Group4 in MCCF2 1 Channels 0–31 32–63 64–95 96–127 128–159 160–191 192–223 224–255 Not on the MPC8270 nor the MPC8275. NOTE The TDM group channel assignments made in MCCF must be coherent with the SI register programming and SI RAM programming; see Section 15.5, “Serial Interface Registers,” and Section 15.4.3, “Programming SIx RAM Entries.” The user must also program MCCF before enabling the TDM channel in the SIGMR; see Section 15.5.1, “SI Global Mode Registers (SIxGMR).” 29.7 MCC Commands The user starts channels by writing to the TSTATE/RSTATE registers as described in Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode,” and Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode.” The following commands, used to stop and initialize channels, are issued to the MCC by writing to CPCR as described in Section 14.4.1, “CP Command Register (CPCR).” All MCC channels must be initialized using one of the following commands before being used in an active TDM. Not all commands are available in all revisions of silicon and the user should refer to Section 14.4.1.1, “CP Commands,” for further details. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-33 Multi-Channel Controllers (MCCs) Table 29-17. MCC Commands Command 1 INIT RX AND TX Description Performs both INIT RX and INIT TX commands contiguously, using the channel number supplied with the command. Initializes MCC receive FIFOs in groups of 32 channels, starting with the channel number programmed in the CPCR[MCN] field when the command is issued. This command should only be issued when the channels are disabled. To initialize more than 32 channels, reissue the command with the appropriate channel numbers. The INIT TX AND RX command may be used to initialize both the receive and transmit sides of an MCC channel at the same time. Note that this command will initialize the first 16 FIFOs to be preloaded with 16 bits of idle, and the second set of FIFOs will be completely empty and ready for data. This is done to stagger when FIFOs require servicing and spread out CPM loading. Initializes MCC transmit FIFOs in groups of 32 channels, starting with the channel number programmed in the CPCR[MCN] field when the command is issued. This command should only be issued when the channels are disabled. To initialize more than 32 channels, reissue the command with the appropriate channel numbers. The INIT TX AND RX command may be used to initialize both the receive and transmit sides of an MCC channel at the same time. Note that this command will initialize the first 16 FIFOs to be preloaded with 16 bits of idle, and the second set of FIFOs will be preloaded with 32 bits of idle. This is done to stagger when FIFOs require servicing and spread out CPM loading. Same as regular INIT RX AND TX, except that all FIFOs are equally preloaded with idle. For applications in which all channels must begin sending or receiving data in the same TDM frame. Performs the INIT TX command but only for the channel number programmed in CPCR[MCN] as opposed to initializing 32 channels at once. Performs the INIT RX command but only for the channel number programmed in CPCR[MCN] as opposed to initializing 32 channels at once. Initializes the state machine hardware of the MCC indicated in CPCR[PAGE] and CPCR[SBC], has the same effect on the MCC block that a CPM reset does. Required after the GUN or GOV MCC event occurs. If this command is not available in the revision of silicon being used, a CPM reset is required instead. Disables the transmission on the selected channel and clears CHAMR[POL]. When this command is issued in the middle of a frame, the CP sends an ABORT indication and then idles/flags on the selected channel. If this command is issued between frames, the CP sends only idles or flags (depending on CHAMR[IDLM]). TBPTR points for the buffer that the CP was using when the STOP TRANSMIT command was issued. Forces the receiver of the selected channel to terminate reception. After this command is executed, the CP does not change the receive parameters in the dual-port RAM. The user must initialize the channel receive parameters in order to restart reception. 1 INIT RX 1 INIT TX INIT TX AND RX1 (16 BITS) INIT TX, ONE1 CHANNEL INIT R X, ONE1 CHANNEL MCC RESET STOP TRANSMIT STOP RECEIVE 1 The INIT PARAMETERS style commands are also used to reset the MCC channel FIFOs and these commands need to be issued to cover any channel number used, whether used normally or as part of a superchannel 29.8 MCC Exceptions The MCC interrupt reporting scheme has two levels. The circular interrupt tables (illustrated in Figure 29-18) report channel-specific events and are masked by each channel’s INTMSK field located in channel-specific parameter RAM. The MCCE global event register (described in Section 29.8.1, “MCC Event Register (MCCE)/Mask Register (MCCM)”) reports some global-level events and whether new activity has taken place in any of that MCC’s interrupt tables. These events can be masked by the MCCM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-34 Freescale Semiconductor Multi-Channel Controllers (MCCs) Interrupt Circular Table Entry 0 1 2–17 18–25 26–31 T/RINTBASE V=0 V=0 V=0 V=0 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=1 Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Interrupt Flags Channel Number Channel Number Channel Number Channel Number Channel Number Channel Number Channel Number Channel Number Channel Number Software Pointer V=1 V=1 T/RINTPTR V=0 V=0 V=0 Figure 29-18. Interrupt Circular Table There is one table for transmitter interrupts and from one to four tables for receiver interrupts. Each channel is programmed to report receiver interrupts in one of the receiver tables. This way receiver interrupts can be sorted, for example, by priority. Each interrupt circular table must be least two entries long. T/RINTBASE and T/RINTPTR, which are user-initialized global MCC parameters (See Section 29.2, “Global MCC Parameters”), point to the starting location of the table (in external memory) and the current empty position (initialized at the top of the table) available to the CP. All the entries in the table must be user-initialized with 0x00000000, except for the last one which must be initialized with 0x40000000 (W = 1, thus defining the end of the table). When an MCC channel generates an interrupt request, the CP writes a new entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry, T/RINTPTR is loaded with T/RINTBASE). The circular interrupt tables consist of channel-specific events, with a bit for each possible event as well as the number of the channel reporting that event. Each channel has an INTMSK field that determines which events on that particular channel trigger the creation of a new entry in the interrupt tables. Whenever a new entry is added to an interrupt table, the MCC will set the appropriate TINT or RINTx bit in the MCCE global event register, if that bit is properly enabled in MCCM global mask register. If there was no room in the interrupt table for a new entry the corresponding queue overflow (QOVx) bit will be set in the MCCE and the interrupt information is lost although operation will continue. After an MCC interrupt reaches the core, the software should read the corresponding MCCE. After clearing the appropriate event bits by writing ones to them, the software may begin processing the table(s) that contain pending events, as indicated by the bits MCCE[RINTx] and MCCE[TINT]. When processing the interrupt tables, the software must clear each entry’s valid bit (V) (see Section 29.8.1.1, “Interrupt Circular Table Entry”). The user follows this procedure until it reaches an entry with V = 0. It may not be appropriate for an application to process every new entry of all interrupt tables at once, depending on desired interrupt handler latency or other factors. It is up to the user to determine an interrupt handling scheme that provides desired performance and functionality. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-35 Multi-Channel Controllers (MCCs) 29.8.1 MCC Event Register (MCCE)/Mask Register (MCCM) The MCC event register (MCCE) is used to report events and generate interrupt requests. For each of its flags, a programmable mask/enable bit in MCCM determines whether an interrupt request is generated. The MCC mask register (MCCM) is used to enable/disable interrupt requests. For each flag in the MCCE there is a programmable mask/enable bit in MCCM which determines whether an interrupt request is generated. Setting an MCCM bit enables and clearing an MCCM bit disables the corresponding interrupt. MCCE bits are cleared by writing ones to them; writing zeros has no effect. Figure 29-19 shows MCCE and MCCM bits. 0 1 2 3 4 5 6 7 8 11 12 13 14 15 Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3 Reset R/W Addr 0000_0000_0000_0000 R/W — TQOV TINT GUN GOV 0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2) Figure 29-19. MCC Event Register (MCCE)/Mask Register (MCCM) Table 29-18 describes MCCE fields. Table 29-18. MCCE/MCCM Register Field Descriptions Bits 0 1 2 3 4 5 6 7 8–11 12 Name Description QOV0 QOVx—Receive interrupt queue overflow. IQOV is set (and an interrupt request generated) by the CP whenever an overflow occurs in the transmit circular interrupt table. This occurs if the CP tries to update an RINT0 interrupt entry that was not handled by the user (such an entry is identified by V = 1). QOV1 RINTx—Receive interrupt. When RINT = 1, the MCC generated at least one new entry in the receive interrupt circular table. After clearing it, the user reads the next entry from the receive interrupt circular table RINT1 and starts processing a specific channel’s exception. The user returns from the interrupt handler when it reaches a table entry with V = 0. QOV2 RINT2 QOV3 RINT3 — Reserved, should be cleared. TQOV Transmit interrupt queue overflow. TQOV is set (and interrupt request generated) by the CP whenever an overflow occurs in the transmit circular interrupt table. This condition occurs if the CP attempts to write a new interrupt entry into an entry that was not handled by the user. Such an entry is identified by V = 1. TINT Transmit interrupt. When TINT = 1, at least one new entry in the transmit interrupt circular table was generated by MCC. After clearing it, the user reads the next entry from the transmit interrupt circular table and starts processing a specific channel’s exception. The user returns from the interrupt handler when it reaches a table entry with V = 0. Global transmit underrun. This flag indicates whether an underrun occurred inside the MCC’s transmit FIFO array (see Section 29.8.1.2, “Global Transmitter Underrun (GUN)”). The user must clear this bit. Global receiver overrun. This flag indicates whether an overrun occurred inside the MCC’s receive FIFO array (see Section 29.8.1.4, “Global Overrun (GOV)”). The user must clear this bit. 13 14 15 GUN GOV MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-36 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.8.1.1 Interrupt Circular Table Entry Each interrupt circular table entry, shown in Figure 29-20, contains information about channel-specific events. The transmit circular table shows only events caused by transmission; the receive circular tables shows only events caused by reception. The corresponding interrupt mask bits are mode-dependent; refer to the appropriate section: • Section 29.3.1.2, “Interrupt Mask (INTMSK)—HDLC Mode” • Section 29.3.2.2, “Interrupt Mask (INTMSK)—Transparent Mode” • Section 29.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES” • Section 29.3.4.1, “Extended Channel Mode Register (ECHAMR)—SS7 Mode” 0 1 2 3 1 4 5 1 6 7 8 9 10 1 11 12 13 14 15 Field V W OCT — SUERM1 — FISU — SLIPS 2 UN TXB — AERM — NID IDL MRF RXF BSY RXB SLIPE2 R/W 16 17 18 R/W 25 26 31 Field R/W — Channel Number R/W — Figure 29-20. Interrupt Circular Table Entry 1 2 SS7 mode only. Otherwise, reserved. Only used in conjunction with AAL1 CES. Table 29-19 describes interrupt circular table fields. Table 29-19. Interrupt Circular Table Entry Field Descriptions Bits 0 Name V Description Valid bit. V = 1 indicates that this entry contains valid interrupt information. Upon generating a new entry, the CP sets V = 1. The user clears V immediately after it reads the interrupt flags of the entry (before processing the interrupt). The V bits in the table are user-initialized. During initialization, the user must clear those bits in all table entries. Wrap bit. W = 1 indicates the last interrupt circular table entry. The next event’s entry is written/read (by CP/user) from the address contained in INTBASE (see Table 29-1 on page 29-4). During initialization, the user must clear all W bits in the table except for the last one which must be set. Reserved, should be cleared. (If SS7 mode, refer to the following description.) SS7 mode only: N octets received. If the channel is in octet counting, this bit is set when N octets have been received. Reserved, should be cleared. (If SS7 mode, refer to the following description.) SS7 mode only: SU error monitor threshold reached. The SU error monitor has reached the programmed threshold T. 1 W 2 — OCT 3 — SUERM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-37 Multi-Channel Controllers (MCCs) Table 29-19. Interrupt Circular Table Entry Field Descriptions (continued) Bits 4 Name FISU Description SS7 mode only: FISU transmission started. The CP has started automatic FISU transmission if the first BD of frame does not have its ready bit set and the SEN_FISU bit is enabled in SS7_OPT register. Please refer to SEN_FISU bit in Section 29.3.4.3, “SS7 Configuration Register—SS7 Mode. Only used in conjunction with AAL1 CES. Slip End. Set when an MCC channel interworking with an ATM channel exits the slip state (the connection’s CESAC falls to the MCC_Start threshold). At this point, the transmitter stops sending the underrun template (or last buffer) and starts sending valid data. Reserved, should be cleared. Only used in conjunction with AAL1 CES.Slip Start. Set when an MCC channel interworking with an ATM channel enters a slip state (the channel’s CESAC reaches the MCC_Stop threshold). At this point the transmitter freezes and begins sending the underrun template (or last buffer) until CESAC falls to the MCC_Start threshold. Tx no data. The CP sets this flag if there is no data available to be sent to the transmitter. The transmitter sends an ABORT indication and then sends idles. Tx buffer. A buffer has been completely transmitted. TXB is set (and an interrupt request is generated) as soon as the programmed number of PAD characters (or the closing flag, for PAD = 0) is written to MCC transmit FIFO. This controls when the TXB interrupt is given in relation to the closing flag sent out at TXD. Section 29.9.2, “Transmit Buffer Descriptor (TxBD)” describes how PAD characters are used. Reserved, should be cleared. Reserved, should be cleared. (If SS7 mode, refer to the following description.) SS7 mode only: Alignment error rate monitor threshold (M value in SS7 channel-specific parameters) has been reached. Set whenever a pattern that is not an idle pattern is identified. Idle. Set when the channel’s receiver identifies the first occurrence of idle (0xFFFE) after any non-idle pattern. Maximum receive frame length violation. This interrupt occurs when more bytes are received than the value specified in MFLR. This interrupt is generated as soon as the MFLR value is exceeded; the remainder of the frame is discarded Rx frame. A complete HDLC frame has been received. Busy. A frame was received but was discarded due to lack of buffers. Rx buffer. A buffer has been received on this channel that was not the last buffer in frame. This interrupt is also given for different error types that can happen during reception. Error conditions are reported in the RxBD. Reserved, should be cleared. Channel number. Identifies the requests channel index (0–255). Reserved, should be cleared. SLIPE 5 — SLIPS 6 7 UN TXB 8 9 — — AERM 10 11 12 NID IDL MRF 13 14 15 RXF BSY RXB 16–17 18–25 26–31 — CN — 29.8.1.2 Global Transmitter Underrun (GUN) A global underrun (GUN) event indicates that the MCC’s transmit FIFO array experienced an underrun condition. This is not due to a lack of ready transmit buffer descriptors (as in the UN condition in an interrupt queue entry); rather, it indicates a hardware latency issue which could be caused in several ways. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-38 Freescale Semiconductor Multi-Channel Controllers (MCCs) It is not possible to determine exactly which channel's FIFO experienced the underrun, therefore a GUN is considered a global event affecting that entire MCC. Following the assertion of MCCE[GUN], the MCC stops transmitting data on all channels and all ones are sent instead. The MCC must be reset either through an MCC RESET command or a CPM RESET after this error and then the MCC may be reinitialized. There are several possible causes for an MCC GUN error: • Glitching on the TDM clock. Refer to Section 29.8.1.2.1, “TDM Clock.” • Synchronization pulse (sync pulse). Refer to Section 29.8.1.2.2, “Synchronization Pulse.” • Misprogramming of SIRAM. Refer to Section 29.8.1.2.3, “SIRAM Programming,” and Section 29.8.1.2.4, “MCC Initialization.” • CPM bandwidth. Refer to Section 29.8.1.2.5, “CPM Bandwidth.” • CPM priority. Refer to Section 29.8.1.2.6, “CPM Priority.” 29.8.1.2.1 TDM Clock Glitches on the TDM clock may be interpreted as an overwhelming number of clocks that the SI may try to process (amongst other anomalous behavior), thus draining the MCC FIFOs on that TDM much too quickly. This results in a GUN. 29.8.1.2.2 Synchronization Pulse A TDM frame length, as programmed in SIRAM, that is shorter than the actual gap between sync pulses may cause an underrun condition (in other words, if SIRAM programming hits an entry with SIxRam[LST] set and then encounters dead time before the next sync pulse on the line). This may result in anomalous behavior in the SI and therefore an underrun condition. To avoid these cases, pad out the SIRAM programming with “null entries”, entries with no CPM peripheral specified (MCC=0 and CSEL = 0000 in SIRAM entry) at the end of the SIRAM programming. Make the null SIRAM entries represent the appropriate amount of time so that the SI frame length matches the gap between sync pulses. 29.8.1.2.3 SIRAM Programming Failure to follow SIRAM programing guidelines can result in erratic behavior or possibly GUN errors. The following is a list of common programming errors: • Failing to set “LAST” in the final entry of an even-numbered total of SIRAM entries (i.e. there cannot be an odd total of SIRAM entries for a TDM) • Programming an SIRAM entry to use an un-initialized MCC channel (or if the MCC as whole has not been initialized with the appropriate “INIT TX RX” commands). • Programming an SIRAM entry to use an MCC channel that is not assigned to that particular TDM. • Using a channel too often (which would overload the FIFO) without going to superchannels. • Turning on too many MCC channels at once in the SIRAM (we suggest not to enable more than 32 channels per TDM frame's worth of time when you are first programming the SI). • Other programming errors, such as incorrect values in the SIRAM entries, etc. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-39 Multi-Channel Controllers (MCCs) 29.8.1.2.4 MCC Initialization CPCR commands for the MCC (such as Init Tx Parameters and Init Rx Parameters) must be issued to cover all MCC channel numbers that appear in either the SIRAM or superchannel table before that channel number is used on an active TDM. Note that the command initializes 32 channels at a time, starting with the channel number given in the command. All channels used in any fashion must be initialized by the Init Tx parameters and the Init Rx parameters command. Before a TDM is enabled to use an MCC channel, the following must be initialized: • Global MCC parameters • Channel Extra Parameters • Channel-Specific Parameters • Super-Channel Table (if appropriate) and registers If the MCC has invalid data in any of these areas when the SI tries to talk to the MCC, a GUN is one of the possible symptoms. Before a TDM is programmed to use an MCC channel, the channel-specific fields RSTATE and TSTATE must either contain the start value or “STOP TX” and “STOP RX” commands must be issued to that channel. It is not a valid condition to leave RSTATE and TSTATE unitialized before TDM operation using that channel 29.8.1.2.5 CPM Bandwidth If the CPM is overloaded, the MCC is usually one of the first communications controllers to exhibit problems, often in the form of the GUN. The MCC's sensitivity to bandwidth issues is due to the shallowness of the FIFOs and the CPM prioritization of the MCC TX. 29.8.1.2.6 CPM Priority It is possible for the MCC to experience a GUN due to prioritization in the CPM. See Section 14.3.5, “Peripheral Interface,” for details on the CPM prioritization scheme. There are some options available for altering how the CPM peripheral prioritization works. These options provide the opportunity for the user to raise the priority of the MCC itself or lower the priority of other peripherals. RCCR[MCCPR] controls the MCC priority in relation to other CPM peripherals (refer to Section 14.3.7, “RISC Controller Configuration Register (RCCR)”). When MCCPR is set, the MCCs are constantly at emergency priority level within the CPM prioritization scheme. If used, this configuration should be tested to ensure that the setting of MCCPR does not have adverse effects on the performance of other peripherals being used in an application. When MCCPR is cleared, the normal priority scheme is be used (refer to Section 14.3.5, “Peripheral Interface”). Each FCC FIFO has threshold values, determined by the mode it is using, for determining normal and emergency CPM request prioritization. When an FCC is in emergency mode, that FCC's TX or RX request may have higher priority than MCC TX or RX. When FCC1 in particular is in emergency priority mode, it will always be of higher priority than an MCC. This opens up the possibility of the FCC starving out the MCC if the FCC continues to be overutilized. This can lead to a GUN. To help alleviate this situation, setting FPSMR[TPRI] prevents the FCC’s TX from going into emergency mode and can minimize the risk of global underrun. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-40 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.8.1.2.7 Bus Latency A GUN may also occur if the external memory bus bandwidth is insufficient for the system. Factors could include a bus that is too slow or external masters keeping the bus for extended periods of time. Bus parking master and bus arbiter configurations as described in Section 4.3.2, “System Configuration and Protection Registers,” should also be considered as factors when making sure the CPM is properly prioritized for bus access. 29.8.1.3 Recovery from GUN Errors The GUN error is considered fatal because it cannot be determined which channel was at fault. The MCC RESET command in the CP command register [CPCR] provides a hard reset to the MCC FIFOs. Refer to the following table. Table 29-20. GUN Error Recovery Step 1 2 3 4 5 Action Disable the TDM by clearing the appropriate enable bit in SIxGMR[4-7]. Issue the MCC RESET command. Issue the INIT RX AND TX command to cover the channels in use. Reprogram the specific MCC channel, global parameters, and any BDs that need to be updated. Enable TDM by setting appropriate bit. 29.8.1.4 Global Overrun (GOV) An MCC receiver global overrun (GOV) is the receive version of the transmit GUN. Due to different prioritization and implementation of MCC RX, the likelihood of a GOV occurring is less than a the likelihood of a GUN. Despite this, all possible causes and recovery procedures apply. 29.9 MCC Buffer Descriptors Each MCC channel requires two BD tables (one for transmit and one for receive). Each BD contains key information about the buffer it defines. The BDs are accessed by the MCC as needed; BDs can be added dynamically to the BDs chain. The RxBDs chain must include at least two BDs; the TxBD chain must include at least one BDs. The MCC BDs are located in the external memory. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-41 Multi-Channel Controllers (MCCs) 29.9.1 Receive Buffer Descriptor (RxBD) Figure 29-21 shows the RxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I L F CM — UB — LG NO AB CR SF1 — Data Length Rx Data Buffer Pointer Figure 29-21. MCC Receive Buffer Descriptor (RxBD) 1 SS7 mode only. Otherwise, reserved. RxBD fields are described in Table 29-21. Table 29-21. RxBD Field Descriptions Bits 0 Name E Description Empty 0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition. The user is free to examine or write to any fields of this RxBD. The CP does not use this BD again while the empty bit remains zero. 1 The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its associated receive buffer are in use by the CP. When E = 1, the user should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in table) 0 This is not the last BD in the RxBD table. 1 This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming data into the first BD in the table (the BD pointed to by RBASE). The number of RxBDs in this table is programmable and is determined by the wrap bit. Interrupt 0 The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected. 1 The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been used by the HDLC controller. These two bits may cause interrupts (if enabled). Last in frame (only for HDLC mode of operation). The HDLC controller sets L = 1, when this buffer is the last in a frame. This implies the reception either of a closing flag or of an error, in which case one or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to the data length field. 0 This buffer is not the last in a frame. 1 This buffer is the last in a frame. First in frame. The HDLC controller sets F = 1 for the first buffer in a frame. In transparent mode, F indicates that there was a synchronization before receiving data in this BD. 0 This is not the first buffer in a frame. 1 This is the first buffer in a frame. 1 2 — W 3 I 4 L 5 F MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-42 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-21. RxBD Field Descriptions (continued) Bits 6 Name CM Description Continuous mode 0 Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed). 1 The empty bit (bit 0) is not cleared by the CP after this BD is closed, allowing the associated data buffer to be overwritten automatically when the CP next accesses this BD. However, if an error occurs during reception, the empty bit is cleared regardless of the CM bit setting. Reserved, should be cleared. User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this bit is used. Reserved, should be cleared. Rx frame length violation (HDLC mode only). Indicates that a frame length greater than the maximum value was received in this channel. Only the maximum-allowed number of bytes, MFLR rounded to the nearest higher word alignment, are written to the data buffer. This event is recognized as soon as the MFLR value is exceeded when data is word-aligned. When data is not word-aligned, this interrupt occurs when the SDMA writes 64 bits to memory. The worst-case latency from MFLR violation until detected is 7 bytes timing for this channel. When MFLR violation is detected, the receiver is still receiving even though the data is discarded. The buffer is closed upon detecting a flag, and this is considered to be the closing flag for this buffer. At this point, LG is set (1) and an interrupt may be generated. The length field for this buffer is everything between the opening flag and this last identifying flag. Rx nonoctet-aligned frame. A frame of bits not divisible exactly by eight was received. NO = 1 for any type of nonalignment regardless of frame length. The shortest frame that can be detected is of type FLAG-BIT-FLAG, which causes the buffer to be closed with NO error indicated. The following shows how the nonoctet alignment is reported and where data can be found. msb xxx .................................... xx Valid data 1 lsb 000...... 0 Invalid data 7 8 9 10 — UB — LG 11 NO To accommodate the extra word of data that may be written at the end of the frame, it is recommended to reserve MFLR + 8 bytes for each buffer data. 12 AB Rx abort sequence. A minimum of seven consecutive 1s was received during frame reception. Abort is not detected between frames. The sequence Closing-Flag, data, CRC, AB, data, opening-flag... does not cause an abort error. If the abort is long enough to be an idle, an idle line interrupt may be generated. An abort within the frame is not reported by a unique interrupt but rather with a RXF interrupt and the user has to examine the BD. Rx CRC error. This frame contains a CRC error. The received CRC bytes are always written to the receive buffer. Reserved, should be cleared. SS7 mode only: Short frame indication. Set if the received frame is less than 5 octets. Reserved, should be cleared. 13 14 CR — SF 15 — The data length and buffer pointer are described as follows: • Data length. Data length is the number of octets written by the CP into this BD’s data buffer. It is written by the CP when the BD is closed. When this is the last BD in the frame (L = 1), the data MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-43 Multi-Channel Controllers (MCCs) • length contains the total number of frame octets (including two or four bytes for CRC). Note that memory allocated for buffers should be not smaller than the contents of the maximum receive buffer length register (MRBLR). The data length does not include the time stamp. Rx buffer pointer. The receive buffer pointer points to the first location of the associated data buffer. This value must be equal to 8*n if CHAMR[TS] = 0 and equal to 8*n - 4 if CHAMR[TS] = 1 (where n is any integer larger than 0). 29.9.2 Transmit Buffer Descriptor (TxBD) Figure 29-22 shows the TxBD. 0 1 2 1 3 4 5 6 7 8 9 10 11 12 1 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 1 R RT W I L TC CM — UB — SUD PAD Data Length Tx Data Buffer Pointer SS7 mode only. Otherwise, reserved. Figure 29-22. MCC Transmit Buffer Descriptor (TxBD) Table 29-22 describes TxBD fields. Table 29-22. TxBD Field Descriptions Bits 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 The data buffer is ready to be transmitted. The transmission may have begun, but it has not completed. The user cannot modify this BD once this bit is set. SS7 mode only: Retransmit. 0 Normal operation 1 The CP repeats transmission of this BD until the RT bit is cleared. After the RT bit is cleared the CP advances to the next BD in the table. This feature is useful for automatic LSSU retransmission. Note: This bit is reserved in all other modes of operation. Wrap (final BD in table) 0 This is not the last BD in the TxBD table. 1 This is the last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the first BD in the table (the BD pointed to by TBASE). The number of TxBDs in this table is programmable and is determined the wrap bit. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt if enabled. 1 RT 2 W 3 I MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-44 Freescale Semiconductor Multi-Channel Controllers (MCCs) Table 29-22. TxBD Field Descriptions (continued) Bits 4 Name L Description Last 0 This is not the last buffer in the frame. 1 This is the last buffer in the current frame. Tx CRC. Valid only when L = 1. Otherwise it is ignored. 0 Transmit the closing flag after the last data byte. This setting can be used for testing purposes to send an erroneous CRC after the data. 1 Transmit the CRC sequence after the last data byte. Continuous mode 0 Normal operation. 1 The CP does not clear the ready bit after this BD is closed, allowing the associated data buffer to be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of the CM bit setting. Reserved, should be cleared. User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this bit is used. Reserved, should be cleared. Reserved, should be cleared. SS7 mode only: Signal unit delay 0 This buffer does not have a transmission delay. 1 A time delay of JTTDelay x 512 µs passes before this buffer is transmitted. Can be used for LSSU transmission according to the JT Q.703 Standard which defines a 24 ms delay between back-to-back LSSUs. This bit is only valid when SS7_OPT[STD] is set. Pad characters. These four bits indicate the number of PAD characters (0x7E or 0xFF depending on the IDLM mode selected in the CHAMR register) that the transmitter sends after the closing flag. The transmitter issues a TXB interrupt only after sending the programmed number of pads to the Tx FIFO buffer. The user can use the PAD value to guarantee that the TXB interrupt occurs after the closing flag has been sent out on the TXD line. PAD = 0, means that the TXB interrupt is issued immediately after the closing flag is sent to the Tx FIFO buffer. The number of PAD characters depends on the FIFO size assigned to the channel in the MCC hardware. If the channel is not part of a super channel then the MCC hardware assigns to this channel a fifo of 4 bytes. So in this case a pad of 4 bytes ensures that the TXB interrupt is not given before the closing flag has been transmitted over the TXD line. For a super channel, the FIFO length equals the number of time slots assigned to the super channel multiplied by two. 5 TC 6 CM 7 8 9–10 11 — UB — — SUD 12–15 PAD The data length and buffer pointer are described below: • Data length. The data length is the number of bytes the MCC should transmit from this BD’s data buffer. It is never modified by the CP. The value of this field should be greater than zero. • Tx buffer pointer. The transmit buffer pointer, which contains the address of the associated data buffer, may be even or odd provided that SS7_OPT[SEN_FIS] = 0 (refer to Section 29.3.4.3, “SS7 Configuration Register—SS7 Mode”). If the automatic FISU option is required, the buffer pointer must be 4-byte aligned. The buffer must reside in external memory. This value is never modified by the CP. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-45 Multi-Channel Controllers (MCCs) 29.10 MCC Initialization and Start/Stop Sequence The MCC must be initialized and started/stopped in relation with the corresponding TDMs. The following section presents the initialization and start/stop sequences which must be followed for single and super channels. The following is a general sequence for initializing an MCC and its channels after reset: 1. Program the parallel I/O port interface for the TDM to be used (refer to Chapter 41, “Parallel I/O Ports”). 2. Program the SIU’s interrupt controller to mask or enable MCC-related interrupts as desired (refer to Section 4.3.1, “Interrupt Controller Registers”). 3. Program the SI’s SIRAM and related registers. If the user wishes to enable the TDM at this time, the SIRAM programming cannot yet contain MCC-related timeslots. Those timeslots should be NULL entries and not programmed for MCC usage until after MCC-related initialization is complete. Refer to Chapter 15, “Serial Interface with Time-Slot Assigner,” for SI programming details. 4. Initialize buffer descriptors and data buffers as needed. 5. Initialize all MCC global parameters. 6. Initialize MCC channel-specific parameters for channels to be used. (Note that, if SI was not already enabled in step 3, TSTATE and RSTATE can be fully programmed here to begin data transmission and reception as soon as the TDM is enabled. If a user wishes to wait until after the TDM is enabled before starting data transmission and reception, the user may program only the FCR portions of RSTATE and TSTATE; and STOP TX and STOP RX commands should be issued for the appropriate channels before enabling the TDM.) 7. Initialize MCC channel-extra parameters for channels to be used. 8. Initialize Superchannel Table if superchannels are to be used. 9. Issue MCC INIT commands as appropriate to make sure all MCC FIFOs that are to be used are initialized. 10. Enable TDM (or if TDM is already enabled, the user may now reprogram the TDM to include MCC-related timeslots). 11. If the user did not program a channel’s TSTATE and RSTATE in step 6 to begin data transmission and reception immediately upon having an active TDM, the user may program the start conditions at this time. NOTE Some steps may be performed out of order. However, it is critical, regardless of their relative sequence, that steps 5, 6, 7, 8 and 9 occur before the enabling of the TDM or an active TDM is reprogrammed to include MCC-related timeslots. Failure to properly initialize MCC parameters and issue appropriate INIT commands before MCC-related timeslots are programmed in an active TDM may result in spurious GUN events or other anomalous behavior. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-46 Freescale Semiconductor Multi-Channel Controllers (MCCs) 29.10.1 Stopping and Restarting a Single-Channel The following sequence must be followed to stop a single channel in order to change the MCC parameters of the respective channel: 1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC Commands,” or change the associated SI RAM entry to point to a channel which is not active and wait for two frame periods in order to clear the internal FIFOs. 2. Change the channel parameters. 3. Enable the MCC channel(s) as described in Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode,” or change the associated SI RAM entry to point to the respective channel. The following sequence must be followed to stop a single channel in order to change the SI without using the shadow SI: 1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC Commands.” 2. Change the SI. 3. Enable the MCC channel as described in Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” It is possible to change the SI using the SI shadow while the channel is active. Both the primary and the shadow configuration of the SI RAM must observe the configuration defined in MCCF (see Section 29.6, “MCC Configuration Registers (MCCFx)”). The MCCF cannot be changed while there are active channels. 29.10.2 Stopping and Restarting a Superchannel The following sequence must be followed to stop a super channel in order to change the SI: 1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC Commands.” 2. Disable the TDM. 3. Change the SI. 4. Enable the TDM. 5. If necessary, change the MCC parameters (in DPRAM and external memory). 6. Enable the MCC channel(s) as described in Section 29.3.1.1, “Internal Transmitter State (TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC Mode.” Under the following restrictions, the SI can be changed using the SI shadow while the channel is active: • Both the primary and the shadow configuration of the SI RAM must observe the configuration of the super channel. Note that the super-channel table and MCCF register cannot be changed dynamically. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-47 Multi-Channel Controllers (MCCs) • A time slot that was previously used by a single channel and had a width different from 8 bits cannot be added dynamically to a super channel. 29.11 MCC Latency and Performance The CPM moves data between an MCC channel's FIFOs and temporary 8 byte data buffers in the corresponding channel-specific parameter RAM. RX FIFOs provide data to the ZDSTATE fields and TX FIFOs are fed from the ZISTATE fields. This traffic is considered completely internal to the CPM. In addition to the loading and storing of buffer descriptors, the CPM transfers data for an MCC channel to/from external memory 8 bytes at a time, to replenish or empty the ZISTATE and ZDSTATE fields as appropriate. The user may then estimate how frequently the MCC will need to transfer data on an external bus for a particular channel by calculating how quickly 8 bytes will be sent or received on that channel. If multiple synchronized TDMs are used (as an example 8 T1 with common clock/sync) it is recommended to start the TDMs out of phase relative to each other, in order to spread out CPM and bus utilization. This avoids CPM and bus activity peaks when all the channels would require CPM attention and possibly have to transfer data to/from the memory simultaneously. When MCC FIFO activity starts, the MCC begins to consume CPM bandwidth immediately upon enabling a TDM which has MCC-related SIRAM programming. This is regardless of whether a channel is stopped or has the “start condition” programmed in the RSTATE and TSTATE channel-specific parameters. If a user wishes to spread out CPM and bus utilization for the MCC channels on a particular TDM, those channels must be dynamically added to the SIRAM programming in an evenly distributed fashion over multiple TDM frames. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 29-48 Freescale Semiconductor Chapter 30 Fast Communications Controllers (FCCs) The MPC8280’s three fast communications controllers (FCCs) are serial communications controllers (SCCs) optimized for synchronous high-rate protocols. FCC key features include the following: • Supports HDLC/SDLC and totally transparent protocols • FCC clocks can be derived from a baud-rate generator or an external signal • Supports RTS, CTS, and CD modem control signals • Use of bursts to improve bus usage • Multibuffer data structure for receive and transmit, external buffer descriptors (BDs) anywhere in system memory • 192-byte FIFO buffers • Full-duplex operation • Fully transparent option for one half of an FCC (receiver/transmitter) while HDLC/SDLC protocol executes on the other half (transmitter/receiver) • Echo and local loopback modes for testing • Assuming a 100-MHz CPM clock, the FCCs support the following: – Full 10/100-Mbps Ethernet/IEEE 802.3x through an MII and RMII interface – Full 155-Mbps ATM segmentation and reassembly (SAR) through UTOPIA (on FCC1 and FCC2 only) (not available on the MPC8270) – ATM internal rate mode for 31 PHYs – ATM 31 PHY addresses for both FCC1 and FCC2 – 45-Mbps (DS-3/E3 rates) HDLC and/or transparent data rates supported on each FCC FCCs differ from SCCs as follows: • No DPLL support. • No BISYNC, UART, or AppleTalk/LocalTalk support. • No HDLC bus. • Ethernet support only through an MII. 30.1 Overview MPC8280 FCCs can be configured independently to implement different protocols. Together, they can be used to implement bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks. FCCs have many physical interface options such as interfacing to TDM buses, ISDN buses, standard modem interfaces, fast Ethernet interface (MII), and ATM interfaces (UTOPIA); see Chapter 15, “Serial Interface with Time-Slot Assigner,” Chapter 36, “Fast MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-1 Fast Communications Controllers (FCCs) Ethernet Controller,” and Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5.” The FCCs are independent from the physical interface, but FCC logic formats and manipulates data from the physical interface. That is why the interfaces are described separately. The FCC is described in terms of the protocol that it is chosen to run. When an FCC is programmed to a certain protocol, it implements a certain level of functionality associated with that protocol. For most protocols, this corresponds to portions of the link layer (layer 2 of the seven-layer OSI model). Many functions of the FCC are common to all of the protocols. These functions are described in the FCC description. Following that, the implementation details that differentiate protocols from one another are discussed, beginning with the transparent protocol. Thus, the reader should read from this point to the transparent protocol and then skip to the appropriate protocol. Since the FCCs use similar data structures across all protocols, the reader's learning time decreases dramatically after understanding the first protocol. Each FCC supports a number of protocols—Ethernet, HDLC/SDLC, ATM, and totally transparent operation. Although the selected protocol usually applies to both the FCC transmitter and receiver, half of one FCC can run transparent operation while the other runs HDLC/SDLC protocol. The internal clocks (RCLK, TCLK) for each FCC can be programmed with either an external or internal source. The internal clocks originate from one of the baud-rate generators or one of the external clock signals. The limitation of the internal clocks frequency depends on the protocol being used, see Table 30-1. See Chapter 15, “Serial Interface with Time-Slot Assigner.” However, the FCC’s ability to support a sustained bit stream depends on the protocol as well as on other factors. Each FCC can be connected to its own set of pins on the MPC8280. This configuration, the nonmultiplexed serial interface, or NMSI, is described in Chapter 15, “Serial Interface with Time-Slot Assigner.” In this configuration, each FCC can support the standard modem interface signals (RTS, CTS, and CD) through the appropriate port pins and the interrupt controller. Additional handshake signals can be supported with additional parallel I/O lines. The FCC block diagram is shown in Figure 30-1. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-2 Freescale Semiconductor Fast Communications Controllers (FCCs) 60x Bus Control Registers Peripheral Bus Clock Generator TCLK RCLK Internal Clocks Receive Data FIFO Transmit Data FIFO Modem Lines Receive Control Unit Transmit Control Unit Modem Lines RXD TXD Decoder Delimiter Shifter Shifter Delimiter Encoder Figure 30-1. FCC Block Diagram Table 30-1. Internal Clocks to CPM Clock Frequency Ratio Mode HDLC 1 bit Transparent 1 bit HDLC nibble Fast Ethernet ATM 1:4 1:4 1:6 1:3 (1:3.5 preferred) 1:3 (1:3.5 preferred) Internal Clock: CPM clock frequency ratio 30.2 General FCC Mode Registers (GFMRx) Each FCC contains a general FCC mode register (GFMRx) that defines common FCC options and selects the protocol to be run. The GFMRx are read/write registers cleared at reset. Figure 30-2 shows the GFMR format. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-3 Fast Communications Controllers (FCCs) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr DIAG TCI TRX TTX CDP CTSP CDS CTSS 0000_0000_0000_0000 R/W — 0x11300 (GFMR1), 0x11320(GFMR2), 0x11340(GFMR3) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Reset R/W Addr SYNL RTSM RENC REVD TENC TCRC ENR ENT MODE 0000_0000_0000_0000 R/W 0x11302 (GFMR1), 0x11322 (GFMR2), 0x11342 (GFMR3) Figure 30-2. General FCC Mode Register (GFMR) Table 30-2. describes GFMR fields. Table 30-2. GFMR Register Field Descriptions Bits 0–1 Name DIAG Description Diagnostic mode. 00 Normal operation—Receive data enters through RXD, and transmit data is shifted out through TXD. The FCC uses the modem signals (CD and CTS) to automatically enable and disable transmission and reception. Timings are shown in Section 30.11, “FCC Timing Control.” 01 Local loopback mode—Transmitter output is connected internally to the receiver input, while the receiver and the transmitter operate normally. RXD is ignored. Data can be programmed to appear on TXD, or TXD can remain high by programming the appropriate parallel port register. RTS can be disabled in the appropriate parallel I/O register. The transmitter and receiver must use the same clock source, but separate CLK x pins can be used if connected to the same external clock source. If external loopback is preferred, program DIAG for normal operation and externally connect TXD and RXD. Then, physically connect the control signals (RTS connected to CD, and CTS grounded) or set the parallel I/O registers so CD and CTS are permanently asserted to the FCC by configuring the associated CTS and CD pins as general-purpose I/O.; see Chapter 41, “Parallel I/O Ports.” 10 Automatic echo mode—The channel automatically retransmits received data, using the receive clock provided. The receiver operates normally and receives data if CD is asserted. The transmitter simply transmits received data. In this mode, CTS is ignored. The echo function can also be accomplished in software by receiving buffers from an FCC, linking them to TxBDs, and transmitting them back out of that FCC. 11 Loopback and echo mode—Loopback and echo operation occur simultaneously. CD and CTS are ignored. Refer to the loopback bit description for clocking requirements. For TDM operation, the diagnostic mode is selected by SIxMR[SDMx]; see Section 15.5.2, “SI Mode Registers (SIxMR).” Transmit clock invert 0 Normal operation. 1 The FCC inverts the internal transmit clock. The edge on which the FCC outputs the data depends on the protocol: • In HDLC and Transparent mode, when TCI=0, data is sent on the falling edge; when TCI=1, on the rising edge. • In Ethernet mode, when TCI=0, data is sent on the rising edge; when TCI=1, on the falling edge. 2 TCI MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-4 Freescale Semiconductor Fast Communications Controllers (FCCs) Table 30-2. GFMR Register Field Descriptions (continued) Bits 3 Name TRX Description Transparent receiver. The MPC8280 FCCs offer totally transparent operation. However, to increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of the MODE bits. This lets the user implement unique applications such as an FCC transmitter configured to HDLC and a receiver configured to totally transparent operation. To do this, program MODE = HDLC, TTX = 0, and TRX = 1. 0 Normal operation 1 The receiver operates in totally transparent mode, regardless of the protocol selected for the transmitter in the MODE bits. Note: Full-duplex, totally transparent operation for an FCC is obtained by setting both TTX and TRX. Attempting to operate an FCC with Ethernet or ATM on its transmitter and transparent operation on its receiver causes erratic behavior. In other words, if the MODE = Ethernet or ATM, TTX must equal TRX. Transparent transmitter. The MPC8280 FCCs offer totally transparent operation. However, to increase flexibility, totally transparent operation is configured with the TTX and TRX bits instead of the MODE bits. This lets the user implement unique applications, such as configuring an FCC receiver to HDLC and a transmitter to totally transparent operation. To do this, program MODE = HDLC, TTX = 1, and TRX = 0. 0 Normal operation. 1 The transmitter operates in totally transparent mode, regardless of the receiver protocol selected in the MODE bits. Note: Full-duplex totally transparent operation for an FCC is obtained by setting both TTX and TRX. Attempting to operate an FCC with Ethernet or ATM on its receiver and transparent operation on its transmitter causes erratic behavior. In other words, if GFMR[MODE] selects Ethernet or ATM, TTX must equal TRX. CD pulse (transparent mode only) 0 Normal operation (envelope mode). CD should envelope the frame; to negate CD while receiving causes a CD lost error. 1 Pulse mode. Once CD is asserted (high to low transition), synchronization has been achieved, and further transitions of CD do not affect reception. Note: CDP must be set if this FCC is used with the TSA in transparent mode. CTS pulse 0 Normal operation (envelope mode). CTS should envelope the frame; to negate CTS while transmitting causes a CTS lost error. See Section 30.11, “FCC Timing Control.” 1 Pulse mode. CTS is asserted when synchronization is achieved; further transitions of CTS do not affect transmission. When running HDLC, the FCC samples CTS only once before sending the first frame after the transmitter is enabled (ENT = 1). CD sampling 0 The CD input is assumed to be asynchronous with the data. The FCC synchronizes it internally before data is received. (This mode is not allowed in transparent mode when SYNL = 0b00.) 1 The CD input is assumed to be synchronous with the data, giving faster operation. In this mode, CD must transition while the receive clock is in the low state. When CD goes low, data is received. This is useful when connecting MPC8280s in transparent mode since it allows the RTS signal of one MPC8280 to be connected directly to the CD signal of another MPC8280. 4 TTX 5 CDP 6 CTSP 7 CDS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-5 Fast Communications Controllers (FCCs) Table 30-2. GFMR Register Field Descriptions (continued) Bits 8 Name CTSS Description CTS sampling 0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized by the FCC, data is sent after a delay of no more than two serial clocks. 1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode, CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data transmission begins. This mode is useful when connecting MPC8280 in transparent mode because it allows the RTS signal of one MPC8280 to be connected directly to the CTS signal of another MPC8280. Reserved, should be 0. Sync length (transparent mode only). Determines the operation of an FCC receiver configured for totally transparent operation only. See Section 38.3.1, “In-Line Synchronization Pattern.” 00 The sync pattern in the FDSR is not used. An external sync signal is used instead (CD signal asserted: high to low transition). 01 Automatic sync (assumes always synchronized, ignores CD signal). 10 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the FDSR. Negation of CD causes CD lost error. 11 16-bit sync. The receiver synchronizes on a 16-bit sync pattern stored in the FDSR. Negation of CD causes CD lost error. Note: If SYNL = 1x, CDP should be cleared (not in CD pulse mode). 9--15 16–17 — SYNL 18 RTSM RTS m ode 0 Send idles between frames as defined by the protocol. RTS is negated between frames (default). 1 Send flags/syncs between frames according to the protocol. RTS is asserted whenever the FCC is enabled. RENC Receiver decoding method. The user should set RENC = TENC in most applications. 00 NRZ 01 NRZI (one bit mode HDLC or transparent only) 1x Reserved REVD Reverse data (valid for a totally transparent channel only) 0 Normal operation 1 The totally transparent channels on this FCC (either the receiver, transmitter, or both, as defined by TTX and TRX) reverse bit order, transmitting the MSB of each octet first. TENC Transmitter encoding method. The user should set TENC = RENC in most applications. 00 NRZ 01 NRZI (one bit mode HDLC or transparent only) 1x Reserved TCRC Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on the transparent channels of the FCC (either the receiver, transmitter, or both, as defined by TTX and TRX). This configuration selects a frame check type; the decision to send the frame check is made in the TxBD. Thus, it is not required to send a frame check in transparent mode. If a frame check is not used, the user can ignore any frame check errors generated on the receiver. 00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) 01 Reserved 10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1) 11 Reserved 19–20 21 22–23 24–25 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-6 Freescale Semiconductor Fast Communications Controllers (FCCs) Table 30-2. GFMR Register Field Descriptions (continued) Bits 26 Name ENR Description Enable receive. Enables the receiver hardware state machine for this FCC. 0 The receiver is disabled and any data in the receive FIFO buffer is lost. If ENR is cleared during reception, the receiver aborts the current character. 1 The receiver is enabled. ENR may be set or cleared regardless of whether serial clocks are present. Describes how to disable and reenable an FCC. Note that the FCC provides other tools for controlling reception—the ENTER HUNT MODE command, CLOSE RXBD command, and RxBD[E]. Enable transmit. Enables the transmitter hardware state machine for this FCC. 0 The transmitter is disabled. If ENT is cleared during transmission, the transmitter aborts the current character and TXD returns to idle state. Data in the transmit shift register is not sent. 1 The transmitter is enabled. ENT can be set or cleared, regardless of whether serial clocks are present. See Section 30.12, “Disabling the FCCs On-the-Fly,” for a description of the proper methods to disable and reenable an FCC. Note that the FCC provides other tools for controlling transmission besides the ENT bit—the STOP TRANSMIT, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, CTS flow control, and TxBD[R]. 27 ENT 28–31 MODE Channel protocol mode 0000 HDLC 0001 Reserved for RAM 0010 Reserved 0011 Reserved for RAM 0100 Reserved 0101 Reserved for RAM 0110 Reserved 0111 Reserved for RAM 1000 Reserved 1001 Reserved for RAM 1010 ATM 1011 Reserved for RAM 1100 Ethernet 11xx Reserved microcode microcode microcode microcode microcode microcode NOTE In addition to selecting the correct mode of operation in GFMRx[MODE], the user must issue the appropriate CP command and choose the correct protocol in CPCR (refer to Section 14.4.1, “CP Command Register (CPCR)”). 30.2.1 General FCC Expansion Mode Register (GFEMR) The general FCC expansion mode register (GFEMR) defines the expansion modes. It should be programmed according to the protocol used. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-7 Fast Communications Controllers (FCCs) 0 1 2 3 7 Field Reset R/W Addr TIREM LPB CLK 0000_0000 R/W — 0x11390 (GFEMR1), 0x113B0(GFEMR2), 0x113D0(GFEMR3) Figure 30-3. General FCC Expansion Mode Register (GFEMR) Table 30-3 describes GFEMRx fields. Table 30-3. GFEMRx Field Descriptions Bit 0 Name TIREM Description Transmit internal rate expanded mode (ATM mode) 0 Internal rate mode: Internal rate for PHYs[0-3] is controlled only by FTIRR[0-3]. FIRPER, FIRSR_HI, FIRSR_LO, FITER are unused. 1 Internal rate expanded mode: PHYs[0-31] are controlled by FTIRR[0-3], FIRPER, FIRSR_HI and FIRSR_LO. Underrun status for PHYs[0-31] is available by FIRER. This bit should be set only in transmit master multi-PHY mode. In this mode mixing of internal rate and external rate is not enabled. RMII Loopback diagnostic mode (Ethernet mode): 0 Normal mode 1 Loopback mode RMII reference clock rate for 50 Mhz input clock from external oscillator (Ethernet mode): 0 50 Mhz (for Fast Ethernet) 1 5 Mhz (for 10BaseT) Reserved, should be cleared. 1 LPB 2 CLK 3–7 — 30.3 FCC Protocol-Specific Mode Registers (FPSMRx) The functionality of the FCC varies according to the protocol selected by GFMR[MODE]. Each FCC has an additional 32-bit, memory-mapped, read/write protocol-specific mode register (FPSMR) that configures them specifically for a chosen mode. The section for each specific protocol describes the FPSMR bits. 30.4 FCC Data Synchronization Registers (FDSRx) Each FCC has a 16-bit, memory-mapped, read/write data synchronization register (FDSR) that specifies the pattern used in the frame synchronization procedure of the synchronous protocols. In the totally transparent protocol, the FDSR should be programmed with the preferred SYNC pattern. For Ethernet protocol, it should be programmed with 0xD555. For the ATM protocol, FSDRx is used to generate a constant byte for the HEC. It does not generate the HEC; instead it only outputs this constant byte as a ‘placeholder’ for the HEC. This byte is then replaced by the ATM PHY with the actual value. At reset, FDSRx defaults to 0x7E7E (two HDLC flags), so it does not need to be written for HDLC mode. The FDSR contents are always sent lsb first. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-8 Freescale Semiconductor Fast Communications Controllers (FCCs) 0 7 8 15 Field Reset R/W Addr 0 1 1 SYN2 1 1 1 1 0 R/W 0 1 1 SYN1 1 1 1 1 0 0x1130C (FDSR1), 0x1132C (FDSR2), 0x1132C (FDSR3) Figure 30-4. FCC Data Synchronization Register (FDSR) 30.5 FCC Transmit-on-Demand Registers (FTODRx) If no frame is being sent by the FCC, the CP periodically polls the R bit of the next TxBD to see if the user has requested a new frame/buffer to be sent. Polling occurs every 256 serial transmit clocks. The polling algorithm depends on the FCC configuration, as shown in the following equations: Fast Ethernet: 10BaseT: 256 clocks / 25 MHz = 10 µs 256 clocks / 2.5 MHz = 100 µs The user, however, can request that the CP begin processing the new frame/buffer without waiting the normal polling time. For immediate processing, after setting TxBD[R], set the transmit-on-demand (TOD) bit in the transmit-on-demand register (FTODR) twice to activate. If TOD is set only once, the new frame/buffer will not be transmitted until the next periodic polling request. This feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful in LAN-type protocols where maximum interframe GAP times are limited by the protocol specification. Since the transmit-on-demand feature gives a high priority to the specified TxBD, it can conceivably affect the servicing of the other FCC FIFO buffers. Therefore, it is recommended that the transmit-on-demand feature be used only for a high-priority TxBD and when transmission on this FCC has not occurred for a given time period, which is protocol-dependent. If a new TxBD is added to the BD table while preceding TxBDs have not completed transmission, the new TxBD is processed immediately after the older TxBDs are sent. 0 1 15 Field TOD Reset R/W Addr — 0000_0000_0000_0000 R/W 0x11308 (FTODR1), 0x11328 (FTODR2), 0x11348 (FTODR3) Figure 30-5. FCC Transmit-on-Demand Register (FTODR) Fields in the FTODR are described in Table 30-4. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-9 Fast Communications Controllers (FCCs) . Table 30-4. FTODR Field Descriptions Field Name 0 TOD Description Transmit on demand 0 Normal polling. 1 The CP gives high priority to the current TxBD and begins sending the frame does without waiting for the normal polling time to check TxBD[R]. TOD is cleared automatically. Reserved, should be cleared. 1–15 — 30.6 FCC Buffer Descriptors Data associated with each FCC is stored in buffers. Each buffer is referenced by a buffer descriptor (BD). All of the transmit BDs for an FCC are grouped into a TxBD circular table with a programmable length. Likewise, receive BDs form an RxBD table. The user can program the start address of the BD tables anywhere in system memory. See Figure 30-6. Dual-Port RAM System Memory Tx Buffer Descriptors Status and Control FCCx TxBD Table FCCx RxBD Table Pointer (RBASE) FCCx TxBD Table Pointer (TBASE) Data Length Buffer Pointer Tx Buffer Rx Buffer Descriptors FCCx RxBD Table Status and Control Data Length Buffer Pointer Rx Buffer Figure 30-6. FCC Memory Structure The format of transmit and receive BDs, shown in Figure 30-7, is the same for every FCC mode of operation except ATM mode; see Section 31.10.5, “ATM Controller Buffer Descriptors (BDs).” The first 16 bits in each BD contain status and control information, which differs for each protocol. The second 16 bits indicate the data buffer length in bytes (the wrap bit is the BD table length indicator). The remaining 32-bits contain the 32-bit address pointer to the actual buffer in memory. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-10 Freescale Semiconductor Fast Communications Controllers (FCCs) 0 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 Status and Control Data Length High-Order Data Buffer Pointer Low-Order Data Buffer Pointer Figure 30-7. Buffer Descriptor Format For frame-based protocols, a message can reside in as many buffers as necessary (transmit or receive). Each buffer has a maximum length of (64K–1) bytes. The CP does not assume that all buffers of a single frame are currently linked to the BD table. It does assume, however, that unlinked buffers are provided by the core soon enough to be sent or received. Failure to do so causes an error condition being reported by the CP. An underrun error is reported in the case of transmit; a busy error is reported in the case of receive. Because BDs are prefetched, the receive BD table must always contain at least one empty BD to avoid a busy error; therefore, RxBD tables must always have at least two BDs. The BDs and data buffers can be anywhere in the system memory. The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC is enabled, it starts with the first BD in that FCC’s TxBD table. When the CP detects that TxBD[R] is set, it begins processing the buffer. The CP detects that the BD is ready either by polling the R bit periodically or by the user writing to the FTODR. When the data from the BD has been placed in the transmit FIFO buffer, the CP moves on to the next BD, again waiting for the R bit to be set. Thus, the CP does no look-ahead BD processing, nor does it skip over BDs that are not ready. When the CP sees the wrap (W) bit set in a BD, it goes back to the beginning of the BD table after processing of the BD is complete. After using a BD, the CP normally clears R (not-ready); thus, the CP does not use a BD again until the BD has been prepared by the core. Some protocols support continuous mode, which allows repeated transmission and for which the R bit remains set (always ready). The CP uses RxBDs in a similar fashion. Once the receive side of an FCC is enabled, it starts with the first BD in the FCC’s RxBD table. Once data arrives from the serial line into the FCC, the CP performs the required protocol processing on the data and moves the resultant data to the buffer pointed to by the first BD. Use of a BD is complete when no room is left in the buffer or when certain events occur, such as the detection of an error or end-of-frame. Regardless of the reason, the buffer is then said to be closed and additional data is stored using the next BD. Whenever the CP needs to begin using a BD because new data is arriving, it checks the E bit of that BD. This check is made on a prefetched copy of the current BD. If the current BD is not empty, it reports a busy error. However, it does not move from the current BD until it is empty. Because there is a periodic prefetch of the RxBD, the busy error may recur if the BD is not prepared soon enough. When the CP sees the W bit set in a BD, it returns to the beginning of the BD table after processing of the BD is complete. After using a BD, the CP clears the E bit (not empty) and does not use a BD again until the BD has been processed by the core. However, in continuous mode, available to some protocols, the E bit remains set (always empty). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-11 Fast Communications Controllers (FCCs) 30.7 FCC Parameter RAM Each FCC parameter RAM area begins at the same offset from each FCC base area. The protocol-specific portions of the FCC parameter RAM are discussed in the specific protocol descriptions. Table 30-5. shows portions common to all FCC protocols. Some parameter RAM values must be initialized before the FCC is enabled; other values are initialized/written by the CP. Once initialized, most parameter RAM values do not need to be accessed by user software because most activity centers around the TxBDs and RxBDs rather than the parameter RAM. However, if the parameter RAM is accessed, note the following: • Parameter RAM can be read at any time. • Tx parameter RAM can be written only when the transmitter is disabled—after a STOP TRANSMIT command and before a RESTART TRANSMIT command or after the buffer/frame finishes transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT command. • Rx parameter RAM can be written only when the receiver is disabled. Note the CLOSE RXBD command does not stop reception, but it does allow the user to extract data from a partially full Rx buffer. • See Section 30.12, “Disabling the FCCs On-the-Fly.” Some parameters in Table 30-5. are not described and are listed only to provide information for experienced users and for debugging. The user need not access these parameters in normal operation. Table 30-5. FCC Parameter RAM Common to All Protocols Except ATM Offset1 0x00 Name RIPTR Width Description Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless it is stated otherwise in the protocol specification. Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless it is stated otherwise in the protocol specification. . Hword Reserved, should be cleared. Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver can write fewer bytes to the buffer than MRBLR if a condition such as an error or end-of-frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied buffers should be at least as large as the MRBLR. Note that FCC transmit buffers can have varying lengths by programming TxBD[Data Length], as needed, and are not affected by the value in MRBLR. MRBLR is not intended to be changed dynamically while an FCC is operating. Change MRBLR only when the FCC receiver is disabled. Word Receive internal state. The high byte, RSTATE[0–7], contains the function code register; see Section 30.7.1, “FCC Function Code Registers (FCRx).” RSTATE[8–31] is used by the CP and must be cleared initially. 0x02 TIPTR 0x04 0x06 — MRBLR 0x08 RSTATE MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-12 Freescale Semiconductor Fast Communications Controllers (FCCs) Table 30-5. FCC Parameter RAM Common to All Protocols Except ATM (continued) Offset1 0x0C Name RBASE Width Description Word RxBD base address (must be divisible by eight). Defines the starting location in the memory map for the FCC RxBDs. This provides great flexibility in how FCC RxBDs are partitioned. By selecting RBASE entries for all FCCs and by setting the W bit in the last BD in each BD table, the user can select how many BDs to allocate for the receive side of every FCC. The user must initialize RBASE before enabling the corresponding channel. Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or erratic operation occurs. Hword RxBD status and control. Reserved for CP use only. Hword RxBD data length. A down-count value initialized by the CP with MRBLR and decremented with every byte written by the SDMA channels. Word RxBD data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed. Word Tx internal state. The high byte, TSTATE[0–7], contains the function code register; see Section 30.7.1, “FCC Function Code Registers (FCRx).” TSTATE[8–31] is used by the CP and must be cleared initially. Word TxBD base address (must be divisible by eight). Defines the starting location in the memory map for the FCC TxBDs. This provides great flexibility in how FCC TxBDs are partitioned. By selecting TBASE entries for all FCCs and by setting the W bit in the last BD in each BD table, the user can select how many BDs to allocate for the transmit side of every FCC. The user must initialize TBASE before enabling the corresponding channel. Furthermore, the user should not configure BD tables of two enabled FCCs to overlap or erratic operation occurs. Hword TxBD status and control. Reserved for CP use only. Hword TxBD data length. A down-count value initialized with the TxBD data length and decremented with every byte read by the SDMA channels. Word TxBD data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed. Word RxBD pointer. Points to the next BD that the receiver transfers data to when it is in idle state or to the current BD during frame processing. After a reset or when the end of the BD table is reached, the CP sets RBPTR = RBASE. Although the user need never write to RBPTR in most applications, the user can modify it when the receiver is disabled or when no receive buffer is in use. Word TxBD pointer. Points either to the next BD that the transmitter transfers data from when it is in idle state or to the current BD during frame transmission. After a reset or when the end of the BD table is reached, the CP sets TBPTR = TBASE. Although the user need never write to TBPTR in most applications, the user can modify it when the transmitter is disabled or when no transmit buffer is in use (after a STOP TRANSMIT or GRACEFUL STOP TRANSMIT command is issued and the frame completes transmission). Word Temporary receive CRC Word Reserved Word Temporary transmit CRC Word First word of protocol-specific area 0x10 0x12 0x14 0x18 RBDSTAT RBDLEN RDPTR TSTATE 0x1C TBASE 0x20 0x22 0x24 0x28 TBDSTAT TBDLEN TDPTR RBPTR 0x2C TBPTR 0x30 0x34 0x38 0x3C 1 RCRC — TCRC — Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-13 Fast Communications Controllers (FCCs) 30.7.1 FCC Function Code Registers (FCRx) The function code registers contain the transaction specification associated with SDMA channel accesses to external memory. Figure 30-8 shows the format of the transmit and receive function code registers, which reside at TSTATE[0–7] and RSTATE[0–7] in the FCC parameter RAM (see Table 30-5). 0 1 2 3 4 5 6 7 Field — FCCP GBL BO TC2 DTB BDB Figure 30-8. Function Code Register (FCR x) FCRx fields are described in Table 30-6. Table 30-6. FCRx Field Descriptions Bits 0 1 Name — Reserved, should be cleared. Description FCCP FCC priority. Used in conjunction with PPC_ACR[PRKM] (see section 4.3.2.2) and LCL_ACR[PRKM] (see section 4.3.2.4) for a low request level. 0 Disables CPM low request level to refer to FCCs and MCCs. 1 Enables CPM low request level to refer to FCCs and MCCs. GBL Global. Indicates whether the memory operation should be snooped. 0 Snooping disabled. 1 Snooping enabled. Byte ordering. Used to select the byte ordering of the buffer. If BO is modified on-the-fly, it takes effect at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD. 01 Munged little-endian byte ordering. As data is sent onto the serial line from the data buffer, the LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer double-word. 10 Freescale byte ordering (normal operation). It is also called big-endian byte ordering. As data is sent onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent earlier than the LSB of the same buffer word. Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Indicates on what bus the data is located. 0 On the 60x bus. 1 On the local. Indicates on what bus the BDs are located. 0 On the 60x bus. 1 On the local bus. 2 3–4 BO 5 6 TC2 DTB 7 BDB 30.8 Interrupts from the FCCs Interrupt handling for each of the FCC channels is configured on a global (per channel) basis in the interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L). One bit in each register is used to either mask, enable, or report an interrupt in an FCC channel. The interrupt priority between the FCCs is programmable in the CPM interrupt priority register (SCPRR_H). The interrupt vector register MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-14 Freescale Semiconductor Fast Communications Controllers (FCCs) (SIVEC) indicates which pending channel has highest priority. Registers within the FCCs manage interrupt handling for FCC-specific events. Events that can cause the FCC to interrupt the processor vary slightly among protocols and are described with each protocol. These events are handled independently for each channel by the FCC event and mask registers (FCCE and FCCM). 30.8.1 FCC Event Registers (FCCEx) Each FCC has an FCC event register (FCCE) used to report events. On recognition of an event, the FCC sets its corresponding FCCE bit regardless of the corresponding mask bit. To the user it appears as a memory-mapped register that can be read at any time. Bits are cleared by writing ones; writing zeros has no effect on bit values. FCCE is cleared at reset. Fields of this register are protocol-dependent and are described in the respective protocol sections. 30.8.2 FCC Mask Registers (FCCMx) Each FCC has a read/write FCC mask register (FCCM) used to enable or disable CP interrupts to the core for events reported in an event register (FCCE). Bit positions in FCCM are identical to those in FCCE. Note that an interrupt is generated only if the FCC interrupts are also enabled in the SIU; see Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L).” If an FCCM bit is zero, the CP does not proceed with its usual interrupt handling whenever that event occurs. Any time a bit in the FCCM register is set, a 1 in the corresponding bit in the FCCE register sets the FCC event bit in the interrupt pending register; see Section 4.3.1.4, “SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).” 30.8.3 FCC Status Registers (FCCSx) Each FCC has an 8-bit, read/write FCC status register (FCCS) that lets the user monitor real-time status conditions (flags, idle) on the RXD line. It does not show the status of CTS and CD; their real-time status is available in the appropriate parallel I/O port (see Chapter 41, “Parallel I/O Ports”). 30.9 FCC Initialization The FCCs require a number of registers and parameters to be configured after a power-on reset. The following outline gives the proper sequence for initializing the FCCs, regardless of the protocol used. 1. Write the parallel I/O ports to configure and connect the I/O pins to the FCCs. 2. Write the appropriate port registers to configure CTS and CD to be parallel I/O with interrupt capability or to connect directly to the FCC (if modem support is needed). 3. If the TSA is used, the SI must be configured. If the FCC is used in the NMSI mode, the CPM multiplexing logic (CMX) must still be initialized. 4. Write the GFMR, but do not write the ENT or ENR bits yet. 5. Write the FPSMR. 6. Write the FDSR. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-15 Fast Communications Controllers (FCCs) 7. Initialize the required values for this FCC in its parameter RAM. 8. Clear out any current events in FCCE, as needed. 9. Write the FCCM register to enable the interrupts in the FCCE register. 10. Write the SCPRR_H to configure the FCC interrupt priority. 11. Clear out any current interrupts in the SIPNR_L, if preferred. 12. Write the SIMR_L to enable interrupts to the CP interrupt controller. 13. Issue an INIT TX AND RX PARAMETERS command (with the correct protocol number). 14. Set GFMR[ENT] and GFMR[ENR]. The first RxBD’s empty bit must be set before the INIT RX COMMAND. However TxBDs can have their ready bits set at any time. Notice that the CPCR does not need to be accessed after a power-on reset until an FCC is to be used. An FCC should be disabled and reenabled after any dynamic change in its parallel I/O ports or serial channel physical interface configuration. A full reset using CPCR[RST] is a comprehensive reset that also can be used. 30.10 FCC Interrupt Handling The following describes what usually occurs within an FCC interrupt handler: 1. When an interrupt occurs, read FCCE to determine interrupt sources. FCCE bits to be handled in this interrupt handler are normally cleared at this time. 2. Process the TxBDs to reuse them if the FCCE[TX,TXE] were set. If the transmit speed is fast or the interrupt delay is long, more than one transmit buffer may have been sent by the FCC. Thus, it is important to check more than just one TxBD during the interrupt handler. One common practice is to process all TxBDs in the interrupt handler until one is found with R set. 3. Extract data from the RxBD if FCCE[RX, RXB, or RXF] is set. If the receive speed is fast or the interrupt delay is long, the FCC may have received more than one receive buffer. Thus, it is important to check more than just one RxBD during interrupt handling. Typically, all RxBDs in the interrupt handler are processed until one is found with E set. Because the FCC prefetches BDs, the BD table must be big enough such that always there will be another empty BD to prefetch. 4. Clear FCCE. 5. Continue normal execution. 30.10.1 FCC Transmit Errors There are four errors in the FCC transmitter that make it necessary for software to act on the transmitter before correct operation can continue. The errors are as follows: • CTS-lost indication in HDLC transmitter (use re-initialization procedure) • Underrun in any of the serial FCC transmitter protocols (use re-initialization procedure) • Late collision in fast Ethernet transmitter (use recovery or re-initialization procedure) • Expiration of retry limit in fast Ethernet (use recovery or re-initialization procedure) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-16 Freescale Semiconductor Fast Communications Controllers (FCCs) In addition to status bits in the current TxBD, these errors are reported via the TXE event bit in the FCCE as a convenience for the user to implement error handling. TXE is a safe indication that a recovery or re-initialization procedure must be started. 30.10.1.1 Re-Initialization Procedure 1. 2. 3. 4. 5. 6. Disable the FCC transmission by clearing GFMR[ENT]. Remember the TBPTR value taken from the FCC parameter RAM. Issue an “INIT TX PARAMS” command using the CPCR. Restore the remembered TBPTR into the FCC parameter RAM. Adjust TxBD handling as described in Section 28.10.1.3. Enable FCC transmission by setting GFMR[ENT]. 30.10.1.2 Recovery Sequence 1. Determine which BD is to be transmitted next and, if necessary, modify BDs. 2. Modify TBPTR field in Parameter RAM to point to next BD (if necessary). 3. Issue a “RESTART TX” command using the CPCR. 30.10.1.3 Adjusting Transmitter BD Handling When a TXE event occurs, the TBPTR may already point beyond BDs still marked as ready due to internal pipelining. If the TBPTR is not adjusted, these BDs would be skipped while still being marked as ready. Software must determine if these BDs should be retransmitted or if they should be skipped, depending on the protocol and application needs. This requires the following steps: 1. From the current TBPTR value, search backwards over all (if any) BDs still marked as ready to find the first BD that has not been closed by the CPM. The search process should stop if the BD to be checked next is not ready or if it is the most recent BD marked as ready by the CPU transmit software. This is to avoid an endless loop in case the CPU software fills the BD ring completely. 2. A) For skipping BDs, manually close all BDs from the BD just found up to and including the BD just before TBPTR. Leave the TBPTR value untouched. B) For retransmitting BDs, change the TBPTR value to point to the BD just found. 30.11 FCC Timing Control When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically controlled by the FCC. GFMR[TCI] is assumed to be cleared, which implies normal transmit clock operation. RTS is asserted when FCC has data to transmit in the transmit FIFO and a falling transmit clock occurs. At this point, the FCC begins sending the data, once the appropriate conditions occur on CTS. In all cases, the first bit of data is the start of the opening flag, or sync pattern. Figure 30-9 shows that the delay between RTS and data is 0 bit times, regardless of the setting of GFMR[CTSS]. This operation assumes that CTS is either already asserted to the FCC or is reprogrammed MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-17 Fast Communications Controllers (FCCs) to be a parallel I/O line, in which case the CTS signal to the FCC is always asserted. RTS is negated one clock after the last bit in the frame. TCLK TXD (Output) RTS (Output) CTS (Input) Note: 1. A frame includes opening and closing flags and syncs, if present in the protocol. First Bit of Frame Data Last Bit of Frame Data Figure 30-9. Output Delay from RTS Asserted If CTS is not already asserted when RTS is asserted, the delays to the first bit of data depend on when CTS is asserted. Figure 30-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit times or no delay, depending on GFMR[CTSS]. TCLK TXD (Output) RTS (Output) CTS (Input) First Bit Of Frame Data Last Bit of Frame Data CTS Sampled Low Note: 1. GFMR[CTSS] = 0. CTSP is a don’t care. TCLK TXD (Output) RTS (Output) CTS (Input) Note: 1. GFMR[CTSS] = 1. CTSP is a don’t care. First Bit of Frame Data Last Bit of Frame Data Figure 30-10. Output Delay from CTS Asserted If it is programmed to envelope the data, CTS must remain asserted during frame transmission or a CTS lost error occurs. The negation of CTS forces RTS high and the transmit data to the idle state. If GFMR[CTSS] = 0, the FCC must sample CTS before a CTS lost is recognized. Otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 30-11. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-18 Freescale Semiconductor Fast Communications Controllers (FCCs) TCLK TXD (Output) RTS (Output) CTS (Input) First Bit of Frame Data Data Forced High RTS Forced High CTS Sampled Low CTS Sampled High CTS Lost Signaled in BD Note: 1. GFMR[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK TXD (Output) RTS (Output) CTS (Input) Note: 1. GFMR[CTSS] = 1. CTSP=0 or no CTS lost can occur. First Bit of Frame Data Data Forced High RTS Forced High CTS Lost Signaled in BD Figure 30-11. CTS Lost NOTE If GFMR[CTSS] = 1, all CTS transitions must occur while the transmit clock is low. Reception delays are determined by CD as Figure 30-12 shows. If GFMR[CDS] = 0, CD is sampled on the rising receive clock edge before data is received. If GFMR[CDS] = 1, CD transitions immediately cause data to be gated into the receiver. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-19 Fast Communications Controllers (FCCs) RCLK RXD (Input) CD (Input) First Bit of Frame Data CD Sampled Low Last Bit of Frame Data CD Sampled High Notes: 1. GFMR[CDS] = 0. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception. RCLK RXD (Input) CD (Input) First Bit of Frame Data CD Assertion Immediately Gates Reception Last Bit of Frame Data CD Negation Immediately Halts Reception Notes: 1. GFMR[CDS] = 1. CDP=0. 2. If CD is negated prior to the last bit of the receive frame, CD lost is signaled in the BD. 3. If CDP=1, CD lost cannot occur and CD negation has no effect on reception. Figure 30-12. Using CD to Control Reception If it is programmed to envelope data, CD must remain asserted during frame transmission or a CD lost error occurs. The negation of CD terminates reception. If [CDS] = 0, CD must be sampled by the FCC before a CD lost is recognized. Otherwise, the negation of CD immediately causes the CD lost condition. NOTE If GFMR[CDS] = 1, all CD transitions must occur while the receive clock is low. 30.12 Disabling the FCCs On-the-Fly Unused FCCs can be temporarily disabled. In this case, a operation sequence is followed that ensures that any buffers in use are closed properly and that new data is transferred to or from a new buffer. Such a sequence is required if the parameters that must be changed are not allowed to be changed dynamically. If the register or bit description states that dynamic changes are allowed, the following sequences are not required and the register or bit may be changed immediately. In all other cases, the sequence should be used. Modifying parameter RAM does not require the FCC to be fully disabled. See the parameter RAM description for when values can be changed. To disable all peripheral controllers, set CPCR[RST] to reset the entire CPM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-20 Freescale Semiconductor Fast Communications Controllers (FCCs) 30.12.1 FCC Transmitter Full Sequence For the FCC transmitter, the full disable and enable sequence is as follows. 1. Issue the STOP TRANSMIT command. This is recommended if the FCC is currently transmitting data because it stops transmission in an orderly way. If the FCC is not transmitting (no TxBDs are ready or the GRACEFUL STOP TRANSMIT command has been issued and completed), then the STOP TRANSMIT command is not required. Furthermore, if the TBPTR is overwritten by the user or the INIT TX PARAMETERS command is executed, this command is not required. 2. Clear GFMR[ENT]. This disables the FCC transmitter and puts it in a reset state. 3. Make changes. The user can modify FCC transmit parameters, including the parameter RAM. To switch protocols or restore the FCC transmit parameters to their initial state, the INIT TX PARAMETERS command must be issued. 4. If an INIT TX PARAMETERS command was not issued in step 3, issue a RESTART TRANSMIT command. 5. Set GFMR[ENT]. Transmission begins using the TxBD that the TBPTR points to as soon as TxBD[R] = 1. 30.12.2 FCC Transmitter Shortcut Sequence A shorter sequence is possible if the user prefers to reinitialize the transmit parameters to the state they had after reset. This sequence is as follows: 1. Clear GFMR[ENT]. 2. Issue the INIT TX PARAMETERS command. Any additional changes can be made now. 3. Set GFMR[ENT]. 30.12.3 FCC Receiver Full Sequence The full disable and enable sequence for the receiver is as follows: 1. Clear GFMR[ENR]. Reception is aborted immediately, which disables the receiver of the FCC and puts it in a reset state. 2. Make changes. The user can modify the FCC receive parameters, including the parameter RAM. If the user prefers to switch protocols or restore the FCC receive parameters to their initial state, the INIT RX PARAMETERS command must be issued. 3. Issue the ENTER HUNT MODE command. This command is required if the INIT RX PARAMETERS command was not issued in step 2. 4. Set GFMR[ENR]. Reception begins immediately using the RxBD that the RBPTR points to if RxBD[E] = 1. 30.12.4 FCC Receiver Shortcut Sequence A shorter sequence is possible if the user prefers to reinitialize the receive parameters to the state they had after reset. This sequence is as follows: 1. Clear GFMR[ENR]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 30-21 Fast Communications Controllers (FCCs) 2. Issue the INIT RX PARAMETERS command. Any additional changes can be made now. 3. Set GFMR[ENR]. 30.12.5 Switching Protocols A user can switch the protocol that the FCC is executing (HDLC) without resetting the board or affecting any other FCC by taking the following steps: 1. Clear GFMR[ENT] and GFMR[ENR]. 2. Issue the INIT TX AND RX PARAMETERS command. This command initializes both transmit and receive parameters. Additional changes can be made in the GFMR to change the protocol. 3. Set GFMR[ENT] and GFMR[ENR]. The FCC is enabled with the new protocol. 30.13 Saving Power Clearing an FCC’s ENT and ENR bits minimizes its power consumption. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 30-22 Freescale Semiconductor Chapter 31 ATM Controller and AAL0, AAL1, and AAL5 NOTE The functionality described in this chapter is not available on the MPC8270. The ATM controller provides the ATM and AAL layers of the ATM protocol using the universal test and operations physical layer (PHY) interface for ATM (UTOPIA level II) for both master and slave modes. It performs segmentation and reassembly (SAR) functions of AAL5, AAL1 circuit emulation service (CES), AAL2, and AAL0, and most of the common parts of the convergence sublayer (CP-CS) of these protocols. For each virtual channel (VC), the controller’s ATM pace control (APC) unit generates a cell transmission rate to implement constant bit rate (CBR), variable bit rate (VBR), available bit rate (ABR), unspecified bit rate (UBR) or UBR+ traffic. To regulate VBR traffic, the APC unit performs a continuous-state leaky bucket algorithm. The APC unit also uses up to eight priority levels to prioritize real-time ATM channels, such as CBR and real-time VBR, over non-real-time ATM channels such as VBR, ABR and UBR. The ATM controller performs the ATM Forum (UNI-4.0) ABR flow control. To perform feedback rate adaptation, it supports forward and backward resource management (RM) cell generation and ATM Forum floating-point calculation. ABR flow control is implemented in hardware and firmware (without software intervention) to prevent potential delays during backward RM cell processing and feedback rate adaptation. The MPC8280 supports a special mode for ATM/TDM interworking. The CPM performs automatic data forwarding between ATM channels and the MCCs’ TDM channels without core intervention. The MPC8280 ATM SAR controller applications are as follows: • ATM line card controllers • ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation) • Residential broadband network interface units (NIU) (ATM-to-Ethernet) • High-performance ATM network interface cards (NIC) • Bridges and routers with ATM interface 31.1 Features The ATM controller has the following features: • Full duplex segmentation and reassembly at 155 Mbps • UTOPIA level II master and slave modes 8/16 bit • AAL5, AAL1, AAL2, AAL0 protocols MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-1 ATM Controller and AAL0, AAL1, and AAL5 • • • • • • • • • • • • • • • Up to 255 active VCs internally, and up to 64K VCs using external memory TM 4.0 CBR, VBR, UBR, UBR+ traffic types VBR type 1 and 2 traffic using leaky buckets (GCRA) TM 4.0 ABR flow control (EFCI and ER) Idle/unassign cells screening/transmission option External and internal rate transmit modes Special mode for ATM-to-TDM or ATM-to-ATM data forwarding CLP and congestion indication marking User-defined cells up to 65 bytes Separate TxBD and RxBD tables for each virtual channel (VC) Special mode of global free buffer pools for dynamic and efficient memory allocation with early packet discard (EPD) support Interrupt report per channel using four priority interrupt queues Compliant with ATMF UNI 4.0 and ITU specification AAL5 cell format — Reassembly – Reassemble PDU directly to external memory – CRC32 check – CLP and congestion report – CPCS_UU, CPI, and length check – Abort message report — Segmentation – Segment PDU directly from external memory – Performs PDU padding – CRC32 generation – Automatic last cell marking – Automatic CPCS_UU, CPI, and length insertion – Abort message option AAL1 cell format — Reassembly – Reassemble PDU directly to external memory – Support for partially filled cells (configurable on a per-VC basis) – Sequence number check – Sequence number protection (CRC-3 and parity) check — Segmentation – Segment PDU directly from external memory – Partially filled cells support (configurable on a per-VC basis) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-2 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 • • • • • • – Sequence number generation – Sequence number protection (CRC-3 and even parity) generation — Structured AAL1 cell format – Automatic synchronization using the structured pointer during reassembly – Structured pointer generation during segmentation — Unstructured AAL1 cell format – Clock recovery using external SRTS (synchronous residual time stamp) logic during reassembly – SRTS generation using external logic during segmentation AAL0 format — Receive – Whole cell is put in memory – CRC10 pass/fail indication — Transmit – Reads a whole cell from memory – CRC10 insertion option AAL1 circuit emulation service (refer to Chapter 32, “ATM AAL1 Circuit Emulation Service,” for more information) AAL2 format — Refer to Chapter 33, “ATM AAL2” Support for user-defined cells — Support cells up to 65 bytes — Extra header insert/load on a per-frame basis — Extra header size has byte resolution — Asymmetric cell size for send and receive — HEC octet insertion option PHY — UTOPIA level II supports 8/16 bits 25/50 MHz – Supports UTOPIA master and slave modes – Supports cell-level handshake – Supports multiple-PHY polling mode ATM pace control (APC) unit — Peak cell rate pacing on a per-VC basis — Peak-and-sustain cell rate pacing using GCRA on a per-VC basis — Peak-and-minimum cell rate pacing on a per-VC basis — Up to eight priority levels — Fully managed by CP with no host intervention MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-3 ATM Controller and AAL0, AAL1, and AAL5 • • • • • Available bit rate (ABR) — Performs ATMF UNI 4.0 ABR flow control on a per-VC basis — Automatic forward-RM, backward-RM cells generation — Automatic feedback rate adaptation — Support for EFCI (explicit forward congestion indication) and ER (explicit rate) — RM cell floating-point calculations — Fully managed by CP with no host intervention Receive address look-up mechanism — Two modes of address look-up are supported – External CAM – Address compression OAM (operations and maintenance) cells — OAM filtering according to PTI field and reserved VCI field — Raw cell queues for transmission and reception — CRC-10 generation/check — Performance monitoring support – Support up to 64 bidirectional block tests simultaneously – Automatic FMC and BRC cell generation and termination – User transmit cell0+1 count – User transmit cell0 count – PM cells time stamp insertion – Block error detection code (BEDC0+1) generation/check – Total receive cell0+1 count – Total receive cell0 count — Specifying channel code for F5 OAM cells ATM layer statistic gathering on a per PHY basis. — UTOPIA receiver error cells count (Rx parity error or short/long cells error) — Misinserted cell count — CRC-10 error cells count (ABR flow only) Memory management — RxBD table per VC with option of global free buffer pool for AAL5 — TxBD table per VC MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-4 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.2 ATM Controller Overview The following sections provide an overview of the transmitter and receiver portions of the ATM controller. 31.2.1 Transmitter Overview Before the transmitter is enabled, the host must initialize the MPC8280 and create the transmit data structure, described in Section 31.10, “ATM Memory Structure.” When data is ready for transmission, the host arranges the BD table and writes the pointer of the first BD in the transmit connection table (TCT). The host issues an ATM TRANSMIT command, which inserts the current channel to the ATM pace control (APC) unit. The APC unit controls the ATM traffic of the transmitter. It reads the traffic parameters of each channel and divides the total bandwidth among them. The APC unit can pace the peak cell rate, peak-and-sustain cell rate (GCRA traffic) or peak-and-minimum cell rate traffic. The APC implements up to eight priority levels for servicing real-time channels before non-real-time channels. The transmitter ATM cell is 53–65 bytes and includes 4 bytes of ATM cell header, a 1-byte HEC, and 48 bytes of payload. The HEC is a constant taken from FDSRx[0–15] when using UTOPIA 16 and from FDSRx[8–15] when using UTOPIA 8; see Section 30.4, “FCC Data Synchronization Registers (FDSRx).” User-defined cells (UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell transfers use the UTOPIA level II, cell-level handshake. Transmission starts when the APC schedules a channel. According to the channel code, the ATM controller reads the channel’s entry in the TCT and opens the first BD for transmission. In auto-VC-off mode, the APC automatically deactivates the current channel when no buffer is ready to transmit. In this case, a new ATM TRANSMIT command is needed for transmission of the VC to resume. 31.2.1.1 AAL5 Transmitter Overview The transmitter reads 48 bytes from the external buffer, adds the cell header, and sends the cell through the UTOPIA interface. The transmitter adds any padding needed and appends the AAL5 trailer in the last cell of the AAL5 frame. The trailer consists of CPCS-UU+CPI, data length, and CRC-32 as defined in ITU I.363. The CPCS-UU+CPI (2-byte entry) can be specified by the user or optionally cleared by the transmitter; see Section 31.10.2.3, “Transmit Connection Table (TCT).” The transmitter identifies the last cell of the AAL5 message by setting the last (L) indication bit in the PTI field of the cell header. An interrupt may be generated to indicate the end of the frame. When the transmission of the current frame ends and no additional valid buffers are in the BD table, the transmit process ends. The transmitter keeps polling the BD table every time this channel is scheduled to transmit. Note that a buffer-not-ready indication during frame transmission aborts the frame transfer. 31.2.1.2 AAL1 Transmitter Overview The MPC8280 supports both structured and unstructured AAL1 formats. For the unstructured format, the transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data field. The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is generated and inserted into the cell. The MPC8280 supports synchronous residual time stamp (SRTS) generation using external PLL. If this mode is enabled, the MPC8280 reads MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-5 ATM Controller and AAL0, AAL1, and AAL5 the SRTS code from the external logic and inserts it into four outgoing cells. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them into the AAL1 user data field. The CP generates the AAL1 PDU header and inserts it into the cell. The header consists of the SN, SNP, and the structured pointer. The MPC8280 supports partially filled cells configured on a per-VC basis. In this mode (TCT[PFM] = 1), only valid octets are copied from the buffer to the ATM cell; the rest of the cell is filled with padding octets. 31.2.1.2.1 AAL1 CES Transmitter Overview Refer to Section 32.2, “AAL1 CES Transmitter Overview.” 31.2.1.3 AAL0 Transmitter Overview No specific adaptation layer is provided for AAL0. The ATM controller reads a whole cell from an external buffer, which always contains exactly one AAL0 cell. The ATM controller optionally generates CRC10 on the cell payload and places it at the end of the payload (CRC10 field). AAL0 mode can be used to send OAM cells or AAL3/4 raw cells. 31.2.1.4 AAL2 Transmitter Overview Refer to Section 33.3.1, “Transmitter Overview.” 31.2.1.5 Transmit External Rate and Internal Rate Modes The ATM controller supports the following two rate modes: • External rate mode—The total transmission rate is determined by the PHY transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts idle/unassign cells to maintain the transmission rate. • Internal rate mode—The total transmission rate is determined by the FCC internal rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal rate mechanism supports up to 4 different rates. Each PHY has its own FTIRR, described in Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” The FTIRR includes the initial value of the internal rate timer. A cell transmit request is sent when an internal rate timer expires. When using internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock the four internal rate timers. 31.2.2 Receiver Overview Before the receiver is enabled, the host must initialize the MPC8280 and create the receive data structure described in Section 31.10, “ATM Memory Structure.” The host arranges a BD table for each ATM channel. Buffers for each connection can be statically allocated (that is, each BD in the BD table is associated with a fixed buffer location) or in the case of AAL5, can be fetched by the CP from a global free buffer pool. See Section 31.10.5, “ATM Controller Buffer Descriptors (BDs).” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-6 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 The receiver ATM cell size is 53–65 bytes. The cell includes: 4 bytes ATM cell header, 1 byte HEC, which can be checked by setting FPSMR[HECC] (refer to Table 31-47), and 48 bytes payload. User-defined cells (UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell transfers use the UTOPIA level II, cell-level handshake. Reception starts when the PHY asserts the receive cell available signal (RxCLAV) to indicate that the PHY has a complete cell in its receive FIFO. The receiver reads a complete cell from the UTOPIA interface and translates the header address (VP/VC) to a channel code by performing an address look-up. If no matches are found, the cell is discarded and the user-network interface (UNI) statistics tables are updated. The receiver uses the channel code to read the channel parameters from the receive connection table (RCT). 31.2.2.1 AAL5 Receiver Overview The receiver copies the 48-byte cell payload to the external buffer and calculates CRC-32 on the entire CPCS-PDU. When the last AAL5 cell arrives, the receiver checks the length, CRC-32, and CPCS-UU+CPI fields and sets the corresponding RxBD status bits. An interrupt may be generated to one of the four interrupt queues. The receiver copies the last cell to memory including the padding and the AAL5 trailer. The CPCS-UU+CPI (16-bit entry) may be read directly from the AAL5 trailer. The ATM controller monitors the CLP and CNG state of the incoming cells. When the message is closed, these events set RxBD[CLP] and RxBD[CNG]. When no buffer is ready to receive cells (busy state), the receiver switches to hunt state and drops all cells associated with the current frame (partial packet discard). The receiver tries to open new buffers for cell reception only after the last cell of the discarded AAL5 frame arrives. 31.2.2.2 AAL1 Receiver Overview The ATM controller supports both AAL1 structured and unstructured formats. For the unstructured format, 47 octets are copied to the current receive buffer. The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is checked. The MPC8280 supports SRTS clock recovery using an external PLL. In this mode, the MPC8280 tracks the SRTS from the four incoming cells and writes the SRTS code to external logic. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” In the unstructured format, when the receive process begins, the receiver hunts for the first cell with a valid sequence number (SN field). When one arrives, the receiver leaves the hunt state and starts receiving. If an SN mismatch is detected, the receiver closes the RxBD, sets the sequence number error flag (RxBD[SNE]), and switches to hunt state, where it stays until a cell with a valid SN field is received. For the structured format, 47 or 46 octets are copied to the current receive buffer. The AAL1 PDU header, which consists of SN and SNP, is checked and the PDU status is written to the BD. In the structured format, when the receive process begins, the receiver hunts for the first cell with a valid structured pointer to gain synchronization. When one arrives, the receiver leaves the hunt state and starts receiving. Then the receiver opens a new buffer. The structured pointer points to the first octet of the structured block, which then becomes the first byte of the new buffer. If an SN mismatch is detected, the ATM receiver closes the current RxBD, sets RxBD[SNE], and returns to the hunt state. The receiver then waits for a cell with a valid structured pointer to regain synchronization. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-7 ATM Controller and AAL0, AAL1, and AAL5 The MPC8280 supports partially filled cells configured on a per-VC basis. In this mode (RCT[PFM] = 1), the ATM controller copies only the valid octets from the cell user data field to the buffer. 31.2.2.2.1 AAL1 CES Receiver Overview Refer to Section 32.3, “AAL1 CES Receiver Overview.” 31.2.2.3 AAL0 Receiver Overview For AAL0, no specific adaptation layer processing is done. The ATM controller copies the whole cell to an external buffer. Each buffer contains exactly one AAL0 cell. The ATM controller calculates and checks the CRC10 of the cell payload and sets RxBD[CRE] if a CRC error occurs. AAL0 mode can be useful for receiving OAM cells or AAL3/4 raw cells. 31.2.2.4 AAL2 Receiver Overview Refer to Section 33.4.1, “Receiver Overview.” 31.2.3 Performance Monitoring The ATM controller supports performance monitoring testing according to ITU I.610. When performance monitoring is enabled, the ATM controller automatically generates and terminates FMCs (forward monitoring cells) and BRCs (backward reporting cells). See Section 31.6.6, “Performance Monitoring.” 31.2.4 ABR Flow Control When AAL5-ABR is enabled, the ATM controller implements the ATM Forum TM 4.0 available-bit-rate flow. It automatically inserts forward- and backward-RM cells into the user cell stream and adjusts the transmission rate according to the backwards RM cell feedback; see Section 31.10.2.2.2, “AAL5-ABR Protocol-Specific RCT.” The ABR flow is controlled on a per-VC basis. 31.3 ATM Pace Control (APC) Unit The ATM pace control (APC) unit schedules the ATM channels for transmitting. While performing this task, the APC unit uses the following parameters: • Frequency (bandwidth) of each ATM channel • ATM traffic pacing—Peak cell rate (PCR), sustain cell rate (SCR), and minimum rate (MCR) • Priority level—Real-time channels (CBR or VBR-RT) are scheduled at high-priority levels; non-real-time channels (VBR-NRT, ABR, UBR) are scheduled at low-priority levels. Up to eight priority levels are available. 31.3.1 APC Modes and ATM Service Types The ATM Forum (http://www.atmforum.com) defines the service types described in Table 31-1. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-8 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-1. ATM Service Types Service Type CBR VBR-RT VBR-NRT ABR1 UBR+ UBR PCR PCR, SCR (peak-and-sustain) PCR, SCR (peak-and-sustain) PCR PCR, MCR (peak-and-minimum) PCR Cell Rate Pacing Real-Time/ Non-Real-Time RT RT NRT NRT NRT NRT Relative Priority 1 (highest) 2 3 4 5 6 (lowest) 1 When ABR flow control is active, the CP automatically adapts the APC parameters PCR, PCR_FRACTION. These parameters function as the channel’s allowed cell rate (ACR). For information about cell rate pacing, see Section 31.3.5, “ATM Traffic Type.” For information about prioritization, see Section 31.3.6, “Determining the Priority of an ATM Channel.” 31.3.2 APC Unit Scheduling Mechanism The APC unit consists of an APC data structure in the dual-port RAM for each PHY and a special scheduling algorithm performed by the CP. Each PHY’s APC data structure includes three elements: an APC parameter table, an APC priority table, and cell transmission scheduling tables for each priority level. (See Section 31.10.4, “APC Data Structure.”) Each PHY’s APC parameter table holds parameters that define the priority table location, the number of priority levels, and other APC parameters. The priority table holds pointers that define the location and size of each priority level’s scheduling table. Each scheduling table is divided into time slots, as shown in Figure 31-1. The user determines the number of ATM cells to be sent each time slot (cells per slot). After a channel is sent, it is removed from the current time slot and advanced to a future time slot according to the channel’s assigned traffic rate (specified in time slots). The PCR parameter in the TCT, or the SCR or MCR parameters in the TCT extension (TCTE) determine the channel’s actual rate. Cells per Slot 9 5 1 6 4 7 8 3 2 Number of Slots Current Slot Cell Rescheduling Figure 31-1. APC Scheduling Table Mechanism MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-9 ATM Controller and AAL0, AAL1, and AAL5 Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to transmit in the same slot are linked to each other using the APC linked-channel field in the TCT. The linked list is not limited; however, if the number of channels for the current slot exceeds the cells per slot parameter (CPS), the extra channels are sent in subsequent time slots. (The rescheduling of extra channels is based on the original slot to maintain each channel’s pace.) Note that a channel can appear only once in the scheduling table at a given time, because each channel has only one APC linked-channel field. 31.3.3 Determining the Scheduling Table Size The following sections describe how to determine the number of cells sent per time slot and the total number of slots needed in a scheduling table. 31.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table The number of cells sent per time slot is determined by the channel with the maximum bit rate; see equation A. The maximum bit rate is achieved when a channel is rescheduled to the next slot. For example, if the line rate is 155.52 Mbps and there are eight cells per slot, equation A yields a maximum VC rate of 19.44 Mbps. (A) Max bit rate = line rate cells per slot Note that a channel can appear only once per time slot; thus, 19.44 Mbps = 155.52Mbps/8. The cells per slot parameter (CPS) affects the cell delay variation (CDV). Because the APC unit does not put cells in a definite order within each time slot (LIFO—last-in/first-out implementation), as CPS increases, the CDV increases. However as CPS decreases, the size of the scheduling table in the dual-port RAM increases and more CPM bandwidth is required. 31.3.3.2 Determining the Number of Slots in a Scheduling Table The number of time slots in a scheduling table is determined by the channel with the minimum bit rate; see equation B. The minimum bit rate is achieved when the channel reschedules only once in a whole table scan. (The maximum schedule advance allowed is equal to number_of_slots-1.) For example, if the line rate is 155.52 Mbps, the minimum bit rate is 32 kbps and the CPS is 4, then, according to equation B, the number of slots should be 1,216. NOTE The following APC configuration is not recommended for values outside the following ranges (PCR = peak cell rate, PCRF = peak cell rate fraction, NOS = number of slots): PCR = 1 and PCRF = 0 PCR = NOS - 1 and PCRF = 0 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-10 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 (B) line rate Min bit rate = (number_of_slots - 1) × cells per slot For the above example, 32 kbps = 155.52 Mbps/((1216-1) × 4). Use equations (A) and (B) to obtain the maximum and minimum bit rates of a scheduling table. For example, given a line rate = 155.52 Mbps, number_of_slots = 1025, and CPS = 8: Max bit rate = (155.52 Mbps)/8 = 19.44 Mbps Min bit rate = (155.52 Mbps)/(1024 × 8) = 18.98 kbps. 31.3.4 Determining the Time-Slot Scheduling Rate of a Channel The time-slot scheduling rate of each ATM channel is defined by equation C. The resulting number of APC slots is written in either TCT[PCR], TCTE[SCR] or TCTE[MCR], depending on the traffic type. (C) Rate [slots] = line rate [bps] VC rate [bps] × cells per slot 31.3.5 ATM Traffic Type The APC uses the cell rate pacing parameters (PCR, SCR, and MCR) to generate CBR, VBR, ABR, UBR+, and UBR traffic. The user determines the kind of traffic that is generated per VC by writing to TCT[ATT] (ATM traffic type); see Section 31.10.2.3, “Transmit Connection Table (TCT).” 31.3.5.1 Peak Cell Rate Traffic Type When the peak cell rate traffic type is selected, the APC schedules channels to transmit according to the PCR and PCR_FRACTION traffic parameters. Other traffic parameters do not apply to this traffic type. 31.3.5.2 Determining the PCR Traffic Type Parameters Suppose a VC uses 15.66 Mbps of the total 155.52 Mbps and CPS = 8. Equation C yields: PCR [slots] = (155.52 Mbps)/(15.66 Mbps × 8) = 1.241 The resulting number of slots is written into TCT[PCR] and TCT[PCR_FRACTION]. Because PCR_FRACTION is in units of 1/256 slots, the fraction must be converted as follows: 1.241 = 1+0.241 × 256/256 =1+ 61.79/256 ~ 1 + 62/256 PCR = 1 PCR_FRACTION = 62 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-11 ATM Controller and AAL0, AAL1, and AAL5 31.3.5.3 Peak and Sustain Traffic Type (VBR) Variable bit rate (VBR) traffic can burst at the peak cell rate as long as the long-term average rate does not exceed the sustainable cell rate. To support VBR channels, the APC implements the GCRA (generic cell rate algorithm) using three parameters—the peak cell rate (PCR), the sustained cell rate (SCR), and burst tolerance (BT), as shown in Figure 31-2. (The GCRA is also known as the leaky bucket algorithm.) Conforming VBR Traffic Incoming cells fill the bucket at the peak cell rate (PCR) or at the SCR if the bucket is full. Burst tolerance (BT) Sustained cell rate (SCR) Figure 31-2. VBR Pacing Using the GCRA (Leaky Bucket Algorithm) When a VBR channel is activated, it bursts at the peak cell rate (PCR) until reaching its initial burst tolerance (BT), which is the buffer length the network allocated for this VC. When the burst limit is reached, the APC reduces the VC’s scheduling rate to the sustained cell rate (SCR). The VC continues sending at SCR as long as TxBDs are ready. However, as each SCR time allotment elapses with no TxBD ready to send, the APC grants the VC a credit for bursting at the peak cell rate (PCR). (Gaining credit implies that the buffer at the switch is not full and can tolerate a burst transmission.) If a TxBD becomes ready, the APC schedules the VC to burst at the PCR as long as credit remains. When the burst credit ends (the network’s UPC leaky bucket reaches its limit), the APC schedules the VC according to SCR. 31.3.5.3.1 Example for Using VBR Traffic Parameters Suppose the traffic parameters of a VBR channel are PCR = 6 Mbps, SCR = 2 Mbps, MBS (maximum burst size) = 1000 cells, and CPS = 8. Equation C (see Section 31.3.4, “Determining the Time-Slot Scheduling Rate of a Channel”) yields the APC parameters, PCR, PCR_FRACTION, SCR, and SCR_FRACTION, which the user writes to the channel’s TCT. PCR [slots] = (155.52 Mbps)/(6 Mbps × 8) = 3.24 3.24 = 3 + 0.24 × 256/256 = 3 + 61.44/256 ~ 3 + 62/256 PCR = 3 PCR_FRACTION = 62 SCR [slots] = (155.52 Mbps)/(2 Mbps × 8) = 9.72 9.72 = 9 + (0.72 × 256/256) = 9 + 184.32/256 ~ 9 + 185/256 SCR = 9 SCR_FRACTION = 185 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-12 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Equation D yields the number of slots the user writes to the channel’s TCT[BT]. (D) BT [slots] = (MBS[cells] - 2) × (SCR[slots] - PCR[slots]) + SCR[slots] = (1000 - 2) × ((9+185/256) - (3+62/256)) + (9 +185/256) = 6477 31.3.5.3.2 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2 The MPC8280 supports two ways to schedule VBR traffic based on the cell loss priority (CLP). When TCTE[VBR2] is cleared, CLP0+1 cells are scheduled by PCR or SCR according to the GCRA state. When TCTE[VBR2] is set, CLP0 cells are still scheduled by PCR or SCR according to the GCRA state, but CLP1 cells are always scheduled by PCR. See Section 31.10.2.3.6, “VBR Protocol-Specific TCTE.” 31.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+) To support UBR+ channels, the APC schedules transmission according to PCR and MCR. For each priority level, the APC maintains a parameter that monitors the traffic load measured as the time-slot delay between the service pointer (pointing to the current time slot waiting transmission) and a real-time slot pointer. If the transmission delay is greater than MDA (maximum delay allowed), the APC begins scheduling channels according to the MCR parameter. If the delay, however, drops below MDA, the APC again schedules channels according to the PCR. Note that in order to guarantee a minimum cell rate for UBR+ channels, there must be enough bandwidth to simultaneously send all possible channels at the MCR. See Section 31.10.2.3.7, “UBR+ Protocol-Specific TCTE.” 31.3.6 Determining the Priority of an ATM Channel The priority mechanism is implemented by adding priority table levels, which point to separate scheduling tables; see Section 31.10.4, “APC Data Structure.” The APC flow control services the APC_LEVEL1 slots first. If there are no cells to send, the APC goes to the next priority level. The APC has up to eight priority levels with APC_LEVEL8 being the lowest. The user specifies the priority of an ATM channel when issuing the ATM TRANSMIT command; see Section 31.14, “ATM Transmit Command.” The real-time channels, CBR and VBR-RT, should be inserted in APC_LEVEL1; non-real-time channels, VBR-NRT, ABR, and UBR should be inserted in lower priority levels. 31.4 VCI/VPI Address Lookup Mechanism The MPC8280 supports two ways to look up addresses for incoming cells: • External CAM lookup • Address compression Writing to GMODE[ALM] (address-lookup-mechanism bit) in the parameter RAM selects the mechanism. Both mechanisms are described in the following sections. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-13 ATM Controller and AAL0, AAL1, and AAL5 31.4.1 External CAM Lookup An external CAM is usually used when the range of VCI/VPI values varies widely or is unknown. Clearing GMODE[ALM] selects the external CAM address lookup mechanism. If there is no match in the external CAM, the cell is considered a misinserted cell. The external CAM can point to internal or external channels (channels whose connection table resides in external memory). The CAM input, shown in Figure 31-3, is the 32-bit cell address: PHY address, GFC + VPI, and VCI. NOTE The bus atomicity mechanism for CAM accesses may not function correctly when the CPM performs a DMA access to an external CAM device. This only impacts systems in which multiple CPMs will access the CAM. 0 3 4 15 16 31 PHY Addr (MPHY) GFC + VPI VCI Figure 31-3. External CAM Data Input Fields The output of the CAM, shown in Figure 31-4, is a 32-bit entry (16-bit channel code and a match-status bit). 0 1 15 16 31 MS — Channel Code Figure 31-4. External CAM Output Fields The external CAM fields are described in Table 31-2. Table 31-2. External CAM Input and Output Field Descriptions Field PHY Addr Description In multiple PHY mode, this field contains the 4 least-significant bits of the current channel’s physical address. Because this CAM comparison field is limited to 4 bits, two CAM devices are needed if using more than 16 PHYs.The msb of the PHY address (bit 4) selects between the two devices. If the msb is zero, the CP accesses the CAM whose address is written in the EXT_CAM_BASE parameter in the parameter RAM; if the msb is set, the CP uses EXT_CAM1_BASE. See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).” In single PHY mode, clear this field. The GFC, VPI, and VCI of the current channel. Pointer to internal or external connection table. Reserved, should be cleared. Match status. 0 Match was found. 1 Match was not found. GFC+VPI, VCI Ch Code — MS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-14 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.4.2 Address Compression The address compression mechanism uses two levels of address translation to help minimize the memory space needed to cover the available address range. The first level of translation (VP-level) uses a look-up table based on the 4-bit PHY address and the 12-bit virtual path identifier; the second level (VC-level) uses the 16-bit virtual channel identifier. If there is no match during address compression, the cell is considered a misinserted cell. During the VP-level translation, VP_MASK in the ATM parameter RAM compresses an incoming cell’s PHY address and VPI to create an index into the VP-level table. The VP-level table entry consists of another mask (VC_MASK) and a pointer to one of the VC-level tables (VCOFFSET). Note that the VP table should reside in the dual-port RAM. In the VC-level translation, the VCI is compressed with the VC_MASK to generate a pointer to the VC-level table entry containing the received cell’s channel code. The VC table should reside in external memory. Figure 31-5 shows an example of address compression. 4 bit PHY Addr 0000 12 bit VPI 0000 00011111 VPpointer 0b00011 0 VP-level addressing table (in dual-port RAM recommended) 32-bit entries 16 bit VC_MASK 16 bit VCOFFSET 31 VPT_BASE VP_MASK 16 bit VCI VCT_BASE 00000111 11110000 VCpointer VC-level addressing tables (in external memory) 32-bit entries 1 bit 15 bit MS — 0 16 bit Ch Code[15–0] 31 Figure 31-5. Address Compression Mechanism Figure 31-5 shows VP_MASK selecting five VPI bits to index the VP-level table. The VP-level table entry contains the 16-bit mask (VC_MASK) and the VC-level table offset (VCOFFSET) for the next level of address mapping. The VC_MASK selects VCI bits 4–10, which is used with VCT_BASE and VCOFFSET MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-15 ATM Controller and AAL0, AAL1, and AAL5 to indicate the received cell’s channel code. Address compression field descriptions are shown in Table 31-3. Table 31-3. Field Descriptions for Address Compression Field PHY Addr Description In multiple PHY mode, this field contains the 4 least-significant bits of the current channel’s physical address. Because this comparison field is limited to 4 bits, two sets of look-up tables are needed if using more than 16 PHYs.The msb of the PHY address (bit 4) selects between the two sets of tables. If the msb is zero, the CP accesses the tables at VPT_BASE and VCT_BASE; if the msb is set, the CP uses VPT1_BASE and VCT1_BASE. See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).” In single PHY mode, clear this field. VCI, VPI The VCI and VPI of the current channel. Ch Code Pointer to internal or external connection table. — MS Reserved, should be cleared. Match status. 0 Match was found. 1 Match was not found. 31.4.2.1 VP-Level Address Compression Table (VPLT) The size of the VP-level table depends on the number of mask bits in VP_MASK. For example, if only one PHY is available (PHY address = 0) and VPMASK = 0b11_1111_1111, VP pointer contains ten bits and the table is 4 Kbytes. Because each VPLT entry is 4 bytes, the address of an entry is VPT_BASE + VP pointer × 4. Each VPLT entry has two parameters: • VC_MASK—A 16-bit VC-level mask for masking the incoming cell’s VCI • VCOFFSET—A 16-bit VC-level table offset from VC_BASE that points to the appropriate VC-level table’s (VCLT) starting address. The address of the VCLT is VC_BASE + VCOFFSET × 4. If the VCLTs are to be placed contiguously in memory, each table’s VCOFFSET depends on the size of preceding tables. Each table’s size depends on the number of ones in VC_MASK. Figure 31-6 gives the general formula for determining VCOFFSET. General formula: VCOFFSET(n+1) = VCOFFSETn + 2(number of ones in VC_MASKn) Figure 31-6. General VCOFFSET Formula for Contiguous VCLTs Table 31-4 shows example VCOFFSET calculations for a VP-level table with four entries. Table 31-4. VCOFFSET Calculation Examples for Contiguous VCLTs VP-Level Table Entry 0 1 VC_MASK 0x0237 0x0230 Number of Ones in VC_MASK 6 3 VC-Level Table Size 26 = 64 entries 23 = 8 entries VCOFFSET 0 64 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-16 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-4. VCOFFSET Calculation Examples for Contiguous VCLTs (continued) VP-Level Table Entry 2 3 VC_MASK 0xA007 x Number of Ones in VC_MASK 5 x VC-Level Table Size 25 = 32 entries x VCOFFSET 64 + 8 = 72 72 + 32 = 104 The MPC8280 can check that all unallocated bits of the PHY + VPI are 0 by setting GMODE[CUAB] (check unallocated bits) in the parameter RAM. If they are not, the cell is considered a misinserted cell. Table 31-5 gives an example of VP-level table entry address calculation. Table 31-5. VP-Level Table Entry Address Calculation Example VPT_BASE 0x0024_0000 VP-Level Table Size 64 entries VP_MASK 0x0237 PHY+VPI 0x0011 VP Pointer 0x09 VP Entry Address VP Base = 0x240000 0x09 x 4 = 0x000024 0x240024 Figure 31-7 shows the VP pointer address compression from Table 31-5. PHY+VPI VP_MASK 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 1 VP Pointer 0 0 1 0 0 1 Figure 31-7. VP Pointer Address Compression 31.4.2.2 VC-Level Address Compression Tables (VCLTs) Each VPLT entry points to a single VCLT. Like the VPLT, the size of each VCLT depends on VC_MASK. Because the VCLT contains word entries, if VC_MASK = 0b11_1111_1111, the table is 4 Kbytes. The address of an entry in this table is VCT_BASE + VCOFFSET × 4 + VCpointer × 4. The MPC8280 can check that all unallocated VCI bits are 0 by setting GMODE[CUAB] (check unallocated bits). If they are not, the cell is considered a misinserted cell. An example of VC-level table entry address calculation is shown in Table 31-6. Note that VCOFFSET is assumed to be 0x100 for this example. Table 31-6. VC-Level Table Entry Address Calculation Example VCT_BASE 0x0084_0000 VCOffset 0x0100 VC-Level Table Size 32 entries VC_MASK 0x0037 VCI 0x0031 VC Pointer 0x19 VC Entry Address VC Base = 0x840000 0x100 x 4 = 0x000400 0x19 x 4 = 0x000064 0x840464 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-17 ATM Controller and AAL0, AAL1, and AAL5 Figure 31-8 shows the VC pointer address compression from Table 31-6. VCI VC_MASK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 VC Pointer 1 1 0 0 1 Figure 31-8. VC Pointer Address Compression 31.4.3 Misinserted Cells If the address lookup mechanism cannot find a match (MS=1), the cell is discarded and ATM layer statistics are updated, as described in Section 31.8, “ATM Layer Statistics.” 31.4.4 Receive Raw Cell Queue Channel one in the RCT is reserved as a raw cell queue. The user should program channel one to operate in AAL0 protocol. The receive raw cell queue is used for removing management cells from the regular cell flow to the host. When a management cell is sent to the receive raw cell queue, the CP sets RxBD[OAM]. The ALL0 BD specifies the channel code associated with the current OAM cell. The following are optionally removed from the regular flow and sent to the raw cell queue: • Segment F5 OAM (PTI = 0b100). To enable F5 segment filtering, set RCT[SEGF]. • End-to-end F5 OAM (PTI = 0b101). To enable F5 end-to-end filtering, set RCT[ENDF]. • RM cells (PTI = 0b110). When ABR flow is enabled the cells are terminated internally; otherwise, they are sent to the raw cell queue. • Reserved PTI value (PTI = 0b111). Always sent to the raw cell queue. • VCI value: 3, 4, 6, 7–15. To enable VCI filtering set the associated bit in the VCIF entry in the parameter RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-18 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Figure 31-9 shows a flowchart of the ATM cell flow. Check address No Discard cell Match Yes No PTI=1xx or VCI=3,4,6,7-15 and filter enable Yes Send cell to VC queue Send cell to raw cell queue Figure 31-9. ATM Address Recognition Flowchart NOTE Even reserved VCI channels should appear in the CAM or address compression tables; otherwise, a cell on a reserved channel will be considered misinserted. 31.5 Available Bit Rate (ABR) Flow Control While CBR service provides a fixed bandwidth and is useful for real-time applications with strictly bounded end-to-end cell transfer delay and cell-delay variation, ABR service is intended for data applications that can adapt to time-varying bandwidth and can tolerate significant cell transfer delay and cell delay variation. The MPC8280 implements the two following mechanisms defined by the ATM Forum TM 4.0 rate-based flow control. • Explicit forward congestion indication (EFCI). The network supplies binary indication of whether congestion occurred along the connection path. This information is carried in the PTI field of the ATM cell header (similar to that used in frame relay). The source initially clears each ATM cell’s EFCI bit, but as the cell passes through the connection, any congested node can set it. The MPC8280 detects this indication and sets the congestion indication (CI) bit in the next backwards RM cell to signal the source end station to reduce its transmission rate. • Explicit rate (ER) feedback. The network carries explicit bandwidth information, to allow the source to adjust its rate. The source sends forward RM cells specifying its chosen transmit rate MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-19 ATM Controller and AAL0, AAL1, and AAL5 (source ER). A congested switch along the network may decrease ER to the exact rate it can support. The destination receives forward RM cells and returns them to the source as backward RM cells. The MPC8280 implements source behavior by adjusting the rate according to each returning backward RM cell’s ER. Explicit rate feedback has several advantages over binary feedback (EFCI). Explicit rate feedback allows immediate source rate adaptation, eliminating rate oscillation caused by incremental rate changes. Using the information in RM cells, the network can allocate bandwidth evenly among active ABR channels. 31.5.1 The ABR Model Figure 31-10 shows the MPC8280’s ABR model. Source Behavior Nrm Data Cells F-RM Cell CCR,ER Turn-around F-RM Cell Destination Behavior B-RM Cell Update Rate ER, CI, NI B-RM Cell Set CI, NI Reduce ER Figure 31-10. MPC8280’s ABR Basic Model The MPC8280 ABR flow control implements both source and destination behavior. The MPC8280’s ABR flowchart is described in Section 31.5.1.3, “ABR Flowcharts.” 31.5.1.1 ABR Flow Control Source End-System Behavior The MPC8280’s implementation of ABR flow control for end-system sources is described in the following steps: 1. An ABR channel’s allowed cell rate (ACR) lies between the minimum cell rate (MCR) and the peak cell rate (PCR). 2. ACR is initialized to the initial cell rate (ICR). 3. An F-RM (Forward-RM) cell is sent for every Nrm data cell sent. If more than Mrm cells are sent and the time elapsed since the last F-RM exceeds Trm, an F-RM cell is sent. 4. When sending an F-RM cell, the current ACR is written in the CCR (current cell rate) field of the RM cell. 5. When B-RM (backward-RM) cell is received with CI = 1 (congestion indication), ACR is reduced by ACR × RDF (rate decrease factor). After the reduction, the new ACR is determined first by letting ACRtemp be the min of (ACR, ER), and then taking the max of (ACRtemp, MCR). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-20 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 6. When B-RM is received with CI=0 and NI=0 (no increase), ACR is increased by RIF × PCR (rate increase factor). The new ACR is determined first by letting ACRtemp be the min of (ACR, ER), and then taking the max of (ACRtemp, MCR). 7. Before sending an F-RM cell, if more than ADTF (ACR decrease time factor) has elapsed since sending the last F-RM cell, ACR is reduced to ICR. In other words, if the source does not fully use its gained bandwidth, it loses it and resumes sending at its initial cell rate. 8. Before sending an F-RM cell and after action 7, if more than Crm F-RM cells were sent since the last B-RM cell was received with BN=0 (backward notification), the ACR is reduced by ACR × CDF (cutoff decrease factor). 9. A source whose ACR is less than the tag cell rate (TCR) sends out-of-rate cells at the TCR. This behavior is intended for sources whose rates were set to zero by the network. These sources should periodically sense the network state by sending out-of-rate RM cells. In this case data cells will not be sent. 10. An RM cell with an incorrect CRC10 is discarded and the UNI statistics tables are updated. 31.5.1.2 ABR Flow Control Destination End-System Behavior The MPC8280’s implementation of ABR flow control for end-system destinations is described in the following steps: 1. A received F-RM cell is turned around and sent as a B-RM cells. 2. The DIR field of the received F-RM cell is changed from 0 to 1 (backward DIR). 3. The CCR and MCR fields are taken from the F-RM and is not changed. 4. The CI bit of the B-RM cell is set if the previous data cell arrived with EFCI = 1 (congestion bit in the ATM cell header). 5. The ER field of the turn around B-RM cells is limited by TCTE[ER-BRM]. 6. If a F-RM cell arrives before the previous F-RM cell was turned around (for the same connection), the new RM cell overwrites the old RM cell. 31.5.1.3 ABR Flowcharts The MPC8280’s ABR transmit and receive flow control is described in the following flowcharts. See Figure 31-11, Figure 31-12, Figure 31-13, and Figure 31-14. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-21 ATM Controller and AAL0, AAL1, and AAL5 Start Channel Tx No ACR < TCR Yes Source End-Sys 9 ACR is low sent only out-of-rate cells at TCR Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = 0, CLP =1) Schedule: Time_to_send = now+1/TCR EXIT ACR>=TCR RM/DATA In Rate Cell Tx Figure 31-11. ABR Transmit Flow MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-22 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 RM/DATA In Rate Cell Tx Source End-Sys 3 No Count >= Nrm or (Count > Mrm and Now ≥ (Last_RM+Trm)) Count=Number of data cells from last F-RM. Nrm=Number of data cells between every RM cell Mrm=Fixed number=2 Trm=Max time between every F-RM Cells. B-RM/DATA In Rate Cell Tx F-RM In Rate Cell Tx Checking “Time-Out Factor” Max time allowed between RM Cells before a rate Decrease is required. Time = Now - Last_RM Yes No Time >ADTF Source End-Sys 7 ACR is too high Idle adjust (“use it or loose it”) Yes ACR = ICR No Unack≥Crm Yes ACR = ACR-ACR × CDF ACR = max(ACR,MCR) Source End-Sys 8 Crm=Max number of F-RM cells without any B-RM cell allowed before rate decrease is required. Unack=Number of F-RM cells sent without any B-RM cell received. Source End-Sys 4 Send RM (DIR = forward, CCR = ACR, ER = PCR, CI = NI = CLP = 0) Count=0 Last_RM = Now First-turn = TRUE Unack = Unack+1 Count = Count+1 First-turn = Flag indicates first turn of RM cell with priority over data cells. EXIT Figure 31-12. ABR Transmit Flow (continued) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-23 ATM Controller and AAL0, AAL1, and AAL5 B-RM/DATA In Rate Cell Tx No Turn-around and (First-turn or not data-in-queue) Destination End-Sys 1,2,3,4 B-RM In Rate Cell Tx Yes CI-TA = CI-TA || CI-VC Send RM cell (DIR = backwards, CCR-TA, ER-TA, MCR-TA, CI-TA, NI-TA, CLP=0) CI-VC = 0 Turn-around = first-turn = FALSE Count = Count+1 EXIT Data Cell Tx Send Data Cell CLP = EFCI = 0 Count = Count+1 Schedule:Time_to_send = Now+1/ACR EXIT Figure 31-13. ABR Transmit Flow (continued) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-24 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 B-RM Cells Rx No CI = 1 Yes Source End-Sys 5 ACR = ACR-ACR×RDF No NI = 0 Yes Source End-Sys 1, 6 ACR = ACR+RIF×PCR ACR = min(ACR,PCR) ACR = min(ACR,ER) ACR = max(ACR,MCR) Source End-Sys 5, 6 No BN = 0 Yes The source generate this RM Unack = 0 Unack = Number of F-RM in absence of B-RM = 0 EXIT Figure 31-14. ABR Receive Flow MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-25 ATM Controller and AAL0, AAL1, and AAL5 31.5.2 RM Cell Structure Table 31-7 describes the structure of the RM cell supported by the MPC8280. For more information, see the ABR flow-control traffic management specification (TM 4.0) on the ATM Forum website. Table 31-7. Fields and their Positions in RM Cells Fields Header ID DIR BN CI NI RA — ER CCR MCR QL SN — — CRC-10 Octet 1–5 6 7 7 7 7 7 7 8–9 10–11 12–13 14–17 18–21 22–51 52 52 53 Bits All All 0 1 2 3 4 5–7 All All All All All All 0–5 6–7 All ATM cell header Protocol ID Direction of RM cell (0 = forward, 1 = backward) Backward notification (BN = 0, the cell was generated by the source; BN=1, the cell was generated by the network or by the destination) Congestion indication. (1 = congestion, 0 = otherwise) No increase indication. (1 = no increase allowed, 0 = otherwise) Not used (ATM Forum ABR) Reserved, should be cleared. Explicit rate; see Section 31.5.2.1 Current cell rate; see Section 31.5.2.1 Minimum cell rate; see Section 31.5.2.1 Not used (ATM Forum ABR) Not used (ATM Forum ABR) Reserved, should be cleared. Reserved, should be cleared. CRC-10 0 0 0x6A for each byte 0 0 0 Description Value RM-VCC PTI=6 1 31.5.2.1 RM Cell Rate Representation Rates in the RM cells are represented in a binary floating-point format using a 5-bit exponent (e), a 9-bit mantissa (m), and a 1-bit nonzero flag (nz), as shown in Figure 31-15. 0 1 2 6 7 15 0 nz Exponent Mantissa Figure 31-15. Rate Format for RM Cells The rate (in cells/second) is calculated as in Figure 31-16. e m Rate = 2 × ⎛ 1 + ---------⎞ × nz ⎝ 512⎠ Figure 31-16. Rate Formula for RM Cells MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-26 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Initialize the traffic parameters (ER, MCR, PCR, or ICR) in the ABR protocol-specific connection tables using the rate formula in Figure 31-16. 31.5.3 ABR Flow Control Setup Follow these steps to setup ABR flow control: 1. Initialize the ABR data structure: RCT, TCT, RCT-ABR protocol-specific, TCTE-ABR protocol-specific. 2. Initialize ABR global parameters in the parameter RAM. See Section 31.10.1, “Parameter RAM.” 3. Program the AAL-type in the RCT and TCT to AAL5 and set TCT[ABRF]. NOTE ABR flow control is available only with AAL5. 4. The time stamp timer generates the RM cell’s time stamp, which the ABR flow control monitors to maintain source behavior in steps #3 and #7 of Section 31.5.1.1, “ABR Flow Control Source End-System Behavior.” Enable the time stamp timer by writing to the RTSCR; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” 5. Initialize the ABR parameters (CPS_ABR and LINE_RATE_ABR) in the APCT; see Section 31.10.4.1, “APC Parameter Tables.” Note that when using ABR, the CPS (cells per slot) parameter in the APCPT should be a power of two. 6. Finally, send the ATM TRANSMIT command to restart channel transmission. 31.6 OAM Support This section describes the MPC8280’s support for ATM-layer (F4 out-of-band, and F5 in-band) operations and maintenance (OAM) of connections. Alarm surveillance, continuity checking, remote defect indication, and loopback cells are supported using OAM receive and transmit AAL0 cell queues. Using dedicated support, performance management block tests can be performed on up to 64 connections simultaneously. The CP automatically inserts forward monitoring cells (FMC) and generates backward-reporting cells (BRC) as recommended by ITU I.610. 31.6.1 ATM-Layer OAM Definitions Table 31-8. Pre-Assigned Header Values at the UNI Use GFC xxxx xxxx xxxx xxxx VPI aaaa_aaaa aaaa_aaaa aaaa_aaaa aaaa_aaaa VCI 0000_0000_0000_0011 0000_0000_0000_0100 aaaa_aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa PTI 0a0 0a0 100 101 CLP a a a a Table 31-8 lists pre-assigned header values at the user-network interface (UNI). Segment OAM F4 flow cell End-to-end OAM F4 flow cell Segment OAM F5 flow cell End-to-end OAM F5 flow cell a = available for use by the appropriate ATM layer function MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-27 ATM Controller and AAL0, AAL1, and AAL5 Table 31-9 lists pre-assigned header values at the network-node interface (NNI). Table 31-9. Pre-Assigned Header Values at the NNI Use Segment OAM F4 flow cell End-to-end OAM F4 flow cell Segment OAM F5 flow cell End-to-end OAM F5 flow cell VPI aaaa_aaaa_aaaa aaaa_aaaa_aaaa aaaa_aaaa_aaaa aaaa_aaaa_aaaa VCI 0000_0000_0000_0011 0000_0000_0000_0100 aaaa_aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa PTI 0a0 0a0 100 101 CLP a a a a a= available for use by the appropriate ATM layer function 31.6.2 Virtual Path (F4) Flow Mechanism The F4 flow is designated by pre-assigned virtual channel identifiers within the virtual path. The following two kinds of F4 flows can exist simultaneously: • End-to-end (identified as VCI 4)—This flow is used for end-to-end VPC operations communications. Cells inserted into this flow can be removed only by the endpoints of the virtual path. Segment (identified as VCI 3)—This flow is used for communicating operations information within one VPC link or among multiple interconnected VPC links. The concatenation of VPC links is called a VPC segment. Cells inserted into this flow can be removed only by the segment endpoints, which must remove these cells to prevent confusion in adjacent segments. • 31.6.3 Virtual Channel (F5) Flow Mechanism The F5 flow is designated by pre-assigned payload type identifiers. The following two kinds of F5 flow can exist simultaneously: • End-to-end (identified by PTI = 5)—This flow is used for end-to-end VCC operations communications. Cells inserted into this flow can be removed only by VC endpoints. • Segment (identified by PTI = 4)—This flow is used for communicating operations information with the bound of one VCC link or multiple interconnected VCC links. A concatenation of VCC links is called a VCC segment. Segment endpoints must remove these cells to prevent confusion in adjacent segments. 31.6.4 Receiving OAM F4 or F5 Cells OAM F4/F5 flow cells are received using the raw cell queue, described in Section 31.4.4, “Receive Raw Cell Queue.” An F4/F5 OAM cell which does not appear in the CAM or address compression tables is considered a misinserted cell. 31.6.5 Transmitting OAM F4 or F5 Cells OAM F4/F5 flow cells are sent using the usual AAL0 transmit flow. For OAM F4/F5 cell transmission, program channel one in the TCT to operate in AAL0 mode. Enable the CR10 (CRC-10 insertion) mode as MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-28 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 described in Section 31.10.2.3.3, “AAL0 Protocol-Specific TCT.” Prepare the OAM F4/F5 flow cell and insert it in an AAL0 TxBD. Finally, issue a ATM TRANSMIT command to send the OAM cell. For multiple PHYs, use several AAL0 channels—each PHY should have one transmit raw cell queue that is associated with its scheduling table. A series of OAM cells can be sent using one ATM TRANSMIT command by creating a table of AAL0 TxBDs. If the channel’s TCT[AVCF] (auto VC off) is set, the transmitter automatically removes it from the APC (that is, it does not generate periodic transmit requests for this channel after all AAL0 BDs are processed). 31.6.6 Performance Monitoring A connection’s performance is monitored by inspecting blocks of cells (delimited by forward monitoring cells) sent between connection or segment endpoints. Each FMC contains statistics about the immediately preceding block of cells. When an endpoint receives an FMC, it adds the statistics generated locally across the same block to produce a backward reporting cell (BRC), which is then returned to the opposite endpoint. The MPC8280 can run up to 64 bidirectional block tests simultaneously. When a bidirectional test is run, FMCs are generated for one direction and checked for the opposite. Figure 31-17 shows the FMC and BRC cell structure. Header = 5 bytes 4 OAM Cell Type 4 Function Type Payload = 48 bytes 10 45 x 8 6 Function Specific Reserved CRC-10 Fields GFC/ VPI VPI VCI PTI CLP HEC 0010 = Performance Management 0000 = Forward Monitoring (FMC) 0001 = Backward Reporting (BRC) Monitoring Total User Sequence Cell 0+1 Number Count (MCSN) (TUC0+1) 1 octet 1 2 Block Error Detection Code (BEDC0+1)1 2 octets Total User Cell 0 Count (TUC0) 2 octets TimeStamp (TSTP) 4 octets Unused Total Received Cells 0 (TRCC0) 2 2 octets Block Error Result (BLER) 2 1 octet Total Received Cells 0+1 (TRCC0+1)2 2 octets 2 octets 29 octets BEDC0+1 appears in FMCs only. TRCC0, BLER, and TRCC0+1 appear in BRCs only. Figure 31-17. Performance Monitoring Cell Structure (FMCs and BRCs) Table 31-10 describes performance monitoring cell fields. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-29 ATM Controller and AAL0, AAL1, and AAL5 Table 31-10. Performance Monitoring Cell Fields Field MCSN TUC0+1 TUC0 TSTP BEDC0+1 TRCC0 BLER TRCC0+1 Description Monitoring cell sequence number. The sequence number of the performance monitoring cell (modulo 256). Total user cell 0+1 count. Counts all user cells (modulo 65,536) sent before the FMC was inserted. Total user cell 0 count. Counts CLP = 0 user cells (modulo 65,536) sent before the FMC was inserted. Time stamp. Used to indicate when the cell was inserted. Block error detection code. Even parity over the payload of the block of user cells sent since the last FMC. Total received cell count 0. Counts CLP=0 user cells (modulo 65,536) received before the FMC was received. Block error result. Counts error parity bits detected by the BEDC of the received FMC. Total received cell count 0+1. Counts all user cells (modulo 65,536) received before the FMC was received. BRC Yes Yes Yes Yes No Yes Yes Yes FMC Yes Yes Yes Yes Yes No No No 31.6.6.1 Running a Performance Block Test For bidirectional PM block tests, FMCs are monitored at the receive side and generated at the transmit side. The following setup is required to run a bidirectional PM block test on an active VCC: 1. Assign one of the available 64 performance monitoring tables by writing to both RCT[PMT] and TCT[PMT] and initializing the one chosen. See Section 31.10.3, “OAM Performance Monitoring Tables.” 2. For PM F5 segment termination set RCT[SEGF]; for PM F5 end-to-end termination set RCT[ENDF]. 3. Finally, set the channel’s RCT[PM] and TCT[PM] and the receive raw cell’s RCT[PM]. For unidirectional PM block tests: • For PM block monitoring only, set only the RCT fields above. • For PM block generation only, set only the TCT fields above. To run a block test on a VPC, assign all the VCCs of the tested VPC to the same performance monitoring table. Configure RCT[PMT] and TCT[PMT] to specify the performance monitoring table associated with each F4 channel. 31.6.6.2 PM Block Monitoring PM block monitoring is done by the receiver. After initialization (see Section 31.6.6.1), whenever a cell is received for a VCC or VPC, the TRCC counters are incremented and the BEDC is calculated. When an FMC is received, the CP adds the BRC fields into the cell payload (TRCC0, TRCC0+1, BLER) and transfers the cell to the receive raw cell queue. The user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-30 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Before the BRC is transferred to the transmit raw cell queue, the PM function type should be changed to backward reporting and additional checking should be done regarding the BLER field. If the sequence numbers (MCSN) of the last two FMCs are not sequential or the differences between the last two TUCs and the last two TRCCs are not equal, BLER should be set to all ones (see the ITU I.610 recommendation). NOTE TRCCs are free-running counters (modulo 65,536) that count user cells received. The total received cells of a particular block is the difference between TRCC values of two consecutive BRC cells. TRCC values are taken from a VC’s performance monitoring table. 31.6.6.3 PM Block Generation The transmitter generates the PM block. Each time the transmitted cell count parameter (TCC) in the performance monitoring table reaches zero, the CP inserts an FMC into the user cell stream. The CP copies the FMC header, SN-FMC, TUC0+1, TUC0, BEDC0+1-Tx from the performance monitoring table and inserts them into the FMC payload. The TSTP value (FMC time stamp field) is taken from the MPC8280 time stamp timer; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” The TUCs are free-running counters (modulo 65,536) that count transmitted user cells. The total transmitted cells of a particular block is the difference between TUC values of two consecutive FMCs. The BEDC (BIP-16, bit interleaved parity) calculation is done on the payload of all user cells of the current tested block. The performance monitoring block can range from 1 to 2K cells, as specified in the BLCKSIZE parameter in the performance monitoring table; see Section 31.10.3, “OAM Performance Monitoring Tables.” In Figure 31-18, the performance monitoring block size is 512 cells. For every 512 user cells sent, the ATM controller automatically inserts an FMC into the regular cell stream as defined in ITU I.610. When an FMC is received, the ATM controller adds the BRC fields to the cell payload and sends the cell to the raw cell queue. The user can monitor the BRC cell results and transfer the cell to the transmit raw cell queue. 512 User Cells 3 FMC Cell TUC0 TUC0+1 BEDC TSTP Data Cell Data Cell 2 FMC Cell TUC0 TUC0+1 BEDC TSTP Destination BRC’s Transmit Stream 1 BRC Cell 2 BRC Cell TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP Data Cell Data Cell 512 User Cells 1 FMC Cell TUC0 TUC0+1 BEDC TSTP 3 BRC Cell TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP Source Cells Stream TUC0 TUC0+1 TRCC0 TRCC0+1 BLER TSTP Figure 31-18. FMC, BRC Insertion MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-31 ATM Controller and AAL0, AAL1, and AAL5 31.6.6.4 BRC Performance Calculations BRC reception uses the regular AAL0 raw cell queue. On receiving two consecutive BRC cells, the management layer can calculate the following: • The difference between two TUCs (Nt) • The difference between two TRCCs (Nr) Information about the connection can be gained by comparing Nt and Nr: • If Nt > Nr, the difference indicates the number of lost cells of this block test. • If Nt < Nr, the difference indicates the number of misinserted cells of this block test. • When Nt = Nr, no cells are lost or misinserted. 31.7 User-Defined Cells (UDC) Typical ATM cells are 53 bytes long and consist of a 4-byte header, 1-byte HEC, and 48-byte payload. The MPC8280 also supports user-defined cells with up to 12 bytes of extra header fields for internal information for switching applications. This choice is made during initialization by writing to the FPSMR; see Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR).” As shown in Figure 31-19, the extra header size can vary between 1 to 12 bytes (byte resolution) and the HEC octet is optional. Extra Header (1–12 Bytes) ATM Cell Header (4 Bytes) + HEC (optional) Payload (48 Bytes) Figure 31-19. Format of User-Defined Cells For AAL5 and AAL1 CES the extra header is taken from the Rx and Tx BDs. The transmitter reads the extra header from the UDC TxBD and adds it to each ATM cell associated with the current buffer. At the receive side, the extra header of the last cell in the current buffer is written to the UDC RxBD. For AAL0 the extra header is attached to the regular ATM cell in the buffer. The transmitter reads the extra header and the ATM cell from the buffer. The receiver writes the extra header and the regular ATM cell to the buffer. 31.7.1 UDC Extended Address Mode (UEAD) For external CAM accesses, the UDC extra header can be used to supply extra routing information; see Figure 31-20. If GMODE[UEAD] = 1, two bytes of the UDC header are used as extensions to the ATM address and the CAM match cycle performs a double-word access. UEAD_OFFSET in the parameter RAM determines the offset from the beginning of the UDC extra header to the UEAD entry. The offset should be half-word aligned (even address). See Section 31.10.1, “Parameter RAM.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-32 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 16-bit CAM data in field: 0 UEAD 4-bit PHY addr 15 16 19 20 12-bit VPI 31 32 16-bit VCI 47 Figure 31-20. External CAM Address in UDC Extended Address Mode 31.8 ATM Layer Statistics ATM layer statistics can be used to identify problems, such as the line-bit error rate, that affect the UNI performance. Statistics are kept in three 16-bit wrap-around counters: • UTOPIA error dropped cells count—Counts cells discarded due to UTOPIA errors: Rx parity errors and short or long cells. • Misinserted dropped cell count—Counts cells discarded due to address look-up failure. • CRC10 error dropped cell count—Counts cells discarded due to CRC10 errors. (ABR only). Counters are implemented in the dual-port RAM for each PHY device. The counters of each PHY are located in the UNI statistics table, described in Section 31.10.7, “UNI Statistics Table.” 31.9 ATM-to-TDM Interworking The MPC8280 supports ATM and TDM interworking. The MCCs and their corresponding SIs handle the TDM data processing. (See Chapter 29, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial Interface with Time-Slot Assigner.”) The ATM controller processes the ATM data. Possible interworking applications include the following: • Circuit emulation service (CES) • Carrying voice over ATM • Multiplexing several low speed services, such as voice and data, onto one ATM connection Data forwarding between the ATM controller and an MCC can be done in two ways: • Core intervention. When an MCC receive buffer is full and its RxBD is closed, the MCC interrupts the core. The core copies the MCC’s receive buffer pointer to an ATM TxBD and sets the ready bit (TxBD[R]). Similarly, when an ATM receive buffer is full and its RxBD is closed, the core services the ATM controller’s interrupt by copying the ATM receive buffer pointer to an MCC TxBD and setting TxBD[R]. This mode is useful when additional core processing is required. • Automatic data forwarding. This mode enables automatic data forwarding between AAL1/AAL0 and transparent mode over a TDM interface. 31.9.1 Automatic Data Forwarding The basic concept of automatic data forwarding is to program the ATM controller and the MCC to process the same BD table, as shown in Figure 31-21. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-33 ATM Controller and AAL0, AAL1, and AAL5 BD Table TDM Interface MCC Transmitter MCC Tx ptr UTOPIA Interface ATM* Receiver ATM Rx ptr 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Buffer 1 Buffer 2 Buffer 3 Buffer 4 Buffer 5 BD Table UTOPIA Interface ATM Transmitter ATM Tx ptr TDM Interface MCC* Receiver MCC Rx ptr 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Buffer 1 Buffer 2 Buffer 3 Buffer 4 Buffer 5 * The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit. Figure 31-21. ATM-to-TDM Interworking When going from TDM to ATM, the MCC receiver routes data from the TDM line to a specific BD table. The ATM controller transmitter is programmed to operate on the same table. When the MCC fills a receive buffer, the ATM controller sends it. The two controllers synchronize on the MCC’s RxBD[E] and the ATM controller’s TxBD[R]. When going from ATM to TDM, the ATM receiver reassembles data received from a particular channel to a specific BD table. The MCC transmitter is programmed to operate on the same table. When the ATM controller fills a receive buffer, the MCC controller sends it. The controllers synchronize on the ATM controller’s RxBD[E] and the MCC’s TxBD[R]. The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity. That is, both receivers receive data into buffers whose RxBD[E] = 0 and set RxBD[E] when a buffer is full. For the ATM receiver, set RCT[INVE] of the AAL1- and AAL0-specific areas of the receive connection table; see Section 31.10.2.2, “Receive Connection Table (RCT).” For the MCC receiver, set CHAMR[EP]; see Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.” 31.9.2 Using Interrupts in Automatic Data Forwarding The core can program the MCC and ATM interrupt mechanism to trigger interrupts for events such as a buffer closing or transfer errors. The interrupt mechanism can be used to synchronize the start of the automatic bridging process. For example, to start the MCC transmitter after a specific buffer reaches the ATM receiver (the buffering is required to cope with the ATM network’s CDV), set ATM RxBD[I]. When the receive buffer is full, the RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit polarity), and the core is interrupted. The core then starts the MCC transmitter. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-34 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.9.3 Timing Issues Use of the TDM interface assumes that all communicating entities are synchronized (that is, that they are using a synchronized serial clock). If the TDM interfaces are not synchronized, a slip can occur in the reassembly buffer. If a buffer-not-ready event occurs at the MCC transmitter, the user must restart the MCC transmit channel. If a buffer-not-ready event occurs at the ATM transmitter, the user must restart the ATM transmit channel. 31.9.4 Clock Synchronization (SRTS and Adaptive FIFOs) Clock synchronization methods, such as using a time stamp (SRTS) or adaptive FIFOs, prevent buffer slipping during reassembly. The SRTS method may be implemented using external logic. The MPC8280 can read the SRTS from external logic and insert it into AAL1 CES cells, and can track the SRTS from AAL1 CES cells and deliver it to external logic. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” Alternatively, an adaptive FIFOs method can be implemented using the core to maintain the bridging buffer at a mid-level point. The difference between the MCC and ATM data pointers is a measure of buffer synchronization. The core calculates the difference between pointers at regular intervals and adapts the TDM clock accordingly to hold the difference constant. 31.9.5 Mapping TDM Time Slots to VCs Using the MCC and the SI, any TDM time-slot combination can be routed to a specific data buffer. (See Chapter 29, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial Interface with Time-Slot Assigner.”) The same data buffers should be used by the ATM controller to route receive and transmit data. For information about ATM buffers see Section 31.10.5, “ATM Controller Buffer Descriptors (BDs).” 31.9.6 CAS Support For applications requiring channel-associated signaling (CAS), circuit emulation with CAS requires additional core processing. External framers perform the CAS manipulation through a serial or parallel interface. When the MCC receives a multi-frame block, it generates an interrupt to the core. The core reads the CAS block from the external framer and places it at the end of the ATM data buffer after the structured multi-frame block. The core then passes the buffer pointer to the ATM controller, and the controller packs the data and CAS block into AAL1 CES cells. All AAL1 CES functions, such as generating PDU-headers and structured pointers, operate normally. When the ATM controller receives a multi-frame block, it generates an interrupt to the core. The core reads the CAS block from the data buffer and writes it to the external framer. The core then moves the buffer pointer to the MCC. The buffer’s data length should not include the CAS octets. To optimize the process, the framer may interrupt the core only when the CAS information changes. (CAS information changes slowly.) The core can keep the CAS block in memory and connect to the framer only when the CAS changes. The core can use regular read and write cycles when connecting to the framer through a parallel interface. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-35 ATM Controller and AAL0, AAL1, and AAL5 The MCC and ATM controller should be synchronized with the framer’s multi-frame block boundary. At the ATM side, the structured block size should equal the multi-frame block size plus the size of the CAS block so that the structured pointer, inserted by the ATM controller, points to the start of the structured data block. At the MCC side, the MCC must to be synchronized with the super frame sync signal. This synchronization can be achieved by external logic that triggers on the super frame sync signal and starts delivering the frame sync to the MCC. When loss of super frame synchronization occurs, this logic should reset and trigger again on the next super frame indication. 31.9.7 Trunk Condition According to the Bellcore standard, the interworking function (IWF) should be able to transmit special payload on both ATM and TDM channels to signal alarm conditions (Bellcore TR-NWT-000170). The core can be used to generate the trunk condition payload in special buffers (or existing buffers) for the ATM controller or MCC. 31.9.8 ATM-to-ATM Data Forwarding Automatic data forwarding can be used to switch ATM AAL0 cells from one ATM port to another without core intervention. The ATM receiver and transmitter should be programed to process the same BD table. When the ATM receiver fills an AAL0 buffer, the ATM transmitter sends it. The ATM receiver and transmitter are synchronized using the same mechanism as described for ATM-to-TDM automatic forwarding; see Section 31.9.1, “Automatic Data Forwarding.” 31.10 ATM Memory Structure The ATM memory structure, described in the following sections, includes the parameter RAM, the connection tables, OAM performance monitoring tables, the APC data structure, BD tables, the AAL1 CES sequence number protection table and the UNI statistics table. 31.10.1 Parameter RAM When configured for ATM mode, the FCC parameter RAM is mapped as shown in Table 31-11. Note that there are additional parameters for AAL1 CES (refer to Table 32-4) and AAL2 (refer to Table 33-13). Table 31-11. ATM Parameter RAM Map Offset1 0x00–0x3F 0x40 Name — RCELL_TMP_ BASE TCELL_TMP_BASE Width — Reserved, should be cleared. Description Hword Rx cell temporary base address. Points to a total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64 byte aligned. User-defined offset from dual-port RAM base. Hword Tx cell temporary base address. Points to total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined offset from dual-port RAM base. 0x42 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-36 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-11. ATM Parameter RAM Map (continued) Offset1 0x44 Name UDC_TMP_BASE Width Description Hword UDC mode only. Points to a total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined offset from dual-port RAM base. Hword Internal receive connection table base. User-defined offset from dual-port RAM base. Hword Internal transmit connection table base. User-defined offset from dual-port RAM base. Hword Internal transmit connection table extension base. User-defined offset from dual-port RAM base. Word Reserved, should be cleared. Word External receive connection table base. User-defined. Word External transmit connection table base. User-defined. Word External transmit connection table extension base. User-defined. Hword User-defined cells mode only. Offset to the user-defined extended address (UEAD) in the UDC extra header. Must be an even address. See Section 31.10.1.1, “Determining UEAD_OFFSET (UEAD Mode Only).” If RCT[BO] = 01, UEAD_OFFSET should be in little-endian format. For example, if the UEAD entry is the first half word of the extra header in external memory, UEAD_OFFSET should be programmed to 2 (second half word entry in dual-port RAM). Hword Reserved, should be cleared. Hword Performance monitoring table base. User-defined offset from dual-port RAM base. Hword APC parameter table base address. User-defined offset from dual-port RAM base. Hword Free buffer pool parameter table base. User-defined offset from dual-port RAM base. Hword Interrupt queue parameter table base. User-defined offset from dual-port RAM base. — Reserved, should be cleared. 0x46 0x48 0x4A 0x4C 0x50 0x54 0x58 0x5C INT_RCT_BASE INT_TCT_BASE INT_TCTE_BASE — EXT_RCT_BASE EXT_TCT_BASE EXT_TCTE_BASE UEAD_OFFSET 0x5E 0x60 0x62 0x64 0x66 0x68 0x6A — PMT_BASE APCP_BASE FBT_BASE INTT_BASE — UNI_STATT_BASE Hword UNI statistics table base. User-defined offset from dual-port RAM base. Note that this must be set up according to Section 29.10.7, “UNI Statistics Table>” It is not optional. Word BD table base address extension. BD_BASE_EXT[0–7] holds the 8 most-significant bits of the Rx/Tx BD table base address. BD_BASE_EXT[8–31] should be zero. User-defined. Word Base address of the address compression VP table/external CAM. User-defined. Word Base address of the address compression VC table. User-defined. Word Base address of the address compression VP1 table/EXT CAM1. User-defined. 0x6C BD_BASE_EXT 0x70 0x74 0x78 VPT_BASE / EXT_CAM_BASE VCT_BASE VPT1_BASE / EXT_CAM1_BASE MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-37 ATM Controller and AAL0, AAL1, and AAL5 Table 31-11. ATM Parameter RAM Map (continued) Offset1 0x7C 0x80 0x82 Name VCT1_BASE VP_MASK VCIF Width Description Word Base address of the address compression VC1 table. User-defined. Hword VP mask for address compression lookup. User-defined. Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCIF bit = 1 the cell is sent to the raw cell queue. VCIF[0–2, 5] should be zero. See Section 31.10.1.2, “VCI Filtering (VCIF).” Hword Global mode. User-defined. See Section 31.10.1.3, “Global Mode Entry (GMODE).” Hword The information field associated with the last host command. User-defined. See Section 31.14, “ATM Transmit Command.” Hword Hword 0x84 0x86 0x88 0x8A 0x8C 0x90 0x94 0x98 GMODE COMM_INFO — CRC32_PRES CRC32_MASK AAL1_SNPT_BASE Word Reserved, should be cleared. Word Preset for CRC32. Initialize to 0xFFFF_FFFF. Word Constant mask for CRC32. Initialize to 0xDEBB_20E3. Hword AAL1 SNP protection look-up table base address. (AAL1 CES only.) The 32-byte table resides in dual-port RAM. AAL1_SNPT_BASE must be halfword-aligned. User-defined offset from dual-port RAM base. See Section 31.10.6, “AAL1 Sequence Number (SN) Protection Table.” Hword Reserved, should be cleared. Word External SRTS logic base address. AAL1 CES only. Should be 16-byte aligned. The four least-significant bits are taken from SRTS_DEV in the AAL1-specific area of the connection table entries. 0x9A 0x9C — SRTS_BASE 0xA0 IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/unassign cell template (little-endian format). Should be 64-byte aligned. User-defined offset from dual-port RAM base. The ATM header should be 0x0000_0000 or 0x0100_0000 (CLP=1). IDLE/UNASSIGN_SIZE EPAYLOAD Trm Hword Idle/unassign cell size. 52 in regular mode; 53–64 in UDC mode. Word Reserved payload. Initialize to 0x6A6A_6A6A. Word (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” For time stamp prescalar of 1µs, program Trm to be 100 ms/1µs = 100,000. Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. 0xA2 0xA4 0xA8 0xAC 0xAE Nrm Mrm MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-38 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-11. ATM Parameter RAM Map (continued) Offset1 0xB0 Name TCR Width Description Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the APC minimum cell rate (MCR) should be at least TCR. Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used by the CP. Should be 16-byte aligned. User-defined offset from dual-port RAM base. — • For additional AAL1 CES parameters, refer to Table 32-4. • For additional AAL2 parameters, refer to Table 33-13. 0xB2 ABR_RX_TCTE — 1 Additional parameters Offset from FCC base: 0x8400 (FCC1) and 0x8500 (FCC2); see Section 14.5.2, “Parameter RAM.” 31.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only) The UEAD_OFFSET value is based on the position of the user-defined extended address (UEAD) in the UDC extra header. Table 31-12 shows how to determine UEAD_OFFSET: first determine the halfword-aligned location of the UEAD, and then read the corresponding UEAD_OFFSET value. Offset 0 0x0 0x4 0x8 UEAD_OFFSET = 0x2 UEAD_OFFSET = 0x6 UEAD_OFFSET = 0xA 15 16 31 UEAD_OFFSET = 0x0 UEAD_OFFSET = 0x4 UEAD_OFFSET = 0x8 Table 31-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header 31.10.1.2 VCI Filtering (VCIF) VCI filtering enable bits are shown in Figure 31-22. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field 0 0 0 VC3 VC4 0 VC6 VC7 VC8 VC9 VC10 VC11 VC12 VC13 VC14 VC15 Figure 31-22. VCI Filtering Enable Bits Table 31-13 describes the operation of the VCI filtering enable bits. Table 31-13. VCI Filtering Enable Field Descriptions Bits 0–2, 5 3, 4, 6, 7–15 Name — VCx Clear these bits. VCI filtering enable 0 Do not send cells with this VCI to the raw cell queue. 1 Send cells with this VCI to the raw cell queue. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-39 ATM Controller and AAL0, AAL1, and AAL5 31.10.1.3 Global Mode Entry (GMODE) Figure 31-23 shows the layout of the global mode entry (GMODE). 0 1 2 3 4 5 6 7 8 9 10 11 1 12 13 14 15 Field 0 0 GBL 0 0 0 ALB CTB REM 0 IMA_EN UEAD CUAB EVPT 0 ALM Figure 31-23. Global Mode Entry (GMODE) 1 MPC8264 and MPC8266 only. Table 31-14 describes GMODE fields. Table 31-14. GMODE Field Descriptions Bits 0–1 2 3–5 6 Name — GBL — ALB Reserved, should be cleared. Global. Asserting GBL enables snooping of connection tables and address compression tables. GBL should not be asserted if any of the related DMAs will access the local bus. Reserved, should be cleared. Address look up bus for CAM or address compression tables 0 Reside on the 60x bus. 1 Reside on the local bus. External connection tables bus 0 Reside on the 60x bus. 1 Reside on the local bus. Receive emergency mode 0 Enable REM operation. When the receive FIFO is full, the ATM transmitter stops sending data cells until the receiver emergency state is cleared (FIFO not full). The transmitter pace is maintained, although a small CDV may be introduced. This mode enables the receiver to receive bursts of cells above the steady state performance. 1 Disable REM operation. Note that to check system performance the user may want to set this bit. Reserved, should be cleared. Description 7 CTB 8 REM1 9–10 10 — IMA_E MPC8264 and MPC8266 only: Enable the associated FCC in IMA mode. N 0 Default. FCC Enabled in normal ATM mode 1 FCC enabled in IMA mode Note that individual PHYs of those IMA-mode enabled FCCs may still be set for non-IMA functionality via the IMAPHY register in the IMA root table. UEAD User-defined cells extended address mode. See Section 31.7.1, “UDC Extended Address Mode (UEAD).” 0 Disable UEAD mode. 1 Enable UEAD mode. Check unallocated bits 0 Do not check unallocated bits during address compression. 1 Check unallocated bits during address compression. External address compression VP table 0 VP table resides in dual-port RAM. 1 VP table reside in external memory. 11 12 CUAB 13 EVPT MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-40 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-14. GMODE Field Descriptions (continued) Bits 14 15 Name — ALM Reserved, should be cleared. Address look-up mechanism. See Section 31.4, “VCI/VPI Address Lookup Mechanism.” 0 External CAM lookup. 1 Address compression. Description 1 MPC8264 and MPC8266 only: GMODE[REM] must be set to disable receive emergency mode. If receive emergency mode were enabled, it would result in IMA transmit protocol violations in cases of system overload, potentially avoiding protocol errors in the IMA receiver at the expense of generating IMA transmit protocol violations to the far end. Rather than causing erratic transmit operation, it is better to set GMODE[REM] and deal with the IMA receive protocol violations locally. Note further that the system should be designed such that overload problems never occur in the field; any errors due to overload should be eliminated during system design and debug. 31.10.2 Connection Tables (RCT, TCT, and TCTE) The receive and transmit connection tables, RCT and TCT, store host-initialized connection parameters after connection set-up. These include AAL type, connection traffic parameters, BD parameters and temporary parameters used during segmentation and reassembly (SAR). The transmit connection table extension (TCTE) supports special connections that use ABR, VBR or UBR+ services. Each connection table entry resides in a 32-byte space. Table 31-15 lists sizes for RCT, TCT, and TCTE. Table 31-15. Receive and Transmit Connection Table Sizes ATM Service Class CBR, UBR service ABR, VBR, UBR+ service RCT 32 bytes 32 bytes TCT 32 bytes 32 bytes TCTE — 32 bytes NOTE An ATM channel is considered internal if its tables are in an internal dual-port RAM; it is considered external if its tables are in external memory.To improve performance, store parameters for fast channels in internal dual-port RAM and parameters for slower channels in external memory. Connection tables for external channels are read and written from external memory each time the CP processes a cell. The CP does, however, minimize memory access time by burst fetching the 32-byte entry and writing back only the first 24 bytes. In all connection tables, fields which are not used must be cleared. 31.10.2.1 ATM Channel Code Each ATM channel has a channel code used as an index to the channel’s connection table entry. The first channel in the table has channel code one, the second has channel code two, and so on. Codes of 255 or less indicate internal channels; codes greater than 255 indicate external channels. Channel code one is reserved as the raw cell queue and cannot be used for another purpose. The channel code is used to specify MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-41 ATM Controller and AAL0, AAL1, and AAL5 a VC when sending a ATM TRANSMIT command, initiating the external CAM or address compression tables, and when the CP sends an interrupt to an interrupt queue. Example: Suppose a configuration supports 1,024 regular ATM channels. To allocate 4 Kbytes of dual-port RAM space to the internal connection table, determine that channel codes 0–63 are internal (64 VCs × 64 bytes (RCT and TCT) = 4 K). Channels 0–1 are reserved. The remaining 962 (1024 - 62) external channels are assigned channel codes 256–1217. See Figure 31-24. Dual-Port RAM INT_RCT_BASE Reserved RCT256 Raw Cell (AAL0) RCT257 RCT2 RCT258 RCT3 RCT259 EXT_RCT_BASE External Memory RCT63 RCT1217 Figure 31-24. Example of a 1024-Entry Receive Connection Table The general formula for determining the real starting address for all internal and external connection table entries is as follows: Connection table base address + (channel code × 32) Thus, the real starting address of the RCT entry associated with channel code 3 is as follows: INT_RCT_BASE+ (3 × 32) = INT_RCT_BASE + 96 Even though it produces a gap in the connection table, the first external channel’s real starting address of the RCT entry (channel code 256) is as follows: EXT_RCT_BASE+ (256 × 32) = EXT_RCT_BASE + 8192 See Section 31.10.1, “Parameter RAM,” to find all the connection table base address parameters. (The transmit connection table base address parameters are INT_TCT_BASE, EXT_TCT_BASE, INT_TCTE_BASE, and EXT_TCTE_BASE.) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-42 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.10.2.2 Receive Connection Table (RCT) Figure 31-25 shows the format of an RCT entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 — GBL BO — DTB BIB — — BUFM SEGF ENDF — ABRF INTQ AAL Offset + 0x02 — INF Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 • Offset + 0x12 • • Offset + 0x14 • • Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — PMT RX Data Buffer Pointer (RXDBPTR) Cell Time Stamp RBD_Offset Protocol Specific For AAL5,Section 31.10.2.2.1, “AAL5 Protocol-Specific RCT.” For AAL2, Section 33.4.4.1, “AAL2 Protocol-Specific RCT.” For AAL1, Section 31.10.2.2.3, “AAL1 Protocol-Specific RCT.” For AAL1 CES, Section 32.9.1.1, “AAL1 CES Protocol-Specific RCT” For AAL0, Section 31.10.2.2.4, “AAL0 Protocol-Specific RCT.” MRBLR RBD_BASE RBD_BASE — PM Figure 31-25. Receive Connection Table (RCT) Entry MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-43 ATM Controller and AAL0, AAL1, and AAL5 Table 31-16 describes RCT fields. Table 31-16. RCT Field Descriptions Offset 0x00 Bits 0–1 2 3–4 Name — GBL BO Reserved, should be cleared. Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. Byte ordering—used for data buffers. 00 Reserved 01 Munged little endian 1x Big endian Reserved, should be cleared. Data buffers bus 0 Data buffers reside on the 60x bus. 1 Data buffers reside on the local bus. BD, interrupt queues, free buffer pool and external SRTS logic bus 0 Reside on the 60x bus. 1 Reside on the local bus. Note that when using AAL5 or AAL1 CES in UDC mode, BDs must be placed on the same bus (RCT[DTB] = RCT[BIB]). This is necessary because in UDC mode the user-defined header, which is part of the cell data, is read using the same bus configuration (byte ordering and bus type) as the payload. Therefore, if data is placed on the 60x bus and the BD on the local bus, the SDMA accesses the UDC header on the 60x bus with the address of the local bus. Reserved, should be cleared. Buffer mode. (AAL5 only) See Section 31.10.5.3, “ATM Controller Buffers.” 0 Static buffer allocation mode. Each BD is associated with a dedicated buffer. 1 Global buffer allocation mode. Free buffers are fetched from global free buffer pools. OAM F5 segment filtering 0 Do not send cells with PTI = 100 to the raw cell queue. 1 Send cells with PTI = 100 to the raw cell queue. OAM F5 end-to-end filtering 0 Do not send cells with PTI=101 to the raw cell queue. 1 Send cells with PTI=101 to the raw cell queue. Reserved, should be cleared. Points to one of four interrupt queues available. Description 5 6 — DTB 7 BIB 8 9 — BUFM 10 SEGF 11 ENDF 12–13 14–15 — INTQ MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-44 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-16. RCT Field Descriptions (continued) Offset 0x02 Bits 0 1 Name — INF Description Internal use only. Should be cleared. (AAL5 only) Indicates the receiver state. Initialize to 0 0 In idle state. 1 In AAL5 frame reception state. Internal use only. Should be cleared. (AAL5 only). Controls ABR flow. 0 ABR flow control is disabled. 1 ABR flow control is enabled. AAL type 000 AAL0—Reassembly with no adaptation layer 001 AAL1—ATM adaptation layer 1 protocol 010 AAL5—ATM adaptation layer 5 protocol 100 AAL2—ATM adaptation layer 2 protocol. Refer to Chapter 33, “ATM AAL2.” 101 AAL1_CES—Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.” All others reserved. Receive data buffer pointer. Holds real address of current position in the Rx buffer. Used for reassembly time-out. Whenever a cell is received, the MPC8280 time stamp timer is sampled and written to this field. See Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” 2–11 12 — ABRF 13–15 AAL 0x04 0x08 — — RxDBPTR Cell Time Stamp 0x0C 0x0E–0x18 0x1A 0x1C — RBD_Offset RxBD offset from RBD_BASE. Points to the channel’s current BD. User-initialized to 0; updated by the CP. — Protocol-specific area. Maximum receive buffer length. Used in both static and dynamic buffer allocation. Reserved, should be cleared. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed on-the-fly. — 0–1 2–7 MRBLR — PMT 8–15 0x1E 0–11 12–14 15 RBD_BASE RxBD base. Points to the first BD in the channel’s RxBD table. The 8 most-significant bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four least-significant bits of the address are taken as zeros. — PM Reserved, should be cleared. Performance monitoring. Can be changed on-the-fly. 0 No performance monitoring for this VC. 1 Perform performance monitoring for this VC. Whenever a cell is received for this VC the performance monitoring table that its code is written in the PMT field is updated. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-45 ATM Controller and AAL0, AAL1, and AAL5 31.10.2.2.1 AAL5 Protocol-Specific RCT Figure 31-26 shows the AAL5 protocol-specific area of an RCT entry. 0 15 Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 — TML RX CRC RBDCNT — RXBM RXFM — BPOOL Figure 31-26. AAL5 Protocol-Specific RCT Table 31-17 describes AAL5 protocol specific RCT fields. Table 31-17. RCT Settings (AAL5 Protocol-Specific) Offset 0x0E 0x10 0x14 0x16 0x18 Bits — — — — 0–7 8 Name TML RxCRC RBDCNT — — RXBM Description Total message length. This field is used by the CP. CRC32 temporary result. RxBD count. Indicates how may bytes remain in the current Rx buffer. RBDCNT is initialized with MRBLR whenever the CP opens a new buffer. Reserved, should be cleared. Reserved, should be cleared. Receive buffer interrupt mask. Determines whether the receive buffer event is disabled. Can be changed on-the-fly. 0 The event is disabled for this channel. (The RXB event is not sent to the interrupt queue when receive buffers are closed.) 1 The event is enabled for this channel. Receive frame interrupt mask. Determines whether the receive frame event is disabled. Can be changed on-the-fly. 0 The event is disabled for this channel. (RXF event is not sent to the interrupt queue.) 1 The event is enabled for this channel. Reserved, should be cleared. Buffer pool. Global buffer allocation mode only. Points to one of four free buffer pools. See Section 31.10.5.2.4, “Free Buffer Pool Parameter Tables.” 9 RXFM 10–13 14–15 — BPOOL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-46 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.10.2.2.2 AAL5-ABR Protocol-Specific RCT Figure 31-27 shows the AAL5-ABR protocol-specific area of an RCT entry. 0 15 Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 RDF AAL5 Protocol-Specific PCR RIF AAL5 Protocol-Specific Figure 31-27. AAL5-ABR Protocol-Specific RCT Table 31-18 describes AAL5-ABR protocol-specific RCT fields. Table 31-18. ABR Protocol-Specific RCT Field Descriptions Offset 0x0E 0x16 Bits — — Name — PCR AAL5 protocol-specific Peak cell rate. The peak number of cells per second of the current ABR channel. The ACR (allowed cell rate) never exceeds this value. PCR uses the ATMF TM 4.0 floating-point format. Rate decrease factor for the current ABR channel. Controls the decrease in cell transmission rate upon receipt of a backward RM cell. RDF represents a negative exponent of two, that is, the decrease factor = 2-RDF. The decrease factor ranges from 1/32768 (RDF=0xF) to 1 (RDF=0). Rate increase factor of the current ABR channel. Controls the increase in the cell transmission rate upon receipt of a backward RM cell. RIF represents a negative exponent of two, that is, the increase factor = 2-RIF. The increase factor ranges from 1/32768 (RIF=0xF) to 1 (RIF=0). AAL5 protocol-specific Description 0x18 0–3 RDF 4–7 RIF 8–15 — 31.10.2.2.3 AAL1 Protocol-Specific RCT Figure 31-28 shows the AAL1 protocol-specific area of an RCT entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 — SRTS_TMP — — — Valid Octet Size (VOS) PFM SRT INVE STF — — SRTS_DEV SPV RBDCNT Structured Pointer (SP) — SNEM — RXBM — SN Figure 31-28. AAL1 Protocol-Specific RCT MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-47 ATM Controller and AAL0, AAL1, and AAL5 Table 31-19 describes AAL1 protocol-specific RCT fields. Table 31-19. AAL1 Protocol-Specific RCT Field Descriptions Offset 0x0E Bits 0–7 8 Name — PFM Reserved, should be cleared. Partially filled mode. 0 Partially filled cells mode is not used. 1 Partially filled cells mode is used. The receiver copies only valid octets from the AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the AAL1 user data field is specified in the VOS (valid octet size) field. Synchronous residual time stamp. Unstructured format only. The MPC8280 supports clock recovery using an external SRTS PLL. The MPC8280 tracks the SRTS from the incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external SRTS device. Every eight cells the CP writes a valid SRTS to external logic. (See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.”) 0 SRTS mode is not used. 1 SRTS mode is used. Inverted empty. 0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty). 1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty). Structured format 0 Unstructured format is used. 1 Structured format is used. Reserved, should be cleared. Description 9 SRT 10 INVE 11 STF 12–15 0x10 0–3 4–11 12–15 0x12 0–1 2–7 — SRTS_TMP Used by the CP to store the received SRTS code. After a cell with SN = 7 is received, the CP writes the SRTS code to the external SRTS device. — Reserved, should be cleared. SRTS_DEV Selects an SRTS device, whose address is SRTS_BASE[0–27] + SRTS_DEV[28–31]. The 16 byte-aligned SRTS_BASE is taken from the parameter RAM. — VOS Reserved, should be cleared. Valid octet size. Specifies the number of valid octets from the beginning of the AAL1 user data field. For unstructured, service values 1–47 are valid; for structured service, values 1-46 are valid. Partially filled cell mode only. Structured pointer valid. Should be user-initialized user to zero. Structured format only. Structured pointer. Used by the CP to calculate the structured pointer. This field should be initialized by the user to zero. Used in structured format only. RxBD count. Indicates how may bytes remain in the current Rx buffer. Initialized with MRBLR whenever the CP opens a new buffer. Reserved, should be cleared. Sequence number. Used by the CP to check incoming cell’s sequence number. 8 9–15 0x14 0x16 — 0–12 13–15 SPV SP RBDCNT — SN MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-48 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-19. AAL1 Protocol-Specific RCT Field Descriptions (continued) Offset 0x18 Bits 0–3 4 Name — SNEM Reserved, should be cleared. Sequence number error flag interrupt mask 0 This mode is disabled. 1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt queue even if RCT[RXBM] is cleared. Note that this mode is the buffer error reporting mechanism during automatic data forwarding (ATM-to-TDM bridging) when no buffer processing is required (RCT[RXBM]=0). Reserved, should be cleared. Receive buffer interrupt mask 0 The receive buffer event of this channel is disabled. (The event is not sent to the interrupt queue.) 1 The receive buffer event of this channel is enabled. Reserved, should be cleared. Description 5–7 8 — RXBM 9–15 — 31.10.2.2.4 AAL0 Protocol-Specific RCT Figure 31-29 shows the layout for the AAL0 protocol-specific RCT. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 — — 0 1 INVE — — RXBM — Figure 31-29. AAL0 Protocol-Specific RCT Table 31-20 describes AAL0 protocol specific RCT fields. Table 31-20. AAL0-Specific RCT Field Descriptions Offset 0x0E Bits 0-7 8-9 10 Name — 0b01 INVE Reserved, should be cleared. Must be programmed to 0b01 for AAL0. Inverted empty. 0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty). 1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty). Reserved, should be cleared. Reserved, should be cleared. Description 11-15 0x10 — — — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-49 ATM Controller and AAL0, AAL1, and AAL5 Table 31-20. AAL0-Specific RCT Field Descriptions (continued) Offset 0x18 Bits 0–7 8 Name — RXBM Reserved, should be cleared. Receive buffer interrupt mask 0 The receive buffer event of this channel is masked. (The RXB event is not sent to the interrupt queue when receive buffers are closed.) 1 The receive buffer event of this channel is enabled. Reserved, should be cleared. Description 9–15 — 31.10.2.2.5 AAL1 CES Protocol-Specific RCT Refer to Section 32.9.1.1, “AAL1 CES Protocol-Specific RCT.” 31.10.2.2.6 AAL2 Protocol-Specific RCT Refer to Section 33.4.4.1, “AAL2 Protocol-Specific RCT.” 31.10.2.3 Transmit Connection Table (TCT) Figure 31-30 shows the format of an TCT entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 • Offset + 0x12 • Offset + 0x14 • • • Offset + 0x16 Offset + 0x18 Offset + 0x1a Offset + 0x1C Offset + 0x1E — — INF GBL BO — DTB BIB AVCF — — ATT CPUU VCON ABRF INTQ AAL Tx Data Buffer Pointer (TXDBPTR) TBDCNT TBD_OFFSET Rate Remainder PCR Protocol Specific For AAL5,Section 31.10.2.3.1, “AAL5 Protocol-Specific TCT.” For AAL2, Section 33.3.5.1, “AAL2 Protocol-Specific TCT.” For AAL1, Section 31.10.2.3.2, “AAL1 Protocol-Specific TCT.” For AAL1 CES, Section 32.9.2.1, “AAL1 CES Protocol-Specific TCT” For AAL0, Section 31.10.2.3.3, “AAL0 Protocol-Specific TCT.” APC Linked Channel (APCLC) ATM Cell Header (VPI,VCI,PTI,CLP) PCR Fraction — PMT TBD_BASE TBD_BASE BNM STPT IMK PM Figure 31-30. Transmit Connection Table (TCT) Entry MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-50 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-21 describes general TCT fields. Table 31-21. TCT Field Descriptions Offset 0x00 Bits 0–1 2 3–4 Name — GBL BO Reserved, should be cleared. Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. Byte ordering. This field is used for data buffers. 00 Reserved 01 Power PC little endian 1x Big endian Reserved, should be cleared. Data buffer bus 0 Reside on the 60x bus. 1 Reside on the local bus. BD, interrupt queue and external SRTS logic bus 0 Reside on the 60xbus. 1 Reside on the local bus. Note: When using AAL5, AAL1 CES in UDC mode, BDs and data should be placed on the same bus (TCT[DTB]=TCT[BIB]). Auto VC off. Determines the behavior of the APC when the last buffer associated with this VC has been sent and no more ready buffers are in the VC’s TxBD table. 0 The APC does not remove this VC from the schedule table and continues to schedule it to transmit. 1 The APC removes this VC from the schedule table. To continue transmission after the host adds buffers for transmission, a new ATM TRANSMIT command is needed, which can be issued only after the CP clears TCT[VCON]. Note: When over-subscribing UBR or UBR+ channels, set AVCF so that the CPM does not become overloaded polling non-active VCs. Reserved, should be cleared. ATM traffic type 00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other traffic parameters are not used. 01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a continuous-state leaky bucket algorithm (GCRA) to pace the channel-sustain cell rate. The host must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst tolerance). 10 Peak and minimum cell rate pacing (UBR+ traffic). The host must initialize PCR, PCR fraction, MCR, MCR fraction, and MDA. 11 Reserved CPCS-UU+CPI insertion (used for AAL5 only). 0 CPCS-UU+CPI insertion disabled. The transmitter clears the CPCS-UU+CPI fields. 1 CPCS-UU+CPI insertion enabled. The transmitter reads the CPCS-UU+CPI (16-bit entry) from external memory. It should be placed after the end of the last buffer (it should not be included in the buffer length). Description 5 6 — DTB 7 BIB 8 AVCF 9 10–11 — ATT 12 CPUU MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-51 ATM Controller and AAL0, AAL1, and AAL5 Table 31-21. TCT Field Descriptions (continued) Offset Bits 13 Name VCON Description Virtual channel is on. Should be set by the host before it issues an ATM TRANSMIT command. When the host sets TCT[STPT] (stop transmit), the CP deactivates this channel and clears VCON when the channel is next encountered in the APC scheduling table. The host can issue another ATM TRANSMIT command only after the CP clears VCON. Points to one of four interrupt queues available. Internal use only. Should be cleared. Used for AAL5 Only. Indicates the transmitter state. Initialize to 0 0 In idle state. 1 In AAL5 frame transmission state. Internal use only. Should be cleared. Used for AAL5 Only. 0 ABR Flow control is disabled. 1 ABR Flow control is enabled. AAL type 000 AAL0—Reassembly with no adaptation layer 001 AAL1—ATM adaptation layer 1 protocol 010 AAL5—ATM adaptation layer 5 protocol 100 AAL2—ATM adaptation layer 2 protocol. Refer to Chapter 33, “ATM AAL2.” 101 AAL1_CES—Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.” All others reserved. Tx data buffer pointer. Holds the real address of the current position in the Tx buffer. Transmit BD count. Counts the remaining data to transmit in the current transmit buffer. Its initial value is loaded from the data length field of the TxBD when a new buffer is open; its value is subtracted for any transmitted cell associated with this channel. 14–15 0x02 0 1 INTQ — INF 2–11 12 — ABRF 13–15 AAL 0x04 0x08 — — TxDBPTR TBDCNT 0x0A 0x0C — 0–7 8–15 TBD_OffSe Transmit BD offset. Holds offset from TBD_BASE of the current BD. Should be cleared t initially. Rate Reminder PCR Fraction PCR Rate remainder. Used by the APC to hold the rate remainder after adding the pace fraction to the additive channel rate. Should be cleared initially. Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256 slot. If this is an ABR channel, this field is automatically updated by the CP. Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel according to the traffic contract. Note that for an ABR channel, the CP automatically updates PCR to the ACR value. Protocol-specific APC linked channel. Used by the CP. Initialize to 0 (null pointer). ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The transmitter appends ATMCH to the cell payload during transmission. 0x0E — 0x10 0x16 0x18 — — — — APCLC ATMCH MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-52 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-21. TCT Field Descriptions (continued) Offset 0x1C Bits 0–1 2–7 Name — PMT Reserved, should be cleared. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed on-the-fly. Description 8–15 0x1E 0–11 12 TBD_BASE TxBD base. Points to the first BD in the channel’s TxBD table. The 8 most-significant bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four least-significant bits of the address are taken as zero. BNM Buffer-not-ready interrupt mask. Can be changed on-the-fly. 0 The transmit buffer-not-ready event of this channel is masked. (TBNR event is not sent to the interrupt queue.) 1 The buffer-not-ready event of this channel is enabled. Stop transmit. Should be cleared initially. When the host sets this bit, the CP deactivates this channel and clears TCT[VCON] when the channel is next encountered in the APC scheduling table. Note that for AAL5 if STPT is set and frame transmission is already started (TCT[INF]=1), an abort indication will be sent (last cell with zero length field). Interrupt mask. Can be changed on-the-fly. 0 The transmit buffer event of this channel is masked. (TXB event is not sent to the interrupt queue.) 1 The transmit buffer event of this channel is enabled. Performance monitoring. Can be changed on-the-fly. 0 No performance monitoring for this VC. 1 Performance is monitored for this VC. When a cell is sent for this VC, the performance monitoring table indicated in PMT field is updated. 13 STPT 0x1E 14 IMK 15 PM 31.10.2.3.1 AAL5 Protocol-Specific TCT Figure 31-31 shows the AAL5 protocol-specific TCT. 0 15 Offset + 0x10 Offset + 0x12 Offset + 0x14 Tx CRC Total Message Length Figure 31-31. AAL5 Protocol-Specific TCT Table 31-22 describes AAL5 protocol-specific TCT fields. Table 31-22. AAL5-Specific TCT Field Descriptions Offset 0x10 0x14 Name Tx CRC Total Message Length CRC32 temporary result. This field is used by the CP. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-53 ATM Controller and AAL0, AAL1, and AAL5 31.10.2.3.2 AAL1 Protocol-Specific TCT Figure 31-32 shows the AAL1 protocol-specific TCT. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x10 Offset + 0x12 Offset + 0x14 — SRTS_DEV SRTS_TMP Valid Octet Size (VOS) PFM SRT SPF STF Block Size Structured Pointer (SP) — SN Figure 31-32. AAL1 Protocol-Specific TCT Table 31-23 describes AAL1 protocol-specific TCT fields. Table 31-23. AAL1 Protocol-Specific TCT Field Descriptions Offset 0x10 Bits 0–1 2–7 Name — VOS Reserved, should be cleared. Valid octet size. Partially filled cell mode only. Specifies the number of valid octets from the beginning of the AAL1 user data field. For unstructured service, values 1-47 are valid; for structured service, values 1-46 are valid. Partially filled mode. 0 Partially filled cells mode is not used. 1 Partially filled cells mode is used. The transmitter copies only valid octets from the buffer to the AAL1 cell. The size of the valid octets from the beginning of the AAL1 user data field is specified in the VOS (valid octet size) field. Synchronous residual time stamp. Unstructured format only. The MPC8280 supports SRTS generation using external logic. If this mode is enabled, the MPC8280 reads the SRTS from external logic and inserts it into four cells for which SN = 1, 3, 5, or 7. The MPC8280 reads the new SRTS from external logic every eight cells. (See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.”) 0 SRTS mode is not used. 1 SRTS mode is used. Structured pointer flag. Indicates that a structured pointer has been inserted in the current block. The user should initialize this field to zero. Used by the CP only. Structured format 0 Unstructured format is used. 1 Structured format is used. Reserved, should be cleared. Sequence number field. Used by the CP to check the incoming cells SN. Should be cleared initially. Description 8 PFM 9 SRT 10 11 SPF STF 12 13–15 0x12 0–3 — SN SRTS_DEV Used to select a SRTS device. The SRTS device address is SRTS_BASE[0–27]+SRTS_DEV[28:31]. SRTS_BASE is taken from the parameter RAM and is 16-byte aligned. Block Size Used only in structured format. Specifies the structured block size (Block Size = 0xFFF = 4 Kbytes maximum). 4–15 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-54 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-23. AAL1 Protocol-Specific TCT Field Descriptions (continued) Offset 0x14 Bits 0–3 Name Description SRTS_TMP Before a cell with SN = 1 is sent, the CP reads the SRTS code from external SRTS logic, writes it to SRTS_TMP, and then inserts SRTS_TMP into the next four cells with an odd SN. SP Structured pointer. Used by the CP to calculate the structured pointer. Should be cleared initially. Structured format only. 4–15 31.10.2.3.3 AAL0 Protocol-Specific TCT Figure 31-33 shows the AAL0 protocol-specific TCT. 0 7 8 9 10 11 12 15 Offset + 0x10 Offset + 0x12 Offset + 0x14 — — 0 CR10 — ACHC — Figure 31-33. AAL0 Protocol-Specific TCT Table 31-24 describes AAL0 protocol-specific TCT fields. Table 31-24. AAL0-Specific TCT Field Descriptions Offset 0x10 Bits 0–7 8 9 Name — 0 CR10 Reserved, should be cleared. Must be 0. CRC-10 0 CRC10 insertion is disabled. 1 CRC10 insertion is enabled. Reserved, should be cleared. Description 10 11 — ACHC ATM cell header change 0 Normal operation ATM cell header is taken from AAL0 buffer. 1 VPI/VCI (28 bits) are taken from TCT. — — Reserved, should be cleared. Reserved, should be cleared. 12–15 0x12–0x14 — 31.10.2.3.4 AAL1 CES Protocol-Specific TCT Refer to Section 32.9.2.1, “AAL1 CES Protocol-Specific TCT.” 31.10.2.3.5 AAL2 Protocol-Specific TCT Refer to Section 33.3.5.1, “AAL2 Protocol-Specific TCT.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-55 ATM Controller and AAL0, AAL1, and AAL5 31.10.2.3.6 VBR Protocol-Specific TCTE Figure 31-34 shows the VBR protocol-specific TCTE. 0 1 7 8 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C VBR2 Offset + 0x0E-1E SCR Burst Tolerance (BT) Out of Buffer Rate (OOBR) Sustain Rate Remainder (SRR) Sustain Rate (SR) SCR Fraction (SCRF) — — Figure 31-34. Transmit Connection Table Extension (TCTE)—VBR Protocol-Specific Table 31-25 describes VBR protocol-specific TCTE fields. Table 31-25. VBR-Specific TCTE Field Descriptions Offset 0x00 Bits — Name SCR Description Sustain cell rate. Holds the sustain cell rate (in slots) permitted for this channel according to the traffic contract. To pace the channel’s sustain cell rate, the APC performs a continuous-state leaky bucket algorithm (GCRA). Burst tolerance. Holds the burst tolerance permitted for this channel according to the traffic contract. The relationship between the BT and the maximum burst size (MBS) is BT=(MBS-2) × (SCR-PCR) + SCR. 0x02 — BT 0x04 0x06 — 0–7 OOBR Out-of-buffer rate. In out of buffer state (when the transmitter tries to open TxBD whose R bit is not set) the APC reschedules the current channel according to OOBR rate. SRR Sustain rate remainder. Holds the sustain rate remainder after adding the pace fraction field to the additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky bucket) state. Initialized to 0. 8–15 0x08 — SCRF Holds the sustain cell rate fraction of this channel in units of 1/256 slot. SR Sustain rate. Used by the APC to hold the sustain rate after adding the pace field to the additive channel sustain rate. Used by the APC to calculate the channel GCRA (leaky bucket) state. VBR type 0 Regular VBR. CLP=0+1 cells are rescheduled by PCR or SCR according to the GCRA state. 1 VBR Type 2. CLP=0 cells are rescheduled by PCR or SCR according to the GCRA state. CLP=1 cells are rescheduled by PCR. Reserved, should be cleared. Reserved, should be cleared. 0x0C 0 VBR2 1–15 0x0E– 0x1E — — — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-56 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.10.2.3.7 UBR+ Protocol-Specific TCTE Figure 31-35 shows the UBR+ protocol-specific TCTE. 0 7 8 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06–0x1E — MCR MCR Fraction (MCRF) Maximum Delay Allowed (MDA) — Figure 31-35. UBR+ Protocol-Specific TCTE Table 31-26 describes UBR+ protocol-specific TCTE fields. Table 31-26. UBR+ Protocol-Specific TCTE Field Descriptions Offset 0x00 0x02 Bits — 0–7 8–15 0x04 0x06– 0x1E — — Name MCR — Description Minimum cell rate for this channel. MCR is in units of APC time slots. Reserved, should be cleared. MCRF Minimum cell rate fraction. Holds the minimum cell rate fraction of this channel in units of 1/256 slot. MDA — Maximum delay allowed. The maximum time-slot service delay allowed for this priority level before the APC reduces the scheduling rate from PCR to MCR. Reserved, should be cleared. 31.10.2.3.8 ABR Protocol-Specific TCTE Figure 31-36 shows the ABR protocol-specific TCTE. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-57 ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 TUAR Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E ACRC Offset + 0x10 Offset + 0x12 Offset + 0x14 FRST Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — CDF — CI-TA NI-TA — ER-TA CCR-TA MCR-TA CP-TA MCR UNACK ACR — RM Cell Time Stamp (RCTS) — CI-VC — COUNT ICR CRM ADTF ER ER-BRM Figure 31-36. ABR Protocol-Specific TCTE Table 31-27 describes ABR-specific TCTE fields. Table 31-27. ABR-Specific TCTE Field Descriptions Offset 0x00 Bits — Name ER-TA Description Explicit rate–turn-around cell. Holds the ER of the last received F-RM cell. If another F-RM cell arrives before the previous F-RM cell was turned around, this field is overwritten by the new RM cell’s ER. 0x02 — CCR-TA Current cell rate–turn-around cell. Holds the CCR of the last received F-RM cell. If another F-RM cell arrives before the previous F-RM cell was turned around, this field is overwritten by the new RM cell’s CCR. MCR-TA Minimum cell rate–turn-around cell. Holds the MCR of the last received F-RM cell. If another F-RM cell arrives before the previous F-RM cell is turned around, this field is overwritten by the new RM cell’s MCR. TUAR Turn-around flag. The CP sets TUAR to indicate that a new F-RM cell was received, which causes the transmitter to send a B-RM cell whenever the ABR flow control permits. Should be cleared initially. Reserved, should be cleared. Congestion indication–turn-around cell. Holds the CI of the last received F-RM cell. If another F-RM cell arrives before the previous F-RM cell was turned around, CI-TA is overwritten by the new RM cell’s CI. 0x04 — 0x06 0 1 2 — CI-TA MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-58 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-27. ABR-Specific TCTE Field Descriptions (continued) Offset Bits 3 Name NI-TA Description No increase–turn-around cell. Holds the NI of the last received F-RM cell. If another F-RM cell arrives before the previous one was turned around, NI-TA is overwritten by the new RM cell’s NI. Reserved, should be cleared. Cell loss priority–turn-around cell. Holds the CLP of the last received F-RM cell. If another F-RM cell arrives before the previous one was turned around, CP-TA is overwritten by the new RM cell’s CLP. Reserved, should be cleared. Congestion indication -VC. Holds the EFCI (explicit forward congestion indication) of the last user data cell. The CI bit of the turned around RM cell is ORed with the CI-VC. Should be cleared initially. Reserved, should be cleared. Minimum cell rate Holds the minimum number of cells/sec of the current ABR channel. Uses the ATMF TM 4.0 floating-point format. Used by the CP to count F-RM cells sent in an absence of received B-RM cells. Should be cleared initially. Allowed cell rate The cells per second allowed for the current ABR channel. Uses the ATMF TM 4.0 floating-point format. Initialize with ICR. ACR change. Indicates a change in ACR. Initialize to one. Reserved, should be cleared. RM cell time stamp. Used exclusively by the CP. Initialize to zero. First turn. Used exclusively by the CP. Indicates the first turn of a backward RM cell, which has priority over a data cell. Initialized to 0. Reserved, should be cleared. Cutoff decrease factor. Controls the decrease in the ACR associated with missing B-RM cells feedback. CDF represents a negative exponent of two, that is, the cutoff decrease factor = 2-CDF. The cutoff decrease factor ranges from 1/64 (CDF=0b0110) to 1 (CDF=0b0000). All other CDF values falling outside this range are invalid. 4–6 7 — CP-TA 8–9 10 — CI-VC 11–15 0x08 0x0A 0x0C 0x0E — — — 0 1–15 0x10 0x14 — 0 1–3 4–7 — MCR UNACK ACR ACRC — RCTS FRST — CDF 8–15 0x16 0x18 0x1A — — — COUNT Count. Used only by the CP. Holds the number of cells sent since the last forward RM cell. Initialize with Nrm (in the parameter RAM). ICR CRM ADTF Initial cell rate. The number of cells per second of the current ABR channel. The channel’s ACR is initialized with ICR. ICR uses the ATMF TM 4.0 floating-point format. Missing RM cells count. Limits the number of forward RM cells that may be sent in the absence of received backward RM cell. The CRM is in units of cells. ADTF–ACR decrease time factor. The ADTF period is 500 ms as defined in the TM 4.0. The ADTF value is defined by the system clock and the time stamp timer prescaler; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” For a time stamp prescaler of 1 µs, ADTF should be programmed to 500m/(1µs × 1024)= 488. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-59 ATM Controller and AAL0, AAL1, and AAL5 Table 31-27. ABR-Specific TCTE Field Descriptions (continued) Offset 0x1C Bits — Name ER Description Explicit rate. Holds the explicit rate value (in cells/sec) of the current ABR channel. ER is copied to the F-RM cell ER field. The user usually initializes this field to PCR. ER uses the ATMF TM 4.0 floating-point format. 0x1E — ER-BRM Explicit rate-backward RM cell. Holds the maximum explicit rate value (in cells/sec) allowed for B-RM cells. The ER-TA field which is inserted to each B-RM cell is limited by this value. ER-BRM uses the ATMF TM 4.0 floating-point format. 31.10.3 OAM Performance Monitoring Tables The OAM performance monitoring tables include performance monitoring block test parameters, as shown in Figure 31-37. Each block test needs a 32-byte performance monitoring table in the dual-port RAM. In the connection’s RCT and TCT, the user allocates an OAM performance table to a VCC or VPC. See Section 31.6.6, “Performance Monitoring.” PMT_BASE in the parameter RAM points to the base address of the tables. The starting address of each PM table is given by PMT_BASE + RCT/TCT[PMT] × 32. 0 1 2 4 5 7 8 15 Offset + 0x00 FMCE TSTE Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — — BLCKSIZE TX Cell Count (TCC) TUC1 TUC0 BEDC0+1-Tx BEDC0+1-RX TRCC1 TRCC0 — — PM CELL HEADER (VPI,VCI,PTI,CLP) SN-FMC — Figure 31-37. OAM Performance Monitoring Table MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-60 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-28 describes fields in the performance monitoring table. Table 31-28. OAM—Performance Monitoring Table Field Descriptions Offset Bits 0x00 0 1 Name FMCE TSTE Description Enables FMC transmission. Initialize to 1. FMC time stamp enable 0 The time stamp field of the FMC is coded with all 1’s. 1 The value of the time stamp timer is inserted into the time stamp field of the FMC. Reserved, should be cleared. Performance monitoring block size ranging from 1 to 2,047 cells. Reserved, should be cleared. TX cell count. Used by the CP to count data cells sent. Initialize to zero. Total user cell 1. Count of CLP = 1 user cells (modulo 65,536) sent. Should be cleared initially. Total user cell 0. Count of CLP = 0 user cells (modulo 65,536) sent. Should be cleared initially. 2–4 5–15 0x02 0–4 5–15 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 — — — — — — 0–7 8–15 0x12 0x14 0x18– 0x1E — — — — BLCKSIZE — TCC TUC1 TUC0 BEDC0+1-Tx Block error detection code 0+1–transmitted cells. Even parity over the payload of the block of user cells sent since the last FMC. Should be cleared initially. BEDC0+1-RX Block error detection code 0+1–received cells. Even parity over the payload of the block of user cells received since the last FMC. Should be cleared initially. TRCC1 TRCC0 — SN-FMC — PMCH — Total received cell 1. Count of CLP = 1 user cells (modulo 65,536) received. Should be cleared initially. Total received cell 0. Count of CLP = 0 user cells (modulo 65,536) received. Should be cleared initially. Reserved, should be cleared. Sequence number of the last FMC sent. Should be cleared initially. Reserved, should be cleared. PM cell header. Holds the ATM cell header of the FMC, BRC to be inserted by the CP into the Tx cell flow. Reserved, should be cleared. 31.10.4 APC Data Structure The APC data structure consists of three elements: the APC parameter tables for the PHY devices, the APC priority table, and the APC scheduling tables. See Figure 31-38. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-61 ATM Controller and AAL0, AAL1, and AAL5 APC Parameter Tables Parameter Table PHY #0 Parameter Table PHY #1 APC Priority Table Priority 1 Priority 2 Priority 3 Priority 4 Priority 5 Priority 6 APC Scheduling Tables Priority 1 Scheduling Table Priority 2 Scheduling Table Priority 3 Scheduling Table Priority 4 Scheduling Table Priority 5 Scheduling Table Priority 6 Scheduling Table Priority 7 Scheduling Table Priority 8 Scheduling Table Parameter Table PHY #31 Priority 7 Priority 8 Note: The shaded areas represent the active structures for an example implementation of PHY #0 with two priorities. (The unshaded areas and dashed arrows represent unused structures.) Figure 31-38. ATM Pace Control Data Structure 31.10.4.1 APC Parameter Tables Each PHY’s APC parameter table, shown in Table 31-29, holds parameters that define the priority table location, the number of priority levels, and other APC parameters. The table resides in the dual-port RAM. The parameter APCP_BASE, described in Section 31.10.1, “Parameter RAM,” points to the base address of PHY#0’s parameter table. For multiple PHYs, the table structure is duplicated. Each table resides in 32 bytes of memory. The starting address of each APC parameter table is given by APCP_BASE + PHY# × 32. Note however that in slave mode with multiple PHYs, the parameter table always resides at APCP_BASE regardless of the PHY address. Table 31-29. APC Parameter Table Offset1 0x00 0x02 0x04 0x06 Name APCL_FIRST APCL_LAST APCL_PTR CPS Width Description Hword Address of first entry in the priority table. Must be 8-byte aligned. User-initialized. Hword Address of last entry in the priority table. Must be 8-byte aligned. User-initialized as APCL_FIRST + 8 x (number_of_priorities - 1). Hword Address of current priority entry used by the CP. User-initialized with APCL_FIRST. Byte Cells per slot. Determines the number of cells sent per APC slot. See Section 31.3.2, “APC Unit Scheduling Mechanism.” User-defined. (0x01 = 1 cell; 0xFF = 255 cells.) Note: If ABR is used, CPS must be a power of two. Cells sent per APC slot counter. User-initialized to CPS; used by the CP. Max iteration allowed. Number of scan iterations allowed in the APC. User-defined. This parameter limits the time spent in a single APC routine, thereby avoiding excessive APC latency. 0x07 0x08 CPS_CNT MAX_ITERATION Byte Byte MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-62 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-29. APC Parameter Table (continued) Offset1 0x09 0x0A 0xC 0x10 1 Name CPS_ABR LINE_RATE_ABR REAL_TSTP APC_STATE Width Byte Description ABR only. Cells per slot represented as a power of two. User-defined. (For example, if CPS is 1, CPS_ABR = 0x00; if CPS is 8, CPS_ABR = 0x03.) Hword ABR only. The PHY line rate in cells/sec, represented in TM 4.0 floating-point format. User-defined. Word Real-time stamp pointer used internally by the APC. Should be cleared initially. Word Used internally by the APC. Should be cleared initially. Offset values are to APCP_BASE+PHY# × 32. However, in slave mode, the offset is from APCP_BASE regardless of the PHY address. 31.10.4.2 APC Priority Table Each PHY’s APC priority table holds pointers to the APC scheduling table of each priority level. It resides in the dual-port RAM. The priority table can hold up to eight priority levels. Table 31-30 shows the structure of a priority table entry. Table 31-30. APC Priority Table Entry Offset 0x00 0x02 0x04 0x06 Name Width Description APC_LEVi_BASE Hword APC level i base address. Pointer to the first slot in the APC scheduling table for level i. Should be half-word aligned. User-defined. APC_LEVi_END Hword APC level i end address. Pointer to the last slot in the APC scheduling table for level i. Should be half-word aligned. User-defined. APC_LEVi_RPTR Hword APC level i real-time/service pointers. APC table pointers used internally by the APC. Initialize both pointers to APC_LEVi_BASE. APC_LEVi_SPTR Hword 31.10.4.3 APC Scheduling Tables The APC uses APC scheduling tables (one table for each priority level) to schedule channel transmission. A scheduling table is divided into time slots, as shown in Figure 31-39. Each slot is a half-word entry. Note that the APC scheduling tables should be cleared before the APC unit is enabled. APC_LEVi_BASE slot 0 slot 1 slot N Control Slot Half Word Entry APC_LEVi_END Figure 31-39. The APC Scheduling Table Structure MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-63 ATM Controller and AAL0, AAL1, and AAL5 Slot N+1 is used as a control slot, as shown in Figure 31-40. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field TCTE 000_0000_0000_0000 Figure 31-40. Control Slot Table 31-31 describes control slot fields. Table 31-31. Control Slot Field Description Bits 0 Name TCTE Description Used for external channels only. 0 Channels in this scheduling table do not use external TCTE. (No external VBR, ABR, UBR+ channels) 1 Channels in this scheduling table use external TCTE. (External VBR, ABR, UBR+ channels) Reserved, should be cleared. 1–15 — 31.10.5 ATM Controller Buffer Descriptors (BDs) Each ATM channel has separate receive and transmit BD tables. The number of BDs per channel and the size of the buffers is user-defined. The last BD in each table holds a wrap indication. Each BD in the TxBD table points to a buffer to send. At the receive side, the user can choose one of two modes: • Static buffer allocation. In this mode, the user allocates dedicated buffers to each ATM channel (that is, the user associates each BD with one buffer). Static buffer allocation is useful when the connection rate is known and constant and when data must be reassembled in a particular memory space. • Global buffer allocation. Available for AAL5 only. In this mode, buffer allocation is dynamic. The user allocates receive buffers and places them in global buffer pools. When the CP needs a receive buffer, it first fetches a buffer pointer from one of the global buffer pools and writes the pointer to the current RxBD. Global buffer allocation is optimized for allocating memory among many ATM channels with variable data rates, such as ABR channels. 31.10.5.1 Transmit Buffer Operation The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an ATM TRANSMIT command. The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer is finished, the CP increments TBD_Offset, which holds the offset from TBD_BASE to the current BD. It then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new ATM TRANSMIT command to restart transmission. Figure 31-41 shows the ready bit in the TxBD tables and their associated buffers for two example ATM channels. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-64 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Ch1 TxBD Table Tx Buffer 1 of Channel 1 Ch1 TxBD Table Pointers in the TCT TBD_BASE TBD_Offset 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Tx Buffer 2 of Channel 1 Tx Buffer 3 of Channel 1 Tx Buffer 4 of Channel 1 Tx Buffer 5 of Channel 1 Ch4 TxBD Table Tx Buffer 1 of Channel 4 Ch4 TxBD Table Pointers in the TCT TBD_BASE 1 0 0 0 0 1 1 BD BD BD BD BD BD BD 1 2 3 4 5 6 7 Tx Buffer 2 of Channel 4 Tx Buffer 3 of Channel 4 Tx Buffer 4 of Channel 4 Tx Buffer 5 of Channel 4 Tx Buffer 6 of Channel 4 Tx Buffer 7 of Channel 4 Note: The shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared. TBD_Offset Figure 31-41. Transmit Buffers and BD Table Example 31.10.5.2 Receive Buffer Operation For AAL5 channels, the user should choose to operate in static buffer allocation or in global buffer allocation by writing to RCT[BUFM]. AAL1 CES and AAL0 channels must use static buffer allocation. 31.10.5.2.1 Static Buffer Allocation The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts filling its associated buffer with received data. When the current buffer is full, the CP increments RBD_Offset, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition has occurred and a busy interrupt is sent to the event queue. Figure 31-42 shows the empty bit in the RxBD tables and their associated buffers for two example ATM channels. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-65 ATM Controller and AAL0, AAL1, and AAL5 Ch1 RxBD Table Rx Buffer 1 of Channel 1 Ch1 RxBD Table Pointers in the RCT RBD_BASE RBD_Offset 0 1 1 0 0 BD BD BD BD BD 1 2 3 4 5 Rx Buffer 2 of Channel 1 Rx Buffer 3 of Channel 1 Rx Buffer 4 of Channel 1 Rx Buffer 5 of Channel 1 Ch4 RxBD Table Rx Buffer 1 of Channel 4 Ch4 RxBD Table Pointers in the RCT RBD_BASE 1 0 0 0 0 1 1 BD BD BD BD BD BD BD 1 2 3 4 5 6 7 Rx Buffer 2 of Channel 4 Rx Buffer 3 of Channel 4 Rx Buffer 4 of Channel 4 Rx Buffer 5 of Channel 4 Rx Buffer 6 of Channel 4 Rx Buffer 7 of Channel 4 Note: The shaded buffers are empty; unshaded buffers are waiting to be processed. RBD_Offset Figure 31-42. Receive Static Buffer Allocation Example 31.10.5.2.2 Global Buffer Allocation The user prepares a table of BDs without assigning buffers to them (no buffer pointers). The address of the first BD is put into the channel’s RCT[RBD_BASE]. The user also prepares sets of free buffers (of size RCT[MRBLR]) in up to four free buffer pools (chosen in RCT[BPOOL]); see Section 31.10.5.2.3, “Free Buffer Pools.” When an ATM cell arrives, the CP opens the first BD in the table, fetches a buffer pointer from the free buffer pool associated with this channel, and writes the pointer to RxBD[RXDBPTR], the receive data buffer pointer field in the BD. When the current buffer is full, the CP increments RBD_Offset, which is the offset from the RBD_BASE to the current BD, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP fetches another buffer pointer from the free buffer pool and reception continues. If the BD is not empty, a busy condition occurs and a busy interrupt is sent to the event queue specifying the ATM channel code. As software then processes each full buffer (RxBD[E] = 0), it sets RxBD[E] and copies the buffer pointer back to the free buffer pool. Figure 31-43 shows two ATM channels’ BD tables and one free buffer pool. Both channels are associated with free buffer pool 1. The CP allocates the first two buffers of buffer pool 1 to channel 1 and the third to channel 4. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-66 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Ch1 RxBD Table RBD_BASE RBD_Offset Free Buffer Pool 1 0 1 1 1 1 BD BD BD BD BD 1 2 3 4 5 Buffer 1 of FBP1 Buffer 2 of FBP1 FBP1_BASE FBP1_PTR Pointer 1 Pointer 2 Pointer 3 Pointer 4 Pointer 5 Pointer 6 Ch4 RxBD Table Buffer 4 Buffer 5 Buffer 6 RBD_BASE, RBD_Offset 1 1 1 1 BD BD BD BD 1 2 3 4 Buffer 3 of FBP1 Notes: Buffers 2 and 3 are receiving data. After buffer 1 is processed, it can be returned to the pool. Figure 31-43. Receive Global Buffer Allocation Example 31.10.5.2.3 Free Buffer Pools As Figure 31-44 shows, when a buffer pointer is fetched from a pool, the CP clears the entry’s valid bit and increments FBP#_PTR. After the CP uses an entry with the wrap bit set (W = 1), it returns to the first entry in the pool. After a buffer pointer is returned to the pool, the user should set V to indicate that the entry is valid. If the CP tries to read an invalid entry (V = 0), the buffer pool is out of free buffers; the global-buffer-pool-busy event is then set in FCCE[GBPB] and a busy interrupt is sent to the interrupt queue specifying the ATM channel code associated with the pool. Word FBP#_BASE V=1 V=1 V=1 Software (Core) Pointer V=0 V=0 V=0 FBP#_PTR V=1 V=1 V=1 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=1 Buffer Pointer Buffer Pointer Buffer Pointer Invalid Invalid Invalid Buffer Pointer Buffer Pointer Buffer Pointer Figure 31-44. Free Buffer Pool Structure Figure 31-45 describes the structure of a free buffer pool entry. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-67 ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 15 Offset + 0x00 Offset + 0x02 V — W I Buffer Pointer (BP) Buffer Pointer (BP) Figure 31-45. Free Buffer Pool Entry Table 31-32 describes free buffer pool entry fields. Table 31-32. Free Buffer Pool Entry Field Descriptions Offset 0x00 Bits 0 Name V Description Valid buffer entry. 0 This free buffer pool entry contains an invalid buffer pointer. 1 This free buffer pool entry contains a valid buffer pointer. Reserved, should be cleared. Wrap bit. When set, this bit indicates the last entry in the circular table. During initialization, the host must clear all W bits in the table except the last one, which must be set. Red-line interrupt. Can be used to indicate that the free buffer pool has reached a red line and additional buffers should be added to this pool to avoid a busy condition. 0 No interrupt is generated. 1 A red-line interrupt is generated when this buffer is fetched from the free buffer pool. Buffer pointer. Points to the start address of the receive buffer. The four msbs are control bits, and the four msbs of the real buffer pointer are taken from the four msbs of the parameter FBP_ENTRY_EXT in the free buffer pool parameter table. 1 2 3 — W I 4–15 0x02 0–15 BP 31.10.5.2.4 Free Buffer Pool Parameter Tables The free buffer pool parameters are held in parameter tables in the dual-port RAM; see Table 31-33. FBT_BASE in the parameter RAM points to the base address of these tables. Each of the four free buffer pools has its own parameter table with a starting address given by FBT_BASE+ RCT[BPOOL] × 16. Table 31-33. Free Buffer Pool Parameter Table Offset 1 0x00 0x04 0x08 Bits — — — Name FBP_BASE FBP_PTR Description Free buffer pool base. Holds the pointer to the first entry in the free buffer pool. FBP_BASE should be word aligned. User-defined. Free buffer pool pointer. Pointer to the current entry in the free buffer pool. Initialize to FBP_BASE. FBP_ENTRY_EXT Free buffer pool entry extension. FBP_ENTRY_EXT[0–3] holds the four left bits of FBP_ENTRY. FBP_ENTRY_EXT[4–15] should be cleared. User-defined. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-68 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-33. Free Buffer Pool Parameter Table (continued) Offset 1 0x0A Bits 0 1 2–7 8 Name BUSY RLI — EPD Description The CP sets this bit when it tries to fetch buffer pointer with V bit clear. FCCE[GBPB] is also set. Initialize to zero. Red-line interrupt. Set by the CP when it fetches a buffer pointer with I = 1. FCCE[GRLI] is also set. Initialize to zero. Reserved, should be cleared. Early packet discard. 0 Normal operation. 1 AAL5 frames in progress are received, but new AAL5 frames associated with this pool are discarded. Can be used to implement EPD under core control. Reserved, should be cleared. Free buffer pool entry. Initialize with the first entry of the free buffer pool. Note that FBP_ENTRY must be reinitialized with the entry pointed to by FBP_PTR when a busy state occurs to reenable free buffer pool processing. 9–15 0x0C — — FBP_ENTRY 1 Offset from FBT_BASE+RCT[BPOOL] × 16 31.10.5.3 ATM Controller Buffers Table 31-34 describes properties of the ATM receive and transmit buffers. Table 31-34. Receive and Transmit Buffers Receive AAL Size Alignment Any ≥ 47 octets 52–64 octets Size Alignment No requirement No requirement No requirement Transmit AAL5 Multiple of 48 octets (except last buffer in frame) Burst-aligned (recommended) AAL1 At least 47 octets AAL0 52-64 octets. Burst-aligned (recommended) Burst-aligned 31.10.5.4 AAL5 RxBD Figure 31-46 shows the AAL5 RxBD. 0 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 E 1 — 2 W 3 I 4 L 5 F 6 CM 7 8 — Data Length (DL) Rx Data Buffer Pointer (RXDBPTR) 9 10 11 12 13 14 15 CLP CNG ABRT CPUU LNE CRE Figure 31-46. AAL5 RxBD MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-69 ATM Controller and AAL0, AAL1, and AAL5 Table 31-35 describes AAL5 RxBD fields. m Table 31-35. AAL5 RxBD Field Descriptions Offset 0x00 Bits 0 Name E Description Empty. 0 The buffer associated with this RxBD is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD and its receive buffer are controlled by the CP. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in table) 0 This is not the last BD in the RxBD table of the current channel. 1 This is the last BD in the RxBD table of this current channel. After this buffer has been used, the CP receives incoming data into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been used. 1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer. FCCE[GINTx] is set in the event register when INT_CNT reaches the global interrupt threshold. Last in frame. Set by the ATM controller for the last buffer in a frame. 0 Buffer is not last in a frame. 1 Buffer is last in a frame. ATM controller writes frame length in DL and updates the error flags. First in frame. Set by the ATM controller for the first buffer in a frame. 0 The buffer is not the first in a frame. 1 The buffer is the first in a frame. Continuous mode 0 Normal operation. 1 The CP does not clear the empty bit after this BD is closed, allowing the associated buffer to be overwritten automatically when the CP next accesses this BD. Reserved, should be cleared. Cell loss priority. At least one cell associated with the current message was received with CLP = 1. May be set at the last buffer of the message. Congestion indication. The last cell associated with the current message was received with PTI middle bit set. CNG may be set at the last buffer of the message. Abort message indication. The current message was received with Length field zero. CPCS-UU+CPI indication. Set when the CPCS-UU+CPI field is non zero. CPUU may be set at the last buffer of the message. Rx length error. AAL5 CPCS-PDU length violation. May be set only for the last BD of the frame if the pad length is greater than 47 or less than zero octets. Rx CRC error. Indicates CRC32 error in the current AAL5 PDU. Set only for the last BD of the frame. 1 2 — W 3 I 4 L 5 F 6 CM 7–9 10 11 12 13 14 15 — CLP CNG ABRT CPUU LNE CRE MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-70 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-35. AAL5 RxBD Field Descriptions (continued) Offset 0x02 Bits — Name DL Description Data length. The number of octets written by the CP into this BD’s buffer. It is written by the CP once the BD is closed. In the last BD of a frame, DL contains the total frame length. 0x04 RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in internal or external memory. It is recommended that the pointer be burst-aligned. 31.10.5.5 AAL1 RxBD Figure 31-47 shows the AAL1 RxBD. 0 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 E 1 — 2 W 3 I 4 SNE 5 — 6 CM Data Length Rx Data Buffer Pointer 7 8 9 10 11 — 12 13 14 15 Figure 31-47. AAL1 RxBD Table 31-36 describes AAL1 RxBD fields. Table 31-36. AAL1 RxBD Field Descriptions Offset 0x00 Bits 0 Name E Description Empty 0 The buffer associated with this RxBD is filled with received data or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP cannot use this BD again while E = 0. 1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in table) 0 This is not the last BD in the RxBD table of the current channel. 1 This is the last BD in the RxBD table of this current channel. After this buffer is used, the CP receives incoming data into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table overall space is constrained to 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been used. 1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold. Sequence number error. SNE is set when a sequence number error is detected in the current AAL1 CES buffer. Reserved, should be cleared. 1 2 — W 3 I 4 5 SNE — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-71 ATM Controller and AAL0, AAL1, and AAL5 Table 31-36. AAL1 RxBD Field Descriptions (continued) Offset Bits 6 Name CM Description Continuous mode 0 Normal operation. 1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the associated buffer to be overwritten automatically when the CP next accesses this BD. Reserved, should be cleared. Data length. The number of octets the CP writes into the buffer once its BD is closed. 7–15 0x02 0x04 — — — DL RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in either internal or external memory. It is recommended that the pointer be burst-aligned. 31.10.5.6 AAL0 RxBD Figure 31-48 shows the AAL0 RxBD. 0 1 2 3 4 5 6 7 9 10 11 12 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 E — W I — CM — CRE OAM — Data Length (DL)/Channel Code (CC) Rx Data Buffer Pointer (RXDBPTR) Figure 31-48. AAL0 RxBD Table 31-37 describes AAL0 RxBD fields. Table 31-37. AAL0 RxBD Field Descriptions Offset 0x00 Bits 0 Name E Description Empty 0 The buffer associated with this RxBD is filled with received data, or data reception was aborted due to an error. The core can examine or write to any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The Rx buffer is empty or reception is in progress. This RxBD and its associated receive buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in table) 0 This is not the last BD in the RxBD table of the current channel. 1 This is the last BD in the RxBD table of the current channel. After this buffer has been used, the CP will receive incoming data into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been used. 1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold. Reserved, should be cleared. 1 2 — W 3 I 4–5 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-72 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-37. AAL0 RxBD Field Descriptions (continued) Offset Bits 6 Name CM Description Continuous mode 0 Normal operation. 1 The CP does not clear the E bit after this BD is closed, allowing the associated buffer to be overwritten automatically when the CP next accesses this BD. Reserved, should be cleared. Rx CRC error. Indicates a CRC10 error in the current AAL0 buffer. The CRE bit is considered an error only if the received cell had a CRC10 field in the cell payload. Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an OAM cell. This cell is associated with the channel indicated by the channel code field (CC field). Reserved, should be cleared. Data length/channel code. If RxBD[OAM] is set, this field functions as CC; otherwise, it is DL. Data length is the size in octets of this buffer (MRBLR value). Channel code specifies the channel code associated with this OAM cell. 7–9 10 11 — CRE OAM 12–15 0x02 — — DL/CC 0x04 — RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in either internal or external memory. This pointer must be burst-aligned. 31.10.5.7 AAL1 CES RxBD Refer to Section 32.12.1, “AAL1 CES RxBD.” 31.10.5.8 AAL2 RxBD Refer to Section 33.4.4.4, “CPS Receive Buffer Descriptor (RxBD).” 31.10.5.9 AAL5, AAL1 CES User-Defined Cell—RxBD Extension In user-defined cell mode, the AAL5 and AAL1 CES RxBDs are extended to 32 bytes; see Figure 31-49. NOTE For AAL0, a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. Offset + 0x08 Extra Cell Header. Used to store the user-defined cell’s extra cell header. The extra cell header can be 1–12 bytes long. Reserved (12 bytes) Offset + 0x14 Figure 31-49. User-Defined Cell—RxBD Extension MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-73 ATM Controller and AAL0, AAL1, and AAL5 31.10.5.10 AAL5 TxBDs Figure 31-50 shows the AAL5 TxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R — W I L — CM — CLP CNG — Data Length (DL) Tx Data Buffer Pointer (TXDBPTR) Figure 31-50. AAL5 TxBD Table 31-38 describes AAL5 TxBD fields. Table 31-38. AAL5 TxBD Field Descriptions Offset 0x00 Bits 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or after an error condition is encountered. 1 The user-prepared buffer has not been sent or is currently being sent. No fields of this BD may be written by the user once R is set. Reserved, should be cleared. Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The number of TxBDs in this table is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced. FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold. Last in frame. Set by the user to indicate the last buffer in a frame. 0 Buffer is not last in a frame. 1 Buffer is last in a frame. Reserved, should be cleared. Continuous mode 0 Normal operation. 1 The CP does not clear R after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of CM. Reserved, should be cleared. The ATM cell header CLP bit of the cells associated with the current frame are ORed with this field. This field is valid only in the first BD of the frame. 1 2 — W 3 I 4 L 5 6 — CM 7-9 10 — CLP MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-74 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-38. AAL5 TxBD Field Descriptions (continued) Offset Bits 11 12–15 0x02 0x04 — — Name CNG — DL Description The ATM cell header CNG bit of the cells associated with the current frame are ORed with this field. This field is valid only in the first BD of the frame. Reserved, should be cleared. The number of octets the ATM controller should transmit from this BD’s buffer. It is not modified by the CP. The value of DL should be greater than zero. TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may not be 8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modified by the CP. 31.10.5.11 AAL1 TxBDs Figure 31-51 shows the AAL1 TxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R — W I — CM Data Length (DL) — Tx Data Buffer Pointer (TXDBPTR) Figure 31-51. AAL1 TxBD Table 31-39 describes AAL1 TxBD fields. Table 31-39. AAL1 TxBD Field Descriptions Offset 0x00 Bits 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears this bit after the buffer has been sent or after an error condition is encountered. 1 The buffer prepared for transmission by the user has not been sent or is being sent. No fields of this BD may be written by the user once R is set. Reserved, should be cleared. Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The number of TxBDs in this table is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced. FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold. Reserved, should be cleared. 1 2 — W 3 I 4–5 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-75 ATM Controller and AAL0, AAL1, and AAL5 Table 31-39. AAL1 TxBD Field Descriptions Offset Bits 6 Name CM Description Continuous mode 0 Normal operation. 1 The CP does not clear the ready bit after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. Reserved, should be cleared. The number of octets the ATM controller should transmit from this BD’s buffer. It is not modified by the CP. The value of DL should be greater than zero. 7–11 0x02 0x04 — — — DL TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may reside in either internal or external memory. This value is not modified by the CP. 31.10.5.12 AAL0 TxBDs Figure 31-52 shows AAL0 TxBDs. Note that the data length field is calculated internally as 52 bytes, plus the extra header length (defined in FPSMR[TEHS]) when in UDC mode. 0 1 2 3 4 5 6 7 10 11 12 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R — W I — CM — — OAM — Tx Data Buffer Pointer (TXDBPTR) Figure 31-52. AAL0 TxBDs Table 31-40 describes AAL0 TxBD fields. Table 31-40. AAL0 TxBD Field Descriptions Offset 0x00 Bits 0 Name R Description Ready 0 The buffer is not ready for transmission. The user can manipulate this BD or its buffer. The CP clears R after the buffer has been sent or after an error occurs. 1 The buffer that the user prepared for transmission has not been sent or is being sent. No fields of this BD may be written by the user once R is set. Reserved, should be cleared. Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The number of TxBDs in this table is determined by the W bit. The current table is constrained to 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced. FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold. 1 2 — W 3 I MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-76 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-40. AAL0 TxBD Field Descriptions (continued) Offset Bits 4–5 6 Name — CM Reserved, should be cleared. Continuous mode 0 Normal operation. 1 The CP does not clear the ready bit after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. Reserved, should be cleared. Operation and maintenance cell. If OAM is set, the current AAL0 buffer contains an F5 or F4 OAM cell. Performance monitoring calculations are not done on OAM cells. Reserved, should be cleared. Reserved, should be cleared. Description 7–10 11 11–15 0x02 0x04 — — — OAM — — TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may not be 8-byte-aligned. The buffer may reside in either internal or external memory. This value is not modified by the CP. 31.10.5.13 AAL1 CES TxBDs Refer to Section 32.12.2, “AAL1 CES TxBDs 31.10.5.14 AAL2 TxBDs Refer to Section 33.3.5.5, “SSSAR Transmit Buffer Descriptor.” 31.10.5.15 AAL5, AAL1 User-Defined Cell—TxBD Extension In user-defined cell mode, the AAL5 and AAL1 TxBDs are extended to 32 bytes; see Figure 31-53. NOTE For AAL0 a complete cell, including the UDC header, is stored in the buffer; the AAL0 BD size is always 8 bytes. Offset + 0x08 Extra Cell Header. Used to store the user-defined cell’s extra cell header. The extra cell header can be 1–12 bytes long. Reserved (12 bytes) Offset + 0x14 Figure 31-53. User-Defined Cell—TxBD Extension 31.10.6 AAL1 Sequence Number (SN) Protection Table The 32-byte sequence number protection table, pointed to by AAL1_SNPT_BASE in the ATM parameter RAM, resides in dual-port RAM and is used for AAL1 only. The table should be initialized according to Figure 31-54. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-77 ATM Controller and AAL0, AAL1, and AAL5 0 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E 0x0000 0x0007 0x000D 0x000A 0x000E 0x0009 0x0003 0x0004 0x000B 0x000C 0x0006 0x0001 0x0005 0x0002 0x0008 0x000F Figure 31-54. AAL1 Sequence Number (SN) Protection Table 31.10.7 UNI Statistics Table The UNI statistics table, shown in Table 31-41, resides in the dual-port RAM and holds UNI statistics parameters. UNI_STATT_BASE points to the base address of this table. Each PHY’s own table has a starting address given by UNI_STATT_BASE+ PHY# × 8. Table 31-41. UNI Statistics Table Offset1 0x00 Name UTOPIAE Width Hword Description Counts cells dropped as a result of UTOPIA/ATM protocol violations. Violations include the following: 1. Parity error 2. HEC error 3. Invalid timing of RxSOC. If RxClav is asserted for the selected PHY, RxSOC should be asserted the cycle immediately following the assertion of RXENB. A violation occurs if RxSOC is not asserted at that time (i.e. is late or is missing). Counts misinserted cells dropped as a result of address look-up failure. Counts cells dropped as a result of CRC10 failure. AAL5-ABR only. Reserved, should be cleared. 0x02 0x04 0x06 1 MIC_COUNT CRC10E_COUNT — Hword Hword Hword Offset from UNI_STATT_BASE+PHY# × 8 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-78 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 31.11 ATM Exceptions The ATM controller interrupt handling involves two principal data structures: FCCEs (FCC event registers) and circular interrupt queues. Four priority interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ], the user determines which queue receives the interrupt. Channel Rx buffer, Rx frame, or Tx buffer events can be masked by clearing interrupt mask bits in RCT and TCT. After an interrupt request, the host reads FCCE. If FCCE[GINTx] = 1, at least one entry was added to one of the interrupt queues. After clearing FCCE[GINTx], the host processes the valid interrupt queue entries and clears each entry’s valid bit. The host follows this procedure until it reaches an entry with V = 0. See Section 31.11.2, “Interrupt Queue Entry.” The host controls the number of interrupts sent to the core using a down counter in the interrupt queue’s parameter table; see Section 31.11.3. For each event sent to an interrupt queue, a counter (that has been initialized to a threshold number of interrupts) is decremented. When the counter reaches zero, the global interrupt, FCCE[GINTx], is set. 31.11.1 Interrupt Queues Interrupt queues are located in external memory. The parameters of each queue are stored in a table. See Section 31.11.3, “Interrupt Queue Parameter Tables.” When an interrupt occurs, the CP writes a new entry to the interrupt queue, the V bit is set, and the queue pointer (INTQ_PTR) is incremented. Once the CP uses an entry with W = 1, it returns to the first entry in the queue. If the CP tries to overwrite a valid entry (V = 1), an overflow condition occurs and the queue’s overflow flag, FCCE[INTOx], is set. The interrupt queue structure is displayed in Figure 31-55. Word INTQ_BASE V=0 V=0 V=0 Software (Core) Pointer V=1 V=1 V=1 INTQ_PTR V=0 V=0 V=0 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=0 W=1 Invalid Invalid Invalid Interrupt Entry Interrupt Entry Interrupt Entry Invalid Invalid Invalid Figure 31-55. Interrupt Queue Structure MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-79 ATM Controller and AAL0, AAL1, and AAL5 31.11.2 Interrupt Queue Entry Each one-word interrupt queue entry provides detailed interrupt information to the host. Figure 31-56 shows an entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 V — W — Channel Code (CC) TBNR RXF BSY TXB RXB Figure 31-56. Interrupt Queue Entry Table 31-42 describes interrupt queue entry fields. Table 31-42. Interrupt Queue Entry Field Description Offset 0x00 Bits 0 Name V Description Valid interrupt entry 0 This interrupt queue entry is free and can be use by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. Reserved, should be cleared. Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. Reserved, should be cleared. 1 2 3–10 11 — W — TBNR Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent only if TCT[BNM] = 1. This interrupt has an associated channel code. Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case, an abort frame transmission is sent (last cell with length=0), the channel is taken out of the APC, and the TCT[VCON] flag is cleared. RXF Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt has an associated channel code. Busy condition. The BD table or the free buffer pool associated with this channel is busy. Cells were discarded due to this condition. This interrupt has an associated channel code. Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code. Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code. Channel code specifies the channel associated with this interrupt. 12 13 14 15 0x02 — BSY TXB RXB CC 31.11.3 Interrupt Queue Parameter Tables The interrupt queue parameters are held in parameter tables in the dual-port RAM; see Table 31-43. INTT_BASE in the parameter RAM points to the base address of these tables. Each of the four interrupt queues has its own parameter table with a starting address given by INTT_BASE+ RCT/TCT[INTQ] × 16. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-80 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-43. Interrupt Queue Parameter Table Offset 1 0x00 0x04 0x08 Name INTQ_BASE INTQ_PTR INT_CNT Width Word Word Half Word Half Word Word Description Base address of the interrupt queue. User-defined. Pointer to interrupt queue entry. Initialize to INTQ_BASE. Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for each interrupt. When INT_CNT reaches zero, the queue’s global interrupt flag FCCE[GINTx] is set. Interrupt initial count. User-defined global interrupt threshold—the number of interrupts required before the CP issues a global interrupt (FCCE[GINTx]). Interrupt queue entry. Must be initialized to the entry pointed to by INTQ_PTR, which is initially the first empty entry of the queue. Note that after an overrun occurs, this entry must be reset to the entry pointed to by INTQ_PTR to reenable interrupt processing. 0x0A 0x0C INT_ICNT INTQ_ENTRY 1 Offset from INTT_BASE+RCT/TCT[INTQ] × 16 31.12 The UTOPIA Interface The ATM controller interfaces with a PHY device through the UTOPIA interface. The MPC8280 supports UTOPIA level 2 for both master and slave modes. 31.12.1 UTOPIA Interface Master Mode Cell transfer on an ATM device (with single or multiple PHYs) uses cell-level handshaking as defined in the UTOPIA standards. The FCC does not pause cell transmission by the PHY and does not stop receiving cells from the PHY. UTOPIA master signals are shown in Figure 31-57. TXDATA[15–0]/[7–0] TxSOC TXENB MPC8280 TXPRTY TXCLK TXCLAV[3–0]/TxClav TXADD[4–0] MPC8280 RXDATA[15–0]/[7–0] RXSOC RXENB RXPRTY RXCLK RXCLAV[3–0]/RxClav RXADD[4–0] Figure 31-57. UTOPIA Master Mode Signals MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-81 ATM Controller and AAL0, AAL1, and AAL5 Table 31-44 describes UTOPIA master mode signals. Table 31-44. UTOPIA Master Mode Signal Descriptions Signal TxDATA[15–0]/[7–0] TxSOC TxENB TxClav/TxCLAV[3–0] TxPRTY TxCLK Description Carries transmit data from the ATM controller to a PHY device. TxDATA[15]/[7] is the msb when using UTOPIA 16/8, TxDATA[0] is the lsb. Transmit start of cell. Asserted by the ATM controller when the first byte of a cell is sent on TxDATA lines. Transmit enable. Asserted by the ATM controller when valid data is placed on the TxDATA lines. Transmit cell available. Asserted by the PHY device to indicate that the PHY has room for a complete cell. Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA bits. Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV, TxPRTY signals. All the above signals are sampled at low-to-high transitions of TxCLK. Transmit address. Address bus from the ATM controller to the PHY device used to select the appropriate M-PHY device. Each M-PHY device needs to maintain its address. TxADD[4] is the msb. Carries receive data from the PHY to the ATM controller. RxDATA[15]/[7] is the msb when using UTOPIA 16/8, RxDATA[0] is the lsb. Receive start of cell. Asserted by the PHY device as the first byte of a cell is received on RxDATA. Receive enable. An ATM controller asserts to indicate that RxDATA and RxSOC will be sampled at the end of the next RxCLK cycle. For multiple PHYs, RxENB is used to three-state RxDATA and RxSOC at each PHY’s output. RxDATA and RxSOC should be enabled only in cycles after those with RxENB asserted. TxADD[4–0] RxDATA[15–0]/[7–0] RxSOC RxENB RxClav/RxCLAV[3–0] Receive cell available. Asserted by a PHY device when it has a complete cell to give the ATM controller. RxPRTY Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA. If there is a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is discarded. See Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR),” and Section 31.10.7, “UNI Statistics Table.” Receiver clock. Synchronization reference for RxDATA, RxSOC, RxENB, RxCLAV, and RxPRTY, all of which are sampled at low-to-high transitions of RxCLK. Receive address. Address bus from the ATM controller to the PHY device used to select the appropriate M-PHY device. Each M-PHY device needs to maintain its address. RxADD[4] is the msb. RxCLK RxADD[4–0] 31.12.1.1 UTOPIA Master Multiple PHY Operation The MPC8280 supports two polling modes: • Direct polling uses CLAV[3–0] with PHY selection using ADD[1–0]. Up to four PHYs can be supported. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-82 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 • Single CLAV polling uses Clav and ADD[4–0]. ATM controller polls all active PHYs starting from PHY address 0x0 to the address written in FPSMR[LAST_PHY]. Up to 31 PHY devices are supported. Both modes support round-robin priority or fixed priority, described in Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR).” 31.12.2 UTOPIA Interface Slave Mode In UTOPIA slave mode (single or multiple PHY), cells are transferred using cell-level and octet-level handshakes as defined by the UTOPIA level-2 standard. The FCC allows cell transfer to be halted or paused. If the master negates TXENB, the cell that the FCC is transmitting is halted. If the master negates RXENB, the cell that the FCC is receiving is paused. Note the following restriction on halting a cell transfer: there cannot be a halt immediately before the transfer of the last data word. There is no restriction on pausing a cell transfer. UTOPIA slave signals are shown in Figure 31-58. TXDATA[15–0]/[7–0] TXSOC TXENB MPC8280 TXPRTY TXCLK TXCLAV TXADD[4–0] MPC8280 RXDATA[15–0]/[7–0] RXSOC RXENB RXPRTY RXCLK RXCLAV RXADD[4–0] Figure 31-58. UTOPIA Slave Mode Signals Table 31-45 describes UTOPIA slave mode signals. Table 31-45. UTOPIA Slave Mode Signals Signal TxDATA[15–0]/[7–0] TxSOC TxENB TxCLAV TxPRTY Description Transmit data bus. Carries transmit data from the ATM controller to the master device. TxDATA[15]/[7] is the msb, TxDATA[0] is the lsb. Transmit start of cell. Asserted by an ATM controller as the first byte of a cell is sent on the TxDATA lines. Transmit enable. An input to the ATM controller. It is asserted by the UTOPIA master to signal the slave to send data in the next TxCLK cycle. Transmit cell available. Asserted by the ATM controller to indicate it has a complete cell to transmit. Transmit parity. Asserted by the ATM controller. It is an odd parity bit over the TxDATA. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-83 ATM Controller and AAL0, AAL1, and AAL5 Table 31-45. UTOPIA Slave Mode Signals (continued) Signal TxCLK Description Transmit clock. Provides the synchronization reference for the TxDATA, TxSOC, TxENB, TxCLAV, and TxPRTY signals. All of the above signals are sampled at low-to-high transitions of TxCLK. Transmit address. Address bus from the master to the ATM controller used to select the appropriate M-PHY device. Receive data bus. Carries receive data from the master to the ATM controller. RxDATA[15]/[7] is the msb, RxDATA[0] is the lsb. Receive start of cell. Asserted by the master device whenever the first byte of a cell is being received on the RxDATA lines. Receive enable. Asserted by the master device to signal the slave to sample the RxDATA and RxSOC signals. Receive cell available. Asserted by the ATM controller to indicate it can receive a complete cell. Receive parity. Asserted by the PHY device. It is an odd parity bit over the RxDATA[15–0]. If there is a RxPRTY error and the receive parity check FPSMR[RxP] is cleared, the cell is discarded. See Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR),” and Section 31.10.7, “UNI Statistics Table.” Receive clock. Provides the synchronization reference for the RxDATA, RxSOC, RxENB, RxCLAV, and RxPRTY signals. All the above signals are sampled at low-to-high transitions of RxCLK. Receive address. Address bus from master to the ATM controller device used to select the appropriate M-PHY device. TxADD[4–0] RxDATA[15–0]/[7–0] RxSOC RxENB RxCLAV RxPRTY RxCLK RxADD[4–0] 31.12.2.1 UTOPIA Slave Multiple PHY Operation The user should write the ATM controller PHY address in FPSMR[PHY ID]. 31.12.2.2 UTOPIA Clocking Modes The UTOPIA clock can be generated internally or externally. If the UTOPIA clock is to be generated internally, the user should assign one of the baud-rate generators to supply the UTOPIA clock. See Chapter 16, “CPM Multiplexing.” 31.12.2.3 UTOPIA Loop-Back Modes The UTOPIA interface supports loop-back mode. In this mode, the Rx and Tx UTOPIA signals are shorted internally. Output pins are driven; input pins are ignored. Note that in loop-back mode, the transmitter and receiver must operate in complementary modes. For example, if the transmitter is master, the receiver must be a slave (FPSMR[TUMS] = 0, FPSMR[RUMS] = 1). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-84 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Modes are selected through GFMR[DIAG], as shown in Table 31-46. Table 31-46. UTOPIA Loop-Back Modes DIAG 00 01 1x Normal mode Loop-back. UTOPIA Rx and Tx signals are shorted internally. Output pins are driven, input pins are ignored. Reserved Description 31.12.3 Extended Number of PHYs The MPC8280 has additional pin muxing to support 31 PHYs on both FCC1 and FCC2. To utilize this feature, do the following: • Program CMXUAR[MAD4] = 1 • Program CMXUAR[MAD3] = 1 • Select dedicated UTOPIA address lines for FCC2 in the parallel I/O (TxADDR[4:3], RxADDR[4:3]). Refer to Chapter 41, “Parallel I/O Ports,” of this document and Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).” 31.13 ATM Registers The following sections describe the configuration of the registers in ATM mode. 31.13.1 General FCC Mode Register (GFMR) The GFMR mode field should be programmed for ATM mode. To enable transmit and receive functions, ENT and ENR must be set as the last step in the initialization process. Full GFMR details are given in Section 30.2, “General FCC Mode Registers (GFMRx).” 31.13.2 FCC Protocol-Specific Mode Register (FPSMR) The FCC protocol-specific mode register (FPSMR), shown in Figure 31-59, controls various protocol-specific FCC functions. The user should initialize the FPSMR. Erratic behavior may result if there is an attempt to write to the FPSMR while the transmitter and receiver are enabled. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-85 ATM Controller and AAL0, AAL1, and AAL5 0 3 4 7 8 9 10 11 15 Field Reset R/W Addr 16 17 TEHS REHS ICD TUMS RUMS LAST PHY/PHY ID 0000_0000_0000_0000 R/W 0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11344(FPSMR3) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Reset R/W Addr — TPRI TUDC RUDC RXP TUMP — TSIZE RSIZE UPRM UPLM RUMP HECI HECC COS 0000_0000_0000_0000 R/W 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11346 (FPSMR3) Figure 31-59. FCC ATM Mode Register (FPSMR) Table 31-47 describes FPSMR fields. Table 31-47. FCC ATM Mode Register (FPSMR) Bits 0–3 Name TEHS Description Transmit extra header size. Used only in user-defined cell mode to hold the Tx user-defined cells’ extra header size. Values between 0–11 are valid. TEHS = 0 generates 1 byte of extra header; TEHS = 11 generates 12 bytes of extra header. Note: When working with a 16-bit UTOPIA interface, TEHS must represent an even number of header bytes (so the actual programmed value should be odd). Note: For IMA1 there is no extra header support for User defined cells so these bits should be programmed to zero for IMA support. Receive extra header size. Used only in user-defined cell mode to hold the Rx user-defined cells’ extra header size. Values between 0–11 are valid. For REHS = 0, the receiver expects 1 byte of extra header; for REHS = 11, it expects 12 bytes of extra header. Note: When working with a 16-bit UTOPIA interface, REHS must represent an even number of header bytes (so the actual programmed value should be odd). Note: For IMA1 there is no extra header support for User defined cells so these bits should be programmed to zero for IMA support. Idle cells discard 0 Discard idle cells (GFC, VPI, VCI, PTI =0) 1 Do not discard idle cells Note: For IMA 1 It is recommended to program ICD=1 so that idle cells will not be discarded. Idle cells should not occur on an IMA link, and their presence indicates an IMA protocol violation. Software should disable the discarding of idle cells, route the idle cells to a dedicated channel, and treat reception of cells on that dedicated channel as an indication of a system or system configuration error Transmit UTOPIA master/slave mode 0 Transmit UTOPIA master mode is selected (Use this mode for IMA support1) 1 Transmit UTOPIA slave mode is selected Receive UTOPIA master/slave mode 0 Receive UTOPIA master mode is selected (Use this mode for IMA support1) 1 Receive UTOPIA slave mode is selected 4–7 REHS 8 ICD 9 TUMS 10 RUMS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-86 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-47. FCC ATM Mode Register (FPSMR) (continued) Bits 11–15 Name LAST PHY/ PHY ID Description Last PHY. (Multiple PHY master mode only.) The UTOPIA interface polls all PHYs starting from PHY address 0 and ending with the PHY address specified in LAST PHY. (The number of active PHYs are LAST PHY+1). LAST PHY should be specified in both single-Clav and direct-polling modes. PHY ID. (Multiple PHY slave mode only.) Determines the PHY address of the ATM controller when configured as a slave in a multiple PHY ATM port. Note: For IMA 1 support this field must be programmed to the PHY address of the last PHY device; it is unrelated to the “virtual PHY number” for the IMA group programmed into VPHYNUM. Reserved, should be cleared. Transmitter priority. Used to adjust the default priority of the FCC transmitter. It is strongly recommended to set TPRI when in multi-PHY mode, or in single-PHY mode if the maximal bit rate (either internal or external rate) is higher than that of the other FCCs; for other modes, it should remain cleared. 0 Default operation 1 Prevents elevation to emergency mode Refer to Table 14-2. Transmit user-defined cells 0 Regular 53-byte cells (Disable this mode for IMA support1) 1 User-defined cells Receive user-defined cells 0 Regular 53-byte cells (Disable this mode for IMA support1) 1 User-defined cells Receive parity check. 0 Check Rx parity line 1 Do not check Rx parity line Transmit UTOPIA multiple PHY mode 0 Transmit UTOPIA single PHY mode is selected 1 Transmit UTOPIA multiple PHY mode is selected (Use this mode for IMA support1) Reserved, should be cleared. Transmit UTOPIA data bus size 0 UTOPIA 8-bit data bus size 1 UTOPIA 16-bit data bus size Receive UTOPIA data bus size 0 UTOPIA 8-bit data bus size 1 UTOPIA 16-bit data bus size UTOPIA priority mode. 0 Round robin. Polling is done from PHY zero to the PHY specified in LAST PHY. When a PHY is selected, the UTOPIA interface continues to poll the next PHY in order. 1 Fixed priority. Polling is done from PHY zero to the PHY specified in LAST PHY. When a PHY is selected, the UTOPIA interface continues to poll from PHY zero. UTOPIA polling mode. 0 Single Clav polling. Polling is done using Add[4–0] and Clav. Selection is done using Add[4–0]. Up to 31 PHYs can be polled. 1 Direct polling. Polling is done using Clav[3–0]. Selection is done using Add[1–0]. Up to 4 PHYs can be polled. 16–17 18 — TPRI 19 TUDC 20 RUDC 21 RxP 22 TUMP 23 24 — TSIZE 25 RSIZE 26 UPRM 27 UPLM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-87 ATM Controller and AAL0, AAL1, and AAL5 Table 31-47. FCC ATM Mode Register (FPSMR) (continued) Bits 28 Name RUMP Description Receive UTOPIA multiple PHY mode. 0 Receive UTOPIA single PHY mode is selected 1 Receive UTOPIA multiple PHY mode is selected (Use this mode for IMA support1) HEC included. Used in UDC mode only. 0 HEC octet is not included when UDC mode is enabled. 1 HEC octet is included when UDC mode is enabled. Receive HEC check 0 Do not check Rx HEC 1 Check Rx HEC. HEC errors are reported in UTOPIAE counter (see Section 31.10.7, “UNI Statistics Table”). This option can be used only in UTIPIA 8-bit data bus size. Coset mode enable 0 Check Rx HEC with no COSET 1 Check Rx HEC with COSET mode enabled 29 HECI 30 HECC 31 COS 1 MPC8264 and MPC8266 only. 31.13.3 ATM Event Register (FCCE)/Mask Register (FCCM) The FCCE register is the ATM controller event register when the FCC operates in ATM mode. When it recognizes an event, the ATM controller sets the corresponding FCCE bit. Interrupts generated by this register can be masked in FCCM. FCCE is memory-mapped and can be read at any time. Bits are cleared by writing ones to them; writing zeros has no effect. Unmasked bits must be cleared before the CP clears the internal interrupt request. FCCM is the ATM controller mask register. The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the corresponding interrupt in the FCCE. 0 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr — TIRU GRLI GBPB GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1 INTO0 0000_0000_0000_0000 R/W 0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/ 0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3) 16 31 Field Reset R/W Addr — 0000_0000_0000_0000 R/W 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Figure 31-60. ATM Event Register (FCCE)/FCC Mask Register (FCCM) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-88 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-48 describes FCCE fields. Table 31-48. FCCE/FCCM Field Descriptions Bits 0–4 5 Name — TIRU Reserved, should be cleared. Transmit internal rate underrun. A cumulative lag of seven cells has formed between the programmable rate and the actual rate for a specific Phy. A transmit internal rate counter expired and a cell was not sent, either because of slow CPM performance or slow PHY performance. TIRU may be set only when using transmit internal rate mode; see Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set in the free buffer pool’s parameter table. Description 6 7 8–11 12–15 GRLI GBPB Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set. The BUSY flag is also set in the free buffer pool’s parameter table. GINTx Global interrupt. Set when the number of events sent to the corresponding interrupt queue reaches the corresponding event threshold. See Section 31.11, “ATM Exceptions.” INTOx Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt queue. This occurs when the CP attempts to overwrite a valid interrupt entry. See Section 31.11.1, “Interrupt Queues.” — Reserved, should be cleared. 16–31 31.14 ATM Transmit Command The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register (CPCR), described in Section 14.4.1. The ATM TRANSMIT command (CPCR[opcode] = 0b1010, CPCR[SBC[code]] = 0b01110, CPCR[SBC[page]] = 0b00100 or 0b00101 (FCC1 or FCC2), CPCR[MCN] = 0b0000_1010) turns a passive channel into an active channel by inserting it into the APC scheduling table. Note that an ATM TRANSMIT command should be issued only after the channel’s TCT is completely initialized and the channel has BDs ready to transmit. Note also that CPCR[SBC[code]] = 0b01110 and not FCC1 or FCC2 code. Before issuing the command, the user should initialize COMM_INFO fields in the parameter RAM as described in Figure 31-61. Offset 0x86 0x88 0x8A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 — CTB PHY# Channel Code (CC) BT ACT PRI Figure 31-61. COMM_INFO Field MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-89 ATM Controller and AAL0, AAL1, and AAL5 Table 31-49 describes COMM_INFO fields. Table 31-49. COMM_INFO Field Descriptions Offset 0x86 Bits 0–4 5 Name — CTB Reserved, should be cleared. Connection tables bus. Used for external channels only 0 External connection tables reside on the 60x bus. 1 External connection tables reside on the local bus. PHY number. In single PHY mode this field should be cleared In multiple PHY mode this field is an index to the APC parameter table associated with this channel. ATM channel type 00 Other channel 01 VBR channel 1x Reserved APC priority level. 000 Highest priority (APC_LEVEL1) 111 Lowest priority (APC_LEVEL8). Channel code. The channel code associated with the current channel. Burst tolerance. For use by VBR channels only (ACT field is 0b01). Specifies the initial burst tolerance (GCRA burst credit) of the current VC. Description 6–10 11–12 PHY# ACT 13-15 PRI 0x88 0x8A 0-15 0-15 CC BT 31.15 Transmission Rate Modes—External, Internal, and Expanded Internal The ATM controller supports the following three rate modes: • External rate mode—The total transmission rate is determined by the PHY transmission rate. The FCC sends cells to keep the PHY FIFOs full; the FCC inserts idle/unassign cells to maintain the transmission rate. Internal rate mode—The total transmission rate is determined by the FCC internal rate timers. In this mode, the FCC does not insert idle/unassign cells. The internal rate mechanism is supported for the first four PHY devices (PHY address 0-3). Each PHY has its own FTIRR, described in Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” The FTIRR includes the initial value of the internal rate timer. A cell transmit request is sent when an internal rate timer expires. When using internal rate mode, the user assigns one of the baud-rate generators (BRGs) to clock the four internal rate timers. Internal rate expanded mode—The total transmission rate is determined by the FCC internal rate timers and by the assignment of rate per PHY. In this mode, the FCC does not insert idle/unassign cells. The internal rate expanded mode differs from the internal rate mode in that the internal rate mechanism is extended for 31 PHY devices (PHY addresses 0-30) and there cannot be a mix of external and internal rate PHYs. Expanded internal rate is configured by registers GFEMRx, FIRPERx, FIRSRx_HI, FIRSRx_LO, and by FTIRRx. Another feature of internal rate expanded mode is an indication of transmit underrun error status per PHY. When using internal rate expanded mode, the user assigns one of the baud-rate generators (BRGs) to clock the four internal rate timers, and any timer can trigger any PHY. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-90 Freescale Semiconductor • • ATM Controller and AAL0, AAL1, and AAL5 31.15.1 FCC Transmit Internal Rate Mode In internal rate mode the total transmission rate is the sum of the rates assigned for all PHYs. This register controls how internal rate is configured. In internal rate mode (GFEMR[TIREM] = 0), the internal rate assigned per PHY is configured by registers FTIRR[0-3]. In internal rate expanded mode (GFEMR[TIREM] = 1), registers FTIRR[0-3] control the available rates, but the PHY settings are configured in registers FIRPER, FIRSR_HI and FIRSR_LO. In TIREM = 0 mode internal rate can only be used for PHYs[0-3], whereas in TIREM = 1 mode up to 31 PHYs are supported. If TIREM = 1 mode is selected, the transmit internal rate underrun (TIRU) status per PHY may be read at any time in register FIRER. 31.15.1.1 FCC Transmit Internal Rate Register (FTIRRx) NOTE The source clock of the internal rate timers is the BRGs clock, which is configured in CMXUAR (refer to Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR)”). The frequency of this clock must be less than one half of the FCC Tx Clock of the UTOPIA interface. If GFEMR[TIREM] = 0, the first four PHY devices (address 00– 03) on FCC1 and FCC2 have their own transmit internal rate registers (FTIRRx_PHY0–FTIRRx_PHY3) for use in transmit internal rate mode. In this mode, the total transmission rate is determined by FCC internal rate timers. As a master, the controller only polls the PHY’s Clav status at the rate determined by the internal rate. As a slave, the controller attempts to insert cells into the FIFO at the internal rate. The controller can handle a lag of up to seven cells per PHY between the programmable and actual bus rate. When the cell count mismatch reaches seven, TIRU event is reported, see Section 31.13.3, “ATM Event Register (FCCE)/Mask Register (FCCM)”. Note that a mismatch occurs if the PHY rate or the CPM performance are lower then the internal rate. If GFEMR[TIREM] = 1, FTIRRx are used as group timers and PHYs at addresses 0-30 are assigned to a rate group by FIRSRx_HI and FIRSRx_LO. FTIRRx, shown in Figure 31-62, includes the initial value of the internal rate timer. The source clock of the internal rate timers is supplied by one of four baud-rate generators selected in CMXUAR; see Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).” Note that in slave mode, FTIRRx_PHY0 is used regardless of the slave PHY address. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-91 ATM Controller and AAL0, AAL1, and AAL5 0 1 7 Field Reset R/W Address TRM Initial Value 0000_0000 R/W GFEMR[TIREM=0] FCC1: 0x1131C (FTIRR1_PHY0), FCC1: 0x1131D (FTIRR1_PHY1), FCC1: 0x1131E (FTIRR1_PHY2), FCC1: 0x1131F (FTIRR1_PHY3), FCC2: 0x1133C (FTIRR2_PHY0), FCC2: 0x1133D (FTIRR2_PHY1), FCC2: 0x1133E (FTIRR2_PHY2), FCC2: 0x1133F (FTIRR2_PHY3). GFEMR[TIREM=1] FCC1: 0x1131C (FTIRR1_GRP0), FCC1: 0x1131D (FTIRR1_GRP1), FCC1: 0x1131E (FTIRR1_GRP2), FCC1: 0x1131F (FTIRR1_GRP3), FCC2: 0x1133C (FTIRR2_GRP0), FCC2: 0x1133D (FTIRR2_GRP1), FCC2: 0x1133E (FTIRR2_GRP2), FCC2: 0x1133F (FTIRR2_GRP3). Figure 31-62. FCC Transmit Internal Rate Register (FTIRR) Table 31-50 describes FTIRRx fields. Table 31-50. FTIRR x Field Descriptions Bit 0 Name TRM (TIREM=0) TRM (TIREM=1) 1–7 Initial Value PHY transmit mode 0 External rate mode. 1 Internal rate mode. Group transmit mode 0 Group rate timer [x] disabled. 1 Internal rate timer for Group[x] is enabled and division factor is set by Initial Value field. The initial value of the internal rate timer. A value of 0x7F produces the minimum clock rate (BRG CLK divided by 128); 0x00 produces the maximum clock rate (BRG CLK divided by 1). Description Figure 31-63 shows how transmit clocks are determined. . PHY#0 Int rate timer PHY#1 Int rate timer BRG CLK PHY#2 Int rate timer PHY#3 Int rate timer PHY# 0 or GRP#0 Tx Rate PHY# 1 or GRP#1Tx Rate PHY# 2 or GRP#2 Tx Rate PHY# 3 or GRP#3 Tx Rate Figure 31-63. FCC Transmit Internal Rate Clocking 31.15.1.2 Example Suppose the MPC8280 is connected to four 155 Mbps PHY devices and the maximum transmission rate is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs. The BRG CLK should be set according to the highest rate. If the CPM clock is 133 MHz and the BRG CLK is 66 MHz, the BRG should be programmed to divide the CPM clock by 181 to generate cell transmit requests every 362 system clocks: MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-92 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 ( 66MHz × ( 53 × 8 ) ) ------------------------------------------------- = 181 155.52Mbps For the 155 Mbps PHY, the FTIRR divider should be programmed to zero (the BRG CLK is divided by one); for the rest of the 10 Mbps PHYs, the FTIRR divider should be programmed to 14 (the BRG CLK is divided by 15). See also Section 31.17.1, “Using Transmit Internal Rate Mode.” 31.15.1.3 Internal Rate Programming Model The programming sequence in TIREM = 0 mode is as follows: 1. Clear GFEMRx[TIREM] 2. Program FTIRRx The programming sequence in TIREM = 1 mode is as follows: 1. 2. 3. 4. 5. Clear FTIRRx[TRM] Set GFEMRx[TIREM] Program FIRSRx_HI and FIRSRx_LO Program FTIRRx Program FIRPERx If FTIRRx are set to generate same order of magnitude rates, setting round robin polling mode is more adequate than fixed priority mode. To reduce the risk of transmit underrun if there are a few PHYs with high internal rate and a number of PHYs with a low internal rate, the fast PHYs should be assigned consecutive addresses starting at 0 and fixed priority mode should be chosen. 31.15.1.4 FCC Transmit Internal Rate Port Enable Registers (FIRPERx) This register enables internal rate transmission for PHYs[0-30]. It is valid only if GFEMR[TIREM] = 1. If a PHY is not enabled in FIRPER, all TxClav indications from that PHY will be masked. The user should configure FIRPER according to the PHY addresses which are being used on the UTOPIA bus and should not enable PHYs with addresses larger then the last PHY address set by FPSMR[Last PHY]. PHYs can be enabled or disabled at any time—for example, if a TIRU event has occurred. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-93 ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 0000_0000_0000_0000 R/W 0x11380 (FIRPER1), 0x113A0 (FIRPER2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 Reset R/W Addr 0000_0000_0000_0000 R/W 0x11382 (FIRPER1), 0x113A2 (FIRPER2) — Figure 31-64. FCC Transmit Internal Rate Port Enable Register (FIRPER x) Table 31-51 describes FIRPERx fields. Table 31-51. FIRPERx Field Descriptions (TIREM=1) Bit 0–15 Name PEy Description Port enable 0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked. 1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by register FIRSR_HI (refer to Section 31.15.1.6, “FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO)”). Port enable. 0 Transmit internal rate for PHY address y is disabled. TxClav from this PHY is masked. 1 Transmit Internal rate for PHY address y is enabled. The rate assigned for PHY y is selected by register FIRSR_LO (refer to Section 31.15.1.6, “FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO)”). Reserved, should be cleared. 16–30 PEy 31 — 31.15.1.5 FCC Internal Rate Event Registers (FIRERx) Transmit internal rate underrun (TIRU) errors are reported for any PHY that has a transmission deficiency of 8 cells. Under this condition and in internal rate mode only, FCCE[TIRU] is set, and if the corresponding bit in the FCC mask register (FCCM[TIRU]) is set, an interrupt is generated. If TIREM = 1, the TIRU status per PHY can be read at any time in the FCC internal rate event register (FIRER). Once FIRER[TIRUy] error status is set, it can be cleared only by writing 1 to it. To prevent an underrun PHY from continuously reporting errors, it can be disabled by FIRPER. The sequence of disabling a PHY is as follows: • Disable PHY y by clearing FIRPER[y] • Clear event FIRER[y] by writing 1 to it • Clear event FCCE[TIRU] by writing 1 to it MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-94 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reset R/W Addr 16 17 18 19 20 0000_0000_0000_0000 R/W 0x11384 (FIRER1), 0x113A4 (FIRER2) 21 22 23 24 25 26 27 28 29 30 31 Field TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Reset R/W Addr 0000_0000_0000_0000 R/W 0x11386 (FIRER1), 0x113A6 (FIRER2) — Figure 31-65. FCC Internal Rate Event Register (FIRERx) Table 31-52 describes FIRERx fields. Table 31-52. FIRERx Field Descriptions (TIREM=1) Bit 0–30 Name TIRUy Description Transmit internal rate underrun 0 There is no transmission underrun for this PHY. 1 Transmit internal rate underrun or PHY address y has occurred. Bit is cleared by writing 1 to it. Writing 0 has no effect on value. Reserved, should be cleared. 31 — 31.15.1.6 FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO) If TIREM = 1, each PHY can be assigned one of four rates, as configured by the four FCC transmit internal rate timers. The FCC internal rate selection registers (FIRSRx_HI, FIRSRx_LO), shown in Figure 31-66 and Figure 31-67, assign rate group to each of the PHYs. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-95 ATM Controller and AAL0, AAL1, and AAL5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr 16 GS0 GS1 GS2 GS3 GS4 GS5 GS6 GS7 0000_0000_0000_0000 R/W 0x11388 (FIRSR1_HI), 0x113A8 (FIRSR2_HI) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Reset R/W Addr GS8 GS9 GS10 GS11 GS12 GS13 GS14 GS15 0000_0000_0000_0000 R/W 0x1138A (FIRSR1_HI), 0x113AA (FIRSR2_HI) Figure 31-66. FCC Internal Rate Selection Register HI (FIRSRx_HI) Table 31-53 describes FIRSRx_HI fields. Table 31-53. IRSRx_HI Field Descriptions (TIREM=1) Bit 0–31 Name GSy Group select for PHY y 00The transmit internal rate 01The transmit internal rate 10The transmit internal rate 11The transmit internal rate Description for PHY address for PHY address for PHY address for PHY address y is controlled by FTIRRx_GRP0. y is controlled by FTIRRx_GRP1. y is controlled by FTIRRx_GRP2. y is controlled by FTIRRx_GRP3. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr GS16 GS17 GS18 GS19 GS20 GS21 GS22 GS23 0000_0000_0000_0000 R/W 0x1138C (FIRSR1_HI), 0x113AC (FIRSR2_HI) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Reset R/W Addr GS24 GS25 GS26 GS27 GS28 GS29 GS30 — 0000_0000_0000_0000 R/W 0x1138E (FIRSR1_HI), 0x113AE (FIRSR2_HI) Figure 31-67. FCC Internal Rate Selection Register LO (FIRSRx_LO) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-96 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Table 31-54 describes FIRSRx_LO fields. Table 31-54. FIRSRx_LO Field Descriptions (TIREM=1) Bit 0-29 Name GSy Description Group select for PHY y 00The transmit internal rate for PHY address y is 01The transmit internal rate for PHY address y is 10The transmit internal rate for PHY address y is 11The transmit internal rate for PHY address y is Reserved, should be cleared. controlled by controlled by controlled by controlled by FTIRRx_GRP0. FTIRRx_GRP1. FTIRRx_GRP2. FTIRRx_GRP3. 30–31 — 31.16 SRTS Generation and Clock Recovery Using External Logic The MPC8280 supports SRTS generation using external logic. If SRTS generation is enabled (TCT[SRT] = 1), the MPC8280 reads SRTS[0–3] from the external SRTS logic and inserts it into 4 cells whose SN fields equal 1, 3, 5, and 7, as shown in Figure 31-68. External SRTS Logic (N=3008 bits = 8 SAR PDU) fs Counter divided by N SRTS Latch 2.43 MHz (E1/T1) 155.52 MHz 1/64 p = 4 bit counter DMA reads new SRTS code SN=1 SN=3 SN=5 SN=7 Figure 31-68. AAL1 CES SRTS Generation Using External Logic For every eight cells, the external SRTS logic should supply a valid SRTS code. The CP reads the SRTS code from the bus selected in TCT[BIB] using a DMA read cycle of 1-byte data size. Each AAL1 CES channel can be programmed to select one of 16 addresses available for reading the SRTS result. The SRTS code should be placed on the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the sequence count cycle—SRTS[0] is inserted into the cell with SN = 7; SRTS[3] is inserted into the cell with SN = 1. For every eighth AAL1 CES SAR PDU, the SRTS logic samples a new SRTS and stores it internally. The SRTS is a sample of a 4-bit counter with a 2.43-MHz reference clock (for E1/T1) synchronized with the network clock. The MPC8280 supports clock recovery using an external SRTS PLL. If SRTS recovery is enabled (RCT[SRT]=1), the MPC8280 tracks the SRTS from four incoming cells whose SN field equals 1, 3, 5, and 7 and writes the result to external SRTS logic, as shown in Figure 31-69. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-97 ATM Controller and AAL0, AAL1, and AAL5 External SRTS Logic (N=3008 bits = 8 SAR PDU) fs Counter divided by N SRTS Latch 2.43 MHz (E1/T1) 155.52 MHz 1/64 p = 4 bit counter + SRTS Diff Latch VCO DMA writes new SRTS code SN=1 SN=3 SN=5 SN=7 Figure 31-69. AAL1 CES SRTS Clock Recovery Using External Logic On every eighth cell, the MPC8280 writes a new SRTS code to the external logic using the bus selected in RCT[BIB]. The CP writes the SRTS code using a DMA write cycle of 1-byte data size. Each AAL1 CES channel can be programmed to select one of 16 addresses available for writing the SRTS result. The SRTS code is written to the least-significant nibble of that address (SRTS[0]=lsb, SRTS[3]=msb). The SRTS is synchronized with the sequence count cycle—SRTS[3] is read from the cell with SN = 1 and SRTS[0] is read from the cell with SN = 7. The SRTS PLL makes periodic clock adjustments based on the difference between a locally generated SRTS and a remotely generated SRTS retrieved every eight received cells. 31.17 Configuring the ATM Controller for Maximum CPM Performance The following sections recommend ATM controller configurations to maximize CPM performance. 31.17.1 Using Transmit Internal Rate Mode When the total transmit rate is less than the PHY rate, use the transmit internal rate mode and configure the internal rate clock to the maximum bit rate required. (See 31.2.1.5, “Transmit External Rate and Internal Rate Modes.”) The PHY then automatically fills the unused bandwidth with idle cells, not the ATM controller. If the internal rate mode is not used, CPM performance is consumed generating the idle cell payload and using the scheduling algorithm to fill the unused bandwidth at the higher PHY rate. For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can configure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100 Mbps. If the system clock is 133 MHz, program a BRG to divide the system clock by 563 to generate a transmit cell request every 563 CPM clocks: ( 133MHz × ( 53 × 8 ) ) ---------------------------------------------------- = 563 100Mbps MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-98 Freescale Semiconductor ATM Controller and AAL0, AAL1, and AAL5 Set FTIRRx_PHY0[TRM] to enable the transmit internal rate mode and clear FTIRRx_PHY0[Initial Value] since there is no need to further divide the BRG. See Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” In external rate mode, however, the transmit cell request frequency is determined by the PHY’s maximum rate, not by internal FCC counters. If an OC-3 PHY is used with the ATM controller in external rate mode, the requests must be generated every 362 CPM clocks (assuming a 133-MHz CPM clock). If only 100 Mbps is used for real data, 36% of the transmit cell requests consume CPM processing time sending idle cells. 31.17.2 APC Configuration Maximizing the number of cells per slot (CPS) and minimizing the priority levels defined in the APC data structure improves CPM performance: • Cells per slot. CPS defines the maximum number of ATM cells allowed to be sent during a time slot. (See Section 31.3.3.1, “Determining the Cells Per Slot (CPS) in a Scheduling Table.”) The scheduling algorithm is more efficient sending multiple cells per time slot using the linked-channel field. Therefore, choose the maximum number of cells per slot allowed by the application. • Priority levels. The user can configure the APC data structure to have from one to eight priority levels. (See Section 31.3.6, “Determining the Priority of an ATM Channel.”) For each time slot, the scheduling algorithm scans all priority levels and maintains pointers for each level. Therefore, enable only the minimum number of priority levels required. 31.17.3 Buffer Configuration Using statically allocated buffers of optimal sizes also improves CPM performance: • Buffer size. Opening and closing buffer descriptors consumes CPM processing time. Because smaller buffers require more opening and closing of BDs, the optimal buffer size for maximum CPM performance is equal to the packet size (an AAL5 frame, for example). • Free buffer pool. When the free buffer pool is used, the CPM dynamically allocates buffers and links them to a channel’s BD. In static buffer allocation, the core assigns a fixed data buffer to each BD. (See Section 31.10.5.2, “Receive Buffer Operation.”) When allowed by the application, use static buffer allocation to increase CPM performance. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 31-99 ATM Controller and AAL0, AAL1, and AAL5 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-100 Freescale Semiconductor Chapter 32 ATM AAL1 Circuit Emulation Service NOTE The functionality described in this chapter is not available on the MPC8270. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. This chapter describes implementation of circuit emulation service (CES) using ATM adaptation layer type 1 (AAL1) on the MPC8280 and should be used as a supplement to Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5.” 32.1 Features The AAL1 CES features on the MPC8280 are as follows: • AAL1 — Reassembly – Reassembles PDU directly to external memory – Supports partially filled cells (configurable on a per-VC basis) – Sequence number (SN) protection (CRC-3 and parity) check – Implements a 3-step SN algorithm – Detects and handles lost or misinserted cell – Maintains bit count integrity (dummy cell insertion) – Dummy cell contents can be programmed by the user (per FCC) – Pointer verification in structured AAL1 cell format – Automatic synchronization using the structured pointer during reassembly – SRTS (synchronous residual time stamp) gathering on every cycle (8 cells) in unstructured AAL1 – Statistics gathering on a per-VC basis: – AAL1 valid cell count – AAL1 lost cell count – AAL1 misinserted cell count – AAL1 pointer mismatch/parity error – AAL1 Rx buffer pre-overflow — Segmentation – Segment PDU directly from external memory MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-1 ATM AAL1 Circuit Emulation Service • Partially filled cells support (configurable on a per-VC basis) Sequence number generation Sequence number protection (CRC-3 and even parity) generation Pointer generation during segmentation in structure AAL1 cell format Clock recovery using external SRTS logic during reassembly in unstructured AAL1 Statistics gathering on a per-VC basis: – AAL1 Tx cell count – AAL1 Tx buffer underrun Circuit emulation service (CES) — ATM to TDM – Structured and unstructured data are transferred between the ATM and MCC automatically without CPU intervention – In case of pre-underrun, the MCC start sending the last frame or the user-defined underrun template. The MCC and ATM controller automatically perform slip control with no CPU intervention. – In case of pre-overrun, the ATM receiver discards incoming cells until the MCC transmitter empties enough buffers for the receiver to restart. – Supports common channel signaling (CCS) – Supports channel associated signaling (CAS) – – – – – – – Up to 4 (one per trunk) CAS blocks residing in internal RAM when in automatic CAS mode and up to 8 blocks when in core CAS modify mode – Supports Nx64 E1/T1 channels – CAS routing table on per-VC basis – Automatic un-packing of the CAS information during reassembly and updating of the internal CAS block — TDM to ATM – Structured and unstructured data are automatically transferred between the MCC and ATM controller without CPU intervention – Supports common channel signaling (CCS) – Supports channel associated signaling (CAS) – Up to 4 (one per trunk) CAS blocks residing in internal RAM when in automatic CAS mode and up to 8 blocks when in core CAS modify mode – Support Nx64 E1/T1 channels – CAS routing table on per-VC basis – Automatic packing of CAS information from internal RAM to AAL1 Tx cells – Once per superframe, the CPM fetches the CAS information from an external framer and updates each internal CAS block. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-2 Freescale Semiconductor ATM AAL1 Circuit Emulation Service 32.2 AAL1 CES Transmitter Overview The MPC8280 supports both structured and unstructured AAL1 cell formats. For unstructured format, the transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data field. For structured format, the transmitter reads 46 or 47 bytes from the external buffer and inserts them into the AAL1 user data field. 32.2.1 Data Path The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is generated and inserted into the AAL1 Tx cell, as shown in Figure 32-1. SN SAR PDU header SNP SAR-PDU payload Figure 32-1. AAL1 Transmit Cell Format When the transmitter operates in structured data transfer (SDT) mode, two types of AAL1 cells are defined: P (pointer) format and non-P format. The two formats are shown below. Non-P format AAL1 cell SAR-PDU header AAL1 user information P format AAL1 cell SAR-PDU header ST pointer AAL1 user information Figure 32-2. AAL1 SDT Cell Types The transmitter generates the structured pointer according to the I.363.1 ITU standard and inserts the pointer exactly once every cycle (eight successive cells). The transmitter will insert the structured pointer, at the first opportunity, into a cell with an even sequence count (SC). When the end of the structure is not present in the current cycle, a P-format cell with a dummy pointer (127) is inserted into the last cell (SC=6) of the cycle. The MPC8280 supports partially filled cells configured on a per-VC basis. In this mode, only the valid octets are filled with user information; the rest of the cell is filled with padding octets. The MPC8280 supports synchronous residual time stamp (SRTS) generation using an external PLL. If this mode is enabled, the MPC8280 reads the SRTS code from external logic and inserts it into four outgoing cells. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” 32.2.2 Signaling Path The MPC8280 automatically handles the signaling information as part of the interworking function. The ATM transmitter packs the signaling information at the end of each superframe during the data segmentation process. Each VC is associated to one signaling block by an internal routing table; see MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-3 ATM AAL1 Circuit Emulation Service Section 32.4.6, “Channel Associated Signaling (CAS) Support.” The signaling information that resides in the internal RAM is inserted into the AAL1 cell according to the af-vtoa-0078 specification. The AAL1 structure is divided into two sections. The first section carries the Nx64 payload, and the second carries the signaling bits that are associated with the payload. The MPC8280 supports two framing modes: one for Nx64 DS1 ESF (extended superframe) framing, and the other for Nx64 E1 G.704 framing. See Figure 32-3. Each of the internal signaling blocks can be used to deliver only one of the framing formats; that is, they cannot be changed dynamically. 24xNx64 • • • • • • 16xNx64 ABCD N signaling nibbles ABCD AAL1 block T1 framing ABCD N signaling nibbles ABCD AAL1 block E1 framing Note: The CAS block size is (N+1) nibble if N is an odd number. Figure 32-3. AAL1 Framing Formats 32.3 AAL1 CES Receiver Overview The ATM controller supports both AAL1 structured and unstructured formats. For the unstructured format, 47 octets are copied to the current receive buffer and for the structured format, 46 (P format) or 47 (non-P format) octets are copied to the current receive buffer. The AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection (SNP) (CRC-3 and parity bit), is checked and the result is delivered to the 3-step-SN algorithm. The 3-step-SN algorithm (see Section 32.6.1, “The Three States of the Algorithm”) handles the lost or misinserted cells. This algorithm can detect one lost or misinserted cell and maintain synchronization. If more than one cell is lost or misinserted, the 3-step-SN algorithm switches to hunt mode where it stays until a cell with a valid SN field is received. After the receiver switches to hunt mode, it closes the RxBD, modifies the receive statistics, generates an optional interrupt to the CPU and performs a restart sequence. The restart sequence is implemented only when the ATM channel works in CES mode (RCT[CESM]). In CAS mode (RCT[CASM]), the ATM receiver channel begins the restart sequence by dropping all incoming cells and advancing to the beginning of the next super frame, which is the first BD after the one marked with EOSF (end of super frame). When this BD is ready and the adaptive counter reaches the ATM_Start threshold, the receiver’s write pointer is not longer in danger of overrunning the read pointer of the MCC transmitter; that is, it is safe to begin receiving cells again. The ATM receiver then begins the resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-4 Freescale Semiconductor ATM AAL1 Circuit Emulation Service received octet becomes the first byte of the new BD (new super frame). (See Section 32.5, “ATM-to-TDM Adaptive Slip Control” and Section 32.4, “Interworking Functions.”) Note that when the ATM channel is not in CES mode, no restart sequence is performed; the ATM receiver immediately starts hunting for the first valid cell. The first received octet becomes the first byte of the next BD. During reassembly, the ATM receiver channel’s 3-step-SN algorithm status is delivered to the pointer verification mechanism. (See Section 32.7, “Pointer Verification Mechanism.”) If the receiver operates in unstructured data format, the 3-step-SN algorithm status is delivered directly to the bit count integrity module. When partially filled cells arrive, the bit count integrity module copies only the valid octets from the received cell (or from the dummy cell if that cell is lost) to the current receive buffer. In unstructured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a valid sequence number (SN field). When one arrives, the receiver leaves the hunt state and begins receiving incoming cells. In structured AAL1 format, when the receive process begins, the receiver hunts for the first cell with a valid structured pointer (not a dummy pointer), that points to the start of a new structure. When one arrives, the receiver leaves the hunt state, opens a new buffer and begins receiving. The structured pointer points to the first octet of the structured block, which then becomes the first byte of the new buffer. During the reassembly process, if the receiver switches to hunt mode (due to the 3-step-SN algorithm or due to receiving two successive mismatched pointers), the ATM receiver closes the current RxBD, discards incoming cells, modifies the receive statistics accordingly and initiates a restart sequence. The receiver then waits for a cell with a valid structured pointer to regain synchronization and start receiving incoming cells again. The MPC8280 supports SRTS clock recovery using an external PLL. The MPC8280 tracks the SRTS from the four incoming cells and writes the SRTS code to external logic. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” The data flow for an AAL1 CES receiver is summarized in Figure 32-4. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-5 ATM AAL1 Circuit Emulation Service Process payload User information Bit count integrity Cell size Unstructured data format Valid cell Pointer verification Tag cell 3-step SN algorithm Valid SN SN/SNP verification Invalid SN Drop cell Valid/dummy/drop AAL1 cell stream Figure 32-4. AAL1 CES Receiver Data flow 32.4 Interworking Functions The MPC8280 supports the interworking of ATM and TDM. The TDM data processing is done by the MCC and the SI (refer to Chapter 29, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial Interface with Time-Slot Assigner,” for further information). The ATM controller processes the ATM data. Data forwarding between the ATM controller and the MCC can be done in two ways: • Automatic data forwarding. This mode enables automatic data forwarding between AAL1 and transparent mode over a TDM. • Core intervention. When an MCC receive buffer is full and its RxBD is closed, the MCC interrupts the core. The core copies the MCC’s receive buffer pointer to an ATM TxBD and sets the ready bit (TxBD[R]). Similarly, when an ATM receive buffer is full and its RxBD is closed, the core services the ATM controller’s interrupt by copying the ATM receive buffer pointer to an MCC TxBD and setting TxBD[R]. This mode is useful when additional core processing is required. Possible interworking applications are as follows: • • • Circuit emulation service (CES) Carrying voice over ATM Multiplexing low speed services, such as voice and data, onto one ATM connection 32.4.1 Automatic Data Forwarding The basic concept of automatic data forwarding is to program the ATM controller and the MCC to process the same BD table (ring). The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity. That is, both receivers receive into buffers in which RxBD[E] = 0 and then set RxBD[E] when the buffer is full. For the MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-6 Freescale Semiconductor ATM AAL1 Circuit Emulation Service ATM receiver, set RCT[INVE] of the AAL1 CES-specific areas of the receive connection table; see Section 32.9.1, “Receive Connection Table (RCT).” For the MCC receiver, set CHAMR[EP]. 32.4.1.1 ATM-to-TDM When going from ATM to TDM (depicted in Figure 32-5), the ATM receiver reassembles data received from a particular channel to a specific BD table. The MCC transmitter is programmed to operate on the same table. When the ATM controller fills a receive buffer, the MCC controller sends it. The controllers synchronize on the ATM controller’s RxBD[E] and the MCC’s TxBD[R]. A threshold mechanism for the MCC transmitter is used to synchronize the automatic start of the ATM-to-TDM data forwarding. The transmitter waits until the start threshold is reached (enough cells are received) before sending the valid data. In effect, the MCC start threshold mechanism implements a jitter buffer designed to accommodate the CDV of the ATM network. In a CES application, software should first initialize the MCC transmitter, then initialize the ATM receiver. This way the MCC transmitter sends idle data (0xFF) until the ATM receiver fills enough buffers to reach the MCC start threshold. (The receiver is effectively filling a jitter buffer.) When the CES_Adaptive_Counter (CESAC) reaches the MCC_Start threshold, the MCC super channel polling CESAC starts sending the received data with the first frame SYNC. (The first octet using the first BD is sent on the first assigned time slot.) Section 32.5, “ATM-to-TDM Adaptive Slip Control,” shows the flow of ATM-to-TDM interworking. BD table TDM interface MCC Tx MCC Tx pointer Buffer 1 Buffer 2 Buffer 3 Buffer 4 0 1 1 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 UTOPIA interface ATM Rx ATM Rx pointer Note: The ATM Rx should be programmed to operate in inverted polarity E (Empty) bit. Buffer 5 Figure 32-5. ATM-to-TDM Interworking 32.4.1.2 TDM-to-ATM When going from TDM to ATM (depicted in Figure 32-6), the MCC receiver routes data from the TDM line to a specific BD table. The ATM transmitter is programmed to operate on the same BD table. When the MCC fills a receive buffer, the ATM controller sends it. The two controllers synchronize on the MCC’s RxBD[E] and the ATM controller’s TxBD[R]. In a CES application, first initialize the ATM transmitter, then initialize the MCC receiver and set CHAMR[EP]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-7 ATM AAL1 Circuit Emulation Service In order to prevent an overrun condition on the MCC receiver, the ATM transmitter should be programmed to work at a faster rate than the MCC super channel. This ensures that the ATM channel polls the common BD table at a higher rate than it is being filled by the MCC. In CES mode, the ATM controller ignores BSY (busy) events when the ATM tries to open a buffer that is not yet full; it continues polling the BD until the buffer is filled by the MCC receiver and then updates the relevant statistics; see Section 32.15, “Internal AAL1 CES Statistics Tables.” Note that if an overrun condition occurs on the MCC, despite the above mechanism, software should restart the MCC and ATM channels in order to recover. Figure 32-6 shows the flow of TDM-to-ATM interworking. BD table UTOPIA interface ATM Tx ATM Tx pointer Buffer 1 Buffer 2 Buffer 3 Buffer 4 0 1 1 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 TDM interface MCC Rx MCC Rx pointer Note: The MCC Rx should be programmed to operate in opposite polarity E (Empty) bit. Buffer 5 Figure 32-6. TDM-to-ATM Interworking 32.4.2 Timing Issues Use of the TDM interface assumes that all communicating entities are synchronized; that is, that they are using a synchronized serial clock. If the TDM interfaces are not synchronized, a slip can occur in the reassembly buffer. In order to prevent the overrun and underrun condition, the MPC8280 maintains an adaptive slip control using a set of 4 threshold pointers and a counter for each ATM-TDM (VC to super channel) connection. Before a buffer-not-ready event (ATM-to-TDM data forwarding) occurs at the MCC transmitter, the MCC buffer pointer reaches the MCC_Stop threshold. Consequently, the MCC pointer freezes on the last transmitted BD and starts sending the underrun template (or the last transmitted frame). In the meantime, the ATM receiver continues to write valid data and advance the ATM buffer pointer. When the adaptive counter CESAC reaches the MCC_start threshold and the MCC has finished sending a multiple frame size, the MCC exits the pre-underrun state, starts sending the valid received data and advances the MCC buffer pointer. (Refer to Section 32.5, “ATM-to-TDM Adaptive Slip Control.”) The same mechanism is implemented on the ATM side. When the ATM receiver (ATM-to-TDM data forwarding) reaches the ATM_Stop threshold (pre-overrun), the ATM controller switches to hunt mode and discards the channel’s incoming cells. In the meantime, the MCC transmitter continues to send valid data and advance the MCC buffer pointer. When CESAC falls to the ATM_start threshold, the ATM write pointer is advanced to the first BD after the one marked with EOSF (in CAS mode). When this BD is ready MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-8 Freescale Semiconductor ATM AAL1 Circuit Emulation Service and CESAC reaches the ATM_Start threshold, the receiver’s write pointer is not longer in danger of overrunning the read pointer of the MCC transmitter; that is, it is safe to begin receiving cells again. The ATM receiver then begins the resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first received octet becomes the first byte of the new BD (new super frame). (Refer to Section 32.5, “ATM-to-TDM Adaptive Slip Control.”) Note that when the ATM receiver is in hunt mode due to one of the following: • Sequence number protection error (SNPE) • Sequence count error (SCE) • Structured pointer error (SPE) • Slip condition The signaling information (CAS) and SRTS information is not updated by the ATM controller until the ATM receiver switches to SYNC mode, that is, a valid cell is received in unstructured cell format or a valid pointer is received in structured cell formats. Software should distinguish between the two types of overrun and underrun conditions: 1. The MCC and ATM controller can automatically recover from overruns and underruns caused by slips without any CPU intervention. (See Section 32.5, “ATM-to-TDM Adaptive Slip Control.”) 2. Global underrun (MCCE[GUN]) and overrun (MCCE[GOV]) conditions are errors that need CPU intervention because it is not known which channels are affected. The CPU should accordingly reinitialize the transmit parameters and/or the receive parameters to recover. 32.4.3 Clock Synchronization (SRTS, Adaptive FIFO) Clock synchronization methods, such as SRTS and adaptive FIFO, may be used to prevent reassembly buffer slip. The SRTS method may be implemented using external logic. The MPC8280 can read the SRTS from external logic and insert it into outgoing AAL1 cells and conversely, can track the SRTS from incoming AAL1 cells and deliver it to external logic. See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.” Alternatively, an adaptive FIFO method can be implemented under core control. Adaptive FIFO is a way to hold the bridging buffer at its mid-level point. One way to implement it is to periodically poll the adaptive counter CESAC (difference between the MCC and ATM data pointers) and use this difference as a pseudo-SRTS; see Section 32.5.1, “CES Adaptive Threshold Tables.” Writing the pseudo-SRTS to the same external PLL logic used in the SRTS method adjusts the TDM clock. 32.4.4 Mapping TDM Time Slots to VCs Any TDM time-slot combination can be routed to a specific data buffer using the MCC and its SI. (Refer to Chapter 29, “Multi-Channel Controllers (MCCs),” and Chapter 15, “Serial Interface with Time-Slot Assigner,” for further information.) A common set of data buffers (one BD table) should be used by the ATM controller to route both the receive and transmit data. For information about ATM buffers see Section 32.11, “Buffer Descriptors.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-9 ATM AAL1 Circuit Emulation Service 32.4.5 Trunk Condition According to the Bellcore standard, the interworking function should be able to transmit special payloads on both the ATM and TDM channels to signal alarm conditions (bellcore TR-NWT-000170). The trunk condition can be generated under core control. The core may deliver buffers containing special data (trunk condition payload) to the ATM controller or MCC or even overwrite data buffers being used by the channels. 32.4.6 Channel Associated Signaling (CAS) Support For applications requiring channel associated signaling (CAS) support, the CAS manipulation is done by an external framer. The MCC should be programmed to receive or transmit the internal CAS block transparently through the external framer’s serial interface. The internal CAS block (depicted in Figure 32-8) can be adjusted to comply with a specific framer’s serial interface. (See Section 32.4.7.1, “CAS Routing Table.”) 8-bits per channel Ch 1 Ch 2 Ch 3 •••••••• Ch 24 Framer serial interface for T1 signaling format XXXX ABCD 8-bits per channel Ch 1 Ch 2 Ch 3 •••••••• Ch 24 •••••••• XXXX ABCD Framer serial interface for T1 signaling format (SF) XXXX ABA’B’ 8-bits per channel Ch 1 Ch 2 Ch 3 •••••••• Ch 32 •••••••• XXXX ABA’B’ Framer serial interface for E1 signaling format XXXX ABCD •••••••• XXXX ABCD Note: The MCC should capture the signaling data on the last frame of a super frame. See Section 1.4.7.2, “TDM-to-ATM CAS Support”. Figure 32-7. Mapping CAS Data on a Serial Interface The MCC and ATM CAS are synchronized with the superframe block boundary. At the ATM side, the structured block size should be set to the superframe block size plus the size of the CAS block so that the structured pointer inserted by the ATM controller points to the start of the structured data block. At the MCC side, the MCC is synchronized with the frame sync signal; the external framer has the ability to place the signaling information at the appropriate place in a superframe. The MPC8280 supports an automatic mode for forwarding the signaling information from the TDM to the ATM and vice versa. The ATM controller maintains two CAS blocks per trunk (eight total). One contains the signaling information unpacked from the AAL1 cells (ATM-to-TDM), and the other contains the signaling information fetched from an external framer (TDM-to-ATM). All 8 CAS blocks reside in the internal RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-10 Freescale Semiconductor ATM AAL1 Circuit Emulation Service CAS block per trunk E1 CAS block (32 bytes) 0 1 • • • 31 XXXX XXXX XXXX • • XXXX ABCD ABCD ABCD • • ABCD T1 – ESF CAS block (24 bytes) 0 1 • • • 23 XXXX XXXX XXXX • • XXXX ABCD ABCD ABCD • • ABCD T1 – SF CAS block (24 bytes) 0 1 • • • 23 XXXX XXXX XXXX • • XXXX ABA’B’ ABA’B’ ABA’B’ • • ABA’B’ 1 ABCD 2 ABCD CAS block resides in the internal RAM. To allow maximum flexibility in working with external framers, the signaling nibble can occupy the first or second nibble in the CAS entry. ABCD XXXX Figure 32-8. Internal CAS Block Formats 32.4.7 Mapping VC Signaling to CAS Blocks Each ATM channel is connected to a specific CAS block. The ATM controller implements CAS routing tables (CRT) to maintain the routing of the signaling information from the AAL1 cells to the internal CAS blocks for receiving, and vice versa for transmitting. Each ATM channel is connected to one receive or transmit routing table. A CRT resides in a 32-byte space with each entry pointing to one signaling nibble. To allow maximum flexibility with external framers, the signaling nibble can occupy the first or second nibble in the internal CAS block (depicted in Figure 32-8). The CRT entries should be initialized only once before the ATM channel is enabled (receiver or transmitter). The number of entries that should be initialized must be equal to the number of active slots (channels) in the corresponding MCC super channel. Each super channel is mapped to a unique ATM connection (VC). The CRT entries are in ascending order based on the channel slots assigned for the MCC super channel (depicted in Figure 32-9). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-11 ATM AAL1 Circuit Emulation Service One MCC super channel that contains only 4 active channels F/S=0 XXXX ABCD 0 0 0 1 One ATM CAS routing table 0 0 0 0 0 0 0 0 0 1 2 23 Slot 0 Slot 1 Slot 2 •••••• Slot 23 Example of one MCC super channel in ESF framing (T1) containing 4 TDM slots connected to an ATM channel with one CAS routing table (CRT). See Section 1.4.7.1, “CAS Routing Table.” Figure 32-9. Mapping CAS Entry 32.4.7.1 CAS Routing Table Figure 32-10 shows the structure of a CAS routing table. The CP maintains a pointer which steps through the table and wraps back to the beginning of the table after servicing the last entry (W=1). Byte First signaling nibble W=0 W=0 W=0 ATM current pointer W=0 W=0 Last signaling nibble W=1 — — — — — — F/S F/S F/S F/S F/S F/S Signaling offset pointer Signaling offset pointer Signaling offset pointer Signaling offset pointer Signaling offset pointer Signaling offset pointer Figure 32-10. AAL1 CES CAS Routing Table (CRT) Figure 32-11 describes the structure of a CAS routing table entry. 0 1 2 3 7 Offset + 0x00 W — F/S Signaling offset pointer (SOP) Figure 32-11. AAL1 CES CAS Routing Table Entry MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-12 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-1 describes CAS routing table entry fields. Table 32-1. CAS Routing Table Entry Field Descriptions Bits 0 1 2 Name W — F/S Description Wrap bit. When set, this bit indicates the last circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. Reserved, should be cleared during initialization. First/Second. 0 Indicates that the signaling information occupies the first nibble in the CAS block (LSB). 1 Indicates that the signaling information occupies the second nibble in the CAS block (MSB). Signaling Offset Pointer. Offset of the signaling nibble from the internal CAS base address. Note that in ESF mode the maximum offset is 23 and in E1 framing format the maximum offset is 31. 3–7 SOP 32.4.7.2 TDM-to-ATM CAS Support During the segmentation process, the AAL1 CES transmitter reads the CAS data from the internal CAS block and packs the data and the signaling information at the end of an AAL1 super frame (depicted in Figure 32-3). All AAL1 functions operate normally (generating AAL1 PDU-headers, structured pointers, etc.). Each common (MCC, ATM) BD table should point to buffers that can contain a whole number of super frames. The last buffer of the super frame is marked as the end of a super frame (BD[EOSF]=1). After closing a buffer with the EOSF indication, the ATM transmitter processes the CAS data—reads it from the internal CAS block and inserts it into the cell payload at the transmit side. The EOSF indication in the BD is statically set by the CPU when initializing the BD table. Data I/F T1/E1 framer MCC Rx MCC Rx pointer Buffer 1 BD table per VC Buffer 2 UTOPIA interface ATM Tx ATM Tx pointer EOSF Buffer 3 EOSF Transmit CAS routing table Buffer 4 Super frame Super frame Shown in Figure 1-10 Incoming CAS block per trunk (internal RAM) CAS serial I/F T1/E1 framer MCC Rx Note: With CAS only 4 T1/E1 are supported. Figure 32-12. CAS Flow TDM-to-ATM The CAS block is automatically written to internal RAM by the MCC receiver using a separate TDM. When a super frame is received the MCC should be triggered with a super-frame (multi-frame) SYNC from the external framer. The incoming CAS block should be captured by the MCC only once for each super frame (on the last frame). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-13 ATM AAL1 Circuit Emulation Service The user may use external logic to convert the framer super-frame SYNC to trigger the MCC. The MCC captures the CAS block from the external framer and copies it transparently into one of four internal CAS blocks. Each byte in the CAS block contains a nibble of valid CAS information (depicted in Figure 32-8). Note that the buffer data size should not include the CAS octets. 32.4.7.2.1 CAS Mapping Using the Core (Optional) To avoid using another TDM dedicated to CAS information, the user can use a parallel interface (controlled by the core) to deliver the CAS information from the framer to the incoming CAS block. In this case, the core service routine reads the CAS information from the external framer and writes it to the incoming CAS block. To optimize the process, the framer can interrupt the core only when new information is received. 32.4.7.3 ATM-to-TDM CAS Support During the reassembly process, the AAL1 CES receiver unpacks the signaling information from the end of an AAL1 super frame (depicted in Figure 32-3) and places it in the internal CAS block (using the receive CAS routing table). All AAL1 functions operate normally (AAL1 PDU-header verification, bit count integrity, 3-step-SN algorithm, etc.). Each common (MCC, ATM) BD table should point to buffers that can contain a whole number of super frames. The last buffer of the super frame is marked with EOSF. After closing a buffer with an EOSF indication, the ATM receiver processes the CAS data (copies it to the internal CAS block from the AAL1 cell payload at the receive side). The EOSF indication in the BD is statically set by the CPU while initializing the BD table. See Figure 32-13. Data I/F T1/E1 framer MCC Tx MCC Tx pointer Buffer 1 BD table per VC Buffer 2 UTOPIA interface ATM Rx ATM Rx pointer EOSF EOSF Receive CAS routing table Buffer 3 Super frame Buffer 4 Super frame Shown in Figure 1-10 Outgoing CAS block per trunk (internal RAM) CAS serial I/F T1/E1 framer MCC Tx Note: With CAS only 4 T1/E1 are supported. Figure 32-13. CAS Flow ATM-to-TDM The CAS block is read from the internal RAM by the MCC. The MCC transmitter continuously reads the signaling information from one of the four outgoing internal CAS blocks and writes it transparently into MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-14 Freescale Semiconductor ATM AAL1 Circuit Emulation Service the external framer. Each byte in the CAS block contains one nibble of valid CAS information (depicted in Figure 32-8). Note that the buffer data size should not include the CAS octets. 32.4.7.3.1 CAS Updates Using the Core (Optional) To avoid using another TDM dedicated to CAS information, the user can use a parallel interface controlled by the core to deliver the outgoing CAS block to the framer. In this case, the ATM receiver should be programmed to operate in core CAS modify mode RCT[CCASM=1] (and RCT[CASM=1]). In this mode, the CP adds an entry to the ATM interrupt queue and sets the appropriate sticky bit in OCASSR each time an AAL1 cell is received with new signaling information (one or more signaling nibble has changed). (See Section 32.10, “Outgoing CAS Status Register (OCASSR).”) A core interrupt service routine can then write the updated outgoing CAS block to the framer. Note to avoid additional latency, the interrupt queue assigned to this connection should have a global interrupt threshold of one. See the INT_ICNT parameter discussed in Section 31.11.3, “Interrupt Queue Parameter Tables.” 32.5 ATM-to-TDM Adaptive Slip Control Two types of slip can occur in ATM-to-TDM operation: overrun and underrun. The two cases are handled by the MCC and ATM controller automatically without requiring CPU intervention. Overrun occurs when the MCC transmitter fetches data from the common BD table at a slower rate than it is being filled by the ATM receiver. In this case, the ATM write pointer meets the MCC read pointer and a BSY state is declared (an entry is added to the ATM interrupt table) on the ATM side. Underrun occurs when the MCC transmitter fetches data from the common BD table at a higher rate than it is being filled by the ATM receiver. In this case, the MCC read pointer reaches a BD that is not ready and a buffer-not-ready state is declared on the MCC side. In both slip cases, the MCC and ATM controller automatically recover and restart the ATM-to-TDM interworking function. In order to prevent overrun and underrun conditions, the MPC8280 maintains an adaptive slip control using a set of 4 threshold pointers for each ATM-TDM (VC - super channel) connection. The pre-underrun state (shown in Figure 32-14) occurs when the MCC read pointer goes faster than the ATM write pointer. When the adaptive counter reaches the MCC_Stop threshold, the MCC read pointer does not advance. At this point, the current BD (or the underrun template) is retransmitted a multiple of the frame size. In the meantime, the ATM receiver continues to receive valid data and advance the ATM write pointer. When the adaptive counter reaches the MCC_start threshold and the MCC has finished sending a multiple of the frame size, the MCC starts to transmit the valid received data and advance the MCC read pointer. Note that when the pre-underrun state occurs, the MCC transmitter can transmit the last buffer continuously or the underrun template. This is determined by the MCC channel configuration; see the CHAMR[UTM] bit description in Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-15 ATM AAL1 Circuit Emulation Service Mode.” In the example shown in Figure 32-14, the MCC is programmed to send the current BD during the pre-underrun condition. The pre-overrun state occurs when the ATM write pointer goes faster than the MCC read pointer. When the adaptive counter reaches the ATM_Stop threshold, the ATM write pointer does not advance. The ATM receiver waits until the adaptive counter reaches the ATM_start threshold. In the meantime, the MCC read pointer continues to process valid data from the common BD table. When CESAC reaches the ATM start threshold, the ATM write pointer advances to the first BD after the one that marked with EOSF (in CAS mode). When this BD is ready, the ATM receiver begins the resynchronization process: for unstructured AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits for the first valid cell that contains a valid pointer. The first received octet becomes the first byte of the new BD (new super frame). Note that this implementation for slip control provides a good interface for an adaptive FIFO implemented in software. CESAC represents the difference between the ATM and MCC pointers; the software application need only convert this value into an SRTS format. Figure 32-14 shows the 8-byte data structure used to implement ATM-to-TDM slip control. (Three of the bytes are unused.) MCC channel Core ATM channel Polling Count down Adaptive counter (1) ATM start threshold ATM stop threshold MCC start threshold MCC stop threshold Count up When the MCC closes the BD, the adaptive counter (CESAC) is decremented When the ATM controller closes the BD, the adaptive counter (CESAC) is incremented CES adaptive threshold table address: CATB + MCC_Super_Channel*8 1. 2. 3. 4. 5. 6. 7. NOTES The MCC start threshold, in effect, implements a CDV jitter buffer. MCC stop threshold should be programmed to (BD Table size -b) to prevent buffer underrun. ATM stop threshold should be programmed to (BD Table size - a) to prevent buffer overrun. The MCC and ATM stop thresholds determine the CDVT. The ATM start threshold determines the time the ATM receiver waits before restarting synchronization process. (MCC start - MCC stop) >= frame size. b and a are integers less the BD table size. Figure 32-14. Data Structure for ATM-to-TDM Adaptive Slip Control 32.5.1 CES Adaptive Threshold Tables The CES adaptive threshold tables (see Table 32-15) reside in the dual-port RAM and hold the CES thresholds on a per-VC basis. The CES adaptive threshold base (CATB), located in the AAL1 CES parameter RAM, points to the base address of these tables. Each AAL1-MCC channel has its own table with a starting address given by CATB + RCT[Super_Channel_Number]# × 8. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-16 Freescale Semiconductor ATM AAL1 Circuit Emulation Service 0 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 — ATM Stop Threshold MCC Stop Threshold 7 8 CES Adaptive Counter ATM Start Threshold MCC Start Threshold — 15 Figure 32-15. CES Adaptive Threshold Table Table 32-2 describes CES adaptive threshold table fields. Table 32-2. CES Adaptive Threshold Table Field Descriptions Offset1 0x00 Bits 0–7 Name — Description Reserved, should be cleared during initialization. 8–15 CESAC CES adaptive counter.This field contains the difference between the ATM write pointer and the MCC read pointer on the common BD table.This field should be cleared by the user during the channel initialization. 0x02 0–7 ASTP ATM stop threshold.This threshold determines the maximum amount of buffering (CDVT) that required in the common BD table (shown in Figure 32-16). When the CESAC reaches this value a pre-overrun condition occurs.This field should be defined by the user during the channel initialization. 8–15 ASTRT ATM start threshold.This threshold determines the Time interval that will take the ATM controller to restart the synchronize process (shown in Figure 32-16) after pre-overrun condition.This field should be defined by the user during the channel initialization. 0x04 0–7 MSTP MCC stop threshold.This threshold determines the minimum amount of buffering in the common BD table (shown in Figure 32-16).When the CESAC reaches this value a pre-underrun condition occur and the MCC starts to transmit the underrun template or the last BD (see Section 32.5, “ATM-to-TDM Adaptive Slip Control”).This field should be defined by the user during the channel initialization. 8–15 MSTRT MCC start threshold.This threshold determines the effective depth of the jitter buffer, the amount of buffering required to cope with the ATM network’s CDV (shown in Figure 32-16).When the CESAC reaches this value the MCC transmitter starts sending the valid data from the common BD table.This field should be defined by the user during the channel initialization. 0x06 1 0–15 — Reserved, should be cleared during initialization. The offset is CATB + RCT[Super_Channel_Number]# × 8 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-17 ATM AAL1 Circuit Emulation Service ATM-to-TDM BD table MCC Tx pointer 0 0 0 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 ATM Rx pointer MCC_Start Step 1: Initialize the MCC and ATM pointers to the same BD table. CESAC=0 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 W ATM-to-TDM BD table MCC Tx pointer 1 1 1 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 MCC_Start ATM Rx pointer W Step 2: When CESAC reaches MCC_Start, the MCC starts transmitting. CESAC=3 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 Step 3: Because the MCC is reading the data faster than the ATM, CESAC falls to the MCC_Stop threshold. The MCC pointer then freezes, and the current buffer1 is retransmitted for a multiple of the frame size. (The buffer size should be a multiple of the frame size.) CESAC=1 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 1 ATM-to-TDM BD table 0 0 0 0 1 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 MCC Tx pointer ATM Rx pointer W MCC_Start The MCC can optionally transmit the underrun template. Step 4: The MCC switches to pre-underrun state and continues to send the current buffer (the last buffer that was sent). When CESAC reaches MCC_Start and a multiple of complete frames has been sent, the MCC starts to transmit again (returns to Step 2 in this flow). Figure 32-16. Pre-Underrun Sequence MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-18 Freescale Semiconductor ATM AAL1 Circuit Emulation Service ATM-to-TDM BD table MCC Tx pointer 0 0 0 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 ATM Rx pointer MCC_Start Step 1: Initialize the MCC and ATM pointers to the same BD table. CESAC=0 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 W ATM-to-TDM BD table MCC Tx pointer 1 1 1 0 0 0 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 MCC_Start ATM Rx pointer W Step 2: When CESAC reaches MCC_Start, the MCC starts transmitting. CESAC=3 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 ATM-to-TDM BD table MCC Tx pointer 0 0 1 1 1 1 0 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 W ATM Rx pointer Step 3: The MCC reads the data slower than the ATM fills it. The ATM points to the last BD in the common BD table. CESAC=4 MCC_Start=3, MCC_Stop=1 ATM_Start=5, ATM_Stop=7-1=6 ATM-to-TDM BD table MCC Tx pointer 1 0 1 1 1 1 1 BD 1 BD 2 BD 3 BD 4 BD 5 BD 6 BD 7 ATM Rx pointer ATM_Start CESAC=6 W Step 4: The ATM wraps around, and CESAC reaches the ATM_Stop threshold. The ATM write pointer freezes on the current BD. The MCC continues to process the valid data. When the CESAC falls to the ATM_Start threshold, the ATM advances to the first BD after EOSF. Step 5: After CESAC reaches the ATM_Start threshold and the ATM advances to the BD after EOSF, the ATM resynchronizes and starts to receive valid data using the new BD (start of SF). Figure 32-17. Pre-Overrun Sequence MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-19 ATM AAL1 Circuit Emulation Service 32.6 3-Step-SN Algorithm The 3-step-SN algorithm is a fast and efficient state machine that has the ability to recover one lost or misinserted cell. The 3-step-SN algorithm does not add significant delay to the AAL1 CES reassembly process due to the fact that the decision to accept a cell is taken immediately after cell arrival. If a lost cell is detected, the receiver will insert a dummy cell. If a misinserted cell is detected, the receiver will discard the cell received after the misinserted cell. If more than one successive cell was lost or misinserted, the 3-step-SN algorithm will switch to hunt mode, where it stays until a cell with a valid SN field is received. 32.6.1 The Three States of the Algorithm The 3-step-SN algorithm has three states: 1. Hunt—The Hunt state is the initial state of the algorithm or the first state after the receiver loses its synchronization. In this state no cell is delivered to the Rx buffer. When a valid cell is detected, the algorithm switches to the Sync state and delivers the current cell to the Rx buffer. 2. Sync—The Sync state is the steady state of the algorithm. In this state any received cell is automatically passed to the Rx buffer. The algorithm will switch from this state when an invalid cell is received (SNP error), or it receives a cell that does not sequence with the last valid cell (SC error). 3. Sync Fail—The Sync Fail state is a transient state. In this state the receiver checks the difference between the received sequence count (RSC) and the expected sequence count (ESC). If the difference between the two (ESC-RSC) is -1, 0, or 1, the receiver switches to sync mode and either discards the current cell, receives the current cell, or inserts a dummy cell, correspondingly. In any other cases the receiver will switch to hunt mode and discard the current cell. SYNC SYNC SYNC ESC = RSC ESC = RSC ESC = RSC RSC = X RSC = X RSC = X ESC = RSC–1 ESC = RSC+1 ESC = RSC Insert dummy cell One cell was lost Discard current cell Misinserted cell Received current cell SNP fault ESC: Expected sequence count. RSC: Received sequence count. RSN=X: Invalid cell received or, a cell that does not match to the ESC. Figure 32-18. Recoverable Sync Fail Sequence Options MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-20 Freescale Semiconductor ATM AAL1 Circuit Emulation Service No valid SN Hunt mode Else Valid SN Valid SN ESC=RSC–1/0/1 Sync fail Sync mode Valid SN Invalid SN or out of sequence Figure 32-19. 3-Step-SN-Algorithm 32.7 Pointer Verification Mechanism After the 3-step-SN algorithm processes the incoming cells, the cells status (Valid, Tag, Drop or Dummy) is delivered to the pointer verification mechanism. This state machine calculates the expected received pointer. If the current cell is valid and supposed to deliver a pointer, the received pointer is compared with the expected one. In the case of pointer mismatch or pointer error (i.e parity error), the pointer state machine switches to “Pre-Hunt-Mode”. If the cell status is not valid (i.e Tag, Drop or Dummy) and it supposed to carry a pointer, the pointer declared a mismatch and the pointer state machine switches to “Pre-Hunt-Mode”. The receiver stays in this transient state for only one AAL1 cell cycle (8 successive cells). When the pointer received in this state is different from the expected one or had a non-valid status, the receiver switches to hunt mode where it stays until a valid cell with a “start” structured pointer is received to regain synchronization. Note that a “start” pointer is a valid pointer with a value not equal to 93 or 127. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-21 ATM AAL1 Circuit Emulation Service No pointer Hunt mode Pointer mismatch/error Missing pointer Valid pointer new structured Valid pointer Pre-hunt mode Sync mode Valid pointer Pointer mismatch/error Missing pointer Figure 32-20. Pointer Verification Mechanism 32.8 AAL-1 Memory Structure The CPM manages ATM traffic by means of transmit and receive buffer descriptors (BD) and by transmit and receive connection tables (referred to as TCTs and RCTs, respectively). Buffer descriptors are circular lists of pointers into transmit and receive buffer space in external memory. The following sections describe the organization and configuration of the buffer descriptors, TCTs, and RCTs. 32.8.1 AAL1 CES Parameter RAM The MPC8280 parameter RAM is used to configure the three FCCs. The CP also uses the parameter RAM to store operational and temporary values. When configured for ATM mode, MPC8280 overlays the configuration structures shown in the next tables. The following table includes fields for ATM operation generally and AAL1 CES fields particularly. Note that some of the values must be initialized by the user; values set by the CP should not be modified by the user. Table 32-3. AAL1 CES Field Descriptions Offset 0x00– 0x3F 0x40 Name — RCELL_TMP_BASE Width — Description Reserved, should be cleared during initialization. Hword Rx cell temporary base address. Points to a total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64 byte aligned. User-defined. Hword Tx cell temporary base address. Points to total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined. Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined. 0x42 TCELL_TMP_BASE 0x44 UDC_TMP_BASE MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-22 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-3. AAL1 CES Field Descriptions (continued) Offset 0x46 0x48 0x4A Name INT_RCT_BASE INT_TCT_BASE INT_TCTE_BASE Width Description Hword Internal receive connection table base. User-defined. Hword Internal transmit connection table base. User-defined. Hword Internal transmit connection table extension base. User-defined. Note that the TCT extension is not needed in AAL1 CES and that the AAL1 CES microcode uses this Hword to point to a CAS routing table. Word Word Word Word Reserved, should be cleared during initialization. External receive connection table base. User-defined. External transmit connection table base. User-defined. External transmit connection table extension base. User-defined. Note that the TCT extension is not needed in AAL1 CES and that the AAL1 CES microcode uses this Hword to point to a CAS routing table. User-defined cells mode only. The offset of the UEAD entry in the UDC extra header. Should be an even address. If RCT[BO]=01 UEAD_OFFSET should be in little-endian format. For example if UEAD entry is the first half word of the extra header in external memory, UEAD_OFFSET should be set to 2 (second half word entry in internal RAM). 0x4C 0x50 0x54 0x58 — EXT_RCT_BASE EXT_TCT_BASE EXT_TCTE_BASE 0x5C UEAD_OFFSET Hword 0x5E 0x60 0x62 0x64 0x66 0x5E 0x6A 0x6C — PMT_BASE APCP_BASE FBT_BASE INTT_BASE — UNI_STATT_BASE BD_BASE_EXT Hword Reserved, should be cleared during initialization. Hword Performance monitoring table base. User-defined. Hword APC parameters table base address. User-defined. Hword Free buffer pool parameters table base. User-defined. Hword Interrupt queue parameters table base. User-defined. — Reserved, should be cleared during initialization. Hword UNI statistics table base. User-defined. Word BD table base address extension. BD_BASE_EXT[0–7] holds the 8 left bits of the Rx/Tx BD table base address. BD_BASE_EXT[8–31] should be zero. User-defined. Base address of the address compression VP table/external CAM. User-defined. Base address of the address compression VC table. User-defined. Base address of the address compression VP1 table/EXT CAM1. User-defined. Base address of the address compression VC1 table. User-defined. 0x70 0x74 0x78 0x7C 0x80 0x82 VPT_BASE / EXT_CAM_BASE VCT_BASE VPT1_BASE / EXT_CAM1_BASE VCT1_BASE VP_MASK VCI_Filtering Word Word Word Word Hword VP mask for address compression lookup. User-defined. Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See Section 31.10.1.2, “VCI Filtering (VCIF).” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-23 ATM AAL1 Circuit Emulation Service Table 32-3. AAL1 CES Field Descriptions (continued) Offset 0x84 0x86 0x88 0x8A 0x8C 0x90 0x94 0x98 Reserved CRC32_PRES CRC32_MASK AAL1_SNPT_BASE Name GMODE COMM_INFO Width Description Hword Global mode. User-defined. See Section 31.10.1.3, “Global Mode Entry (GMODE).” Hword The information field associated with the last host command. User-defined. See Section 31.14, “ATM Transmit Command.” Hword Hword Word Word Word Reserved, should be cleared during initialization. Preset for CRC32. Initialize to 0xFFFFFFFF. Constant mask for CRC32. Initialize to 0xDEBB20E3. Hword AAL1 SNP protection look up table base address. (AAL1 and AAL1 CES only.) The 32-byte table resides in dual-port RAM and must be initialized by the user (See Section 32.14, “AAL1 Sequence Number (SN) Protection Table.”). Hword Reserved, should be cleared during initialization. Word External SRTS logic base address. (AAL1and AAL1 CES only.) Should be 16-byte aligned. 0x9A 0x9C 0xA0 — SRTS_BASE IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/unassign cell template (little-endian format). Should be 64-byte aligned. User-defined. The ATM header should be 0x0000_0000 or 0x0100_0000 (CLP=1). IDLE/UNASSIGN_SIZE Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode. EPAYLOAD Trm Word Word Reserved payload. Initialize to 0x6A6A6A6A. (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler (See RTSCR). For time stamp prescalar of 1µS, Trm should be set to 100 ms/1µs = 100,000. 0xA2 0xA4 0xA8 0xAC 0xAE 0xB0 Nrm Mrm TCR Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less then TCR sends only out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the APC minimum cell rate should be at least TCR. Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used by the CP. Should be 16 byte aligned. User-defined. 0xB2 ABR_RX_TCTE Additional CES parameters needed by the AAL1 microcode are described in the following table. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-24 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-4. AAL1 CES Parameters Offset 0x4A Name INT_RTCRT_BASE Width Description Hword Internal receive/transmit CAS routing table extension base. User-defined. Note that because AAL1 CES does not need the TCT extension, the AAL1 CES microcode uses this Hword to point to a CAS routing table. Should be 32 byte aligned. User-defined. Word External receive/transmit CAS routing table extension base. User-defined. Note that because AAL1 CES does not need the TCT extension, the AAL1 CES microcode uses this word to point to a CAS routing table. 0x58 EXT_RTCRT_BASE 0xB2 0xd0 0xE0 AAL1_INT_RX_CRT OCASSR Hword (CES only) Points to a reserved scratchpad area of 32 bytes in the dual-port RAM used by the CES microcode. Should be 32 byte aligned. User-defined. Byte Outgoing CAS Status Register. See Section 32.10, “Outgoing CAS Status Register (OCASSR).” Transmit Cell Temporary base address (64-byte aligned). Points to an external memory block reserved for partially filled cells (64 octets for each CES channel). This area is allocated by the user but used by the CP. TCELL_TMP_BASE_EXT Word 0xE4 0xE6 0xE8 IN_CAS_BLOCK_BASE Hword Incoming CAS Block Base (depicted in Figure 32-12). Points to dual-port RAM. Should be 32-byte aligned. User-defined. OUT_CAS_BLOCK_BASE Hword Outgoing CAS Block Base (depicted in Figure 32-10). Points to dual-port RAM. Should be 32-byte aligned. User-defined. AAL1_Int_STATT_BASE Hword AAL1 Internal Statistics Table Base. Points to dual-port RAM. Should be 16-byte aligned. User-defined. See Section 32.15, “Internal AAL1 CES Statistics Tables.” Hword ALL1 Dummy cell base address. Points to dual-port RAM area contains the AAL1 dummy cell template (little-endian format). Should be 64-byte aligned. User-defined. Hword CES adaptive threshold tables base address. Points to the dual-port RAM area containing the CES slip control thresholds and the adaptive counter See Section 32.15, “Internal AAL1 CES Statistics Tables.” Should be 8-byte aligned (8 octets for each AAL1-MCC channel). User-defined and should match the CATB value programmed in the MCC parameter RAM; see Section 29.3.3, “MCC Parameters for AAL1 CES Usage.” Word AAL1 External Statistics Table Base. Points to External memory. Should be 16-byte aligned (16 octets for each AAL1 channel).User-defined. See Section 32.16, “External AAL1 CES Statistics Tables.” 0xEA AAL1_DUMMY_CELL_ BASE CATB 0xEC 0xF0 AAL1_Ext_STATT_BASE 32.9 Receive and Transmit Connection Tables (RCT, TCT) The connection tables, RCT and TCT, hold channel configuration and temporary parameters for each receive and transmit channel (AAL type, connection traffic parameters, BDs’ parameters and temporary parameters used during segmentation and reassembly). The internal connection tables hold parameters for up to 128 channels (channels 0–127). In extended channel mode, parameters for channels 256 and above are kept in external memory. The only relationship between transmit and receive connection tables of the same channel is the CRT (CAS routing table); see Section 32.4.7.1, “CAS Routing Table.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-25 ATM AAL1 Circuit Emulation Service Each connection table entry resides in 32 bytes. The pointers to these connection tables reside in the parameter RAM. 32.9.1 Receive Connection Table (RCT) Figure 32-21 shows the format of an RCT entry. 0 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — PMT RBD_BASE MRBLR RBD_BASE CCASM CESM — PM RBD_Offset Protocol Specific. Refer to Section 32.9.1.1, “AAL1 CES Protocol-Specific RCT.” Cell Time Stamp — 1 2 GBL 3 BO 4 5 — 6 DTB — 7 BIB 8 — 9 10 SEGF 11 ENDF CASM 12 — ABRF 13 SYNC 14 AAL 15 INTQ RX Data Buffer Pointer (RXDBPTR) Figure 32-21. Receive Connection Table (RCT) Entry NOTE For an active channel, the CP uses a burst cycle to fetch the 32-byte RCT and writes back only the first 24 bytes. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-26 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-5 describes RCT fields. Table 32-5. RCT Field Descriptions Offset 0x00 Bits 0–1 2 3–4 Name — GBL BO Description Reserved, should be cleared during initialization. Global. Asserting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. Byte ordering—used for data buffers. 00 Reserved 01munged little endian 1x Big endian Reserved, should be cleared during initialization. Data buffers bus 0 Data buffers reside on the 60x bus. 1 Data buffers reside on the local bus. BD interrupt queues, free buffer pool, and CES external statistics tables bus placement 0 Reside on the 60x bus. 1 Reside on the local bus. Notes: 1. When in UDC mode (AAL5 or AAL1 or AAL1 CES), BDs and data should be placed on the same bus (RCT[DTB]=RCT[BIB]). 2. RCT[BIB] programming must be consistent across all CES receive channels because they share the same AAL1_Ext_STATT_BASE parameter. Reserved, should be cleared during initialization. OAM F5 segment filtering 0 Do not send cells with PTI=100 to the raw cell queue. 1 Send cells with PTI=100 to the raw cell queue. OAM F5 end-to-end filtering 0 Do not send cells with PTI=101 to the raw cell queue. 1 Send cells with PTI=101 to the raw cell queue. Reserved, should be cleared during initialization. AAL1 SYNC. The user should set this bit for first AAL1 synchronization. Used internally by the CP. Points to one of four interrupt queues available. 5 6 — DTB 7 BIB 8–9 10 — SEGF 11 ENDF 12 13 14–15 — SYNC INTQ MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-27 ATM AAL1 Circuit Emulation Service Table 32-5. RCT Field Descriptions (continued) Offset 0x02 Bits 0–3 4–10 11 Name — — CASM Internal use only. Initialize to 0. Internal use only. Initialize to 0. Common associated signaling mode. 0 CAS operation mode is disable. 1 CAS operation mode is enable. Reserved, should be cleared during initialization. AAL type 000 AAL0 —Reassembly with no adaptation layer 001 AAL1 —ATM adaptation layer 1 010 AAL5 —ATM adaptation layer 5 100 AAL2 —ATM adaptation layer 2. Refer to Chapter 33, “ATM AAL2.” 101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service All others reserved. Receive data buffer pointer. Holds real address of current position in the Rx buffer. Used for reassembly time-out. Whenever a cell is received, the MPC8280 time stamp timer is sampled and written to this field. See Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” Description 12 13–15 — AAL 0x04 0x08 — — RxDBPTR Cell Time Stamp 0x0C 0x0E-0 x18 0x1A 0x1C — RBD_Offset RxBD offset from RBD_BASE. Points to the channel’s current BD. User-initialized to 0; updated by the CP. — Protocol-specific area. Maximum receive buffer length. Used in both static and dynamic buffer allocation. Note that in CES mode (CESM=1) this value must be a multiple of 8 (MCC limited). Reserved, should be cleared during initialization. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed on-the-fly. — 0–1 2–7 MRBLR — PMT 8–15 0x1E 0–11 12 RBD_BASE RxBD base. Points to the first BD in the channel’s RxBD table. The 8 most-significant bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four least-significant bits of the address are taken as zeros. CCASM Core CAS modify. When this mode is enabled, the CP sets OCASSR[MCASBn] sticky bit each time the outgoing (ATM to TDM) CAS block is changed. 0 Core CAS modify mode is disabled. 1 Core CAS modify mode is enabled. See Section 32.10, “Outgoing CAS Status Register (OCASSR).” Circuit Emulation Service Mode. 0 CES operation mode is disable. Adaptive Slip control mechanism is disabled. 1 CES operation mode is enable. Adaptive Slip control mechanism is enabled. Reserved, should be cleared during initialization. Performance monitoring. Can be changed on-the-fly. 0 No performance monitoring for this VC. 1 Perform performance monitoring for this VC. Whenever a cell is received for this VC the performance monitoring table that its code is written in the PMT field is updated. 13 CESM 14 15 — PM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-28 Freescale Semiconductor ATM AAL1 Circuit Emulation Service 32.9.1.1 AAL1 CES Protocol-Specific RCT Figure 32-22 shows the AAL1 CES protocol-specific area of an RCT entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x0E Offset + 0x10 SRTS_DEV OCASB/SRTS_TMP — — — PFM — SRT INVE STF — Valid Octet Size (VOS) Offset + 0x12 SPV Offset + 0x14 Offset + 0x16 Offset + 0x18 Structured Pointer (SP) RBDCNT Block Size — RXBM SLIPIM — SN CASBS Super Channel Number Figure 32-22. AAL1 CES Protocol-Specific RCT Table 32-6 describes AAL1 CES protocol-specific RCT fields. Table 32-6. AAL1 CES Protocol-Specific RCT Field Descriptions Offset 0x0E Bits 0–3 4–7 8 Name Description SRTS_DEV Selects an SRTS device, whose address is SRTS_BASE[0–27] + SRTS_DEV[28–31]. The 16 byte-aligned SRTS_BASE is taken from the parameter RAM. — PFM Reserved, should be cleared during initialization. Partially filled mode. 0 Partially filled cells mode is not used. 1 Partially filled cells mode is used. The receiver copies only valid octets from the AAL1 cell to the Rx buffer. The number of the valid octets from the beginning of the AAL1 user data field is specified in the VOS (valid octet size) field. Synchronous residual time stamp. Unstructured format only. The MPC8280 supports clock recovery using an external SRTS PLL. The MPC8280 tracks the SRTS from the incoming four cells with SN = 1, 3, 5, and 7 and writes it to the external SRTS device. Every eight cells the CP writes a valid SRTS to external logic. (See Section 31.16, “SRTS Generation and Clock Recovery Using External Logic.”) 0 SRTS mode is not used. 1 SRTS mode is used. Inverted empty. 0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty). 1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty). Note that in CAS mode (CESM=1) this bit must be set by the user; see Section 32.4.1, “Automatic Data Forwarding.” Structured format. 0 Unstructured format is used. 1 Structured format is used. Note that although the structured format may be used, if the block size is one, the user should clear STF. Only non P-format AAL1 cells are received. The receiver does not check the AAL1 structured pointer because there is no need to when the block size is one. Reserved, should be cleared during initialization. 9 SRT 10 INVE 11 STF 12–15 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-29 ATM AAL1 Circuit Emulation Service Table 32-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued) Offset 0x10 Bits 0–3 Name Description OCASB/SR OCASB applies when in CAS mode. Outgoing CAS Block. Points to one of the eight TS_TMP available internal CAS blocks. The starting address of the table is OUT_CAS_BLOCK_BASE+OCASB¥ 32. See Section 32.4.7.1, “CAS Routing Table” for more details. Note that the RCT and TCT use the same CAS routing table (CRT). SRTS_TMP applies when not in CAS mode. Used by the CP to store the received SRTS code. After a cell with SN = 7 is received, the CP writes the SRTS code to the external SRTS device. Note that when the receiver is in hunt mode SRTS information is not updated. 4–9 10–15 — VOS Reserved, should be cleared during initialization. Valid octet size. Specifies the number of valid octets from the beginning of the AAL1 user data field. For unstructured, service values 1–47 are valid; for structured service, values 1-46 are valid. Partially filled cell mode only. Structured pointer valid. Should be user-initialized user to zero. Structured format only. Reserved, should be cleared during initialization. Structured pointer. Used by the CP to calculate the structured pointer. This field should be initialized by the user to zero. Used in structured format only. RxBD count. Indicates how many bytes remain in the current Rx buffer. Initialized with MRBLR whenever the CP opens a new buffer. Used only in structured format. Specifies the structured block size (Block Size = 0xFFF = 4 Kbytes maximum). Note that when working in CAS mode (CESM=1 and CASM=1), the block size should be programmed to the superframe block size plus the size of the CAS block. However, when working in basic mode (CES without CAS: CESM=1 and CASM=0) the block size should be programmed to the number of MCC slots (Nx64) per frame assigned to this channel. Reserved, should be cleared during initialization. Sequence number. Used by the CP to check incoming cell’s sequence number. 0x12 0 1–3 4–15 SPV — SP RBDCNT Block Size 0x14 0x16 — 0–11 12 13–15 — SN MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-30 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-6. AAL1 CES Protocol-Specific RCT Field Descriptions (continued) Offset 0x18 Bits 0–7 Name SCN Description Super Channel Number. This field should contain the MCC Super Channel Number that mapped to this ATM channel. This field must be initialized by the user in CES mode only. See Section 32.4.7, “Mapping VC Signaling to CAS Blocks.” Receive buffer interrupt mask 0 The receive buffer event of this channel is disabled. (The event is not sent to the interrupt queue.) 1 The receive buffer event of this channel is enabled. Slip interrupt mask 0 The slip interrupts SLIPS and SLIPE are both masked. 1 When the receiver switches to hunt mode due to a 3-step-SN algorithm fault, or due to two successive mismatched pointers, or due to a pre-overrun condition, the SLIPS interrupt is sent to the interrupt queue. See Section 32.6, “3-Step-SN Algorithm,” and Section 32.13, “AAL1 CES Exceptions.” When the receiver resynchronizes, SLIPE interrupt is sent to the interrupt queue. Note that this is the error reporting mechanism during automatic data forwarding (ATM-to-TDM bridging). Reserved, should be cleared during initialization. CAS block size.This field contains the number divided by two (N/2) of signaling nibbles mapped to this ATM channel. See Section 32.4.7, “Mapping VC Signaling to CAS Blocks.” Note that if the number of signaling nibbles is odd , this field should be programmed to (N+1)/2. See Section 32.2.2, “Signaling Path.” Example: ESF with three T1 time slots connected to one ATM channel. The Data_Size = 3*24 = 72 octets and the CAS Block= 2 octets (N=3, (N+1)/2 = 2), so in this case the Block_Size = 72+2 = 74 8 RXBM 9 SLIPIM 10–11 12–15 — CASBS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-31 ATM AAL1 Circuit Emulation Service 32.9.2 Transmit Connection Table (TCT) Figure 32-23 shows the format of an TCT entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1a Offset + 0x1C Offset + 0x1E — GBL BO — DTB BIB — — ATT AVCF VCON INTQ AAL Tx Data Buffer Pointer (TXDBPTR) TBDCNT TBD_OFFSET Rate Remainder PCR Protocol Specific. Refer to Section 32.9.2.1, “AAL1 CES Protocol-Specific TCT.” PCR Fraction APC Linked Channel ATM Cell Header (VPI,VCI,PTI,CLP) — PMT TBD_BASE TBD_BASE BNM STPT IMK PM Figure 32-23. Transmit Connection Table (TCT) Entry Table 32-7 describes general TCT fields. Table 32-7. TCT Field Descriptions Offset 0x00 Bits 0–1 2 3–4 Name — GBL BO Description Reserved, should be cleared during initialization. Global. Asserting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. Byte ordering. This field is used for data buffers. 00 Reserved. 01 Power PC little endian. 1x Big endian. Reserved, should be cleared during initialization. Data buffer and CES transmit cell scratchpad bus placement 0 Reside on the 60x bus. 1 Reside on the local bus. Note: TCT[DTB] programming must be consistent across all CES transmit channels because they share the same TCELL_TMP_BASE_EXT parameter. BD and interrupt queue bus 0 Reside on the 60xbus. 1 Reside on the local bus. Note: When using AAL5, AAL1 or AAL1 CES in UDC mode, BDs and data should be placed on the same bus (TCT[DTB]=TCT[BIB]). Reserved, should be cleared during initialization. 5 6 — DTB 7 BIB 8–9 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-32 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-7. TCT Field Descriptions (continued) Offset Bits 10–11 Name ATT Description ATM traffic type 00 Peak cell-rate pacing. The host must initialize PCR and the PCR fraction. Other traffic parameters are not used. 01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a continuous-state leaky bucket algorithm (GCRA) to pace the channel-sustain cell rate. The host must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst tolerance). 10 Peak and minimum cell rate pacing (UBR+ traffic). The host must initialize PCR, PCR fraction, MCR, MCR fraction, and MDA. 11 Reserved. Auto VC off. Determines APC behavior when the last buffer associated with this VC has been sent and no more buffers are in the VC’s TxBD table, 0 The APC does not remove this VC from the schedule table and continues to schedule it to transmit. 1 The APC removes this VC from the schedule table. To continue transmission after the host adds buffers for transmission, a new ATM TRANSMIT command is needed, which can be issued only after the CP clears the VCON bit. (Bit 13) Virtual channel is on Should be set by the host before it issues an ATM TRANSMIT command. When the host sets TCT[STPS] (stop transmit), the CP deactivates this channel and clears VCON when the channel is next encountered in the APC scheduling table. The host can issue another ATM TRANSMIT command only after the CP clears VCON. Points to one of four interrupt queues available. Reserved, should be cleared during initialization. AAL type 000 AAL0 —Reassembly with no adaptation layer 001 AAL1 —ATM adaptation layer 1 010 AAL5 —ATM adaptation layer 5. 100 AAL2 —ATM adaptation layer 2. Refer to Chapter 33, “ATM AAL2.” 101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service All others reserved. Tx data buffer pointer. Holds the real address of the current position in the Tx buffer. Transmit BD count. Counts the remaining data to transmit in the current transmit buffer. Its initial value is loaded from the data length field of the TxBD when a new buffer is open; its value is subtracted for any transmitted cell associated with this channel. Transmit BD offset. Holds offset from TBD_BASE of the current BD. Initialize to 0. Rate remainder. Used by the APC to hold the rate remainder after adding the pace fraction to the additive channel rate. Initialize to 0. 12 AVCF 13 VCON 14–15 0x02 0–12 13–15 INTQ — AAL 0x04 0x08 — — TxDBPTR TBDCNT 0x0A 0x0C — 0–7 8–15 TBD_Offset Rate Reminder PCR Fraction Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256 slot. If this is an ABR channel, this field is automatically updated by the CP. PCR Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel according to the traffic contract. Note that for an ABR channel, the CP automatically updates PCR to the ACR value. Protocol-specific APC linked channel. Used by the CP. Initialize to 0 (null pointer). ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The transmitter appends ATMCH to the cell payload during transmission. 0x0E — 0x10 0x16 0x18 — — — — APCLC ATMCH MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-33 ATM AAL1 Circuit Emulation Service Table 32-7. TCT Field Descriptions (continued) Offset 0x1C Bits 0–1 2–7 Name — PMT Description Reserved, should be cleared during initialization. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT × 32. Can be changed on-the-fly. TxBD base. Points to the first BD in the channel’s TxBD table. The 8 most-significant bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four least-significant bits of the address are taken as zero. Buffer-not-ready interrupt mask. Can be changed on-the-fly. 0 The transmit buffer-not-ready event of this channel is masked. (TBNR event is not sent to the interrupt queue.) 1 The buffer-not-ready event of this channel is enabled. Stop transmit. Initialize to 0. When the host sets this bit, the CP deactivates this channel and clears TCT[VCON] when the channel is next encountered in the APC scheduling table. Note that for AAL5 if STPT is set and frame transmission is already started (TCT[INF]=1), an abort indication will be sent (last cell with zero length field). Interrupt mask. Can be changed on-the-fly. 0 The transmit buffer event of this channel is masked. (TXB event is not sent to the interrupt queue.) 1 The transmit buffer event of this channel is enabled. Performance monitoring. Can be changed on-the-fly. 0 No performance monitoring for this VC. 1 Performance is monitored for this VC. When a cell is sent for this VC, the performance monitoring table indicated in PMT field is updated. 8–15 0x1E 0–11 12 TBD_BASE BNM 13 STPT 14 IMK 15 PM 32.9.2.1 AAL1 CES Protocol-Specific TCT Figure 32-24 shows the AAL1 CES protocol-specific transmission connection tables (TCT). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x10 Offset + 0x12 Offset + 0x14 — SRTS_DEV Valid Octet Size (VOS) PFM SRT SPIF STF — SN Block Size Structured Pointer (SP) ICASB/SRTS_TMP Figure 32-24. AAL1 CES Protocol-Specific TCT Table 32-8 describes AAL1 CES protocol-specific TCT fields. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-34 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-8. AAL1 CES Protocol-Specific TCT Field Descriptions Offset 0x10 Bits 0–1 2–7 Name — VOS Description Reserved, should be cleared during initialization. Valid octet size. Partially filled cell mode only. Specifies the number of valid octets from the beginning of the AAL1 user data field. For unstructured service, values 1-47 are valid; for structured service, values 1-46 are valid. Partially filled mode. 0 Partially filled cells mode is not used. 1 Partially filled cells mode is used. The transmitter copies only valid octets from the buffer to the AAL1 cell. The size of the valid octets from the beginning of the AAL1 user data field is specified in the VOS (valid octet size) field. Synchronous residual time stamp. Unstructured format only. The MPC8280 supports SRTS generation using external logic. If this mode is enabled, the MPC8280 reads the SRTS from external logic and inserts it into four cells for which SN = 1, 3, 5, or 7. The MPC8280 reads the new SRTS from external logic every eight cells. (See Section , “.”) 0 SRTS mode is not used. 1 SRTS mode is used. Structured pointer inserted flag. Indicates that a structured pointer has been inserted in the current cycle. The user should initialize this field to zero. Used by the CP only. Structured format. 0 Unstructured format is used. 1 Structured format is used. Note that although the structured format may be used, if the block size is one, the user should clear STF so that only non P-format AAL1 cells are generated. Reserved, should be cleared during initialization. Sequence number field. Used by the CP to check the incoming cells SN. Initialize to 0. Used to select a SRTS device. The SRTS device address is SRTS_BASE[0–27]+SRTS_DEV[28:31]. SRTS_BASE is taken from the parameter RAM and is 16-byte aligned. Used only in structured format. Specifies the structured block size (Block Size = 0xFFF = 4 Kbytes maximum). Note that when working in CAS mode (CESM=1 and CASM=1), the block size should be programmed to the superframe block size plus the size of the CAS block. However, when working in basic mode (CES without CAS: CESM=1 and CASM=0) the block size should be programmed to the number of MCC slots (Nx64) per frame assigned to this channel. 8 PFM 9 SRT 10 11 SPIF STF 12 13–15 0x12 0–3 — SN SRTS_DEV 4–15 Block Size 0x14 0–3 ICASB/SRTS ICASB applies when in CAS mode. Incoming CAS Block. Points to one of the eight _TMP available internal CAS block. The starting address of the table is IN_CAS_BLOCK_BASE+ICASB × 32. See Section 32.4.7.1, “CAS Routing Table” for more details. Note that the RCT and TCT use the same CAS routing table (CRT). SRTS_TMP applies when not in CAS mode. Before a cell with SN = 1 is sent, the CP reads the SRTS code from external SRTS logic, writes it to SRTS_TMP, and then inserts SRTS_TMP into the next four cells with an odd SN. 4–15 SP Structured pointer. Used by the CP to calculate the structured pointer. Initialize to 0. Structured format only. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-35 ATM AAL1 Circuit Emulation Service 32.10 Outgoing CAS Status Register (OCASSR) Figure 32-25 shows the layout of the outgoing CAS block status register (OCASSR). 0 7 8 9 10 11 12 13 14 15 Field — MCASB7 MCASB6 MCASB5 MCASB4 MCASB3 MCASB2 MCASB1 MCASB0 Figure 32-25. Outgoing CAS Status Register (OCASSR) This status register contains sticky bits that give the software application an indication that the CP has modified the associated CAS block. When the ATM receiver operates in core CAS modify mode RCT[CCASM=1], the CP generates an interrupt and sets the appropriate sticky bit in OCASSR each time an AAL1 cell is received with new signaling information (one or more signaling nibble has changed). Note that this flag bit stays set until it is cleared by software. If new signaling is received and the relevant sticky bit is already set, the CP updates the CAS block without generating another interrupt. Table 32-9 describes OCASSR fields. Table 32-9. OCASSR Field Descriptions Bits 0–7 Name — Description Reserved, should be cleared during initialization. Modify CAS Block n. When the CP updates this outgoing CAS block, it sets the MCASBn sticky bit and generates an interrupt to notify the core that the signaling information has changed in block n. Each channel selects the CAS block number in its RCT; see Section 32.9.1.1, “AAL1 CES Protocol-Specific RCT.” 8, 9, MCASBn 10, 11, 12, 13, 14, 15 32.11 Buffer Descriptors The AAL1 CES controller operates as a multi-channel protocol, performing simultaneous segmenting and reassembling of transmit and receive data, to and from different sets of memory buffers for all channels. This behavior makes it necessary to have a separate list of BDs for each channel. Each channel is configured with two BD lists: one for transmit and the other for receive operations. The amount of BDs’ in the table is defined by the user. The BD table is a circular list, the last BD in the table holds a wrap indication. When the MPC8280 reaches the last BD, it returns to the head of the list. Each BD in the TxBD table points to a buffer to send. At the receive side, the user allocates dedicated buffers to each channel (that is, one BD for each buffer). When the receiver or transmitter completes writing or reading the buffer, it moves to the next buffer in the list and optionally issues an interrupt. 32.11.1 Transmit Buffer Operation The user prepares a table of BDs pointing to the buffers to be sent. The address of the first BD is put in the channel’s TCT[TBD_BASE]. The transmit process starts when the core issues an atm transmit command. The CP reads the first TxBD in the table and sends its associated buffer. When the current buffer is finished, the CP increments TBD_OFFSET, which holds the offset from TBD_BASE to the current BD. It then reads the next BD in the table. If the BD is ready (TxBD[R] = 1), the CP continues sending. If the MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-36 Freescale Semiconductor ATM AAL1 Circuit Emulation Service current BD is not ready, the CP polls the ready bit at the channel rate unless TCT[AVCF] = 1, in which case the CP removes the channel from the APC and clears TCT[VCON]. The core must issue a new atm transmit command to restart transmission. Note that when the ATM transmitter is in CES mode, the buffer-not-ready state is ignored by the ATM controller; see Section 32.4.1.2, “TDM-to-ATM.” BD memory space Tx BD table of ch 1 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 Data memory space Pointers from ch 1 entry of TCT TBD_Base Tx buffer 1 of channel 1 Tx buffer 3 of channel 1 TBD_Offset • • • Tx buffer 4 of channel 1 Tx buffer 1 of channel 4 Tx buffer 2 of channel 1 TBD_Base Pointers from ch 4 entry of TCT Tx BD table of ch 4 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 TxBD 7 TxBD 8 TxBD 9 • • • Tx buffer 2 of channel 4 Tx buffer 3 of channel 4 Tx buffer 8 of channel 4 TBD_Offset Figure 32-26. Transmit Buffers and BD Table Example 32.11.2 Receive Buffer Operation The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts filling its associated buffer with received data. When the current buffer is full, the CP increments RBD_OFFSET, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table. If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition has occurred and the ATM receiver optionally issues an interrupt to the event queue. Note that when the ATM receiver is in CES mode, the buffer-not-ready (busy) state is handled by an automatic slip control mechanism; see Section 32.5, “ATM-to-TDM Adaptive Slip Control.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-37 ATM AAL1 Circuit Emulation Service BD memory space Rx BD table of ch 1 RxBD 1 RxBD 2 RxBD 3 RxBD 4 RxBD 5 RxBD 6 Data memory space Pointers from ch 1 entry of RCT RBD_Base Rx buffer 1 of channel 1 Rx buffer 3 of channel 1 RBD_Offset • • • Rx buffer 4 of channel 1 Rx buffer 1 of channel 4 Rx buffer 2 of channel 1 RBD_Base Pointers from ch 4 entry of RCT Rx BD table of ch 4 RxBD 1 RxBD 2 RxBD 3 RxBD 4 RxBD 5 RxBD 6 RxBD 7 RxBD 8 RxBD 9 • • • Rx buffer 2 of channel 4 Rx buffer 3 of channel 4 Rx buffer 8 of channel 4 RBD_Offset Figure 32-27. Receive Buffers and BD Table Example 32.12 ATM Controller Buffers Table 32-10 describes properties of the ATM receive and transmit buffers. Table 32-10. Receive and Transmit Buffers Receive AAL Size AAL5 Alignment Size Alignment No requirement No requirement Transmit Multiple of 48 octets (except last buffer in frame) Double word aligned Any Double word aligned At least 44 octets No requirement AAL3/4 At least 44 octets (except last buffer in frame) AAL1/ AAL1 CES AAL0 Multiple of 8 octets Multiple of 8 octets No requirement 52-64 octets. Burst-aligned 52–64 octets. No requirement MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-38 Freescale Semiconductor ATM AAL1 Circuit Emulation Service 32.12.1 AAL1 CES RxBD Figure 32-28 shows the AAL1 CES RxBD. 0 1 2 3 4 5 6 7 8 9 10 11 15 Offset + 0x00 Offset + 0x02 Offset + 0x06 Offset + 0x08 E — W I — — CM — — EOSF — Data Length Rx Data Buffer Pointer Figure 32-28. AAL1 CES RxBD Table 32-11 describes AAL1 CES RxBD fields. Table 32-11. AAL1 CES RxBD Field Descriptions Offset 0x00 Bits 0 Name E Description Empty. 0 The buffer associated with this RxBD is filled with received data or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP cannot use this BD again while E = 0. 1 The buffer is not full. This RxBD and its associated receive buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD. — Wrap (final BD in table) 0 This is not the last BD in the RxBD table of the current channel. 1 This is the last BD in the RxBD table of this current channel. After this buffer is used, the CP receives incoming data into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table overall space is constrained to 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been used. 1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this buffer. FCCE[GINTx] is set when the INT_CNT reaches the global interrupt threshold. — Continuous mode 0 Normal operation. 1 The empty bit (RxBD[E]) is not cleared by the CP after this BD is closed, allowing the associated buffer to be overwritten automatically when the CP next accesses this BD. — End of super frame. CES mode (RCT[CESM=1]) only. 0 No signaling information should be inserted after closing this buffer. 1 When closing this buffer, the ATM receiver unpacks the CAS information from the incoming AAL1 cells and stores it in the internal CAS block. Note that this bit should be set by the user at the end of each super-frame in the common (MCC, ATM) BD table. See Section 32.4.6, “Channel Associated Signaling (CAS) Support.” — 1 2 — W 3 I 4-5 6 — CM 7-8 9 — EOSF 10-15 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-39 ATM AAL1 Circuit Emulation Service Table 32-11. AAL1 CES RxBD Field Descriptions Offset 0x02 0x04 Bits — — Name DL Description Data length. The number of octets the CP writes into the buffer once its BD is closed. RXDBPTR Rx data buffer pointer. Points to the first location of the associated buffer; may reside in either internal or external memory. This pointer must be burst-aligned. 32.12.2 AAL1 CES TxBDs Figure 32-29 shows the AAL1 CES TxBD. 0 1 2 3 4 5 6 7 8 9 10 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R — W I — CM — EOSF — Data Length (DL) Tx Data Buffer Pointer (TXDBPTR) Figure 32-29. AAL1 CES TxBD Table 32-12 describes AAL1 CES TxBD fields. Table 32-12. AAL1 CES TxBD Field Descriptions Offset 0x00 Bits 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears this bit after the buffer has been sent or after an error condition is encountered. 1 The buffer prepared for transmission by the user has not been sent or is being sent. No fields of this BD may be written by the user once R is set. — Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from the first BD in the table (the BD pointed to by the channel’s TCT[TBD_BASE]). The number of TxBDs in this table is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx buffer event is sent to the interrupt queue after this buffer is serviced. FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold. — Continuous mode 0 Normal operation. 1 The CP does not clear the ready bit after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. — 1 2 — W 3 I 4–5 6 — CM 7–8 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-40 Freescale Semiconductor ATM AAL1 Circuit Emulation Service Table 32-12. AAL1 CES TxBD Field Descriptions (continued) Offset Bits 9 Name EOSF Description End of super frame. CES mode (TCT[CESM=1]) only. 0 No signaling information should be inserted after closing this buffer. 1 When closing this buffer the ATM transmitter fetches the CAS information from the internal CAS block and packs it to the outgoing AAL1 cells. Note that this bit should be set by the user at the end of each super-frame in the common (MCC, ATM) BD table. See Section 32.4.6, “Channel Associated Signaling (CAS) Support.” — The number of octets the ATM controller should transmit from this BD’s buffer. It is not modified by the CP. The value of DL should be greater than zero. 10–15 0x02 0x04 — — — DL TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may reside in either internal or external memory. This value is not modified by the CP. 32.13 AAL1 CES Exceptions There are four circular interrupt queues available for each channel. The interrupt queue number is programmed in RCT[INTQ] and TCT[INTQ]. Events can be masked by clearing interrupt mask bits in the RCT and TCT. When one of the AAL1 channels generates an interrupt request, the CP writes a new entry to the table consisting of the channel’s number and a description of the exception. The valid (V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches the entry in which W is set, it returns to the first entry of the queue. Each one-word entry provides detailed interrupt information to the host. More details can be found in Section 29.11, “ATM Exceptions.” 32.13.1 AAL1 CES Interrupt Queue Entry The figure below shows an interrupt queue entry. 0 1 2 3 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 V — W — SLIPE SLIPS CASUP TBNR RXF BSY TXB RXB Channel Code (CC) Figure 32-30. AAL1 CES Interrupt Queue Entry The table below describes interrupt queue entry fields. Table 32-13. AAL1 CES Interrupt Queue Entry Field Descriptions Offset 0x00 Bits 0 Name V Description Valid interrupt entry 0 This interrupt queue entry is free and can be use by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. — 1 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-41 ATM AAL1 Circuit Emulation Service Table 32-13. AAL1 CES Interrupt Queue Entry Field Descriptions (continued) Offset Bits 2 3–7 8 Name W — SLIPE Description Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. — Slip End.Set when an AAL1 channel exits a slip state (the channel’s adaptive counter reaches the ATM_Start threshold and the ATM channel regains its SYNC). At this point the receiver starts to receive the incoming cells. See Section 32.6, “3-Step-SN Algorithm.” Note that this interrupt can be masked with RCT[SLIPIM=0]. See Section 32.9.1, “Receive Connection Table (RCT).” This interrupt has an associated channel code. Slip Start.Set when an AAL1 channel enters a slip state (the channel’s adaptive counter reaches the ATM_Stop threshold or the ATM channel loses its SYNC). At this point the receiver drops incoming cells until the adaptive counter reaches the ATM_Start threshold and the channel is resynchronized. See Section 32.6, “3-Step-SN Algorithm.” Note that this interrupt can be masked with RCT[SLIPIM=0]. See Section 32.9.1, “Receive Connection Table (RCT).” This interrupt has an associated channel code. CAS Update Interrupt. Set when one of the eight outgoing CAS blocks is updated by the CP. New signaling information has been received within the received AAL1 cells. Note that this interrupt available in CES mode and when RCT[CCASM=1] mode. This interrupt has an associated channel code. Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent only if TCT[BNM] = 1. This interrupt has an associated channel code. Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case, an abort frame transmission is sent (last cell with length=0), the channel is taken out of the APC, and the TCT[VCON] flag is cleared. Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt has an associated channel code. Busy condition. The BD table or the free buffer pool associated with this channel is busy. Cells were discarded due to this condition. This interrupt has an associated channel code. Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code. Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code. Channel code specifies the channel associated with this interrupt. 9 SLIPS 10 CASUP 11 TBNR 12 RXF 13 BSY 14 15 TXB RXB 0x02 — CC 32.14 AAL1 Sequence Number (SN) Protection Table The 32-byte sequence number protection table, pointed to by AAL1_SNPT_BASE in the ATM parameter RAM, resides in dual-port RAM and is used for AAL1 only. The table should be initialized according to Figure 32-31. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-42 Freescale Semiconductor ATM AAL1 Circuit Emulation Service 0 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E 0x0000 0x0007 0x000D 0x000A 0x000E 0x0009 0x0003 0x0004 0x000B 0x000C 0x0006 0x0001 0x0005 0x0002 0x0008 0x000F Figure 32-31. AAL1 Sequence Number (SN) Protection Table 32.15 Internal AAL1 CES Statistics Tables An AAL1 CES statistics table, shown in Table 32-14, resides in the dual-port RAM and holds AAL1 CES statistics on a per-VC basis. AAL1_Int_STATT_BASE points to the base address of these tables. Each AAL1 channel has its own table with a starting address given by AAL1_Int_STATT_BASE + ATM_CHANNEL# × 8. Table 32-14. AAL1 CES DPR Statistics Table Offset 0x00 0x02 Name Rx_AAL1_VALID Rx_AAL1_BOV Width Hword Hword Description 16-bit cyclic counter. Counts the total received AAL1 cells delivered to the receive buffers. This counter includes the tag cells (with SCE, SNE). 16-bit cyclic counter. Counts the number of ATM buffer-pre overrun events i.e the ATM write pointer reaches the ATM_STOP threshold.See Section 32.5, “ATM-to-TDM Adaptive Slip Control.” 16-bit cyclic counter. Counts the transmitted AAL1 cells. 16-bit cyclic counter. Counts the number of ATM buffer underrun events. See Section 32.4.1.2, “TDM-to-ATM.” 0x04 0x06 Tx_AAL1_VALID Tx_AAL1_BUN Hword Hword MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-43 ATM AAL1 Circuit Emulation Service 32.16 External AAL1 CES Statistics Tables An AAL1 CES statistics table, shown in Table 32-15, resides in the external memory and holds AAL1 CES statistics on a per-VC basis. AAL1_Ext_STATT_BASE points to the base address of these tables. Each AAL1 channel has its own table with a starting address given by AAL1_Ext_STATT_BASE + ATM_CHANNEL# × 16. Table 32-15. AAL1 CES External Statistics Table O ffset 0x00 0x02 0x04 Name Rx_AAL1_LOST Rx_AAL1_MISS Rx_AAL1_SCE Width Hword Hword Hword Description 16-bit cyclic counter. Counts the number of AAL1 lost cells events. See Section 32.6, “3-Step-SN Algorithm.” 16-bit cyclic counter. Counts the number of AAL1 misinserted events. See Section 32.6, “3-Step-SN Algorithm.” 16-bit cyclic counter. Counts the number of AAL1 sequence errors i.e the expected SC is not match with the received one (ESC!= RSC). See Section 32.6, “3-Step-SN Algorithm.” 16-bit cyclic counter. Counts the number of ATM cell that received with SNP error. (AAL1 PDU Header Error) 16-bit cyclic counter. Counts the number of structured pointer error events (i.e parity error, Tag cell or pointer mismatch). See Section 32.7, “Pointer Verification Mechanism.” 16-bit cyclic counter. Counts the number of AAL1 resynchronized events: pointer reframes, slip events, two consecutive cells with errors (SNE, SCE, Tag…), and two consecutive pointers with errors (parity error or pointer mismatch). Reserved, should be cleared during initialization. 0x06 0x08 Rx_SNP_Error Rx_AAL1_SPE Hword Hword 0x0A Rx_ReSYNC Hword 0x0C– 0x0E — Word Note that both the internal and the external statistics tables should be cleared by the user. 32.17 CES-Specific Additions to the MCC Additions to the MCC global parameter RAM and modifications to the channel-specific CHAMR and INTMASK registers have been implemented to support CES operation. Refer to Section 29.3.3, “MCC Parameters for AAL1 CES Usage,” Section 29.3.3.1.1, “Interrupt Circular Table Entry and Interrupt Mask (INTMSK) —AAL1 CES,” and Section 29.3.1.3, “Channel Mode Register (CHAMR)—HDLC Mode,” for more information. 32.18 Application Considerations • • • The buffer size (MCC [MRBLR]) must be a multiple of 8 octets. The CAS buffer operates in continuous mode with newer signaling information continuously overwriting older signaling. The CES application does not use super-frame synchronization for the data flow in ATM-to-TDM and TDM-to-ATM interworking. However, for the signaling flow, the MPC8280 uses the super-frame sync signal to know when to supply the signaling information to the external framer. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-44 Freescale Semiconductor ATM AAL1 Circuit Emulation Service • • • The external framer then places the signaling information at the appropriate position in the super frame. See Section 32.4.6, “Channel Associated Signaling (CAS) Support.” Simple external logic is needed to synchronize the MCC-to-framer serial connection. When going from TDM-to-ATM, the CAS information should be read by the MCC on the 24th frame of a super frame. The adaptive rate FIFO method can be implemented by the core by calculating the difference between the ATM and MCC pointers. When going from TDM-to-ATM, the ATM channel should be programmed to work at a higher rate than the MCC super-channel rate. We expect that the jitter caused by the APC traffic reshaping will depend on the ATM channel rate (PCR, PCR_FRACTION). Figure 32-32 illustrates this timing issue. See also Section 32.4.1.2, “TDM-to-ATM.” MCC timing: BDs are ready to be transmitted at the rate shown below. ATM timing: The optimal ATM channel rate would match the MCC super channel rate exactly. ATM timing (adjusted to higher rate): If PCR and PCR_FACTION cannot provide the exact MCC super channel rate, the ATM channel should be programmed to a higher rate to avoid the MCC buffer-not-ready state. It is recommended that the ATM rate be double that of the MCC. Extra request at the higher rate to compensate for jitter. Note that some of the extra requests will not be needed (buffer-not-ready) and will be ignored by the ATM controller. Figure 32-32. TDM-to-ATM Timing Issue MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 32-45 ATM AAL1 Circuit Emulation Service MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 32-46 Freescale Semiconductor Chapter 33 ATM AAL2 NOTE The functionality described in this chapter is not available on the MPC8270. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. The microcode implementation of the ATM adaptation layer type 2 (AAL2) on the MPC8280 is compliant with the ITU-T recommendations I.363.2 and I.366.1. This chapter describes the functionality and data structures of AAL2 CPS, CPS switching, and SSSAR and should be used as a supplement to Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5.” 33.1 Introduction AAL2 enables the multiplexing of voice and data channels over a single ATM VC. The channels consist of packets transported within individual ATM cells (see Figure 33-1). Packet lengths are allowed to vary in order to accommodate bandwidth fluctuations of the individual channels. Each packet has a channel identifier (CID) so that each AAL2 user (channel) is uniquely identified by the triplet VP | VC | CID. SSSAR SDU SSSAR PDU PH PP PH CPS PDU STF PH PP ATM cell ATM header STF PH PP PH PP Padding PH PP Padding PP SSSAR CPS ATM Figure 33-1. AAL2 Data Units MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-1 ATM AAL2 AAL2 is subdivided into two sublayers, as shown in Figure 33-2: • Common part sublayer (CPS)—In the CPS sublayer, variable length packets coming from multiple users are assembled into CPS-PDUs belonging to a single ATM VC. • Service-specific convergence sublayer (SSCS)—The SSCS sublayer handles the mapping of user data to the CPS sublayer. The SSCS segments large data frames into smaller CPS packets and also provides different services to the user, such as transmission error detection. The SSCS sublayer is further divided into three service-specific layers: — Service-specific segmentation and reassembly sublayer (SSSAR) — Service-specific transmission error detection sublayer (SSTED) — Service-specific assured data transfer sublayer (SSADT) User User User User SAP SSADT Service specific assured data transfer SAP SSTED SSCS AAL2 SSSAR Service specific transmission error detection SAP Service specific segmentation & reassembly SAP Common part sublayer (SAP): Service access point CPS CPS Figure 33-2. AAL2 Sublayer Structure The AAL2 microcode implements the CPS and SSSAR sublayers. (The SSADT and SSTED sublayers are not implemented.) As shown in Figure 33-2, the user can access the CPS sublayer directly or through the SSSAR sublayer. The SSSAR sublayer is used mainly for transferring large data frames. The AAL2 microcode also enables switching from one PHY | VP | VC | CID combination to another; an example is shown in Figure 33-3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-2 Freescale Semiconductor ATM AAL2 UTOPIA PHY4 VP=5|VC=20|CID=13 X VP=27|VC=3|CID=212 UTOPIA PHY7 Figure 33-3. AAL2 Switching Example 33.2 Features The MPC8280’s AAL2 features are as follows: • Fully complies with ITU-T I.363.2 (09/97 and 11/00) and ITU-T I.366.1 (06/98) specifications. • Number of AAL2 external channels supported is subject to internal memory constraints — Each external channel requires space for one Transmit Queue Descriptor in internal memory. Typically, up to 1000 external channels can be supported. • Supports CBR, VBR and UBR+ traffic types — PCR pacing (with optional Timer_CU) — VBR pacing (with optional Timer_CU) — UBR+ pacing (no Timer_CU support) • Priority mechanism for transmitting per VC. The priority mechanism provides for TX queues having equal or differing priorities. The SSSAR TX queues can be prioritized flexibly among the CPS TX queues. • Timer_CU support • NoSTF mode support • Support for partially filled cells • User-defined cells (as described in Section 31.7, “User-Defined Cells (UDC)”). • Interrupt indications include the ATM channel number, the CID, and the event type. The events reported are TX buffer not ready, TX buffer transmitted, RX buffer not ready, RX buffer, RX SSSAR frame, and RX AAL2 error events. • CPS switching — Switching from a receive PHY1 | VP1 | VC1 | CID1 combination to another transmit PHY2 | VP2 | VC2 | CID2 combination — Partial packet discard support — For each switched queue, a counter for the total number of packets in the queue is available. • CPS Receiver — Segmentation of CPS PDU directly to external memory queues MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-3 ATM AAL2 • • • — A separate queue for every VP | VC | CID or a common queue for multiple VP | VC | CID combinations — Receive one or multiple VP | VC | CIDs directly to a specific TX queue to enable switching — Sequence number (SN) protection check for CPS-PDU — CRC5 (HEC) check to detect errors in the CPS-PH of the CPS-Packet — OSF (offset field) of the STF (start of frame) check (a valid value is less than 48) — An SDU length limit parameter (Max_SDU_Deliver_Length) per ATM VC — Odd parity check for the STF octet of the CPS-PDU CPS Transmitter — Reassemble CPS PDU directly from external memory — Perform CPS-PDU padding as needed — Insert Sequence Number bit of the CPS-PDU — Parity bit is calculated to provide odd parity over the STF octet — Calculation of CRC-5 on the first 19 bits of the CPS-PH — UUI field in the CPS-Packet header is programmed according to the value of the CPS_UUI parameter (per packet) — A free running counter (per TX Queue) is decremented for each packet sent. SSSAR Receiver — Reassemble CPS packets from the same CID into an SSSAR SDU — A separate queue for every PHY | VP | VC | CID — Perform all the above mentioned CPS receiver functions — A Ras_Timer mode is provided. When the Ras_Timer expires the buffer is closed with a timer expired error. The next packet received starts a new SSSAR SDU in a new buffer. — The SDU length is checked. If the frame exceeds the length limit (SSSAR_Max_SDU_Length), the receiver discards the rest of the packets from the current frame, closes the buffer and reports a Max_SDU violation error in the BD. The next packet received starts a new SSSAR SDU in a new buffer. — Partial Packet Discard. If no buffer is available when a packet arrives, the receiver enters a frame hunt state and discards each incoming packet from the current frame. — The UUI field is stored for the host into the RxBD after receiving the whole SSSAR frame. SSSAR Transmitter — Segmentation of SSSAR SDUs from SSSAR TX queue into CPS packets — An SSSAR TX queue may contain several CIDs — Performs all the above mentioned CPS transmitter functions — A programmable segment length (Seg_Len) is copied from the SSSAR SDU into the CPS packet payload, except for when at the end of the frame or buffer. — UUI mode available. When UUI mode is enabled, the SSSAR UUI is copied from the byte following the last byte of the frame. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-4 Freescale Semiconductor ATM AAL2 33.3 AAL2 Transmitter The following sections describe the AAL2 transmitter. 33.3.1 Transmitter Overview A transmitter cycle starts when the APC schedules an ATM channel number for transmission. The TCT is fetched and the AAL type of the channel is checked. For AAL2 cells, the transmitter first handles uncompleted packets from the previous cell of the current CID (partial and split cases) by filling the beginning of the cell with the remainder of the last packet. Then, the transmitter performs the priority mechanism (see Section 33.3.2, “Transmit Priority Mechanism”) in order to fill the cell with new packets. The priority mechanism determines the order in which the TX queues are serviced. The transmitter continues to search for ready packets in the TX Queues until either the cell is successfully filled with packets, or no more packets are ready but the cell is not yet completed. In the first case the cell is simply sent. In the latter case, the optional Timer_CU (described in Section 33.3.5.1, “AAL2 Protocol-Specific TCT”) is examined. If the Timer_CU has expired, the uncompleted cell is padded with zeros and sent; otherwise, the cell is temporarily stored in external memory for the CP to attempt to complete it the next time the channel is scheduled. The TX queues are the data structures that store the CPS packets and SSSAR frames. Each TX queue can contain different CIDs. Each TX queue is maintained by a Tx queue descriptor (TxQD) that holds the queue pointer and parameters to manage the queue. When the transmitter fetches a packet out of an SSSAR TX Queue, it usually takes out of the SSSAR buffer a number of octets equal to TxQD[Seg_Len] (see Section 33.3.5.4, “SSSAR Tx Queue Descriptor). The channel CID is taken from the BD of the first buffer of the SSSAR frame (see Section 33.3.5.5, “SSSAR Transmit Buffer Descriptor”). A CPS UUI = 27 is used for all the in-frame packets until the last packet from the SSSAR frame is sent. The last packet can optionally contain a per frame, user-defined UUI. After an SSSAR buffer is completely sent, an optional interrupt event is issued to the host. Also, if an SSSAR TX queue is empty an optional interrupt event is issued to the host. In case of CPS TX Queue, the transmitter fetches the packet header out of a buffer descriptor and the packet payload out of a CPS buffer (see Section 33.3.5.3, “CPS Buffer Structure”). The HEC in the packet header is calculated by the CP or taken from the buffer descriptor based on the user configuration. After a CPS packet is sent, an optional interrupt event is issued to the host. Also, if the CPS TX queue is empty an optional interrupt event is issued to the host. The optional partial filled mode (see Section 33.3.3, “Partial Fill Mode (PFM)”) limits the number of data octets per cell. This can be used to ensure that a cell does not contain a split packet or to limit transmission to one packet per TX cell by setting a low partial fill threshold (PFT). The no-STF (no start of frame) mode (see Section 33.3.4, “No STF Mode”) enables the transmission of cells that do not include the STF byte, thus allowing for 48-byte packets. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-5 ATM AAL2 33.3.2 Transmit Priority Mechanism The transmit priority mechanism operates in two modes: • Round robin (TCT[Fix]=0) • Fixed priority (TCT[Fix]=1) The following sections describe the priority options. 33.3.2.1 Round Robin Priority In round robin priority mode, the Tx queues all have equal priority. The transmitter starts with the TxQD pointed to by TCT[FirstQueue], as shown in Figure 33-4. The number of packets that the transmitter services from each queue is determined by the one-packet bit (TCT[OneP]). If TCT[OneP]=0, the transmitter tries to process as many packets in the queue as needed to fill up the cell. Only when the queue is empty does the transmitter move on to the next queue (assuming the cell is not completed). If TCT[OneP]=1, the transmitter attempts to take only one packet out of each queue. (Set TCT[OneP] for implementations where each queue contains only one CID.) TxQD TCT Fix=0 FirstQueue NextQueue TxQD NextQueue TxQD NextQueue Figure 33-4. Round Robin Priority The transmitter steps from one TxQD to the next along the queue links. The TCT[MaxStep] parameter limits the number of TX Queues that the transmitter visits during a cell time. If MaxStep is reached before the cell has been completely filled, one of the following events takes place: • TCT[ET]=0 (Timer CU disabled). The cell is padded with zeros and sent. • TCT[ET]=1 (Timer CU enabled). If the timer has not expired, the cell is not sent. (The transmitter attempts to fill the cell the next time this channel is scheduled.) If the timer has expired, the cell is padded with zeros and sent After the transmitter sends a cell, it saves the queue link of the last TxQD serviced in TCT[FirstQueue]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-6 Freescale Semiconductor ATM AAL2 33.3.2.2 Fixed Priority In fixed priority mode (TCT[Fix]=1), the transmitter, with each new cell, starts with searching the highest priority queue and then moves on to the lower priority queues. The TCT[FirstQueue] points to the highest priority queue, as shown in Figure 33-5, and remains unchanged by the CP. TxQD Highest priority queue TCT Fix=1 FirstQueue NextQueue TxQD NextQueue TxQD 0x0000 (null link) Lowest priority queue Figure 33-5. Fixed Priority Mode The TCT[OneP] determines the number of packets that the transmitter attempts to take from each queue (see the explanation in round robin mode). The NextQueue field of the lowest priority TxQD should be cleared (null link), and TCT[MaxStep] should be programmed to the total number of TX queues in the channel. When the transmitter reaches the null link and the cell is still not complete, the transmitter checks the TIMER CU mode as described above for the round robin mode. 33.3.3 Partial Fill Mode (PFM) The partial fill mode (TCT[PFM]=1) allows the user to specify a partial fill threshold (TCT[PFT]), which limits the number of data octets sent with each ATM cell. Partial fill mode assures that packets are not split over two cells, unless the first packet of the cell is greater than 47 bytes. In partial fill mode, the transmitter starts by filling the ATM cell with the first packet. After the first packet, the CP determines if including the next packet in the cell would exceed the PFT limit. If so, the second packet is not inserted into the current cell, the unused payload is padded with zeros, and the cell is sent. If the second packet does not exceed PFT, the CP inserts it into the CPS-PDU and moves on to the third packet, and so on. By programming PFT = 1, the partial fill mode can also serve to assure that only one packet is sent per cell. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-7 ATM AAL2 The following figures provide examples of partial fill mode operation: 1. Five packets fit exactly within the PFT limit Cell header STF AAL2 packet 1 AAL2 packet 2 AAL2 packet 3 AAL2 packet 4 AAL2 packet 5 Padding Transmit 0 PFT 2. Because PFT is less than the combined lengths of packet 1, packet 2 and packet 3, the ATM cell is sent only with packets 1 and 2. (Packet 3 will be sent with the next cell.) Cell header STF AAL2 packet 1 AAL2 packet 2 AAL2 packet 3 Empty 0 Cell header STF AAL2 packet 1 Remove packet 3 AAL2 packet 2 PFT Padding Transmit 0 PFT 3. Because the first packet exceeds the PFT value, the CPS-PDU consists only of this packet (and the unused octets are padded with zeros). Cell AAL2 header STF packet 1 Padding Transmit 0 PFT 33.3.4 No STF Mode The no-STF (no start of frame) mode enables the transmission of 48-byte packets by not including the STF byte in the CPS PDU. The no-STF mode should always be used with PFT programmed to 47 in order to prevent split and partial packets. For the AAL2 channels that use this mode, packets must not be larger than a maximum packet size of 48. The user activates this mode per ATM channel by doing the following: 1. Setting TCT[NoSTF]=1 and TCT[PFM]=1 2. Establishing a partial fill threshold by programming TCT[PFT]=47 The following figure shows a cell using no-STF mode: Cell header AAL2 packet of 48 bytes 0 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-8 Freescale Semiconductor ATM AAL2 33.3.5 AAL2 Tx Data Structures The following sections describe the transmit connection tables (TCT) and the structures in which CPS packets and SSSAR SDUs are stored in memory. 33.3.5.1 AAL2 Protocol-Specific TCT The transmit connection table (TCT) is a VC-level table and is where the AAL type for the ATM channel number is selected. The parameters related to the ATM channel number or to all the TX Queues of the ATM channel are maintained here. Figure 33-6 shows the AAL2-specific TCT. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1a Offset + 0x1C Offset + 0x1E — GBL BO — DTB BIB AVCF PFM — — ATT ET NoSTF VCON INTQ AAL — FirstQueue Rate Remainder PCR Timer_CU_period Timer_Period_Shadow — APC Linked Channel ATM Cell Header (VPI,VCI,PTI,CLP) PCR Fraction — — PMT PFT — MaxStep OneP STPT Fix PM Figure 33-6. AAL2 Protocol-Specific Transmit Connection Table (TCT) NOTE When the channel is active, the CP fetches the TCT (32 bytes) using burst cycle and writes back only the first (24 bytes). Table 33-1 describes the AAL2 TCT fields. Table 33-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions Offset 0x00 Bits 0–1 2 Name1 — GBL Description Reserved, should be cleared during initialization. Global. Setting GBL enables snooping of data buffers, BD, interrupt queues and free buffer pool. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-9 ATM AAL2 Table 33-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued) Offset Bits 3–4 Name1 BO Description Byte ordering. This field is used for data buffers. 00 Reserved. 01 Power PC little endian. 1x Big endian. Reserved, should be cleared during initialization. Data buffer bus selection. 0 Data buffers reside on the 60x bus. 1 Data buffers reside on the local bus. Bus selection for the BDs, interrupt queues and the free buffer pool. 0 Reside on the 60x bus. 1 Reside on the local bus. Auto VC off. Determines APC behavior when the last buffer associated with this VC has been sent and no more buffers are in the VC’s TxBD table, 0 The APC does not remove this VC from the schedule table and continues to schedule it to transmit. 1 The APC removes this VC from the schedule table. To continue transmission after the host adds buffers for transmission, a new ATM TRANSMIT command is needed, which can be issued only after the CP clears the VCON bit. (Bit 13) Partial fill mode. See Section 33.3.3, “Partial Fill Mode (PFM).” 0 Partially filled cells are not supported. 1 Partially filled cells are supported. ATM traffic type 00 Peak cell-rate pacing (regular traffic). The host must initialize PCR and PCR fraction. Other traffic parameters are not used. 01 Peak and sustain cell rate pacing (VBR traffic). The APC performs a continuous-state leaky bucket algorithm (GCRA) to pace the channel-sustain cell rate. The host must initialize PCR, PCR fraction, SCR, SCR fraction, and BT (burst tolerance). 10 Peak and Minimum cell rate pacing. The host must initialize PCR, PCR fraction, MCR, MCR fraction, and MDA. 11 Reserved. Enable Timer_CU. 0 Timer_CU operation in this channel is disabled. 1 Timer_CU operation in this channel is enabled. Virtual channel is on Should be set by the host before it issues an ATM TRANSMIT command. When the host sets the STPT (stop transmit) bit, the CP deactivates this channel and clears VCON. The host can issue another ATM TRANSMIT command only when the CP clears VCON. Points to one of the four interrupt queues available. 5 6 — DTB 7 BIB 8 AVCF 9 PFM 10–11 ATT 12 ET 13 VCON 14–15 INTQ MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-10 Freescale Semiconductor ATM AAL2 Table 33-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued) Offset 0x02 Bits 0–11 12 Name1 — NoSTF Description Reserved, should be cleared during initialization. No STF byte. See Section 33.3.4, “No STF Mode.” 0 Normal AAL2 cell structure. 1 The cell does not include the STF byte. In this mode each cell starts with a new packet and contains only whole packets (no split or partial). AAL type 000 AAL0 —Segmentation with no adaptation layer 001 AAL1 —ATM adaptation layer 1 protocol 010 AAL5 —ATM adaptation layer 5 protocol 100 AAL2 —ATM adaptation layer 2 protocol 101 AAL1_CES. Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.” All others reserved. Reserved, should be cleared during initialization. Reserved, should be cleared during initialization. Reserved, should be cleared during initialization. Points to the first queue to be serviced in the transmitter cycle. In round-robin priority mode (TCT[Fix]=0), this pointer could point to any one of the TxQDs related to this channel. In fixed priority mode (TCT[Fix]=1), this pointer should point to the highest priority TxQD. Rate remainder. Used by the APC to hold the rate remainder after adding the pace fraction to the additive channel rate. Should be cleared during initialization by the user. Peak cell rate fraction. Holds the peak cell rate fraction of this channel in units of 1/256 slot. If this is an ABR channel, this field is automatically updated by the CP. Peak cell rate. Holds the peak cell rate (in units of APC slots) permitted for this channel according to the traffic contract. Note that for an ABR channel, the CP automatically updates PCR to the ACR value. Timer_CU duration in units of APC slots. Assures that CPS-Packet already packed in a cell wait at most the Timer_CU duration. The user defines this field. 13–15 AAL 0x04 0x06 0x08 0x0A — — — — — — — FirstQueue 0x0C 0–7 Rate Remainder 8–15 PCR Fraction 0x0E — PCR 0x10 — Timer_CU_period 0x12 0x14 0x16 0x18 — — — — Timer_Period_Shadow This field must be initialized to the Timer_CU period in units of APC slots. — APCLC ATMCH Reserved, should be cleared during initialization. APC linked channel. Used by the CP. Should be cleared during initialization. ATM cell header. Holds the full (4-byte) ATM cell header of the current channel. The transmitter appends ATMCH to the cell payload during transmission. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-11 ATM AAL2 Table 33-1. AAL2 Protocol-Specific Transmit Connection Table (TCT) Field Descriptions (continued) Offset 0x1C Bits 0–1 2–7 Name1 — PMT Description Reserved, should be cleared during initialization. Performance monitoring table. Points to one of the available 64 performance monitoring tables. The starting address of the table is PMT_BASE+PMT*32. Holds the number of TX Queues visited for each cell being prepared for transmission. In fixed priority mode (TCT[Fix]=1), MaxStep should be set to the total number of TX queues in the channel. See Section 33.3.2, “Transmit Priority Mechanism.” Reserved, should be cleared during initialization. Partial fill threshold. Used for partially filled cells only; see Section 33.3.3, “Partial Fill Mode (PFM).” Specifies the maximum number of packet bytes allowed in a CPS PDU. The range 1–48 are valid values. If PFT=48 in partial fill mode, performance is adversely affected. When not in partial fill mode, PFT must be initialized to 47. Reserved, should be cleared during initialization. One packet per queue. See Section 33.3.2, “Transmit Priority Mechanism.” 0 The transmitter reads as many packets as possible from each TX queue before moving to the next queue. 1 The transmitter reads only one packet from each TX queue before advancing to the next queue. Stop transmit. Should be cleared during initialization. When the host sets this bit, the CP removes this channel from the APC and clears TCT[VCON] flag. Fixed priority. See Section 33.3.2, “Transmit Priority Mechanism.” 0 Round robin priority. The TX Queues related to this channel all share the same priority. 1 Fixed priority. The TX Queues are ordered in a fixed priority ladder. Performance monitoring 0 No performance monitoring for this VC. 1 Performance is monitored for this VC. When a cell is sent for this VC, the performance monitoring table indicated in PMT field is updated. 8–15 MaxStep 0x1E 0–1 2–7 — PFT 8–11 12 — OneP 13 STPT 14 Fix 15 PM 1 Boldfaced entries must be initialized by the user. 33.3.5.2 CPS Tx Queue Descriptor Each CPS TxBD table is managed by a CPS Tx queue descriptor (TxQD), as shown in Figure 33-7. The TxQD contains the address of the next BD to be serviced, and other queue-specific parameters. The NextQueue pointer is used to create a linked list of TxQDs, as described in Section 33.3.2, “Transmit Priority Mechanism.” The CPS TxQD is located in the dual-port RAM, in a 16-byte aligned address. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-12 Freescale Semiconductor ATM AAL2 0 7 8 9 10 11 12 13 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E — BNM SW HEC CPS TBM — TxBD Table Offset In (switched mode only) TxBD Table Base TxBD Table Offset Out Number of Packets In Queue NextQueue — Figure 33-7. CPS Tx Queue Descriptor (TxQD) Table 33-2 describes the CPS TxQD fields. . Table 33-2. CPS TxQD Field Descriptions Offset 0x00 Bits 0–7 8 Name1 — BNM Description Reserved for internal use. (Used to save the BD status of the open BD.) Buffer not-ready interrupt mask of the TxBD table. 0 The transmit buffer-not-ready event for this queue is masked. (The event is not sent to the interrupt queue.) 1 The buffer-not-ready event for this queue is enabled. Switching queue. 0 Normal TX Queue. 1 This TxQD handles a switching queue. The receiver and transmitter share this queue. HEC calculation. 0 Transmitter calculates the CPS header HEC. 1 The CPS header HEC is taken as is from the CPS buffer descriptor. Sublayer type. For a CPS TxQD, this field must be set. 0 SSSAR or SSTED. 1 CPS packet. Transmit buffer interrupt mask. 0 The transmit buffer event of this queue is masked. (The event is not sent to the interrupt queue). 1 The transmit buffer event of this queue is enabled. Reserved, should be cleared during initialization. Used only when this queue is used for switching (SW=1). Should be cleared during initialization. This pointer points to the base address of the BD table. Holds the offset from the TxBD table base to the next BD to be opened by the transmitter. Should be cleared during initialization. 9 SW 10 HEC 11 CPS 12 TBM 13–15 0x02 0x04 0x08 — — — — TxBD Table Offset In TxBD Table Base TxBD Table Offset Out MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-13 ATM AAL2 Table 33-2. CPS TxQD Field Descriptions (continued) Offset 0x0A Bits — Name1 Number of Packets In Queue Description Counts the number of packets currently in the queue. If this queue is switched, the receiver increments this counter with each new received packet and the transmitter decrements it with each packet sent. For switching, the user should initialize this counter to zero. When this queue is not switched, this counter counts down with every packet sent. (This can have various purposes such as evaluating the packet rate that is transmitted from this queue.). Points to the next TxQD to be serviced after this one. See Section 33.3.2, “Transmit Priority Mechanism.” Reserved, should be cleared during initialization. 0x0C 0x0E 1 — — NextQueue — Boldfaced entries must be initialized by the user. 33.3.5.3 CPS Buffer Structure The CPS buffer structure consists of a BD table that points to data buffers. The BDs contain, apart from the buffer pointer, also the packet header. The buffers contain the packet payload. See Figure 33-8. BD memory space TxBD table of ch 1 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 Data memory space Pointers from CPS TxQD TxBD_Table_Base Tx buffer 1 of channel 1 Tx buffer 3 of channel 1 TxBD_Table_Offset_Out • • • Tx buffer 4 of channel 1 Tx buffer 1 of channel 4 Tx buffer 2 of channel 1 TxBD_Table_Base Pointers from another CPS TxQD TxBD_Table_Offset_Out TxBD table of ch 4 TxBD 1 TxBD 2 TxBD 3 TxBD 4 TxBD 5 TxBD 6 TxBD 7 TxBD 8 TxBD 9 • • • Tx buffer 2 of channel 4 Tx buffer 3 of channel 4 Tx buffer 8 of channel 4 Figure 33-8. Buffer Structure Example for CPS Packets MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-14 Freescale Semiconductor ATM AAL2 Figure 33-9 shows a CPS TxBD. 0 1 2 3 4 7 8 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R CM W I — CPS Packet Header CPS Packet Header Tx Data Buffer Pointer (TXDBPTR) Figure 33-9. CPS TxBD Table 33-3 describes the CPS TxBD fields. . Table 33-3. CPS TxBD Field Descriptions Offset 0x00 Bits 0 Name1 R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or after an error condition is encountered. 1 The user-prepared buffer has not been sent or is currently being sent. No fields of this BD may be written by the user once R is set. Continuous mode 0 Normal operation. 1 The CP does not clear R after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of the CM bit setting. Wrap (final BD in table) 0 This is not the last BD in the TxBD table. 1 This is the last BD in the TxBD table. After this buffer is used, the CP transmits outgoing data for this channel from the first BD in the table (the BD pointed to by the channel’s TxBD_table_Base in the TxQD). The number of TxBDs in this table is determined only by the W bit. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced. The GHIN/GLIN bit in the event register is set when the INT_CNT counter reaches terminal count. Reserved, should be cleared during initialization. 1 CM 2 2 W 3 I 4–7 8–15 0x02 — — CPS Packet This field contains the beginning (MSB) of the 3-byte packet header. See Header Figure 33-10 for the CPS packet header format. CPS Packet This field contains the rest of the packet header. If TxQD[HEC] = 0, the HEC part of Header the packet header is calculated by the CP, and the user may disregard the five least-significant bits of this field. See Figure 33-10 for the CPS packet header format. TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. There are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. This pointer is not modified by the CP. 0x04 — 1 2 Boldfaced entries must be initialized by the user. Setting Continuous mode (TxBD[CM] = 1) is not allowed in CID switching mode. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-15 ATM AAL2 0 7 8 13 14 18 19 23 Channel identifier (CID) Length indicator (LI) User-to-user ID (UUI) Header error check (HEC) Figure 33-10. CPS Packet Header Format 33.3.5.4 SSSAR Tx Queue Descriptor A SSSAR TxBD table and its associated buffers are collectively called an SSSAR TX Queue. Each SSSAR TX Queue is managed by an SSSAR TxQD, as shown in Figure 33-11. The TxQD contains the base address of the BD table, the offset of the next BD to be serviced, the data buffer pointer, and other queue-specific parameters. The NextQueue pointer is used to create a linked list of TxQDs, as described in Section 33.3.2, “Transmit Priority Mechanism.” The SSSAR TxQD is located in the dual-port RAM in a 32-byte aligned address. 0 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0C Offset + 0x0E Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1a Offset + 0x1C Offset + 0x1E — Seg_Len BNM UUI INF CPS TBM SSSAR — — TxBD Table Base TxBD Table Offset Out — NextQueue — Figure 33-11. SSSAR Tx Queue Descriptor MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-16 Freescale Semiconductor ATM AAL2 Table 33-4 describes the SSSAR TxQD fields. . Table 33-4. SSSAR TxQD Field Descriptions Offset 0x00 Bits 0–7 8 Name1 — BNM Description Reserved, should be cleared during initialization. Buffer-not-ready interrupt mask of the TxBD table. 0 The transmit buffer-not-ready event for this queue is masked. (The event is not sent to the interrupt queue.) 1 The buffer-not-ready event for this queue is enabled. UUI insertion mode 0 UUI of last CPS packet is 0. 1 UUI of last CPS packet is taken from the next byte after the end of the buffer.2 Indicates the current state of the frame. 0 The next packet will be the first of a new frame. 1 Currently in the middle of the frame. Sublayer type. For an SSSAR TxQD, this field must be cleared. 0 SSSAR or SSTED. 1 CPS packet. Transmit buffer interrupt mask for TxBD table. 0 The transmit buffer event of this queue is masked. (The event is not sent to the interrupt queue.) 1 The transmit buffer event of this queue is enabled. SSSAR bit 0 SSTED sublayer 1 SSSAR sublayer Reserved, should be cleared during initialization. Specifies the maximum length in bytes of the SSSAR PDU (excluding the packet header). Seg_Len is limited to 45 in NoSTF=1 mode. The CP always attempts to segment the SSSAR SDU according to this length, but not more than it. Reserved, should be cleared during initialization. 9 UUI 10 INF 11 CPS 12 TBM 13 SSSAR 14–15 0x02 0–7 — Seg_Len 8–15 0x04 0x08 0x0A 0x0C 0x0E– 0x1E 1 2 — — — — — — TxBD Table Base Must be initialized to the first TxBD by the user. TxBD Table Offset Out — NextQueue — Used to calculate the pointer to the next TxBD to be used for transmission. Should be cleared during initialization. Reserved, should be cleared during initialization. Points to the next TxQD to be serviced after this one. See Section Section 33.3.2, “Transmit Priority Mechanism.” Reserved, should be cleared during initialization. Boldfaced entries must be initialized by the user. The 5-bit UUI field is inserted into the header of the last packet of an SSSAR SDU. The user must append the UUI to the last buffer as an additional byte. This additional byte is then inserted into the UUI field of the last packet header (note that, it is important that this additional byte—the byte after the last byte in the last data buffer of the SSSAR frame—contains the 5 bits of the UUI). The 3 MSB bits of this extra byte should be cleared; refer to Figure 33-10. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-17 ATM AAL2 33.3.5.5 SSSAR Transmit Buffer Descriptor The SSSAR buffer structure consists of a BD table that points to data buffers. The buffers may contain SSSAR SDUs belonging to different CIDs. Each buffer may contain a whole SSSAR SDU or part of it. The CPS CID is located in the first BD of the SSSAR SDU. See Figure 33-12. 0 1 2 3 4 5 7 8 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 R CM W I L — Data Length (DL) Tx Data Buffer Pointer (TXDBPTR) CID Figure 33-12. SSSAR TxBD . Table 33-5. SSSAR TxBD Field Descriptions Offset 0x00 0 Bits R Name1 Description Ready 0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or after an error condition is encountered. 1 The user-prepared buffer has not been sent or is currently being sent. No fields of this BD may be written by the user once R is set. Continuous mode 0 Normal operation. 1 The CP does not clear R after this BD is closed, allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of the CM bit setting. Wrap (final BD in table) 0 This is not the last BD in the TxBD table. 1 This is the last BD in the TxBD table. After this buffer is used, the CP transmits outgoing data for this channel from the first BD in the table (the BD pointed to by the channel’s TxBD_table_Base in the TxQD). The number of TxBDs in this table is determined only by the W bit. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced. The GHIN/GLIN bit in the event register is set when the INT_CNT counter reaches terminal count. Last. 0 This is not the last buffer of the SSSAR SDU. 1 This is the last buffer of the SSSAR SDU. Reserved, should be cleared during initialization. Contains the CID number of the SSSAR SDU pointed by this BD. This field should be written to the first BD of an SSSAR SDU. 1 CM 2 W 3 I 4 L 5–7 8–15 — CID MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-18 Freescale Semiconductor ATM AAL2 Table 33-5. SSSAR TxBD Field Descriptions (continued) Offset 0x02 Bits — Name1 Data Length Description Contains the length of the buffer associated with this BD. If this is the last buffer (L=1) and the UUI bit in the SSSAR TxQD is set, the 5-bit UUI field is located at (TXDBPTR+Data Length)[3:7] with bit [3] being the msb, that is, in the byte (right justified) immediately following the last byte of the buffer. For best bandwidth utilization and optimized partitioning of the SDU to packets of exactly Seglen size when an SDU is spread over multiple BD’s, the application should set Data Length to be an integer multiple of Seg_Len. (Data Length == n x Seg_Len). For an SDU on a single BD this restriction does NOT apply. Tx data buffer pointer. Points to the address of the associated buffer. There are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. This value is not modified by the CP. 0x04 — TXDBPTR 1 Boldfaced entries must be initialized by the user. 33.4 AAL2 Receiver The following sections describe the AAL2 receiver. 33.4.1 Receiver Overview The receiver cycle starts after the FCC receives a cell. If the cell header is successfully mapped to an ATM channel number, the corresponding RCT is fetched and the AAL type is read. For AAL2 cells, the receiver begins by checking if the last cell received in this channel (CID) has an uncompleted (split) packet. If so, the receiver first finishes handling this packet. The receiver then goes through a validation process. The receiver matches the OSF field in the STF with the expected OSF based on the actual split packet (if the first packet is not split, the OSF should be zero). If the two values do not match, an OSF error interrupt is issued and the receiver drops the last packet. Also, if the STF parity check, the SN check or the OSF>47 check results in an error, the receiver issues an interrupt and discards the whole cell. If any of the above errors has occurred and the cell has started with the remainder of an uncompleted packet, the receiver does the following: • For a CPS sublayer CID, the packet’s RxBD[UP] (uncompleted packet) bit is set. • For an SSSAR sublayer CID, the buffer is closed with RxBD[RxError = US = 10] (uncompleted SDU), and the rest of the frame is dropped. The receiver now begins the process of extracting new CPS packets out of the cell with another round of error checking. The receiver examines each CPS packet header for the following errors: • Incorrect packet HEC. The packet and rest of the cell are discarded. • Packet length (LI+1) is larger than CPS_Max_SDU_Length. The receiver discards the packet and then continues to extract the next packet in the cell. However, if the packet belongs to an SSSAR CID, the receiver closes the SSSAR buffer with RxBD[RxError = OS = 11] (oversized) and discards the rest of the frame. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-19 ATM AAL2 The receiver issues an interrupt for each of the above errors.When a SSSAR buffer is closed with RxBD[RxError = US or OS], indicating Uncompleted SDU or Oversized, then RxBD[L] is set, and if RxQD[RFM]=1 then the receiver also issues an RXF interrupt. Then, if no errors have occurred in the packet header, the packet CID is used to match the PHY | VP | VC | CID with an RxQD; see Section 33.4.2, “Mapping of PHY | VP | VC | CID.” The match process yields an RxQD pointer. The RxQD indicates the type of SAR operation to be performed on the PHY | VP | VC | CID. Three SAR operation modes are supported: • For the CPS sublayer, each packet from the CID is stored, as is, in a one packet buffer. • For switching, the packet is stored directly into the transmit buffer, and the CID is translated. • For the SSSAR sublayer, all packets received from the CID are reassembled into an SSSAR SDU similar to the BD and buffer structures used for AAL5 frames. • For the SSSAR sublayer, last packet UUI indication is stored in the last RxBD of the SDU. For the SSSAR sublayer, two additional parameters are verified for each new packet received: • RAS_Timer expiration. The RAS_Timer_Duration defined in the AAL2 parameter RAM limits the time (starting when the first packet is received) allowed to receive a complete SSSAR SDU. If this time limit is exceeded, the receiver closes the current buffer with RxBD[RxError = TE = 01] (Ras_Timer expired) and starts a new SSSAR frame with the next packet. When a buffer is closed with RxBD[RxError = TE = 01], RxBD[L] is not set and the receiver does not issue an RXF interrupt. • SSSAR_Max_SDU_Length. With each new packet the receiver checks whether the current accumulated length of the SSSAR SDU exceeds the SSSAR_Max_SDU_Length. If so, the receiver closes the current buffer with RxBD[RxError = OS = 11] (oversized), discards the rest of the SSSAR SDU, RxBD[L] is set, and if RxQD[RFM]=1 issues an RXF interrupt. NOTE CIDs that have the same number but that are from different AAL2 connections cannot use the same RxQD, unless they never have split packets. 33.4.2 Mapping of PHY | VP | VC | CID The AAL2 mapping mechanism translates a PHY | VP | VC | CID combination into an RxQD. An RxQD can be unique per PHY | VP | VC | CID. The mapping mechanism, shown in Figure 33-13, can be broken down as follows: • Each ATM channel number (RCT) has its own CID mapping table. The mapping table can be placed in internal or external memory (according to RCT[MAP]) and is pointed to by RCT[CID Mapping Table Base]. The CID of the received packet is used as an index into the mapping table. • Each entry in the mapping table contains a 2-byte RxQD offset. This offset, multiplied by 4, is the offset to an RxQD in either the internal or external RxQD table. • The two RxQD tables serve all the ATM channel numbers of an FCC. (RxQD_Base_Int and RxQD_Base_Ext are defined in the FCC parameter RAM.) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-20 Freescale Semiconductor ATM AAL2 • • • RxQD offsets from 8 through 511 point into the internal RxQD table located in dual-port RAM at RxQD_Base_Int. Note that the first 32 bytes of the internal RxQD table are reserved (so offsets 0–7 are reserved). RxQD offsets greater than 511 point into the external RxQD table located at RxQD_Base_Ext + (512*4). Because the three types of RxQDs are different sizes, some offset numbers may not be used. ATM cell Header STF CID-PH CPS packet payload CID-PH CPS packet payload AAL2 RCT RxQD_Base_Int (in FCC parameter RAM) RxBD table CID0 CID1 • • • CID255 RxQD offset RxQD offset Half-word RxQD_Base_Ext + 512*4 (in FCC parameter RAM) 2044 Tx queue descriptor RxQD table (external) 2048 CPS RxQD Switch RxQD TxBD table Tx buffers CID mapping table RxQD offset RxQD offset RxQD_Base_Int + RxQD_Offset*4 RxQD table (internal) 0 Reserved 32 SSSAR RxQD 64 CPS RxQD 72 Switch RxQD Rx buffers CID mapping table base RxBD table Rx buffers Figure 33-13. CID Mapping Process 33.4.3 AAL2 Switching Switching is performed by pointing an RX CID at a switch RxQD (see Figure 33-14). The switch RxQD is unique for each Rx CID. The descriptor holds a translation CID number and a pointer to a CPS TxQD into which this packet is saved and later sent by the transmitter. (The TxQD pointer is responsible for the actual PHY | VP | VC switching.) The TxQD pointed to by the switch RxQD(s) should have TxQD[SW] set and should not be modified by the host when the channel is active. The transmit scheduling of the packet is done by the APC according to the programmed bit rate of the ATM channel that holds the switched queue. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-21 ATM AAL2 ATM Rx VC1 CID mapping table TxQD RxQD table SW=1 Switch RxQD ATM Rx VC2 CID mapping table Switch RxQD TxQD SW=1 CID14 Offset TxBD table Tx buffers ATM Tx VC CID71 Offset TxBD table Tx buffers Figure 33-14. AAL2 Switching A partial packet discard mode is provided for the AAL2 switched channels that perform end-to-end SSSAR. When this mode is enabled (switch RxQD[PPD]=1), if no buffer is available to receive a packet in the middle of a frame, the subsequent middle packets of the SSSAR SDU are discarded. When the last packet of the SSSAR SDU arrives, the receiver attempts to re-open a buffer. A number-of-packets-in-queue counter is available in the TxQD. The CP increments the counter for each packet received and decrements it for each packet sent. The host can poll the counter periodically to verify that the switching queues are not over-loaded. On any open BD that is partially filled, the receiver sets the UP (Un-complete packet) bit. When the packet is fully received during a normal error-free operation, the UP mark is removed, the Empty bit is set, and operation continues. However, if an error is detected by the receiver, the Empty bit is set and the UP bit remains set. In such a case, the transmitter skips this BD and proceeds to the next one. If for any reason the receiver that was in the middle of the BD stopped receiving traffic, the UP bit remains set and the Empty bit is cleared. Another receiver using the same BD ring monitors the UP bit in addition to the Empty bit. If the UP bit is set, the other receiver does not proceed with the reception and gives a Busy interrupt. See Figure 33-17. The receiver that is in a “stuck” state marks the BD with the receiver channel code that received the partial packet so that the host intervention is easier if needed. See Figure 33-19. If the TBNR Time Out CNT mechanism is used, the transmitter advances after it tries to transmit the same BD with UP set after a given amount of attempts. The BD will be freed up for use. Refer to the TBNR Time Out CNT description in Table 33-6. 33.4.4 AAL2 RX Data Structures The following sections describe the receive connection tables and the structures in which CPS packets and SSSAR SDUs are stored in memory. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-22 Freescale Semiconductor ATM AAL2 33.4.4.1 AAL2 Protocol-Specific RCT The receive connection table (RCT) is a VC-level table and is where the AAL type for the ATM channel number is selected. The parameters related to the ATM channel number or to all the RX Queues of the ATM channel are maintained here. The RCT also contains the pointer to the CID mapping table for the ATM VC. Figure 33-15 shows the AAL2-specific RCT. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0c Offset + 0x0e Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — GBL BO — DTB BIB — — SEGF ENDF — NoSTF MAP INTQ AAL — CID Mapping Table Base — PMT Max_CPS_SDU_Deliver_length TBNR Time OUT CNT — EM PM Figure 33-15. AAL2 Protocol-Specific Receive Connection Table (RCT) NOTE For an active channel, the CP uses a burst cycle to fetch the 32-byte RCT and writes back only the first 24 bytes. Table 33-6 describes the AAL2 RCT fields. Table 33-6. AAL2 Protocol-Specific RCT Field Descriptions Offset 0x00 Bits 0–1 2 3–4 — GBL BO Name 1 Description Reserved, should be cleared during initialization. Global. Setting GBL enables snooping of data buffers, BDs, interrupt queues and free buffer pool. Byte ordering—used for data buffers. 00 Reserved 01 munged little endian 1x Big endian MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-23 ATM AAL2 Table 33-6. AAL2 Protocol-Specific RCT Field Descriptions (continued) Offset 5 6 Bits — DTB Name 1 Description Reserved, should be cleared during initialization. Data buffer bus selection. 0 Reside on the 60x bus. 1 Reside on the local bus. Bus selection for the BDs, interrupt queues, CID mapping table, RxQDs, and the free buffer pool. 0 Reside on the 60x bus. 1 Reside on the local bus. Reserved, should be cleared during initialization. OAM F5 segment filtering 0 Do not send cells with PTI=100 to the raw cell queue. 1 Send cells with PTI=100 to the raw cell queue. OAM F5 end-to-end filtering 0 Do not send cells with PTI=101 to the raw cell queue. 1 Send cells with PTI=101 to the raw cell queue. Reserved, should be cleared during initialization. CID mapping table memory location select 0 Resides in the dual-port RAM. 1 Resides in external memory. Assigns one of the four available interrupt queues to this ATM channel number. Reserved, should be cleared during initialization. No STF byte. 0 Normal AAL2 cell structure. 1 The cell does not include the STF byte. In this mode each cell starts with a packet and contains only whole packets (no split or part). AAL type 000 AAL0 —Reassembly with no adaptation layer 001 AAL1 —ATM adaptation layer 1 protocol 010 AAL5 —ATM adaptation layer 5 protocol 100 AAL2 —ATM adaptation layer 2 protocol 101 AAL1_CES. Refer to Chapter 32, “ATM AAL1 Circuit Emulation Service.” All others reserved. 7 BIB 8–9 10 — SEGF 11 ENDF 12 13 — MAP 14–15 0x02 0–11 12 INTQ — NoSTF 13–15 AAL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-24 Freescale Semiconductor ATM AAL2 Table 33-6. AAL2 Protocol-Specific RCT Field Descriptions (continued) Offset 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 Bits — — — — — — — — — — — CID Mapping Points to the base address of the CID mapping table (see Figure 33-13). Table Base If RCT[MAP] = 0, the pointer contains a dual-port RAM address and only the 16 lsb (at 0x1A and 0x1B) are relevant. If MAP = 1, the pointer is a full 32-bit address in the memory space. — PMT TBNR Time Out CNT Reserved, should be cleared during initialization. Performance monitoring table. Assigns one of the available 64 performance monitoring tables to this VC. The table’s starting address is PMT_BASE+PMT*32. The TBNR Time-Out CNT is a parameter that describes the amount of attempts the transmitter tries to transmit a packet on a BD ring which is current marked as partially filled, i.e. waiting for a receiver to finish reception of a packet. This value will be used internally by the transmitter that is the destination for this packet and decremeted by the CPM on each attempt. Upon reaching the value 1, the transmitter will act as if the receiver is stuck in error condition and proceed to the next BD in the BD ring. This parameter is valid in switch mode only and should be programmed to a higher value than the ratio between the transmitter rate and the lowest receiver rate in the BD ring. The 8 bit value is scaled by 4 (setting TBNR Time-Out CNT =1 yields a value of 4 internally) so that the max number is 1K. Clearing this field will disable this feature completely — Name 1 Description Reserved, should be cleared during initialization. 0x1C 0–1 2–7 8–15 0x1E 0–7 Max_CPS_S Indicates the maximum size CPS_SDU in bytes that is allowed to be transported on DU_Deliver_ this channel. This value is compared to the length of each CPS_SDU before it is delivered, as specified in the ITU-T recommendation I.363.2. Length — EM Reserved, should be cleared during initialization. Receive error mask for AAL2 protocol-specific events. Note that buffer-not-ready, Rx buffer and Rx frame events are not affected by this mask. 0 Disable AAL2 receive error events. 1 Enable AAL2 error events. Enable performance monitoring 0 No performance monitoring for this VC. 1 Perform performance monitoring for this VC. Whenever a cell is received by this VC, the associated performance monitoring table is updated. 8–13 14 15 PM 1 Boldfaced entries must be initialized by the user. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-25 ATM AAL2 33.4.4.2 CID Mapping Tables and RxQDs Each PHY | VP | VC | CID combination is assigned an RxQD using a CID mapping table. To multiplex several receive CIDs into a single common queue, map each multiplexed PHY | VP | VC | CID combination to one RxQD. The ATM channel’s RCT contains the base address of the associated CID mapping table. This base address is external (32 bits) when RCT[MAP]=1; otherwise, the table resides in the dual-port RAM and the base address is two bytes. The CID of the received packet is used as an index into the mapping table. The mapping table entries are 2-byte RxQD offsets. If the CID mapping table is external, it must be on the same bus as the BDs and interrupt queues as specified by RCT[BIB]. There are two RxQDs—one for internal RxQDs and one for external RxQDs. Offsets between 0–511 belong to the 2048-byte internal RxQD table. It is recommended to have as many RxQDs as possible in the internal table. Note that the first 32 bytes of the internal RxQD table are reserved for internal use; that is, RxQD offsets between 0–7 are reserved. The address of an internal RxQD is RxQD_Base_Int + 4*RxQD_Offset. Offsets between 512–65535 belong to the external RxQD table. The address of an external RxQD is RxQD_Base_Ext + 4*RxQD_Offset. The external RxQD table must be on the same bus as the BDs and interrupt queues as specified by RCT[BIB]. Because the three kinds of RxQDs are each a different size (for example, an SSSAR RxQD is 32 bytes and a CPS switch RxQD is only 4 bytes), some of the offset numbers are left unused. 33.4.4.3 CPS Rx Queue Descriptors Each CPS RxQD, as shown in Figure 33-16, points to an CPS RxBD table. 0 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 — RxBD Table Offset RxBD Table Base RBM — SubType Figure 33-16. CPS Rx Queue Descriptor MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-26 Freescale Semiconductor ATM AAL2 Table 33-7 describes the CPS RxQD fields. Table 33-7. CPS RxQD Field Descriptions Offset 0x00 Bits 0–11 12 — RBM Name1 Description Reserved, should be cleared during initialization. Receive buffer mask. 0 Disable receive buffer interrupt. 1 Enable receive buffer interrupt. Reserved, should be cleared during initialization. SubType. Sublayer type, should be 00 (CPS) for this descriptor. 00 CPS sublayer. 01 CPS switched. 10 SSSAR. 11 Reserved. 13 — 14–15 SubType 0x02 0x04 1 — — RxBD Table Holds the offset to the next BD to be opened by the receiver. Should be cleared Offset during initialization. RxBD Table Holds the pointer to the first BD in the BD table. Base Boldfaced entries must be initialized by the user. 33.4.4.4 CPS Receive Buffer Descriptor (RxBD) The CPS RxBD structure consists of a BD table that points to data buffers. The RxBDs contain, apart from the buffer pointer, the packet header, as shown in Figure 33-17. The buffers contain the packet payload. 0 1 2 3 4 6 7 8 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 E CM W I — UP Packet Header CPS Packet Header Rx Data Buffer Pointer (RXDBPTR) Figure 33-17. CPS Receive Buffer Descriptor Table 33-8 describes the CPS RxBD fields. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-27 ATM AAL2 . Table 33-8. CPS RxBD Field Descriptions Offset 0x00 0 Bits E Name1 Description Buffer empty bit 0 The CPS RX buffer is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD while E remains zero. 1 The CPS RX buffer is empty or reception is in progress. This is controlled by the CP. Once E is set, the core should not access any fields of this buffer. Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed, allowing the associated buffer to be reused automatically when the CP next accesses this BD. However, the E bit is cleared if an error occurs while receiving, regardless of the CM bit setting. Wrap (final BD in table) 0 This is not the last BD in the RxBD table. 1 This is the last BD in the RxBD table of this current channel. After this buffer has been used, the CP receives incoming data for this channel into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 The CP will not issue an interrupt after this buffer is serviced. 1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD is set. Reserved, should be cleared during initialization. Uncompleted packet 0 No error occurred in this packet 1 A receive error occurred that caused this packet to be uncompleted. The receive error type is reported to the interrupt queue. 1 CM 2 W 3 I 4–6 7 — UP 8–15 0x02 — CPS Packet Contains the beginning of the packet header. See Figure 33-10 for the CPS packet Header header format. CPS Packet Contains the rest of the packet header. The CP checks the packet HEC and if Header appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0. See Figure 33-10 for the CPS packet header format. RXDBPTR Rx data buffer pointer. Points to the address of the associated buffer. There are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. This value is not modified by the CP. 0x04 — 1 Boldfaced entries must be initialized by the user. 33.4.4.5 CPS Switch Rx Queue Descriptor The switch RxQD, shown in Figure 33-18, is used for CIDs that are being switched from one PHY1 | VP1 | VC1 | CID1 to another PHY2 | VP2 | VC2 | CID2. The RxQD contains the pointer to the TxQD that controls the TxBD table through which the packet is transferred. The switch RxQD also contains the translation CID that is saved with the packet in the transmit buffer. A PPD mode enables the discarding of the rest of an SSSAR frame when a buffer is not available. Note that the CPS switch RxQD must be unique for every Rx switched CID. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-28 Freescale Semiconductor ATM AAL2 0 7 8 11 12 13 14 15 Offset + 0x00 Offset + 0x02 TX CID — TxQD Pointer RBM PPD SubType Figure 33-18. CPS Switch Rx Queue Descriptor Table 33-9 describes the CPS switch RxQD fields. Table 33-9. CPS Switch RxQD Field Descriptions Offset 0x00 Bits 0–7 8–11 12 Name1 TX CID — RBM Description Translation CID. The received CID is saved in a TX Queue with this new CID number. Reserved, should be cleared during initialization. Receive buffer mask 0 Disable receive buffer interrupt 1 Enable receive buffer interrupt Partial packet discard 0 Normal mode 1 When a buffer-not-ready event causes a packet to be discarded, the remainder of the SSSAR SDU is also discarded. This allows for better performance for switched channels that implement SSSAR. Sublayer type. Should be 01 (CPS switched) for this descriptor. 00 CPS sublayer 01 CPS switched 10 SSSAR 11 Reserved Points to the TxQD into which the packets of this CID are stored and later sent. 13 PPD 14–15 SubType 0x02 1 — TxQD Pointer Boldfaced entries must be initialized by the user. 33.4.4.6 SWITCH Receive/Transmit Buffer Descriptor (RxBD) The switch buffer structure consists of a BD table that points to data buffers. The RxBDs contain, apart from the buffer pointer, the packet header, as shown in Figure 33-19. The buffers contain the packet payload. This BD is common to the receiver and the transmitter. 0 1 2 3 4 5 6 7 8 15 Offset + 0x00 E/R Offset + 0x02 Offset + 0x04 Offset + 0x06 0 W I — UP CPS Packet Header Packet Header (Receiver CC) Rx Data Buffer Pointer (RXDBPTR) Figure 33-19. Switch Receive/Transmit Buffer Descriptor MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-29 ATM AAL2 Table 33-10 describes the Switch RxBD fields. Table 33-10. Switch RxBD Field Descriptions Offset 0x00 Bits 0 1 2 Name1 E/R 0 W Buffer Ready Must be set to zero. Not valid for switching mode, should be cleared to 0 upon initialization. Wrap (final BD in table) 0 This is not the last BD in the RxBD table. 1 This is the last BD in the RxBD table of this current channel. After this buffer has been used, the CP receives incoming data for this channel into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt. 0 The CP will not issue an interrupt after this buffer is serviced. 1 The CP will issue an interrupt after this buffer is serviced if the RBM bit in the RxQD is set. Reserved, should be cleared during initialization. Uncompleted packet. 0 No error occurred in this packet and the complete packet has been received. 1 if R/E=1 a receive error occurred that caused this packet to be uncompleted. The receive error type is reported to the interrupt queue. The transmitter will skip this BD when in this state and continue to the next BD in the ring. If R/E=0 a receiver has received the first part of a packet and is waiting for the rest of it to be received on the next ATM cell. Contains the beginning of the packet header. See Figure 33-10 for the CPS packet header format. (see remark in next row) Contains the rest of the packet header. The CP checks the packet HEC and if appropriate, indicates a packet HEC error in an interrupt queue entry with CID = 0. See Figure 33-10 for the CPS packet header format. In case of a “stuck” receiver in switch mode, where the BD ring in common to Tx and Rx, this field indicates the last Receiver Channel Code number which has been received. The terminology for “stuck” implies a receiver which started receiving a packet and the rest of the packet hasn’t been received.When the receiver is in a “stuck” state the entry: CPS Packet Header is not valid. If the Time-out mechanism is being used this field is being used internally by the CPM. Rx data buffer pointer. Points to the address of the associated buffer. There are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. This value is not modified by the CP. Description 3 I 4–6 7 — UP 8–15 0x02 — CPS Packet Header CPS Packet Header (Receiver CC) 0x04 — RXBDPTR 1 Boldfaced entries must be initialized by the user. 33.4.4.7 SSSAR Rx Queue Descriptor The SSSAR RxQD, as shown in Figure 33-20, points to the RxBD table and contains other parameters specific to the SSSAR sublayer. This descriptor can belong to only one PHY | VP | VC | CID. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-30 Freescale Semiconductor ATM AAL2 0 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 Offset + 0x08 Offset + 0x0A Offset + 0x0c Offset + 0x0e Offset + 0x10 Offset + 0x12 Offset + 0x14 Offset + 0x16 Offset + 0x18 Offset + 0x1A Offset + 0x1C Offset + 0x1E — RxBD Table Offset RxBD Table Base RasT RBM RFM SubType — Time Stamp — — MRBLR Max_SSSAR_SDU_Length — Figure 33-20. SSSAR Rx Queue Descriptor Table 33-11 describes the SSSAR RxQD fields. . Table 33-11. SSSAR RxQD Field Descriptions Offset 0x00 Bits 0–10 11 — RasT Name1 Description Reserved, should be cleared during initialization. Ras Timer enable. 0 Ras Timer disabled (Time Stamp field is still valid) 1 Ras Timer enabled. The Ras Timer duration is set by the Ras Timer Duration parameter in the parameter RAM. If the current SSSAR SDU is not completed before the RasTimer expires, the BD is closed showing the Ras_Timer expired (TE) (SSSAR RxBD[RxError] = 01) and the next packet starts a new SDU. Receive buffer mask. 0 Disable receive buffer interrupt 1 Enable receive buffer interrupt Receive frame mask. 0 Disable receive frame interrupt 1 Enable receive frame interrupt Sublayer type. Should be 10 (SSSAR) for this descriptor. 00 CPS sublayer 01 CPS switched 10 SSSAR 11 Reserved 12 RBM 13 RFM 14–15 SubType MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-31 ATM AAL2 Table 33-11. SSSAR RxQD Field Descriptions (continued) Offset 0x02 0x04 0x08 0x0A 0x0C Bits — — — — — Name1 RxBD Table Offset RxBD Table Base — — Time Stamp Description Points to the next BD to be handled by the CP. The user should initialize this pointer to zero. Points to the beginning of the BD table. Reserved, should be cleared during initialization. Reserved, should be cleared during initialization. Used for reassembly timeout of the SSSAR SDU. Whenever the first packet of an SSSAR SDU arrives the timestamp timer is sampled and stored here (regardless of the RasT bit). Reserved, should be cleared during initialization. Reserved, should be cleared during initialization. Maximum receive buffer length. Holds the maximum receive buffer length. The actual buffer size can be less. 0x10 0x12 0x14 0x16 — — — — — — MRBLR Max_SSSAR Holds the maximum SSSAR SDU length. Upon each new packet the accumulated frame size is compared with this value. If the limit is exceeded, the CP discards the rest _SDU_ of the packets of the current frame. Length — Reserved, should be cleared during initialization. 0x18– 0x1E 1 — Boldfaced entries must be initialized by the user. 33.4.4.8 SSSAR Receive Buffer Descriptor The SSSAR SDU is stored in a BD-buffer structure similar to the structures used for AAL5 frames. The buffer size is determined by SSSAR RxQD[MRBLR]; the actual buffer space used may be smaller. If the received SSSAR SDU is greater than MRBLR, the SDU spans over multiple buffers. The SSSAR RxBD is shown in Figure 33-21. 0 1 2 3 4 5 6 7 10 11 15 Offset + 0x00 Offset + 0x02 Offset + 0x04 Offset + 0x06 E CM W I L RxError — Data Length (DL) UUI Rx Data Buffer Pointer (RXDBPTR) Figure 33-21. SSSAR Receive Buffer Descriptor MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-32 Freescale Semiconductor ATM AAL2 Table 33-12 describes the SSSAR RxBD fields. Table 33-12. SSSAR RxBD Field Descriptions Offset 0x00 0 Bits E Name1 Description Empty 0 The buffer associated with this RxBD is full or data reception was aborted due to an error. The core can read or write any fields of this RxBD. The CP does not use this BD again while E remains zero. 1 The buffer associated with this RxBD is empty or reception is in progress. This RxBD and its receive buffer are controlled by the CP. Once E is set, the core should not write any fields of this RxBD. Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed, allowing the associated buffer to be reused automatically when the CP next accesses this BD. However, the E bit is cleared if an error occurs while receiving, regardless of the CM bit setting. Wrap (final BD in the table) 0 This is not the last BD in the RxBD table of the current channel. 1 This is the last BD in the RxBD table of this current channel. After this buffer has been used, the CP receives incoming data for this channel into the first BD in the table. The number of RxBDs in this table is programmable and is determined only by the W bit. The current table cannot exceed 64 Kbytes. Interrupt 0 No interrupt is generated after this buffer has been serviced. 1 An Rx buffer event is sent (provided that RxQD[RBM] is set) to the interrupt queue after this buffer is serviced. The GHIN/GLIN bit in the event register is set when the INT_CNT counter reaches terminal count. Last. Set by the CP. 0 This is not the last buffer of the SSSAR SDU. 1 This is the last buffer of the SSSAR SDU. Rx error occurred 00 No Rx error occurred 01 TE—Ras_Timer expired. The Ras Timer expired before this buffer could be completed. The SSSAR SDU stored in this buffer is not completed.2 10 US—Uncompleted SDU. A receive error caused a packet belonging to this SSSAR SDU to be lost. The receiver discarded the rest of this SSSAR SDU. 11 OS—Oversized. The size of the SSSAR SDU has exceeded the Max_SSSAR_SDU_Size parameter. The rest of the SDU was discarded. Reserved, should be cleared during initialization. Contains the UUI of the last packet in the received SDU. Valid only where the L bit is set. 1 CM 2 W 3 I 4 L 5–6 RxError 7–10 11–15 — UUI MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-33 ATM AAL2 Table 33-12. SSSAR RxBD Field Descriptions (continued) Offset 0x02 0x04 Bits — — Name1 Data Length RXDBPTR Description Contains the length of the buffer associated with this BD. If this is the last buffer (L=1) of the SSSAR SDU, this field contains the total frame length. Rx data buffer pointer. Points to the address of the associated buffer. There are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. This value is not modified by the CP. 1 2 Boldfaced entries must be initialized by the user. When RAS timer expires the RxBD is closed with RAS timer expired indication, the Last (L) bit is not set, and RXF interrupt is not issued. A new RxBD is opened for the next incoming AAL2 packet and the frame is processed as normal and is treated as a new frame. When the next SSSAR end-of-frame indication is received, the RxBD at that time is closed with an L indication, and if RxQD[RFM] = 1, the receiver issues an RXF interrupt. 33.5 AAL2 Parameter RAM When configured for ATM mode, the FCC parameter RAM is mapped as shown in Table 33-13. The table includes both the fields for general ATM operation and also the fields specific to AAL2 operation. Note that some of the values must be initialized by the user, but values updated by the CP should not be modified by the user. Table 33-13. AAL2 Parameter RAM Offset 0x00– 0x3F 0x40 — RCELL_TMP_BASE Name Width — Description Reserved. Should be cleared during initialization. Hword Rx cell temporary base address. Points to a total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64 byte aligned. User-defined. (Recommended address space: 0x3000–0x4000 or 0xB000–0xC000.) Hword Tx cell temporary base address. Points to total of 64 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined. (Recommended address space: 0x3000–0x4000 or 0xB000–0xC000.) Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM area used by the CP. Should be 64-byte aligned. User-defined. (Recommended address space: 0x3000–0x4000 or 0xB000–0xC000.) Hword Internal receive connection table base. User-defined. Hword Internal transmit connection table base. User-defined. Hword Internal transmit connection table extension base. User-defined. Word Word Word Word Contains the RAS_Timer duration in microseconds for the SSSAR sublayer. User-defined. External receive connection table base. User-defined. External transmit connection table base. User-defined. External transmit connection table extension base. User-defined. 0x42 TCELL_TMP_BASE 0x44 UDC_TMP_BASE 0x46 0x48 0x4A 0x4C 0x50 0x54 0x58 INT_RCT_BASE INT_TCT_BASE INT_TCTE_BASE RAS_Timer_Duration EXT_RCT_BASE EXT_TCT_BASE EXT_TCTE_BASE MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-34 Freescale Semiconductor ATM AAL2 Table 33-13. AAL2 Parameter RAM (continued) Offset 0x5C Name UEAD_OFFSET Width Description Hword User-defined cells mode only. The offset of the UEAD entry in the UDC extra header. Should be an even address. If RCT[BO]=01 UEAD_OFFSET should be in little-endian format. For example if UEAD entry is the first half word of the extra header in external memory, UEAD_OFFSET should be set to 2 (second half word entry in internal RAM). Hword Points to the base address of the internal RxQD table. The pointer should be 32-byte aligned. User-defined. Hword Performance monitoring table base. User-defined. Hword APC parameters table base address. User-defined. Hword Free buffer pool parameters table base. User-defined. Hword Interrupt queue parameters table base. User-defined. — Reserved. Should be cleared during initialization. 0x5E 0x60 0x62 0x64 0x66 0x68 0x6A 0x6C RxQD_Base_Int PMT_BASE APCP_BASE FBT_BASE INTT_BASE — UNI_STATT_BASE BD_BASE_EXT Hword UNI statistics table base. User-defined. Word BD table base address extension. BD_BASE_EXT[0-7] hold the 8 most significant bits of the RX/TxBD table base address. BD_BASE_EXT[8-31] should be zero. User-defined. Base address of the address compression VP table/external CAM. User-defined. Base address of the address compression VC table. User-defined. Base address of the address compression VP1 table/EXT CAM1. User-defined. Base address of the address compression VC1 table. User-defined. 0x70 0x74 0x78 0x7C 0x80 0x82 VPT_BASE / EXT_CAM_BASE VCT_BASE VPT1_BASE / EXT_CAM1_BASE VCT1_BASE VP_MASK VCI_Filtering Word Word Word Word Hword VP mask for address compression lookup. User-defined. Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCI_Filtering bit = 1 the cell is sent to the raw cell queue. VCI=3 is associated with VCI_Filtering[3], VCI=15 is associated with VCI_Filtering[15]. VCI_Filtering[0–2, 5] should be zero. See Section 31.10.1.2, “VCI Filtering (VCIF).” Hword Global mode. User-defined. See Section 31.10.1.3, “Global Mode Entry (GMODE).” Hword The information field associated with the last host command. User-defined. See Section 31.14, “ATM Transmit Command. “ Hword Hword 0x84 0x86 0x88 0x8A 0x8C 0x90 0x94 GMODE COMM_INFO — CRC32_PRES CRC32_MASK Word Word Word Reserved. Should be cleared during initialization. Preset for CRC32. Initialize to 0xFFFFFFFF. Constant mask for CRC32. Initialize to 0xDEBB20E3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-35 ATM AAL2 Table 33-13. AAL2 Parameter RAM (continued) Offset 0x98 Name AAL1_SNPT_BASE Width Description Hword AAL1 SN protection look up table base address. (AAL1 only.) The 32-byte table resides in dual-port RAM and must be initialized by the user (See Section 31.10.6, “AAL1 Sequence Number (SN) Protection Table”). Hword Reserved. Should be cleared during initialization. Word External SRTS logic base address. (AAL1 only.) Should be 16-byte aligned. 0x9A 0x9C 0xA0 — SRTS_BASE IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/unassign cell template (little-endian format). Should be 64-byte aligned. User-defined. The ATM header should be 0x0000_0000 or 0x0100_0000 (CLP=1). Hword Idle/Unassign cell size. 52 in regular mode. 53–64 in UDC mode. Word Word Reserved payload. Initialize to 0x6A6A6A6A. (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler (See RTSCR). For time stamp prescalar of 1µs, Trm should be set to 100 ms/1µs = 100,000. 0xA2 0xA4 0xA8 IDLE/UNASSIGN_SIZE EPAYLOAD Trm 0xAC 0xAE 0xB0 Nrm Mrm TCR Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. Hword (ABR only) Tag cell rate. The minimum cell rate allowed for all ABR channels. An ABR channel whose ACR is less than TCR sends only out-of-rate F-RM cells at TCR. Should be set to 10 cells/sec as defined in the TM 4.0. Uses the ATMF TM 4.0 floating-point format. Note that the APC minimum cell rate should be at least TCR. Hword (ABR only) Points to total of 16 bytes reserved dual-port RAM area used by the CP. Should be 16-byte aligned. User-defined. Word Points to the base address of the external RxQD table. The actual address of the first RxQD in the table is RxQD_Base_Ext + 512*4. User-defined. Valid only for AAL2 VCs. Points to the base of the RX UDC header table that contains the UDC headers of the AAL2 VCs. The pointer to a VC UDC header is: RX_UDC_Base + 16*CH# (where CH# is the ATM channel number) Valid only for AAL2 VCs. Points to the base of the TX UDC header table that contains the UDC headers of the AAL2 VCs. The pointer to a VC UDC header is: TX_UDC_Base + 16*CH# (where CH# is the ATM channel number) Reserved. Should be cleared during initialization. 0xB2 0xB4 ABR_RX_TCTE RxQD_Base_Ext 0xB8 RX_UDC_Base Word 0xBC TX_UDC_Base Word 0xC0– 0xDF — — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-36 Freescale Semiconductor ATM AAL2 Table 33-13. AAL2 Parameter RAM (continued) Offset 0xE0 Name Width Description Transmit Cell Temporary base address. Points to a total of 64*last_AAL2_Ch# octets reserved in external memory for partially filled cells. Note: TCELL_TMP_BASE_EXT must be on the same bus as the all the AAL2 data buffers required for CPS, SSSAR and CID switching. Reserved. Should be cleared during initialization. TCELL_TMP_BASE_EXT Word 0xE4– 0xFB 0xFC 0xFE — PAD_TMP_BASE — — Hword PAD template base address. Points to an internal memory area that contains the zero cell template. Should be 64-byte aligned. User-defined. — Reserved. Should be cleared during initialization. 33.6 User-Defined Cells in AAL2 The user-defined cell (UDC) mode for ATM as described in Section 31.7, “User-Defined Cells (UDC),” also applies to AAL2 operation. However, for AAL2 operation only, the UDC headers reside in a table in external memory, not in the BDs. For transmit channels in AAL2 UDC mode, initialize its UDC header entry in the TX UDC header table before activating the channel. The header can be up to 12 bytes. The TX_UDC_Base parameter in the parameter RAM (see Table 33-13), points to the beginning of the TX UDC header table. The UDC header of a specific AAL2 transmit VC is located at the following address: TX_UDC_Base + CH# *16 (where CH# is the ATM channel number) For receive channels in AAL2 UDC mode, the receiver copies the UDC header from the first cell received by the VC to the RX_UDC header table. The UDC headers of subsequent cells of that VC are discarded; UDC extended address mode (UEAD) is not affected. The UDC header of a specific AAL2 receive VC is located at the following address: RX_UDC_Base + CH#*16 (where CH# is the ATM channel number) The structure of a UDC header table (receive or transmit) is shown in Figure 33-22. UDC_Base 0 CH0 UDC header 16 CH1 UDC header n*16 CHn UDC header Figure 33-22. UDC Header Table MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-37 ATM AAL2 33.7 AAL2 Exceptions For each VC, four circular interrupt queues are available. By programming RCT[INTQ] and TCT[INTQ] for each VC, the user assigns an interrupt queue number. When one of the CIDs generates an interrupt request, the CP writes a new entry to the interrupt queue containing the ATM channel number, the CID and a description of the exception. Because CID = 0 is a unique CID number, it is used to specify that the event is related to the VC rather than the CID. As with all ATM exceptions, the valid (V) bit is then set and INTQ_PTR is incremented. When INTQ_PTR reaches a location with the W bit set, it wraps to the first entry in the queue. More details can be found in Section 31.11, “ATM Exceptions.” An interrupt entry for a CID is shown in Figure 33-23. 0 1 2 3 10 11 12 13 14 15 Offset + 0x00 Offset + 0x02 V — W CID Channel Code (CC) TBNR RXB BSY TXB RXF Figure 33-23. AAL2 Interrupt Queue Entry CID ≠ 0 Table 33-14 describes the interrupt queue entry fields for a CID. Table 33-14. AAL2 Interrupt Queue Entry CID ≠ 0 Field Descriptions Offset 0x00 0 Bits Name V Description Valid interrupt entry 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. — Wrap bit. When set, this is the last interrupt entry in the circular table. During initialization, the host must clear all W bits in the table except the last one, which must be set. CID number. The exception occurred for this CID. Tx buffer not ready interrupt. This interrupt is issued when the CP tries to open a TxBD, which is not ready (R = 0). This interrupt is sent only if TxQD[BNM] = 1. The interrupt has an associated channel code and CID. Note: The CID number that is placed in the interrupt queue is the one currently located in the last BD. Because the CID is not updated when the BD is not ready, the CID value is the one extracted from this BD when it was last processed and transmitted. If the BD is never processed and the BD was cleared, the CID value could be zero. Rx buffer interrupt. This interrupt is issued when the I bit is set for an RxBD and the RxQD[RBM] bit is set. This interrupt has an associated channel code and CID. Busy condition. The RxBD table associated with this channel’s CID is busy. Packets were discarded due to this condition. Transmit buffer interrupt. This interrupt is issued when the TxBD[I] bit is set. This interrupt is sent only if TxQD[TBM] is set. This interrupt has an associated channel code and CID. Receive SSSAR SDU (frame). An SSSAR frame belonging to this channel’s CID has been received. This interrupt is sent only if RxQD[RFM]=1. Channel code specifies the ATM channel number associated with this interrupt. 1 2 3–10 11 — W CID TBNR 12 13 14 15 0x02 1 RXB1 BSY TXB RXF1 CC — These interrupt queue fields are defined differently for other AAL types. Refer toTable 31-42 for more information. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-38 Freescale Semiconductor ATM AAL2 An interrupt entry for the VC is shown in Figure 33-24. . 0 1 2 3 10 11 12 15 Offset + 0x00 Offset + 0x02 V — W 0000_0000 Channel Code (CC) Error_Code Figure 33-24. AAL2 Interrupt Queue Entry CID = 0 Table 33-15 describes the interrupt queue entry fields for the VC. All the receive error events are enabled by setting RCT[EM]. Table 33-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions Offset 0x00 0 Bits V Name Description Valid interrupt entry 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. — Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. CID number. Equals zero. This exception applies to the whole cell. Reserved 1 2 3–10 11 12–15 — W CID — Error_Code A receive error was detected. 0000 Parity error of the OSF. 0001 The STF sequence number is incorrect. 0010 The number of octets expected to overlap into this cell does not match the OSF. 0011 OSF is greater than 47. 0100 A packet HEC error was detected. 0101 The length of the CPS packet exceeds the Max_SDU_Length. 0111 A packet HEC error was detected in a split header packet. CC Channel code specifies the ATM channel number associated with this interrupt. 0x02 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 33-39 ATM AAL2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 33-40 Freescale Semiconductor Chapter 34 Inverse Multiplexing for ATM (IMA) NOTE The functionality described in this chapter is available only on the MPC8280. Refer to www.freescale.com for the latest RAM microcode packages that support enhancements. This chapter provides specifications for the inverse multiplexing for ATM (IMA) microcode. In this chapter, ‘IMA microcode’ and ‘microcode’ are synonymous. 34.1 Features The IMA ATM Forum Specification defines the functions shown in Table 34-1. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-1 Inverse Multiplexing for ATM (IMA) I Table 34-1. IMA Sublayer in Layer Reference Model Layer ATM Sublayer — User Plane Functions — • ATM cell stream splitting and reconstruction • ICP Cell Insertion & Removal • Cell Rate decoupling • IMA frame synch • Stuffing • Discarding bad-HEC cells • No cell discarding • No cell rate decoupling Interface Specific Transmission Convergence • Cell delineation • Cell scrambling & descrambling • Header error correction • HEC generation & verification • Bit timing • Line coding • Physical Medium Layer Management Functions — • IMA connectivity • ICP cell errors (OIF) • LIF/LODS/RDI-IMA defect processing • RDI-IMA alarm generation • Tx/Rx IMA link state report • • • • Plane Management Functions — IMA group configuration Link addition/removal ATM cell rate change IMA group failure notification • IMA statistics IMA Specific Transmission Convergence Physical — • HEC error indication • LCD-RDI alarm Generation — • LCD failure notification • TC statistics Physical Medium Dependent • Local alarm processing • RDI alarm generation • Link failure notification • PMD state The MPC8280’s IMA microcode alone does not implement all of these functions. Software running on the MPC8280 is responsible for managing the start-up procedure, handling changes in group control, status, and maintaining the Link State Machine and Group State Machine. In general, the MPC8280 IMA microcode implements most of the IMA sublayer user plane functions and provides interrupts/statistics for the layer and plane management functions. The key features of the IMA microcode are: • Supports any FCC with multi-PHY UTOPIA capability • Supports both IMA links and non-IMA links on the same FCC (on a per-PHY basis) • Supports up to 8 IMA groups with one FCC • Supports up to 8 links per IMA group using an internal TC layer hardware • Supports up to 31 links per IMA group using an external TC layer device. Note that a maximum of 31 total links can be supported either on FCC1 or FCC2 but not concurrently on both FCCs) • Performs the following IMA User Plane functions — ATM cell stream splitting and reconstruction — ICP cell insertion/removal--communication of control and framing information — Cell rate decoupling--insertion of ‘filler’ cells when ATM layer cells are unavailable — IMA frame synchronization--finding IMA frame boundaries within links MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-2 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) • • • • • — Stuffing—insertion of ‘stuff’ cells into fast links—in order to maintain an average data rate between links of a group — Discards cells with bad HECs (available on .25µm rev B silicon and forward) Delay synchronization--correlating IMA frames among links of a group Maximum differential delay supported is user-programmable Optionally recovers IMA data clock rate (IDCR) Provides interrupts on errors/state changes Maintains low-level statistic counters — Transmit stuff events — Receive stuff events — Receive ICP violations — Receive Out-of-IMA Frame anomalies 34.1.1 References The features provided by the IMA microcode are driven by The ATM Forum’s IMA specification. The implementation of the IMA microcode is driven by the features, architecture, and resources available on the MPC8280. In addition to published MPC8280 device errata, users should be familiar with the following (available at www.atmforum.com): • The ATM Forum Technical Committee. Inverse Multiplexing for ATM (IMA) Specification Version 1.1 - AF-PHY-0086.001 • The ATM Forum Technical Committee. Inverse Multiplexing for ATM (IMA) Specification Version 1.0 - AF-PHY-0086.000 34.1.2 IMA Versions Supported The IMA microcode supports IMA version 1.0 and version 1.1, with only minor configuration changes. These include the following: • Programming the IMA version encoding in the OAM labels of the transmit ICP and Filler cell templates. • Programming the validated OAM label field in the IMA group receive parameters. 34.1.3 MPC8280 Versions Supported IMA support in ROM is available on the MPC8264 and the MPC8266. On these derivatives of the MPC8280 family, integrated DS1/E1 transmission convergence (TC) layer hardware facilitates HEC checking of received cells. (Refer to Chapter 35, “ATM Transmission Convergence Layer.”) So in these MPC8280 devices, IMA support is available for either the integrated DS1/E1 TC layer or external UTOPIA PHY devices connected via UTOPIA Level 2 multi-PHY. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-3 Inverse Multiplexing for ATM (IMA) 34.1.4 PHY-Layer Devices Supported The IMA microcode is primarily targeted at ATM’s primary application (i.e. IMA over multiple DS1/E1). However, the IMA microcode supports any UTOPIA PHY device which (1) has a constant data rate and (2) can be programmed not to screen out HEC-errorred cells. Most PHYs have this mode available for IMA also. 34.1.5 ATM Features Not Supported The following ATM features are not available for IMA links only, but are available for non-IMA links: • User-defined cells (UDC) (i.e. cells that are not 53 bytes and/or with customized headers) • Internal rate mode for APC scheduling 34.1.6 Additional Impact on MPC8280 Features If the IDCR recovery feature is used, the following are true: • One of the IDMA channels are unavailable, and its resources are dedicated instead to the IDCR master clock function. This can be any IDMA channel (1, 2, 3, or 4). • MPC8280 features sharing the IDMA channel’s parameter RAM page are unavailable. For more detailed information, refer to Section 34.4.8.2, “IDCR FCC Parameter Shadow.” 34.2 IMA Protocol Overview This section describes the IMA protocol, not the MPC8280’s IMA microcode. 34.2.1 Introduction Inverse Multiplexing over ATM (IMA) provides a cost effective solution to carry high speed connections, for example, T3/E3 and OC-3c/STM-1 links, over already installed low speed connections, for example, T1/E1 links, in a flexible way by dynamically adding/removing links as required, depending on the bandwidth required. IMA is defined as transmitting a stream of data over multiple low speed links and recombining the stream in the correct order at the end. IMA involves inverse multiplexing and de-multiplexing of ATM cells in a cyclical fashion among links grouped to form a higher bandwidth logical link whose rate is approximately the sum of the link rates. This is referred to as an IMA group. Figure 34-1 provides a simple illustration of ATM Inverse Multiplexing technique in one direction. This technique applies in the opposite direction. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-4 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) IMA Group TC Physical Link #1 + PHY IMA Group TC + PHY Original ATM Cell Stream to ATM Layer TC + PHY Single ATM Cell Stream from ATM Layer TC Physical Link #2 + PHY TC Physical Link #3 + PHY TC + PHY TC Physical Link #4 + PHY TC + PHY Figure 34-1. Basic Concept of IMA In the transmit direction (near-end), the ATM cell stream received from the ATM layer is distributed on a cell by cell basis, across the multiple links within the IMA group. At the far-end, the receiving IMA unit recombines the cells from each link, on a cell by cell basis, recreating the original ATM cell stream. The aggregate cell stream is then passed to the ATM layer.The IMA protocol enables the demultiplexing/deconstruction (transmit) of an ATM cell stream into multiple links. When receiving, the IMA protocol multiplexes/reconstructs incoming cells from multiple links into the original ATM cell stream. The IMA protocol must compensate for differences in clock rate and delay over the multiple links. 34.2.2 IMA Frame Overview The IMA interface periodically transmits special cells that contain information that permit reconstruction of the ATM cell stream at the receiving end of the IMA virtual link. The receiver end reconstructs the ATM cell stream after accounting for the link differential delays, smoothing CDV introduced by the control cells, etc. These cells, defined as IMA Control Protocol (ICP) cells, provide the definition of an IMA frame. The transmitter must align the transmission of IMA frames on all links (shown in Figure 34-2). This allows the receiver to adjust for differential link delays among the constituent physical links. Based on this required behavior, the receiver can detect the defensible delays be measuring the arrival times of the IMA frames on each link. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-5 Inverse Multiplexing for ATM (IMA) IMA Frame Length = M cells Link 0 ATM ATM ATM F ICP2 F ATM ATM F ICP1 F F ATM F ICP0 Link 1 M-1 F F ICP2 F ATM ATM ATM ICP1 F F F 3 F 2 ICP0 1 F 0 ATM Link 3 ATM ICP2 F F ATM F ICP1 ATM F ATM ATM ICP0 ATM F F ATM: ATM Layer Cell ICPx: IMA Control Protocol Cell F: Filler Cell Figure 34-2. Illustration of IMA Frames At the transmitting end, the cells are transmitted continuously. If there are no ATM layer cells to be sent between ICP cells within an IMA frame, then the IMA transmitter sends filler cells to maintain a continuous stream of cells at the physical layer. The insertion of Filler cells provides cell rate decoupling at the IMA sublayer. The Filler cells should be discarded by the IMA receiver. A new OAM cell is defined for use by the IMA protocol. The cell has codes that define it as an ICP or Filler cell. The data multiplexing performed by IMA is cell-based, where cells are distributed among the links in the IMA group in a round-robin cycle. In order to compensate for different clock rates, IMA must periodically insert ‘stuff’ cells into faster links in order to maintain a consistent average data rate over the links of the group. Furthermore, IMA must compensate for potential differences in delay between the links of the group. Per the IMA specification, the allowable delay differential for DS1/E1 links is 25ms, which at E1 rates is equivalent to approximately 118 cells. The IMA microcode allows the user to define the allowable delay differential via a delay compensation buffer of programmable length. IMA accomplishes these goals by the periodic insertion of special OAM cells, which (among other things) define M-cell frame boundaries, provide frame sequence numbers, and provide stuffing information. This framing information is used by the receiver to correlate the received cell streams and extract cells in-order from the links of the IMA group, thereby reconstructing the original cell stream. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-6 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Link ID #1 Cell n+1 Cell 1 Cell n Cell 4 Cell 3 Cell 2 Cell 1 Phy 1 ATM TX Function IMA TX Function acting as a Virtual PHY Cell 2 Fast Communication Controller Phy 2 Links 1 - N make up an IMA group Link ID #N Cell n Phy n Cell 1 Cell 2 Cell 3 Cell 4 Cell n Cell 1 Cell n+1 Phy 1 ATM RX Function IMA RX Function acting as a Virtual PHY Cell 2 Fast Communication Controller Phy 2 Cell n Phy n Figure 34-3. IMA Microcode Overview 34.2.3 Overview of IMA Cells An IMA frame consists of M number of cells (M = 32, 64, 128, or 256 cells). Each frame consists of ATM data cells and IMA control cells. Two types of IMA control cells are defined by and used by the IMA protocol; IMA Control Protocol (ICP) cells and filler cells. 34.2.3.1 IMA Control Cells There is at least one control cell (IMA Control Protocol) in each frame. An additional ICP cell may be included in a frame to compensate for timing differences between the links in an IMA group (e.g., one link is slightly faster than the other). The insertion of additional ICP cells to compensate for timing differences between links is called a “stuff event”. The transmitter is responsible for inserting “stuff” ICP (SICP) cells and the receiver will monitor for stuff indication and discard SICP cells. The location of the ICP cell in an IMA frame is determined during the IMA start-up sequence. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-7 Inverse Multiplexing for ATM (IMA) IMA Frame Cell n ..... ICP Cell Cell 4 Cell 3 Cell 2 Cell 1 ICP Cell offset should be different for each link. ICP cell offset is determined at start-up. ICP Cell 1-5 Cell Header 6 OAM Label 7 Cell ID 8 IMA 11 12 14 13 10 ICP Link Stat. & IMA G rp. TX cell SI Ctrl CI ID Stat. & timing Ctrl. info offset 9 15 16 17 18-49 50 51 52-53 Link ID FSN end to TX TX RX Link test test test info. X end CRC ctrl ptrn. ptrn ch. PTI/CLP = b1011 HEC = 0x64 Link information for links 0-31 Figure 34-4. IMA Frame and ICP Cell Formats The IMA protocol must compensate for potential differences in delay between the different links of the IMA group. The allowable delay differential for DS1/E1 links is 25ms, which at E1 rates is equivalent to approximately 118 cells. 34.2.3.2 IMA Filler Cells At the transmitting end, cells are transmitted continuously. If there are no ATM layer cells to be sent between ICP cells within an IMA frame, then the IMA transmitter sends filler cells to maintain a continuous stream of cells at the physical layer. The insertion of Filler cells provides cell rate decoupling at the IMA sublayer. The Filler cells should be discarded by the IMA receiver. 34.3 IMA Microcode Architecture This chapter explains the architecture of the receive and transmit IMA microcode tasks. 34.3.1 IMA Function Partitioning The IMA microcode performs only those functions with regular, critical real-time demands. The other functions of IMA (e.g. control and management) are the responsibility of host software. As such, the IMA microcode corresponds primarily to the user plane functions defined in the IMA specification, and software must provide the layer management and plane management functionality. The IMA microcode provides interrupts when interaction with layer management and plane management is required. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-8 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.3.1.1 • • • • • • User Plane Functions Performed by Microcode ATM cell stream splitting and reconstruction ICP cell insertion/removal Cell rate decoupling (i.e. filler cell insertion/removal) IMA frame synchronization Stuffing Discards cells with bad HECs (available on .25µm rev B silicon and forward) 34.3.1.2 Plane Management Functions Performed by Microcode As stated above, most plane management functions must be performed in software. However, certain statistics are intimately related to the lower-level user plane functions, and are thus best provided by the microcode. These include the following: • ICP violations • Transmit stuff events • Receive stuff events 34.3.2 Transmit Architecture This section discusses the behavior of the IMA microcode during transmission, focusing particularly on the independent transmit clock (ITC) mode of IMA. Differences in behavior when common transmit clock (CTC) mode is used are discussed at the end of this section. Only one cell scheduler (known as the ATM pace controller or APC) is used per IMA group. This APC schedules transmission for the IMA group as a single aggregate channel. The APC hands these cells off to the IMA Tx microcode, which distributes these scheduled cells to each of the PHYs in the IMA group. To compensate for clocking differences (jitter and average speed differential), the IMA Tx process distributes ATM cells into N jitter buffers with a depth of 5 cells. The IMA PHYs take cells from these jitter buffers and transmit them. The cell scheduling is triggered by requests from the timing reference link (i.e. assertion of TxClav from the TRL’s PHY). Requests from non-TRL PHYs only interact with the jitter buffer, and perform the stuffing function as needed (when the jitter buffer becomes too shallow). Therefore, the microcode tasks performed in response to TRL PHY requests and non-TRL PHY requests are different. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-9 Inverse Multiplexing for ATM (IMA) APC N times SAR TRL Tx Task Tx Queue Tx Queue Tx Queue Tx Queue Jitter Buffers TRL Tx non-TRL Tx Task UTOPIA Multi-PHY Figure 34-5. IMA Transmit Task Interaction 34.3.2.1 TRL Operation A request from the TRL PHY is used to trigger a complete round-robin process of cell scheduling and distribution, distributing one cell for each of the transmit queues of the N links in the IMA group. For each link, the microcode will: 1. Determine whether an ICP cell or a data/filler cell should be sent for the link: — If data/filler, determine whether link is in ‘active’ or ‘filler-only’ mode — If active, run the APC scheduling algorithm to find the next scheduled ATM channel 2. Distribute either: — An ICP cell — A filler cell (if ‘filler-only’ or ‘active’ with nothing scheduled in the APC) — A data cell (if a channel is scheduled in the APC, performing the appropriate segmentation task for the scheduled ATM channel, as determined by the channel’s AAL type) The cells are distributed by writing the complete cells into circular transmit queues provided per link. These transmit queues function as ‘jitter buffers’, as they are used to decouple the transmit rate of the TRL PHY from the transmit rate of the non-TRL PHYs in the group to allow for clocking differences between the PHYs. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-10 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) At startup, the non-TRL links will transmit filler cells until their transmit queues have reached a minimum depth. In order to maintain less than the specified maximum +/-2.5 cell transmit timing differential (for cells within an IMA frame), the TRL must exhibit the same behavior. Therefore, a 4-cell transmit buffer is also maintained for the timing reference link. The timing reference link will only begin to pass ATM layer cells to its PHY after it has 3 cells in its buffer. Prior to this, it will send filler cells. This behavior will only be experienced at group start-up. The TRL task will also implement the standard amount of stuffing on the TRL link by maintaining a counter. When this task has scheduled (2048/ M) ICP cells for the TRL, a TRL stuff event will be flagged and an indication of an upcoming stuff event will be signaled in the ICP LSI field. If a TRL stuff event is flagged when the TRL task triggers, then a stuff cell will be sent to the TRL’s transmit queue, but no cells will be sent to the transmit queues of the non-TRL PHYs. This forces a standard amount of stuffing on the TRL, thereby reducing the effective data bit rate of the TRL to less than the minimum data clock rate allowed by the clock rate tolerance of the physical-layer standard. Therefore by definition, this effective data bit rate is achievable by the non-TRL links; the non-TRL links can either stuff less (if their data clock rate is slower than the TRL), or stuff more (if their data clock rate is faster than the TRL). 34.3.2.1.1 TRL Service Latency NOTE The functionality described in this section is available only with the latest RAM microcode package. This optional feature allows the user to change the IMA APC behavior upon TRL request. When enabled the TRL request will pass a programmable number of cells to the Tx queue of the links in an IMA group. This can be used in order to suppress the TRL from consuming a large amount of bandwidth before another cell is transmitted. The TRL request normally places a cell in a queue for N links where the group contains N links; after this happens then a non_TRL link is free to pass a cell over the UTOPIA interface. The delay for the TRL can be long and in some cases the TC layer FIFO can underrun. This feature can be used to ensure that TRL and non-TRL requests are handled in the same manner - 1 cell in 1 cell out to the transmit queues. The non-TRL requests will also trigger APC iterations when this feature is enabled. When using this feature, the depth of the TRL transmit queue must equal the non-TRL queues. 34.3.2.2 Non-TRL Operation A request from a non-TRL PHY does not trigger any scheduling task. The cells for non-TRL links will already be supplied (by the TRL task) in its associated transmit queue. The TRL will simply read a cell out of its transmit queue and update the queue pointers. If the transmit queue becomes too shallow (because this link’s request rate is faster than the TRL), the link will flag that a stuff event is imminent. The link will signal an upcoming stuff event in the LSI field of its next ICP cell and will then flag that a stuff event is due. Having flagged this stuff event, the link will continue sending cells from its queue as normal until it reaches its next ICP cell, upon which it indicates a stuff event in the ICP cell and transmits it, but does not update the transmit queue pointers. When the link next requests a cell, the previous ICP cell is repeated (since the queue pointers were not updated). This process causes the transmit queue to deepen to the intended level. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-11 Inverse Multiplexing for ATM (IMA) At group start-up, instead of accessing its transmit queue, the link will send filler cells. This is to allow the transmit queues to reach their target steady-state depth. After the group start-up flag is cleared, normal operation as described above will commence. 34.3.2.3 Transmit Queue Operation Examples (ITC mode) The following diagrams demonstrate the different cases of queue operation, and consequently justify the queue depth of 5 cells. • The extraction pointer points to the queue entry that is currently being supplied to the PHY. This cell must be entirely ready when the PHY requests it. • The insertion pointer points to the queue entry which will be filled next by the TRL process. In the figures, note that the pointers and filled queue locations are just shown with respect to the overall queue depth available with the extraction pointer always shown at the bottom of the queue. This is done only for the purpose of ease of illustration. In reality, the transmit queues are circular queues in which the insertion and extraction pointers are continually rotating through the queue. Tx Queue Queue insertion pointer (Filled by TRL task) Floats between these two positions Depth averages at 3.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Figure 34-6. Transmit Queue Normal Operating State Tx Queue TRL stuff event occurs and this link is not given a cell during a round robin pass. Depth decreases to 2.x “Imminent stuff” flagged Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Queue insertion pointer Stuff event is performed (ICP cell is left in queue after transmission to be sent one extra time.) Depth increases back to 3.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Figure 34-7. Transmit Queue Behavior: Link Clock Rate Same as TRL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-12 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Tx Queue Queue insertion pointer creeps up such that it floats between these two positions (wrapped) Depth is 4.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Queue insertion pointer TRL stuff event happens, so this link is not given a cell during round robin. Depth ratchets down to normal operation of 3.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Figure 34-8. Transmit Queue Behavior: Link Clock Rate Slower than TRL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-13 Inverse Multiplexing for ATM (IMA) Tx Queue TRL stuff event occurs and this link is not given a cell during a round robin pass. Depth decreases to 2.x “imminent stuff” flagged Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Before stuff event can happen, queue depth creeps down below 2.x threshold to 1.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Stuff event occurs, bringing queue depth back to 2.x “imminent stuff’ remains flagged, but Normal ‘Wander zone’ is held off for minimum 5 frames. Queue extraction pointer (Transmitted by non-TRL task) Tx Queue Holdoff expires and stuff event occurs, bringing queue depth back to normal depth of 3.x Normal ‘Wander zone’ Queue extraction pointer (Transmitted by non-TRL task) Figure 34-9. Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case Event Sequence 34.3.2.4 Differences in CTC Operation Overall, CTC operation is similar to ITC operation in task partitioning and overall structure. Differences are as follows: 1. Transmit buffers are still maintained for the non-TRL links, but these buffers will not ‘jitter’, since the transmit clocks are all the same. However, queue depths may vary slightly because PHY requests, while synchronous, will not necessarily come in simultaneously (i.e. may have constant offsets) and will definitely not be serviced simultaneously. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-14 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 2. The non-TRL tasks do not determine when to perform stuffing on the non-TRL links. When the TRL flags ‘imminent stuff’ on its own link, it will flag ‘imminent stuff’ on all of the non-TRL links as well. Thus, the non-TRL links will also stuff their links every 2048 cells. 3. The non-TRL queue depths are the same as the TRL’s queue (i.e. 4 cells). 34.3.3 Receive Architecture The receive task consists of three parts. The first part is for cell reception from the link. The second part provides the trigger for activating the cell processing task, including timing recovery if desired. The third part performs the actual cell processing (i.e. passing cells to the ATM layer). The cell reception task services requests from the links (via the UTOPIA multi-PHY interface and the FCC), maintains the link state, and (if the link and group state dictates) writes the received cells into the link’s delay compensation buffer in external memory. The cell processing activation function coordinates passing cells from the cell reception task, on either an on-demand basis or at a rate determined by the reconstructed IDCR (IMA data cell rate). The cell processing task extracts cells from the delay compensation buffers and passes them to the ATM layer for processing. Cell Processing Task Delay Compensation Buffers Cell Processing Activation Function Cell Reception Task UTOPIA Multi-PHY Figure 34-10. IMA Receive Task Interaction 34.3.3.1 Cell Reception Task In the cell reception task, received ICP cells in which an SCCI change is noted, except for the first ICP received cell, are passed to a user-defined receive AAL0 channel to be processed by software. These MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-15 Inverse Multiplexing for ATM (IMA) received cells (and other event indications) are used by the software to initialize IMA links and groups, and to manage transitions between link and group states. The cell reception task centers around a four-state link state machine. Microcode tasks are performed within each state, but transitions between states are managed by software. The processing of received cells (both ICP cells and data cells) is determined by the state of the link. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-16 Freescale Semiconductor Cell Reception Task - Each IMA Link follows a Four-State Machine Freescale Semiconductor - Received ICP Cell (AAL0 specific channel) are processed by the driver to control the State Machine - According to the Link’s state, the Microcode executes different Tasks Microcode Actions Group Unassigned Configuration to reach to move to next state - Group & Link initialized by the driver based on the ICP content ( Link’s M value, ICP frame format) - screen incoming cells - keep only ICP cells, discard other cells IRLCNTL.GA=1 (Set by the driver) - screen incoming cells - IMA Frame Sequence Number Validation - search for one ICP cell - look for several lCP cells in expected position Link IFSM Unsynchronized IFSW INT generated (IMA_event) to the driver IGRSTATE.GDSS=1 (all links of the Group generated the IFSW INT) - Group achieves delay synchronization - “New Group Link Delay Synchro Algo” Figure 34-11. IMA Microcode: Receive Process Link Delay Unsynchronized MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Set Rx Links/Groups to active mode OR - “Added Link Delay Synchro Algo” either GDS INT in case of Group Start Up Procedure or LDS INT in case of added Link - data ATM cell reception enable No Link Defect Inverse Multiplexing for ATM (IMA) 34-17 Inverse Multiplexing for ATM (IMA) The states are described as follows: • Group Unassigned—This corresponds to a link which is known to be IMA, but for which no information is known (e.g. IMA group number, IMA frame size). In this state, the receive task only screens the incoming cells for ICP cells and discards all others. ICP cells in which an SCCI change is noted are passed to a user-defined receive channel, where software must interpret their content in order to initialize the link and add it to the group. The link transitions to the ‘Link IFSM Unsynchronized’ state when the link’s ‘Group Assigned’ flag is set by software. • Link IFSM Unsynchronized—In this state, the link state machine has not yet found or validated the frame boundary for this link. This state is initially entered after software defines the link’s M value and expected ICP cell format, then sets the ‘Group Assigned’ flag. This state can be subsequently re-entered as the result of a link defect. In this state, the link searches for an ICP cell, then looks for ICP cells in the expected position of subsequent frames in order to validate frame synchronization. Cells other than ICP cells are discarded. When the IFSM becomes synchronized, an interrupt to the host is generated. The link transitions to the ‘Link Delay Unsynchronized’ state when the link’s group and link synchronization flags are set appropriately by software. • Link Delay Unsynchronized—This state contains two separate operations, depending on the state of the group to which the link belongs. If the link enters this state as the result of group start-up, it performs the “new-group link delay synchronization algorithm”. If the link enters this state while the group is already activated (per the link addition/slow recovery (LASR) procedure of the IMA standard), it performs the “added-link delay synchronization algorithm”. As the result of either algorithm, an interrupt will be generated to the host when delay synchronization is achieved. • No Link Defect—This is the state in which normal receive operation occurs after the link has been established and the link-state has been communicated appropriately to the far end. If the link is not inhibited at the group or link level, reception of ATM cells will occur. If the link or group is inhibited, non-ICP received cells will be replaced with filler cells. In the “no link defect” state, cells received (or their replacements) are written to the link’s delay compensation buffer. The link will transition out of this state only as the result of an error or if reset by host software. 34.3.3.2 Cell Processing Activation Function The cell processing activation function operates in two modes. The first, simplest mode is for on-demand cell processing. The second mode is for cell processing as determined by the reconstructed IMA data cell rate, as determined from the recovered receive data clock of the timing reference link (TRL) of the IMA group. 34.3.3.2.1 On-Demand Cell Processing In this mode, the cell processing activation function is null. The cell processing task is triggered directly by the cell reception task if a cell is written to a delay compensation buffer. This mode is strictly demand-driven; there is no attempt to reconstruct an IMA Data Cell Rate (IDCR) from the IMA group at which to process incoming cells. Per the IMA specification, this is allowable under the following conditions: • The IMA receiver is directly built into end equipment that directly terminates the ATM layer (i.e. terminates all ATM connections), and MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-18 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) • The system is only capable of carrying services that either do not require CDV control (e.g. some data services), or where the CDV is handled in some other way (e.g. absorbed in a play-out buffer at the ATM layer connection termination). The MPC8280 may qualify as such a system, if the MPC8280 terminates all ATM connections that it receives. The buffer-descriptors and external memory serve as a play-out buffer. Furthermore, a system which does not terminate cells, but instead passes cells port-to-port, can also use this mode of operation if either of the following conditions are met: • All cell streams are switched at the VC level only, and the VC’s traffic type is one supported by the MPC8280’s APC. In this case, the APC of the MPC8280 can be programmed to appropriately reshape the VC at the egress port, and therefore no cell delay variation (CDV) will be introduced. • Some (or all) cell streams are switched at the VP level, but the switched VPs only carry traffic for which cell delay variation (CDV) within the bounds of an IMA round-robin distribution is tolerable. For example, if the IMA group consists of 8 DS1 links, then the maximum CDV introduced by this method would be 8 cell times, or approximately 2.2ms If the system meets the above qualifications, then this mode of operation is recommended, as it is the simplest and will yield overall better system performance (i.e. this mode requires less CPM processing power). 34.3.3.2.2 IDCR-Regulated Cell Processing In this mode, cell processing is triggered at the recovered IMA data cell rate (IDCR). During group startup, the microcode recovers the PHY clock rate of the TRL from the average period between requests from the TRL PHY. It does this by averaging the difference of timestamps taken from the IDCR master timer whenever the TRL’s PHY is serviced. As part of the group activation process, software calculates the required IDCR request rate (scaling this rate by the number of links in the IMA group and by the 2048/2049 scale factor introduced by stuffing on the TRL), programs it in the IMA group’s associated entry in the IDCR timer table, and enables the group’s IDCR timer table entry. Whenever a link is added or removed from the group, software must update the IDCR timer table entry. The IDCR timer table entries are maintained by the CPM according to the IDCR master timer. For each IDCR master timer tick, the IDCR timer table entries are updated. When an IDCR timer table entry times out, it triggers cell processing for one cell from the delay compensation buffers of its associated IMA group. The timer table entry is then reset according to its IDCR request rate. For this function to operate reliably and regularly, an adequate amount of CPM processing bandwidth must be reserved for the microcode task that services the IDCR timers. If care is not taken with this aspect of system design, then the IDCR task might miss the cell processing of incoming cells, resulting in the eventual overflow of the delay compensation buffers. In order to ensure against this, it is recommended to either (1) program the IDCR to run as a high-priority CPM task, or (2) leave an adequate margin of CPM performance, on the order of 15%. One additional benefit from IDCR-regulated cell processing is the microcode support for IMA group service timeouts. If an active IMA group experiences 3 IDCR tick timeouts without having a data cell available in its delay compensation buffers, then the group is determined to have stalled and an error interrupt is provided to software. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-19 Inverse Multiplexing for ATM (IMA) 34.3.3.3 Cell Processing Task The cell processing task is triggered by the cell processing activation function. When the cell processing task is triggered, it will extract cells in-order from the delay compensation buffers. Cells extracted from the delay compensation buffers are processed per the standard MPC8280 ATM operation (i.e. mapped into ATM channels and processed per the appropriate AAL or OAM function). If the on-demand cell processing activation function is used, then when the cell processing task is triggered, it will extract cells in-order from the delay compensation buffers until either (1) no more are available, or (2) four cells have been extracted. The purpose of limiting the cell processing task to a maximum of four cells is to limit the maximum latency of servicing requests from the external PHYs. Note that, on the average, the receive process will deliver one cell to the ATM layer per cell reception. If the IDCR-regulated processing activation function is used, then one cell will be extracted from the delay compensation buffers of a particular IMA group per timeout of that group’s IDCR timer. 34.4 34.4.1 IMA Programming Model Data Structure Organization Figure 34-12 shows the organization of IMA data structures. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-20 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) IMA Root Table Filler Cell Template IMA Group Tx Table Transmit Queue Info IMA Control Parameter PHY Management IMAEXTBASE IMAGRPT_TX IMAGRPT_RX IMALINKT_TX IMALINKT_RX IRLINKSTAT Group 0 IMA Data Structures DCBs, TX Queue . . . Group 7 IMA Group Rx Table Group 0 External memory (Local or 60x Bus) must be aligned to 1MByte Boundary. . . . Group 7 Link 0 . . . Link 31 IMA Link Rx Table Link 0 IMA Root Table IDCR Table IDCR param. (Optional) IMA Link Receive Statistics Table . . . Link 31 IMA Link Tx Table Internal DPRAM Figure 34-12. IMA Root Table Data Structures The IMA data structures are organized as follows: • Parameters at the FCC level determine common ATM parameters and location of the IMA Root Table • IMA Root Table includes parameters that are used by all IMA links of this FCC • IMA Group Receive Table and IMA Group Transmit Table entries include parameters that define the receive and transmit states and settings of the associated IMA group • IMA Link Receive Table and IMA Link Transmit Table entries include parameters that define the receive and transmit states and settings of the associated IMA link • Optional IDCR Table that contains IDCR timers for the IMA groups MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-21 Inverse Multiplexing for ATM (IMA) 34.4.2 34.4.2.1 34.4.2.1.1 IMA FCC Programming FCC Registers FPSMRx The FCC protocol-specific mode register (FPSMR) for ATM operation is described in Section 31.13.2, “FCC Protocol-Specific Mode Register (FPSMR).” Refer to that section for information pertaining to IMA. 34.4.2.1.2 FTIRRx For any PHY programmed in IMA mode (i.e. corresponding bit in IMAPHY is set), the corresponding FTIRRx must be programmed to zero, for external rate mode. However, for PHYs 0-3, internal rate mode may be selected for non-IMA PHYs. Refer to Section 31.15.1.1, “FCC Transmit Internal Rate Register (FTIRRx).” 34.4.2.2 34.4.2.2.1 FCC Parameters TCELL_TMP_BASE and RCELL_TMP_BASE The TCELL_TMP_BASE and RCELL_TMP_BASE have the same definitions as for a standard FCC, in that they contain 64-byte aligned addresses of regions of DPRAM for temporary cell storage. However, the 4 bytes leading and 4 bytes following the region indicated by TCELL_TMP_BASE must also be reserved for use by the IMA microcode (thereby increasing its size to 60 bytes); and the 12 bytes following the region indicated by RCELL_TMP_BASE must also be reserve for use by the IMA microcode (thereby increasing its size to 64 bytes). RCELL_TMP_BASE may be programmed to any 64-byte aligned address. TCELL_TMP_BASE must be programmed to a 64-byte aligned address terminating with 0x40 (i.e. 0xnn40). 34.4.2.2.2 GMODE IMA functionality in ROM is enabled using the GMODE register. Refer to Section 31.10.1.3, “Global Mode Entry (GMODE).” 34.4.2.3 IMA-Specific FCC Parameters The following parameter must be programmed in the FCC parameter RAM page in addition to the standard FCC parameters for ATM. Table 34-2. FCC Parameter RAM Additions Offset 0xEE Name IMAROOT Width Hword Description Offset of IMA root table in DPRAM. Must be 128-byte aligned. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-22 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) NOTE IMAROOT must be programmed to a 128-byte aligned address terminating with 0x80 (i.e. 0xnn80). 34.4.3 Offset 0x04 0x00– 0x2F IMA Root Table Table 34-3. IMA Root Table1 Name IMAFILLERHD2 IMAFILLERPLD Width 4 Bytes Description Filler cell template. Used by microcode in transmission of filler cells. The cell is formatted as byte-swapped, and additionally the header is 48 Bytes bitswapped. [This is due to hardware implementation, and does not imply the order of the transmission of the cell. The transmission of the cell is per the ATM standard.] Content should be: 0xD0000000 (header) 0x6A6A0001 or 0x6A6A0003 (for IMA Version 1.0 or 1.1) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0x6A6A6A6A (padding) 0xC6026A6A or 0xD9026A6A (for IMA Version 1.0 or 1.1) Byte Byte Byte Tag indicating that the filler template is a filler cell. Program to zero. Transmit queue size. Recommended value is 0x18. Must be a multiple of 4. Refer to Section 34.4.6.1, “Transmit Queues for more details Transmit queue target level. Recommended value is 0x0C. Must be a multiple of 4. Transmit queue stuff threshold. Recommended value is 0x0C. Must be a multiple of 4. Reserved. IMA control parameter. Controls functions shared by all IMA groups for this FCC. Microcode managed parameter (pass count). Receive PHY enable. Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0). Setting a bit enables reception for the corresponding PHY. Must be used to enable/disable the corresponding PHY regardless of whether or not the PHY is defined as IMA in IMAPHY. All cells received by disabled PHYs are discarded. Note that the FCC must also be enabled in GFMR[ENR] for reception to occur. Bit 31 is reserved, and must be programmed to zero. 0x30 0x31 0x32 0x33 0x34 0x36 0x37 0x38 FILLTAG TQ_SIZE TQ_TARGET TQ_THRESHOLD Byte RESERVED IMACNTL TMP_PCNT RXPHYEN Hword Byte Byte Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-23 Inverse Multiplexing for ATM (IMA) Table 34-3. IMA Root Table1 (continued) Offset 0x3C Name TXPHYEN Width Word Description Transmit PHY enable. Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0). Setting a bit enables transmission for the corresponding PHY. Must be used to enable/disable the corresponding PHY regardless of whether or not the PHY is defined as IMA in IMAPHY. Only idle/unassigned cells are transmitted on disabled PHYs. Note that the FCC must also be enabled in GFMR[ENT] for transmission to occur. Bit 31 is reserved, and must be programmed to zero. Bit array addressed by PHY address (e.g. bit 0 corresponds to PHY 0). Setting a bit defines the corresponding PHY to operate in IMA mode. Clearing a bit defines the corresponding PHY to operate as a normal (non-IMA) multi-PHY. Bit 31 is reserved, and must be programmed to zero. IMA external structure base pointer. Points to region in external memory where external IMA data structures are located. Must be aligned to a 1MB boundary (i.e. program bits 12-31 to zero). Offset of IMA group transmit table in DPRAM. Must be 16-byte aligned. Offset of IMA group receive table in DPRAM. Must be 64-byte aligned. Offset of IMA link transmit table in DPRAM. Must be 32-byte aligned. Offset of IMA link receive table in DPRAM. Must be 32-byte aligned. Offset of the optional IMA link receive statistics table in DPRAM. Must be 8-byte aligned. Microcode-managed parameter. Temporary storage of link table pointer. Microcode-managed parameter. Temporary transmit table pointer. Microcode-managed parameter. Temporary transmit group pointer. Microcode-managed parameter. Temporary transmit group order pointer. Microcode-managed parameter. Temporary receive group pointer. Microcode-managed parameter. Temporary return pointer. Microcode-managed parameter. Temporary receive group pointer 2. Refer to Section 34.4.8, “IDCR Timer Programming,” for more details Reserved. Must be programmed to zero during initialization. Required for optional TRL Service Latency enhancement only. IMA Temp Group Order - Points to the base of a 2byte temp pointer storage per group. Software initialized before FCC is enabled. Microcode managed parameter. Reserved. Must be programmed to zero during initialization. 0x40 IMAPHY Word 0x44 IMAEXTBASE Word 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0x5A 0X5C 0x5E IMAGRPT_TX IMAGRPT_RX IMALINKT_TX IMALINKT_RX IRLINKSTAT TMP_LPTR_RX TMP_LPTR_TX TMP_GPTR_TX Hword Hword Hword Hword Hword Hword Hword Hword TMP_GPORD_TX Hword TMP_GPTR_RX TMP_RTRN_RX Hword Hword TMP_GPTR2_RX Hword — — Hword 0x60–0x68 IDCR ROOT PARAMETERS 0x68 0x6C — ITPGRPO 0x6E–0x7 F 1 — — Boldfaced entries in the above table indicate parameters which must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 2 IMAFILLERHD is located at the word which immediately precedes the 128-byte aligned region defined by IMAROOT. Thus it is located at offset - 0x04 from base of IMAROOT table. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-24 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.3.1 IMA Control (IMACNTL) The fields of the IMACNTL are shown in Figure 34-13. 0 1 2 3 4 5 6 7 Field — IRSE IQB DSB — INTQ Figure 34-13. IMA Control (IMACNTL) Table 34-4 describes the IMACNTL bit fields. Table 34-4. IMACNTL Field Descriptions Bits 0–1 2 — IRSE Name Reserved IMA link receive statistics enable. If link receive statistics gathering is disabled, there is no need to initialize IRLINKSTAT or reserve space for the receive statistics table. 0 Link receive statistics gathering is disabled. 1 Link receive statistics gathering is enabled. Interrupt queue bus. Defines on which bus the IMA interrupt queue is located. 0 On the 60x bus. 1 On the local bus. Data structure bus. Defines on which bus the IMA external structure memory area is located. 0 On the 60x bus. 1 On the local bus. Reserved. Number of the ATM interrupt queue dedicated to IMA events. Note that these do not include ICP cell reception events; the handling of ICP cell reception events is programmed in the RCT of the ICP channel defined by RICPCH. Description 3 IQB 4 DSB 5 6–7 — INTQ 34.4.4 IMA Group Tables The IMA group tables consist of multiple IMA group structures indexed by group number, which ranges from 0 to 7. The transmit and receive parameters are located in separate tables. The IMA group transmit table entries are 16 bytes long. The IMA group receive table entries are 64 bytes long. However, there is no need to reserve memory space in DPRAM for 8 receive IMA groups if less than 8 IMA groups are required. To conserve memory space used by these tables, it is best to add groups starting from group zero. Note also that group number is independent of the assignment of IMA ID. 34.4.4.1 IMA Group Transmit Table Entry Table 34-5. IMA Group Transmit Table Entry 1 Offset 0x00 0x01 Name IGTCNTL IGTSTATE Width Byte Byte Description IMA group transmit control parameters. IMA group transmit state. Microcode-managed parameter. Must be initialized to zero at group start-up. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-25 Inverse Multiplexing for ATM (IMA) Table 34-5. IMA Group Transmit Table Entry (continued)1 Offset 0x02 0x04 Name TGRPORDER TVPHYNUM Width Hword Byte Description Offset of transmit group order table in DPRAM. Can be changed on the fly. Transmit Virtual PHY number. Maps this IMA transmit group to a virtual PHY number for the purpose of selecting an ATM pace controller (APC) table number for this IMA group. Note that this parameter must be unique; it must not conflict with the PHY number of any non-IMA PHYs or with the TVPHYNUM of any other IMA group. If there are any PHY numbers which will never be used in a system (i.e. the actual PHY with the address does not exist), then TVPHYNUM should be selected from one of these PHYs. If no such PHY numbers are available (i.e. the multi-PHY interface consists of the full 31 PHYs), then select TVPHYNUM from one of the PHY numbers of the PHYs within this IMA group. Transmit IMA Frame Sequence Number (IFSN). Microcode-managed parameter. Increments each time an IMA frame is transmitted, cycling from 0 through 255. Should be initialized to zero at group start-up. Transmit IMA M counter. Microcode-managed parameter. Tracks IMA frame boundaries. Increments once per round-robin distribution of cells to the transmit queues, cycling from 0 through M. Initialize to zero at group startup. TRL stuff frame counter. Microcode-managed parameter. Controls required stuffing on the TRL. Decrements each time an ICP cell is sent on the TRL, cycling from TRLSTFN through 0. A TRL stuff event occurs when it reaches zero. Initialize to the value of TRLSTFN at group start-up. Offset of transmit ICP cell payload template area in DPRAM. Must be 64-byte aligned. This parameter and the associated template area may only be changed when IGCNTL[ICPC]=IGTSTATE[ICPCA]. After changing TICPPTR, IGCNTL[ICPC] must be toggled. Transmit IMA frame size. Program to 31, 63, 127, or 255 for frame sizes (M) of 32, 64, 128, or 256, respectively. TRL stuff frame number. Defines the number of IMA frames sent between TRL stuff events. For ITC operation IGTCNT[CTC] = 0, program TRLSTFN = 2048/M. For CTC operation IGTCNT[CTC] = 1, program TRLSTFN = (2048/M) – 1. Refer to Section 34.4.4.1.1, “IMA Group Transmit Control (IGTCNTL)." Number of transmit links in the IMA group that are in the active state (ILTCNTL[TXSC]=01). Used by the APC to scale the rescheduling parameters appropriately when rescheduling channels. Real time-stamp subcounter. Microcode-managed parameter, used by the APC. Initialize to zero at group start-up. Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells Counter - Number of cells passed to the groups links upon request. Initialize to IASNC. Required for optional TRL Service Latency enhancement only. IMA APC Scheduled Number of Cells - reset for IASNCtr. Number of cells passed to the groups links upon request. Recommended value is 1. 0x05 TIFSN Byte 0x06 TMCTR Byte 0x07 TRLSTFCNT Byte 0x08 TICPPTR Hword 0x0A 0x0B TM TRLSTFN Byte Byte 0x0C TNUMLINKS Byte 0x0D 0x0E RTSTPCNT IASNCCtr Byte Byte 0x0F IASNC Byte 1 Boldfaced entries must be initialized by the user. All other parameters initialize to zero. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-26 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.4.1.1 IMA Group Transmit Control (IGTCNTL) The fields of the IGTCNTL register are shown in Figure 34-14. 0 2 3 4 5 6 7 Field — TXSC ISIE CTC ICPC Figure 34-14. IMA Group Transmit Control (IGTCNTL) Table 34-6 describes the IGTCNTL bit fields. Table 34-6. IGTCNTL Field Descriptions Bits 0–2 3–4 — TXSC Name Reserved Transmit status/control. Sets the transmit mode of the IMA group. 00 Filler mode. The IMA group transmits only ICP and filler cells, no data cells. 01 Active mode. The IMA group is capable of sending data cells. 1X Reserved. Required for optional TRL Service Latency enhancement only. IMA Scheduler Split Iterations Enable 0 - APC is not split, TRL completes round robin distribution of cells. 1 - APC split, both TRL and non-TRL requests distribute cells to the transmit queues. Transmit clock mode for this IMA group. 0 Independent transmit clock (ITC) mode. 1 Common transmit clock (CTC) mode. ICP change flag. Maintains at least the minimum 2-frame spacing of ICP cell control/status changes. Initialize to zero at group start-up. Must be toggled by software whenever TICPPTR is changed. After two subsequent IMA frames are transmitted, the IGTSTATE[ICPCA] field will be changed to match IGTCNTL[ICPC]. When IGTCNTL[ICPC] equals IGTSTATE[ICPCA], changes to TICPPTR are allowed. Description 5 ISIE 6 CTC1 7 ICPC 1Ensure transmit clock mode is not changed during IMA group startup to avoid erratic behavior. 34.4.4.1.2 IMA Group Transmit State (IGTSTATE) The fields of the IGTSTATE register are shown in Figure 34-15. 0 1 2 3 4 5 6 7 Field TSTF TIMSTf GTE TRQS ELX — ICH ICPCA Figure 34-15. IMA Group Transmit State (IGTSTATE) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-27 Inverse Multiplexing for ATM (IMA) Table 34-7 describes the IGTSTATE bit fields. Table 34-7. IGTSTATE Field Descriptions Bits 0 1 Name TSTF TIMSTF Description TRL stuff flag. Microcode-managed parameter. Indicates that the next ICP cell on the TRL will be part of a stuff event. Initialize to zero at group startup. TRL imminent stuff flag. Microcode-managed parameter. Indicates that an upcoming stuff event will be signalled in the next ICP of the TRL (via LSI=001). Initialize to zero at group startup. Go to end flag - TRL has requested 2 times before round robin distribution has completed or link will underrun and is still due a cell from round robin distribution. Microcode managed parameter initialize to 0. Used for optional TRL Service Latency enhancement only. TRL Request - TRL has requested therefore 1 round robin distribution of cells and is yet to be completed. Microcode managed parameter initialize to 0. Used for optional TRL Service Latency enhancement only. Early exit flag. Microcode-managed parameter. Initialize to zero at group startup. Reserved ICP change holdoff. Microcode-managed parameter. Initialize to zero at group startup. ICP change allowed flag. Microcode-managed parameter. See description of IGTCNTL[ICPC]. 2 GTE 3 TRQS 4 5 6 7 ELX — ICH ICPCA 34.4.4.1.3 Transmit Group Order Table The transmit group order table defines the order of the links in the round-robin distribution of cells to the links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each byte providing the PHY address of its associated link. The end of the table is indicated by an entry programmed to 0x1F. This table alone defines the order of cell distribution. It is the responsibility of software to program the LID of the links in the IMA Link Table entries, and to program the group order table such that its order corresponds to the order of increasing LIDs within the group. The format of a transmit group order table entry is shown in Figure 34-16. 0 2 3 7 Field — PHY ADDRESS Figure 34-16. Transmit Group Order Table Entry Table 34-8 describes the format of a transmit group order table entry. Table 34-8. Transmit Group Order Table Entry Field Descriptions Bits 0–2 3–7 — PHY ADDRESS Name Reserved PHY address (Up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin. A value of 0x1F in this field indicates the end of the group order table. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-28 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.4.1.4 ICP Cell Templates The ICP cell templates are areas of memory provided by software to the microcode for construction of ICP cells for transmission. Software prepares the fields which are common to the group (i.e. class B, C, D, and E parameters). The other (class A) parameters will be written to the appropriate fields by the microcode. The template is 53 bytes long and must be aligned on a 64-byte boundary. Table 34-9 describes the format of a group order table entry. The ICP cell template is formatted as byte-swapped, and additionally the ICP cell header is bitswapped. [This is due to hardware implementation, and does not imply the order of transmission of the cell. The transmission of the cell is per the ATM standard.] Reflecting this byte-swap, the offset column gives the offset in DPRAM from the ICP template base. Table 34-9. ICP Cell Template 1 Offset 0x00 0x04 0x05 0x06 0x07 Name ICP CELL HEADER ICP Cell Offset IMA Frame Sequence Number Cell ID and Link ID OAM LABEL Width Word Byte Byte Byte Byte Description ICP cell header. Program to 0xD0000000. Microcode-managed area. Microcode will program this field dynamically. Microcode-managed area. Microcode will program this field dynamically. Microcode-managed area. Microcode will program this field dynamically. IMA Version value. 1 IMA Version 1.0 3 IMA Version 1.1 Bits 7-4: Group State 0000 = Start-up, 0001 = Start-up-Ack, 0010 = Config-Aborted - Unsupported M, 0011 = Config-Aborted - Incompatible Group Symmetry, 0100 = Config-Aborted - Unsupported IMA Version, 0101, 0110 = Reserved for other Config-Aborted reasons in a future version of the IMA specification, 0111 = Config-Aborted - Other reasons, 1000 = Insufficient-Links, 1001 = Blocked, 1010 = Operational, Others: Reserved for later use in a future version of the IMA specification. Bits 3-2: Group Symmetry Mode 00 = Symmetrical configuration and operation, 01 = Symmetrical configuration and asymmetrical operation (optional), 10 = Asymmetrical configuration and asymmetrical operation (optional), 11 = Reserved Bits 1-0: IMA Frame Length (00: M=32, 01: M=64, 10: M=128, 11: M=256) Bits 7-0: IMA ID 0x08 GROUP STATUS AND CONTROL Byte 0x09 IMA ID Byte MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-29 Inverse Multiplexing for ATM (IMA) Table 34-9. ICP Cell Template (continued)1 Offset 0x0A Name STATUS AND CONTROL CHANGE INDICATION (SCCI) Link Stuff Indication RX TEST PATTERN TX TEST PATTERN TX TEST CONTROL Width Byte Description Software must increment this field in the new ICP template whenever a new ICP template is created. Microcode-managed area. Microcode will program this field dynamically. Bits 7-0: Rx Test Pattern (value from 0 to 255) Bits 7-0: Tx Test Pattern (value from 0 to 255) Bits 7-6: Unused and set to 0 Bit 5: Test Link Command (0: inactive, l: active) Bits 4-0: Tx LID of test link (0 to 31) Bits 7-6: Unused and set to 0 Bit 5: Transmit Clock Mode: (0: ITC mode, 1: CTC mode) Bits 4-0: Tx LID of the timing reference (0 to 31) Status and control of link with LID = 3 Status and control of link with LID = 2 Status and control of link with LID = 1 Status and control of link with LID = 0 Status and control of link with LID = 7 Status and control of link with LID = 6 Status and control of link with LID = 5 Status and control of link with LID = 4 Status and control of link with LID = 11 Status and control of link with LID = 10 Status and control of link with LID = 9 Status and control of link with LID = 8 Status and control of link with LID = 15 Status and control of link with LID = 14 Status and control of link with LID = 13 Status and control of link with LID = 12 Status and control of link with LID = 19 Status and control of link with LID = 18 Status and control of link with LID = 17 Status and control of link with LID = 16 Status and control of link with LID = 23 Status and control of link with LID = 22 0x0B 0x0C 0x0D 0x0E Byte Byte Byte Byte 0x0F TRANSMIT TIMING INFORMATION LINK 3 INFO LINK 2 INFO LINK 1 INFO LINK 0 INFO LINK 7 INFO LINK 6 INFO LINK 5 INFO LINK 4 INFO LINK 11 INFO LINK 10 INFO LINK 9 INFO LINK 8 INFO LINK 15 INFO LINK 14 INFO LINK 13 INFO LINK 12 INFO LINK 19 INFO LINK 18 INFO LINK 17 INFO LINK 16 INFO LINK 23 INFO LINK 22 INFO Byte 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-30 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-9. ICP Cell Template (continued)1 Offset 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x32 0x33 0x34 1 Name LINK 21 INFO LINK 20 INFO LINK 27 INFO LINK 26 INFO LINK 25 INFO LINK 24 INFO LINK 31 INFO LINK 30 INFO LINK 29 INFO LINK 28 INFO CRC10 END-TO-END CHANNEL UNUSED TAG Width Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Hword Byte Byte Byte Description Status and control of link with LID = 21 Status and control of link with LID = 20 Status and control of link with LID = 27 Status and control of link with LID = 26 Status and control of link with LID = 25 Status and control of link with LID = 24 Program to 0x00. Status and control of link with LID = 30 Status and control of link with LID = 29 Status and control of link with LID = 28 Microcode-managed area. Microcode will program this field dynamically. Program to any value desired for end-to-end implementation-dependent signalling, or program to 0x00 if unused. Program to 0x6A. Internally-used tag value indicating that this is an ICP cell. Program to 0x80. Boldfaced entries in the above table indicate parameters which must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 34.4.4.2 IMA Group Receive Table Entry Table 34-10. IMA Group Receive Table Entry 1 Offset 0x00 0x01 0x02 0x03 Name IGRCNTL IGRSTATE RIMAID IMAVER Width Byte Byte Byte Byte Description IMA group receive control parameters. IMA group receive state. Microcode-managed parameter. Initialize to zero at group startup. Receive IMA ID. Program to the validated receive IMA ID value. IMA version. Program to the validated IMA version value. 1 IMA Version 1.0 3 IMA Version 1.1 Receive IMA frame size. Program to 31, 63, 127, or 255 for frame sizes of 32, 64, 128, or 256, respectively. Number of receive links in the IMA group that are in the active state (ILRCNTL[RXSC]=01. Current cell (x out of RM cells in a Frame) being processed by the reconstruction routine. Microcode-managed parameter. Initialize to zero at group startup. 0x04 0x05 0x06 RM RNUMLINKS DCB_RM Byte Byte Byte MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-31 Inverse Multiplexing for ATM (IMA) Table 34-10. IMA Group Receive Table Entry (continued)1 Offset 0x07 0x08 RSCCI DCBLNK Name Width Byte Hword Description Receive IMA SCCI field. Microcode-managed parameter. Holds the SCCI value of the last ICP cell received by this group. Pointer to link entry in group order table currently in use. Microcode-managed parameter. Initialize to value of RGRPORDER0 at group startup. Delay-compensation buffer extraction pointer. Microcode-managed parameter. Initialize to zero at group startup. Number of IDCR or On-demand requests made for which there were no cells available in a link’s DCB. Microcode managed parameter. Initialize to zero at group startup. Identifies the IFSN of the frame being processed by the “reconstruction” routine. Microcode managed parameter. Pointer to the start of the current frame being processed by the “reconstruction” routine. Microcode managed parameter. Initialize to zero at group startup. Offset of receive group order table 0 in DPRAM. Offset of receive group order table 1 in DPRAM. Alpha and beta parameters for IMA frame synchronization mechanism (IFSM). Bits 0-3: Alpha. Allowable range is 1-2; typical value is 2. Bits 4-7: Beta. Allowable range is 1-5; typical value is 2. Gamma parameter for IMA frame synchronization mechanism (IFSM). Allowable range is 1-5; typical value is 1. TRL rate. Used only when IDCR-regulated cell processing is used (i.e. IGRCTNL[IDCR]=1). Calculated by microcode during group startup, prior to group activation. Referenced by software in order to program the IDCRREQ and IDCRREQF of the group’s IDCR table entry. Value is valid after IGRSTATE[IDCR_DN] is set by the microcode. Bit array identifying which of the links (i.e., PHY) in this group are enabled. Bit 0 corresponds to PHY 0, bit 30 corresponds to PHY 30. Software must set the corresponding bits to 1 so that the delay compensation process for the link(s) is started. Bit array identifying which of the links in this group has received an ICP cell. A “1” in the corresponding link’s bit position indicates that an ICP cell has been received. Microcode-managed parameter. Initialize to zero at group startup. Bit array identifying which of the links in this group has started storing cells to its corresponding DCB. A “1” in the corresponding link’s bit position indicates that cells have been stored in the DCB. Microcode-managed parameter. Initialize to zero at group startup. 0x0A 0x0C DCBX STALL_COUNT Hword Byte 0x0D 0x0E REF_IFSN GFP Byte Hword 0x10 0x12 0x14 RGRPORDER0 RGRPORDER1 ALPHABETA Hword Hword Byte 0x15 0x16 GAMMA TRLR Byte Hword 0x18 REF_LINK Word 0x1C LINK_ICP Word 0x20 LINK_DCB Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-32 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-10. IMA Group Receive Table Entry (continued)1 Offset 0x24 Name LINK_LD Width Word Description Bit array identifying which of the “added” links in this group has a Longer propagation Delay (LD) than any of the existing links. A “1” in the corresponding link’s bit position indicates that it has a longer propagation delay. Microcode-managed parameter. Initialize to zero at group startup. Number of cells received on the TRL while in the Group Delay Sync. stage. Used only when IDCR-regulated cell processing is used (i.e. IGRCTNL[IDCR]=1). Used for determining TRLR. When CELL_COUNT = 128, TRLR is calculated and can be used for programming IDCR timer values. Microcode-managed parameter. Initialize to zero at group startup. Receive Virtual PHY number. Maps this IMA receive group to a virtual PHY number for the purpose of address mapping of received cells. Note that this parameter must be unique; it must not conflict with the PHY number of any non-IMA PHYs or with the RVPHYNUM of any other IMA group. If there are any PHY numbers which will never be used in a system (i.e. the actual PHY with the address does not exist), then RVPHYNUM should be selected from one of these PHYs. If no such PHY numbers are available (i.e. the multi-PHY interface consists of the full 31 PHYs), then select RVPHYNUM from one of the PHY numbers of the PHYs within this IMA group. Stall threshold. Used to detect stalled links when performing round-robin cell extraction from the delay compensation buffers (Dcbz). This is the number of cells which may be received without advancing the cell extraction pointer. The value is application-dependent and must be tuned by the user to the “expected worst case.” Its value depends on the depth of queues and FIFOs in the complete transmit/receive path, and the ’burstiness’ of the behavior of the FIFOs. Assuming very bursty FIFOs, it is approximately: STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO) where: a) RNUMLINKS is the number of links in the receive group order structure (regardless of link status). b) RX_FIFO is the depth of the receive FIFOs of the TC layer. c) 3 is the rounded value of the allowed transmit skew between links of a group (2.5, per the IMA standard). An optimal value for STALL_THR will be great enough to produce no link stall events in normal operation, but low enough to detect a failed link as quickly as possible. IMA Receive Group Frame Size Bits 0-5: Reserved Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field (Bits 1:0) which determine the IMA frame size. This field must be programmed before links in the group are assigned Reserved. Must be initialized to zero at group startups. 0x28 CELL_COUNT Byte 0x29 RVPHYNUM Byte 0x2A STALL_THR Byte 0x2B IRGFS Byte 0x2C — Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-33 Inverse Multiplexing for ATM (IMA) Table 34-10. IMA Group Receive Table Entry (continued)1 Offset 0x30 Name LINK_DCBO Width Word Description Link DCB overflow interrupt indication. Bit array identifying which links have issued a link DCB overflow (DCBO) interrupt. This parameter ensures that only one DCBO interrupt is generated per event. Microcode managed parameter. Initialize to zero at group startup. Reserved. Must be initialized to zero at group startups. 0x34– 0x3F 1 — 3 Words Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 34.4.4.2.1 IMA Group Receive Control (IGRCNTL) The fields of the IGRCNTL register are shown in Figure 34-17. 0 1 2 3 4 5 6 7 Field GOTP — RXSC IDCR — Figure 34-17. IMA Group Receive Control (IGRCNTL) Table 34-11 describes the IGRCNTL bit fields. Table 34-11. IGRCNTL Field Descriptions Bits 0 Name GOTP Description Group order table pointer. Defines which group order table pointer (RGRPORDER0 or RGRPORDER1) will be used for the cell extraction round-robin. Initialize to zero at group startup. Reserved, initialize to zero. Receive status/control. Sets the receive mode of the IMA group. 00 Filler mode. The IMA group processes only ICP cells. Data cells are replaced with filler cells. 01 Active mode. The IMA group is capable of receiving data cells. 1X Reserved. Defaults to Filler Mode. IDCR recovery enable. Selects the mode of the receive process activation function. 0 On-demand cell processing 1 IDCR-regulated cell processing Reserved, initialize to zero. 1–2 3–4 — RXSC 5 IDCR 6–7 — 34.4.4.2.2 IMA Group Receive State (IGRSTATE) The fields of the IGRSTATE register are shown in Figure 34-18. 0 1 2 3 7 Field IDCR_DN GDSS — Figure 34-18. IMA Group Receive State (IGRSTATE) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-34 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-12 describes the IGRSTATE bit fields. Table 34-12. IGRSTATE Field Descriptions Bits 0 Name IDCR_DN Description IDCR Done. Microcode-managed parameter. When this bit is set by the microcode, the TRLR value is valid and can be used to program the IDCR timer entry values for this group. Initialize to zero at group startup. Group delay synchronization state. Initialize to zero at group startup. Must be changed by software to 01 after sufficient links have achieved frame synchronization. Subsequently managed by microcode. 00 Group delay synchronization process inhibited. 01 Group delay synchronization process enabled. 10 Group delay synchronization process in progress. 11 Group delay synchronized. Refer to Section 34.5.4.10, “Receive Event Response Procedures". Reserved, initialize to zero. 1–2 GDSS 3–7 — 34.4.4.2.3 IMA Receive Group Frame Size The fields of the IRGFS register are shown in Figure 34-19. 0 1 6 7 Field 0 — GSC-M Figure 34-19. IMA Receive Group Frame Size (IGRSTATE) Table 34-13 describes the IRGFS bit fields. Table 34-13. IRGFS Field Descriptions Bits 0 1–5 6–7 0 — GSC-M Name Reserved, initialize to zero. Reserved, initialize to zero. IMA Receive Group Frame Size Bits 0-5: Reserved Bits 6-7 - GSC_M: Value of received ICP cell Group Status Contl field (Bits 1:0) which determine the IMA frame size. This field must be programmed before links in the group are assigned Description 34.4.4.2.4 Receive Group Order Tables The receive group order tables define the order of the links in the round-robin extraction of cells to the links of the IMA group. The table consists of an array of bytes ordered from first link to last link, with each byte providing the PHY address of its associated link. The end of the table is indicated by an entry programmed to 0x1F. Two group order tables are used in order to allow for on-the-fly changes (i.e. to add or remove links), while making certain that the changes only occur at the end of a round-robin cycle. IGRCNTL[GOTP] indicates which group order table pointer (and therefore, group table) is currently in use. Changes should be made MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-35 Inverse Multiplexing for ATM (IMA) to the group order table not in use, and then IGRCNTL[GOTP] should be toggled. When the current round-robin cell extraction process completes, the next process will use the new table. This table alone defines the order of cell extraction from the delay compensation buffers. It is the responsibility of software to read the LIDs of the links in the group from the received ICP cells during group startup, and to program the group order table such that its order corresponds to the order of increasing LIDs within the group. The format of a receive group order table entry is shown in Figure 34-20. 0 2 3 7 Field — PHY ADDRESS Figure 34-20. Receive Group Order Table Entry Table 34-14 describes the format of a receive group order table entry. Table 34-14. Receive Group Order Table Entry Field Descriptions Bits 0–2 3–7 — PHY ADDRESS Name Reserved, initialize to zero. PHY address (up to 31 PHYs[0–30]) of the link transmitting in this position in the round-robin. A value of 0x1F in this field indicates the end of the group order table. Description 34.4.5 IMA Link Tables The IMA link tables consist of multiple IMA group structures indexed by the PHY address of their corresponding PHYs. The transmit and receive parameters are located in separate tables. The IMA group transmit and receive table entries are each 32 bytes long. Note that to conserve memory space consumed by these tables, it is best to group the addresses of the PHYs that are assigned as IMA. [For example, if out of eight total links only four are IMA, then optimally these would be links 0 through 3.] 34.4.5.1 IMA Link Transmit Table Entry Table 34-15. IMA Link Transmit Table Entry 1 Offset 0x00 0x01 0x02 Name ILTCNTL ILTSTATE LICPOS Width Byte Byte Byte Description IMA link transmit control parameters. IMA link transmit state. Microcode-managed parameter. Initialize to zero at link startup. Link ICP offset. Determines the position of the ICP cell within the IMA frame. Program in the range 0 to M-1. See the IMA specification for recommended methods for programming this field. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-36 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-15. IMA Link Transmit Table Entry (continued)1 Offset 0x03 ILID Name Width Byte Description IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell. Bit 0: 1 (indicating ICP cell) Bits 1-2: Not Used, set to zero Bits 3-7: Program to software-assigned LID. [Note: This value is only used by microcode to format ICP cells for this link, it is not used to determine round-robin transmission order. That function is performed by the group order table.] IMA transmit stuff event counter. While ILTCNTL[SES]=0, increments each time a stuff event is performed on this link. Initialize to zero at link startup. IMA link transmit queue start pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Refer to Section 34.4.6.1, “Transmit Queues". IMA link transmit queue end pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Points to the last cell in the transmit queue. Program this parameter to ITQSP+TQ_SIZE-4. Refer to Section 34.4.6.1, “Transmit Queues". IMA link transmit queue fill pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Initialize this to the value of ITQSP. Refer to Section 34.4.6.1, “Transmit Queues". IMA link transmit queue extract pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Initialize this to the value of ITQSP. Refer to Section 34.4.6.1, “Transmit Queues“. IMA transmit interrupt mask. Has the same format as the upper byte of the IMA interrupt queue entry. Setting a bit enables the associated interrupt; clearing a bit masks it. For group-related events, only the mask register for the TRL is referenced. IMA transmit interrupt status. Indicates the status of transmit interrupt events. Stuff holdoff counter. Maintains the minimum five-frame spacing between stuff events for non-TRL links. Must be initialized to zero. Set to 4 by the microcode after a stuff event, and decrements after each ICP cell is sent (saturating at zero). Signalling of ‘imminent stuff’ (and subsequent stuff events) will not occur while this counter is non-zero. 0x04 ITSEC Word 0x08 ITQSP Hword 0x0A ITQEP Hword 0x0C ITQFP Hword 0x0E ITQXP Hword 0x10 ITINTMSK Byte 0x11 0x12 ITINTSTAT LSHC Byte Byte 1 Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 34.4.5.1.1 IMA Link Transmit Control (ILTCNTL) The fields of the ILTCNTL register are shown in Figure 34-21. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-37 Inverse Multiplexing for ATM (IMA) 0 1 2 3 4 5 7 field TRL SES — TXSC IGNUM Figure 34-21. IMA Link Transmit Control (ILTCNTL) Table 34-16 describes the ILTCNTL bit fields. Table 34-16. ILTCNTL Field Descriptions Bits 0 Name TRL Description Defines this link as the timing reference link (TRL) of the group. 0 This link is not the TRL. 1 This link is the TRL. Note: One and only one link of the group must be programmed as the TRL. If zero or more than one links are defined as TRL, erratic operation will occur. Severely errored seconds. Set by software when a severely errored second indication is detected. When set, causes the transmit stuff event counter to stop counting. Reserved, initialize to zero. Transmit status/control. Sets the transmit mode of the IMA link. 00 Filler mode. The IMA link transmits only ICP and filler cells, no data cells. 01 Active mode. The IMA link is capable of sending data cells. 1X Reserved. Determines to which IMA group this link belongs. Contains the number of the link’s associated IMA Group Table entry. Note: This value need not be the same as the group’s IMA ID; the IMA ID is programmed separately in the group’s ICP cell template. 1 2 3–4 SES — TXSC 5–7 IGNUM 34.4.5.1.2 IMA Link Transmit State (ILTSTATE) The fields of the ILTSTATE register are shown in Figure 34-22 0 1 2 3 4 5 7 Field LSTF LIMSTf LSTFIP LGSU TQSU LDC — Figure 34-22. IMA Link Transmit State (ILTSTATE) Table 34-17 describes the ILTSTATE bit fields. Table 34-17. ILTSTATE Field Descriptions Bits 0 1 2 Name LSTF LIMSTF LSTFIP Description Link stuff flag. Microcode-managed parameter. Indicates that the next ICP cell on this link will be part of a stuff event. Initialize to zero at link startup. Link imminent stuff flag. Microcode-managed parameter. Indicates that an upcoming stuff event will be signalled in the next ICP of this link (via LSI=001). Initialize to zero at link startup. Link stuff-in-progress flag. Microcode-managed parameter. Indicates that the next cell on this link will be the second cell of a stuff event. Initialize to zero at link startup. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-38 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-17. ILTSTATE Field Descriptions (continued) Bits 3 Name LGSU Description Link/group startup flag. Microcode-managed parameter. Will be set by the microcode after the link’s transmit queue has reached target average depth of 3 cells. While this bit is cleared, the link will transmit only filler cells. Initialize to zero at link startup. Transmit queue startup flag. Microcode-managed parameter. Will be set by the microcode after the first cell has been sent to the transmit queue. Initialize to zero at link startup. Link Due Cell - Link is due cell from round robin distribution. Microcode managed parameter initialize to 0. Used for optional TRL Service Latency enhancement only. Reserved, initialize to zero. 4 5 6–7 TQSU LDC — 34.4.5.1.3 IMA Transmit Interrupt Status (ITINTSTAT) The fields of the ITINTSTAT register are shown in Figure 34-23. 0 3 4 5 6 7 Field — PTQO TQO PTQU TQU Figure 34-23. IMA Transmit Interrupt Status (ITINTSTAT) Table 34-18 describes the ITINTSTAT bit fields. Table 34-18. ITINTSTAT Field Descriptions Bits 0–3 4 — PTQO Name Reserved, initialize to zero. Persistent transmit queue overflow. Set when a transmit queue overflow occurs for two cells in a row. Further transmit queue overflow events are masked when this bit is set, in order to avoid a ’flood’ of interrupts. This bit can be used to distinguish a temporary overflow condition (which could be caused by a rate differential between the TRL and non-TRL link which was out of compensatable range), or a persistent overflow condition (which could be caused by a more permanent condition, such as a failure of this link’s PHY device). Initialize to zero at link startup. Transmit queue overflow. Set when a transmit queue overflow occurs; cleared when a cell is successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be set when software reads it if the overflow condition was only temporary. PTQO should be used instead to distinguish between persistent or temporary underrun conditions. Persistent transmit queue underrun. Set when a transmit queue underrun occurs for two cells in a row. Further transmit queue underrun events are masked when this bit is set, in order to avoid a ’flood’ of interrupts. This bit can be used to distinguish a temporary underrun condition (which could be caused by a rate differential between the TRL and non-TRL link which was out of compensatable range), or a persistent underrun condition (which could be caused by a more permanent condition, such as a TRL failure). Initialize to zero at link startup. Transmit queue underrun. Set when a transmit queue underrun occurs; cleared when a cell is successfully transmitted. As this bit is set or cleared on a cell-by-cell basis, it may no longer be set when software reads it if the underrun condition was only temporary. PTQU should be used instead to distinguish between persistent or temporary underrun conditions. Initialize to zero at link startup. Description 5 TQO 6 PTQU 7 TQU MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-39 Inverse Multiplexing for ATM (IMA) 34.4.5.2 IMA Link Receive Table Entry Table 34-19. IMA Link Receive Table Entry1 Offset 0x00 0x02 0x04 Name ILRCNTL ILRSTATE ILID Width Hword Hword Byte Description IMA link receive control parameters. IMA link receive state. Microcode-managed parameter. Initialize to 0x0040 at link startup. IMA link ID. Formatted per the Cell ID and Link ID field of an ICP cell. Bit 0: 1 (indicating ICP cell) Bits 1-2: Program to zero Bits 3-7: Program to validated LID for this link [Note: This value is only used by microcode to validate incoming ICP cells for this link, it is not used to determine round-robin transmission order. That function is performed by the group order table.] Receive M counter. Microcode-managed parameter. Receive IFSN counter. Microcode-managed parameter. Number of frames to discard on a this link until it is caught up with the other links in this group (long propagation delay). Microcode-managed parameter. IMA link delay compensation buffer start pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Refer to Section 34.4.6.2, “Delay Compensation Buffers (DCB) for more details. IMA link delay compensation buffer end pointer. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Refer to Section 34.4.6.2, “Delay Compensation Buffers (DCB),” for more details. IMA link delay compensation buffer fill pointer. Microcode-managed parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Initialize to DCBSP at link startup. IMA link delay compensation buffer read pointer. Only used during group delay synchronization and link addition. Microcode-managed parameter. This parameter forms bits 12-27 of the pointer; bits 0-11 are from IMAEXTBASE, and bits 28-31 are zero. Receive ICP channel number. ATM receive channel number to which received ICP cells are sent. IMA receive interrupt mask. Has the same format as the IMA interrupt queue entry.; however, only receive-related bits are relevant. Setting a bit enables the associated interrupt; clearing a bit masks it. For group-related events, only the mask register for the TRL is referenced. Link ICP offset. Program to the ICP offset validated for this link. IMA receive stuff event counter. Increments each time a stuff event is received on this ink. Initialize to zero at link startup. 0x05 0x06 0x07 RMCTR LRIFSN DFC Byte Byte Byte 0x08 DCBSP Hword 0x0A DCBEP Hword 0x0C DCBFP Hword 0x0E DCBRP Hword 0x10 0x12 RICPCH IRINTMSK Hword Byte 0x13 0x14 LICPOS IRSEC Byte Word MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-40 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-19. IMA Link Receive Table Entry1 (continued) Offset 0x18 0x19 0x1A 0x1C Name ANOMALY_CTR ALPHABETA_CTR GAMMA_CTR DEFECT_CTR Width Byte Byte Byte Word Description Anomaly counter. Microcode-managed parameter. Initialize to zero at link startup. Alpha/beta counter. Microcode-managed parameter. Initialize to zero at link startup. Gamma counter. Microcode-managed parameter. Initialize to zero at link startup. Defect counter. This counter is active while the link is in the Loss-of-IMA-Frame (LIF) state and is used to ensure IFSD interrupts are generated for every GAMMA+2 frames. Software can use the period interrupt issued by this counter in order to determine if the link is taking too long to synchronize. The DEFECT_CTR is active before IFSM reaches SYNC. It starts counting from the first cell received and will count from 0 to (GAMMA+2) x M. When it reaches (GAMMA+2) x M an IFSD interrupt is generated and the counter is reset. Upon reception of the next cell it starts to count again and subsequent interrupts are generated. Microcode managed parameter. Initialize to zero at link startup. 1 Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 34.4.5.2.1 IMA Link Receive Control (ILRCNTL) The fields of the ILRCNTL register are shown in Figure 34-24 0 1 2 3 4 5 7 Field GA 8 SES 9 TRL 10 RXSC IGNUM 15 Field Add_new MON_ICP — Figure 34-24. IMA Link Receive Control (ILRCNTL) Table 34-20 describes the ILRCNTL bit fields. Table 34-20. ILRCNTL Field Descriptions Bits 0 GA Name Description Group assigned flag. Set by software after group parameters have been validated. 0 Group unassigned. 1 Group assigned. Severely errored seconds. Set by software when a severely errored second indication is detected. When set, causes the receive stuff event counter and ICP violation counter to stop counting. Identifies this link in the group as the Timing Reference Link (NOTE: Only one link per group can be selected as the TRL). 1 SES 2 TRL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-41 Inverse Multiplexing for ATM (IMA) Table 34-20. ILRCNTL Field Descriptions (continued) Bits 3–4 Name RXSC Description Receive status/control. Sets the receive mode of the IMA link. 00 Filler mode. The IMA link processes only ICP cells. Data cells are replaced with filler cells. 01 Active mode. The IMA link is capable of receiving data cells. 10 Dropped. Must be set by the user during the process of dropping the link. Dropped links are treated filler mode until they are switched out of the receive round-robin (i.e. data cells are replaced with filler cells). 11 Reserved. Determines to which IMA group this link belongs. Contains the number of the link’s associated IMA Group Table entry. Note: This value need not be the same as the group’s IMA ID; the IMA ID is programmed separately in the receive group’s RIMAID field. Identifies this link as a new/added link to a group. Software must flip (0 to 1 or 1 to 0) this bit ONLY when adding a link to an existing group that is operational. If ADD_NEW = ILRSTATE[ADD_NEW_M] = 0, set ADD_NEW to 1 to indicate this is an added link. If ADD_NEW = ILRSTATE[ADD_NEW_M] = 1, set ADD_NEW to 0 to indicate this is an added link. Initialize to zero. Setting this bit will allow changed ICP cells received on this link to be passed on to the ATM layer (defined channel). The user must monitor at least one link in order for ICP cells to be passed on to the ATM layer. Reserved, initialize to zero. 5–7 IGNUM 8 ADD_NEW 9 MON_ICP 10–15 — 34.4.5.2.2 IMA Link Receive State (ILRSTATE) The fields of the ILRSTATE register are shown in Figure 34-25 0 1 2 3 4 5 6 7 Field ADD_NEW_M 8 9 IFSS 10 MASK_ERR 11 STFEX 12 SU 13 CHK_NXT DATA_ERR 14 15 Field icp_cell FSES SYNC_DeFeCT STFIP DL — Figure 34-25. IMA Link Receive State (ILRSTATE) Table 34-21 describes the ILRSTATE bit fields. Table 34-21. ILRSTATE Field Descriptions Bits 0 1–2 Name ADD_NEW_M IFSS1 Description "New Link" shadow bit. Microcode managed parameter. Initialize to zero at link startup. IMA frame synchronization state. Microcode-managed parameter. Initialize to zero at link startup. 00 IMA hunt. 01 IMA presync. 1x IMA sync. Mask Error. Microcode managed parameter. Initialize to zero at link startup. Stuff cell expected. Microcode-managed parameter. Initialize to zero at link startup. 3 4 MASK_ERR STFEX MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-42 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-21. ILRSTATE Field Descriptions (continued) Bits 5 6 7 8 9–10 SU CHK_NXT DATA_ERR ICP_CELL FSES1 Name Description Start Up. Microcode-managed parameter. Initialize to zero at link startup. Check Next. Microcode-managed parameter. Initialize to zero at link startup. Data Error - Parity/CRC. Microcode-managed parameter. Initialize to zero at link startup. Current Cell is an ICP Cell. Microcode-managed parameter. Initialize to zero at link startup. Frame Synchronization Error State. Microcode-managed parameter. Initialize to 10 at link startup. 00 IMA working. 01 Out-of-IMA frame anomaly. 1x Loss-of-IMA frame defect. Synchronization Defect. Microcode-managed parameter. Initialize to zero at link startup. Stuff In-Progress flag. Microcode-managed parameter. Initialize to zero at link startup. Dropped link. Microcode-managed parameter. Initialize to zero at link startup. Reserved, initialize to zero. 11 12 13 14–15 1Enable SYNC_DEFECT STFIP DL — these parameters to their default values during IMA initialization to avoid spurious IMA exceptions in the IMA interrupt queues. 34.4.5.3 IMA Link Receive Statistics Table The IMA link receive statistics table is optional. It is enabled globally for this FCC via IMACNTL[IRSE]. The base of this table is determined by IRLINKSTAT. Entries in the table are indexed by the link number of the associated link. The format for the IMA link receive statistic table entries is shown in Table 34-22 Table 34-22. IMA Link Receive Statistics Table Entry Offset 0x00 Name ICPVIOL Width Word Description IMA receive ICP violation event counter. While ILRCNTL[SES]=0, increments each time an errored, invalid, or missing ICP cell is received on this link. Initialize to zero at link startup. Out-of-IMA frame counter. While ILRCNTL[SES]=0, increments each time an Out-of-IMA Frame anomaly occurs on this link. Initialize to zero at link startup. 0x04 OIF Word 34.4.6 Structures in External Memory The IMA microcode requires supporting queue structures in external memory. These are used for the jitter buffers (on transmission) and the delay compensation buffers (on reception). These structures reside in a 1 megabyte memory region defined by IMAEXTBASE, and may reside on either the 60x bus or the local bus, as defined by IMACNTL[DSB]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-43 Inverse Multiplexing for ATM (IMA) 34.4.6.1 Transmit Queues Transmit queues are allocated on a per-link basis. They are circular queues of 64-byte buffers, defined by their start and end pointers. For the transmit queue of the timing reference link (TRL), the queue must consist of a minimum of four buffers (although it may consist of five buffers, if consistency of data structures is desired). For the transmit queues of non-TRL links, the queues must consist of five buffers. Queue fill and extract pointers must be initialized by software to the start of the queue; thereafter, these pointers are managed by the microcode. The queue pointers must be on a 64-byte aligned boundary. IMAEXTBASE IMA External Structure Region bits 0-11 IMAEXTBASE bits 12-27 ITQSP bits 28-31 0000 Transmit Queue 64-byte boundary ITQSP + TQ_SIZE - 4 IMAEXTBASE ITQEP 0000 Figure 34-26. IMA Transmit Queue 34.4.6.2 Delay Compensation Buffers (DCB) Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs are allocated on a per-link basis. They are of user-definable length, thereby providing a programmable maximum synchronizable delay. Note that DCBs of links within a group must all have the same size. DCBs consist of a circular queue of 64-byte cell buffers. These cell buffers contain the received cell followed by 12 bytes of header/status information. 52 bytes RX CELL 64 bytes 12 bytes HEADER/STATUS Figure 34-27. Cell Buffer in Delay Compensation Buffer The length of a DCB is defined by the link’s DCBSP and DCBEP parameters. The length of the DCB (defined by (DCBEP-DCBSP) x 16) must be an integer multiple of the IMA frame length in bytes, M x 64. Furthermore, the DCBSP must be aligned on a M x 64-byte boundary. For example, if M = 64, then DCBSP must be on a 4KB boundary. To ensure group delay synchronization, the minimum length of the DCB should be 2(Mx64). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-44 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) The DCB memory area must be initialized to zero at link startup. IMAEXTBASE IMA External Structure Region bits 0-11 IMAEXTBASE bits12-27 DCBSP bits 28-31 DCB 0000 M x 64-byte boundary (DCBEP - DCBSP) x 16 IMAEXTBASE DCBEP 0000 Figure 34-28. IMA Delay Compensation Buffer 34.4.7 IMA Exceptions One of the four ATM interrupt queues must be dedicated to IMA events. This enables minimum latency in dealing with the IMA state machines, and ensures that the unique format for IMA exceptions are not confused with other exceptions. The IMA interrupt queue is defined in the IMACNTL[INTQ] parameter. IMA events sent to this queue include only those described in this section. ICP receive events are treated as normal receive events, and should therefore go to the interrupt queue allocated for receive events. 34.4.7.1 IMA Interrupt Queue Entry The format for the IMA interrupt queue entries is shown in Figure 34-29 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 OFFSET + 0 V — W — TQU TQO — NUM DSL LS DCBO LDS GDS IFSD IFSW OFFSET + 2 L/G Figure 34-29. IMA Interrupt Queue Entry Table 34-23 describes the IMA interrupt queue entry bit fields. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-45 Inverse Multiplexing for ATM (IMA) Table 34-23. IMA Interrupt Queue Entry Field Descriptions Offset Offset + 0 0 Bits Name V Description Valid interrupt entry. 0 This interrupt queue entry is free and can be used by the CP. 1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit. Reserved. Wrap bit.When set, this is the last interrupt circular table entry. During initialization, the host must clear all W bits in the table except the last one, which must be set. Reserved Reserved Transmit queue underrun. Indicates that the corresponding PHY for this link requested a cell for transmission, but the transmit queue was empty. Transmit queue overflow. Indicates that the TRL attempted to send a cell to this link’s transmit queue, but no space was available. Reserved DCB synchronization lost. This interrupt is issued when a link in a group with IGRSTATE[GDSS] = 11 loses synchronization, and the link enters HUNT state at the IFSM. Link stalled. A link in the round-robin cell extraction process has excessively stalled and been deactivated (i.e. switched to filler mode by the microcode). 1 2 3–4 5 6 7 8 9 — W — — TQU TQO — DSL 10 11 12 13 14 15 Offset + 2 0 LS DCBO Link out of delay synchronization. Set when the link’s DCB overflows, indicating that delay synchronization for this link is not possible. LDS GDS IFSD IFSW L/G Link delay synchronized. Set when delay synchronization is achieved for a link that has been added to an existing group. Group delay synchronized. Set when a group achieves delay synchronization as part of the group startup procedure. IMA frame synchronization status = defect. Set when the associated link goes into the Loss of IMA Frame Defect state of the Error/Maintenance State Machine. IMA frame synchronization status = working. Set when the associated link goes into the IMA Working state of the Error/Maintenance State Machine. Link/group indicator. Indicates whether this interrupt is associated with a link or a group, and thus if the NUM field is a link number or group number. 0 This interrupt is associated with a link. 1 This interrupt is associated with a group. Link or group number associated with this interrupt. 1–15 NUM 34.4.7.2 ICP Cell Reception Exceptions ICP cells are received as AAL0 in the channel defined in RICPCH. Receive interrupts are provided for this channel if enabled in its associated RCT. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-46 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.8 IDCR Timer Programming Programming of the IDCR timer data structures is optional. It is only required if any of the IMA groups use IDCR-regulated cell processing. Only one IDCR master clock per FCC is supported; the IDCR timers for the individual groups are derived from the IDCR master clock. Each IDCR timer has an associated IDCR table entry, indexed by the IMA group number. 34.4.8.1 IDCR Master Clock The signal normally used for DMA request for a selected IDMA channel is instead used to provide the clock signal for the IDCR master clock. This signal must be provided on the external DREQx signal, either by using an external clock source or by externally connecting one of the baud rate generator (BRG) outputs to the signal. The IDCR master clock is enabled by configuring the DREQx pin and supplying the external clock signal. The IDCR master clock is disabled by either (1) turning the clock signal off, or (2) changing the configuration of DREQx to be an alternate function or general-purpose I/O. The IDCR_Init command must be issued before enabling the IDCR master clock. A higher IDCR master clock frequency provides greater resolution in determining and reconstructing the IDCR. However, an IDCR master clock frequency that is too high will consume too much CPM processing power and will hinder the function of the MPC8280. Therefore, the period of the IDCR master clock should be no less than (number of IMA receive groups) x (500 CPM clocks). The DONEx and DACKx signals of the IDMA channel are not used. Their I/O ports must be programmed to an alternate function or to general-purpose I/O. RCCR[DRxM] should be programmed to edge-sensitive for the DREQx signal functioning as the IDCR master clock. 34.4.8.2 IDCR FCC Parameter Shadow The FCC parameters (including IMAROOT) for the FCC associated with the IDCR master clock must be copied onto the parameter RAM page for that IDCR master clock. For example, if DREQ1 serves as the IDCR master clock signal for FCC2, then the FCC parameters for FCC2 (at offset 0x8500) must be copied to parameter page 8 (at offset 0x8700). 34.4.8.2.1 MPC8280 Features Unavailable if IDCR is Used Since their parameter RAM space is used as FCC parameter shadow space, other MPC8280 features associated with this parameter RAM space will not be available. Selection of the IDCR clock signal must be made with this in mind. Table 34-24 summarizes the MPC8280 features that share IDMA parameter space which will not be available if DREQx is used as IDCR master clock, MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-47 Inverse Multiplexing for ATM (IMA) Table 34-24. Unavailable Features when DREQx used as IDCR Master Clock IDCR Master Clock DPRAM Page DREQ1 DREQ2 DREQ3 DREQ4 8 9 10 11 MPC8280 Features Not Available MCC1, SMC1, and IDMA1 are unavailable. MCC2, SMC2, and IDMA2 SPI and IDMA3 RISC Timers, Microcode Rev Num, Random Number Generator function and IDMA4 34.4.8.2.2 Programming the FCC Parameter Shadow All of the user-defined or user-initialized FCC parameters of the FCC should be copied from the FCC parameter page to the shadow page. The following parameters are exceptions: • RCELL_TMP_BASE of the shadow page must differ from RCELL_TMP_BASE of the FCC parameter page. This RCELL_TMP_BASE must point to a separate temporary cell storage area similar to that reserved on the FCC parameter page. • Either: — (1) INTT_BASE of the shadow page must differ from the INTT_BASE of the FCC parameter page, and along with it separate interrupt parameters and queues. — OR (2) INTT_BASE of the shadow page and FCC parameter page may be the same and therefore share common structures, but (a) receive interrupts for the data channels associated with non-IMA links, data channels associated with non-IDCR IMA links, and ICP channels for group-unassigned IMA links must be directed to one dedicated interrupt queue, and (b) receive interrupts for the data channels of group-assigned IMA links using IDCR must be directed to another dedicated interrupt queue. • COMM_INFO on the shadow page is unused. ATM commands issued will use the COMM_INFO fields on the FCC parameter page. • INT_RCT_BASE and EXT_RCT_BASE should be the same for both the shadow page and the FCC parameter page. However, (a) received data from data channels associated with non-IMA links, received data from data channels associated with non-IDCR IMA links, and received ICP cells from group-unassigned IMA links, and (b) received data and ICP cells from group-assigned IMA links using IDCR must never target the same receive queues. This would not normally be done anyway; however, if it was done, it would result in erratic operation. 34.4.8.2.3 On-the-Fly Changes of FCC Parameters In general, the FCC parameters should not require changes when the FCC is operating. In the event that on-the-fly changes of FCC parameters is performed, those changes should be made one-by-one first in the parameters of the shadow area, followed by the same change in the FCC parameter area. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-48 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.8.3 IDCR_Init Command The IDCR_Init command is a host command issued to the CPCR (refer to Section 14.4.1, “CP Command Register (CPCR)”). This command selects and configures the IDMA request which will be used for the IDMA master clock. Any of the IDMA channels may be selected for this function. The format of the command is as follows: • SBC = [per the selected IDMA channel] • OPCODE = 0x00 • PAGE = [per the selected IDMA channel] 34.4.8.4 IDCR Root Parameters Table 34-25. IDCR IMA Root Parameters1 The following IDCR parameters are added to the IMA root table only when IDCR is used. Offset 0x60 0x62 0x64 Name IDCR_BASE IDCRTICK IDCREN Width Hword Hword Byte Description IDCR table base. Offset of the IDCR table in DPRAM. Must be 8-byte aligned. IDCR global tick counter. Initialize to zero. IDCR enable array. Each bit (0-7) enables/disables the IDCR timer for the associated IMA group. Initialize to zero at FCC initialization. 0 The IDCR for the associated group is disabled. 1 The IDCR for the associated group is enabled. Group number of last enabled IDCR timer. IDCR timer currently being serviced. Microcode-managed parameter. Initialize to zero. 0x65 0x66 1 IDCR_LAST IDCR_SVC Byte Byte Boldfaced entries indicate parameters that must be initialized by the user. All other parameters are managed by the microcode and should be initialized to zero unless otherwise stated. 34.4.8.5 IDCR Table Entry A table entry of the format provided below must be provided for any IMA group for which IDCR recovery is performed. Table entries in the IDCR table are indexed by the group number of the associated group. The table entry must be initialized before the associated bit is set in IDCREN. Table 34-26. IDCR Table Entry Offset 0x00 Name IDCRCNT Width Hword Description IDCR count. Holds the count of the IDCR timer for this IMA group. Decremented once for each IDCR master clock tick. Initialize to IDCRREQ. IDCR count fraction. Holds the fractional portion of the count of the IDCR timer for this IMA group. Initialize to IDCRREQF. 0x02 IDCRCNTF Hword MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-49 Inverse Multiplexing for ATM (IMA) Table 34-26. IDCR Table Entry (continued) Offset 0x04 0x06 Name IDCRREQ IDCRREQF Width Hword Hword Description IDCR request rate. Program to [TRLR/(RNUMLINKS x 128)] x (2048/2049). IDCR request rate fraction. Holds the fractional portion of the IDCR request rate, represented as (IDCRREQF / 65536). 34.4.8.6 IDCR Counter Algorithm The IDCR count of each enabled IDCR timer is decremented each tick of the IDCR master clock. When the IDCRCNT reaches zero, a cell is processed for the associated IMA group, and IDCRCNT and IDCRCNTF are added with IDCRREQ and IDCRREQF, respectively. When IDCRCNTF overflows, the ’carry’ is added to IDCRCNT, such that the average rate of IDCRCNT timeouts equals the integer-plus-fraction rate programmed into IDCRREQ and IDCRREQF. For each tick of the IDCR master clock, the timer table is scanned from entry zero to the entry programmed in IDCR_LAST. For greatest efficiency, the groups which use IDCR-regulated reception should therefore be allocated the lowest group numbers, beginning from zero. 34.4.8.7 IDCR Events For channels running on IMA links with IDCR mode enabled, events are reported and masked in the IDSR and IDMR registers associated with the IDCR master clock. Furthermore, these events are signalled via the associated IDMAx bit in the SIPNR_L register. The fields of the IDSR and IDMR registers are shown in Figure 34-30 Note that INTO1/GRLI and INTO0/GBPB occupy the same bits in the register. Events of either type will cause this bit to be set. It is therefore recommended that if the global buffer pool feature is used for channels running on IMA links in IDCR mode, then the user should not use interrupt queues 1 and 0 for receive or transmit events from these IMA links. 0 1 2 3 4 5 6 7 Field GINT3 GINT2 GINT1 GINT0 INTO3 INTO2 INTO1/GRLI INTO0/GBPB Figure 34-30. IDMA Event/Mask Registers in IDCR Mode (IDSR/IDMR) Table 34-27 describes the IDSR/IDMR bit fields. Table 34-27. IDSR/IDMR Field Descriptions Bits 0–3 4–5 Name GINTx INTOx Description Global Interrupt. Set when an event is sent to the corresponding interrupt queue. Interrupt queue overflow. Set when an overflow condition occurs in the corresponding interrupt queue. This occurs when the CP attempts to overwrite a valid interrupt entry.. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-50 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) Table 34-27. IDSR/IDMR Field Descriptions (continued) Bits 6 Name INTO1/ GRLI INTO0/ GBPB Description INTO1: Interrupt queue overflow 1. See INTOx above. GRLI: Global red-line interrupt. GRLI is set when a free buffer pool’s RLI flag is set. The RLI flag is also set in the free buffer pool’s parameter table. INTO0: Interrupt queue overflow 1. See INTOx above. GBPB: Global buffer pool busy interrupt. GBPB is set when a free buffer pool’s BUSY flag is set. The BUSY flag is also set in the free buffer pool’s parameter table. 7 34.4.9 APC Programming for IMA Dynamically adding and dropping links from a group changes the overall bandwidth of the group. The bandwidth of a particular ATM channel is programmed as a percentage of the overall bandwidth, up to 100% in the case of APC pace of 1. In the case of IMA, it is desirable to allow for the dynamic addition and deletion of links without changing the bandwidth of individual ATM channels, so that ATM traffic contracts will not be violated. To do this without requiring updates of the APC parameters of all of the ATM channels, the APC algorithm must be modified to consider the number of links in the group. To accomplish this for channels which will be used with IMA groups, the APC parameters should be programmed to define the bandwidth of a channel as a percentage of one link of the IMA group. As such, the APC pace can be greater than 100%, in the case that a channel uses more bandwidth than a single link can provide. The APC pace will be scaled automatically by the IMA group transmit parameter TNUMLINKS. After scaling, if the pace required of the group is still greater than 100% of the group bandwidth, the channel will be rescheduled at 100% of the group bandwidth. Refer to the examples in Table 34-28. Table 34-28. Examples of APC Programming for IMA Example 1 Description [The simplest case.] For an IMA group consisting of one 2Mbps link, with one CBR channel consuming the full bandwidth of that link (i.e. 2Mbps), TNUMLINKS for the group should be programmed to 1 and the APC pace of the channel should be programmed to 1 (PCR=1, PCR_Fraction=0). Another 2Mbps link is added to the IMA group in Example 1. The overall bandwidth of the group is now 4Mbps. However, TNUMLINKS is now 2, and therefore the programmed PCR will be scaled by 2. [Note that the scaling is done automatically internally; the PCR programmed into the channels transmit connection table entry is not modified.] A scaled PCR of 2 indicates that the channel uses 50% of the bandwidth of the group, or 2Mbps. Comparing to example 1 above, we see that the bandwidth of the channel has not changed, even though the bandwidth of the group has changed. Consider an IMA group consisting of five 2Mbps links, over which a 6Mbps CBR channel is to be sent. 6Mbps is 300% of what a single 2Mbps link can provide, so its pace should be programmed as 1/3 (PCR=0, PCR_Fraction=85). Scaling the pace by TNUMLINKS results in 5/3 (PCR=1, PCR_Fraction=169), which indicates that the channel will use 60% of the bandwidth of the group, or 6Mbps. 2 3 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-51 Inverse Multiplexing for ATM (IMA) Table 34-28. Examples of APC Programming for IMA (continued) Example 4 Description Assume that one link is dropped from the IMA group in Example 4. The overall bandwidth of the group is now 8Mbps, and TNUMLINKS becomes 4. Therefore, the pace for the 6Mbps CBR channel described above scales to 4/3 (PCR=1, PCR_Fraction=84), indicating that the channel will use 75% of the bandwidth of the group, which is still 6Mbps. Assume that two links more are dropped from the IMA group in Example 4. The overall bandwidth of the group is now 4Mbps, and TNUMLINKS becomes 2. Therefore, the pace for the 6Mbps CBR channel described above scales to 2/3 (PCR=0, PCR_Fraction=170). This is less than 1, which is not possible to support, so it is rounded up to 1. The channel originally programmed for 6Mbps now consumes 100% of the 4Mbps IMA group. 5 Per the above explanation and examples, it is seen that TNUMLINKS is the only parameter which needs to be modified by software when a link is added or dropped from an IMA group. All other APC parameters need not be modified. [Note, however, that if links are dropped such that the total scheduled bandwidth of the ATM channels is greater than 100% of the IMA group bandwidth, this will result eventually in APC overruns, and should therefore be corrected and/or avoided. NOTE Software should ensure that the length of the APC scheduling table is increased if links are added to the IMA group. When incrementing the number of links in an IMA group, the user might exceed the length of the APC scheduling table; if this happens, the ATM channel is mapped outside of the APC scheduling table and the channel stops. 34.4.9.1 Programming for CBR, UBR, VBR, and UBR+ All APC parameters for CBR, UBR, VBR, and UBR+ channels which will be transmitted over IMA groups should be scaled by the intended steady-state value of TNUMLINKS. Their values should be divided by TNUMLINKS, as they will be scaled by TNUMLINKS when the pacing algorithms are performed. The parameters which must be scaled include: PCR, SCR, OOBR, BT, MCR, and MDA. 34.4.9.2 Programming for ABR ABR channels are a special case, in that they are not programmed as a percentage of the physical line rate as inferred from the period of requests from the PHY layer. Instead, the rate of an ABR channel is programmed as a percentage of an explicitly-provided parameter, the LINE_RATE_ABR, which is programmed in the APC parameter table for each APC. Therefore, when links are added or dropped from an IMA group which carries ABR traffic, the parameter LINE_RATE_ABR must also be scaled to reflect the change in bandwidth of the group. For example, if TNUMLINKS increases from three to four, then LINE_RATE_ABR must also be multiplied by 4/3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-52 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.4.10 Changing IMA Version A new CPCR command has been added to the IMA microcode to change the IMA version on-the-fly without software intervention. Use the following procedure: 1. Before issuing the command, the user should initialize the COMM_INFO fields in the parameter RAM as described in Figure 34-31. 2. To issue this FCC command, refer to Section 14.4, “Command Set.” Use opcode 1110(0xD). m 0 8 9 11 12 15 0x86 0x88 0x8A — Filler CRC — ITG — IV Figure 34-31. COMM_INFO Field m Table 34-29. COMM_INFO Field Descriptions Offset 0x86 Bits 0–8 — Name Reserved, should be cleared. IMA transmit group. Program to the IMA group number [0–7] multiplied by 16 bytes. For example, if the IMA group number = 3, program ITG to 0x30. Reserved, should be cleared. Description 9–11 ITG 12–15 — 0x88 0x8A 0–15 Filler CRC Filler cell CRC. Set to 0xC602 (for IMA version 1.0) or 0xD902 (for IMA version 1.1) 0–13 — 14–15 IV Reserved, should be cleared. IMA version 00 Reserved 01 IMA version 1.0 10 Reserved 11 IMA version 1.1 3. Wait for the CPCR[FLG] to be cleared by the CPM before issuing a new CP command. Refer to Section 14.4, “Command Set.” 34.5 34.5.1 IMA Software Interface and Requirements Software Model The IMA microcode facilitates the implementation of the lower levels of an IMA system. Host software (from here on, “host software” is code running on the G2_LE core) is responsible for initializing MPC8280 IMA data structures, establishing and tearing down connections, handling of alarms, keeping statistics, and controlling protocol state machines. The IMA microcode interfaces to the software-implemented (layer management and plane management) functions by providing received ICP cells and by interrupts. The software-implemented functions control the microcode and the system via the IMA root, group, and link parameters and by providing an ICP cell template to the microcode for ICP cell transmission. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-53 Inverse Multiplexing for ATM (IMA) Tx ICP Template ICP Cells Link 1 Interrupts Layer Management IMA Tx Microcode Routine Link n Host Software Link 1 Plane Management Interrupts IMA Rx Microcode Routine Rx ICP Channel Link n ICP Cells IMA Parameters Figure 34-32. IMA Microcode/Software Interaction 34.5.2 Initialization Procedure 1. Program FCC registers/parameters for ATM operation with UTOPIA multi-PHY (excluding APC parameters for IMA PHYs). 2. Program IMA FCC and root parameters. 3. Enable FCC via GFMRx[ENR,ENT]. Aside from IMA state machine control and IMA-specific error events, subsequent interaction with the ATM channels is the same as for non-IMA operation (e.g. host commands, RCT/TCT parameters, buffer descriptors, interrupts). 34.5.3 Software Responsibilities The following functions are the responsibility of the host software which must complement the IMA microcode in order to provide a complete IMA solution. 34.5.3.1 • System Definition Definition of P(Rx) and P(Tx)—software variables which are used to determine “sufficient links” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-54 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.5.3.2 • • General Operation React to received ICP cells. ICP cells are only received when their SCCI field changes, except the first received ICP cell Report any NE and FE timing mode mismatches (ITC vs. CTC) to the Unit Management 34.5.3.3 • Receive Link State Machine Control • • • • Set up unassigned links, awaiting ICP cells — Define either as standard multi-PHY or as unassigned IMA link — Set up receive channel for ICP OAM cells for this link only Create and initialize delay compensation buffer Respond to received ICP cells. Extract and validate link/group parameters — IMA ID — Link ID — Link ICP offset — IMA frame size (M) After establishment of group, change receive channel for ICP OAM cells such that all links in the group point to the same channel Control link operation (via ILRCTNL[RXSC]) in coordination with link and group states 34.5.3.4 • • Receive Group State Machine Control • • • Coordinate receive links, using received ICP cells to identify a proposed group Establish and validate group parameters in conjunction with the received link states and parameters — IMA version — IMA ID — Group order table Enable delay synchronization for the group, and react to its completion Control group operation (via IGRCNTL[RXSC]) in coordination with group state Signal receive group state via ICP cells of corresponding transmit group 34.5.3.5 • Transmit Link State Machine Control • Define the IMA link — Define link parameters (e.g. IMA ID, Link ID, IMA frame size (M)) in coordination with IMA group definition — Assign ICP offset — Create and initialize transmit queue Control link operation (via ILTCNTL[TXSC]) in coordination with link and group states MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-55 Inverse Multiplexing for ATM (IMA) 34.5.3.6 • Transmit Group State Machine Control • • • • • Define the IMA group(s) — Assign IMA ID — Assign Link IDs and the transmit group order table — Assign TRL — Assign IMA frame size (M) — Signal group parameters via ICP cells — Define ATM pace controller (APC) parameters for this transmit group Signal transmit group state via ICP cells Negotiate transmit group parameters with the far end Check status of links in group to make ‘Sufficient Links’ determination Control group operation (via IGTCNTL[TXSC]) in coordination with group state Coordinate link state transitions with group state transitions during group startup and link addition 34.5.3.7 Group Symmetry Control All types of group symmetry (operation and configuration) are supportable. This is facilitated by the ability to independently enable/disable links (via RXPHYEN and TXPHYEN) and to control link and group states (via independent link and group transmit and receive parameters). 34.5.3.8 • • ICP End-to-End Channel Transmission Can send information on end-to-end channel by updating field in Tx ICP. No Rx support is provided for end-to-end channel. 34.5.3.9 Link Addition and Slow Recovery (LASR) Procedure Coordinate addition of links for both receive and transmit, including the following: • Establishing their parameters • Checking for defects • On-the-fly insertion into data structures 34.5.3.10 Failure Alarms • • • • • React to errors signalled in received ICP cells React to physical layer errors Monitor persistence of errors to determine alarm condition. Report receive defects within 2M cells of entering defect state Signal upper-layer software MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-56 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.5.3.11 Test Pattern Control • • Initiate transmit test patterns in the group’s transmit ICP cells (via TXTC and TXTP), and monitor response in the receive ICP cells of the associated receive group Respond to test patterns by: — Recognizing test pattern activity in the received ICP cells — Locating the Tx Test Pattern field in the ICP cell of the test link. (Because the SCCI field changes as part of the test pattern generation by the far end, the cell will necessarily be among the received ICP cells. Locate the latest ICP cell with a LID matching the Tx LID of the test link). — Signalling back via the transmit ICP cells of the associated transmit group, by modifying the transmit ICP cell template appropriately 34.5.3.12 Performance Parameter Measurement and Reporting • • • Establish timers to correlate errors with time intervals (e.g. to determine severely errorred seconds (SES) or unusable seconds (UUS)) Maintain statistics Enable/disable receive and transmit event counters according to severely errorred seconds (SES) condition via ILRCNTL[SES] and ILTCNTL[SES] 34.5.3.13 SNMP MIBs Control interface and statistics information should be provided per the SNMP MIB definition for IMA. 34.5.4 IMA Software Procedures The following procedures must be followed in order to assure the synchronization of changes between the link state machines and the group state machine. Issues to be considered are order of changes to the ICP cell and pointer, group order structure and pointer, IMA PHY assignment structure, and group/link Tx control fields. 34.5.4.1 Transmit ICP Cell Signalling 1. Copy the transmit ICP cell template currently in use (as indicated by TICPPTR) to the ICP cell template area not in use. 2. In the new template, change the ICP cell template fields as appropriate. 3. Verify that the IGTCNTL[ICPC] equals IGTSTATE[ICPCA]. If not, wait until it does. 4. Change TICPPTR to point to the “changed/altered” (see step 1) ICP cell template. 5. Toggle IGTCNTL[ICPC]. 34.5.4.2 Receive Link Start-up Procedure Before “activation” of links and group can take place, ICP cells must be received and processed by the management software. Software must configure all IMA links to “group unassigned” mode. Reception MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-57 Inverse Multiplexing for ATM (IMA) of ICP cells requires that the corresponding PHYs (i.e., links) have been enabled and the corresponding connection table entry/entries initialized (see RXPHYEN, IMAPHYEN, and RICPH). In “group unassigned” mode, the first received ICP cell will always be reported to the corresponding channel’s buffer (RICPCH) and subsequently every time there is a change in the SCCI (Status and Control Change Indication) field of the ICP cell. • Set ILRCNTL[GA] to 0 (zero). Setting GA to zero (group unassigned) allows only ICP cells to be processed, all other cells are dropped. The management software will analyze the ICP cells and program the corresponding IMA Link Receive Table parameters: • IMA Link ID (ILID) • Link ICP offset (LICPOS) • Select link as the Timing Reference Link (only one link can be TRL). ILRCNTL[TRL] = 1. • Assign the link to a group. ILRCNTL[IGNUM] = x. • Verify size of frame (M) is the expected value. The software must have built in knowledge of the mapping between physical links and their corresponding channel number (e.g., PHY 0 uses channel 2 (RICPH = 2)). Once a group has been established, the user can have all links in a group report changed ICP cells to a single channel (either by changing RICPCH for all the links to be the same or by clearing the MON_ICP bit): • ILRCNTL[MON_ICP] = 0. Note, at least 1 link in the group must have this bit set. 34.5.4.3 Group Start-up Procedure The IMA Frame Synchronization Mechanism (IFSM) is initiated when a link is switched to “group assigned.” However, before that happens, management software must have programmed the group parameters based upon the received/negotiated values in ICP cells: • IMA ID (RIMAID) • IMA Version (IMAVER) • IMA Frame Size (RM) There are other parameters that don’t depend on ICP information for programmability. Therefore, it is the assumption that they have been initialized prior to the start of the IFSM. Start the IFSM by setting each link in the group to “Group Assigned”: • Set ILRCNTL[GA] to 1 (one). Management software must now wait until each link in the group has achieved IMA frame synchronization. For each link in the group that was “group assigned” an IFSW (IMA Frame Synchronization Working) event is generated. See section “IMA Exceptions.” Having achieved frame synchronization, software can now enable the Group Delay Synchronization (GDS) mechanism (i.e., finding link with shortest delay and buffering accordingly via DCB). • Configure group order table with the ascending link order (round robin distribution) to be used when reconstructing the ATM stream. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-58 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) • • Set the corresponding PHY bit in REF_LINK. Set IGRSTATE[GDSS] to 1 (one) to enable GDS. Once group delay synchronization is achieved, a “GDS” exception is generated. At this point, ATM stream reconstruction can take place. In order for stream reconstruction to be performed by the MPC8280, the user must switch all links and corresponding group (both directions) to “active” mode (i.e., capable of receiving data cells). Set RX to “active” first, to avoid having the transmitter generate a data stream when the opposite end is not ready: • Set ILRCNTL[RXSC] to 1 (one) to enable reception of data cells at the link level. • Set IGRCNTL[RXSC] to 1 (one) to enable reception of data cells at the group level. • Set ILTCNTL[TXSC] to 1 (one) to enable transmission of data cells at the link level. • Set IGTCNTL[TXSC] to 1 (one) to enable reception of data cells at the group level. 34.5.4.3.1 As Initiator (TX) Most of the actions required when a system initiates the establishment of a group with X links involves the exchange of ICP cells between the Near End (Initiator) and the Far End (Responder). In any case, both ends must start with a group of X potential links configured to “filler mode”. One and only one of the links in the group must be designated as TRL. • Set ILTCNTL[TXSC] to 0 (zero)—link is in filler mode. • Set IGTCNTL[TXSC] to 0 (zero)—group is in filler mode. The actions at both ends mirror each other. That is, the Near End will initiate the establishment of a group with X links by sending ICP cells to the FE and vise versa. The normal ICP state changes, driven by the state machine software, are (on a per-link basis): 1. Not In Group 2. Unusable 3. Usable 4. Active Refer to section “Transmit ICP Cell Signalling” for details on how to modify and transmit an updated ICP cell. It is the responsibility of the GSM/LSM (Group/Link State Machine software) to initialize the IMA ID (i.e. group ID) in the ICP cell template and link ID in the corresponding TX IMA Link Transmit Table Entry (ILTTE): • Set ILTTE[ILID] = corresponding Link ID. • Set IMA ID accordingly in the ICP Cell Template. As an initiator, the NE (“end” is relative) must have established a group with X links provisioned. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-59 Inverse Multiplexing for ATM (IMA) Tx ICP Template Tx ICP Template TX GSM/ LSM TX GSM/ LSM Near-end MPC8280 RX Far-end MPC8280 RX ICP buffer ICP buffer Figure 34-33. Near-End versus Far-End 34.5.4.3.2 As Responder (RX) The IMA GSM/LSM software will receive ICP cells in the ICP buffer conveying the state of the FE’s group and links. Once it has determined that the required minimum number of links are available, it can proceed to enable the “group delay synchronization (GDS)” mechanism in which the all links in the corresponding group are analyzed to find the one with the shortest propagation delay. The amount of delay tolerated is programmable and is programmed via the setting of the beginning and ending addresses (size) of the delay compensation buffers (DCB). Note that the size of all DCBs must be the same and must be initialized before the GDS mechanism is activated. Activate GDS: • Set IGRSTATE[GDSS] to 1 (one) to enable GDS. Once GDS is enabled, the user must not alter GDSS. Once group delay synchronization is achieved, a “GDS” exception is generated. At this point, ATM stream reconstruction can take place. In order for ATM stream reconstruction to be performed by the MPC8280, the user must switch all links in the group to “active” mode (i.e., capable of receiving data cells), as specified earlier in this section. The initialization of the ATM TX and RX data structures required to generate and receive the ATM stream is out of the scope of this document, however, it is documented in Chapter 31, “ATM Controller and AAL0, AAL1, and AAL5.” 34.5.4.4 Link Addition Procedure Adding a link to an existing group requires changes to both the group and link table entries. Aside from the normal exchange of ICP cells by the state machines at the FE and NE, the following steps should be followed. In general, a new link entry is appended to the existing list of link table entries and the required parameters initialized. This has no impact until the corresponding link is enabled via the PHYEN fields in the IMA root table. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-60 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.5.4.4.1 1. 2. 3. 4. 5. 6. 7. Rx Steps Reset all RX parameters in the new link table entry to zero. Assign corresponding group number for the new link: ILRCNTL[IGNUM] = x. Assign channel number for ICP cell reception: RICPCH = x. Enable desired interrupts: IRINTMSK = x Allow for the reception of ICP cells during the IFSM stage: ILRCNTL[MON_ICP] = 1. Indicate that this link has not yet been assigned to a group: ILRCNTL[GA] = 0. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in IMAPHY. See Table 34-3. 8. Enable the corresponding link/PHY in the IMA Root Table by setting the corresponding bit in RXPHYEN. See Table 34-3. 9. Software receives and accepts ICP cell values (e.g. M, LID, etc.). 10. Program expected LID: ILID = x 11. Program the expected ICP offset: LICPOS = x 12. Initialize the DCB pointers accordingly: DCBEP, DCBSP, DCBFP. Note, it is recommended that the DCB be initialized to zero. 13. Configure link to “Loss of IMA Frame” state: ILRSTATE[FSES] = 2. 14. Start the IMA Frame Synchronization Mechanism (IFSM) by assigning this link to the group: ILRCNTL[GA] = 1. 15. Software must now wait for the IFSW (IMA Frame Synchronization Working) event/exception. 16. Now that we have a “frame” synchronized link, we can proceed to allow the link to be “delay” synchronized. Indicate that this is a new link (GDS/reconstruction function) by inverting the current “add-new” bit value: ILRCNTL[ADD_NEW] = x. 17. Formulate new group order table with the new link included (see Section 34.4.4.2.4, “Receive Group Order Tables”). 18. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x. 19. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to an emptied DCB condition (stalled link, see LS exception). The recommended new value is: STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See Section 34.4.4.2, “IMA Group Receive Table Entry”: IGRTE[STALL_THR] = x. 20. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding bit in REF_LINK. See Table 34-3. 21. Software must now wait for the link delay synchronization process to complete. A LDS (Link Delay Synchronized) exception will be generated by the MPC8280 as soon as this happens. 22. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 1. 34.5.4.4.2 TX Parameters 1. Reset all TX parameters in the new link table entry to zero. 2. Assign corresponding group number for the new link: ILTCNTL[IGNUM] = x. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-61 Inverse Multiplexing for ATM (IMA) 3. Enable desired interrupts: ITINTMSK = x. 4. Software formats content of ICP template accordingly (see section “Transmit ICP Cell Signalling”). 5. Program the Link’s ID (LID) in the IMA Link Transmit Table Entry (ILTTE): ILID = x. 6. Program the ICP offset (ILTTE): LICPOS = x. 7. Initialize the Transmit Queue pointers accordingly: ITQSP, ITQEP, ITQFP, and ITQXP. 8. Construct the new TX Group Order Table (includes the added/new link). 9. Point to new TX Group Order Table in the corresponding IMA Group Transmit Table Entry (IGTTE): TGRPORDER = New Table Offset. 10. Configure this link/PHY as an IMA link in the IMA Root Table by setting the corresponding bit in IMAPHY. See Table 34-3. 11. Enable the corresponding link/PHY in the IMA Root Table by setting the corresponding bit in TXPHYEN. See Table 34-3. 12. Software must now wait for the corresponding FE link to go to “active” state (See Section 34.4.4.1.4, “ICP Cell Templates.”). At this point, the link can be configured to “active mode”, capable of sending data cells. Prior to this point, only filler and ICP cells were transmitted. ILTCNTL[TXSC] = 1. 13. Increment the number of links currently in the group (IGTTE): TNUMLINKS += 1. 34.5.4.5 Link Removal Procedure Removing a link from an existing group requires changes to both the group and link table entries. Aside from the normal exchange of ICP cells by the state machines at the FE and NE, the following steps should be followed. In general, a link entry is removed from the existing list of link table entries and the required parameters initialized. Note that if only one link is used in a group the software must monitor the TC layer in order to detect that this link has stalled. 34.5.4.5.1 Rx Steps 1. Formulate new group order table with the “dropped” link excluded (see Section 34.4.4.2.4, “Receive Group Order Tables“). 2. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to an emptied DCB condition (stalled link; see LS exception). The recommended new value is: STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See section “IMA Group Receive Table Entry”: IGRTE[STALL_THR] = x. 3. Inhibit storing of cells in DCB for “dropped” link (in IMA Root Table): REF_LINK &= ~x (i.e., clear the corresponding link bit in the REF_LINK entry). 4. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2. 5. Software should wait (poll) for the MPC8280 to remove the link from the DCB routine. The corresponding bit in the group table’s LINK_DCB entry will be cleared by the MPC8280 (IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB != REF_LINK). 6. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-62 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 7. Indicate that this link is no longer assigned to a group: ILRCNTL[GA] = 0. 8. Inhibit reception of cells over dropped link in the IMA Root Table: RXPHYEN &= ~x (i.e., clear the corresponding link bit in the RXPHYEN entry). Note, you must reenable (set to 1) the corresponding bit at a later point if you wish to use this link as a non-IMA link. 9. Software should wait (poll) for the MPC8280 to be using the new group order table. This simply ensures that it is safe to modify/re-use the dropped link parameters (i.e., the MPC8280 is no longer using the dropped link’s data structures). Do this by making sure the group order pointer points to the new group order table (at this point, no more cells are extracted out of the dropped link’s DCB), e.g.,: while (dcblink != new_pointer). DCBLINK is an entry in the IGRTE. 10. Indicate that this link is no longer an IMA Link in the IMA Root Table: IMAPHY &= ~x (clear the bit). Note, in a symmetrical operation, this step should be the last one performed (after both RX and TX have been disabled). Setting this bit prematurely will halt transmission/reception on the corresponding link. 34.5.4.5.2 TX Parameters 1. Formulate new group order table with the “dropped” link excluded (see Section 34.4.4.1.3, “Transmit Group Order Table”). 2. Point to new TX Group Order Table in the corresponding IMA Group Transmit Table Entry (IGTTE): TGRPORDER = New Table Offset. 3. Decrement the number of links in the group (IGTTE): TNUMLINKS -= 1. 4. Inhibit transmission of cells over dropped link in the IMA Root Table: TXPHYEN &= ~x (i.e., clear the corresponding link bit in the TXPHYEN entry). Note, you must reenable (set to 1) the corresponding bit at a later point if you wish to use this link as a non-IMA link. 5. Indicate that this link is no longer an IMA Link in the IMA Root Table: IMAPHY &= ~x (clear the bit). Note, in symmetrical operation, this step should be the last one performed (after both RX and TX have been disabled). Setting this bit prematurely will halt transmission/reception on the corresponding link. 34.5.4.6 Link Receive Deactivation Procedure The following procedure assumes that the link was part of the IMA group during the group delay synchronization procedure and that an IFSW (IMA Frame Synchronization Working) event has already been received for the link. 1. Formulate new group order table with the “dropped” link excluded (see Section 34.4.4.2.4, “Receive Group Order Tables"). 2. Decrement RNUMLINKS in the group receive table 3. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to an emptied DCB condition (stalled link, see LS exception). The recommended new value is: STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See Section 34.4.4.2, “IMA Group Receive Table Entry”: IGRTE[STALL_THR] = x. 4. Inhibit storing of cells in DCB for “dropped” link (in IMA Root Table): REF_LINK &= ~x (i.e., clear the corresponding link bit in the REF_LINK entry). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-63 Inverse Multiplexing for ATM (IMA) 5. Indicate that the link should be dropped: ILRCNTL[RXSC] = 2. 6. Software should wait (poll) for the MPC8280 to remove the link from the DCB routine. The corresponding bit in the group table’s LINK_DCB entry will be cleared by the MPC8280 (IMA) (this means no more cells are being stored in the DCB), e.g.,: while (LINK_DCB != REF_LINK). 7. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x. 8. Set the link to filler mode ILRCNTL[RXSC] = 0 9. Initialize the DCB pointers accordingly: DCBSP=DCBFP, DCBRP=Null. 10. Initialize link DCB in external memory to zero. 34.5.4.7 Link Receive Reactivation Procedure The following procedure assumes that the link was part of the IMA group during the group delay synchronization procedure and that an IFSW(IMA Frame Synchronization Working) event has already been received for the link. 1. Indicate that this is a new link (GDS/reconstruction function) by inverting the current “add_new” bit value: ILRCNTL[ADD_NEW] = x. 2. Formulate new group order table with the new link included (see Section 34.4.4.2.4, “Receive Group Order Tables"). 3. Use the new group order table by inverting the current GOTP value: IGRCNTL[GOTP] = x. 4. Increment RNUMLINKS in the group receive table. 5. The “Stall Threshold” needs to be recalculated. This parameter defines the acceptable tolerance to an emptied DCB condition (stalled link, see LS exception). The recommended new value is: STALL_THR = 2 x RNUMLINKS x (3 + RX_FIFO). See Section 34.4.4.2, “IMA Group Receive Table Entry”: IGRTE[STALL_THR] = x. 6. Start the delay compensation process for this link (in IMA Root Table) by setting the corresponding bit in REF_LINK. See Table 34-3. 7. Software must now wait for the link delay synchronization process to complete. A LDS (Link Delay Synchronized) exception will be generated by the MPC8280 as soon as this happens. 8. It is now safe for the link to receive data, set link to “active” mode: ILRCNTL[RXSC] = 01. 34.5.4.8 TRL On-the-Fly Change Procedure Timing Reference Link (TRL) requests (CLAV) drive the distribution of cells to the corresponding link transmit queues. To change the TRL, do the following: 1. Clear TRL bit for the existing TRL: ILTCNTL[TRL] = 0. 2. Set TRL bit for the new TRL: ILTCNTL[TRL] = 1. Only one link must be selected as “TRL” in a group. Note, when operating in IDCR mode (RX only), the timer value programmed was based on the TRL Rate (TRLR) acquired when the group was brought up. It is necessary to restart the entire group if the RX TRL is changed and a new TRLR (see Section 34.4.4.2, “IMA Group Receive Table Entrye Entry”) is expected. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-64 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.5.4.9 Transmit Event Response Procedures The following TX events may take place when operating in IMA mode. It is recommended that all events be handled via an “exception/interrupt service routine” (ISR) as the response time inherent with interrupt driven events should diminish the negative impact/propagation of such events: 1. TQU (Transmit Queue Underrun)—Indicates that a transmit queue was emptied. This implies that the offending link (PHY) is requesting cells at a faster rate relative to the TRL. If the TRL is out of spec, then you will see multiple links reporting TQUs (because all links in the group will be faster relative to the TRL). The offending link should be removed (see Section 34.5.4.5, “Link Removal Procedure”), check the following: PHY, TX Queue depth (start and end pointers should not be the same), TNUMLINKS is equal (not less or greater) than the number of active links. 2. TQO (Transmit Queue Overflow)—Indicates that a transmit queue was not ready to receive a cell (full). This implies that the offending link (PHY) is requesting cells at a slower rate relative to the TRL. If the TRL is out of spec, then you will see multiple links reporting TQOs (because all links in the group will be slower relative to the TRL). The offending link should be removed (see Section 34.5.4.5, “Link Removal Procedure”), check the following: PHY, TX Queue depth (depth should be the same as other queues), TNUMLINKS is equal (not less or greater) than the number of active links. 34.5.4.10 Receive Event Response Procedures The following RX events may take place when operating in IMA mode. It is recommended that all events be handled via an “exception/interrupt service routine” (ISR) as the response time inherent with interrupt driven events should diminish the negative impact/propagation of such events: 1. LS (Link Stalled)—The link’s DCB has emptied, either because the PHY is no longer functioning or it is relatively slower than the other links. The offending link should be removed (see Section 34.5.4.5, “Link Removal Procedure”). Make sure the DCB start and end pointers are not the same. If only one link is used in a group the software must monitor the TC layer to detect that this link has stalled. No LS event is reported in the IMA interrupt queue. To re-start an IMA group properly after link(s) have recovered, the user must reset all the microcode-managed parameters in the IMA receive group to zero. 2. DCBO (DCB Overflow)—Indicates that the Delay Compensation Buffer has no more space. The source of the problem can be varied: 1) the offending PHY is sending at a faster rate (out of spec.), 2) the propagation delay of one of the other links in the group is greater than anticipated (need to make DCB larger) or, 3) the size of the offending link was programmed incorrectly, i.e., smaller (the size of all DCBs in the group should be the same). The offending link should be removed (see Section 34.5.4.5, “Link Removal Procedure”). This exception corresponds to the LODS (Link Out of Delay Synchronization Defect) and should be reported to the FE (via the ICP cell, RxDefect = LODS) of the problem. The MPC8280 will continue to report this exception if the condition persists (unless the event is masked). 3. LDS (Link Delay Synchronized)—Indicates that the new/added link (to an existing group) has achieved synchronization (link delay). The link is capable of receiving data at this point, (see Section 34.5.4.4, “Link Addition Procedure”). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-65 Inverse Multiplexing for ATM (IMA) 4. GDS (Group Delay Synchronized)—Group delay synchronized achieved or group delay synchronized not achieved. In some cases, it is not possible for the GDS to complete. GDS can not complete if a link experiences problems during the GDS process - for example losing SYNC state for the IFSM. If this occurs, it is not possible to determine the links true differential delay with respect to other member links of the group. In order to determine if the GDS process completed successfully, the ucode will set IGRSTATE[GDSS] to either of the following values after the GDS interrupt has been generated: — IGRSTATE[GDSS] = 00 - GDS process failed, a link lost IFSM SYNC during GDS process — IGRSTATE[GDSS] = 11 - GDS process completed Software can then read IGRSTATE[GDSS] and use this status information before deciding whether to change the links to the active state or to try and resynchronize again at the group level. In addition to the above status information, the ILRSTATE[ADD_NEW_M] bit of the link that caused the failure of the GDS process will be flipped such that it is logically inverted with respect to the ILRCNTL[ADD_NEW] bit. It is recommended however, that software, after GDS failure and when restarting the GDS process, changes all of the links in the group to the group unassigned state and then update the link and group parameters to their default values before starting the GDS process again. Note that a link losing SYNC during the GDS process can cause DCBO interrupt for other links in the group. If this situation occurs, the GDS process should be restarted as described above. 5. IFSD (Link (IMA) Frame Synchronization Defect)—Indicates that the link has lost synchronization (e.g., unexpected IFSN value for a number (GAMMA + 2) of consecutive frames). If this condition persists, the link should be removed. The threshold that would trigger the removal of the link is system specific. The IFSD event corresponds to the “Loss of IMA Frame” (LIF) state and the software should react to this by informing the FE (via the ICP cell, RxDefect = LIF) of the problem. If the condition persists, IFSD events will continue to be generated every GAMMA+2 frames. The MPC8280 maintains counters (if enabled) to track the overall “quality” of a particular link: see OIF (Out of IMA Frame) and ICPVIOL (ICP Violation) in Section 34.4.5.3, “IMA Link Receive Statistics Table.” If the link returns to working state, the MPC8280 will automatically perform Link Delay Synchronization and generate an LDS event upon achieving synchronization. The software can use one of the MPC8280 timers as a time stamp when handling IFSD events and check if the “persistence” time threshold has been crossed when subsequent events take place. The LIF state time stamp should be reset when the IFSW event is reported. 6. IFSW (Link (IMA) Frame Synchronization Working)—Indicates that the link is has achieved frame synchronization. This event is reported when a link has been assigned to a group (start-up or link addition) or it was previously assigned and working, but had a defect (see IFSD event). If going from defect to working, the software should update the RxDefect field of the ICP. Again, a time stamp (timer) can be used to measure the “persistence” time. 7. DSL (DCB Synchronization Lost)—Indicates that a link in a group with IGRSTATE[GDSS] = 11 loses synchronization and enters the HUNT state at the IFSM. When this interrupt occurs, the link should be removed by software, and the CPM will no longer perform the automatic LASR procedure. Note that when the interrupt is generated, the ILRSTATE[DL] bit is set, and the software should clear the IMA group and link receive state information as described above for the GDS interrupt. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-66 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 34.5.4.11 Test Pattern Procedure Test patterns are used verify “connectivity” of a link in a particular group. The NE will request, via an ICP cell, that a test pattern be looped back to the FE over all links currently in the group. For this test, the FE will look only at ICP cells received over the link being tested (LID = x) and upon receiving an ICP cell “echo” the pattern back to the NE over all the links in the group. The major task of initiating and verifying the pattern on all the links in the group falls on the software. The MPC8280 will simply transmit and receive the modified/changed ICP cells. If the software detects that the pattern was “echoed” by the FE, then connectivity is verified. 34.5.4.11.1 As Initiator (NE) Alter the (unused) ICP cell template to the “Test Link” command to the FE: 1. Tx Test Control = Set to “Active” and select LID (link) to be tested. 2. Tx Pattern = X (0-255). 3. Increment SCCI. 4. Make this the active ICP template (see Section 34.5.4.1, “Transmit ICP Cell Signalling”). 5. Repeat steps 1-4 until expected pattern is received in any of the incoming ICP cells (alternate ICP templates must be used). After sending the request to perform the test (pattern) to the FE, the NE software must wait for the TX test pattern to be echoed back/received in the RX Pattern field of the ICP cell (any of the active links in the group can be monitored for the RX Pattern). After verifying connectivity, the test can be de-activated (set Tx Test Control = “Inactive” and repeat steps 3 and 4 above). 34.5.4.11.2 As Responder (FE) When the FE receives a request to perform the “pattern” test on any of the active links, it must monitor the selected link (see Tx LID of Tx Test Control) for reception of an ICP cell. Upon receiving an ICP cell (remember, the other end is incrementing the SCCI field), the software should copy the Tx Pattern to the Rx Pattern field of the ICP Cell and transmit the ICP cell. Alter the ICP cell: 1. Rx Pattern = Tx Pattern (of received ICP Cell). 2. Increment SCCI 3. Make this the active ICP template (see Section 34.5.4.1, “Transmit ICP Cell Signalling”). 4. Repeat steps 1-3 until the test is inactive. There are two ways to monitor the link under test. The first method is to simply look for the expected LID in the received ICP cells (ICP cell buffer). For this to happen, all links in the group must have MON_ICP bit set: 1. Monitor link for changes in SCCI: ILRCNTL[MON_ICP] = 1. Now, since changed ICP cells are passed to the ICP buffer only when the SCCI field changes, then it may take some time for the link under test to pass on an ICP cell. Again, ICP cells will be passed on to the buffer MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-67 Inverse Multiplexing for ATM (IMA) for the first link encountered in which a change (SCCI) is detected, it may or may not be the link under test. An alternate method is to monitor only the link under test: 1. Don’t Monitor link for changes in SCCI for all links except link under test: ILRCNTL[MON_ICP] = 0 (alter the corresponding Link Table Entries). 2. Monitor link under test for changes in SCCI: ILRCNTL[MON_ICP] = 1. This will allow only changed ICP cells for the link under test to be passed on to the ICP Cell buffer. 34.5.4.12 IDCR Operation The ATM stream reconstruction (RX) can be driven alternatively by another clock source (as opposed to triggered by the arrival of cells/CLAV). The reconstruction rate (IMA Data Cell Rate (IDCR)) clock can be generated by an external clock or by one of the MPC8280’s baud rate generators (BRGs). Note that the designated Rx TRL is used to record the TRLR (TRL Rate) and this is only captured once, when a group’s GDS process is initialized. After, GDS is completed, the TRLR cannot be updated (unless the group is re-initialized. 34.5.4.12.1 IDCR Start-up There are some basic initialization steps that must be performed before any of the groups are activated and make use of IDCR stream reconstruction. These steps should only be performed once: 1. Configure the base offset of the IDCR Table in the IMA Root table: IMAROOT[IDCR_BASE] = x. 2. Reset (to zero) the IDCR tick counter: IMAROOT[IDCRTICK] = 0. 3. Reset (to zero) the IDCR in Service field: IMAROOT[IDCR_SVC] = 0. 4. Reset (to zero) the IDCR_EN field: IMAROOT[IDCREN] = 0. Subsequently, any groups operating in IDCR mode will require that this field be updated (ORed) to enable IDCR mode (e.g. set bit for the corresponding group). 5. Since we have no active groups, configure IMAROOT[IDCR_LAST] to zero. As additional groups are created/added, this field must also be modified accordingly with the group number (groups are numbered 0-7). 6. Copy existing ATM parameter RAM contents to shadow RAM parameter space. For example, if DREQ1 is used then page 8 (parameter RAM offset 0x8700) must be used as the shadow RAM. If DREQ2 is used, then page 9 must be used, and so on. Note that the corresponding functionality previously available and mapped to that page (e.g., MCC1, MCC2, etc.) will no longer be available. 7. The shadow RAM must use a different address for the RCELL_TMP_BASE. Program a different address (different than existing value being used) in RCELL_TMP_BASE. See Section 34.4.8.2.2, “Programming the FCC Parameter Shadow.” 8. Program PIO registers: Indicate which pin is being used as the IDCR input (i.e., DREQx). The port and pin selection is configurable and is driven by what other resources are being used on the MPC8280 (e.g., Port C can be used of DREQ1 or DREQ2). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-68 Freescale Semiconductor Inverse Multiplexing for ATM (IMA) 9. Program to appropriate rate and enable timer if using a BRG (refer to Chapter 17, “Baud-Rate Generators (BRGs)”): TMRx, TRRx, and TGCRx. Note: This is only required if the IDCR clock is supplied by the MPC8280. If an external source is used, this step can be skipped. An external connection (physical) is required between the output of the BRG (TOUTx) and DREQx (see step 7 above). 10. Enable IDMAx interrupts (refer to Section 19.8.4, “IDMA Event Register (IDSR) and Mask Register (IDMR)”). 11. Clear IDCR table entries (reset to zero). 12. Issue the IDCR Initialization command (see Section 34.4.8.3, “IDCR_Init Command”). After this point, the IDCR mechanism can be used. 34.5.4.12.2 Activating a Group in IDCR Mode The following steps are required when activating a group in IDCR mode. 1. Configure the corresponding group to operate in IDCR mode: IGRCNTL[IDCR] = 1. 2. Indicate which is the last group that has IDCR enabled. Groups are numbered 0-7. As additional groups are created/added or removed, this field must also be modified accordingly with the group number of the last group (in the order of 0-7) that has IDCR enabled. For example, lets say groups 0 and 1 are active and group 2 is being added. Then IMAROOT[IDCR_LAST] = 2. 3. After GDS has been achieved, the software can now read the captured TRLR value (see IGRTE[TRLR]). At this point, the group’s corresponding IDCR Table Entry can be programmed. IDCRCNT and IDCRREQ are both initialized to the integer part of: ((TRLR/(num_links x 128)) x (2048/2049)). IDCRCNTF and IDCRREQF are both initialized to the fraction value of the previous equation times 65536. For example, lets say ((TRLR/(num_links x 128)) x (2048/2049)) yielded 10.45, then IDCRCNT and IDCRREQ would equal 10. IDCRCNTF and IDCRREQF would then be set to (.45 x 65536) = 29491 (0x7333). 4. Once the IDCR Table has been programmed, IDCR driven stream reconstruction for this group can start: IMAROOT[IDCREN] |= x. The corresponding bit must be cleared if this group is being deactivated/removed from a multi-group configuration. 34.5.4.13 End-to-End Channel Signalling Procedure 34.5.4.13.1 Transmit The end-to-end channel signalling field can be used by software to signal to the far end. Because the end-to-end channel is not covered by the SCCI field and there are no standard requirements for the minimum number of frames between changes of the end-to-end channel field, it is not necessary to follow the procedure for ICP cell signalling in order to do this; instead, the end-to-end channel field of the ICP template currently in use can be directly updated. However, if a minimum number of frames between changes is desired, then the procedure for ICP cell signalling can be used, skipping the step in which the SCCI is updated. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 34-69 Inverse Multiplexing for ATM (IMA) 34.5.4.13.2 Receive No special facility is included for reception of the end-to-end channel. The end-to-end channel field is part of the received ICP cells, so its information can be read by software from those cells. However, ICP cells are only received when the SCCI field changes, so changes in the end-to-end channel will not be received until the SCCI field also changes (when there is a change in the status and/or control of the far end). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 34-70 Freescale Semiconductor Chapter 35 ATM Transmission Convergence Layer NOTE The functionality described in this chapter is available only on the MPC8280. The MPC8280 can support applications which receive ATM traffic over the standard serial protocols like E1, T1, and xDSL via its serial interface (SIx TDMx) ports because the ATM TC-layer functionality is implemented internally. This allows the use of standard low-cost PHY devices in system applications instead of PHYs that support UTOPIA bus devices. A typical TC layer application requires the use of one SI TDM channel per TC block. As shown in Figure 35-1, all TC blocks are internally connected to FCC2. In addition, Figure 35-1 shows FCC1 connected to a UTOPIA 16-bit MPHY bus which can be routed outside and operated independently of the TC blocks. UTOPIA level-2 8-/16-bit bus FCC1 SIx UTOPIA level-2 8-bit bus TDMx TC Blocks FCC2 DPR FCC3 Figure 35-1. Serial ATM Using FCC2 and TC Blocks (Single Channel) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-1 ATM Transmission Convergence Layer 35.1 Features Primary features of the TC layer include the following: • Eight TDM channels routed in hardware to eight TC layer blocks — Protocol-specific overhead bits may be discarded or routed to other controllers by the SI — Performing ATM TC layer functions (according to ITU-T I.432) — Transmit (Tx) updates are as follows: – Cell HEC generation – Payload scrambling using self synchronizing scrambler (programmable by the user) – Coset generation (programmable by the user) – Cell rate by inserting idle cells — Receive (Rx) updates are as follows: – Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA parameters for the delineation state machine – Payload descrambling using self synchronizing scrambler (programmable by the user) – Coset removing (programmable by the user) – Filtering idle/unassigned cells (programmable by the user) – Performing HEC error detection and single bit error correction (programmable by the user) – Generating loss of cell delineation status/interrupt (LOC / LCD) • Operates with FCC2 (UTOPIA 8) • Serial loop back mode • Cell echo mode • Supports both FCC transmit modes: — External rate mode—Idle cells are generated by the FCC (microcode) to control data rate — Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate. The TC layer generates idle/unassigned cells to maintain the line bit rate • Supports the TC layer and PMD (physical medium dependent) WIRE interface (according to the ATM-Forum af-phy-0063.000) • Cell counters for performance monitoring: — 16-bit counters count: – HEC errored cells – HEC single bit errored and corrected cells – Idle/unassigned cells filtered – Idle/unassigned cells transmitted – Transmitted ATM cells – Received ATM cells — Maskable interrupt sent to the host when a counter expires MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-2 Freescale Semiconductor ATM Transmission Convergence Layer • • Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps are supported. 35.2 Functionality The TC layer block is shown in Figure 35-2. The transmit and the receive parts are independent; the only case in which they are synchronized is in cell echo mode. MPC8280 60x Bus Registers FCC2 Rx Cell Functions Rx Serial I/F • cell delineation • descrambling • coset • HEC error detection and correction Rx FIFO M-PHY UTOPIA Rx I/F Rx Rx UTOPIA I/F (PHY) Counters Tx M-PHY UTOPIA Tx I/F Tx Cell Functions Tx Serial I/F • HEC generation • scrambling • coset • rate adaptation Tx FIFO SI PHY one channel TC Layer Tx UTOPIA I/F (PHY) Figure 35-2. TC Layer Block Diagram 35.2.1 Receive ATM Cell Functions The ATM receive cell functions block (RCF) performs the receive functions of the TC block. It performs cell delineation, cell payload descrambling, HEC verification and correction, and idle/unassigned cell filtering. Cell delineation is the process of framing data to ATM cell boundaries using the header error check (HEC) received in the ATM cell header. The HEC is a CRC-8 calculation over the first four octets of the ATM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-3 ATM Transmission Convergence Layer cell header. The cell delineation algorithm assumes that repetitive correct HEC calculations over consecutive cells indicate valid ATM cell boundaries. The RCF performs a sequential bit by bit hunt for a correct HEC sequence. While performing this hunt, the cell delineation state machine is in HUNT state. When a correct HEC is found, the RCF locks on the particular cell boundary and enters the PRESYNCH state, which indicates that the previously detected HEC pattern is not a false indication. If a correct HEC pattern is false, an incorrect HEC is received within the next DELTA cells. If an incorrect cell is detected, then a transition to the HUNT state is made. If an incorrect HEC is not detected in the PRESYNCH state, a transition to the SYNCH state is made. In the SYNCH state, the TC is assumed to be synchronized so that other functions can be applied to the received cell. A transition back to the HUNT state is made only after ALPHA consecutive incorrect HEC patterns are detected. The cell delineation state machine is shown in Figure 35-3. The ALPHA and DELTA parameters determine the robustness of the delineation method. ALPHA determines the robustness against false misalignment due to bit errors. DELTA determines the robustness against false delineation in the synchronization. Both parameters are programmable for each TC block and are provided to help tune the system according to the line error characteristics of a specific application. Bit-by-Bit Correct HEC HUNT ALPHA Consecutive Incorrect HEC Incorrect HEC Cell-by-Cell PRESYNCH SYNCH DELTA Consecutive Correct HEC Cell-by-Cell Figure 35-3. TC Cell Delineation State Machine The RCF descrambles (programmable) the cell payload using the self-synchronizing descrambler with a polynomial of x43 + 1. The HEC calculation is a CRC-8 calculation over the first four octets of the ATM cell header. The RCF verifies the received HEC using the accumulation polynomial, x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HEC octet before comparison with the calculated result (programmable). The RCF can perform single bit error correction on the header. If multiple bit errors are found in the HEC, the cell is discarded. If the single bit error correction mode is not enabled (TCMODE[SBC] = 1), the cell is also discarded when a single bit error is found in the header. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-4 Freescale Semiconductor ATM Transmission Convergence Layer When the cell delineation state machine is in the SYNCH state, the HEC verification state machine (see Figure 35-4) implements the correction algorithm. This state machine makes sure that a single cell header is corrected at a time. If consecutive cells are detected with single bit errors in their headers, only the first cell error is corrected and the rest are discarded. This state machine reduces the probability of the delivery of cells with errored headers under bursty error conditions. Multi-bit error detected (Cell discarded) No error detected (No action) Correction Mode No error detected Detection Mode Error detected (Cell discarded) Single-bit error detected (correction) Figure 35-4. HEC: Receiver Modes of Operation The RCF can also perform idle/unassigned cell filtering. Both features are programmable (TCMODE[CF]). Cells that are detected to be idle/unassigned are discarded, that is, not forwarded to the UTOPIA interface Rx FIFO. 35.2.1.1 Receive ATM 2-Cell FIFO The receive FIFO provides FIFO management and an interface to the UTOPIA receive cell interface. The receive FIFO can hold two ATM cells, thereby providing the cell rate decoupling function between the transmission system physical layer and the ATM layer. FIFO management includes filling the FIFO, indicating to the UTOPIA interface that it contains cells, maintaining the FIFO read and write pointers, and detecting FIFO overrun (TCER[OR]) conditions. 35.2.2 Transmit ATM Cell Functions The transmit ATM cell functions block (TCF) performs the ATM cell payload scrambling and is responsible for the HEC generation and the idle cell generation. The TCF scrambles (programmable by the user) the cell payload using the self-synchronizing scrambler with polynomial x43 + 1. The HEC is generated using the polynomial x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) (programmable by the user) to the calculated HEC octet. The result overwrites the HEC octet on the transmitted cell. When the transmit FIFO is empty, the TCF inserts idle cells (counted in ICC). The TCF accumulates the number of transmitted assigned cells in a counter (TCC). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-5 ATM Transmission Convergence Layer 35.2.2.1 Transmit ATM 2-Cell FIFO The transmit FIFO provides FIFO management and an interface to the UTOPIA transmit interface. The FIFO provides the cell rate decoupling between the transmission system physical layer and the ATM layer. The FIFO management includes emptying cells from the transmit FIFO, indicating to the UTOPIA interface that it is full, maintaining the FIFO read and write pointers, and detecting FIFO underrun (TCER[UR]) conditions. 35.2.3 Receive UTOPIA Interface This block performs the receive interface with the FCC via the UTOPIA bus. It implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface. 35.2.4 Transmit UTOPIA Interface This block performs the transmit interface with the FCC via the UTOPIA bus. It implements the UTOPIA level-2 (multi-PHY) 8-bit PMD side (slave) interface. 35.3 Signals The TC layer is operated via an SI TDM port using a serial protocol. Synchronization signals are required for some applications and must be supported. Table 35-1 describes the signals required for operating the TC layer. Table 35-1. TC Layer Signals Signal Txc Txd Txsyn Rxc Rxd Rxsyn Direction Input Output Input Input Input Input Description Tx clock. Clocks Tx data out of the TC to external device. Tx data from TC to external device. Tx synch. Synchronizes the transmit data to the beginning of a frame. Rx clock. Clocks the data into the TC. Rx data. From external device to the TC. Rx synch. Synchronizes the received data. 35.4 TC Layer Programming Mode This section describes the TC layer-specific registers and other programming model features. For a complete and concise list of TC layer registers, refer to Chapter 3, “Memory Map.” 35.4.1 TC Layer Registers Each TC layer block is controlled by registers located in the block and accessed from the 60x bus. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-6 Freescale Semiconductor ATM Transmission Convergence Layer 35.4.1.1 TC Layer Mode Registers 1–8 (TCMODEx) Each TC layer block is configured using a TC layer mode register TCMODEx, as shown in Figure 35-5. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field RXEN Reset R/W TXEN RPS TPS RC TC SBC CF URE LB TBA IMA SM CM 0000_0000_0000_0000 R/W Figure 35-5. TC Layer Mode Registers (TCMODEx) Table 35-2 describes TCMODE fields. Table 35-2. TCMODEx Field Descriptions Bits 0 Name RXEN Description TC Layer Rx enable bit. Enables the TC Layer Rx block operation: 0 TC Layer Rx operation is disabled. 1 TC Layer Rx operation is enabled. TC Layer Tx enable bit. Enables the TC Layer Tx block operation: 0 TC Layer Tx operation is disabled. 1 TC Layer Tx operation is enabled. Rx Payload DeScrambling 0 Payload descrambling is performed on received payload data. 1 No payload descrambling is performed on received payload data. Tx Payload Scrambling 0 Payload scrambling is performed on transmitted payload data. 1 No payload scrambling is performed on transmitted payload data. Rx Coset Enable 0 XOR with 0xAA is done on received HEC. 1 No XOR with 0xAA is done on received HEC. Tx Coset Enable 0 XOR with 0xAA is done on transmitted HEC. 1 No XOR with 0xAA is done on transmitted HEC. Header Single Bit error Correction 0 Perform single bit error correction on the header according to HEC while in Synch mode. 1 Do not perform single bit error correction on the header. Rx Idle/Unassigned Cells Filtering 00 No cell filtering is done on Rx cells. 01 Idle cell filtering is done - idle cells are discarded. 10 Unassigned cell filtering is done - unassigned cells are discarded. 11 Idle and unassigned cell filtering is done - both idle and unassigned cells are discarded. The Header of idle cell (ITU-T I.361): b00000000_00000000_00000000_00000001 The Header of unassigned cell (ITU-T I.361): b00000000_00000000_00000000_0000xxx0 Note that physical layer cells bypass the TC layer; they are not filtered. Also note that the filter works on the header only and ignores the HEC. 1 TXEN 2 RPS 3 TPS 4 RC 5 TC 6 SBC 7–8 CF MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-7 ATM Transmission Convergence Layer Table 35-2. TCMODEx Field Descriptions (continued) Bits 9 Name URE Description Underrun interrupt (TCER[UR]) enable. Underrun interrupt may be set when Idle cell is generated by the TC. 0 Underrun interrupt disabled. 1 Underrun interrupt enabled. Loopback/echo modes 00 Normal operation. 01 Cell echo mode operation. Received cells are transmitted and do not go out to the UTOPIA bus. 10 Data loopback mode operation. Transmit data stream is connected to the receive data stream. 11 Not used. Note that for echo mode operation, TCMODE[SM] should be cleared, independent of the FCC multi-PHY mode configuration. 12 TBA Tx Byte align 0 Tx data is transferred as soon as it is enabled. 1 Tx data is transferred byte aligned to the Txsyn signal. IMA mode 0 Rx is not in IMA. 1 Rx is in IMA mode. Single mode 0 TC is not the only PHY on UTOPIA 1 TC is the only PHY on UTOPIA Cell counters mode 0 Reading a cell counter clears the counter. 1 Reading a cell counter does not change the counter’s value. 10–11 LB 13 IMA 14 SM 15 CM 35.4.1.2 Cell Delineation State Machine Registers 1–8 (CDSMRx) The cell delineation state machine register (CDSMRx), as shown in Figure 35-6, holds the ALPHA and DELTA parameters of the cell delineation state machine. 0 4 5 9 10 15 Field Reset R/W ALPHA DELTA 0000_0000_0000_0000 R/W — Figure 35-6. Cell Delineation State Machine Registers (CDSMRx) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-8 Freescale Semiconductor ATM Transmission Convergence Layer Table 35-3 describes CDSMR fields. Table 35-3. CDSMRx Field Descriptions Bits 0–4 5–9 10–15 Name ALPHA DELTA — Description ALPHA consecutive received cells with incorrect HEC are counted by the cell delineation state machine to pass from state SYNCH to state HUNT. DELTA consecutive received cells with correct HEC are counted by the cell delineation state machine to pass from state PRESYNCH to state SYNCH. Reserved 35.4.1.3 TC Layer Event Registers 1–8 (TCERx) The TC layer event registers (TCERx), as shown in Figure 35-7, records error events for each TC block. TCER event bits are cleared by writing ones to them. 0 1 2 3 4 5 9 10 11 12 13 14 15 Field Reset R/W OR UR CDT MS PARE — 0000_0000_0000_0000 R/W ROF TOF EOF COF IOF FOF Figure 35-7. TC Layer Event Registers (TCERx) The TCER bits are described in Table 35-4. Table 35-4. TCERx Field Descriptions Bits 0 1 Name OR UR Description Overrun. Rx FIFO OverFlow. Set when Rx FIFO is full and another complete cell is received. The cell is discarded. Underrun. No ATM cell to transmit. Set when the Tx FIFO is empty and the transmission of a cell is completed. An idle cell is sent. This interrupt is enabled only if TCMODE[URE] is set. The idle cell header is: 0x00000001 (I.432), whose HEC is: 0x52 The idle cell payload is:0x6A (I.432). Cell delineation toggled. Set when the cell delineation bit (CD) in TCGSR has changed. Misplaced Txsyn signal Set when Txsyn is out of place. (The first Txsyn is by definition always in place.) Parity event Set when parity from UTOPIA to transmit is wrong. Reserved Received cell counter overflow Set when the received cells counter passes its maximum value. Transmitted cell counter overflow Set when the transmitted cells counter passes its maximum value. 2 3 4 5–9 10 11 CDT MS PARE — ROF TOF MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-9 ATM Transmission Convergence Layer Table 35-4. TCERx Field Descriptions (continued) Bits 12 13 14 15 Name EOF COF IOF FOF Description Errored cells counter overflow Set when the errored cells counter passes its maximum value. Corrected cells counter overflow Set when the corrected cells counter passes its maximum value. Tx Idle cells counter overflow Set when the Tx idle cells counter passes its maximum value. Filtered cells counter overflow Set when the filtered cells counter passes its maximum value. 35.4.1.4 TC Layer Mask Register (TCMRx) This register’s field description is identical to that of TCER (refer to Section 35.4.1.3, “TC Layer Event Registers 1–8 (TCERx)”). Each bit that is set in TCMR enables an interrupt when the corresponding bit in TCER is set. 35.4.2 TC Layer General Registers The TC layer general registers are registers that are distributed to all of the TC blocks. Each TC block is represented by specific bits. When accessing a general register each TC block is responsible for its specific bits only. 35.4.2.1 TC Layer General Event Register (TCGER) The TC layer general event register (TCGER), as shown in Figure 35-8, summarizes the events for all the TC blocks. Each bit stands for an ORed event register of a TC block. Once a bit is set, it indicates that one or more event bits are set in the corresponding TC block event register. 0 1 2 3 4 5 6 7 8 15 Field TC1 Reset R/W TC2 TC3 TC4 TC5 TC6 TC7 TC8 — 0000_0000_0000_0000 R/W Figure 35-8. TC Layer General Event Register (TCGER) Table 35-5 describes TCGER fields. Table 35-5. TCGER Field Descriptions Bits 0 1 2 Name TC1 TC2 TC3 Description One bit or more is set in TC1 event register. One bit or more is set in TC2 event register. One bit or more is set in TC3 event register. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-10 Freescale Semiconductor ATM Transmission Convergence Layer Table 35-5. TCGER Field Descriptions (continued) Bits 3 4 5 6 7 Name TC4 TC5 TC6 TC7 TC8 Description One bit or more is set in TC4 event register. One bit or more is set in TC5 event register. One bit or more is set in TC6 event register. One bit or more is set in TC7 event register. One bit or more is set in TC8 event register. 35.4.2.2 TC Layer General Status Register (TCGSR) Figure 35-9 shows the TC layer general status register (TCGSR), which records the cell delineation and transmit FIFO status for all TC blocks. 0 1 2 3 4 5 6 7 8 15 Field CD1 Reset R/W CD2 CD3 CD4 CD5 CD6 CD7 CD8 — 0000_0000_0000_0000 R Figure 35-9. TC Layer General Status Register (TCGSR) Table 35-6 describes TCGSR fields. f Table 35-6. TCGSR Field Descriptions Bits 0–7 Name CDx Description Cell Delineation. The cell delineation state machine status of TCx. 0 Cell delineation state machine is in Hunt or Pre-Synch modes. 1 Cell delineation machine is in Synch mode. Reserved 8–15 — 35.4.3 TC Layer Cell Counters Each TC block maintains six memory-mapped 16-bit performance cell counters that are updated during operation and can be read by the host. If a counter overflows, it wraps back to zero and generates a maskable interrupt. These counters are automatically cleared when read if TCMODE[CM] = 0; see Section 35.4.1.1, “TC Layer Mode Registers 1–8 (TCMODEx).” 35.4.3.1 Received Cell Counters 1–8 (TC_RCCx) This cell counter is updated whenever a received cell without HEC errors is passed to the Rx UTOPIA FIFO. 35.4.3.2 Transmitted Cell Counters 1–8 (TC_TCCx) This cell counter is updated whenever the transmission of a cell is completed. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-11 ATM Transmission Convergence Layer 35.4.3.3 Errored Cell Counters 1–8 (TC_ECCx) This cell counter is updated whenever a received errored cell (cell with header error) is discarded. 35.4.3.4 Corrected Cell Counters 1–8 (TC_CCCx) This cell counter is updated whenever a received cell with a HEC single bit error is corrected. If header single bit error correction is not enabled (TCMODE[SBC] is set), this counter is not updated. (All errored cells are counted by the errored cell counter (ECC).) 35.4.3.5 Transmitted IDLE Cell Counters 1–8 (TC_ICCx) This cell counter is updated whenever an idle cell is transmitted. 35.4.3.6 Filtered Cell Counters 1–8 (TC_FCCx) This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are not enabled (TCMODE[CF] is cleared), this counter is not updated. 35.4.4 Programming FCC2 FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the UTOPIA bus internally. FCC2 should be programmed to work with the TC blocks as if the TC blocks are external PHYs located on the lowest eight (or fewer) addresses. 35.4.5 35.4.5.1 Programming and Operating the TC Layer Receive The TC layer receive operation is enabled by setting TCMODEx[RXEN]. The host software polls the CD bits of each enabled TC layer block to see that its receive cell delineation state machines are synchronized. For each TC layer block that is synchronized, the host clears TCERx[CDT]. Once all the enabled TC layer blocks are synchronized, the host terminates its initialization routine, and the system starts normal operation. Once a TC block gets out of synchronization, the corresponding TCGSR[CD] is cleared. This change then causes a TCER[CDT] interrupt to the host (if enabled in the mask register—TCMRx). On the receive path, the TC layer receives the bit stream via the SI and does the following: 1. Attempts to gain synchronization on the ATM cell boundaries by checking each byte against the HEC calculated on the preceding 32 bits (ATM cell header candidate). 2. Once synchronized: — Performs the descrambling function on the cell payload (if enabled) — Performs the coset function on the HEC (if enabled) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-12 Freescale Semiconductor ATM Transmission Convergence Layer — Checks for HEC errors and corrects single HEC errors when found (again, if enabled). Cells containing multi-bit header errors (at least 2 errors) are discarded. Idle and unassigned cells are filtered (discarded) when detected (if the filters are enabled). Once an ATM cell’s processing is complete, it is passed to the TC layer receive FIFO and the internal TC layer cell counters are updated. The cell is passed from the TC layer receive FIFO via the internal UTOPIA interface to the FCC2 receive FIFO. An overrun condition occurs when the TC layer receive FIFO is full and the FCC is unable to read a cell from it (via the internal UTOPIA interface) before another valid cell is received. The incoming cell is discarded and TCER[OR] interrupt is sent to the host (if enabled in the mask register—TCMRx). 35.4.5.2 Transmit The TC layer transmit operation is enabled by setting TCMODEx[TXEN]. The TC layer requests ATM cells for transmission via the internal UTOPIA interface. Then, when the ATM cell is passed to the TC layer transmit block, it is stored in the TC layer transmit FIFO. When the ATM cell is to be transmitted, it is read and processed from the TC layer transmit FIFO. The scrambling function is performed on the ATM cell payload if TCMODEx[TPS] = 1. The ATM cell header HEC value is calculated and the coset function is performed on the HEC if TCMODEx[TC] = 1. The ATM cell is then sent to the PHY via the SI. Once ATM cell transmission is complete, the relevant TC layer cell counters are updated. When a TC layer cell counter overflows, an interrupt (TCERx[TOF]) is set (if enabled in the corresponding TCMRx[TOF]). The TC layer is responsible for providing the data rate required by the physical medium device (PMD). On MPC8280 there are two ATM transmit modes. Users should refer to Section 31.2.1.5, “Transmit External Rate and Internal Rate Modes,” for more details. The following text and figures are specific to TC layer operation. • External Rate—In general, the TC would never have its transmit FIFO empty, and thus would not need to generate idle cells. However, if the CPM is busy and if the transmit FIFO is empty, the TC layer generates an idle cell and an underrun condition will occur. If TCMODEx[URE] = 1, the TCERx[UR] interrupt is sent to the host (if not masked). See Figure 35-10. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-13 ATM Transmission Convergence Layer . MPC8280 Keep FCC FIFO full Generate Idle Cells cell_req 2M Serial Rate 2M Cell Rate ATM Channels CP UTOPIA BTM PHY Idle Cell ATM Cell TC FCC (External Rate) DPR Figure 35-10. TC Operation in FCC External Rate Mode • Internal Rate (Sub Rate)—The TC layer continues to request ATM cells and transmits idle cells. TCERx[UR] interrupts can by disabled by clearing TCMODEx[URE] until a valid ATM cell is transmitted via the internal UTOPIA bus from FCC2 to the TC layer FIFO. See Figure 35-11. MPC8280 1M Sub Rate BRG Generate Cell Req cell req 2M Serial Rate 1M Cell Sub Rate ATM Channels CP Write to FIFO ATM Cells Only UTOPIA BTM PHY TC Generate Idle Cells FCC (Internal/Sub Rate) DPR Idle cell ATM cell Figure 35-11. TC Operation in FCC Internal Rate Mode (Sub Rate Mode) Operation in byte-aligned mode (TCMODE[xTBA] = 1) is required for T1/E1 mainly. In this mode, once the TC is enabled, it waits for the first Txsyn pulse to start transmit the first byte of the first cell. This ensures that subsequent Txsyn pulses are byte-aligned to the cell boundaries. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-14 Freescale Semiconductor ATM Transmission Convergence Layer 35.5 Implementation Example Figure 35-12 shows the MPC8280 connected to two PHY devices, each containing four T1 framers. The eight T1 bit streams are connected to the eight MPC8280 SI TDMs and routed via the SI to the eight TC layer blocks. The eight TC layer blocks, each with its own address, are connected internally to FCC2 via the UTOPIA 8-bit bus. Another ATM stream is managed by FCC1 via the UTOPIA 16-bit bus connected to a SONET 155-Mbps PHY. MPC8280 SONET 155 mbps PHY FCC1 UTOPIA 16-bit bus UTOPIA 8-bit bus PHY 4*1.5 mbps 4 channel T1 Framer FCC2 SI-1 TDMa TDMb TDMc TDMd 8*1.5 mbps DPR 4 channel T1 Framer PHY 4*1.5 mbps TDMa TDMb TDMc TDMd TC SI-2 Figure 35-12. Example of Serial ATM Application 35.5.1 Operating the TC Layer at Higher Frequencies The operation of the TC layer requires a minimum frequency ratio of 1:2.5 between the serial clock and the UTOPIA clock (in Rx and Tx separately). Using the TC for serial frequencies greater than 10 MHz requires using higher UTOPIA frequencies to preserve that ratio. 35.5.2 Programming a T1 Application This section describes the configurations necessary to implement a T1 application using a single TC layer block. Note that using two or more TCs requires FCC2 to work in MPHY mode. Assuming that the MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-15 ATM Transmission Convergence Layer required ATM parameters and data structures have been setup and initialized, implementing a T1 application requires the following steps: 1. Program FCC2 2. Setup I/O Ports and Clocks 3. Enable Tx/Rx on FCC2 4. Program CPM MUX 5. Program the TC block 6. Program the Serial Interface (SI) 7. Enable TDM Step 1 To setup and initialize FCC2, program the FPSMR and GFMR as shown in Table 14. This is for working with one TC block operating in a single PHY environment. The transmitter and receiver should not be enabled at this time. In this example, FCC2 does not discard idle cells. Table 35-7. Programming GFMR and FPSMR to Setup the FCC2 Init Values FPSMR2 = 0x0080_0000 GFMR2 = 0x0000_000A Description UTOPIA Rx and Tx in Master Mode, Idle cells are not discarded ATM Protocol Mode, Receiver and Transmitter are disabled Step 2 Because the FCC2 UTOPIA bus is connected internally to the TC UTOPIA bus, program the parallel ports and BRGs for the active TDM(s). Step 3 To enable receiving and transmitting, FCC2 should be programmed as shown in Table 15. Table 35-8. Enable FCC2 Init Values GFMR2 = 0x0000_003A Enable Rx and Tx Description Step 4 To define the connection of FCC2, the CPM MUX should be programmed as shown in Table 16. Table 35-9. Programming the CPM MUX for a TI Application Init Values CMXFCR = 0x0080_0000 CMXUAR = 0x0000 Description FCC2 is connected to the TC Layer FCC2 as UTOPIA master MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-16 Freescale Semiconductor ATM Transmission Convergence Layer Step 5 The TCx layer block should be configured using the TCMODEx and CDSMR1 registers as shown in Table 17. Note that the TC layer must be enabled after both FCC2 and CPM MUX have been programmed. Table 35-10. Programming the TC Layer Block Init Values TCMODE1 = 0xC202 CDSMR1 = 0x3980 Description Enable TC Layer Rx and Tx, no error correction on header, the TC is the only PHY on UTOPIA ALPHA = 7, DELTA = 6 (default values) Step 6 Program the SI to retrieve the data bits (192 bits) out of the T1 frame (193 bits). The SI frame pattern is programmed in the SI RAM (Rx or Tx), as shown in Table 18. Table 35-11. Programming the SI RAM (Rx or Tx) for a T1 Application Init Values SI_RAM[00]=0x0000 SI_RAM[02]=0x015E SI_RAM[04]=0x015E SI_RAM[06]=0x015F 1 bit is ignored. Route 8 bytes to FCC2. Route 8 bytes to FCC2. Route 8 bytes to FCC2 and go back to the first entry in table. Description Step 7 The last step in this example is to initialize the serial interface registers and enable TDM—in this case TDMa on SI1 as shown in Table 19. Table 35-12. Programming SI Registers to Enable TDM Init Values SI1AMR = 0x0040 SI1GMR = 01 Description Common Receive and Transmit Pins for TDMa Enable TDMa MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 35-17 ATM Transmission Convergence Layer MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 35-18 Freescale Semiconductor Chapter 36 Fast Ethernet Controller The Ethernet IEEE 802.3 protocol is a widely-used LAN based on the carrier-sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted. Ethernet/IEEE 802.3 frames are based on the frame structure shown in Figure 36-1. Frame Length is 64–1,518 Bytes Preamble 7 Bytes Start Frame Destination Delimiter Address 1 Byte 6 Bytes Source Address 6 Bytes Type/ Length 2 Bytes Data 46–1500 Bytes Frame Check Sequence 4 Bytes Note: The lsb of each octet is transmitted first. Figure 36-1. Ethernet Frame Structure The elements of an Ethernet frame are as follows: • 7-byte preamble of alternating ones and zeros. • Start frame delimiter (SFD)—Signifies the beginning of the frame. • 48-bit destination address. • 48-bit source address. Original versions of the IEEE 802.3 specification allowed 16-bit addressing, which has never been used widely. • Ethernet type field/IEEE 802.3 length field. The type field signifies the protocol used in the rest of the frame, such as TCP/IP; the length field specifies the length of the data portion of the frame. For Ethernet and IEEE 802.3 frames to exist on the same LAN, the length field must be unique from any type fields used in Ethernet. This requirement limits the length of the data portion of the frame to 1,500 bytes and, therefore, the total frame length to 1,518 bytes. • Data • Four-bytes frame-check sequence (FCS), which is the standard, 32-bit CCITT-CRC polynomial used in many protocols. When a station needs to transmit, it waits until the LAN becomes silent for a specified period (interframe gap). When a station starts sending, it continually checks for collisions on the LAN. If a collision is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions usually occur close to the beginning of a frame. The station then waits a random time period (backoff) before attempting to send again. When the backoff completes, the station waits for silence on the LAN and then begins retransmission on the LAN. This process is called a retry. If the frame is not successfully sent within 15 retries, an error is indicated. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-1 Fast Ethernet Controller 10-Mbps Ethernet basic timing specifications follow: • Transmits at 0.8 µs per byte • The preamble plus start frame delimiter is sent in 6.4 µs. • The minimum interframe gap is 9.6 µs. • The slot time is 51.2 µs. 100-Mbps Ethernet basic timing specifications follow: • Transmits at 0.08 µs per byte • The preamble plus start frame delimiter is sent in 0.64 µs. • The minimum interframe gap is 0.96 µs. • The slot time is 5.12 µs. 36.1 Fast Ethernet on the MPC8280 When a general FCC mode register (GFMRx[MODE]) selects Ethernet protocol, that FCC performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control (MAC) and channel interface functions. Figure 36-2 shows a block diagram of the FCC Ethernet control logic. 60x-Bus Random No. Control Registers Peripheral Bus Slot Time And Defer Counter Clock Generator RX_CLK TX_CLK Internal Clocks RX_ER RX_DV COL CRS Receiver Control UNIT Receive Data FIFO Transmit Data FIFO Transmitter Control Unit TX_ER TX_EN COL CRS RXD[3–0] Shifter Shifter TXD[3–0] Figure 36-2. Ethernet Block Diagram 36.2 Features The following is a list of Fast Ethernet key features: • Support for Fast Ethernet through the MII (media-independent interface) • Performs MAC (media access control) layer functions of Fast Ethernet and IEEE 802.3x MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-2 Freescale Semiconductor Fast Ethernet Controller • • • • • • • • • • • Performs framing functions — Preamble generation and stripping — Destination address checking — CRC generation and checking — Automatic padding of short frames on transmit — Framing error (dribbling bits) handling Full collision support — Enforces the collision (jamming and TX_ER assertion) — Truncated binary exponential backoff algorithm for random wait — Two nonaggressive backoff modes — Automatic frame retransmission (until retry limit is reached) — Automatic discard of incoming collided frames — Delay transmission of new frames for specified interframe gap Bit rates up to 100 Mbps Receives back-to-back frames Detection of receive frames that are too long Multibuffer data structure Supports 48-bit addresses in three modes — Physical. One 48-bit address recognized or 64-bin hash table for physical addresses — Logical. 64-bin group address hash table plus broadcast address checking — Promiscuous. Receives all frames regardless of address (a CAM can be used for address filtering) External CAM support on system bus interfaces Special RMON counters for monitoring network statistics Transmitter network management and diagnostics — Lost carrier sense — Underrun — Number of collisions exceeded the maximum allowed — Number of retries per frame — Deferred frame indication — Late collision Receiver network management and diagnostics — CRC error indication — Nonoctet alignment error — Frame too short — Frame too long MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-3 Fast Ethernet Controller • • • • • • — Overrun — Busy (out of buffers) Error counters — Discarded frames (out of buffers or overrun occurred) — CRC errors — Alignment errors Internal and external loopback mode Supports Fast Ethernet in duplex mode Supports pause flow control frames Support of out-of-sequence transmit queue (for flow-control frames) External buffer descriptors (BDs) 36.3 Connecting the MPC8280 to Fast Ethernet Figure 36-3 shows the basic components of the media-independent interface (MII) and the signals required to make the Fast Ethernet connection between the MPC8280 and a PHY. Media-Independent Interface (MII) Transmit Error (TX_ER) Transmit Nibble Data 0–3 (TXD[0–3]) Transmit Enable (TX_EN) Transmit Clock (TX_CLK) Collision Detect (COL) Receive Nibble Data (RXD[0–3]) MPC8280 Receive Error (RX_ER) Receive Clock (RX_CLK) Receive Data Valid (RX_DV) Carrier Sense Output (CRS) Management Data Clock1 (MDC) Management Data I/O1 (MDIO) 1 Fast Ethernet PHY Medium The management signals (MDC and MDIO) can be common to all of the Fast Ethernet connections in the system, assuming that each PHY has a different management address. Use parallel I/O port pins to implement MDC and MDIO. (The I2C controller cannot be used for this function.) Figure 36-3. Connecting the MPC8280 to Ethernet MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-4 Freescale Semiconductor Fast Ethernet Controller Each FCC has 18 signals, defined by the IEEE 802.3u standard, for connecting to an Ethernet PHY. The two management signals (MDC and MDIO) required by the MII should be implemented separately using the parallel I/O. The MPC8280 has additional signals for interfacing with an optional external content-addressable memory (CAM), which are described in Section 36.7, “CAM Interface.” The MPC8280 uses the SDMA channels to store every byte received after the start frame delimiter into system memory. On transmit, the user provides the destination address, source address, type/length field, and transmit data. To meet minimum frame requirements, MPC8280 automatically pads frames with fewer than 64 bytes in the data field. The MPC8280 also appends the FCS to the frame. 36.3.1 Connecting the MPC8280 to Ethernet (RMII) Figure 36-4 shows the basic components of the reduced media-independent interface (RMII) and the signals required for the fast Ethernet connection between the MPC8280 and a PHY. The MDC/MDIO management interface is the same as in MII. The RMII reference clock (REF_CLK) is distributed over the FCC transmit clock. In RMII mode receive clock is not used. Clock from board Reference Clock (REF_CLK) Transmit di-bit Data (TXD[1:0]) Transmit Enable (TX_EN) Receive di-bit Data (RXD[1:0]) MPC8280 Receive Error (RX_ER) Receive CRS_DV (CRS_DV) Management Data Clock1 (MDC) Management Data I/O 1 (MDIO) management signals (MDC and MDIO) can be common to all of the fast Ethernet connections in the system, assuming that each PHY has a different management address. Use parallel I/O port pins to implement MDC and MDIO. (The I2C controller cannot be used for this function.) 1The Medium Fast Ethernet RMII PHY Figure 36-4. Connecting the M PC8280 to Ethernet (RMII) 36.4 Ethernet Channel Frame Transmission The Ethernet transmitter requires almost no core intervention. When the core enables the transmitter, the Ethernet controller polls the first TxBD in the FCC’s TxBD table every 256 serial clocks. If the user has a frame ready to transmit, setting FTODR[TOD] eliminates waiting for the next poll. When there is a frame to transmit, the Ethernet controller begins fetching the data from the data buffer and asserts TX_EN. The preamble sequence, start frame delimiter, and frame information are sent in that order; see Figure 36-1. In full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap 28 serial clocks (112 bit time period) regardless of CRS assertion. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-5 Fast Ethernet Controller There is one internal buffer for out-of-sequence flow control frames (in full-duplex Fast Ethernet). When the Fast Ethernet controller is between frames, this buffer is polled if flow control is enabled. This buffer must contain the whole frame. However, in half-duplex mode, the controller defers transmission if the line is busy (CRS asserted). Before transmitting, the controller waits for carrier sense to become inactive, at which point the controller determines if CRS remains negated for 16 serial clocks. If so, the transmission begins after an additional 8 serial clocks (96 bit-times after CRS originally became negated). In the fast ethernet transmitter, if CRS is asserted and then negated within 10 clocks after TXEN is negated, the next frame is not deferred and a defer indication is asserted. If a collision occurs during the transmit frame, the Ethernet controller follows a specified backoff procedure and tries to retransmit the frame until the retry limit is reached. The Ethernet controller stores at least the first 64 bytes of data of the transmit frame in the FCC FIFO, so that the data does not have to be retrieved from system memory in case of a collision. This improves bus usage and latency if the backoff timer output requires an immediate retransmission. When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes are appended (if TxBD[TC] = 1), and TX_EN is negated. This notifies the PHY of the need to generate the illegal Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS, the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. When the end of the current buffer is reached and TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is cleared. For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD] = 1, the Ethernet controller pads short frames to the value of the minimum frame length register (MINFLR), described in Table 36-2. To rearrange the transmit queue before the CP finishes sending all frames, issue a GRACEFUL STOP TRANSMIT command. This can be useful for transmitting expedited data ahead of previously linked buffers or for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller stops immediately if no transmission is in progress or continues transmission until the current frame either finishes or terminates with a collision. When the Ethernet controller is given the RESTART TRANSMIT command, it resumes transmission. The Ethernet controller sends bytes least-significant nibble first. 36.5 Ethernet Channel Frame Reception The Ethernet receiver is designed to work with almost no core intervention and can perform address recognition, CRC checking, short frame checking, maximum DMA transfer checking, and maximum frame-length checking. When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted as long as COL remains negated (full-duplex mode ignores COL). In hunt mode, as data is shifted into the receive shift register four bits at a time, the contents of the register are compared to the contents of the SYN2 field in the FCC’s data synchronization register (FDSR). When the registers match, the hunt mode is terminated and character assembly begins. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-6 Freescale Semiconductor Fast Ethernet Controller When the receiver detects the first bytes of a frame, the Ethernet controller performs address recognition functions on the frame; see Section 36.12, “Ethernet Address Recognition.” The receiver can receive physical (individual), group (multicast), and broadcast addresses. Because Ethernet receive frame data is not written to memory until the internal address recognition algorithm is complete, bus usage is not wasted on frames not addressed to this station. The receiver can also operate with an external CAM, in which case frame reception continues normally, unless the CAM specifically signals the frame to be rejected. See Section 36.7, “CAM Interface.” If an address is recognized, the Ethernet controller fetches the next RxBD and, if it is empty, starts transferring the incoming frame to the RxBD’s associated data buffer. In half-duplex mode, if a collision is detected during the frame, the RxBDs associated with this frame are reused. Thus, no collision frames are presented to the user except late collisions, which indicate serious LAN problems. When the buffer has been filled, the Ethernet controller clears RxBD[E] and generates an interrupt if RxBD[I] is set. If the incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in the table; if it is empty, it continues receiving the rest of the frame. The RxBD length is determined by MRBLR in the parameter RAM. The user should program MRBLR to be at least 64 bytes. During reception, the Ethernet controller checks for frames that are too short or too long. When the frame ends, the receive CRC field is checked and written to the data buffer. The data length written to the last BD in the Ethernet frame is the length of the entire frame, which enables the software to recognize a frame-too-long condition. If an external CAM is used (FPSMRx[CAM] = 1), the Ethernet controller adds the two lower bytes of the CAM output at the end of each frame. Note that the data length does not include these two bytes; that is, the extra two bytes could push the buffer length past MRBLR. When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other frame status bits into the RxBD, and clears RxBD[E]. The Ethernet controller next generates a maskable interrupt, indicating that a frame was received and is in memory. The Ethernet controller then waits for a new frame. The Ethernet controller receives serial data least-significant nibble first. 36.6 Flow Control Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the maximum rate. When the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame size. The length/type fields of these frames have a special value. Table 36-1 shows the flow-control frame structure. Table 36-1. Flow Control Frame Structure Size [Octets] 7 1 6 6 Description Preamble SFD Destination address Source address 01-80C2-00-00-01 Start frame delimiter Multicast address reserved for use in MAC frames Value Comment MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-7 Fast Ethernet Controller Table 36-1. Flow Control Frame Structure (continued) Size [Octets] 2 2 2 Description Length/type MAC opcode MAC parameter Value 88-08 00-01 up to 0xFFFE Control frame type Pause command Pause period measured in slot times, most-significant octet first with a two time-slot resolution. Note: Because the pause period has a resolution of two time slots, the value programmed in this field is rounded up to the nearest even number before being used, as follows: MAC Parameter ValuePause Period 0 none 1 or 2 2 x slot time 3 or 4 4 x slot time …… Comment 42 4 Reserved FCS — Frame check sequence (CRC) When flow-control mode is enabled (FPSMRx[FCE]) and the receiver identifies a pause-flow control frame sent to individual or broadcast addresses, transmission stops for the time specified in the control frame. During this pause, only the out-of-sequence frame is sent. Normal transmission resumes after the pause timer stops counting. If another pause-control frame is received during the pause, the period changes to the new value received. 36.7 CAM Interface The MPC8280 internal address recognition logic can be used in combination with an external CAM. When using a CAM, the FCC must be in promiscuous mode (FPSMRx[PRO] = 1). See Section 36.12, “Ethernet Address Recognition.” The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in a 32-bit access. If the high bit of the result is set, the frame is rejected; otherwise, the lower 16 bits are attached to the end of the frame. When an external CAM is used for address filtering, users can choose to either discard rejected frames (FPSMR[ECM] = 0) or receive rejected frames and signal the CAM miss in the RxBD (FPSMR[ECM] = 1). NOTE The bus atomicity mechanism for CAM accesses may not function correctly when the CPM performs a DMA access to an external CAM device. This only impacts systems in which multiple CPMs will access the CAM. 36.8 Ethernet Parameter RAM For Ethernet mode, the protocol-specific area of the FCC parameter RAM is mapped as in Table 36-2. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-8 Freescale Semiconductor Fast Ethernet Controller Table 36-2. Ethernet-Specific Parameter RAM Offset1 0x3C 0x40 0x44 0x48 0x4C Name STAT_BUF CAM_PTR C_MASK C_PRES CRCEC2 Width Word Buffer of internal usage Word CAM address. For FCC Fast Ethernet operation the CAM should be located on the same bus as the data buffers. Word Constant MASK for CRC (initialize to 0xDEBB_20E3). For the 32-bit CRC-CCITT. Word Preset CRC (initialize to 0xFFFF_FFFF). For the 32-bit CRC-CCITT. Word CRC error counter. Counts each received frame with a CRC error. Does not count frames not addressed to the station, frames received in the out-of-buffers condition, frames with overrun errors, or frames with alignment errors. Word Alignment error counter. Counts frames received with dribbling bits. Does not count frames not addressed to the station, frames received in the out-of-buffers condition, or frames with overrun errors. Word Discard frame counter. Incremented for discarded frames because of an out-of-buffers condition or overrun error. The CRC need not be correct for this counter to be incremented. Hword Retry limit (typically 15 decimal). Number of retries that should be made to send a frame. If the frame is not sent after this limit is reached, an interrupt can be generated. Hword Retry limit counter. Temporary decrementer used to count retries made. Hword Persistence. Allows the Ethernet controller to be less persistent after a collision. Normally cleared, P_PER can be from 0 to 9 (9 = least persistent). The value is added to the retry count in the backoff algorithm to reduce the chance of transmission on the next time-slot. Using a less persistent backoff algorithm increases throughput in a congested Ethernet LAN by reducing the chance of collisions. FPSMR[SBT] can also reduce persistence of the Ethernet controller. The Ethernet/802.3 specifications permit the use of P_PER. Hword Backoff counter Word Group address filters high and low are used in the hash table function of the group addressing mode. The user may write zeros to these values after reset and before the Word Ethernet channel is enabled to disable all group hash address recognition functions. The SET GROUP ADDRESS command is used to enable the hash table. See Section 36.13, “Hash Table Algorithm.” Hword Out-of-sequence TxBD. Includes the status/control, data length, and buffer pointer fields in the same format as a regular TxBD. Useful for sending flow control frames. Hword This area’s TxBD[R] is always checked between frames, regardless of FPSMRx[FCE]. Word If it is not ready, a regular frame is sent. The user must set TxBD[L] when preparing this BD. If TxBD[I] is set, a TXC event is generated after frame transmission. This area should be cleared when not in use. Hword Maximum frame length register (typically1518 decimal). If the Ethernet controller detects an incoming frame exceeding MFLR, it sets RxBD[LG] (frame too long) in the last RxBD, but does not discard the rest of the frame. The controller also reports the frame status and length of the received frame in the last RxBD. MFLR includes all in-frame bytes between the start frame delimiter and the end of the frame. Description 0x50 ALEC 2 0x54 DISFC 2 0x58 0x5A 0x5C RET_LIM RET_CNT P_PER 0x5E 0x60 0x64 BOFF_CNT GADDR_H GADDR_L 0x68 0x6A 0x6C TFCSTAT TFCLEN TFCPTR 0x70 MFLR MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-9 Fast Ethernet Controller Table 36-2. Ethernet-Specific Parameter RAM (continued) Offset1 0x72 0x74 0x76 0x78 0x7A 0x7C 0x7E 0x80 0xA0 0xA4 Name PADDR1_H PADDR1_M PADDR1_L IBD_CNT IBD_START IBD_END TX_LEN IBD_BASE IADDR_H IADDR_L Width Description Hword The 48-bit individual address of this station. PADDR1_L is the lowest order half-word, and PADDR1_H is the highest order half-word. Hword Hword Hword Internal BD counter Hword Internal BD start pointer Hword Internal BD end pointer Hword Tx frame length counter 32 Internal microcode usage Bytes Word Individual address filter high/low. Used in the hash table function of the individual addressing mode. The user can write zeros to these values after reset and before the Word Ethernet channel is enabled to disable all individual hash address recognition functions. Issuing a SET GROUP ADDRESS command enables the hash table. See Section 36.13, “Hash Table Algorithm.” Hword Minimum frame length register (typically 64 decimal). If the Ethernet receiver detects an incoming frame shorter than MINFLR, it discards that frame unless FPSMR[RSH] (receive short frames) is set, in which case RxBD[SH] (frame too short) is set in the last RxBD. The Ethernet transmitter pads frames that are too short (according to TxBD[PAD] and the PAD value in the parameter RAM). PADs are added to make the transmit frame MINFLR bytes. Hword Allows addition of addresses to the individual and group hashing tables. After an address is placed in TADDR, issue a SET GROUP ADDRESS command. TADDR_L is the Hword lowest-order half-word; TADDR_H is the highest. Hword A zero in the I/G bit indicates an individual address; 1 indicates a group address. Hword Internal PAD pointer. This internal 32-byte aligned pointer points to a 32-byte buffer filled with pad characters. The pads may be any value, but all the bytes should be the same to assure padding with a specific character. If a specific padding character is not needed, PAD_PTR should equal the internal temporary data pointer TIPTR; see Section 30.7, “FCC Parameter RAM.” Hword Reserved, should be cleared. Hword Control frame range. Internal usage Hword Maximum BD byte count. Internal usage Hword Max DMA1 length register (typically 1520 decimal). Lets the user prevent system bus writes after a frame exceeds a specified size. The MAXD1 value is valid only if an address match is detected. If the Ethernet controller detects an incoming Ethernet frame larger than the user-defined value in MAXD1, the rest of the frame is discarded. The Ethernet controller waits for the end of the frame (or until MFLR bytes have been received) and reports the frame status and length (including the discarded bytes) in the last RxBD. This value must be greater than 32. 0xA8 MINFLR 0xAA 0xAC 0xAE 0xB0 TADDR_H TADDR_M TADDR_L PAD_PTR 0xB2 0xB4 0xB6 0xB8 — CF_RANGE MAX_B MAXD1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-10 Freescale Semiconductor Fast Ethernet Controller Table 36-2. Ethernet-Specific Parameter RAM (continued) Offset1 0xBA Name MAXD2 Width Description Hword Max DMA2 length register (typically 1520 decimal). Lets the user prevent system bus writes after a frame exceeds a specified size. The value of MAXD2 is valid in promiscuous mode when no address match is detected. If the Ethernet controller detects an incoming Ethernet frame larger than the value in MAXD2, the rest of the frame is discarded. The Ethernet controller waits for the end of the frame (or until MFLR bytes are received) and reports frame status and length (including the discarded bytes) in the last RxBD. In a monitor station, MAXD2 can be much less than MAXD1 to receive entire frames addressed to this station, but receive only the headers of all other frames.This value must be less than MAXD1. Hword Rx maximum DMA. Internal usage Hword Rx DMA counter. Temporary down-counter used to track the frame length. Word (RMON mode only) The total number of octets of data (including those in bad packets) received on the network (excluding framing bits but including FCS octets). Word (RMON mode only) The best estimate of the total number of collisions on this Ethernet segment. Word (RMON mode only) The total number of good packets received that were directed to the broadcast address. Note that this does not include multicast packets. Word (RMON mode only) The total number of good packets received that were directed to a multicast address. Note that this number does not include packets directed to the broadcast address. Word (RMON mode only) The total number of packets received that were less than 64 octets (excluding framing bits but including FCS octets) and were otherwise well-formed. Word (RMON mode only) The total number of packets received that were less than 64 octets long (excluding framing bits but including FCS octets) and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). Note that it is entirely normal for etherStatsFragments to increment because it counts both runts (which are normal occurrences due to collisions) and noise hits. Word (RMON mode only) The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets) and were otherwise well-formed. Word (RMON mode only) The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets), and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). Note that this definition of jabber is different than the definition in IEEE-802.3 section 8.2.1.5 (10BASE5) and section 10.3.1.4 (10BASE2). These documents define jabber as the condition where any packet exceeds 20 ms. The allowed range to detect jabber is between 20 ms and 150 ms. Word (RMON mode only) The total number of packets (including bad packets) received that were 64 octets long (excluding framing bits but including FCS octets). Word (RMON mode only) The total number of packets (including bad packets) received that were between 65 and 127 octets long inclusive (excluding framing bits but including FCS octets). 0xBC 0xBE 0xC0 0xC4 0xC8 0xCC MAXD DMA_CNT OCTC 2 COLC 2 BROC 2 MULC 2 0xD0 0xD4 USPC 2 FRGC 2 0xD8 OSPC 2 0xDC JBRC 2 0xE0 0xE4 P64C 2 P65C 2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-11 Fast Ethernet Controller Table 36-2. Ethernet-Specific Parameter RAM (continued) Offset1 0xE8 Name P128C 2 Width Description Word (RMON mode only) The total number of packets (including bad packets) received that were between 128 and 255 octets long inclusive (excluding framing bits but including FCS octets). Word (RMON mode only) The total number of packets (including bad packets) received that were between 256 and 511 octets long inclusive (excluding framing bits but including FCS octets). Word (RMON mode only) The total number of packets (including bad packets) received that were between 512 and 1023 octets long inclusive (excluding framing bits but including FCS octets). Word (RMON mode only) The total number of packets (including bad packets) received that were between 1024 and 1518 octets long inclusive (excluding framing bits but including FCS octets). Word Internal buffer for CAM result Word Reserved, should be cleared. Byte 10 Mbps Poll Delay 100 Mbps = 0x0 10 Mbps = 0x0B (up to 100 Mhz CPM) = 0x18 (up to 200 Mhz CPM) = 0x32 (up to 333 Mhz CPM) 0xEC P256C 2 0xF0 P512C 2 0xF4 P1024C 2 0xF8 0xFC 0xFF CAM_BUF — — 1 2 Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.” 32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled. 36.9 Programming Model The core configures an FCC to operate as an Ethernet controller using GFMR[MODE]. The receive errors (collision, overrun, nonoctet-aligned frame, short frame, frame too long, and CRC error) are reported through the RxBD. The transmit errors (underrun, heartbeat, late collision, retransmission limit, and carrier sense lost) are reported through the TxBD. The user should program the FDSR as described in Section 30.4, “FCC Data Synchronization Registers (FDSRx),” with FDSR[SYN2] = 0xD5 and FDSR[SYN1] = 0x55. 36.10 Ethernet Command Set The transmit and receive commands are issued to the CPCR; see Section 14.4, “Command Set.” NOTE Before resetting the CPM, configure TX_EN (RTS) to be an input. Transmit commands that apply to Ethernet are described in Table 36-3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-12 Freescale Semiconductor Fast Ethernet Controller Table 36-3. Transmit Commands Command STOP TRANSMIT GRACEFUL STOP TRANSMIT Description When used with the Ethernet controller, this command violates a specific behavior of an Ethernet/IEEE 802.3 station. It should not be used. Used to smoothly stop transmission after the current frame finishes sending or undergoes a collision (immediately if there is no frame being sent). FCCE[GRA] is set once transmission stops. Then the Ethernet transmit parameters (including BDs) can be modified by the user. The TBPTR points to the next TxBD in the table. Transmission begins when the R bit of the next BD is set and the RESTART TRANSMIT command is issued. Note that if the GRACEFUL STOP TRANSMIT command is issued and the current transmit frame ends in a collision, the TBPTR points to the beginning of the collided frame with TxBD[R] still set (the frame looks as if it was never sent). Enables transmission of characters on the transmit channel. It is expected by the Ethernet controller after a GRACEFUL STOP TRANSMIT command or transmitter error (underrun, retransmission limit reached, or late collision). The Ethernet controller resumes transmission from the current TBPTR in the channel TxBD table. Initializes all the transmit parameters in this serial channel parameter RAM to their reset state. This command should be issued only when the transmitter is disabled. Note that the INIT TX AND RX PARAMETERS command can also be used to reset the transmit and receive parameters. RESTART TRANSMIT INIT TX PARAMETERS Receive commands that apply to Ethernet are described in Table 36-4. Table 36-4. Receive Commands Command ENTER HUNT MODE Description After the hardware or software is reset and the channel in the FCC mode register is enabled, the channel is in the receive enable mode and uses the first BD in the table. This command is generally used to force the Ethernet receiver to abort reception of the current frame and enter hunt mode. In hunt mode, the Ethernet controller continually scans the input data stream for a transition of carrier sense from inactive to active followed by a preamble sequence and the start frame delimiter. After receiving the command, the current receive buffer is closed, the error status flags and length field are cleared, RxBD[E] (the empty bit) is set, and the CRC calculation is reset. Further frame reception uses the current RxBD. Note that short frames pending in the internal FIFO may be lost. Initializes all the receive parameters in this serial channel parameter RAM to their reset state and should only be issued when the receiver is disabled. Note that the INIT TX AND RX PARAMETERS command can also be used to reset the receive and transmit parameters. Used to set one of the 64 bits of the four individual/group address hash filter registers (GADDR[1–4] or IADDR[1–4]). The individual or group address (48 bits) to be added to the hash table should be written to TADDR_L, TADDR_M, and TADDR_H in the parameter RAM prior to executing this command. The CP checks the I/G bit in the address stored in TADDR to determine whether to use the individual hash table or the group hash table. A 0 in the I/G bit indicates an individual address; 1 indicates a group address. This command can be executed at any time, regardless of whether the Ethernet channel is enabled. INIT RX PARAMETERS SET GROUP ADDRESS If an address from the hash table must be deleted, the Ethernet channel must be disabled, the hash table registers must be cleared, and the SET GROUP ADDRESS command must be executed for the remaining preferred addresses. This is required because the hash table might have mapped multiple addresses to the same hash table bit. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-13 Fast Ethernet Controller 36.11 RMON Support The Fast Ethernet controller can automatically gather network statistics required for RMON without the need to receive all addresses using promiscuous mode. Setting FPSMRx[MON] enables RMON support. The RMON statistics and their corresponding counters in the parameter RAM are described in Table 36-5. Table 36-5. RMON Statistics and Counters Statistic etherStatsDropEvents Description The total number of events in which packets were detected as dropped by the probe due to lack of resources. Note that this may not be the number of packets dropped; it is the number of times this condition is detected. The total number of octets of data (including those in bad packets) received on the network (excluding framing bits but including FCS octets). The total number of packets (including bad packets, broadcast packets, and multicast packets) received. Counter DISFC etherStatsOctets OCTC etherStatsPkts USPC + OSPC + FRGC + JBRC + P64C + P65C + P128C + P256C + P512C + P1024C BROC etherStatsBroadcastPkts The total number of good packets received that were directed to the broadcast address. Note that this does not include multicast packets. The total number of good packets received that were directed to a multicast address. Note that this number does not include packets directed to the broadcast address. The total number of packets received that had a length (excluding framing bits but including FCS octets) of between 64 and 1518 octets, inclusive, but had either an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). The total number of packets received that were less than 64 octets long (excluding framing bits but including FCS octets) and were otherwise well-formed. The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets) and were otherwise well-formed. The total number of packets received that were less than 64 octets long (excluding framing bits but including FCS octets) and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). Note that it is entirely normal for etherStatsFragments to increment, because it counts both runts (which are normal occurrences due to collisions) and noise hits. etherStatsMulticastPkts MULC etherStatsCRCAlignErrors CRCEC + ALEC -FRGC -JBRC USPC etherStatsUndersizePkts etherStatsOversizePkts OSPC etherStatsFragments FRGC MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-14 Freescale Semiconductor Fast Ethernet Controller Table 36-5. RMON Statistics and Counters (continued) Statistic etherStatsJabbers Description The total number of packets received that were longer than 1518 octets (excluding framing bits but including FCS octets) and had either a bad FCS with an integral number of octets (FCS error) or a bad FCS with a non-integral number of octets (alignment error). Note that this definition of jabber is different than the definition in IEEE-802.3 Section 8.2.1.5 (10BASE5) and Section 10.3.1.4 (10BASE2). These documents define jabber as the condition where any packet exceeds 20 ms. The allowed range to detect jabber is between 20 ms and 150 ms. The best estimate of the total number of collisions on this Ethernet segment. The total number of packets (including bad packets) received that were 64 octets long (excluding framing bits but including FCS octets). The total number of packets (including bad packets) received that were between 65 and 127 octets long inclusive (excluding framing bits but including FCS octets). The total number of packets (including bad packets) received that were between 128 and 255 octets long inclusive (excluding framing bits but including FCS octets). The total number of packets (including bad packets) received that were between 256 and 511 octets long inclusive (excluding framing bits but including FCS octets). The total number of packets (including bad packets) received that were between 512 and 1023 octets long inclusive (excluding framing bits but including FCS octets). The total number of packets (including bad packets) received that were between 1024 and 1518 octets long inclusive (excluding framing bits but including FCS octets). Counter JBRC etherStatsCollisions etherStatsPkts64Octets COLC P64C etherStatsPkts65to127Octets P65C etherStatsPkts128to255Octets P128C etherStatsPkts256to511Octets P256C etherStatsPkts512to1023Octets P512C etherStatsPkts1024to1518Octets P1024C 36.12 Ethernet Address Recognition The Ethernet controller can filter the received frames based on different addressing types—physical (individual), group (multicast), broadcast (all-ones group address), and promiscuous. The difference between an individual address and a group address is determined by the I/G bit in the destination address field. Figure 36-5 is a flowchart for address recognition on received frames. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-15 Fast Ethernet Controller Check Address G I/G Address I Broadcast Addr T F F Individual Addr Match? Hash Search Use Group Table Hash Search Use Individual Table T Broadcast Enabled T Receive Frame T Match? F F F Promiscuous? T T Use CAM? F T Discard Frame Rejected by CAM? F Start Receive Figure 36-5. Ethernet Address Recognition Flowchart MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-16 Freescale Semiconductor Fast Ethernet Controller In the physical type of address recognition, the Ethernet controller compares the destination address field of the received frame with the physical address that the user programs in the PADDR. If it fails, the controller performs address recognition on multiple individual addresses using the IADDR_H/L hash table. Since the controller always checks PADDR and the individual hash, for individual address the user must write zeros to the hash in order to avoid a hash match and ones to PADDR in order to avoid individual address match. In the group type of address recognition, the Ethernet controller determines whether the group address is a broadcast address. If it is a broadcast and broadcast addresses are enabled, the frame is accepted. If the group address is not a broadcast address, the user can perform address recognition on multiple group addresses using the GADDR_H/L hash table. In promiscuous mode, the Ethernet controller receives all of the incoming frames regardless of their address when an external CAM is not used. If an external CAM is used for address recognition (FPSMR[CAM] = 1), the user should select promiscuous mode; the frame can be rejected if there is no match in the CAM. If the on-chip address recognition functions detect a match, the external CAM is not accessed. Otherwise, the CPM issues a match transaction to the CAM using the bus on which the data buffers reside. (The data buffer bus is selected in FCRx[DTB]; see Section 30.7.1, “FCC Function Code Registers (FCRx).”) Note that even if the CAM is placed on the local bus and the data buffers are on the 60x bus, match transactions are eventually accessed correctly. That is, the CPM attempts to access the CAM on the 60x bus, but the 60x-to-local-bus bridge logic detects the 60x bus transaction and forwards it to the CAM on the local bus. 36.13 Hash Table Algorithm The hash table process used in the individual and group hash filtering operates as follows. The Ethernet controller maps any 48-bit address into one of 64 bins, which are represented by the 64 bits in GADDR_H/L or IADDR_H/L. When the SET GROUP ADDRESS command is executed, the Ethernet controller maps the selected 48-bit address in TADDR into one of the 64 bits. This is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and using 6 bits of the CRC-encoded result to generate a number between 1 and 64. Bit 26 of the CRC result selects which address filter registers are used in the hashing process—either GADDR_H/IADDR_H or GADDR_L/IADDR_L— and bits 27–31 of the CRC result select which bit is set. The same process is used when the Ethernet controller receives a frame. If the CRC generator selects a bit that is set in the group/individual hash table, the frame is accepted; otherwise, it is rejected. The result is that if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. The core must further filter those that reach memory to determine if they contain one of the eight preferred addresses. Better performance is achieved by using the group and individual hash tables in combination. For instance, if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames (not just group address frames) are prevented from reaching memory. The effectiveness of the hash table declines as the number of addresses increases. For instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the hash table bits are set, preventing only a small fraction of frames from reaching memory. In such instances, an external CAM is advised if the extra bus use cannot be tolerated. See Section 36.7, “CAM Interface.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-17 Fast Ethernet Controller NOTE The hash tables cannot be used to reject frames that match a set of selected addresses because unintended addresses can map to the same bit in the hash table. Thus, an external CAM must be used to implement this function. 36.14 Interpacket Gap Time The minimum interpacket gap time for back-to-back transmission is 96 bit-times. The receiver receives back-to-back frames with this minimum spacing. In addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated before retransmitting the frame. The retransmission begins 96 bit times after carrier sense is negated if it stays negated for at least 64 bit times. So if there is no change in the carrier sense indication during the first 64 bit-times (16 serial clocks), the retransmission begins 96 clocks after carrier sense is first negated 36.15 Handling Collisions If a collision occurs during frame transmission, the Ethernet controller continues transmission for at least 32-bit times, transmitting a jam pattern of 32 ones. If the collision occurs during the preamble sequence, the jam pattern is sent after the sequence ends. If a collision occurs within 64 byte times, the process is retried. The transmitter waits a random number of slot times. (A slot time is 512 bit times.) If a collision occurs after 64 byte times, no retransmission is performed, FCCE[TXE] is set, and the buffer is closed with a late-collision error indication in TxBD[LC]. If a collision occurs during frame reception, reception is stopped. This error is reported only in the RxBD if the frame is at least as long as the MINFLR or if FPSMR[RSH] = 1. 36.16 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both receive and transmit FIFO buffers are used and the FCC operates in full-duplex. Both internal and external loopback are configured using combinations of FPSMR[LPB] and GFMR[DIAG]. Because of the full-duplex nature of the loopback operation, the performance of the other FCCs is degraded. Internal loopback disconnects the FCC from the SI. The receive data is connected to the transmit data. The transmitted data from the transmit FIFO is received immediately into the receive FIFO. There is no heartbeat check in this mode. In external loopback operation, the Ethernet controller listens for data received from the PHY while it is sending. 36.17 Ethernet Error-Handling Procedure The Ethernet controller reports frame reception and transmission error conditions using the channel BDs, the error counters, and the FCC event register. Transmission errors are described in Table 36-6. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-18 Freescale Semiconductor Fast Ethernet Controller Table 36-6. Transmission Errors Error Transmitter underrun Response The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after receiving the RESTART TRANSMIT command. If no collision is detected in the frame, the controller sets TxBD[CSL] and FCCE[TXE], and it Carrier sense lost during frame continues the buffer transmission normally. No retries are performed as a result of this error. transmission Retransmission attempts limit expired Late collision The controller terminates buffer transmission, closes the buffer, sets TxBD[RL] and FCCE[TXE]. Transmission resumes after receiving the RESTART TRANSMIT command. The controller terminates buffer transmission, closes the buffer, sets TxBD[LC] and FCCE[TXE]. The controller resumes transmission after receiving the RESTART TRANSMIT command. Note that late collision parameters are defined in FPSMR[LCW]. Reception errors are described in Table 36-7. Table 36-7. Reception Errors Error Overrun error Description The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer overrun occurs, the controller writes the received data byte to the internal FIFO buffer over the previously received byte. The previous data byte and frame status are lost. The controller closes the buffer, sets RxBD[OV] and FCCE[RXF], and increments the discarded frame counter (DISFC). The receiver then enters hunt mode. A frame is received and discarded due to a lack of buffers. The controller sets FCCE[BSY] and increments the discarded frame counter (DISFC). The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the alignment error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no error is reported. When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF]. Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. Busy error Non-octet error (dribbling bits) CRC error 36.18 Fast Ethernet Registers The following sections describe registers used for configuring and operating the Fast Ethernet controller. 36.18.1 FCC Ethernet Mode Registers (FPSMRx) The MPC2880 supports 10/100 Mbps Ethernet through a RMII interface (according to RMII Specification March 20, 1998). The RMII use a single reference clock (50 MHz) and seven pins which are a proper subset of the MII interface pins. Ethernet features are unchanged in RMII mode. To select RMII-PHY interface, a mode bit in the Ethernet mode register (FPSMR) has been added, as shown in Figure 36-6. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-19 Fast Ethernet Controller 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field HBC Reset R/W Addr 16 FC SBT LPB LCW FDE MON — PRO FCE RSH — RMII — 0000_0000_0000_0000 R/W 0x11304 (FPSMR1), 0x11324 (FPSMR2) 20 21 22 23 24 25 26 31 Field Reset R/W Addr — CAM BRO — CRC — 0000_0000_0000_0000 R/W 0x11306 (FPSMR1), 0x11326 (FPSMR2) Figure 36-6. FCC Ethernet Mode Registers (FPSMRx) Table 36-8 describes FPSMR fields. Table 36-8. FPSMR Ethernet Field Descriptions Bits 0 Name HBC Description Heartbeat checking 0 No heartbeat checking is performed. Do not wait for a collision after transmission. 1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission. TxBD[HB] is set if the heartbeat is not heard within 40 transmit serial clocks. Force collision 0 Normal operation 1 The channel forces a collision on transmission of every transmit frame. The MPC8280 should be configured in loopback operation when using this feature, which allows the user to test the MPC8280 collision logic. It causes the retry limit to be exceeded for each transmit frame. Stop backoff timer 0 The backoff timer functions normally. 1 The backoff timer (for the random wait after a collision) is stopped whenever carrier sense is active. In this method, the retransmission is less aggressive than the maximum allowed in the IEEE 802.3 standard. The persistence (P_PER) feature in the parameter RAM can be used in combination with the SBT bit (or in place of the SBT bit). Local protect bit. 0 Receiver is blocked when transmitter sends (default). 1 Receiver is not blocked when transmitter sends. Must set for full-duplex operation. For external loopback, GFMR[DIAG] must be programmed also; see Section 30.2, “General FCC Mode Registers (GFMRx)." Late collision window 0 A late collision is any collision that occurs at least 64 bytes from the preamble. 1 A late collision is any collision that occurs at least 56 bytes from the preamble. Full duplex Ethernet 0 Disable full-duplex 1 Enable full-duplex. Must be set if FSMR[LPB] is set or external loopback is performed. RMON mode 0 Disable RMON mode 1 Enable RMON mode 1 FC 2 SBT 3 LPB 4 LCW 5 FDE 6 MON MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-20 Freescale Semiconductor Fast Ethernet Controller Table 36-8. FPSMR Ethernet Field Descriptions (continued) Bits 7–8 9 Name — PRO Reserved, should be zero Promiscuous 0 Check the destination address of incoming frames. 1 Receive the frame regardless of its address. A CAM can be used for address filtering when FSMR[CAM] is set. Flow control enable 0 Flow control is not enabled 1 Flow control is enabled Receive short frames 0 Discard short frames (frames smaller than the value specified in MINFLR). 1 Receive short frames. Reserved, should be zero. RMII interface mode 0 MII interface 1 RMII interface. RMII to/from MII conversion logic is enabled. Reserved, should be zero. CAM address matching 0 Normal operation. 1 Use the CAM for address matching; CAM result (16 bits) is added at the end of the frame. Broadcast address 0 Receive all frames containing the broadcast address. 1 Reject all frames containing the broadcast address unless FSMR[PRO] = 1. Reserved, should be zero CRC selection 0x Reserved. 10 32-bit CCITT-CRC (Ethernet). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1. Select this to comply with Ethernet specifications. 11 Reserved. Reserved, should be zero Description 10 FCE 11 RSH 12–13 — 14 RMII 15–20 — 21 CAM 22 BRO 23 — 24–25 CRC 26–31 — 36.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM) The FCCE, shown in Figure 36-7, is used as the Ethernet event register when the FCC functions as an Ethernet controller. It generates interrupts and reports events recognized by the Ethernet channel. On recognition of an event, the Ethernet controller sets the corresponding FCCE bit. Interrupts generated by this register can be masked in the Ethernet mask register (FCCM). The FCCM has the same bit format as FCCE. Setting an FCCM bit enables and clearing a bit masks the corresponding interrupt in the FCCE. The FCCE can be read at any time. Bits are cleared by writing ones; writing zeros does not affect bit values. Unmasked FCCE bits must be cleared before the CP clears the internal interrupt request. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-21 Fast Ethernet Controller Figure 36-7. Ethernet Event Register (FCCE)/Mask Register (FCCM) 0 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr — GRA RXC TXC 0000_0000_0000_0000 R/W TXE RXF BSY TXB RXB 0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/ 0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3) 16 31 Field Reset R/W Addr — 0000_0000_0000_0000 R/W 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Table 36-9 describes FCCE/FCCM fields. Table 36-9. FCCE/FCCM Field Descriptions Bits 0–7 8 Name — GRA Reserved, should be cleared. Graceful stop complete. A graceful stop, initiated by the GRACEFUL STOP TRANSMIT command, is complete. When the command is issued, GRA is set as soon the transmitter finishes sending a frame in progress. If no frame is in progress, GRA is set immediately. RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter finishes sending the current frame, a pause operation is performed. TX control. An out-of-sequence frame was sent. Tx error. An error occurred on the transmitter channel. This event is not maskable via the TxBD[I] bit Rx frame. Set when a complete frame is received on the Ethernet channel. This event is not maskable via the RxBD[I] bit. Busy condition. Set when a frame is received and discarded due to a lack of buffers. Tx buffer. Set when a buffer has been sent on the Ethernet channel. Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel. Reserved, should be cleared. Description 9 10 11 12 13 14 15 16–31 RXC TXC TXE RXF BSY TXB RXB — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-22 Freescale Semiconductor Fast Ethernet Controller Figure 36-8 shows interrupts that can be generated in the Ethernet protocol. Frame Received in Ethernet Time RXD Line Idle Stored in Rx Buffer P SFD DA SA T/L D CR Line Idle RX_DV Ethernet FCCE Events RXB RXF Notes: 1. RXB event assumes receive buffers are 64 bytes each. 2. The RXF interrupt may occur later than RX_DV due to receive FIFO latency. Frame Transmitted by Ethernet TXD Line Idle Stored in Tx Buffer P SFD DA SA T/L D CR Line Idle TX_EN COL Ethernet FCCE Events TXB TXB, GRA Notes: 1. TXB events assume the frame required two transmit buffers. 2. The GRA event assumes a graceful stop transmit command was issued during frame transmission. Legend: P = Preamble, SFD = Start frame delimiter, DA and SA = Destination/Source address, T/L = Type/Length, D = Data, CR = CRC bytes Figure 36-8. Ethernet Interrupt Events Example NOTE The FCC status register is not valid for the Ethernet protocol. The current state of the MII signals can be read through the parallel ports. 36.19 Ethernet RxBDs The Ethernet controller uses the RxBD to report information about the received data for each buffer. Figure 36-9 shows the FCC Ethernet RxBD format. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-23 Fast Ethernet Controller 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I L F CMR M BC MC LG NO SH CR OV CL Data Length Rx Data Buffer Pointer Figure 36-9. Fast Ethernet Receive Buffer (RxBD) Table 36-10 describes Ethernet RxBD fields. Table 36-10. RxBD Field Descriptions Bits 0 Name E Description Empty 0 The buffer associated with this RxBD is full or reception terminated due to an error. The core can examine or read to any fields of this RxBD. The CP does not use this BD as long as E = 0. 1 The associated buffer is empty. The RxBD and buffer are owned by the CP. Once E = 1, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in RxBD table) 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to in the table. The number of RxBDs in this table is programmable and determined only by the W bit. The RxBD table must contain more than one BD in Ethernet mode. Interrupt 0 No interrupt is generated after this buffer is used; FCCE[RXF] is unaffected. 1 FCCE[RXB] or FCCE[RXF] are set when this buffer is used by the Ethernet controller. These two bits can cause interrupts if they are enabled. Last in frame. Set by the Ethernet controller when this buffer is the last in a frame. This implies the end of the frame or a reception error, in which case one or more of the CL, OV, CR, SH, NO, and LG bits are set. The Ethernet controller writes the number of frame octets to the data length field. 0 Not the last buffer in a frame. 1 Last buffer in a frame. First in frame. Set by the Ethernet controller when this buffer is the first in a frame. 0 Not the first buffer in a frame. 1 First buffer in a frame. CAM match result for the frame. Set by the Ethernet controller when using a CAM for address matching and FPSMR[ECM] = 1. Valid only if the L bit is set. 0 A hit in the CAM. 1 A miss in the CAM. Miss. Set by the Ethernet controller for frames that are accepted in promiscuous mode, but are flagged as a miss by the internal address recognition. Thus, while using promiscuous mode, the user uses the miss bit to determine quickly whether the frame is destined for this station. Valid only if RxBD[I] is set. 0 The frame is received because the address is recognized. 1 The frame is received because of promiscuous mode (address is not recognized). 1 2 — W 3 I 4 L 5 F 6 CMR 7 M MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-24 Freescale Semiconductor Fast Ethernet Controller Table 36-10. RxBD Field Descriptions (continued) Bits 8 9 10 11 12 13 14 15 Name BC MC LG NO SH CR OV CL Description Broadcast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address is the broadcast address. Multicast address. Valid only for the last buffer in a frame (RxBD[L] = 1). The received frame address is a multicast address other than a broadcast address. Rx frame length violation. A frame length greater than the MFLR (maximum frame length) defined for this FCC is recognized. Rx nonoctet aligned frame. A frame that contained a number of bits not divisible by eight is received and the CRC check at the preceding byte boundary generated an error. Short frame. A frame length less than the MINFLR (minimum frame length) defined for this channel is recognized. This indication is possible only if the FPSMR[RSH] = 1. Rx CRC error. This frame contains a CRC error. Overrun. A receiver overrun occurred during frame reception. Collision. This frame is closed because a collision occurred during frame reception. Set only if a late collision occurs or if FPSMR[RSH] is set. The late collision definition is determined by the setting of FPSMR[LCW]. Data length is the number of octets the CP writes into this BD data buffer. It is written by the CP as the buffer is closed. When this BD is the last BD in the frame (RxBD[L] = 1), the data length contains the total number of frame octets (including four bytes for CRC). Note that at least as much memory should be allocated for each receive buffer as the size specified in MRBLR. MRBLR should be divisible by 32 and not less than 64. The receive buffer pointer, which points to the first location of the associated data buffer, can reside in external memory. This value must be divisible by 16. When a received frame’s data length is an exact multiple of MRBLR, the last BD contains only the status and total frame length. NOTE At least two BDs must be prepared before beginning reception. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-25 Fast Ethernet Controller Figure 36-10 shows how RxBDs are used during Ethernet reception. E Status Length Pointer 0 Receive BD 0 LF 01 0x0040 32-Bit Buffer Pointer Buffer Full MRBLR = 64 Bytes for this FCC Buffer Destination Address (6) Source Address (6) Type/Length (2) Data Bytes (50) Receive BD 1 LF 10 0x0045 32-Bit Buffer Pointer Buffer Closed after CRC Received. Optional Tag Byte Appended CRC Bytes (4) Tag Byte (1) Empty 64 Bytes 64 Bytes E Status Length Pointer 0 Buffer Receive BD 2 E Status Length Pointer 1 XXXX 32-Bit Buffer Pointer Collision Causes Buffer to be Reused Buffer Old Data from Collided Frame Will be Overwritten 64 Bytes Empty Buffer Receive BD 3 E Status Length Pointer 1 XXXX 32-Bit Buffer Pointer Buffer Still Empty Empty 64 Bytes Non-Collided Ethernet Frame 1 Two Frames Received in Ethernet Time Line Idle Frame 2 Collision Present Time Figure 36-10. Ethernet Receiving Using RxBDs 36.20 Ethernet TxBDs Data is sent to the Ethernet controller for transmission on an FCC channel by arranging it in buffers referenced by the channel’s TxBD table. The Ethernet controller uses TxBDs to confirm transmission or MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-26 Freescale Semiconductor Fast Ethernet Controller indicate errors so the core knows when buffers have been serviced. Figure 36-11 shows the FCC Ethernet TxBD format. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R PAD W I L TC DEF HB LC RL RC UN CSL Data length Tx data Buffer Pointer Figure 36-11. Fast Ethernet Transmit Buffer (TxBD) Table 36-11 describes Ethernet TxBD fields. Table 36-11. Ethernet TxBD Field Definitions Field 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission; the user can manipulate this BD or its associated buffer. The CP clears R after the buffer has been sent or after an error. 1 The buffer is ready to be sent. The buffer is either waiting or in the process of being sent. The user cannot change fields in this BD or its associated buffer once R = 1. Short frame padding. Valid only when L = 1; otherwise, it is ignored. 0 Do not add PADs to short frames. 1 Add PADs to short frames. PAD bytes are inserted until the length of the transmitted frame equals the MINFLR. The PAD bytes are stored in a buffer pointed to by PAD_PTR in the parameter RAM. Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the first BD that TBASE points to in the table. The number of TxBDs in this table is programmable and determined only by the W bit. The TxBD table must contain more than one BD in Ethernet mode. Interrupt 0 No interrupt is generated after this buffer is serviced; FCCE[TXE] is unaffected. 1 FCCE[TXB] or FCCE[TXE] is set after this buffer is serviced. These bits can cause interrupts if they are enabled. Last 0 Not the last buffer in the transmit frame. 1 Last buffer in the current transmit frame. Tx CRC. Valid only when the L bit is set; otherwise, it is ignored. 0 End transmission immediately after the last data byte. 1 Transmit the CRC sequence after the last data byte. Defer indication. This frame did not have a collision before it was sent but it was sent late because of deferring. Heartbeat. The collision input is not asserted within 40 transmit serial clocks following completion of transmission. This bit cannot be set unless FPSMR[HBC] = 1. Written by the Ethernet controller after sending the associated buffer. Late collision. A collision occurred after the number of bytes defined in FPSMR[LCW] (56 or 64) are sent. The Ethernet controller terminates the transmission and updates LC after sending the buffer. 1 PAD 2 W 3 I 4 L 5 TC 6 7 DEF HB 8 LC MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 36-27 Fast Ethernet Controller Table 36-11. Ethernet TxBD Field Definitions (continued) Field 9 10–13 Name RL RC Description Retransmission limit. The transmitter failed (RET_LIM + 1) attempts to successfully send a message due to repeated collisions. The Ethernet controller updates RL after sending the buffer. Retry count. Indicates the number of retries required for this frame to be successfully sent. If RC = 0, the frame is sent correctly the first time. If RC = 15 and RET_LIM = 15 in the parameter RAM, 15 retries were needed. If RC = 15 and RET_LIM > 15, 15 or more retries were needed. The Ethernet controller updates RC after sending the buffer. Underrun. The Ethernet controller encountered a transmitter underrun condition while sending the associated buffer. The Ethernet controller updates UN after sending the buffer. Carrier sense lost. Carrier sense is lost during frame transmission. The Ethernet controller updates CSL after sending the buffer. 14 15 UN CSL Data length is the number of octets the Ethernet controller should transmit from this BD data buffer. This value should be greater than zero. The CP never modifies the data length in a TxBD. Tx data buffer pointer, which contains the address of the associated data buffer, can be even or odd. The buffer can reside in external memory. The CP never modifies the buffer pointer. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 36-28 Freescale Semiconductor Chapter 37 FCC HDLC Controller Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most common protocols. The framing structure of HDLC is shown in Figure 37-1. HDLC uses a zero insertion/deletion process (commonly known as bit stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on the physical layer for a method of clocking and of synchronizing the transmitter/receiver. Because the layer 2 frame can be transmitted over a point-to-point link, a broadcast network, or a packet-and-circuit switched system, an address field is needed for the frame's destination address. The length of this field is commonly 0, 8, or 16 bits, depending on the data link layer protocol. For instance, SDLC and LAPB use an 8-bit address and SS#7 has no address field because it is used always in point-to-point signaling links. LAPD further divides its 16-bit address into different fields to specify various access points within one device. It also defines a broadcast address. Some HDLC-type protocols also permit extended addressing beyond 16 bits. The 8- or 16-bit control field provides a flow-control number and defines the frame type (control or data). The exact use and structure of this field depends upon the protocol using the frame. Data is transmitted in the data field, which can vary in length depending upon the protocol using the frame. Layer 3 frames are carried in this data field. Error control is implemented by appending a cyclic redundancy check (CRC) to the frame, which in most protocols is 16-bits long but can be as long as 32-bits. In HDLC, the lsb of each octet is transmitted first and the msb of the CRC is transmitted first. When GFMR[MODE] selects HDLC mode, that FCC functions as an HDLC controller. When an FCC in HDLC mode is used with a nonmultiplexed modem interface, the FCC outputs are connected directly to the external pins. Modem signals can be supported through the appropriate port pins. The receive and transmit clocks can be supplied either externally or from the bank of baud-rate generators. The HDLC controller can also be connected to one of the TDM channels of the serial interface and used with the TSA. The HDLC controller consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with other FCCs. The user can allocate external buffer descriptors (BDs) for receive and transmit tasks so many frames can be sent or received without core intervention. 37.1 Key Features Key features of the HDLC include the following: • Flexible data buffers with multiple buffers per frame • Separate interrupts for frames and buffers (receive and transmit) • Received frames threshold to reduce interrupt overhead MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-1 FCC HDLC Controller • • • • • • • • • • • • Four address comparison registers with masks Maintenance of four 16-bit error counters Flag/abort/idle generation and detection Zero insertion/deletion 16- or 32-bit CRC-CCITT generation/checking Detection of nonoctet-aligned frames Detection of frames that are too long Programmable flags (0–15) between successive frames External BD table Up to T3 rate Support of time stamp mode for Rx frames Support of nibble mode HDLC (4 bits per clocks) 37.2 HDLC Channel Frame Transmission Processing The HDLC transmitter is designed to work with almost no core intervention. When the core enables a transmitter, it starts sending flags or idles as programmed in the HDLC mode register (FPSMR). The HDLC controller polls the first BD in the transmit channel BD table. When there is a frame to transmit, the HDLC controller fetches the data (address, control, and information) from the first buffer and begins sending the frame after first inserting the user-specified minimum number of flags between frames. When the end of the current buffer is reached and TxBD[L] (last buffer in frame) is set, the FCC appends the CRC (if selected) and closing flag. In HDLC, the lsb of each octet and the msb of the CRC are sent first. Figure 37-1 shows a typical HDLC frame. Opening Flag 8 Bits Address 16 Bits Control 8 Bits Information (Optional) 8n Bits CRC 16 Bits Closing Flag 8 Bits Figure 37-1. HDLC Framing Structure After the closing flag is sent, the HDLC controller writes the frame status bits into the BD and clears the R bit. When the end of the current BD is reached and the L (last) bit is not set (working in multibuffer mode), only the R bit is cleared. In either mode, an interrupt can be issued if the I bit in the TxBD is set. The HDLC controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each buffer, after a specific buffer, after each frame, or after a number of frames. To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT command. This can be useful for sending expedited data before previously linked buffers or for error situations. When receiving the STOP TRANSMIT command, the HDLC controller aborts the current frame transmission and starts transmitting idles or flags. When the HDLC controller is given the RESTART TRANSMIT command, it resumes transmission. To insert a high-priority frame without aborting the current frame, the GRACEFUL STOP TRANSMIT command can be issued. A special interrupt (GRA) can be generated in the event register when the current frame is complete. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-2 Freescale Semiconductor FCC HDLC Controller 37.3 HDLC Channel Frame Reception Processing The HDLC receiver is designed to work with almost no core intervention and can perform address recognition, CRC checking, and maximum frame length checking. The received frame is available for any HDLC-based protocol. When the core enables a receiver, the receiver waits for an opening flag character. When it detects the first byte of the frame, the HDLC controller compares the frame address against the user-programmable addresses. The user has four 16-bit address registers and an address mask available for address matching. The HDLC controller compares the received address field to the user-defined values after masking with the address mask. The HDLC controller can also detect broadcast (all ones) address frames if one address register is written with all ones. If a match is detected, the HDLC controller checks the prefetched BD; if it is empty, it starts transferring the incoming frame to the BD’s associated buffer. When the buffer is full, the HDLC controller clears BD[E] and generates an interrupt if BD[I] = 1. If the incoming frame is larger than the buffer, the HDLC controller fetches the next BD in the table and, if it is empty, continues transferring the frame to the associated buffer. During this process, the HDLC controller checks for frames that are too long. When the frame ends, the CRC field is checked against the recalculated value and written to the buffer. The data length written to the last BD in the HDLC frame is the length of the entire frame. This enables HDLC protocols that lose frames to correctly recognize a frame-too-long condition. The HDLC controller then sets the last buffer in frame bit, writes the frame status bits into the BD, and clears the E bit and fetches the next BD. The HDLC controller then generates a maskable interrupt, indicating that a frame was received and is in memory. The HDLC controller then waits for a new frame. Back-to-back frames can be received separated only by a single shared flag. The user can configure the HDLC controller not to interrupt the core until a specified number of frames have been received. This is configured in the received frames threshold (RFTHR) location of the parameter RAM. This function can be combined with a timer to implement a time-out if fewer than the threshold number of frames are received. 37.4 HDLC Parameter RAM When an FCC operates in HDLC mode, the protocol-specific area of the FCC parameter RAM is mapped with the HDLC-specific parameters in Table 37-1. Table 37-1. FCC HDLC-Specific Parameter RAM Memory Map Offset1 0x3C 0x44 0x48 0x4C Name — C_MASK C_PRES DISFC 2 Width 2 Words Reserved Word Word Hword CRC constant. For the 16-bit CRC-CCITT, initialize C_MASK to 0x0000_F0B8. For the 32-bit CRC-CCITT, initialize C_MASK to 0xDEBB_20E3. CRC preset. For the 16-bit CRC-CCITT, initialize C_PRES to 0x0000_FFFF. For the 32-bit CRC-CCITT, initialize C_PRES to 0xFFFF_FFFF. Discard frame counter. Counts error-free frames discarded due to lack of buffers. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-3 FCC HDLC Controller Table 37-1. FCC HDLC-Specific Parameter RAM Memory Map (continued) Offset1 0x4E 0x50 0x52 0x54 0x58 Name CRCEC2 ABTSC2 NMARC2 MAX_CNT MFLR Width Hword Hword Hword Word Hword Description CRC error counter. Counts frames not addressed to the user or frames received in the BSY condition, but does not include overrun, CD lost, or abort errors. Abort sequence counter Nonmatching address Rx counter. Counts nonmatching addresses received (error-free frames only). See the HMASK and HADDR[1–4] parameter description. Max_length counter. Temporary decrementing counter that tracks frame length. Max frame length register. If the HDLC controller detects an incoming HDLC frame that exceeds the user-defined value in MFLR, the rest of the frame is discarded and the LG (Rx frame too long) bit is set in the last BD belonging to that frame. The HDLC controller waits for the end of the frame and then reports the frame status and length in the last RxBD. MFLR includes all in-frame bytes between the opening and closing flags (address, control, data, and CRC). Received frames threshold. Used to reduce the interrupt overhead that might otherwise occur when a series of short HDLC frames arrives, each causing an RXF interrupt. By programming RFTHR, the user lowers the frequency of RXF interrupts, which occur only when the RFTHR value is reached. Note that the user should provide enough empty RxBDs to receive the number of frames specified in RFTHR. Received frames count. A decrementing counter used to implement this feature. Initialize this counter with RFTHR. HMASK and HADDR[1–4]. The HDLC controller reads the frame address from the HDLC receiver, checks it against the four address register values, and masks the result with HMASK. In HMASK, a 1 represents a bit position for which address comparison should occur; 0 represents a masked bit position. When addresses match, the address and subsequent data are written into the buffers. When addresses do not match and the frame is error-free, the nonmatching address received counter (NMARC) is incremented. Note that for 8-bit addresses, mask out (clear) the eight high-order bits in HMASK. The eight low-order bits and HADDRx should contain the address byte that immediately follows the opening flag. For example, to recognize a frame that begins 0x7E (flag), 0x68, 0xAA, using 16-bit address recognition, HADDRx should contain 0xAA68 and HMASK should contain 0xFFFF. See Figure 37-2. Temporary storage Temporary storage 0x5A RFTHR Hword 0x5C 0x5E 0x60 0x62 0x64 0x66 RFCNT HMASK HADDR1 HADDR2 HADDR3 HADDR4 Hword Hword Hword Hword Hword Hword 0x68 0x6A 1 2 TS_TMP TMP_MB Hword Hword Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.” DISFC, CRCEC, ABTSC, and NMARC—These 16-bit (modulo 216) counters are maintained by the CP. The user can initialize them while the channel is disabled. Figure 37-2 shows an example of using HMASK and HADDR[1–4]. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-4 Freescale Semiconductor FCC HDLC Controller 16-Bit Address Recognition Flag 0x7E Address 0x68 HMASK HADDR1 HADDR2 HADDR3 HADDR4 Address 0xAA Control 0x44 etc. Flag 0x7E 8-Bit Address Recognition Address 0x55 Control 0x44 0x00FF 0xXX55 0xXX55 0xXX55 0xXX55 etc. 0xFFFF 0xAA68 0xFFFF 0xAA68 0xAA68 HMASK HADDR1 HADDR2 HADDR3 HADDR4 Recognizes one 16-bit address (HADDR1) and the 16-bit broadcast address (HADDR2) Recognizes one 8-bit address (HADDR1) Figure 37-2. HDLC Address Recognition Example 37.5 Programming Model The core configures each FCC to operate in the protocol specified in GFMR[MODE]. The HDLC controller uses the same data structure as other modes. This data structure supports multibuffer operation and address comparisons. 37.5.1 HDLC Command Set The transmit and receive commands are issued to the CPCR; see Section 14.4, “Command Set.” Table 37-2 describes the transmit commands that apply to the HDLC controller. Table 37-2. Transmit Commands Command STOP TRANSMIT Description After the hardware or software is reset and the channel is enabled in the FCC mode register, the channel is in transmit enable mode and starts polling the first BD in the table every 256 transmit clocks (immediately if FTODR[TOD] = 1). STOP TRANSMIT command disables the transmission of frames on the transmit channel. If this command is received by the HDLC controller during frame transmission, transmission is aborted after a maximum of 64 additional bits are sent and the transmit FIFO buffer is flushed. The TBPTR is not advanced, no new BD is accessed, and no new frames are sent for this channel. The transmitter sends an abort sequence consisting of 0x7F (if the command was given during frame transmission) and begins sending flags or idles, as indicated by the HDLC mode register. Note that if FPSMR[MFF] = 1, one or more small frames can be flushed from the transmit FIFO buffer. The GRACEFUL STOP TRANSMIT command can be used to avoid this. Used to stop transmission smoothly rather than abruptly, as performed by the regular STOP TRANSMIT command. It stops transmission after the current frame finishes sending or immediately if no frame is being sent. FCCE[GRA] is set once transmission has stopped. Then the HDLC transmit parameters (including BDs) can be modified. The TBPTR points to the next TxBD in the table. Transmission begins once the R bit of the next BD is set and the RESTART TRANSMIT command is issued. GRACEFUL STOP TRANSMIT MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-5 FCC HDLC Controller Table 37-2. Transmit Commands (continued) Command RESTART TRANSMIT Description Enables character transmission on the transmit channel. This command is expected by the HDLC controller after a STOP TRANSMIT command, after a STOP TRANSMIT command is issued and the channel in its FCC mode register is disabled, after a GRACEFUL STOP TRANSMIT command, or after a transmitter error (underrun or CTS lost with no automatic frame retransmission). The HDLC controller resumes sending from the current TBPTR in the channel TxBD table. Initializes all transmit parameters in this serial channel parameter RAM to their reset state. This command should only be issued when the transmitter is disabled. Notice that the INIT TX AND RX PARAMETERS command can also be used to reset the transmit and receive parameters. INIT TX PARAMETERS Table 37-3 describes the receive commands that apply to the HDLC controller. Table 37-3. Receive Commands Command ENTER HUNT MODE Description After the hardware or software is reset and the channel is enabled in the FCC mode register, the channel is in receive enable mode and uses the first BD in the table. The ENTER HUNT MODE command is generally used to force the HDLC receiver to abort reception of the current frame and enter the hunt mode. In hunt mode, the HDLC controller continually scans the input data stream for the flag sequence. After receiving the command, the current receive buffer is closed, the error status flags and length field are cleared, RxBD[E] (the empty bit) is set, and the CRC calculation is reset. Further frame reception uses the current RxBD. Initializes all the receive parameters in this serial channel parameter RAM to their reset state and should be issued only when the receiver is disabled. Notice that the INIT TX AND RX PARAMETERS command resets both receive and transmit parameters. INIT RX PARAMETERS 37.5.2 HDLC Error Handling The HDLC controller reports frame reception and transmission error conditions using the channel BDs, error counters, and HDLC event register (FCCE). Table 37-4 describes HDLC transmission errors, which are reported through the TxBD. Table 37-4. HDLC Transmission Errors Error Transmitter Underrun Description When this error occurs, the channel terminates buffer transmission, transmit an ABORT sequence (a sequence which will generate CRC error on the frame), closes the buffer, sets the underrun (U) bit in the BD, and generates the TXE interrupt if it is enabled. The channel resumes transmission after receiving the RESTART TRANSMIT command. CTS Lost during When this error occurs, the channel terminates buffer transmission, closes the buffer, sets TxBD[CT], and generates a TXE interrupt (if it is enabled). The channel resumes transmission after Frame receiving the RESTART TRANSMIT command. Transmission MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-6 Freescale Semiconductor FCC HDLC Controller Table 37-5 describes HDLC reception errors, which are reported through the RxBD. Table 37-5. HDLC Reception Errors Error Overrun Error Description The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins programming the SDMA channel and updating the CRC whenever data is received in the FIFO buffer. When a receive FIFO overrun occurs, the channel writes the received data byte to the internal FIFO buffer over the previously received byte. The previous byte and the frame status are lost. The channel closes the buffer with RxBD[OV] set and generates the RXF interrupt if it is enabled. The receiver then enters hunt mode. Even if the overrun occurs during a frame whose address is not matched in the address recognition logic, an RxBD with data length two is opened to report the overrun and the RXF interrupt is generated if it is enabled. When this error occurs, the channel terminates frame reception, closes the buffer, sets RxBD[CD], and generates the RXF interrupt if it is enabled. This error has highest priority. The rest of the frame is lost and other errors are not checked in that frame. At this point, the receiver enters hunt mode. If CD is Lost during the first 8 serial bits it will not be reported as CD Lost error and there will be no indication of error. CD Lost During Frame Reception Abort Sequence The HDLC controller detects an abort sequence when seven or more consecutive ones are received. When this error occurs and the HDLC controller receives a frame, the channel closes the buffer by setting RxBD[AB] and generates the RXF interrupt (if enabled). The channel also increments the abort sequence counter. The CRC and nonoctet error status conditions are not checked on aborted frames. The receiver then enters hunt mode. When an abort sequence is received, the user is given no indication that an HDLC controller is not currently receiving a frame. Nonoctet Aligned Frame When this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets the Rx nonoctet aligned frame bit RxBD[NO], and generates the RXF interrupt (if it is enabled). The CRC error status should be disregarded on nonoctet frames. After a nonoctet aligned frame is received, the receiver enters hunt mode. An immediate back-to-back frame is still received. The nonoctet data portion may be derived from the last byte in the buffer by finding the least-significant set bit, which marks the end of valid data as follows: msb Valid data CRC Error 1 0 0 lsb 0 When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer, sets RxBD[CR], and generates the RXF interrupt (if it is enabled). The channel also increments the CRC error counter. After receiving a frame with a CRC error, the receiver enters hunt mode. An immediate back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-7 FCC HDLC Controller 37.6 HDLC Mode Register (FPSMR) When an FCC is configured for HDLC mode, the FPSMR is used as the HDLC mode register, shown in Figure 37-3. 0 3 4 5 6 8 9 10 15 Field Reset R/W Addr 16 NOF FSE MFF — TS — 0000_0000_0000_0000 R/W 0x11304 (FPSMR1), 0x11324 (FPSMR2), 0x11324 (FPSMR3) 17 23 24 25 26 31 Field NBL Reset R/W Addr — CRC 0000_0000_0000_0000 R/W — 0x11306 (FPSMR1), 0x11326 (FPSMR2), 0x11326 (FPSMR3) Figure 37-3. HDLC Mode Register (FPSMR) The FPSMR fields are described in Table 37-6. Table 37-6. FPSMR Field Descriptions 1 Bits 0–3 Name NOF Description Number of flags. Minimum number of flags between or before frames (0–15 flags). If NOF = 0000, no flags are inserted between the frames. Thus, for back-to-back frames, the closing flag of one frame is immediately followed by the opening flag of the next frame. Flag sharing enable. This bit is valid only if GFMR[RTSM] is set. 0 Normal operation 1 If NOF = 0000, a single shared flag is transmitted between back-to-back frames. Other values of NOF are decremented by 1 when FSE is set. This is useful in signaling system #7 applications. Multiple frames in FIFO. Setting MFF applies only when in RTS mode (GFMRx[RTSM] = 1). 0 Normal operation. The transmit FIFO buffer must never contain more than one HDLC frame. The CTS lost status is reported accurately on a per-frame basis. The receiver is not affected by this bit. 1 The transmit FIFO buffer can contain multiple frames, but lost CTS is not guaranteed to be reported on the exact buffer/frame it occurred on. This option, however, can improve the performance of HDLC transmissions for small back-to-back frames or if the user prefers to strongly limit the number of flags sent between frames. MFF does not affect the receiver. Refer to note 1 at the end of this table. Reserved, should be cleared. Time stamp 0 Normal operation. 1 A 32-bit time stamp is added at the beginning of the receive BD data buffer, thus the buffer pointer must be (32-byte aligned - 4). The BD’s data length does not include the time stamp. See Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” Reserved, should be cleared. 4 FSE 5 MFF 7–8 9 — TS 10–15 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-8 Freescale Semiconductor FCC HDLC Controller Table 37-6. FPSMR Field Descriptions (continued)1 Bits 16 Name NBL Description Nibble mode enable 0 Nibble mode disabled (1 bit of data per clock). Note that at the end of the frame (after the closing flag), RTS negates immediately after the active edge of TCLK. 1 Nibble mode enabled (4 bits of data per clock). The negation of the RTS output signal is not synchronized to the serial clock. The RTS is negated after the last nibble of the data and always before the next edge of the serial clock. Note that at the end of the frame (after the closing flag), RTS negates a maximum of 5 CPM clocks after the active edge of TCLK. Reserved, should be cleared. CRC selection 00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1 01 Reserved 10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1 11 Reserved Reserved, should be cleared. 17–23 24-25 — CRC 26–31 1 — When operating an FCC in HDLC nibble mode with the multiframe per FIFO bit off (FPSMR[MFF] = 0), the CPM might lose synchronization with the FCC HDLC controller. As a result the HDLC controller will become stuck and stop transmission. Therefore in HDLC nibble mode, FPSMR[MFF] must be set or the FCC must alternatively operate in HDLC bit mode. 37.7 HDLC Receive Buffer Descriptor (RxBD) The HDLC controller uses the RxBD to report on data received for each buffer. Figure 37-4 shows an example of the RxBD process. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-9 FCC HDLC Controller E Status Length Pointer 0 RxBD 0 LF 01 0x0020 32-Bit Buffer Pointer Buffer Full MRBLR = 32 Bytes for this FCC Buffer Address 1 Address 2 Control Byte 29 Information (I-Field) Bytes 32 Bytes E Status Length Pointer 0 RxBD 1 LF 10 0x0023 32-Bit Buffer Pointer Buffer Closed When Closing Flag Received Buffer Last I-Field Byte CRC Byte 1 CRC Byte 2 Empty 32 Bytes E Status Length Pointer 0 RxBD 2 LF 11 0x0003 AB 1 Buffer Address 1 Address 2 Abort was Received after Control Byte Control Byte Empty Buffer 32 Bytes 32-Bit Buffer Pointer RxBD 3 E Status Length Pointer 1 XXXX 32-Bit Buffer Pointer Buffer Still Empty Empty 32 Bytes Stored in Rx Buffer F A A C I I ... I CR CR F Line Idle Stored in Rx Buffer F A A C Abort/Idle Two Frames Received in HDLC Time Legend: F = Flag A = Address Byte C = Control Byte I = Information Byte CR = CRC Byte Unexpected Abort Present Time Occurs before Closing Flag Figure 37-4. FCC HDLC Receiving Using RxBDs MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-10 Freescale Semiconductor FCC HDLC Controller Figure 37-5 shows the FCC HDLC RxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I L F CM — Data Length LG NO AB CR OV CD Rx Data Buffer Pointer Figure 37-5. FCC HDLC Receive Buffer Descriptor (RxBD) Table 37-7 describes RxBD fields. Table 37-7. RxBD field Descriptions Bits 0 Name E Description Empty 0 The buffer is full with received data or data reception stopped because of an error. The core can read or write to any fields of this RxBD. The CP does not use this BD while E = 0. 1 The buffer associated with this BD is empty. This RxBD and its associated receive buffer are owned by the CP. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (final BD in table) 0 Not the last BD in the RxBD table. 1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data into the first BD that RBASE points to in the table. The number of RxBDs in this table is programmable and is determined only by the W bit and the overall space constraints of the dual-port RAM. The RxBD table must contain more than one BD in HDLC mode. Interrupt 0 The RXB bit is not set after this buffer is used, but RXF operation remains unaffected. 1 FCCE[RXB] or FCCE[RXF] is set when the HDLC controller uses this buffer. These two bits can cause interrupts if they are enabled. Last in frame. Set by the HDLC controller when this buffer is the last one in a frame. This implies the reception of a closing flag or reception of an error, in which case one or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to the data length field. 0 Not the last buffer in a frame. 1 Last buffer in a frame. First in frame. Set by the HDLC controller when this buffer is the first in a frame. 0 Not the first buffer in a frame. 1 First buffer in a frame. Continuous mode 0 Normal operation. 1 The E bit is not cleared by the CP after this BD is closed, allowing the associated data buffer to be automatically overwritten the next time the CP accesses this BD. However, the E bit is cleared if an error occurs during reception, regardless of the CM bit. Reserved, should be cleared. Rx frame length violation. A frame length greater than the maximum defined for this channel is recognized, and only the maximum-allowed number of bytes (MFLR) is written to the data buffer. This event is not reported until the RxBD is closed, the RXF bit is set, and the closing flag is received. The number of bytes received between flags is written to the data length field of this BD. 1 2 — W 3 I 4 L 5 F 6 CM 7–9 10 — LG MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-11 FCC HDLC Controller Table 37-7. RxBD field Descriptions (continued) Bits 11 12 13 14 15 Name NO AB CR OV CD Description Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by eight. Rx abort sequence. At least seven consecutive 1s are received during frame reception. Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive buffer. Overrun. A receiver overrun occurs during frame reception. Carrier detect lost. CD has negated during frame reception. This bit is valid only for NMSI mode. The RxBD status bits are written by the HDLC controller after receiving the associated data buffer. The remaining RxBD parameters are as follows: • Data length is the number of octets the CP writes into this BD’s data buffer. It is written by the CP once the BD is closed. When this is the last BD in the frame (L = 1), this field contains the total number of frame octets, including 2 or 4 bytes for CRC. The memory allocated for this buffer should be no smaller than the MRBLR value. • Rx data buffer pointer. The receive buffer pointer, which always points to the first location of the associated data buffer, resides in internal or external memory and must be divisible by 32 unless FPSMR[TS] = 1 (see Table 37-6). 37.8 HDLC Transmit Buffer Descriptor (TxBD) Data is presented to the HDLC controller for transmission on an FCC channel by arranging it in buffers referenced by the channel TxBD table. The HDLC controller confirms transmission (or indicates errors) using the BDs to inform the core that the buffers have been serviced. Figure 37-6 shows the FCC HDLC TxBD. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R — W I L TC CM Data Length Tx Data Buffer Pointer — UN CT Figure 37-6. FCC HDLC Transmit Buffer Descriptor (TxBD) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-12 Freescale Semiconductor FCC HDLC Controller Table 37-8 describes HDLC TxBD fields. Table 37-8. HDLC TxBD Field Descriptions Bits 0 Name R Description Ready 0 The buffer associated with this BD is not ready for transmission. The user can manipulate this BD or its associated buffer. The CP clears R after the buffer has been sent or an error occurs. 1 The buffer is ready to be sent. The transmission may have begun, but it has not completed. The user cannot set fields in this BD once R is set. Reserved, should be cleared. Wrap (final BD in table) 0 Not the last BD in the TxBD table. 1 Last BD in the TxBD table. After this buffer has been used, the CP sends data from the first BD that TBASE points to in the table. The number of TxBDs in this table is determined only by the W bit and the overall space constraints of the dual-port RAM. Interrupt 0 No interrupt is generated after this buffer is serviced; FCCE[TXE] is unaffected. 1 Either FCCE[TXB] or FCCE[TXE] is set when this buffer is serviced by the HDLC controller. These bits can cause interrupts if they are enabled. Last 0 Not the last buffer in the frame. 1 Last buffer in the current frame. Tx CRC.Valid only when the L bit is set. Otherwise, it is ignored. 0 Transmit the closing flag after the last data byte. This setting can be used to send a bad CRC after the data for testing purposes. 1 Transmit the CRC sequence after the last data byte. Continuous mode 0 Normal operation. 1 The R bit is not cleared by the CP after this BD is closed, allowing the buffer to be retransmitted automatically the next time the CP accesses this BD. However, the R bit is cleared if an error occurs during transmission, regardless of the CM bit. Reserved, should be cleared. Underrun. The HDLC controller encounters a transmitter underrun condition while sending the buffer. The HDLC controller writes UN after sending the buffer. CTS lost. Set when CTS is lost during frame transmission in NMSI mode. If data from more than one buffer is in the FIFO buffer when this error occurs, CT is set in the currently open TxBD. The HDLC controller writes CT after sending the buffer. 1 2 — W 3 I 4 L 5 TC 6 CM 7–13 14 15 — UN CT The TxBD status bits are written by the HDLC controller after sending the associated data buffer. The remaining TxBD parameters are as follows: • Data length is the number of bytes the HDLC controller should transmit from this data buffer; it is never modified by the CP. The value of this field should be greater than zero. • Tx data buffer pointer. The transmit buffer pointer, which contains the address of the associated data buffer, can be even or odd. The buffer can reside in internal or external memory. This value is never modified by the CP. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-13 FCC HDLC Controller 37.9 HDLC Event Register (FCCE)/Mask Register (FCCM) The FCCE is used as the HDLC event register when the FCC operates as an HDLC controller. The FCCE reports events recognized by the HDLC channel and generates interrupts. On recognition of an event, the HDLC controller sets the corresponding FCCE bit. FCCE bits are cleared by writing ones; writing zeros does not affect bit values. All unmasked bits must be cleared before the CP clears the internal interrupt request. Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM), which has the same bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt in the event register is enabled. If the bit is 0, the interrupt is masked. Figure 37-7 represents the FCC/FCCM. 0 1 2 3 — 4 5 6 7 8 GRA 0000_0000_0000_0000 9 — 10 11 TXE 12 RXF 13 BSY 14 TXB 15 RXB Field Reset R/W Addr R/W 0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/ 0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Reset R/W Addr — FLG IDL — 0000_0000_0000_0000 R/W 0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/ 0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3) Figure 37-7. HDLC Event Register (FCCE)/Mask Register (FCCM) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-14 Freescale Semiconductor FCC HDLC Controller Table 37-9 describes FCCE/FCCM fields. Table 37-9. FCCE/FCCM Field Descriptions Bits 0–7 8 Name — GRA Reserved, should be cleared. Graceful stop complete. A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is now complete. GRA is set as soon as the transmitter finishes transmitting any frame that is in progress when the command was issued. It is set immediately if no frame is in progress when the command is issued. Reserved, should be cleared. Tx error. An error (CTS lost or underrun) occurs on the transmitter channel. This event is not maskable via the TxBD[I] bit. Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two clocks after receipt of the last bit of the closing flag. Busy condition. A frame is received and discarded due to a lack of buffers. Transmit buffer. Enabled by setting TxBD[I]. A buffer is sent on the HDLC channel. TXB is set no sooner than when the last bit of the closing flag begins its transmission if the buffer is the last one in the frame. Otherwise, TXB is set after the last byte of the buffer is written to the transmit FIFO buffer. Receive buffer. When RXB = 1, a buffer for which the I bit is set in the corresponding BD was filled, regardless if the end of a frame was completed in it. Reserved, should be cleared. Flag status changed. The HDLC controller stops or starts receiving HDLC flags. The real-time status can be obtained in FCCS; see Section 37.10, “FCC Status Register (FCCS).” Idle sequence status changed. A change in the status of the serial line is detected on the HDLC line. The real-time status can be read in FCCS; see Section 37.10, “FCC Status Register (FCCS).” Reserved, should be cleared. Description 9–10 11 12 13 14 — TXE RXF BSY TXB 15 16–21 22 23 24–31 RXB — FLG IDL — Figure 37-8 shows interrupts that can be generated in the HDLC protocol. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-15 FCC HDLC Controller Frame Received by HDLC Time RXD Line Idle F F A Stored in Rx Buffer A C I I I CR CR F Line Idle CD HDLC FCCE Events CD IDL FLG FLG RXB RXF FLG IDL FLG CD Notes: 1. RXB event assumes receive buffers are 6 bytes each. 2. The second IDL event occurs after 15 ones are received in a row. 3. The FLG interrupts show the beginning and end of flag reception. 4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency. 5. The CD event must be programmed in the parallel I/O port, not in the FCC itself. 6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte Frame Transmitted by HDLC TXD Line Idle F Stored in Tx Buffer F A A C CR CR F Line Idle RTS CTS HDLC FCCE Events CT TXB CT Notes: 1. TXB event shown assumes all three bytes were put into a single buffer. 2. Example shows one additional opening flag. This is programmable. 3. The CT event must be programmed in the parallel I/O port, not in the FCC itself. Figure 37-8. HDLC Interrupt Event Example 37.10 FCC Status Register (FCCS) The FCCS register, shown in Figure 37-9, allows the user to monitor real-time status conditions on the RXD line. The real-time status of the CTS and CD signals are part of the parallel I/O port; see Chapter 41, “Parallel I/O Ports.” 0 1 2 3 4 5 6 7 Field Reset R/W Addr — 0000_0000 R FG — ID 0x11318 (FCCS1), 0x11338 (FCCS2), 0x11358 (FCCS3) Figure 37-9. FCC Status Register (FCCS) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-16 Freescale Semiconductor FCC HDLC Controller Table 37-10 describes FCCS bits. Table 37-10. FCCS Register Field Descriptions Bits 0–4 5 Name — FG Reserved, should be cleared. Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are examined to see if a flag is present. FG is set as soon as an HDLC flag (0x7E) is received on the line. Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined. If another flag occurs, FG stays set for at least another eight bits. Otherwise, FG is cleared and the search begins again. • 0HDLC flags are not currently being received. • 1HDLC flags are currently being received. Reserved, should be cleared. Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is cleared after a logic zero is received. • 0The line is busy. • 1The line is idle. Description 6 7 — ID MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 37-17 FCC HDLC Controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 37-18 Freescale Semiconductor Chapter 38 FCC Transparent Controller The FCC transparent controller functions as a high-speed serial-to-parallel and parallel-to-serial converter. Transparent mode provides a clear channel on which the FCC performs no bit-level manipulation—implementing higher-level protocols would require software. Transparent mode is also referred to as a totally transparent or promiscuous operation. Basic applications for an FCC in transparent mode include the following: • For data, such as voice, moving serially without the need for protocol processing • For board-level applications, such as chip-to-chip communications, requiring a serial-to-parallel and parallel-to-serial conversion • For applications requiring the switching of data paths without altering the protocol encoding itself, such as a multiplexer in which data from a high-speed TDM serial stream is divided into multiple low-speed data streams An FCC transmitter and receiver can be programmed in transparent mode independently. Setting GFMRx[TTx] enables the transparent transmitter; setting GFMRx[TRx] enables the transparent receiver. Both bits must be set for full-duplex transparent operation. If only one bit is set, the other half of the FCC operates with the protocol programmed in GFMRx[MODE]. This allows loopback modes to transfer data from one memory location to another (using DMA) while the data is converted to a specific serial format. However, the Ethernet and ATM controllers cannot be split in this way. See Section 30.2, “General FCC Mode Registers (GFMRx).” The FCC in transparent mode can work with the TSA or NMSI and support modem lines using the general-purpose I/O signals. The data can be transmitted and received with msb or lsb first in each octet. The FCC consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to the other FCCs. Each clock can be supplied from the internal BRG bank or external signals. 38.1 Features The following is a list of the transparent controller’s important features: • Flexible data buffers • Automatic SYNC detection on receive — 16-bit pattern — 8-bit pattern — Automatic sync (always synchronized) — External sync signal support • CRCs can optionally be transmitted and received MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 38-1 FCC Transparent Controller • • • Reverse data mode Another protocol can be performed on the FCC’s other half (transmitter or receiver) during transparent mode External BD table 38.2 Transparent Channel Operation The transparent transmitter and receiver operates in the same way as the HDLC controller of the FCC (see Chapter 37, “FCC HDLC Controller”) except in the following ways: 1. The FPSMR does not affect the transparent controller, only the GFMR does. 2. In Table 37-1 on page 37-3, MFLR, HMASK, RFTHR, and RFCNT must be cleared for proper operation of the transparent receiver. 3. Transmitter synchronization has to be achieved using CTS before the transmitter begins sending; see Section 38.3, “Achieving Synchronization in Transparent Mode.” 38.3 Achieving Synchronization in Transparent Mode Once the FCC transmitter is enabled for transparent operation in the GFMR, the TxBD is prepared for the FCC, and the transmit FIFO is preloaded by the SDMA channel, transmit synchronization must be established before data can be sent. Similarly, once the FCC receiver is enabled for transparent operation in the GFMR and the RxBD is made empty for the FCC, receive synchronization must occur before data can be received. The synchronization process gives the user bit-level control of when the transmission and reception begins. The methods for this are as follows: • An in-line synchronization pattern • External synchronization signals • Automatic sync 38.3.1 In-Line Synchronization Pattern The transparent channel can be programmed to transmit and receive a synchronization pattern if GFMR[SYNL] ≠ 0; see Section 30.2, “General FCC Mode Registers (GFMRx).” The pattern is defined in the FDSR; see Section 30.4, “FCC Data Synchronization Registers (FDSRx).” GFMR[SYNL] defines the SYNC pattern length. The synchronization pattern is shown in Figure 38-1. 0 7 8 15 Field Field 8-Bit Sync Pattern 16-Bit Sync Pattern (Second Byte) — (First Byte) Figure 38-1. In-Line Synchronization Pattern MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 38-2 Freescale Semiconductor FCC Transparent Controller The receiver synchronizes on the synchronization pattern located in the FDSR. For instance, if an 8-bit SYNC is selected, reception begins as soon as these eight bits are received, beginning with the first bit following the 8-bit SYNC. This effectively links the transmitter synchronization to the receiver synchronization. 38.3.2 External Synchronization Signals If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the transmitter and CD is used for the receiver; these signals share the following sampling options. • The pulse/envelope option determines whether CD or CTS need to be asserted only once to begin reception/transmission or whether they must be asserted and stay that way for the duration of the transparent frame. This option is controlled by the CDP and CTSP bits of the GFMR. If the user expects a continuous stream of data without interruption, the pulse option should be used. However, if the user needs to identify frames of transparent data, the envelope mode of the these signals should be used. Note that the first bit of a frame is transmitted as zero every time RTS is asserted before CTS is asserted (GFMR[CTSS] = 1); subsequent data bits are sent accurately. Similarly, if CTS is in pulse mode (GFMR[CTSP] = 1), only the first frame is affected. If CTS is not in pulse mode (GFMR[CTSP] = 0), every frame is affected separately. Note that if NRZI encoding is used (GFMR[TENC]=01), RTS must be asserted before CTS, or else the first bit of the frame might be corrupted. The sampling option determines the delay between CD and CTS being asserted and the resulting action by the FCC. These signals can be assumed to be asynchronous to the data and then internally synchronized by the FCC, or they can be assumed to be synchronous to the data giving faster operation. This option allows the RTS of one FCC to be connected to the CD of another FCC (on another MPC8280) and to have the data synchronized and bit aligned. It is also an option to link the transmitter synchronization to the receiver synchronization. • When working with the FCC receiver in envelope mode, RTS should be asserted for at least 3 clock cycles between frames. Otherwise, the receiver cannot recognize the start of a new frame. Diagrams for the pulse/envelope and sampling options are in Section 30.11, “FCC Timing Control.” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 38-3 FCC Transparent Controller 38.3.3 Transparent Synchronization Example MPC8280 (A) TXD RTS BRGOx RXD CD CLKx MPC8280 (B) RXD CD CLKx TXD RTS BRGOx Figure 38-2 shows an example of synchronization using external signals. BRGOx (Output is CLKx Input) TXD (Output is RXD Input) RTS (Output is CD Input) Last Bit of Frame Data First Bit of Frame Data or CRC TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame Notes: 1 Each MPC8280 generates its own transmit clocks. If the transmit and receive clocks are the same, one can generate transmit and receive clocks for the other MPC8280. For example, CLKx on MPC8280 (B) could be used to clock the transmitter and receiver 2 CTS should be configured as always asserted in the parallel I/O port or connected to ground externally. 3 The required GSMR configurations are DIAG= 00, CTSS=1, CTSP is a don’t care, CDS=1, CDP=0, TTX=1, and TRX=1. REVD and TCRC are application-dependent. 4 The transparent frame contains a CRC if TxBD[TC] is set. Figure 38-2. Sending Transparent Frames between MPC8280s MPC8280(A) and MPC8280(B) exchange transparent frames and synchronize each other using RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is connected directly to the other MPC8280’s CD. GFMR[SYNL] is not used and transmission and reception from each MPC8280 are independent. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 38-4 Freescale Semiconductor Chapter 39 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC8280 to exchange data between other MPC8280 chips, the MPC860, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit. The transmitter and receiver sections use the same clock, which is derived from the SPI baud rate generator in master mode and generated externally in slave mode. During an SPI transfer, data is sent and received simultaneously. Because the SPI receiver and transmitter are double-buffered, as shown in Figure 39-1, the effective FIFO size (latency) is 2 characters. The SPI’s msb is shifted out first. When the SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power. 60x Bus Peripheral Bus SPI Mode Register Transmit_Register Receive_Register Counter RxD IN_CLK Shift_Register TxD Pins Interface SPIBRG BRGCLK SPISEL SPIMOSI SPIMISO SPICLK Figure 39-1. SPI Block Diagram 39.1 Features The following is a list of the SPI’s main features: • Four-signal interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL) multiplexed with port D signals • Full-duplex operation • Works with data characters from 4 to 16 bits long MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-1 Serial Peripheral Interface (SPI) • • • • • • • • • Supports back-to-back character transmission and reception Master or slave SPI modes supported Multimaster environment support Continuous transfer mode for automatic scanning of a peripheral Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode, assuming a 100-MHz system clock Independent programmable baud rate generator Programmable clock phase and polarity Open-drain outputs support multimaster configuration Local loopback capability for testing 39.2 SPI Clocking and Signal Functions The SPI can be configured as a slave or as a master in single- or multiple-master environments. The master SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG). The SPI BRG takes its input from BRGCLK, which is generated in the MPC8280 clock synthesizer. SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured with SPMODE[CI, CP]. SPI signals can also be configured as open-drain to support a multimaster configuration in which a shared SPI signal is driven by the MPC8280 or an external SPI device. The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to communicate with one another using a common hardware configuration. • When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI’s SPISEL while it is master causes an error. • When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a multimaster environment, SPISEL (always an input) is used to detect an error when more than one master is operating. As described in Chapter 41, “Parallel I/O Ports,” SPIMISO, SPIMOSI, SPICLK, and SPISEL are multiplexed with port D[16–19] signals, respectively. They are configured as SPI signals through the port D signal assignment register (PDPAR) and the port D data direction register (PDDIR), specifically by setting PDPAR[DDn] and PDDIR[DRn]. 39.3 Configuring the SPI Controller The SPI can be programmed to work in a single- or multiple-master environment. This section describes SPI master and slave operation in a single-master configuration and then discusses the multi-master environment. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-2 Freescale Semiconductor Serial Peripheral Interface (SPI) 39.3.1 The SPI as a Master Device In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply. A single master MPC8280 with multiple slaves can use general-purpose parallel I/O signals to selectively enable slaves, as shown in Figure 39-2. To eliminate the multimaster error in a single-master environment, the master’s SPISEL input can be forced inactive by selecting port D[19] for general-purpose I/O (PDPAR[DD19] = 0). MPC8280 Slave 0 SPIMOSI SPIMISO SPICLK M aster SPI Slave 1 SPIMOSI SPIMISO The SPISEL decoder can be either internal or external logic. SPICLK SPISEL SPIMOSI SPIMISO SPICLK SPISEL Slave 2 SPIMOSI SPIMISO SPICLK SPISEL Figure 39-2. Single-Master/Multi-Slave Configuration To start exchanging data, the core writes the data to be sent into a buffer, configures a TxBD with TxBD[R] set, and configures one or more RxBDs. The core then sets SPCOM[STR] in the SPI command register to start sending data, which starts once the SDMA channel loads the Tx FIFO with data. The SPI then generates programmable clock pulses on SPICLK for each character and simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data is written into a Rx buffer using the next available RxBD. The SPI keeps sending and receiving characters until the whole buffer is sent or an error occurs. The CP then clears TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt controller in the SIU. When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD is processed after data from the current buffer is sent. Typically there is no delay on SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer is not full; therefore, Rx buffers need not be the same length as Tx buffers. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-3 Serial Peripheral Interface (SPI) 39.3.2 The SPI as a Slave Device In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slave’s SPISEL must be asserted before Rx clocks are recognized; once SPISEL is asserted, SPICLK becomes an input from the master to the slave. SPICLK can be any frequency from DC to BRGCLK/2 (12.5 MHz for a 25-MHz system). To prepare for data transfers, the slave’s core writes data to be sent into a buffer, configures a TxBD with TxBD[R] set, and configures one or more RxBDs. The core then sets SPCOM[STR] to activate the SPI. Once SPISEL is asserted, the slave shifts data out from SPIMISO and in through SPIMOSI. A maskable interrupt is issued when a full buffer finishes receiving and sending or after an error. The SPI uses successive RxBDs in the table to continue reception until it runs out of Rx buffers or SPISEL is negated. Transmission continues until no more data is available or SPISEL is negated. If it is negated before all data is sent, it stops but the TxBD stays open. Transmission continues once SPISEL is reasserted and SPICLK begins toggling. After the characters in the buffer are sent, the SPI sends ones as long as SPISEL remains asserted. 39.3.3 The SPI in Multimaster Operation The SPI can operate in a multimaster environment in which SPI devices are connected to the same bus. In this configuration, the SPIMOSI, SPIMISO, and SPICLK signals of all SPIs are shared; the SPISEL inputs are connected separately, as shown in Figure 39-3. Only one SPI device can act as master at a time—all others must be slaves. When an SPI is configured as a master and its SPISEL input is asserted, a multimaster error occurs because more than one SPI device is a bus master. The SPI sets SPIE[MME] in the SPI event register and a maskable interrupt is issued to the core. It also disables SPI operation and the output drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again. After correcting the problems, clear SPIE[MME] and reenable the SPI. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-4 Freescale Semiconductor Serial Peripheral Interface (SPI) MPC8280 SPI #0 SPIMOSI SPIMISO SPICLK SPISEL SELOUT1 SELOUT2 SELOUT3 MPC8280 SPI #1 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT2 SELOUT3 MPC8280 SPI #2 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT3 MPC8280 SPI #3 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT2 Notes: • All signals are open-drain • For a system with more than two masters, SPISEL and SPIE[MME] do not detect all possible conflicts • It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example) • SELOUTx signals are implemented in software with general-purpose I/O signals Figure 39-3. Multi-Master Configuration The maximum sustained data rate that the SPI supports is SYSTEMCLK/50. However, the SPI can transfer a single character at much higher rates—SYSTEMCLK/4 in master mode and SYSTEMCLK/2 in slave MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-5 SPISEL0 SPISEL1 SPISEL2 SPISEL3 Serial Peripheral Interface (SPI) mode. Gaps should be inserted between multiple characters to keep from exceeding the maximum sustained data rate. 39.4 Programming the SPI Registers The following sections describe the registers used in configuring and operating the SPI. 39.4.1 SPI Mode Register (SPMODE) The SPI mode register (SPMODE), shown in Figure 39-4, controls both the SPI operation mode and clock source. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr — LOOP CI CP DIV16 REV M/S EN LEN PM 0000_00 — R/W 0x11AA0 0_0000_0000 Figure 39-4. SPMODE—SPI Mode Register Table 39-1 describes the SPMODE fields. Table 39-1. SPMODE Field Descriptions Bits 0 1 Name — Reserved, should be cleared. Description LOOP Loop mode. Enables local loopback operation. 0 Normal operation. 1 Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data is ignored. CI Clock invert. Inverts SPI clock polarity. See Figure 39-5 and Figure 39-6. 0 The inactive state of SPICLK is low. 1 The inactive state of SPICLK is high. Clock phase. Selects the transfer format. See Figure 39-5 and Figure 39-6. 0 SPICLK starts toggling at the middle of the data transfer. 1 SPICLK starts toggling at the beginning of the data transfer. 2 3 CP 4 DIV16 Divide by 16. Selects the clock source for the SPI baud rate generator when configured as an SPI master. In slave mode, SPICLK is the clock source. 0 BRGCLK is the input to the SPI BRG. 1 BRGCLK/16 is the input to the SPI BRG. REV Reverse data. Determines the receive and transmit character bit order. 0 Reverse data—lsb of the character sent and received first. 1 Normal operation—msb of the character sent and received first. Master/slave. Selects master or slave mode. 0 The SPI is a slave. 1 The SPI is a master. 5 6 M/S MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-6 Freescale Semiconductor Serial Peripheral Interface (SPI) Table 39-1. SPMODE Field Descriptions (continued) Bits 7 Name EN Description Enable SPI. Do not change other SPMODE bits when EN is set. 0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not functioning and the input clock is disabled. 1 The SPI is enabled. Configure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as described in Section 41.2, “Port Registers. “ Character length in bits per character. If the character length is not greater than a byte, every byte in memory holds (LEN+1) valid bits. If the character length is greater than a byte, every half-word holds (LEN+1) valid bits. See Section 39.4.1.1, “SPI Examples with Different SPMODE[LEN] Values.” 0000–0010 Reserved, causes erratic behavior. 0011 4-bit characters … 1111 16-bit characters Prescale modulus select. Specifies the divide ratio of the prescale divider in the SPI clock generator. BRGCLK is divided by 4 * ([PM0–PM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle. 8–11 LEN 12–15 PM SPICLK SPICLK SPIMOSI (From Master) SPIMISO (From Slave) SPISEL (CI = 0) (CI = 1) msb msb lsb lsb Q NOTE: Q = Undefined Signal. Figure 39-5. SPI Transfer Format with SPMODE[CP] = 0 Figure 39-6 shows the SPI transfer format in which SPICLK starts toggling at the beginning of the transfer (SPMODE[CP] = 1). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-7 Serial Peripheral Interface (SPI) SPICLK SPICLK SPIMOSI (From Master) SPIMISO (From Slave) SPISEL (CI = 0) (CI = 1) msb Q msb lsb lsb NOTE: Q = Undefined Signal. Figure 39-6. SPI Transfer Format with SPMODE[CP] = 1 39.4.1.1 SPI Examples with Different SPMODE[LEN] Values The examples below show how SPMODE[LEN] is used to determine character length. To help map the process, the conventions shown in Table 39-2 are used in the examples. Table 39-2. Example Conventions Convention g–v x __ 1 _ 1 1 Description Binary symbols Deleted bit Original byte boundary Original 4-bit boundary. Both __ and _ are used to aid readability. Once the data string image is determined, it is always transmitted byte by byte with the lsb of the most-significant byte sent first. For all examples below, assume the memory contains the following binary image: msb ghij_klmn__opqr_stuv lsb Example 1 with LEN=4 (data size=5), the following data is selected: msb xxxj_klmn__xxxr_stuv lsb with REV=0, the data string image is: msb j_klmn__r_stuv lsb the order of the string appearing on the line, a byte at a time is: first nmlk_j__vuts_r last with REV=1,the string has each byte reversed, and the data string image is: msb nmlk_j__vuts_r lsb the order of the string appearing on the line, one byte at a time is: first j_klmn__r_stuv last MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-8 Freescale Semiconductor Serial Peripheral Interface (SPI) Example 2 with LEN=7 (data size=8), the following data is selected: msb ghij_klmn__opqr_stuv lsb the data string is selected: msb ghij_klmn__opqr_stuv lsb with REV=0, the string transmitted, a byte at a time with lsb first is: first nmlk_jihg__vuts_rqpo last with REV=1, the string is byte reversed and transmitted, a byte at a time, with lsb first: first ghij_klmn__opqr_stuv last Example 3 with LEN=0xC (data size=13), the following data is selected: msb ghij_klmn__xxxr_stuv lsb the data string selected is: msb r_stuv__ghij_klmn lsb with REV=0, the string transmitted, a byte at a time with lsb first is: first vuts_r__nmlk_jihg last with REV=1, the string is half-word reversed: msb nmlk_jihg__vuts_r lsb and transmitted a byte at a time with lsb first: first ghij_klmn__r_stuv last 39.4.2 SPI Event/Mask Registers (SPIE/SPIM) The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by writing a 1—writing 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared before the CP clears internal interrupt requests. Figure 39-7 shows both registers. 0 1 2 3 4 5 6 7 Field Reset R/W Addr — MME TXE 0000_0000 R/W — BSY TXB RXB 0x11AA6 (SPIE); 0x11AAA (SPIM) Figure 39-7. SPIE/SPIM—SPI Event/Mask Registers Table 39-3 describes the SPIE/SPIM fields. Table 39-3. SPIE/SPIM Field Descriptions Bits 0–1 2 3 4 Name — MME TXE — Reserved, should be cleared. Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode. Tx error. Set when an error occurs during transmission.This event is not maskable via the TxBD[I] bit. Reserved, should be cleared. Description MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-9 Serial Peripheral Interface (SPI) Table 39-3. SPIE/SPIM Field Descriptions (continued) Bits 5 6 7 Name BSY TXB RXB Description Busy. Set after the first character is received but discarded because no Rx buffer is available. Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two character times to be sure data is completely sent over the transmit signal. Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed. 39.4.3 SPI Command Register (SPCOM) The SPI command register (SPCOM), shown in Figure 39-8, is used to start SPI operation. 0 1 7 Field Reset R/W Addr STR 0000_0000 Write Only 0x11AAD — Figure 39-8. SPCOM—SPI Command Register Table 39-4 describes the SPCOM fields. Table 39-4. SPCOM Field Descriptions Bits 0 Name STR Description Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is asserted. STR is cleared automatically after one system clock cycle. Reserved and should be cleared. 1–7 — 39.5 SPI Parameter RAM The SPI parameter RAM area is similar to the SCC general-purpose parameter RAM. The CP accesses the SPI parameter table using a user-programmed pointer (SPI_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” The SPI parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). Some parameter values must be user-initialized before the SPI is enabled; the CP initializes the others. Once initialized, parameter RAM values do not usually need to be accessed. They should be changed only when the SPI is inactive. Table 39-5 shows the memory map of the SPI parameter RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-10 Freescale Semiconductor Serial Peripheral Interface (SPI) Table 39-5. SPI Parameter RAM Memory Map Offset 1 0x00 0x02 Name RBASE TBASE Width Description Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM. Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are Hword allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling the SPI. Furthermore, do not configure BD tables of the SPI to overlap any other active controller’s parameter RAM. RBASE and TBASE should be divisible by eight. Byte Byte Rx/Tx function code registers. The function code registers contain the transaction specification associated with SDMA channel accesses to external memory. See Section 39.5.1, “Receive/Transmit Function Code Registers (RFCR/TFCR).” 0x04 0x05 0x06 RFCR TFCR MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to define the maximum number of bytes the MPC8280 writes to a Rx buffer before moving to the next buffer. The MPC8280 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never exceeds the MRBLR value. User-supplied buffers should be no smaller than MRBLR. Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes to be sent is programmed in TxBD[Data Length]. MRBLR is not intended to be changed while the SPI is operating. However it can be changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). The change takes effect when the CP moves control to the next RxBD. To guarantee the exact RxBD on which the change occurs, change MRBLR only while the SPI receiver is disabled. MRBLR should be greater than zero; it should be an even number if the character length of the data exceeds 8 bits. RSTATE — RBPTR Word Word Rx internal state.2 Reserved for CP use. The Rx internal data pointer 2 is updated by the SDMA channels to show the next address in the buffer to be accessed. 0x08 0x0C 0x10 Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be serviced when idle. After a reset or when the end of the BD table is reached, the CP initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but it can be updated when the receiver is disabled or when no Rx buffer is in use. Hword The Rx internal byte count 2 is a down-count value that is initialized with the MRBLR value and decremented with every byte the SDMA channels write. Word Word Word Rx temp.2 Reserved for CP use. Tx internal state.2 Reserved for CP use. The Tx internal data pointer2 is updated by the SDMA channels to show the next address in the buffer to be accessed. 0x12 0x14 0x18 0x1C 0x20 — — TSTATE — TBPTR Hword TxBD pointer. Points to the current Tx BD during frame transmission or the next BD to be processed when idle. After reset or when the end of the Tx BD table is reached, the CP initializes TBPTR to the TBASE value. Most applications do not need to modify TBPTR, but it can be updated when the transmitter is disabled or when no Tx buffer is in use. Hword The Tx internal byte count2 is a down-count value initialized with TxBD[Data Length] and decremented with every byte read by the SDMA channels. Word Word Tx temp.2 Reserved for CP use. SDMA temp. 0x22 0x24 0x34 1 2 — — — From the pointer value programmed in SPI_BASE at IMMR + 0x89FC. Normally, these parameters need not be accessed. They are listed to help experienced users in debugging. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-11 Serial Peripheral Interface (SPI) 39.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR) Figure 39-9 shows the fields in the receive/transmit function code registers (RFCR/TFCR). 0 1 2 3 4 5 6 7 Field Reset R/W Addr — GBL BO 0000_0000 R/W TC2 DTB — SPI Base + 04 (RFCR)/SPI Base + 05 (TFCR) Figure 39-9. RFCR/TFCR—Function Code Registers Table 39-6 describes the RFCR/TFCR fields. Table 39-6. RFCR/TFCR Field Descriptions Bits 0–1 2 Name — GBL Reserved, should be cleared. Global access bit 0 Disable memory snooping 1 Enable memory snooping Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-fly, it takes effect at the beginning of the next frame or BD. 00 True little-endian. Note this mode can only be used with 32-bit port size memory. 01 Munged little-endian 1x Big-endian Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Data bus indicator. 0 Use 60x bus for SDMA operation. 1 Use local bus for SDMA operation. Reserved, should be cleared. Description 3–4 BO 5 6 TC2 DTB 7 — 39.6 SPI Commands Table 39-7. SPI Commands Table 39-7 lists transmit/receive commands sent to the CP command register (CPCR). Command INIT TX PARAMETERS Description Initializes all transmit parameters in the parameter RAM to their reset state and should be issued only when the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters. Forces the SPI controller to close the current RxBD and use the next BD for subsequently received data. If the controller is not receiving data, no action is taken. Use this command to extract data from a partially full buffer. Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters. CLOSE RXBD INIT RX PARAMETERS MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-12 Freescale Semiconductor Serial Peripheral Interface (SPI) 39.7 The SPI Buffer Descriptor (BD) Table As shown in Figure 39-10, BDs are organized into separate RxBD and TxBD tables in dual-port RAM. The tables have the same basic configuration as for the SCCs and SMCs and form circular queues that determine the order buffers are transferred. The CP uses BDs to confirm reception and transmission or to indicate error conditions so that the core knows buffers have been serviced. The buffers themselves can be placed in external memory or in any unused parameter area of the dual-port RAM. Dual-Port RAM TxBD Table Tx Buffer Frame Status Data Length Buffer Pointer Tx Buffer External Memory Pointer to SPI TxBD Table Pointer to SPI RxBD Table RxBD Table Frame Status Data Length Buffer Pointer Rx Buffer Figure 39-10. SPI Memory Structure 39.7.1 SPI Buffer Descriptors (BDs) Receive and transmit BDs report information about each buffer transferred and whether a maskable interrupt should be generated. Each 64-bit BD, shown in Figure 39-11 and Figure 39-12, has the following structure: • The half word at offset + 0 contains status and control bits. The CP updates the status bits after the buffer is sent or received. • The half word at offset + 2 contains the data length (in bytes) that is sent or received. — For an RxBD, this is the number of octets the CP writes into this RxBD’s buffer once the BD closes. The CP updates this field after the received data is placed into the buffer. Memory allocated for this buffer should be no smaller than MRBLR. — For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this value should be greater than zero. If the character length is more than 8 bits, the data length should be even. For example, to send three characters of 8-bit data, 1 start, and 1 stop, the data length field should be initialized to 3. However, to send three characters of 9-bit data, the data length field should be initialized to 6 since the three 9-bit data fields occupy three half-words in memory. The CP never modifies this field. • The word at offset + 4 points to the beginning of the buffer. — For an RxBD, the pointer must be even and can point to internal or external memory. — For a TxBD, the pointer can be even or odd, unless the character exceeds 8 bits, for which it must be even. The buffer can be in internal or external memory. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-13 Serial Peripheral Interface (SPI) 39.7.1.1 SPI Receive BD (RxBD) The CP uses RxBDs to report on each received buffer. It closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer once the current buffer is full. The CP also closes the buffer when the SPI is configured as a slave and SPISEL is negated, indicating that reception stopped. The core should write RxBD bits before the SPI is enabled. The format of an RxBD is shown in Figure 39-11. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I L — CM Data Length Rx Buffer Pointer — OV ME Figure 39-11. SPI RxBD Table 39-8 describes the RxBD status and control fields. Table 39-8. SPI RxBD Status and Control Field Descriptions Bits 0 Name E Description Empty. 0 The buffer is full or stopped receiving because of an error. The core can examine or write to any fields of this RxBD, but the CP does not use this BD while E = 0. 1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. Reserved, should be cleared. Wrap (last BD in table). 0 Not the last BD in the RxBD table. 1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is filled. 1 SPIE[RXB] is set when this buffer is full, indicating the need for the core to process the buffer. SPIE[RXB] causes an interrupt if not masked. Last. Updated by the SPI when the buffer is closed because SPISEL was negated (slave mode only). Otherwise, RxBD[ME] is set. The SPI updates L after received data is placed in the buffer. 0 This buffer does not contain the last character of the message. 1 This buffer contains the last character of the message. Reserved, should be cleared. Continuous mode. Master mode only; in slave mode, CM should be cleared. 0 Normal operation. 1 The CP does not clear RxBD[E] after this BD is closed; the buffer is overwritten when the CP next accesses this BD. This allows continuous reception from an SPI slave into one buffer for autoscanning of a serial A/D peripheral with no core overhead. Reserved, should be cleared. 1 2 — W 3 I 4 L 5 6 — CM 7–13 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-14 Freescale Semiconductor Serial Peripheral Interface (SPI) Table 39-8. SPI RxBD Status and Control Field Descriptions (continued) Bits 14 15 Name OV ME Description Overrun. Set when a receiver overrun occurs during reception (slave mode only). The SPI updates OV after the received data is placed in the buffer. Multimaster error. Set when this buffer is closed because SPISEL was asserted when the SPI was in master mode. Indicates a synchronization problem between multiple masters on the SPI bus. The SPI updates ME after the received data is placed in the buffer. 39.7.1.2 SPI Transmit BD (TxBD) Data to be sent with the SPI is sent to the CP by arranging it in buffers referenced by TxBDs in the TxBD table. TxBD fields should be prepared before data is sent. The format of an TxBD is shown in Figure 39-12. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R — W I L — CM Data Length Tx Buffer Pointer — UN ME Figure 39-12. SPI TxBD Table 39-9 describes the TxBD status and control fields. Table 39-9. SPI TxBD Status and Control Field Descriptions Bits 0 Name R Description Ready. 0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R (unless RxBD[CM] is set) after the buffer is sent (unless RxBD[CM] is set) or an error occurs. 1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set. Reserved, should be cleared. Wrap (last BD in TxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data using the BD pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is processed; SPIE[TXE] is unaffected. 1 SPIE[TXB] or SPIE[TXE] are set when this buffer is processed and causes interrupts if not masked. Last. 0 This buffer does not contain the last character of the message. 1 This buffer contains the last character of the message. Reserved, should be cleared. 1 2 — W 3 I 4 L 5 — MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-15 Serial Peripheral Interface (SPI) Table 39-9. SPI TxBD Status and Control Field Descriptions (continued) Bits 6 Name CM Description Continuous mode. Valid only when the SPI is in master mode. In slave mode, it should be cleared. 0 Normal operation. 1 The CP does not clear TxBD[R] after this BD is closed, allowing the buffer to be resent automatically when the CP next accesses this BD. Reserved, should be cleared. Underrun. Indicates that the SPI encountered a transmitter underrun condition while sending the buffer. This error occurs only when the SPI is in slave mode. The SPI updates UN after it sends the buffer. Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI was in master mode. A synchronization problem occurred between devices on the SPI bus. The SPI updates ME after sending the buffer. 7–13 14 — UN 15 ME 39.8 SPI Master Programming Example The following sequence initializes the SPI to run at a high speed in master mode: 1. Configure port D to enable SPIMISO, SPIMOSI, SPICLK and SPISEL. 2. Configure a parallel I/O signal to operate as the SPI select output signal if needed. 3. In address 0x89FC, assign a pointer to the SPI parameter RAM. 4. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and TxBD tables in the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of the dual-port RAM, write RBASE with 0x0000 and TBASE with 0x0008. 5. Write RFCR and TFCR with 0x10 for normal operation. 6. Write MRBLR with the maximum number of bytes per Rx buffer. For this case, assume 16 bytes, so MRBLR = 0x0010. 7. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR. 10. Write 0xFF to SPIE to clear any previous events. 11. Write 0x37 to SPIM to enable all possible SPI interrupts. 12. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode, SPI enabled, 8-bit characters, and the fastest speed possible. 13. Set SPCOM[STR] to start the transfer. After 5 bytes are sent, the TxBD is closed. Additionally, the Rx buffer is closed after 5 bytes are received because TxBD[L] is set. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-16 Freescale Semiconductor Serial Peripheral Interface (SPI) 39.9 SPI Slave Programming Example The following is an example initialization sequence to follow when the SPI is in slave mode. It is very similar to the SPI master example, except that SPISEL is used instead of a general-purpose I/O signal (as shown in Figure 39-2). 1. Enable SPIMISO, SPIMOSI, SPICLK, and SPISEL. 2. In address 0x89FC, assign a pointer to the SPI parameter RAM. 3. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008 in the SPI parameter RAM. 4. Write RFCR and TFCR with 0x10 for normal operation. 5. Program MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer. 6. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. 7. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer]. 8. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR. 9. Write 0xFF to SPIE to clear any previous events. 10. Write 0x37 to SPIM to enable all SPI interrupts. 11. Set SPMODE to 0x0170 to enable normal operation (not loopback), slave mode, SPI enabled, and 8-bit characters. BRG speed is ignored in slave mode. 12. Set SPCOM[STR] to enable the SPI to be ready once the master begins the transfer. NOTE If the master sends 3 bytes and negates SPISEL, the RxBD is closed but the TxBD remains open. If the master sends 5 or more bytes, the TxBD is closed after the fifth byte. If the master sends 16 bytes and negates SPISEL, the RxBD is closed without triggering an out-of-buffers error. If the master sends more than 16 bytes, the RxBD is closed (full) and an out-of-buffers error occurs after the 17th byte is received. 39.10 Handling Interrupts in the SPI The following sequence should be followed to handle interrupts in the SPI: 1. Once an interrupt occurs, read SPIE to determine the interrupt source. Normally, SPIE bits should be cleared at this time. 2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR]. 3. Execute an rfi instruction. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 39-17 Serial Peripheral Interface (SPI) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 39-18 Freescale Semiconductor Chapter 40 I2C Controller The inter-integrated circuit (I2C®) controller lets the MPC8280 exchange data with other I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. It uses two signals—serial data (SDA) and serial clock (SCL)—to carry information between the integrated circuits connected to it. As shown in Figure 40-1, the I2C controller consists of transmit and receive sections, an independent baud-rate generator (BRG), and a control unit. The transmit and receive sections use the same clock, which is derived from the I2C BRG when in master mode and generated externally when in slave mode. Wait states are inserted during a data transfer if SCL is held low by a slave device. In the middle of a data transfer, the master I2C controller recognizes the need for wait states by monitoring SCL. However, the I2C controller has no automatic time-out mechanism if the slave device does not release SCL; therefore, software should monitor how long SCL stays low to generate bus timeouts. Peripheral Bus 60x Bus Rx Data Register Tx Data Register Mode Register Shift Register Shift Register SDA Control Baud-Rate Generator SCL Figure 40-1. I2C Controller Block Diagram The I2C receiver and transmitter are double-buffered, which corresponds to an effective two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out first. When the I2C is not enabled in the I2C mode register (I2MOD[EN] = 0), it consumes little power. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-1 I2C Controller 40.1 Features The following is a list of the I2C controller’s main features: • Two-signal interface (SDA and SCL) • Support for master and slave I2C operation • Multiple-master environment support • Continuous transfer mode for automatic scanning of a peripheral • Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%), assuming a 100-MHz system clock. • Independent, programmable baud-rate generator • Supports 7-bit I2C addressing • Open-drain output signals allow multiple master configuration • Local loopback capability for testing 40.2 I2C Controller Clocking and Signal Functions The I2C controller can be configured as a master or slave for the serial channel. As a master, the controller’s BRG provides the transfer clock. The I2C BRG takes its input from the BRG clock (BRGCLK), which is generated from the CPM clock; see Section 10.4, “System Clock Control Register (SCCR).” SDA and SCL are bidirectional signals connected to a positive supply voltage through an external pull-up resistor. When the bus is free, both signals are pulled high. The general I2C master/slave configuration is shown in Figure 40-2. VDD Master SCL SDA SCL SDA Slave (EEPROM, for example) VDD Figure 40-2. I2C Master/Slave General Configuration When the I2C controller is master, the SCL clock output, taken directly from the I2C BRG, shifts receive data in and transmit data out through SDA. The transmitter arbitrates for the bus during transmission and aborts if it loses arbitration. When the I2C controller is a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can range from DC to BRGCLK/48. 40.3 I2C Controller Transfers To initiate a transfer, the master I2C controller sends a message specifying a read or write request to an I2C slave. The first byte of the message consists of a 7-bit slave port address and a R/W request bit. Note that MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-2 Freescale Semiconductor I2C Controller because the R/W request follows the slave port address in the I2C bus specification, the R/W request bit must be placed in the lsb (bit 7) unless operating in reverse data mode; see Section 40.4.1, “I2C Mode Register (I2MOD).” To write to a slave, the master sends a write request (R/W = 0) along with either the target slave’s address or a general call (broadcast) address of all zeros, followed by the data to be written. To read from a slave, the master sends a read request (R/W = 1) and the target slave’s address. When the target slave acknowledges the read request, the transfer direction is reversed, and the master receives the slave’s transmit buffer(s). If the receiver (master or slave) does not acknowledge each byte transfer in the ninth bit frame, the transmitter signals a transmission error event (I2ER[TXE]). An I2C transfer timing diagram is shown in Figure 40-3. Start Condition SCL 123 456 789 A C K Stop Condition SDA Data Byte Figure 40-3. I2C Transfer Timing Select master or slave mode for the controller using the I2C command register (I2COM[M/S]). Set the master’s start bit, I2COM[STR], to begin a transfer; setting a slave’s I2COM[STR] activates the slave to wait for a transfer request from a master. If a master or slave transmitter’s current TxBD[L] is set, transmission stops once the buffer is sent; that is, I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero, once the current buffer is sent, the controller begins processing the next TxBD without waiting for I2COM[STR] to be set again. The following sections further detail the transfer process. 40.3.1 I2C Master Write (Slave Read) If the MPC8280 is the master, prepare the transmit buffers and BDs before initiating a write. Initialize the first transmit data byte with the slave address and write request (R/W = 0). If the MPC8280 is the slave target of the write, prepare receive buffers and BDs to await the master’s request. Figure 40-4 shows the timing for a master write. S T A R T SDA Device Address S T AO CP K A C WK Data Byte Note: Data and ACK are repeated n times. Figure 40-4. I2C Master Write Timing MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-3 I2C Controller A master write occurs as follows: 1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel loads the Tx FIFO with data and the I2C bus is not busy. 2. The I2C master generates a start condition—a high-to-low transition on SDA while SCL is high—and the transfer clock SCL pulses for each bit shifted out on SDA. If the master transmitter detects a multiple-master collision (by sensing a ‘0’ on SDA while sending a ‘1’), transmission stops and the channel reverts to slave mode. A maskable interrupt is sent to the master’s core so software can try to retransmit later. 3. The slave acknowledges each byte and writes to its current receive buffer until a new start or stop condition is detected. 4. After sending each byte, the master monitors the acknowledge indication. If the slave receiver fails to acknowledge a byte, transmission stops and the master generates a stop condition—a low-to-high transition on SDA while SCL is high. 40.3.2 I2C Loopback Testing When in master mode, an I2C controller supports loopback operation for master write requests. The master I2C controller simply issues a write request directed to its own address (programmed in I2ADD). The master’s receiver monitors the transmission and reads the transmitted data into its receive buffer. Loopback operation requires no special register programming. 40.3.3 I2C Master Read (Slave Write) Before initiating a master read with the MPC8280, prepare a transmit buffer of size n+1 bytes, where n is the number of bytes to be read from the slave. The first transmit byte should be initialized to the slave address with R/W = 1. The next n transmit bytes are used strictly for timing and can be left uninitialized. Configure suitable receive buffers and BDs to receive the slave’s transmission. If the MPC8280 is the slave target of the read, prepare the I2C transmit buffers and BDs and activate it by setting I2COM[STR]. Figure 40-5 shows the timing for a master read. S T A R T SDA Device Address N O A C RK S AT CO KP Data Byte Note: After the nth data byte, the master does not acknowledge the slave. Figure 40-5. I2C Master Read Timing A master read occurs as follows: 1. Set the master’s I2COM[STR] to initiate the read. The transfer starts when the SDMA channel loads the transmit FIFO with data and the I2C bus is not busy. 2. The slave detects a start condition on SDA and SCL. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-4 Freescale Semiconductor I2C Controller 3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave is an MPC8280, the address is programmed in its I2C address register (I2ADD). — If a match is found, the slave acknowledges the received byte and begins transmitting on the clock pulse immediately following the acknowledge. — If a match is found but the slave is not ready, the read request is not acknowledged and the transaction is aborted. If the slave is an MPC8280, a maskable transmission error interrupt is triggered to allow software to prepare data for transmission on the next try. — If a mismatch occurs, the slave ignores the message and searches for a new start condition. 4. The master acknowledges each byte sent as long as an overrun does not occur. If the master receiver fails to acknowledge a byte, the slave aborts transmission. For a slave MPC8280, the abort generates a maskable interrupt. A maskable interrupt is also issued after a complete buffer is sent or after an error. If an underrun occurs, the MPC8280 slave sends ones until a stop condition is detected. 40.3.4 I2C Multi-Master Considerations The I2C controller supports a multi-master configuration, in which the I2C controller must alternate between master and slave modes. The I2C controller supports this by implementing I2C master arbitration in hardware. However, due to the nature of the I2C bus and the implementation of the I2C controller, certain software considerations must be made. An MPC8280 I2C controller attempting a master read request could simultaneously be targeted for an external master write (slave read). Both operations trigger the controller’s I2CER[RXB] event, but only one operation wins the bus arbitration. To determine which operation caused the interrupt, software must verify that its transmit operation actually completed before assuming that the received data is the result of its read operation. Problems could also arise if the MPC8280's I2C controller master sets up a transmit buffer and BD for a write request, but then is the target of a read request from another master. Without software precautions, the I2C controller responds to the other master with the transmit buffer originally intended for its own write request. To avoid this situation, a higher-level handshake protocol must be used. For example, a master, before reading a slave, writes the slave with a description of the requested data (which register should be read, for example). This operation is typical with many I2C devices. In addition, it is not recommended to enable the MPC8280’s I2C controller while another I2C master is executing transactions on the bus. The MPC8280’s I2C controller should wait for the bus to become idle. The MPC8280’s I2C controller assumes that other I2C devices on the bus closely conform to the I2C specification. Unexpected behavior can occur if the MPC8280 I2C controller is connected with devices which operate outside the specification. For example, a slave device which acknowledges a master write with two SCL pulses instead of one (total of 10 SCL pulses), can cause wrong behavior of the PowerQUICC I2C controller on its next transaction. 40.4 I2C Registers The following sections describe the I2C registers. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-5 I2C Controller 40.4.1 I2C Mode Register (I2MOD) The I2C mode register, shown in Figure 40-6, controls the I2C modes and clock source. 0 1 2 3 4 5 6 7 Field Reset R/W Addr — REVD GCD FLT PDIV EN 0000_0000 R/W 0x11860 Figure 40-6. I2C Mode Register (I2MOD) Table 40-1 describes I2MOD bit functions. Table 40-1. II2MOD Field Descriptions Bits 0–1 2 Name — Reserved and should be cleared. Description REVD Reverse data. Determines the Rx and Tx character bit order. 0 Normal operation. The msb (bit 0) of a character is transferred first. 1 Reverse data. the lsb (bit 7) of a character is transferred first. Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices. GCD General call disable. Determines whether the receiver acknowledges a general call address. 0 General call address is enabled. 1 General call address is disabled. Clock filter. Determines if the I2C input clock SCL is filtered to prevent spikes in a noisy environment. 0 SCL is not filtered. 1 SCL is filtered by a digital filter. Predivider. Selects the clock division factor before it is input into the I2C BRG. The clock source for the I2C BRG is the BRGCLK generated from the CPM clock; see Section 10.4, “System Clock Control Register (SCCR).” 00 BRGCLK/32 01 BRGCLK/16 10 BRGCLK/8 11 BRGCLK/4 Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division factor (slowest clock) that still meets performance requirements. Enable I2C operation. 0 I2C is disabled. The I2C is in a reset state and consumes minimal power. 1 I2C is enabled. Do not change other I2MOD bits when EN is set. 3 4 FLT 5–6 PDIV 7 EN MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-6 Freescale Semiconductor I2C Controller 40.4.2 I2C Address Register (I2ADD) The I2C address register, shown in Figure 40-7, holds the address for this I2C port. 0 6 7 Field Reset R/W Addr SAD Undefined R/W 0x11864 — Figure 40-7. I2C Address Register (I2ADD) Table 40-2 describes I2ADD fields. Table 40-2. I2ADD Field Descriptions Bits 0–6 7 Name SAD — Description Slave address 0–6. Holds the slave address for the I2C port. Reserved and should be cleared. 40.4.3 I2C Baud Rate Generator Register (I2BRG) The I2C baud rate generator register, shown in Figure 40-8, sets the divide ratio of the I2C BRG. 0 7 Field Reset R/W Addr 2 DIV 1111_1111 R/W 0x11868 Figure 40-8. I C Baud Rate Generator Register (I2BRG) Table 40-3 describes I2BRG fields. Table 40-3. I2BRG Field Descriptions Bits 0–7 Name DIV Description Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I2C clock generator. The output of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled (I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1) . 40.4.4 I2C Event/Mask Registers (I2CER/I2CMR) The I2C event register (I2CER) is used to generate interrupts and report events. When an event is recognized, the I2C controller sets the corresponding I2CER bit. I2CER bits are cleared by writing ones; writing zeros has no effect. Setting a bit in the I2C mask register (I2CMR) enables and clearing a bit masks MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-7 I2C Controller the corresponding interrupt. Unmasked I2CER bits must be cleared before the CP clears internal interrupt requests. Figure 40-9 shows both registers. 0 2 3 4 5 6 7 Field Reset R/W Addr — TXE 0000_0000 R/W — BSY TXB RXB 0x11870(I2CER)/0x11874 I2CMR) Figure 40-9. I C Event/Mask Registers (I2CER/I2CMR) 2 Table 40-4 describes the I2CER/I2CMR fields. Table 40-4. I2CER/I2CMR Field Descriptions Bits 0–2 3 4 5 6 7 Name — TXE — BSY TXB RXB Reserved and should be cleared. Tx error. Set when an error occurs during transmission. This event is not maskable via the TxBD[I] bit. Reserved and should be cleared. Busy. Set after the first character is received but discarded because no Rx buffer is available. Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two character times must elapse to guarantee that all data has been sent. Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed. Description 40.4.5 I2C Command Register (I2COM) The I2C command register, shown in Figure 40-10, is used to start I2C transfers and to select master or slave mode. 0 1 2 3 4 5 6 7 Field Reset R/W Addr STR — 0000_0000 R/W 0x1186C M/S Figure 40-10. I2C Command Register (I2COM) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-8 Freescale Semiconductor I2C Controller Table 40-5 describes I2COM fields. Table 40-5. I2COM Field Descriptions Bits 0 Name STR Description Start transmit. In master mode, setting STR causes the I2C controller to start sending data from the I2C Tx buffers if they are ready. In slave mode, setting STR when the I2C controller is idle causes it to load the Tx data register from the I2C Tx buffer and start sending when it receives an address byte that matches the slave address with R/W = 1. STR is always read as a 0. Reserved and should be cleared. Master/slave. Configures the I2C controller to operate as a master or a slave. 0 I2C is a slave. 1 I2C is a master. 1–6 7 — M/S 40.5 I2C Parameter RAM The I2C controller parameter table is used for the general I2C parameters and is similar to the SCC general-purpose parameter RAM. The CP accesses the I2C parameter table using a user-programmed pointer (I2C_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” The I2C parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). The user must initialize certain parameter RAM values before the I2C is enabled; the CP initializes the other values. Software usually does not access parameter RAM entries once they are initialized; they should be changed only when the I2C is inactive. Table 40-6 shows the I2C parameter memory map. Table 40-6. I2C Parameter RAM Memory Map Offset 1 0x00 0x02 Name RBASE TBASE Width Description Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM. Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are Hword allocated for the Tx and Rx sections of the I2C. Initialize RBASE/TBASE before enabling the I2C. Furthermore, do not configure BD tables of the I2C to overlap any other active controller’s parameter RAM. RBASE and TBASE should be divisible by eight. Byte Byte Rx/Tx function code registers. The function code registers contain the transaction specification associated with SDMA channel accesses to external memory. See Figure 40-11 and Table 40-7. 0x04 0x05 0x06 RFCR TFCR MRBLR Hword Maximum receive buffer length. Defines the maximum number of bytes the MPC8280 writes to a Rx buffer before moving to the next buffer. The MPC8280 writes fewer bytes to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should not be smaller than MRBLR. Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be sent is specified in TxBD[Data Length]. MRBLR is not intended to be changed while the I2C is operating. However it can be changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). The change takes effect when the CP moves control to the next RxBD. To guarantee the exact RxBD on which the change occurs, change MRBLR only while the I2C receiver is disabled. MRBLR should be greater than zero; it should be an even number if the character length of the data exceeds 8 bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-9 I2C Controller Table 40-6. I2C Parameter RAM Memory Map (continued) Offset 1 0x08 0x0C 0x10 Name RSTATE RPTR RBPTR Width Description Word Rx internal state.2 Reserved for CP use. Word Rx internal data pointer2 is updated by the SDMA channels to show the next address in the buffer to be accessed. Hword RxBD pointer. Points to the next descriptor the receiver transfers data to when it is in an idle state or to the current descriptor during frame processing for each I2C channel. After a reset or when the end of the descriptor table is reached, the CP initializes RBPTR to the value in RBASE. Most applications should not write RBPTR, but it can be modified when the receiver is disabled or when no receive buffer is used. Hword Rx internal byte count 2 is a down-count value that is initialized with the MRBLR value and decremented with every byte the SDMA channels write. Word Rx temp.2 Reserved for CP use. Word Tx internal state.2 Reserved for CP use. Word Tx internal data pointer 2 is updated by the SDMA channels to show the next address in the buffer to be accessed. Hword TxBD pointer. Points to the next descriptor that the transmitter transfers data from when it is in an idle state or to the current descriptor during frame transmission. After a reset or when the end of the descriptor table is reached, the CP initializes TBPTR to the value in TBASE.Most applications should not write TBPTR, but it can be modified when the transmitter is disabled or when no transmit buffer is used. Hword Tx internal byte count 2 is a down-count value initialized with TxBD[Data Length] and decremented with every byte read by the SDMA channels. Word Tx temp.2 Reserved for CP use. 0x12 0x14 0x18 0x1C 0x20 RCOUNT RTEMP TSTATE TPTR TBPTR 0x22 0x24 0x34 1 2 TCOUNT TTEMP SDMATMP Word SDMA temp.2 Reserved for CP use. From the pointer value programmed in I2C_BASE at IMMR + 0x8AFC. Normally, these parameters need not be accessed. Figure 40-11 shows the RFCR/TFCR bit fields. 0 1 2 3 4 5 6 7 Field Reset R/W Addr GBL BO 0000_0000 R/W TC2 DTB — I2C_BASE + 04 (RFCR)/I2C_BASE + 05 (TFCR) Figure 40-11. I2C Function Code Registers (RFCR/TFCR) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-10 Freescale Semiconductor I2C Controller Table 40-7 describes the RFCR/TFCR bit fields. Table 40-7. RFCR/TFCR Field Descriptions Bits 0–1 2 Name — GBL Reserved, should be cleared. Global access bit 0 Disable memory snooping 0 Enable memory snooping Byte ordering. Selects the required byte ordering for the buffer. If BO is changed on-the-fly, it takes effect at the beginning of the next frame or BD. 00 True little-endian. Note this mode can only be used with 32-bit port size memory. 01 Big-endian 1x Munged little-endian Transfer code 2. Contains the transfer code value of TC[2], used during this SDMA channel memory access. TC[0–1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access. Data bus indicator. 0 Use 60x bus for SDMA operation. 1 Use local bus for SDMA operation. Reserved, should be cleared. Description 3–4 BO 5 6 TC2 DTB 7 — 40.6 I2C Commands The I2C transmit and receive commands, shown in Table 40-8, are issued to the CP command register (CPCR). Table 40-8. I2C Transmit/Receive Commands Command INIT TX PARAMETERS Description Initializes all transmit parameters in the parameter RAM to their reset state. Should be issued only when the transmitter is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters. Forces the I2C controller to close the current Rx BD and use the next BD for subsequently received data. If the controller is not receiving data, no action is taken. Use this command to extract data from a partially full buffer. Initializes all receive parameters in the parameter RAM to their reset state. Should be issued only when the receiver is disabled. The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters. CLOSE RXBD INIT RX PARAMETERS 40.7 The I2C Buffer Descriptor (BD) Table As shown in Figure 40-12, buffer descriptors (BDs) are organized into separate RxBD and TxBD tables in dual-port RAM. The tables have the same basic configuration as for the SCCs and SMCs and form circular queues that determine the order buffers are transferred. The CP uses BDs to confirm reception and transmission or to indicate error conditions so that the core knows buffers have been serviced. The buffers themselves can be placed in external memory or in any unused parameter area of the dual-port RAM. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-11 I2C Controller Dual-Port RAM TxBD Table Tx Buffer Status and Control Data Length I2C TxBD Table Buffer Pointer External Memory Tx Buffer I2C RxBD Table RxBD Table Status and Control Rx Buffer I2C RxBD Table Pointer (RBASE) I2C TxBD Table Pointer (TBASE) Data Length Buffer Pointer Figure 40-12. I2C Memory Structure 40.7.1 I2C Buffer Descriptors (BDs) Receive and transmit buffer descriptors report information about each buffer transferred and whether a maskable interrupt should be generated. Each 64-bit BD, shown in Figure 40-13 and Figure 40-14, has the following structure: • The half word at offset + 0 contains status and control bits. The CP updates the status bits after the buffer is sent or received. • The half word at offset + 2 contains the data length (in bytes) that is sent or received. — For an RxBD, this is the number of octets the CP writes into this RxBD’s buffer once the descriptor closes. The CP updates this field after the received data is placed into the associated buffer. Memory allocated for this buffer should be no smaller than MRBLR. — For a TxBD, this is the number of octets the CP should transmit from its buffer. Normally, this value should be greater than zero. The CP never modifies this field. • The word at offset + 4 points to the beginning of the buffer. — For an RxBD, the pointer must be even and can point to internal or external memory. — For a TxBD, the pointer can be even or odd. The buffer can reside in internal or external memory. 40.7.1.1 I2C Receive Buffer Descriptor (RxBD) Using RxBDs, the CP reports on each buffer received, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current one is full. It closes the buffer when a stop or start condition is found on the I2C bus or when an overrun error occurs. The core should write RxBD bits before the I2C controller is enabled. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-12 Freescale Semiconductor I2C Controller 0 1 2 3 4 5 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 E — W I L Data Length — OV — RX Buffer Pointer Figure 40-13. I2C RxBD Table 40-9 describes I2C RxBD status and control bits. Table 40-9. I2C RxBD Status and Control Bits Bits 0 Name E Description Empty. 0 The buffer is full or stopped receiving because of an error. The core can examine or write to any fields of this RxBD, but the CP does not use this BD while E = 0. 1 The buffer is empty or reception is in progress. The CP owns this RxBD and its buffer. Once E is set, the core should not write any fields of this RxBD. Reserved and should be cleared. Wrap (last BD in table). 0 Not the last BD in the RxBD table. 1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data using the BD pointed to by RBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is full. 1 The I2CER[RXB] is set when the CP fills this buffer, indicating that the core needs to process the buffer. The RXB bit can cause an interrupt if it is enabled. Last. The I2C controller sets L. 0 This buffer does not contain the last character of the message. 1 This buffer holds the last character of the message. The I2C controller sets L after all received data is placed into the associated buffer, or because of a stop or start condition or an overrun. Reserved and should be cleared. Overrun. Set when a receiver overrun occurs during reception. The I2C controller updates this bit after the received data is placed into the associated buffer. Reserved and should be cleared. 1 2 — W 3 I 4 L 5–13 14 15 — OV — 40.7.1.2 I2C Transmit Buffer Descriptor (TxBD) Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The first word of the TxBD, shown in Figure 40-14, contains status and control bits. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 40-13 I2C Controller 0 1 2 3 4 5 6 12 13 14 15 Offset + 0 Offset + 2 Offset + 4 Offset + 6 R — W I L S Data Length — NAK UN CL Tx Buffer Pointer Figure 40-14. I2C TxBD Table 40-10 describes I2C TxBD status and control bits. Table 40-10. I2C TxBD Status and Control Bits Bits 0 Name R Description Ready. 0 The buffer is not ready to be sent. This BD or its buffer can be modified. The CP clears R after the buffer is sent or an error occurs. 1 The buffer is ready for transmission or is being sent. The BD cannot be modified once R is set. Reserved and should be cleared. Wrap (last BD in TxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP transmits data using the BD pointed to by TBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall space constraints of the dual-port RAM. Interrupt. 0 No interrupt is generated after this buffer is serviced; I2CER[TXE] is unaffected. 1 I2CER[TXB] or I2CER[TXE] is set when the buffer is serviced. If enabled, an interrupt occurs. Last. 0 This buffer does not contain the last character of the message. 1 This buffer contains the last character of the message. The I2C controller generates a stop condition after sending this buffer. Generate start condition. Provides ability to send back-to-back frames with one I2COM[STR] trigger. 0 Do not send a start condition before the first byte of the buffer. 1 Send a start condition before the first byte of the buffer. (Used to separate frames.) Note: If this BD is the first one in the frame when I2COM[STR] is triggered, a start condition is sent regardless of the value of TxBD[S]. Reserved and should be cleared. No acknowledge. Indicates that the transmission was aborted because the last byte sent was not acknowledged. The I2C controller updates NAK after the buffer is sent. Underrun. Indicates that the I2C controller encountered a transmitter underrun condition while sending the associated buffer. The I2C controller updates UN after the buffer is sent. Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for the bus. The I2C controller updates CL after the buffer is sent. 1 2 — W 3 I 4 L 5 S 6–12 13 14 15 — NAK UN CL MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 40-14 Freescale Semiconductor Chapter 41 Parallel I/O Ports The CPM supports four general-purpose I/O ports—ports A, B, C, and D. Each pin in the I/O ports can be configured as a general-purpose I/O signal or as a dedicated peripheral interface signal. Port C is unique in that 16 of its pins can generate interrupts to the interrupt controller. Each pin can be configured as an input or output and has a latch for data output, read or written at any time, and configured as general-purpose I/O or a dedicated peripheral pin. Part of the pins can be configured as open-drain (the pin can be configured in a wired-OR configuration on the board). The pin drives a zero voltage but three-states when driving a high voltage. Note that port pins do not have internal pull-up resistors. Due to the CPM’s significant flexibility, many dedicated peripheral functions are multiplexed onto the ports. The functions are grouped to maximize the pins’ usefulness in the greatest number of MPC8280 applications. The reader may not obtain a full understanding of the pin assignment capability described in this chapter without understanding the CPM peripherals. 41.1 Features The following is a list of the parallel I/O ports’ important features: • Port A is 32 bits • Port B is 28 bits • Port C is 32 bits • Port D is 28 bits • All ports are bidirectional • All ports have alternate on-chip peripheral functions • All ports are three-stated at system reset • All pin values can be read while the pin is connected to an on-chip peripheral • Open-drain capability on some pins • Port C offers 16 interrupt input pins 41.2 Port Registers Each port has four memory-mapped, read/write, 32-bit control registers. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-1 Parallel I/O Ports 41.2.1 Port Open-Drain Registers (PODRA–PODRD) The port open-drain register (PODR), shown in Figure 41-1, indicates a normal or wired-OR configuration of the port pins. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr OD01 OD11 OD21 OD31 OD4 OD5 OD6 OD7 OD8 OD9 OD10 OD11 OD12 OD13 OD14 OD15 0000_0000_0000_0000 R/W 0x10D0C (PODRA), 0x10D2C (PODRB), 0x10D4C (PODRC), 0x10D6C (PODRD) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field OD16 OD17 OD18 OD19 OD20 OD21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31 Reset R/W Addr 1 These 0000_0000_0000_0000 R/W 0x10D0E (PODRA), 0x10D2E (PODRB), 0x10D4E (PODRC), 0x10D6E (PODRD) bits are valid for PODRA and PODRC only Figure 41-1. Port Open-Drain Registers (PODRA–PODRD) Table 41-1 describes PODR fields. Table 41-1. PODRx Field Descriptions Bits 0–31 Name ODx Description Open-drain configuration. Determines whether the corresponding pin is actively driven as an output or is an open-drain driver. Note that bits OD0–OD3 are valid for PODRA and PODRC only. 0 The I/O pin is actively driven as an output. 1 The I/O pin is an open-drain driver. As an output, the pin is driven active-low, otherwise it is three-stated. 41.2.2 Port Data Registers (PDATA–PDATD) A read of a port data register (PDATx), shown in Figure 41-2, returns the data at the pin, independent of whether the pin is defined as an input or output. This allows detection of output conflicts at the pin by comparing the written data with the data on the pin. A write to the PDATx is latched and if the equivalent PDIR bit is configured as an output, the value latched for that bit is driven onto its respective pin. PDATx can be read or written at any time and is not initialized. If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin is configured as an output, the output latch data is gated onto the port pin. In this case, when PDATx is read, the port pin itself is read. If a port pin is configured as an input, data written to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-2 Freescale Semiconductor Parallel I/O Ports 0 1 1 2 1 3 1 4 1 5 6 7 8 9 10 11 12 13 14 15 Field D0 Reset R/W Addr D1 D2 D3 D4 D5 D6 D7 — D8 D9 D10 D11 D12 D13 D14 D15 R/W 0x10D10 (PDATA), 0x10D30 (PDATB), 0x10D50 (PDATC), 0x10D70 (PDATD) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field D16 Reset R/W Addr 1 These D17 D18 D19 D20 D21 D22 D23 — D24 D25 D26 D27 D28 D29 D30 D31 R/W 0x10D12 (PDATA), 0x10D32 (PDATB), 0x10D52 (PDATC), 0x10D72 (PDATD) bits are valid for PDATA and PDATC only Figure 41-2. Port Data Registers (PDATA–PDATD) 41.2.3 Port Data Direction Registers (PDIRA–PDIRD) The port data direction register(PDIR), shown in Figure 41-3, is cleared at system reset. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Reset R/W Addr DR01 DR11 DR21 DR31 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 0000_0000_0000_0000 R/W 0x10D00 (PDIRA), 0x10D20 (PDIRB), 0x10D40 (PDIRC), 0x10D60 (PDIRD) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field DR16 DR17 DR18 DR19 DR20 DR21 DR22 DR23 DR24 DR25 DR26 DR27 DR28 DR29 DR30 DR31 Reset R/W Addr 1 These 0000_0000_0000_0000 R/W 0x10D02 (PDIRA), 0x10D22 (PDIRB), 0x10D42 (PDIRC), 0x10D62 (PDIRD) bits are valid for PDIRA and PDIRC only Figure 41-3. Port Data Direction Register (PDIR) Table 41-2 describes PDIR fields. Table 41-2. PDIR Field Descriptions Bits 0–31 Name DRx Description Direction. Indicates whether a pin is used as an input or an output. Note that bits DR0–DR3 are valid for PDIRA and PDIRC only. 0 The corresponding pin is an input or is bidirectional. 1 The corresponding pin is an output. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-3 Parallel I/O Ports 41.2.4 Port Pin Assignment Register (PPAR) The port pin assignment register (PPAR) is cleared at system reset. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DD01 DD11 DD21 DD31 DD4 Reset R/W Addr 16 17 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 0000_0000_0000_0000 R/W 0x10D04 (PPARA), 0x10D24 (PPARB), 0x10D44 (PPARC), 0x10D64 (PPARD) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 Reset R/W Addr 1 These 0000_0000_0000_0000 R/W 0x10D06 (PPARA), 0x10D26 (PPARB), 0x10D46 (PPARC), 0x10D66 (PPARD) bits are valid for PPARA and PPARC only Figure 41-4. Port Pin Assignment Register (PPARA–PPARD) Table 41-2 describes PPARx fields. Table 41-3. PPAR Field Descriptions Bits 0–31 Name DDx Description Dedicated enable. Indicates whether a pin is a general-purpose I/O or a dedicated peripheral pin. Note: Bits DD0–DD3 are valid for PPARA and PPARC only. 0 General-purpose I/O. The peripheral functions of the pin are not used. 1 Dedicated peripheral function. The pin is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits such as those is the PDIR. 41.2.5 Port Special Options Registers A–D (PSORA–PSORD) Figure 41-5 shows the port special options registers (PSORx). MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-4 Freescale Semiconductor Parallel I/O Ports 0 1 1 2 1 3 1 4 1 5 6 7 8 9 10 11 12 13 14 15 Field SO0 Reset R/W Addr 16 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SO8 SO9 SO10 SO11 SO12 SO13 SO14 SO15 0000_0000_0000_0000 R/W 0x10D08 (PSORA), 0x10D28 (PSORB), 0x10D48 (PSORC), 0x10D68 (PSORD) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field SO16 SO17 SO18 SO19 SO20 SO21 SO22 SO23 SO24 SO25 SO26 SO27 SO28 SO29 SO30 SO31 Reset R/W Addr 1 These 0000_0000_0000_0000 R/W 0x10D0A (PSORA), 0x10D2A (PSORB), 0x10D4A (PSORC), 0x10D6A (PSORD) bits are valid for PSORA and PSORC only Figure 41-5. Special Options Registers (PSORA–POSRD) PSOR bits are effective only if the corresponding PPARx[DDx] = 1 (a dedicated peripheral function). Table 41-4 describes PSORx fields. Table 41-4. PSORx Field Descriptions Bits 0–31 Name SOx Description Special-option. Determines whether a pin configured for a dedicated function (PPARx[DD x] = 1) uses option 1 or option 2. Note that bits SO0–SO3 are valid for PSORA and PSORC only. Options are described in Section 41.2, “Port Registers.” 0 Dedicated peripheral function. Option 1. 1 Dedicated peripheral function. Option 2. NOTE Program PSORx and PDIRx before programming PPARx to ensure desired functions are configured when PPARx bits are set. Otherwise, a pin might function for a short period as an unwanted dedicated function and cause unknown behavior. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-5 Parallel I/O Ports 41.3 Port Block Diagram Figure 41-6 shows the functional block diagram. Read To/from internal bus PDATx Write PDATx Read PDATx Latch From DED OUT1 From DED OUT2 0 1 1 PSOR PPAR PDIR PODR 0 O pen Drain Control EN Pin 0 To DED IN1 1 PPAR & PSOR & PDIR 0 To DED IN2 1 PPAR & PSOR & PDIR Register Name PPAR x PSORx PDIR x PODRx PDATx 1 Default Input IN1 Default Input IN2 0 General purpose Dedicated 1 Input Regular 0 1 Dedicated Dedicated 2 Output Open drain 1 Description Port pin assignment Special operation Direction1 Data Bidirectional signals must be programmed as inputs (PDIR = 0). Figure 41-6. Port Functional Operation 41.4 Port Pins Functions Each pin can operate as a general purpose I/O pin or as a dedicated input or output pin. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-6 Freescale Semiconductor Parallel I/O Ports 41.4.1 General Purpose I/O Pins Each one of the port pins is independently configured as a general-purpose I/O pin if the corresponding port pin assignment register (PPAR) bit is cleared. Each pin is configured as a dedicated on-chip peripheral pin if the corresponding PPAR bit is set.When the port pin is configured as a general-purpose I/O pin, the signal direction for that pin is determined by the corresponding control bit in the port data direction register (PDIR). The port I/O pin is configured as an input if the corresponding PDIR bit is cleared; it is configured as an output if the corresponding PDIR bit is set. All PPAR and PDIR bits are cleared on total system reset, configuring all port pins as general-purpose input pins. If a port pin is selected as a general-purpose I/O pin, it can be accessed through the port data register (PDATx). Data written to the PDATx is stored in an output latch. If a port pin is configured as an output, the output latch data is gated onto the port pin. In this case, when PDATx is read, the port pin itself is read. If a port pin is configured as an input, data written to PDATx is still stored in the output latch, but is prevented from reaching the port pin. In this case, when PDATx is read, the state of the port pin is read. 41.4.2 Dedicated Pins When a port pin is not configured as a general-purpose I/O pin, it has a dedicated functionality, as described in the following tables. Note that if an input to a peripheral is not supplied from a pin, a default value is supplied to the on-chip peripheral as listed in the right-most column. NOTE Some output functions can be output on 2 different pins. For example, the output for BRG1 can come out on both PC31 and PD19. The user can freely configure such functions to be output on two pins at once. However, there is typically no advantage in doing so unless there is a large fanout where it is advantageous to share the load between two pins. Many input functions can also come from two different pins; see Section 41.5, “Ports Tables.” 41.5 Ports Tables Table 41-5 through Table 41-8 describe the ports functionality according to the configuration of the port registers (PPARx, PSORx, and PDIRx). Each pin can function as a general purpose I/O, one of two dedicated outputs, or one of two dedicated inputs. As shown in Figure 41-7, some input functions can come from two different pins for flexibility. Secondary option programming is relevant only if primary option is programmed to the default value. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-7 Parallel I/O Ports PD4 Secondary option for SMC2 RxD GND 0 MUX PA8 Primary option for SMC2 RxD 0 to SMC2 RxD MUX Pin PD4 1 Pin PA8 1 PPARD[4] == 1 & PSORD[4] == 1 & PDIRD[4] == 0 PPARA[8] == 1 & PSORA[8] == 0 & PDIRA[8] == 0 Figure 41-7. Primary and Secondary Option Programming In the tables below, the default value for a primary option is simply a reference to the secondary option. In the secondary option, the programming is relevant only if the primary option is not used for the function. Table 41-5 shows the port A pin assignments. Table 41-5. Port A—Dedicated Pin Assignment (PPARA = 1) Pin Function Pin PSORA = 0 PDIRA = 1 (Output) PA31 PA30 FCC1: TxEnb1 UTOPIA master FCC1: TxClav1 UTOPIA slave PDIRA = 0 (Input) FCC1: TxEnb1 UTOPIA slave FCC1: TxClav1 UTOPIA master FCC1: TxClav01 MPHY, master, direct polling PSORA = 1 Defaul PDIRA = 0 (Input, or PDIRA = 1 (Output) t Input Inout if Specified) GND GND FCC1: RTS FCC1: COL M II FCC1: CRS M II Defaul t Input GND GND PA29 PA28 PA27 FCC1: TxSOC1 UTOPIA FCC1: RxEnb1 UTOPIA master FCC1: RxEnb1 UTOPIA slave FCC1: RxSOC1 UTOPIA GND GND FCC1: TX_ER MII FCC1: TX_EN MII/RMII FCC1: RX_DV M II FCC1: CRS_DV RMII FCC1: RX_ER MII/RMII GND PA26 FCC1: RxClav1 UTOPIA slave FCC1: RxClav1 UTOPIA master FCC1: RxClav01 MPHY, master, direct polling GND GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-8 Freescale Semiconductor Parallel I/O Ports Table 41-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued) Pin Function Pin PSORA = 0 PDIRA = 1 (Output) PA25 FCC1: TxD[0]1 UTOPIA 8 FCC1: TxD[8]1 UTOPIA 16 FCC1: TxD[1]1 UTOPIA 8 FCC1: TxD[9]1 UTOPIA 16 FCC1: TxD[2]1 UTOPIA 8 FCC1: TxD[10]1 UTOPIA 16 FCC1: TxD[3]1 UTOPIA 8 FCC1: TxD[11]1 UTOPIA 16 FCC1: TxD[4]1 UTOPIA 8 FCC1: TxD[12]1 UTOPIA 16 FCC1: TxD[3] M II/HDLC nibble FCC1: TxD[5]1 UTOPIA 8 FCC1: TxD[13]1 UTOPIA 16 FCC1: TxD[2] M II/HDLC nibble FCC1: TxD[6] UTOPIA 8 FCC1: TxD[14] UTOPIA 16 FCC1: TxD[1] M II/HDLC nibble FCC1: TxD[1] RMII dibit PDIRA = 0 (Input) PSORA = 1 Defaul PDIRA = 0 (Input, or PDIRA = 1 (Output) t Input Inout if Specified) MSNUM[0]2 Defaul t Input PA24 MSNUM[1]2 PA23 PA22 PA21 PA20 PA19 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-9 Parallel I/O Ports Table 41-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued) Pin Function Pin PSORA = 0 PDIRA = 1 (Output) PA18 FCC1: TxD[7]1 UTOPIA 8 FCC1: TxD[15]1 UTOPIA 16 FCC1: TxD[0] M II/HDLC nibble FCC1: TxD[0] RMII dibit FCC1: TxD HDLC/transp FCC1: RxD[7]1 UTOPIA 8 FCC1: RxD[15]1 UTOPIA 16 FCC1: RxD[0] MII/HDLC nibble FCC1: RxD[0] RMII dibit FCC1: RxD HDLC/transp. FCC1: RxD[6]1 UTOPIA 8 FCC1: RxD[14]1 UTOPIA 16 FCC1: RxD[1] MII/HDLC nibble FCC1: RxD[1] RMII dibit FCC1: RxD[5]1 UTOPIA 8 FCC1: RxD[13]1 UTOPIA 16 FCC1: RxD[2] MII/HDLC nibble FCC1: RxD[4]1 UTOPIA 8 FCC1: RxD[12]1 UTOPIA 16 FCC1: RxD[3] MII/HDLC nibble FCC1: RxD[3]1 UTOPIA 8 FCC1: RxD[11]1 UTOPIA 16 GND PDIRA = 0 (Input) PSORA = 1 Defaul PDIRA = 0 (Input, or PDIRA = 1 (Output) t Input Inout if Specified) Defaul t Input PA17 PA16 GND PA15 GND PA14 GND PA13 GND MSNUM[2]2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-10 Freescale Semiconductor Parallel I/O Ports Table 41-5. Port A—Dedicated Pin Assignment (PPARA = 1) (continued) Pin Function Pin PSORA = 0 PDIRA = 1 (Output) PA12 PDIRA = 0 (Input) FCC1: RxD[2]1 UTOPIA 8 FCC1: RxD[10]1 UTOPIA 16 FCC1: RxD[1]1 UTOPIA 8 FCC1: RxD[9] 1 UTOPIA 16 FCC1: RxD[0]1 UTOPIA 8 FCC1: RxD[8]1 UTOPIA 16 SMC2: SMTXD FCC2: TxAddr[4] SMC2: SMRXD (primary option) by PD4 PSORA = 1 Defaul PDIRA = 0 (Input, or PDIRA = 1 (Output) t Input Inout if Specified) GND MSNUM[3]2 Defaul t Input PA11 GND MSNUM[4]2 PA10 GND MSNUM[5]2 PA9 PA8 TDM_A1: L1TXD[0] Output, nibble TDM_A1: L1TXD Inout, serial TDM_A1: L1RXD[0] Input, nibble TDM_A1: L1RXD Inout, serial TDM_A1: L1TSYNC/GRANT TDM_A1: L1RSYNC GND GND PA7 PA6 PA5 FCC2: TxAddr[3] FCC2: RxAddr[3] SCC2: RSTRT SMC2: SMSYN (primary option) by PC0 GND GND GND FCC1: UTOPIA (secondary option) SCC2: REJECT CLK19 CLK20 SCC1: REJECT RxPrty1 GND FCC2: MPHY master RxAddr[2]1 IDMA4: DREQ PA4 PA3 PA2 PA1 PA0 1 2 FCC2: RxAddr[1]1 MPHY master FCC2: RxAddr[0]1 MPHY master FCC2: TxAddr[0]1 MPHY master FCC2: TxAddr[1]1 MPHY master SCC1: RSTRT VDD GND GND VDD FCC2: TxAddr[2]1 MPHY master IDMA4: DACK IDMA3: DACK IDMA4: DONE Inout TDM_A2: L1RXD[1] Nibble VDD GND IDMA3: DONE Inout IDMA3: DREQ VDD GND Not available on the MPC8270. MSNUM[0–4] is the sub-block code of the peripheral controller using SDMA; MSNUM[5] indicates which section, transmit or receive, is active during the transfer. See Section 19.2.4, “SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM).” MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-11 Parallel I/O Ports Table 41-6 shows the port B pin assignments. Table 41-6. Port B Dedicated Pin Assignment (PPARB = 1) Pin Function Pin PSORB = 0 PDIRB = 1 (Output) PB31 PB30 FCC2: TX_ER MII FCC2: TxSOC1 UTOPIA PDIRB = 0 (Input) FCC2: RxSOC1 UTOPIA FCC2: RX_DV MII FCC2: CRS_DV RMII FCC2: RxClav1 UTOPIA master FCC2: RX_ER MII/RMII FCC2: COL MII FCC2: CRS MII PSORB = 1 Defaul PDIRB = 0 (Input or PDIRB = 1 (Output) t Input Inout if Specified) GND GND TDM_B2: L1TXD Inout TDM_B2: L1RXD Inout Defaul t Input GND GND PB29 PB28 PB27 PB26 PB25 FCC2: RxClav1 UTOPIA slave FCC2: RTS FCC2: TxD[0]1 UTOPIA 8 FCC2: TxD[1]1 UTOPIA 8 FCC2: TxD[4]1 UTOPIA 8 FCC2: TxD[3] M II/HDLC nibble FCC2: TxD[5]1 UTOPIA 8 FCC2: TxD[2] M II/HDLC nibble FCC2: TxD[6]1 UTOPIA FCC2: TxD[1] M II/HDLC nibble FCC2: TxD[1] RMII dibit FCC2: TxD[7]1 UTOPIA FCC2: TxD[0] M II/HDLC nibble FCC2: TxD[0] RMII dibit FCC2: TxD H DLC/transp. serial GND GND GND GND FCC2: TX_EN MII/RMII SCC1: TXD TDM_B2: L1RSYNC TDM_B2: L1TSYNC/GRANT TDM_C2: L1TXD Inout TDM_C2: L1RXD Inout GND GND GND GND GND TDM_A1: L1TXD[3] Nibble TDM_C2: L1TSYNC/GRANT PB24 TDM_A1: L1RXD[3] Nibble GND TDM_C2: L1RSYNC GND PB23 TDM_A1: L1RXD[2] Nibble GND TDM_D2: L1TXD Inout GND PB22 TDM_A1: L1RXD[1] Nibble GND TDM_D2: L1RXD Inout GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-12 Freescale Semiconductor Parallel I/O Ports Table 41-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued) Pin Function Pin PSORB = 0 PDIRB = 1 (Output) PB21 PDIRB = 0 (Input) FCC2: RxD[7] UTOPIA 8 FCC2: RxD[0] MII/HDLC nibble FCC2: RxD[0] RMII dibit FCC2: RxD HDLC/transp. serial FCC2: RxD[6] UTOPIA 8 FCC2: RxD[1] MII/HDLC nibble FCC2: RxD[1] RMII dibit FCC2: RxD[5]1 UTOPIA 8 FCC2: RxD[2] MII/HDLC nibble FCC2: RxD[4] UTOPIA 8 FCC2: RxD[3] MII/HDLC nibble TDM_A1: L1RQ FCC3: RX_DV MII FCC3: CRS_DV RMII FCC3: RX_ER MII/RMII SCC2: RXD (primary option) SCC3: RXD (primary option) FCC3: COL MII FCC3: CRS MII FCC3: RxD[3] MII/HDLC nibble PSORB = 1 Defaul PDIRB = 0 (Input or PDIRB = 1 (Output) t Input Inout if Specified) GND TDM_A1: L1TXD[2] Nibble TDM_D2: L1TSYNC/GRANT Defaul t Input GND PB20 GND TDM_A1-L1TXD[1] Nibble TDM_D2: L1RSYNC GND PB19 GND TDM_D2: L1RQ TDM_A2: L1RXD[3] Nibble GND PB18 GND TDM_D2: L1CLKO TDM A2: L1RXD[2] Nibble GND PB17 GND CLK17 GND PB16 PB15 TDM_A1: L1CLKO FCC3: TX_ER MII FCC3: TX_EN MII/RMII TDM_B1: L1RQ GND by PD28 by PD25 GND TDM_A2: L1TXD[1] Nibble SCC2: TXD CLK18 TDM_C1: L1TXD Inout (primary option) TDM_C1: L1RXD Inout (primary option) TDM_C1: L1TSYNC/GRANT (primary option) TDM_C1: L1RSYNC (primary option) TDM_D1: L1TXD Inout (primary option) GND by PD28 by PD27 by PD16 by PD26 by PD25 PB14 PB13 PB12 PB11 TDM_B1: L1CLKO FCC2: TxD[0]1 UTOPIA 8 GND GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-13 Parallel I/O Ports Table 41-6. Port B Dedicated Pin Assignment (PPARB = 1) (continued) Pin Function Pin PSORB = 0 PDIRB = 1 (Output) PB10 FCC2: TxD[1]1 UTOPIA 8 FCC2: TxD[2]1 UTOPIA 8 PDIRB = 0 (Input) FCC3: RxD[2] MII/HDLC nibble FCC3: RxD[1] MII/HDLC nibble FCC3: RxD[1] RMII dibit FCC3: RxD[0] MII/HDLC nibble FCC3: RxD[0] RMII dibit FCC3: RxD HDLC/transp. serial FCC2: RxD[3]1 UTOPIA 8 (primary option) PSORB = 1 Defaul PDIRB = 0 (Input or PDIRB = 1 (Output) t Input Inout if Specified) GND TDM_D1: L1RXD Inout (primary option) TDM_A2: L1TXD[2] Nibble TDM_D1: L1TSYNC/GRANT (primary option) TDM_D1: L1RSYNC (primary option) Defaul t Input by PD24 by PD4 PB9 GND PB8 FCC2: TxD[3]1 UTOPIA 8 GND SCC3: TXD by PD23 PB7 FCC3: TXD[0] M II/HDLC nibble FCC3: TXD[0] RMII dibit FCC3: TXD HDLC/transp. serial FCC3: TXD[1] M II/HDLC nibble FCC3: TXD[1] RMII dibit FCC3: TXD[2] M II/HDLC nibble FCC3: TXD[3] M II/HDLC nibble by PC10 TDM_A2: L1TXD[0] Output, nibble TDM_A2: L1TXD Inout, serial (primary option) by PD22 PB6 FCC2: RxD[2]1 UTOPIA 8 (primary option) by PC11 TDM_A2: L1RXD Inout, serial TDM_A2: L1RXD[0] Input, nibble (primary option) TDM_A2: L1TSYNC/GRANT (primary option) FCC3: RTSN TDM_A2: L1RSYNC (primary option) by PD21 PB5 FCC2: RxD[1]1 UTOPIA 8 (primary option) FCC2: RxD[0]1 UTOPIA 8 (primary option) by PD10 by PD11 by PC9 PB4 by PD20 1 Not available on the MPC8270. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-14 Freescale Semiconductor Parallel I/O Ports Table 41-7 shows the port C pin assignments. Table 41-7. Port C Dedicated Pin Assignment (PPARC = 1) Pin Function PIN PSORC = 0 PDIRC = 1 (Output) PC31 PC30 PC29 BRG1: BRGO FCC2: TxD[3]1 UTOPIA 8 BRG2: BRGO PDIRC = 0 (Input) CLK1 CLK2 CLK3/TIN2 PSORC = 1 Defaul PDIRC = 0 (Input or PDIRC = 1 (Output) t Input Inout if Specified) CLK5 CLK6 CLK7 Timer1:TOUT SCC1: CTS2 SCC1: CLSN 2 Ethernet (secondary option) FCC2: RxAddr[4] SCC2: CTS2 SCC2: CLSN 2 Ethernet (secondary option) GND Defaul t Input PC28 Timer2: TOUT CLK4/TIN1 CLK8 GND PC27 FCC3: TxD HDLC/transp. serial FCC3: TxD[0] MII/HDLC nibble FCC3: TXD[0] RMII dibit Timer3: TOUT FCC2: TxD[2]1 UTOPIA 8 FCC2: TxD[3]1 UTOPIA 8 BRG5: BRGO FCC1: TxPrty1 UTOPIA (secondary option)2 BRG6: BRGO USB: OE BRG7: BRGO CLK5 GND BRG3: BRGO PC26 PC25 PC24 PC23 PC22 CLK6 CLK7 CLK8 CLK9 CLK10 GND GND GND CLK13 CLK14 BRG4: BRGO Timer4: TOUT IDMA1: DACK TMCLK real-time counter BRGO 1 IDMA1: DONE Inout (primary option) by PD5 PC21 PC20 PC19 CLK11 CLK12 CLK13 CLK15 CLK16 GND timer1/2: TGATE1 SPI: SPICLK2 Inout (secondary option) timer3/4: TGATE2 GND GND PC18 PC17 PC16 BRG8: BRGO CLK14 CLK15/TIN3 CLK16/TIN4 GND GND GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-15 Parallel I/O Ports Table 41-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued) Pin Function PIN PSORC = 0 PDIRC = 1 (Output) PC15 SMC2: SMTXD PDIRC = 0 (Input) SCC1: CTS SCC1: CLSN Ethernet (primary option) SCC1: CD SCC1: RENA Ethernet TDM_D1: L1RQ SCC2: CTS SCC2: CLSN Ethernet (primary option) SCC2: CD SCC2: RENA Ethernet SCC3: CTS SCC3: CLSN Ethernet (primary option) SCC3: CD SCC3: RENA Ethernet SCC4: CTS SCC4: CLSN / USB: RP Ethernet (primary option) SCC4: CD SCC4: RENA / USB: RN Ethernet FCC1: CTS PSORC = 1 Defaul PDIRC = 0 (Input or PDIRC = 1 (Output) t Input Inout if Specified) by PC29 FCC1: TxAddr[0]1 MPHY, master FCC1: TxAddr[0]1,3 MPHY, slave FCC2: TxAddr[4] MPHY, slave FCC1: RxAddr[0]1,3 MPHY, slave FCC2: RxAddr[4]1 MPHY, slave FCC1: TxAddr[1]1,3 MPHY, slave FCC2: TxAddr[3]1 MPHY, slave FCC1: RxAddr[1]1,3 MPHY, slave FCC2: RxAddr[3]1 MPHY, slave FCC2: RxD[2]1, 3 UTOPIA 8 (secondary option) FCC2: RxD[3]1,3 UTOPIA (secondary option) TDM_A2: L1TSYNC/GRANT (secondary option) Defaul t Input GND PC14 GND FCC1: RxAddr[0]1 MPHY, master GND PC13 by PC28 FCC1: TxAddr[1]1 MPHY, master GND PC12 SI1: L1ST3 GND FCC1: RxAddr[1]1 MPHY, master GND PC11 TDM_D1: L1CLKO by PC8 TDM_A2: L1TXD[3] Nibble GND PC10 FCC1: TxD[2]1 UTOPIA 16 FCC1: TxD[1]1 UTOPIA 16 GND SI1: L1ST4 strobe SI2: L1ST1 strobe GND PC9 by PC3 GND PC8 FCC1: TxD[0]1 UTOPIA 16 GND SI2: L1ST2 Strobe SCC3: CTS SCC3:CLSN2 (secondary option) FCC1: TxAddr[2]1,3 MPHY, slave, multiplexed polling FCC1: TxClav11,3 MPHY, master, direct polling FCC2: TxAddr[2]1 MPHY, slave, multiplexed polling GND PC7 TDM_C1: L1RQ GND FCC1: TxAddr[2]1 MPHY master, multiplexed: polling GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-16 Freescale Semiconductor Parallel I/O Ports Table 41-7. Port C Dedicated Pin Assignment (PPARC = 1) (continued) Pin Function PIN PSORC = 0 PDIRC = 1 (Output) PC6 TDM_C1: L1CLKO PDIRC = 0 (Input) FCC1: CD PSORC = 1 Defaul PDIRC = 0 (Input or PDIRC = 1 (Output) t Input Inout if Specified) GND FCC1: RxAddr[2]1 MPHY, master, multiplexed polling FCC1: RxAddr[2]1,3 MPHY, slave, multiplexed polling) FCC1: RxClav11,3 MPHY, master, direct polling FCC2: RxAddr[2]1 MPHY, slave, multiplexed polling FCC2: CTS FCC2: CD SCC4: CTS SCC4: CLSN 2 (secondary option) IDMA2: DONE Inout TDM_A2: L1RQ SPI: SPISEL2 Inout (secondary option) SMC2: SMSYN (secondary option) GND Defaul t Input GND PC5 PC4 PC3 FCC2: TxClav1 UTOPIA, slave FCC2: RxEnb1 UTOPIA, master FCC2: TxD[2]1 UTOPIA 8 FCC2: TxD[3]1 UTOPIA 8 BRG6: BRGO FCC2: TxClav1 UTOPIA, master FCC2: RxEnb1 UTOPIA, slave FCC3: CTS GND GND GND SI2: L1ST3 Strobe SI2: L1ST4 Strobe IDMA2: DACK GND GND GND PC2 PC1 FCC3: CD IDMA2: DREQ GND GND VDD PC0 1 2 BRG7: BRGO IDMA1: DREQ GND TDM_A2: L1CLKO Not available on the MPC8270. Available only when the primary option for this function is not used. 3 MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”) Table 41-8 shows the port D pin assignments. Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1) Pin Function Pin PDIRD = 1 (Output) PD31 PD30 FCC2: TxEnb UTOPIA master 1 PSORD = 0 PDIRD = 0 (Input) SCC1: RXD FCC2: TxEnb UTOPIA slave 1 PSORD = 1 Defaul PDIRD = 0 (Input, or PDIRD = 1 (Output) t Input Inout if Specified) GND GND SCC1: TXD Defaul t Input MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-17 Parallel I/O Ports Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued) Pin Function Pin PDIRD = 1 (Output) PD29 SCC1: RTS SCC1: TENA Ethernet PSORD = 0 PDIRD = 0 (Input) PSORD = 1 Defaul PDIRD = 0 (Input, or PDIRD = 1 (Output) t Input Inout if Specified) FCC1: RxAddr[3]1,2 FCC1: RxAddr[3]1,3 MPHY, master, MPHY, slave, multiplexed polling multiplexed polling FCC2: RxAddr[4]1 FCC1: RxClav21, 3 MPHY, master, MPHY, master, direct multiplexed polling polling FCC2: RxAddr[1]1 MPHY, slave, multiplexed polling SCC2: RXD4 (secondary option) FCC1: RxD[7]1 UTOPIA 16 FCC1: RxD[6]1 UTOPIA 16 SCC3: RXD4 (secondary option) FCC1: RxD[5]1 UTOPIA 16 FCC1: RxD[4]1 UTOPIA 16 SCC4: RXD / USB: Rxd GND TDM_C1: L1TXD 4 Inout (secondary option) TDM_C1: L1RXD 4 Inout (secondary option) TDM_C1: L1RSYNC4 (secondary option) TDM_D1: L1TXD 4 Inout (secondary option) TDM_D1: L1RXD 4 Inout (secondary option) TDM_D1: L1RSYNC4 (secondary option) TDM_A2: L1TXD[0]4 Output, nibble (secondary option) TDM_A2: L1TXD 4 Inout, serial (secondary option) TDM_A2: L1RXD 4 Inout, serial TDM_A2: L1RXD[0]4 Input, nibble (secondary option) TDM_A2: L1RSYNC4 (secondary option) Defaul t Input GND PD28 FCC1: TxD[7]1 UTOPIA 16 bit SCC2: TXD GND PD27 GND GND PD26 SCC2: RTS SCC2: TENA Ethernet FCC1: TxD[6]1 UTOPIA 16 SCC3: TXD GND GND PD25 GND GND PD24 GND GND PD23 SCC3: RTS SCC3: TENA Ethernet FCC1: TxD[5]1 UTOPIA 16 GND GND PD22 GND GND PD21 SCC4: TXD / USB: TN FCC1: RxD[3]1 UTOPIA 16 GND GND PD20 SCC4: RTS SCC4: TENA Ethernet USB: TP FCC1: RxD[2]1 UTOPIA 16 GND GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-18 Freescale Semiconductor Parallel I/O Ports Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued) Pin Function Pin PDIRD = 1 (Output) PD19 FCC1: TxAddr[4] 1, 2 PSORD = 0 PDIRD = 0 (Input) FCC1: TxAddr[4] 11,3 MPHY, slave, multiplexed polling FCC1: TxClav31,3 MPHY, master, direct polling FCC2: TxAddr[0]1 MPHY, slave, multiplexed polling FCC1: RxAddr[4]1,3 MPHY, slave, multiplexed polling FCC1: RxClav31,3 MPHY, master, direct polling FCC2: RxAddr[0]1 MPHY, slave, multiplexed polling FCC1: RxPrty UTOPIA (primary option) TDM_C1: L1TSYNC/GRANT4 (secondary option) FCC1: RxD[1]1 UTOPIA 16 FCC1: RxD[0] 1 UTOPIA 16 PSORD = 1 Defaul PDIRD = 0 (Input, or PDIRD = 1 (Output) t Input Inout if Specified) GND BRG1: BRGO SPI: SPISEL (primary option) Defaul t Input VDD MPHY, master, multiplexed polling FCC2: TxAddr[3]1 MPHY, master, multiplexed polling PD18 FCC1: RxAddr[4]1,2 MPHY, master, multiplexed polling FCC2: RxAddr[3]1 MPHY, master, multiplexed polling GND SPI: SPICLK Inout (primary option) GND PD17 BRG2: BRGO GND SPI: SPIMOSI Inout SPI: SPIMISO Inout I2C: I2CSDA Inout I2C: I2CSCL Inout TDM_B1: L1TXD Inout TDM_B1: L1RXD Inout VDD PD16 FCC1: TxPrty1 UTOPIA (primary option) TDM_C2: L1RQ TDM_C2: L1CLKO SI1: L1ST1 SI1: L1ST2 TDMB2: L1RQ GND SPIMO SI VDD GND GND GND GND PD15 PD14 PD13 PD12 PD11 GND GND FCC2: RxD[0]1,4 UTOPIA 8 (secondary option) FCC2: RxD[1]1,4 UTOPIA 8 (secondary option) GND TDM_B1: L1TSYNC/GRANT BRG4: BRGO TDM_B1: L1RSYNC PD10 TDMB2: L1CLKO GND GND PD9 SMC1: SMTXD BRG3: BRGO FCC2: RxPrty 1 UTOPIA GND MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-19 Parallel I/O Ports Table 41-8. Port D Dedicated Pin Assignment (PPARD = 1) (continued) Pin Function Pin PDIRD = 1 (Output) PD8 PD7 FCC2: TxPrty 1 UTOPIA PSORD = 0 PDIRD = 0 (Input) SMC1: SMRXD SMC1: SMSYN PSORD = 1 Defaul PDIRD = 0 (Input, or PDIRD = 1 (Output) t Input Inout if Specified) GND GND BRG5: BRGO FCC1: TxAddr[3]1,2 FCC1: TxAddr[3]1,3 MPHY, master, M PHY, slave, multiplexed polling multiplexed polling FCC2: TxAddr[4]1 FCC1: TxClav21,3 MPHY, master, direct MPHY, master, polling multiplexed polling FCC2: TxAddr[1]1 MPHY, slave, multiplexed polling IDMA1: DACK IDMA1: DONE4 Inout (secondary option) TDM_D1: L1TSYNC/GRANT4 (secondary option) GND FCC3: RTS SMC2: SMRXD4 (secondary option) VDD GND Defaul t Input PD6 PD5 FCC1: TxD[4] 1 UTOPIA 16 FCC1: TxD[3] 1 UTOPIA 16 BRG8: BRGO PD4 GND 1 2 Not available on the MPC8270. MPHY address pins 3 and 4 (master mode) can come from FCC2, depending on CMXUAR programming. (See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”) 3 MPHY address pins 0–4 (slave mode) can come from FCC2, depending on CMXUAR programming. (See Section 16.4.1, “CMX UTOPIA Address Register (CMXUAR).”) 4 Available only when the primary option for this function is not used. 41.6 Interrupts from Port C The port C lines associated with CDx and CTSx have a mode of operation where the pin can be internally connected to the SCC/FCC but can also generate interrupts. Port C still detects changes on the CTS and CD pins and asserts the corresponding interrupt request, but the SCC/FCC simultaneously uses CTS and/or CD to automatically control operation. This lets the user fully implement protocols V.24, X.21, and X.21 bis (with the assistance of other general-purpose I/O lines). To configure a port C pin as a CTS or CD pin that connects to the SCC/FCC and generates interrupts, these steps should be followed: 1. Write the corresponding PPARC bit with a 1 and PSORC bit with 0. 2. Write the corresponding PDIRC bit with a zero. 3. Set the SIEXR bit (in the interrupt controller) to determine which edges cause interrupts. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-20 Freescale Semiconductor Parallel I/O Ports 4. Write the corresponding SIMR (mask register) bit with a 1 to allow interrupts to be generated to the core. 5. The pin value can be read at any time using PDATC. NOTE After connecting CTS or CD to the SCC/FCC, the user must also choose the normal operation mode in GSMR[DIAG] to enable and disable SCC/FCC transmission and reception with these pins. The IDMA-DREQ signals on port C can assert an external request to the CP instead of asserting an interrupt to the core. Each line can be programmed to assert an interrupt request upon a high-to-low change or any change as configured in SIEXR. NOTE Do not program the IDMAx-DREQ pins to assert external requests to the IDMA, unless the IDMA is used. Otherwise, erratic operation occurs. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 41-21 Parallel I/O Ports MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 41-22 Freescale Semiconductor Appendix A Register Quick Reference Guide A0 This section provides a brief guide to the core registers. A.1 PowerPC Registers—User Registers The implements the user-level registers defined by the PowerPC architecture except those required for supporting floating-point operations (the floating-point register file (FPRs) and the floating-point status and control register (FPSCR)). User-level, PowerPC registers are listed in Table A-1 and Table A-2. Table A-2 lists user-level special-purpose registers (SPRs). Table A-1. User-Level PowerPC Registers (non-SPRs) Description General-purpose registers Condition register Name Comments Access Level User User Serialize Access — Only mtcrf GPRs The thirty-two 32-bit (GPRs) are used for source and destination operands. CR See the Programming Environments Manual Table A-2 lists SPRs defined by the PowerPC architecture implemented on the MPC8280. Table A-2. User-Level PowerPC SPRs SPR Number Name Decimal SPR [5–9] SPR [0–4] 1 8 9 268 269 1 2 Comments Serialize Access 00000 00000 00000 01000 01000 00001 01000 01001 01100 01101 XER LR CTR See the Programming Environments Manual See the Programming Environments Manual See the Programming Environments Manual Write: Full sync Read: Sync relative to load/store operations No No Write (as a store) TBL read 1 See the Programming Environments Manual TBU read 2 Extended opcode for mftb, 371 rather than 339. Any write (mtspr) to this address causes an implementation-dependent software emulation exception. A.2 PowerPC Registers—Supervisor Registers All supervisor-level registers implemented on the MPC8280 are SPRs, except for the machine state register (MSR), described in Table A-3. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor A-1 Register Quick Reference Guide Table A-3. Supervisor-Level PowerPC Registers Description Machine state register Name MSR Comments See the Programming Environments Manual and G2 PowerPC Core Reference Manual Serialize Access Write fetch sync Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture. Table A-4. Supervisor-Level PowerPC SPRs SPR Number Name Decimal SPR[5–9] 18 00000 SPR[0–4] 10010 DSISR See the Programming Environments Manual See the Programming Environments Manual See the Programming Environments Manual See the Programming Environments Manual See the Programming Environments Manual See the Programming Environments Manual Write: Full sync Read: Sync relative to load/store operations Write: Full sync Read: Sync relative to load/ store operations Write Write Write Write Comments Serialize Access 19 00000 10011 DAR 22 26 27 272 273 274 275 284 285 287 1 00000 00000 00000 01000 01000 01000 01000 01000 01000 01000 10110 11010 11011 10000 10001 10010 10011 11100 11101 11111 DEC SRR0 SRR1 SPRG0 SPRG1 SPRG2 SPRG3 TBL write1 See the Programming Environments Manual TBU write 1 PVR Section 2.3.1.2.4, “Processor Version Register (PVR).” Write (as a store) No (read-only register) Any read (mftb) to this address causes an implementation-dependent software emulation exception. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 A-2 Freescale Semiconductor Register Quick Reference Guide A.3 MPC8280-Specific SPRs Table A-2 and Table A-5 list SPRs specific to the MPC8280. Debug registers, which have additional protection, are described in Chapter 36, “System Development and Debugging.” Supervisor-level registers are described in Table A-5. Table A-5. MPC8280-Specific Supervisor-Level SPRs SPR Number Name Decimal SPR[5–9] 976 977 978 979 980 981 982 1008 11110 11110 11110 11110 11110 11110 11110 11111 SPR[0–4] 10000 10001 10010 10011 10100 10101 10110 10000 DMISS DCMP HASH1 HASH2 IMISS ICMP RPA HID0 See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. See the G2 PowerPC TM Core Reference Manual. Section 2.3.1.2.1, “Hardware Implementation-Dependent Register 0 (HID0).” Section 2.3.1.2.2, “Hardware Implementation-Dependent Register 1 (HID1).” See the G2 PowerPC TM Core Reference Manual. Section 2.3.1.2.3, “Hardware Implementation-Dependent Register 2 (HID2).” Comments Serialize Access 1009 11111 10001 HID1 1010 1011 11111 11111 10010 10011 IABR HID2 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor A-3 Register Quick Reference Guide MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 A-4 Freescale Semiconductor Appendix B Revision History This appendix provides a list of the major differences between revisions of the MPC8280 PowerQUICC II Family Reference Manual. There were no significant changes between revisions. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor B-1 Revision History MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 B-2 Freescale Semiconductor Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std. 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by the Institute of Electrical and Electronics Engineers, Inc. with the permission of the IEEE. Note that some terms are defined in the context usage in this book. A Architecture. A detailed specification of requirements for a processor or computer system. It does not specify details for implementing the processor or computer system; instead, it provides a template for a family of compatible implementations. Asynchronous exception. Exception caused by events external to the processor’s execution. In this document, the term ‘asynchronous exception’ is used interchangeably with the word 'interrupt'. Atomic access. A bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address (the term refers to the fact that the transactions are indivisible). The PowerPC architecture implements atomic accesses through the lwarx/stwcx. instruction pair. Autobaud. The process of determining a serial data rate by timing the width of a single bit. B Big-endian. A byte-ordering method in memory where the address n of a word corresponds to the most-significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 as the most-significant byte. See Little-endian. Blockage. A pipeline stall that occurs when an instruction occupies an execution unit and prevents a subsequent instruction from being dispatched. Boundedly undefined. A characteristic of results of certain operations that are not rigidly prescribed by the PowerPC architecture. Boundedly- undefined results for a given operation may vary among implementations, and between execution attempts in the same implementation. Although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined, the results of executing instructions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction. Breakpoint. A programmable event that forces the core to take a breakpoint exception. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Glossary-1 Burst. A bus transfer whose data phase consists of a sequence of transfers. For example, on a 64-bit bus, a 4-beat burst can transfer four 64-bit double words. Bus parking. A feature that optimizes the use of the bus by allowing a device to retain bus mastership without having to rearbitrate. C Cache. High-speed memory component containing recently-accessed data and/or instructions (subset of main memory). Cache coherency. An attribute in which an accurate and common view of memory is provided to all devices that share a memory system. Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor’s cache. Cache flush. An operation that removes from a cache any data from a specified address range. This operation ensures that any modified data within the specified address range is written back to main memory. This operation is generated typically by a Data Cache Block Flush (dcbf) instruction. Caching-inhibited. A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. Cast-outs. Cache blocks that must be written to memory when a cache miss causes a cache block to be replaced. Changed bit. One of two page history bits found in each page table entry (PTE). The processor sets the changed bit if any store is performed into the page. See also Page access history bits and Referenced bit. Clear. To cause a bit or bit field to register a value of zero. The opposite of 'set'. Context synchronization. An operation that ensures that all instructions in execution complete past the point where they can produce an exception, that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain events occur (such as an exception). Copy-back. An operation in which modified data in a cache block is copied back to memory. Critical-data first. An aspect of burst accesses that allow the requested data (typically a word or double word) in a cache block to be transferred first. D Denormalized number. A nonzero floating-point number whose exponent has a reserved value, usually the format's minimum, and whose explicit or implicit leading significand bit is zero. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-2 Freescale Semiconductor Direct-mapped cache. A cache in which each main memory address can appear in only one location within the cache. Operates more quickly when the memory request is a cache hit. Direct-store. Interface available on processors that implement the PowerPC architecture only to support direct-store devices from the POWER architecture. When the T bit of a segment descriptor is set, the descriptor defines the region of memory that will be a direct-store segment. Note that this facility is being phased out of the architecture and will not likely be supported in future devices. Therefore, software should not depend on it and new software should not use it. E Effective address (EA). The 32- or 64-bit address specified for a load, store, or an instruction fetch. This address is then submitted to the MMU for translation to either a physical memory address or an I/O address. Exception. A condition encountered by the processor that requires special, supervisor-level processing. Exception handler. A software routine that executes when an exception is taken. Normally, the exception handler corrects the condition that caused the exception, or performs some other meaningful task (that may include aborting the program that caused the exception). The address for each exception handler is identified by an exception vector offset defined by the architecture and a prefix selected via the MSR. Extended opcode. A secondary opcode field generally located in instruction bits 21–30 that further defines the instruction type. All PowerPC instructions are one word in length. The most significant 6 bits of the instruction are the primary opcode, identifying the type of instruction. See also Primary opcode. Execution synchronization. A mechanism by which all instructions in execution are architecturally complete before beginning execution (appearing to begin execution) of the next instruction. Similar to context synchronization but doesn't force the contents of the instruction buffers to be deleted and refetched. Exponent. In the binary representation of a floating-point number, the exponent is the component that normally signifies the integer power to which the value 2 is raised in determining the value of the represented number. See also Biased exponent. F Fetch. Retrieving instructions from either the cache or main memory and placing them into the instruction queue. Fully-associative. Addressing scheme in which every cache location (every byte) can have any possible address. G General-purpose register (GPR). Any of the 32 registers in the general-purpose register file. These registers provide the source operands and destination results for all MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Glossary-3 integer data manipulation instructions. Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory. H I Harvard architecture. An architectural model featuring separate caches for instructions and data. IEEE 754. A standard written by the Institute of Electrical and Electronics Engineers that defines operations and representations of binary floating-point arithmetic. Illegal instructions. A class of instructions that are not implemented for a particular processor that implement the PowerPC architecture. These include instructions not defined by the PowerPC architecture. In addition, for 32-bit implementations, instructions that are defined only for 64-bit implementations are considered to be illegal instructions. For 64-bit implementations instructions that are defined only for 32-bit implementations are considered to be illegal instructions. Implementation. A particular processor that conforms to the PowerPC architecture, but may differ from other architecture-compliant implementations (for example, in design, feature set, and implementation of optional features). The PowerPC architecture has many different implementations. Implementation-dependent. An aspect of a feature in a processor’s design that is defined by a processor’s design specifications rather than by the PowerPC architecture. Implementation-specific. An aspect of a feature in a processor’s design that is not required by the PowerPC architecture, but for which the PowerPC architecture may provide concessions to ensure that processors that implement the feature do so consistently. Imprecise exception. A type of synchronous exception that is allowed not to adhere to the precise exception model (See also Precise exception). The PowerPC architecture allows only floating-point exceptions to be handled imprecisely. Internal bus. The bus connecting the core and system interface unit (SIU). Instruction latency. The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction. Interrupt. An asynchronous exception. On PowerPC processors, interrupts are a special case of exceptions. See also Asynchronous exception. L Latency. Time that an operation requires. For example, execution latency is the number of processor clocks an instruction takes to execute. Memory latency is the number of bus clocks needed to perform a memory operation. Least-significant bit (lsb). The bit of least value in an address, register, data element, or instruction encoding. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-4 Freescale Semiconductor Least-significant byte (LSB). Byte of least value in an address, register, data element, or instruction encoding. Little-endian. Byte-ordering method in memory where the address n of a word corresponds to the least-significant byte. In an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte. See Big-endian. M Master. Name given to a bus device that has been granted control or mastership of the bus. Memory access ordering. Specific order in which the processor performs load and store memory accesses and the order in which those accesses complete. Memory controller. Unit whose primary function is to control the external bus memories and I/O devices. Memory coherency. Aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory. Memory consistency. Refers to agreement of levels of memory with respect to a single processor and system memory (for example, on-chip cache, secondary cache, and system memory). Memory management unit (MMU). The functional unit that is capable of translating an effective (logical) address to a physical address, providing protection mechanisms, and defining caching methods. Microarchitecture. The hardware details of a microprocessor’s design. Such details are not defined by the PowerPC architecture. Mnemonic. The abbreviated name of an instruction used for coding. Modified state. When a cache block is in the modified state, it has been modified by the processor since it was copied from memory. See MESI. Munging. A modification performed on an effective address that allows it to appear to the processor that individual aligned scalars are stored as little-endian values, when in fact it is stored in big-endian order, but at different byte addresses within double words. Note that munging affects only the effective address and not the byte order. Note also that this term is not used by the PowerPC architecture. Most-significant bit (msb). Highest-order bit in an address, registers, data element, or instruction encoding. Most-significant byte (MSB). Highest-order byte in an address, registers, data element, or instruction encoding. N No-op. No-operation. A single-cycle operation that does not affect registers or generate bus activity. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Glossary-5 O OEA (operating environment architecture). Level of the architecture that describes PowerPC memory management model, supervisor-level registers, synchronization requirements, and the exception model. It also defines the time-base feature from a supervisor-level perspective. Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA. Optional. A feature, such as an instruction, a register, or an exception, that is defined by the PowerPC architecture but not required to be implemented. Out-of-order. An aspect of an operation that allows it to be performed ahead of one that may have preceded it in the sequential model, for example, speculative operations. An operation is said to be performed out-of-order if, at the time that it is performed, it is not known to be required by the sequential execution model. See In-order. Out-of-order execution. A technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream. Overflow. An error condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register(s). For example, if two 32-bit numbers are multiplied, the result may not be representable in 32 bits. P Pace control. Controls the rate of the data flow between a master and slave. Page. Region in memory. The OEA defines a page as a 4-Kbyte area of memory, aligned on a 4-Kbyte boundary. Page fault. Condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory. On processors that implement the PowerPC architecture, a page fault exception condition occurs when a matching, valid page table entry (PTE[V] = 1) cannot be located. Physical memory. The actual memory that can be accessed through the system’s memory bus. Pipelining. Technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed. Precise exceptions. A category of exception for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after exception handling has completed. See Imprecise exceptions. Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding that identifies the type of instruction. See Secondary opcode. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-6 Freescale Semiconductor Protection boundary. Boundary between protection domains. Protection domain. A protection domain is a segment, a virtual page, a BAT area, or a range of unmapped effective addresses. It is defined only when the appropriate relocate bit in the MSR (IR or DR) is 1. Q R Quad word. A group of 16 contiguous locations starting at an address divisible by 16. rA. Instruction field that specifies a GPR to be used as a source or destination. rB. Instruction field that specifies a GPR to be used as a source. rD. Instruction field that specifies a GPR to be used as a destination. rS. Instruction field that specifies a GPR to be used as a source. Real address mode. An MMU mode when no address translation is performed and the effective address specified is the same as the physical address. The processor’s MMU is operating in real address mode if its ability to perform address translation was disabled through the MSR registers IR or DR bits. Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When set, it updates the condition register (CR) to reflect the result of the operation. Register indirect addressing. A form of addressing that specifies one GPR that contains the address for the load or store. Register indirect with immediate index addressing. A form of addressing that specifies an immediate value to be added to the contents of a specified GPR to form the target address for the load or store. Register indirect with index addressing. A form of addressing that specifies that the contents of two GPRs be added together to yield the target address for the load or store. Reservation. The processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a memory semaphore into a GPR. Reserved field. In a register, a reserved field is one that is not assigned a function. A reserved field may be a single bit. The handling of reserved bits is implementation-dependent. Software is permitted to write any value to such a bit. A subsequent reading of the bit returns 0 if the value last written to the bit was 0 and returns an undefined value (0 or 1) otherwise. RISC (reduced instruction set computing). An architecture characterized by fixed-length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Glossary-7 S Scalability. The capability of an architecture to generate implementations specific for a wide range of purposes, and in particular implementations of significantly greater performance or functionality than at present, while maintaining compatibility with current implementations. Scan chain. The peripheral buffers of a device, linked in JTAG test mode, which are addressed in a shift-register fashion. Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term ‘set’ may also be used to describe updating of a bit or bit field. Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in any one of the sets, typically corresponding to its lower-order address bits. Because several memory locations can map to the same location, cached data is typically placed in the set whose cache block corresponding to that address was used least recently. See Set-associative. Set-associative. Aspect of cache organization in which the cache space is divided into sections, called sets. The cache controller associates a particular main memory address with the contents of a particular set or region within the cache. Significand. The component of a binary floating-point number that consists of an explicit or implicit leading bit to the left of its implied binary point and a fraction field to the right. Slave. A device that responds to the master’s address. A slave receives data on a write cycle and gives data to the master on a read cycle. Static branch prediction. Mechanism by which software (for example, compilers) can give a hint to the machine hardware about the direction a branch is likely to take. Sticky bit. A bit that when set must be cleared explicitly. Superscalar machine. A machine that can issue multiple instructions concurrently from a conventional linear instruction stream. Supervisor mode. The privileged operation state of a processor. In supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. Synchronization. A process to ensure that operations occur strictly in order. See Context synchronization and Execution synchronization. Synchronous exception. An exception that is generated by the execution of a particular instruction or instruction sequence. The two types of synchronous exceptions are precise and imprecise. System memory. Physical memory available to a processor. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-8 Freescale Semiconductor T Time-division multiplex (TDM). A single serial channel used by several channels that take turns. TLB (translation lookaside buffer). A cache that holds recently used page table entries. Throughput. The measure of the number of instructions that are processed per clock cycle. U UISA (user instruction set architecture). The level of the architecture to which user-level software should conform. The UISA defines the base user-level instruction set, user-level registers, data types, floating-point memory conventions and exception models as seen by user programs, and the memory and programming models. User mode. The unprivileged operating state of a processor used typically by application software. In user mode, software can only access certain control registers and can access only user memory space. No privileged operations can be performed. Also referred to as 'problem state' V VEA (virtual environment architecture). The level of the architecture that describes the memory model for an environment in which multiple devices can access memory, defines aspects of the cache model, defines cache control instructions, and defines the time-base facility from a user-level perspective. Implementations that conform to the PowerPC VEA also adhere to the UISA, but may not necessarily adhere to the OEA. Virtual address. An intermediate address used in the translation of an effective address to a physical address. Virtual memory. The address space created using the memory management facilities of the processor. Program access to virtual memory is possible only when it coincides with physical memory. W Watchpoint. An event that is reported, but does not change the timing of the machine. Word. A 32-bit data element. Note that on other processors a word may be a different size. Write-back. A cache memory update policy in which processor write cycles are directly written only to the cache. External memory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data. Write-through. A cache memory update policy in which all processor write cycles are written to both the cache and memory. MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Glossary-9 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Glossary-10 Freescale Semiconductor Index Index Numerics 603e features list, 2-3 60x bus 60x-compatible mode 60x-compatible bus mode, 8-3 address latch enable (ALE), 11-10 BUFCMD, 11-42 EAMUX signal, 11-42 MAR, 11-77 overview, 11-102 size calculation, 8-17 60x-to-local bus transaction priority, 11-7 address arbitration, 8-7 ARTRY, 8-21 operations, 8-7 pipelining, 8-8 timing configuration, 8-23 transfer attribute signals, 8-9 transfer termination, 8-21 bandwidth control on the IDMA channel, 19-11 bus protocol address pipelining, 8-6 arbitration phase, 8-5 overview, 8-4 split-bus transactions, 8-6 configuration, 8-2 data asserting TEA, 8-28 data bus arbitration, 8-24 data bus transfers, 8-25 data streaming mode, 8-25 effect of ARTRY assertion, 8-26 normal termination, 8-25 operations, 8-24 port size data bus transfers and PSDVAL termination, 8-26 data transfers alignment, 8-14 burst ordering, 8-13 port size, 8-15 extended transfer mode, 8-18 extended write cycle data bus contents, 8-19 little-endian mode, 8-31 LSDMR register, 11-24 lwarx/stwcx. support, 8-31 MEI protocol, 8-29 memory coherency, 8-29 no-pipeline mode, 8-23 one-level pipeline mode, 8-23 overview, 8-1 pipeline control, 8-23 port size device interfaces, 8-16 processor state signals, 8-30 PSDMR register, 11-20 single-MPC8280 bus mode, 8-2 TBST signal, 8-12 TCn signals, 8-12 terminology, 8-1 TESCRx registers, 11-33 TLBISYNC input, 8-31 TSIZn signals, 8-12 TTn signals, 8-9 60x bus memory controller, see Memory controller A AAL1, 32-1 3-step-SN algorithm, 32-20 three states, 32-20 application considerations, 32-45 ATM controller buffers, 32-39 RxBD, 32-39 TxBDs, 32-41 ATM-to-TDM adaptive slip control, 32-15 CES adaptive threshold tables, 32-16 buffer descriptors, 32-37 receive buffer operation, 32-38 transmit buffer operation, 32-37 cell format, 32-3 CES-specific additions to MCC, 32-45 connection tables, 32-25 protocol-specific RCT, 32-29 protocol-specific TCT, 32-35 RCT, 32-26 TCT, 32-32 data path, 32-3 exceptions, 32-42 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-1 interrupt queue entry, 32-42 external statistics tables, 32-45 features, 32-1 framing formats, 32-4 internal statistics tables, 32-44 interworking functions automatic data forwarding, 32-6 ATM-to-TDM, 32-7 TDM-to-ATM, 32-7 channel associated signaling support, 32-10 clock synchronization, 32-9 mapping ATM-to-TDM CAS support, 32-14 CAS mapping, 32-14 CAS routing table, 32-12 CAS updates, 32-15 TDM-to-ATM support, 32-13 VC signaling to CAS blocks, 32-11 mapping TDM time slots, 32-9 timing issues, 32-7, 32-8 trunk condition, 32-10 memory structure, 32-22 parameter RAM, 32-22 OCASSR, 32-36 overview, 32-3 pointer verification mechanism, 32-21 receiver data flow, 32-6 sequence number protection table, 32-43 AAL2, 33-1 exceptions, 33-40 features, 33-3 introduction, 33-1 parameter RAM, 33-36 receiver, 33-21 AAL2 Rx data structures, 33-24 CID mapping tables and RxQDs, 33-28 CPS Rx queue descriptors, 33-28 CPS switch Rx queue descriptor, 33-30 receive connection tables, 33-25 SSSAR receive buffer descriptor, 33-34 SSSAR Rx queue descriptor, 33-32 SWITCH receive/transmit buffer descriptor (RxBD), 33-31 AAL2 switching, 33-23 figure, 33-24 CID mapping process, 33-23 mapping of PHY | VP | VC | CID, 33-22 overview, 33-21 sublayer structure, 33-2 switching example, 33-3 transmitter, 33-5 AAL2 Tx data structures, 33-9 CPS buffer structure, 33-16 CPS Tx queue descriptor, 33-14 SSSAR transmit buffer descriptor, 33-20 SSSAR Tx queue descriptor, 33-18 no-STF mode, 33-8 overview, 33-5 partial fill mode (PFM), 33-7 transmit priority mechanism, 33-5 fixed priority, 33-6 flow, 33-7 round robin priority, 33-6 flow, 33-6 user-defined cells in AAL2, 33-39 accessing dual-port RAM, 14-21 Acronyms and abbreviated terms, list, 1-lxxxiv, -2, II-2, III-2, 2-4 AppleTalk mode GSMR, 26-4 programming example, 26-4 PSMR, 26-4 TODR, 26-4 ATM controller AAL1 sequence number protection table, 31-80 AALn RxBD, 31-6, 31-71 AALn TxBD, 31-5, 31-76 ABR flow control, 31-8, 31-19 address compression, 31-15 ATM layer statistics, 31-33 ATM memory structure, 31-36 ATM pace control (APC) unit ATM service types, 31-8 configuration, 31-102 data structures, 31-63 modes, 31-8 overview, 31-8 parameter tables, 31-64 priority table, 31-65 scheduling mechanism, 31-9 scheduling tables, 31-65 traffic type, 31-11 UBR+ traffic, 31-13 VBR traffic, 31-12 ATM TRANSMIT command, 31-92 ATM-to-ATM data forwarding, 31-36 ATM-to-TDM interworking, 31-33 buffer descriptors, 31-66 exceptions, 31-82 external rate mode, 31-6 FCCE, 31-91 FCCM, 31-91 features list, 31-1 FPSMR, 31-88 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-2 Freescale Semiconductor GFMR register, 31-88 global mode entry (GMODE), 31-40 internal rate mode, 31-6 interrupt queues, 31-82 maximum performance configuration, 31-101 OAM performance monitoring, 31-29, 31-62 OAM support, 31-27 operations and maintenance (OAM) support, 31-27 overview, 31-4 parameter RAM, 31-36 performance monitoring, 31-8 performance, maximum (configuration), 31-101 programming model, 31-88 receive connection table (RCT) AALn protocol-specific RCTs, 31-46, 31-46–??, 31-49 ATM channel code, 31-41 overview, 31-41 raw cell queue, 31-18 RCT entry format, 31-43 registers, 31-88 RxBD, 31-71 RxBD extension, 31-76 SRTS generation using external logic, 31-100 transmit connection table (TCT) AALn protocol-specific TCTs, 31-55 ATM channel code, 31-41 overview, 31-41 TCT entry format, 31-50 transmit connection table extension (TCTE) ABR protocol-specific, 31-59 ATM channel code, 31-41 overview, 31-41 UBR+ protocol-specific, 31-58 VBR protocol-specific, 31-57 transmit rate modes, 31-6 TxBD, 31-76 TxBD extension, 31-80 UDC extended address mode, 31-32 UEAD_OFFSET determination, 31-39 UNI statistics table, 31-81 user-defined cells (UDC) extended address mode, 31-32 overview, 31-32 RxBD extension (AAL5/AAL1), 31-76 TxBD extension (AAL5/AAL1), 31-80 user-defined RxBD extension (AAL5/AAL1), 31-76 user-defined TxBD extension (AAL5/AAL1), 31-80 UTOPIA interface, 31-84 VCI filtering, 31-39 VCI/VPI address lookup, 31-13 VC-level address compression tables (VCLT), 31-17 VP-level address compression table (VPLT), 31-16 B Baud-rate generator (BRG) BRGCLK, 40-2 memory map, 3-18 BCR (bus configuration register), 4-26 BDLE (SCC BISYNC DLE) register, 23-8 BISYNC mode commands, 23-4 control character recognition, 23-5 error handling, 23-9 frame reception, 23-3 frame transmission, 23-2 overview, 23-1 parameter RAM, 23-3 programming example, 23-18 programming the controller, 23-17 receiving synchronization sequence, 23-9 RxBD, 23-12 sending synchronization sequence, 23-9 TxBD, 23-14 block diagram dual-port RAM, 14-20 system PLL,, 10-6 Block diagrams cascaded mode, 18-3 communications processor (CP), 14-7 communications processor module (CPM), 14-3 CPM multiplexing logic (CMX), 16-2 DPLL receiver, 20-21 dual-bus architecture, 11-2 Fast Ethernet, 36-2 FCC overview, 30-3 I2C controller, 40-1 IEEE 1149.1 test access port, 1-2 parallel I/O ports, 41-6 SCC block diagram, 20-2 serial interface, 15-2 serial peripheral interface (SPI), 39-1 system interface unit (SIU) periodic interrupt timer, 4-5 SIU block diagram, 4-1 software watchdog timer, 4-7 system configuration/protection logic, 4-3 time counter (TMCNT), 4-5 timers, 18-1 Branch processing unit, 2-6 BRGCLK, 40-2 BRn (base registers), 11-13 BSYNC (BISYNC SYNC) register, 23-7 BUFCMD (external address and command buffers), 11-42 Buffer SPI buffer descriptor ring, 27-22 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-3 SPI receive buffer descriptor, 27-24 Buffer descriptors ATM controller receive, 31-67, 31-71 transmit, 31-66, 31-76 BISYNC mode, 23-12 definition, 32-22 fast communications controllers (FCCs) Fast Ethernet mode receive, 36-24 transmit, 36-27 HDLC mode receive, 37-9 transmit, 37-12 overview receive, 30-10 transmit, 30-10 GCI mode monitor channel, 28-33 HDLC mode, 22-8 I2C controller receive, 40-12 transmit, 40-13 IDMA emulation auto buffer, 19-15 IDMA buffers, 19-23 multi-channel controllers (MCCs) receive, 29-42 transmit, 29-45 overview, 20-10, 32-37 serial management controllers (SMCs), 28-4 serial peripheral interface (SPI) receive, 39-14 transmit, 39-15 transparent mode serial communications controllers (SCCs), 24-9 serial management controllers (SMCs), 28-26 UART mode serial communications controllers (SCCs), 21-14 serial management controllers (SMCs), 28-13 Buffers BUFCMD, 11-42 Bus interface hierarchical bus interface example, 11-102 BxTx (byte-select signals), 11-75 Byte stuffing, 23-1 Byte-select signals, 11-75 C Cache units, 2-8 Cascaded mode, 18-3 CHAMR (channel mode register), 29-8 CHAMR (channel mode register, transparent mode), 29-13, 29-15 Chip-select assertion timing, 11-53 chip-select machine, 11-51 signals, 11-74 write enable deassertion timing, 11-54 clock control,, 10-6, 10-7 Clocks memory map, 3-9 overview, 10-1 clocks and power control PLL pins,, 10-5 PLL, low power, and reset control register,, 10-6, 10-7 system clock control,, 10-6 system PLL skew elimination,, 10-2 clocks and reset keys memory map,, 3-5 CMXFCR (CMX FCC clock route register), 16-13 CMXSCR (CMX SCC clock route register), 16-16 CMXSI1CR (CMX SI1 clock route register), 16-12 CMXSI2CR (CMX SI2 clock route register), 16-12 CMXSMR (CMX SMC clock route register), 16-19 CMXUAR (CMX UTOPIA address register), 16-7 Commands ATM TRANSMIT command, 31-92 fast communications controllers (FCCs) Ethernet mode receive commands, 36-13 transmit commands, 36-12 HDLC mode receive commands, 37-6 transmit commands, 37-5 I2C controller, 40-11 IDMA emulation, 19-26 serial peripheral interface (SPI), 39-12 communication processor module features, 35-7 Communications processor (CP) block diagram, 14-7 execution from RAM, 14-9 features list, 14-4 memory map, 3-19 microcode execution from RAM, 14-9 microcode revision number, 14-12 peripheral interface, 14-8 RCCR, 14-10 REV_NUM, 14-12 RTSCR, 14-11 RTSR, 14-12 Communications processor module (CPM) ATM controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-4 Freescale Semiconductor AAL1 sequence number protection table, 31-80 AALn RxBD, 31-6, 31-71 AALn TxBD, 31-5, 31-76 ABR flow control, 31-8, 31-19 address compression, 31-15 ATM layer statistics, 31-33 ATM memory structure, 31-36 ATM pace control (APC) unit ATM service types, 31-8 configuration, 31-102 data structure, 31-63 modes, 31-8 overview, 31-8 parameter tables, 31-64 priority table, 31-65 scheduling mechanism, 31-9 scheduling tables, 31-65 traffic type, 31-11 UBR+ traffic, 31-13 VBR traffic, 31-12 ATM TRANSMIT command, 31-92 ATM-to-ATM data forwarding, 31-36 ATM-to-TDM interworking, 31-33 buffer descriptors, 31-66 exceptions, 31-82 external rate mode, 31-6 FCCE, 31-91 FCCM, 31-91 features list, 31-1 FPSMR, 31-88 GFMR register, 31-88 global mode entry (GMODE), 31-40 internal rate mode, 31-6 interrupt queues, 31-82 maximum performance configuration, 31-101 OAM performance monitoring, 31-29, 31-62 OAM support, 31-27 operations and maintenance (OAM) support, 31-27 overview, 31-4 parameter RAM, 31-36 performance monitoring, 31-8 performance, maximum (configuration), 31-101 programming model, 31-88 receive connection table (RCT) ATM channel code, 31-41 overview, 31-41 raw cell queue, 31-18 RCT entry format, 31-43 registers, 31-88 RxBD, 31-71 RxBD extension, 31-76 SRTS generation using external logic, 31-100 transmit connection table (TCT) AALn protocol-specific TCTs, ??–31-57 ATM channel code, 31-41 overview, 31-41 TCT entry format, 31-50 transmit connection table extension (TCTE) ABR protocol-specific, 31-59 ATM channel code, 31-41 overview, 31-41 UBR+ protocol-specific, 31-58 VBR protocol-specific, 31-57 transmit rate modes, 31-6 TxBD, 31-76 TxBD extension, 31-80 UDC extended address mode, 31-32 UEAD_OFFSET determination, 31-39 UNI statistics table, 31-81 user-defined cells (UDC) extended address mode, 31-32 overview, 31-32 RxBD extension (AAL5/AAL1), 31-76 TxBD extension (AAL5/AAL1), 31-80 user-defined RxBD extension (AAL5/AAL1), 31-76 user-defined TxBD extension (AAL5/AAL1), 31-80 UTOPIA interface, 31-84 VCI filtering, 31-39 VCI/VPI address lookup, 31-13 VC-level address compression tables (VCLT), 31-17 VP-level address compression table (VPLT), 31-16 block diagram, 14-3 command set command descriptions, 14-17 command execution latency, 14-19 command register example, 14-18 CPCR, 14-13 opcodes, 14-16 overview, 14-13 communications processor (CP) block diagram, 14-7 execution from RAM, 14-9 features list, 14-4 microcode execution from RAM, 14-9 microcode revision number, 14-12 peripheral interface, 14-8 RCCR, 14-10 REV_NUM, 14-12 RTSCR, 14-11 RTSR, 14-12 CPM multiplexing logic (CMX) block diagram, 16-2 overview, 16-1 dual-port RAM MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-5 buffer descriptors, 14-24 overview, 14-20 parameter RAM, 14-25 fast communications controllers (FCCs) Fast Ethernet mode address recognition, 36-15 block diagram, 36-2 CAM interface, 36-8 collision handling, 36-18 connecting to the MPC8280, 36-4 error handling, 36-18 FCCE, 36-21 FCCM, 36-21 features list, 36-2 FPSMR, 36-19 frame reception, 36-6 frame transmission, 36-5 hash table algorithm, 36-17 hash table effectiveness, 36-17 interpacket gap time, 36-18 interrupt events, 36-24 loopback mode, 36-18 parameter RAM, 36-8 programming model, 36-12 registers, 36-19 RMON support, 36-14 RxBD, 36-24 TxBD, 36-27 HDLC mode bit stuffing, 37-1 error control, 37-1 error handling, 37-6 FCCE, 37-14 FCCM, 37-14 FCCS, 37-16 features list, 37-1 FPSMR, 37-7 frame reception, 37-3 frame transmission, 37-2 overview, 37-1 parameter RAM, 37-3 programming model, 37-5 receive commands, 37-6 reception errors, 37-6 RxBD, 37-9 transmission errors, 37-6 transmit commands, 37-5 TxBD, 37-12 overview block diagram, 30-3 disabling FCCs, 30-20 FCCEx, 30-15 FCCMx, 30-15 FCCSx, 30-15 FCRx, 30-14 FDSRx, 30-8 FPSMRx, 30-8 FTODRx, 30-9 GFMRx, 30-3 initialization, 30-15 interrupt handling, 30-16 interrupts, 30-14 overview, 30-1 parameter RAM, 30-12 RxBD, 30-10 saving power, 30-22 switching protocols, 30-22 timing control, 30-17 TxBD, 30-10 transparent mode achieving synchronization, 38-2 external synchronization signals, 38-3 features list, 38-1 in-line synchronization pattern, 38-2 receive operation, 38-2 synchronization example, 38-3 transmit operation, 38-2 features list, 14-1 I2C controller block diagram, 40-1 BRGCLK, 40-2 clocking and pin functions, 40-2 commands, 40-11 features list, 40-2 loopback testing, 40-4 master read (slave write), 40-4 master write (slave read), 40-3 multi-master considerations, 40-5 parameter RAM, 40-9 programming model, 40-5 registers, 40-5 RxBD, 40-12 slave read (master write), 40-3 slave write (master read), 40-4 transfers, 40-2 TxBD, 40-13 IDMA emulation auto buffer, 19-15 buffer chaining, 19-15 buffers, 19-23 bus exceptions, 19-27 commands, 19-26 controlling 60x bus bandwidth, 19-11 DACKx, 19-13 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-6 Freescale Semiconductor DCM, 19-18 DONEx, 19-14 DREQx, 19-13 DTS/STS programming, 19-21 dual-address transfers, 19-10 edge-sensitive mode, 19-14 exceptions, bus, 19-27 external request mode, 19-8 features list, 19-5 IDMR, 19-23 IDSR, 19-23 level-sensitive mode, 19-14 normal mode, 19-9 operand transfers, recognizing, 19-28 operation, 19-15 overview, 19-5 parallel I/O register programming, 19-28 parameter RAM, 19-16 priorities, 19-12 programming examples, 19-29 programming the parallel I/O registers, 19-28 signals, 19-13 single address transfers (fly-by), 19-10 transfers, 19-6 interrupt controller memory map, 3-8 multi-channel controllers (MCCs) CHAMR HDLC mode, 29-8 transparent mode, 29-13, 29-15 channel extra parameters, 29-28 commands, 29-34 data structure organization, 29-2 exceptions, 29-35 features list, 29-1 global parameters, 29-4, 29-15 HDLC parameters (channel-specific), 29-5 initialization, 29-47 INTMSK, 29-15 MCCE, 29-37 MCCFx, 29-33 MCCM, 29-37 parameters for transparent operation, 29-11 RSTATE, 29-10 RxBD, 29-42 TSTATE, 29-7 TxBD, 29-45 overview, CPM, 14-1 parallel I/O ports block diagram, 41-6 features, 41-1 overview, 41-1 PDATx, 41-2 PDIRx, 41-3 pin assignments (port A–port D), 41-8–41-20 PODRx, 41-1 port C interrupts, 41-20 port pin functions, 41-6 PPAR, 41-4 programming options, 41-8 PSORx, 41-4 registers, 41-1 resetting registers and parameters for all channels, 14-14 RISC timer tables CP loading tracking, 14-32 features list, 14-27 initializing RISC timer tables, 14-30 interrupt handling, 14-31 overview, 14-27 parameter RAM, 14-27 RAM usage, 14-28 RTMR, 14-29 scan algorithm, 14-31 SET TIMER command, 14-30 table entries, 14-29 timer counts, comparing, 14-32 TM_CMD, 14-29 tracking CP loading, 14-32 SDMA channels bus arbitration, 19-2 bus transfers, 19-2 LDTEA, 19-4 LDTEM, 19-4 overview, 19-1 PDTEA, 19-4 PDTEM, 19-4 programming model, 19-3 registers, 19-3 SDMR, 19-4 SDSR, 19-3 serial configuration, 14-3 serial peripheral interface (SPI) block diagram, 39-1 clocking and pin functions, 39-2 commands, 39-12 configuring the SPI, 39-2 features list, 39-1 interrupt handling, 39-18 master mode, 39-3 maximum receive buffer length (MRBLR), 39-11 multi-master operation, 39-4 parameter RAM, 39-10 programming example master, 39-16 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-7 slave, 39-17 programming model, 39-6 RxBD, 39-14 slave mode, 39-4 SPCOM, 39-10 SPIE, 39-9 SPIM, 39-9 SPMODE, 39-6 TxBD, 39-15 system interface unit (SIU) 60x bus monitor function, 4-2 add flexibility to CPM interrupt priorities, 4-12 BCR, 4-26 block diagram, 4-1 bus monitor, 4-3 clocks, 4-3 configuration functions, 4-2 configuration/protection logic block diagram, 4-3 encoding the interrupt vector, 4-14 FCC relative priority, 4-12 flexibility of interrupt priorities, 4-12 highest priority interrupt, 4-13 IMMR, 4-36 interrupt controller features list, 4-7 interrupt priorities, add flexibility, 4-12 interrupt source priorities, 4-9 interrupt vector calculation, 4-14 interrupt vector encoding, 4-14 interrupt vector generation, 4-14 L_TESCR1, 4-43 L_TESCR2, 4-44 LCL_ACR, 4-31 LCL_ALRH, 4-32 LCL_ALRL, 4-33 local bus monitor function, 4-2 masking interrupt sources, 4-13 MCC relative priority, 4-12 periodic interrupt timer (PIT), 4-5 periodic interrupt timer (PIT) function, 4-2 pin multiplexing, 4-51 PISCR, 4-47 PITC, 4-48 PITR, 4-49 port C interrupts, 4-16 PPC_ACR, 4-29 PPC_ALRH, 4-30 PPC_ALRL, 4-31 programming model, 4-17 registers, 4-17 SCC relative priority, 4-12 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-25 signal multiplexing, 4-51 SIMR_H, 4-22 SIMR_L, 4-23 SIPNR_H, 4-21 SIPNR_L, 4-22 SIPRR, 4-18 SIUMCR, 4-33 SIVEC, 4-24 software watchdog timer, 4-6 SWR, 4-7 SWSR, 4-38 SYPCR, 4-37 system protection, 4-2 TESCR1, 4-40 TESCR2, 4-42 time counter (TMCNT) function, 4-2 overview, 4-4 timers, 4-3 TMCNT, 4-45 TMCNTAL, 4-46 TMCNTSC, 4-44 timers memory map, 3-10 Completion unit, 2-7 Conventions notational conventions, 1-lxxxiii, II-1, III-2, 2-3 terminology, 1-lxxxvii Core, see G2_LE core, 2-1 CPCR (CP command register), 14-13 CPCR (CPM command register), 27-32 CPM multiplexing logic (CMX) overview, 16-1 see also Serial interface (SI) CPM multiplexing, see CPM multiplexing logic (CMX) CPM MUX memory map, 3-24 CPM MUX, see CPM multiplexing logic (CMX) CxTx (chip-select signals), 11-74 D DCM (IDMA channel mode), 19-18 Digital phase-locked loop (DPLL) operation, 20-21 Dispatch unit, 2-5 DSR (data synchronization register) overview, 20-9 UART mode, 21-10 Dual-port RAM buffer descriptors, 14-24 parameter RAM, 14-25 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-8 Freescale Semiconductor E EAMUX (external address multiplexing) signal, 11-42 EDO interface connection, MPC8280 to 60x bus, 11-92 EPxPTR, 27-13 Ethernet mode fast communications controller (FCC) address recognition, 36-15 block diagram, 36-2 CAM interface, 36-8 collision handling, 36-18 connecting to the MPC8280, 36-4 error handling, 36-18 FCCE, 36-21 FCCM, 36-21 features list, 36-2 FPSMR, 36-19 frame reception, 36-6 frame transmission, 36-5 hash table algorithm, 36-17 hash table effectiveness, 36-17 interpacket gap time, 36-18 interrupt events, 36-24 loopback mode, 36-18 parameter RAM, 36-8 programming model, 36-12 registers, 36-19 RMON support, 36-14 RxBD, 36-24 TxBD, 36-27 Ethernet mode register,, 36-20 Exceptions exception handling, 11-73 overview, 2-21 EXTCLK,, 6-15 F Fast communications controllers (FCCs) Fast Ethernet mode address recognition, 36-15 block diagram, 36-2 CAM interface, 36-8 collision handling, 36-18 connecting to the MPC8280, 36-4 error handling, 36-18 FCCE, 36-21 FCCM, 36-21 features list, 36-2 FPSMR, 36-19 frame reception, 36-6 frame transmission, 36-5 hash table algorithm, 36-17 hash table effectiveness, 36-17 interpacket gap time, 36-18 interrupt events, 36-24 loopback mode, 36-18 parameter RAM, 36-8 programming model, 36-12 registers, 36-19 RMON support, 36-14 RxBD, 36-24 TxBD, 36-27 HDLC mode bit stuffing, 37-1 error control, 37-1 error handling, 37-6 FCCE, 37-14 FCCM, 37-14 FCCS, 37-16 features list, 37-1 FPSMR, 37-7 frame reception, 37-3 frame transmission, 37-2 overview, 37-1 parameter RAM, 37-3 programming model, 37-5 receive commands, 37-6 reception errors, 37-6 RxBD, 37-9 transmission errors, 37-6 transmit commands, 37-5 TxBD, 37-12 overview block diagram, 30-3 disabling FCCs, 30-20 FCCEx, 30-15 FCCMx, 30-15 FCCSx, 30-15 FCRx, 30-14 FDSRx, 30-8 FPSMRx, 30-8 FTODRx, 30-9 GFMRx, 30-3 initialization, 30-15 interrupt handling, 30-16 interrupts, 30-14 overview, 30-1 parameter RAM, 30-12 RxBD, 30-10 saving power, 30-22 switching protocols, 30-22 timing control, 30-17 TxBD, 30-10 switching protocols, 30-22 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-9 transparent mode features list, 38-1 receive operation, 38-2 synchronization achieving, 38-2 example, 38-3 external signals, 38-3 in-line pattern, 38-2 transmit operation, 38-2 FCCE register ATM, 31-91 Ethernet, 36-21 FCC overview, 30-15 HDLC, 37-14 FCCM register ATM, 31-91 Ethernet, 36-21 FCC overview, 30-15 HDLC, 37-14 FCCS (FCC status) register, 30-15, 37-16 FCRx (function code registers), 30-14 FDSRx (FCC data synchronization registers), 30-8 Features list SIU interrupt controller, 4-7 Features lists communications processor (CP), 14-4 communications processor module (CPM), 14-1 ATM controller, 31-1 parallel I/O ports, 41-1 CPM multiplexing, 16-2 Ethernet mode, 25-2 fast communications controllers (FCCs) Fast Ethernet, 36-2 HDLC mode, 37-1 transparent mode, 38-1 G2_LE core, 2-3 HDLC bus controller, 22-18 I2C controller, 40-2 IDMA emulation, 19-5 implementation-specific, 1-1 memory controller features list, 11-3 new features supported, 11-1 multi-channel controllers (MCCs), 29-1 processor core, 2-3 RISC timer tables, 14-27 serial communications controllers (SCCs) AppleTalk mode, 26-2 BISYNC mode, 23-2 general list, 20-2 HDLC mode, 22-1 transparent mode, 24-1 UART mode, 21-2 serial interface, 15-3 serial management controllers (SMCs) general list, 28-2 transparent mode, 28-20 UART mode, 28-11 UART mode, features not supported, 28-10 serial peripheral interface (SPI), 39-1 timers, 18-1 Floating-point unit (FPU), 2-6 FPSMR register Ethernet, 36-19 HDLC, 37-7 protocol-specific mode, 30-8 FPU, 2-3 Frame number (FRAME_N), 27-15 FTODRx (FCC transmit-on-demand registers), 30-9 G G2 features not present on PID6-603e, 2-5 G2_LE core features, 2-3 branch processing unit, 2-6 completion unit, 2-7 dispatch unit, 2-5 execution units, 2-6 floating-point unit (FPU), 2-6 integer unit (IU), 2-6 load/store unit (LSU), 2-7 System register unit (SRU, 2-7 instruction queue (IQ), 2-5 instruction unit, 2-5 memory subsystem support, 2-7 overview, 2-1 GCI activation and deactivation, 15-33 programming, 15-33 support, 15-31 General-purpose chip-select machine (GPCM) common features, 11-5 differences between MPC8xx and MPC8280, 11-63 external access termination, 11-61 implementation differences with UPMs and SDRAM machine, 11-6 interface signals, 11-52 MPC8xx versus MPC8280, 11-63 overview, 11-51 SRAM configuration, 11-52 strobe signal behavior, 11-53 terminating external accesses, 11-61 timing configuration, 11-53 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-10 Freescale Semiconductor General-purpose signals, 11-76 GFMR (general FCC mode register), 30-3, 31-88 GMODE (global mode entry), 31-40 GPLn (general-purpose signals), 11-76 GSMR (general SCC mode register) AppleTalk mode, 26-4 HDLC bus protocol, programming, 22-22 overview, 20-3 GSMR_H,, 31-96, 31-98, 31-99 gsmr_h,, 31-96, 31-98, 31-99 HID0 register bit settings, 2-11 doze, nap, sleep, DPM bits, 2-12 I I2ADD (I 2C address) register, 40-6 I2BRG (I2C baud rate generator) register, 40-7 I2C controller block diagram, 40-1 BRGCLK, 40-2 clocking and pin functions, 40-2 commands, 40-11 features list, 40-2 loopback testing, 40-4 master read (slave write), 40-4 master write (slave read), 40-3 multi-master considerations, 40-5 parameter RAM, 40-9 programming model, 40-5 registers, 40-5 RxBD, 40-12 slave read (master write), 40-3 slave write (master read), 40-4 transfers, 40-2 TxBD, 40-13 I2C memory map,, 3-18 I2CER (I2C event register), 40-7 I2CMR (I2C mask register), 40-7 I2COM (I2C command) register, 40-8 I2MOD (I2C mode) register, 40-6 IDL interface programming,, 15-29 IDL interface support, 15-25 IDMA emulation auto buffer, 19-15 buffer chaining, 19-15 buffers, 19-23 bus exceptions, 19-27 commands, 19-26 controlling 60x bus bandwidth, 19-11 DACKx, 19-13 DCM, 19-18 DONEx, 19-14 DREQx, 19-13 DTS/STS programming, 19-21 dual-address transfers, 19-10 edge-sensitive mode, 19-14 exception, bus, 19-27 external request mode, 19-8 features list, 19-5 IDMR, 19-23 IDSR, 19-23 level-sensitive mode, 19-14 H HDLC mode accessing the bus, 22-18 bus controller, 22-16 collision detection, 22-16, 22-19 commands, 22-5 delayed RTS mode, 22-20 error handling, 22-5 fast communications controllers (FCCs) bit stuffing, 37-1 error control, 37-1 error handling, 37-6 FCCE, 37-14 FCCM, 37-14 FCCS, 37-16 features list, 37-1 FPSMR, 37-7 frame reception, 37-3 frame transmission, 37-2 overview, 37-1 parameter RAM, 37-3 programming model, 37-5 receive commands, 37-6 reception errors, 37-6 RxBD, 37-9 transmission errors, 37-6 transmit commands, 37-5 TxBD, 37-12 features list, 22-1 GSMR, HDLC bus protocol programming, 22-22 multi-master bus configuration, 22-17 overview, 22-1 parameter RAM, 22-3 performance, increasing, 22-19 programming example, 22-14, 22-22 programming the controller, 22-4 PSMR, 22-7 RxBD, 22-8 single-master bus configuration, 22-18 TxBD, 22-11 using the TSA, 22-21 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-11 normal mode, 19-9 operand transfers, recognizing, 19-28 operation, 19-15 overview, 19-5 parallel I/O register programming, 19-28 parameter RAM, 19-16 priorities, 19-12 programming examples, 19-29 programming the parallel I/O registers, 19-28 signals, 19-13 single address transfers (fly-by), 19-10 transfers, 19-6 IDMA parameter RAM,, 19-16 IDMR (IDMA mask registers), 19-23 IDSR (IDMA event (status) register), 19-23 IEEE 1149.1 test access port block diagram, 1-2 boundary scan register, 1-3 instruction decoding, 1-6 instruction register, 1-5 nonscan chain operation, 1-7 overview, 1-1 restrictions, 1-7 TAP controller, 1-2 IMA, 34-1 FCC programming registers, 34-26 features, 34-1 ATM features not supported, 34-4 impact on MPC8280 features, 34-4 MPC8280 versions supported, 34-3 PHY-layer devices supported, 34-3 references, 34-3 versions supported, 34-3 microcode architecture, 34-10 function partitioning, 34-10 plane management functions, 34-11 receive, 34-17 cell processing activation function, 34-22 cell processing task, 34-24 cell reception task, 34-17 IDCR-regulated cell processing, 34-23 on-demand cell processing, 34-22 summary, 34-21 transmit, 34-11 non-TRL operation, 34-13 transmit queue (ITC mode), 34-14 TRL operation, 34-12 user plan functions, 34-11 programming model, 34-25 APC programming, 34-56 ABR, 34-57 CBR, UBR, VBR, and UBR+, 34-57 data structure organization, 34-25 exceptions, 34-49 ICP cell reception exceptions, 34-51 interrupt queue entry, 34-50 FCC programming IMA-specific parameters, 34-26 parameters, 34-26 GMODE, 34-26 RCELL_TMP_BASE, 34-26 TCELL_TMP_BASE, 34-26 group tables, 34-30 group receive control (IGRCNTL), 34-38 group receive state (IGRSTATE), 34-39 group receive table entry, 34-36 group transmit state (IGTSTATE), 34-32 ICP cell templates, 34-33 receive group frame size, 34-39 receive group order tables, 34-40 transmit group order table, 34-32 transmit table entry, 34-30 group transmit control (IGTCNTL), 34-31 IDCR timer programming, 34-52 FCC parameter shadow, 34-52 on-the-fly FCC parameter changes, 34-53 programming, 34-53 unavailable MPC8280 features, 34-52 IDCR counter algorithm, 34-55 IDCR events, 34-55 IDCR root parameters, 34-54 IDCR table entry, 34-54 IDCR_Init command, 34-54 master clock, 34-52 IMA FCC programming, 34-26 link tables, 34-41 link receive statistics table, 34-48 link receive table entry, 34-44 link receive control (ILRCNTL), 34-46 link receive state (ILRSTATE), 34-47 link transmit table entry, 34-41 ILTCNTL, 34-42 link transmit state (ILTSTATE), 34-43 transmit interrupt status (ITINTSTAT), 34-43 root table, 34-27 control (IMACNTL), 34-29 structures in external memory, 34-48 transmit queues, 34-48 delay compression buffers (DCB), 34-49 protocol overview, 34-4 IMA cells, 34-7 control cells, 34-7 filler cells, 34-10 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-12 Freescale Semiconductor IMA frame overview, 34-5 introduction, 34-4 root table data structures, 34-25 software interface and requirements, 34-58 initialization procedure, 34-59 software model, 34-58 software procedures, 34-62 end-to-end channel signalling, 34-74 transmit, 34-74 group start-up, 34-63 as initiator (TX), 34-64 as responder (RX), 34-65 IDCR operation, 34-73 IDCR mode group activation, 34-74 start-up, 34-73 link addition, 34-65 Rx steps, 34-65 TX parameters, 34-66 link receive deactivation procedure, 34-68 link receive reactivation, 34-69 link removal, 34-67 Rx steps, 34-67 TX parameters, 34-68 receive event response, 34-70 receive link start-up procedure, 34-62 test pattern, 34-72 as initiator (NE), 34-72 as responder (FE), 34-72 transmit event response, 34-70 transmit ICP cell signalling, 34-62 TRL on-the-fly change, 34-69 software responsibilities, 34-59 failure alarms, 34-61 general operation, 34-60 group symmetry control, 34-61 ICP end-to-end channel transmission, 34-61 link addition and slow recovery (LASR), 34-61 performance parameter measurement and reporting, 34-62 receive group state machine control, 34-60 receive link state machine control, 34-60 SNMP MIBs, 34-62 system definition, 34-59 test pattern control, 34-62 transmit group state machine control, 34-61 transmit link state machine control, 34-60 IMMR (internal memory map register), 4-36 Input/output port memory map, 3-9 Instruction field conventions, 1-lxxxviii Instruction queue (IQ), 2-5 Instruction timing overview, 2-26 Instruction unit, 2-5 Integer unit (IU), 2-6 Interrupts ATM interrupt queues, 31-82 RISC timer tables interrupt handling, 14-31 SCC interrupt handling, 20-16 Inverse Multiplexing for ATM (IMA) see IMA, 34-1 J JTAG implementation, 1-5 L L_TESCR1 (local bus transfer error status and control register 1), 4-43 L_TESCR2 (local bus transfer error status and control register 2), 4-44 L_TESCRx (local bus error status and control registers), 11-33 LCL_ACR (local bus arbiter configuration register), 4-31 LCL_ALRH (local bus arbitration high-level register), 4-32 LCL_ALRL (local bus arbitration low-level register), 4-33 LDTEA (SDMA local bus transfer error address register), 19-4 LDTEM (SDMA local bus transfer error MSNUM register), 19-4 Load/store unit (LSU), 2-7 Loopback mode, 15-7 LSDMR (local bus SDRAM mode register), 11-24 LSRT (local bus-assigned SDRAM refresh timer) register, 11-32 LURT (local bus-assigned UPM refresh timer) register, 11-30 M MCCE (MCC event) register, 29-37 MCCFx (MCC configuration registers), 29-33 MCCM (MCC mask) register, 29-37 MDR (memory data register), 11-28 Memory controller address checking, 11-7 address latch enable (ALE), 11-10 address space checking, 11-7 architecture overview, 11-4 atomic bus operation, 11-9 basic architecture, 11-4 basic operation, 11-7 boot chip-select operation, 11-62 controlling the timing of GPL1, GPL2, and CSx, 11-69 CSx timing example, 11-69 delayed read, 11-9 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-13 EDO interface connection, MPC8280 to 60x bus, 11-92 error checking and correction (ECC), 11-8 external master support, 11-102 external support, 11-10 features common to all machines, 11-5 features list, 11-3 general-purpose chip-select machine (GPCM) access termination, external, 11-61 assertion timing, 11-53 common features, 11-5 differences between MPC8xx and MPC8280, 11-63 external access termination, 11-61 implementation differences with UPMs and SDRAM machine, 11-6 interface signals, 11-52 MPC8xx versus MPC8280, 11-63 OE timing, 11-58 overview, 11-51 programmable wait state configuration, 11-58 PSDVAL, 11-58 read access extended hold time, 11-59 relaxed timing, 11-56 SRAM configuration, 11-52 strobe signal behavior, 11-53 terminating external accesses, 11-61 timing configuration, 11-53 write enable deassertion timing, 11-54 GPLn timing example, 11-69 implementation differences between machines, 11-6 machine selection, 11-5 MAR in 60x-compatible mode, 11-77 new features supported, 11-1 overview, 11-1 page hit checking, 11-7 parity byte select (PBSE), 11-10 parity checking, 11-8 parity generation, 11-8 programming model, 11-12 PSDVAL, 11-10, 11-58 register descriptions, 11-12 SDRAM machine (synchronous DRAM machine) address multiplexing, 11-37 bank interleaving, 11-36 BSMA bit, 11-37 commands, JEDEC-standard, 11-35 common features, 11-5 configuration example, 11-48 implementation differences with UPMs and GPCM, 11-6 JEDEC-standard commands, 11-35 MODE-SET command timing, 11-47 overview, 11-33 page mode support, 11-36 parameters activate-to-read/write interval, 11-39 column address to first data out, 11-40 last data in to precharge, 11-41 last data out to precharge, 11-41 overview, 11-38 precharge-to-activate interval, 11-39 refresh recovery interval (RFRC), 11-42 pipeline accesses, 11-36 power-on initialization, 11-35 read/write transactions supported, 11-46 refresh, 11-47 SDAM bit, 11-37 supported configurations, 11-35 TEA generation, 11-8 UPMs (user-programmable machines) access times, handling devices, 11-102 address control bits, 11-77 address multiplexing, 11-77 clock timing, 11-67 common features, 11-5 data sample control, 11-77 data valid, 11-77 differences between MPC8xx and MPC8280, 11-80 DRAM configuration example, 11-79 EDO interface example, 11-92 exception requests, 11-67 hierarchical bus interface example, 11-102 implementation differences with SDRAM machine and GPCM, 11-6 loop control, 11-76 memory access requests, 11-66 memory system interface example, 11-81 MPC8xx versus MPC8280, 11-80 overview, 11-63 programming the UPM, 11-67 RAM array, 11-69 RAM word, 11-70 refresh timer requests, 11-66 register settings, 11-80 requests, 11-65 signal negation, 11-78 signals, 11-63 software requests, 11-67 UPWAIT signal, 11-78 wait mechanism, 11-78 Memory management units (MMUs), 2-8 memory map BRGs,, 3-18 clocks and reset keys,, 3-5 PIP,, 3-13 Memory maps MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-14 Freescale Semiconductor cross-reference guide, 3-1 quick reference guide, 3-1 serial communications controllers (SCCs) HDLC mode, 22-3 serial management controllers (SMCs) GCI mode, 28-31 transparent mode, 28-6 UART mode, 28-6 Microcode revision number, 14-12 Modes 60x bus mode 60x-compatible bus mode, 8-3 address latch enable (ALE), 11-10 data streaming mode, 8-25 extended transfer mode, 8-18 no-pipeline mode, 8-23 one-level pipeline mode, 8-23 single-MPC8280 bus mode, 8-2 ATM controller APC modes, 31-8 external rate mode, 31-6 internal rate mode, 31-6 transmit rate modes, 31-6 BISYNC mode, 23-1 cascaded mode, 18-3 echo mode, 28-1 HDLC mode, 22-1 hunt mode, 21-9 IDMA emulation edge-sensitive mode, 19-14 external request mode, 19-8 level-sensitive mode, 19-14 normal mode, 19-9 loopback mode, 28-1 NMSI mode, synchronization, 24-3 SCC AppleTalk mode, 26-1 serial interface (SI) echo mode, 15-7 serial peripheral interace (SPI) master mode, 39-3 slow go, 18-2 transparent mode overview, 38-1 serial communications controllers (SCCs), 24-1 serial management controllers (SMCs), 28-20 UART mode serial communications controllers (SCCs), 21-1 serial management controllers (SMCs), 28-10 MPTPR (memory refresh timer prescaler register), 11-32 Multi-channel controllers (MCCs) CHAMR HDLC mode, 29-8 transparent mode, 29-13, 29-15 channel extra parameters, 29-28 commands, 29-34 data structure organization, 29-2 exceptions, 29-35 features list, 29-1 global parameters, 29-4, 29-15 HDLC parameters (channel-specific), 29-5 initialization, 29-47 INTMSK, 29-15 MCCE, 29-37 MCCFx, 29-33 MCCM, 29-37 parameters for transparent operation, 29-11 RSTATE, 29-10 RxBD, 29-42 TSTATE, 29-7 TxBD, 29-45 M xMR (machine x mode registers), 11-26 N NMSI (non-multiplexed serial interface) configuration, 16-4 SMC NMSI connection, receive and transmit, 28-2 synchronization in NMSI mode, transparent operation, 24-3 O Operations atomic bus operation, 11-9 digital phase-locked loop (DPLL) operation, 20-21 SMC buffer descriptor, 28-4 transparent operation, NMSI sychronization, 24-3 ORx (option registers), 11-15 P Parallel I/O ports block diagram, 41-6 features, 41-1 overview, 41-1 PDATx, 41-2 PDIRx, 41-3 pin assignments (port A–port D), 41-8–41-20 PODRx, 41-1 port C interrupts, 41-20 port pin functions, 41-6 PPAR, 41-4 programming options, 41-8 PSORx, 41-4 registers, 41-1 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-15 Parameter RAM ATM controller, 31-36 fast communications controllers (FCCs) Fast Ethernet mode, 36-8 HDLC mode, 37-3 overview, 30-12 HDLC mode, 22-3 I2C controller, 40-9 IDMA emulation, 19-16 memory map, 27-12 serial communications controllers (SCCs) base addresses, 20-14 BISYNC mode, 23-3 overview, 20-13 UART mode, 21-3 serial management controllers (SMCs) GCI mode, 28-31 overview, 28-5, 28-30 transparent mode, 28-6 UART mode, 28-6 serial peripheral interface (SPI), 39-10 USB controller, 27-12 parameter RAM,, 14-25 Parity byte select (PBSE), 11-10 PCI bridge, 9-1 60x bus arbitration priority, 9-4 60x bus masters, 9-4 address map, 9-21 address decode flow chart, 9-21, 9-22, 9-23 address translation, 9-24 PCI inbound, 9-25 PCI outbound, 9-26 example, 9-24 programming, 9-24 SIU registers, 9-26 arbitration example, 9-20 burst read example, 9-10 burst write example, 9-11 clocking, 9-3 compact PCI hot swap specification support, 9-4 CompactPCI Hot Swap specification support, 9-5 configuration registers, 9-27 memory-mapped configuration registers, 9-27 discard timer control register (PTCR), 9-32 error address capture register (PCI_EACR), 9-39 error control capture register (PCI_ECCR), 9-40 error control register (ECR), 9-38 error data capture register (PCI_EDCR), 9-40 error mask register (EMR), 9-37 error status register (ESR), 9-35 general purpose control register (GPCR), 9-33 inbound base address registers (PIBARx), 9-42 inbound comparison mask registers (PICMRx), 9-43 inbound translation address registers (PITARx), 9-42 message unit (I2O) registers, 9-30 PCI general control register (PCI_GCR), 9-35 PCI outbound base address registers (POBARx), 9-31 PCI outbound comparison mask registers (POCMRx), 9-31 PCI outbound translation address registers (POTARx), 9-30 PCI bridge, 9-45 BIST control register, 9-53 device ID register, 9-47 general purpose local access base address registers (GPLABARx), 9-54 Hot Swap control status register, 9-61 initializing the PCI configuration registers, 9-64 PCI bus arbiter configuration register, 9-60 PCI bus base class code register, 9-51 PCI bus cache line size register, 9-51 PCI bus capabilities pointer register, 9-56 PCI bus command register, 9-47 PCI bus function register, 9-59 PCI bus internal memory-mapped registers base address register (PIMMRBAR), 9-53 PCI bus interrupt line register, 9-57 PCI bus interrupt pin register, 9-57 PCI bus latency timer register, 9-52 PCI bus MAX LAT, 9-58 PCI bus MIN GNT, 9-58 PCI bus programming interface register, 9-50 PCI bus status register, 9-48 PCI configuration register access from core, 9-62 PCI configuration register access in Big-Endian mode, 9-62, 9-63 PCI Hot Swap register block, 9-61 reader type register, 9-53 revision ID register, 9-49 subclass code register, 9-51 subsystem device ID register, 9-56 subsystem vendor ID register, 9-55 vendor ID register, 9-46 DMA controller, 9-85 block diagram, 9-85 descriptors, 9-95 Big Endian mode, 9-96 Little Endian mode, 9-97 operation, 9-85 byte count registers (DMABCRx), 9-93 current descriptor address registers (DMACDARx), 9-91 destination address registers (DMADARx), 9-93 direct mode, 9-86 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-16 Freescale Semiconductor DMA chaining mode, 9-86 DMA coherency, 9-87 DMA transfer types, 9-87 halt and error conditions, 9-87 mode registers (DMAMRx), 9-88 next descriptor address registers (DMANDARx), 9-94 source address registers (DMASARx), 9-92 status registers (DMASRx), 9-90 error handling, 9-97 interrupt and error signals, 9-97 embedded utilities, 9-100 error reporting, 9-98 illegal register access error, 9-98 parity error (PERR), 9-98 PCI bus error signals, 9-97 PCI interface, 9-98, 9-99, 9-100 system error (SERR), 9-98 in MPC8280, 9-2 initialization, 9-3 interface, 9-5 bus arbitration, 9-19 alogrithm, 9-19 master latency timer, 9-20 parking, 9-19 operation, 9-6 bus commands, 9-6 bus transactions read and write, 9-9 termination, 9-11 error functions, 9-17 parity, 9-17 reporting, 9-18 other bus operations, 9-13 agent mode configuration access, 9-16 data streaming, 9-14 device selection, 9-13 fast back-to-back transactions, 9-14 host mode configuration access, 9-15 interrupt acknowledge, 9-17 special cycle command, 9-16 protocol fundamentals, 9-7 addressing, 9-8 basic transfer control, 9-8 bus driving and turnaround, 9-9 byte enable signals, 9-9 interrupts from, 9-4 message unit (I2O), 9-66 door bell registers, 9-68 inbound (IDR), 9-68 outbound (ODR), 9-68 I20 unit, 9-69 I20 registers, 9-77 inbound FIFO queue port register (IFQPR), 9-77 inbound message interrupt mask register (IMIMR), 9-82 inbound message interrupt status register (IMISR), 9-81 messaging unit control register (MUCR), 9-83 outbound FIFO queue port register (OFQPR), 9-78 outbound message interrupt mask register (OMIMR), 9-80 outbound message interrupt status register (OMISR), 9-79 queue base address register (QBAR), 9-84 inbound FIFOs, 9-70 PCI configuration identification, 9-70 inbound FIFOs Free_FIFO head pointer register (IFHPR), 9-71 Free_FIFO tail pointer register (IFTPR), 9-71 post_FIFO head pointer register (IPHPR), 9-72 post_FIFO tail pointer register (IPTPR), 9-72 message registers, 9-66 inbound message registers (IMRx), 9-66 outbound message registers (OMRx), 9-67 outbound FIFOs, 9-74 free_FIFO head pointer register (OFHPR), 9-74 free_FIFO tail pointer register (OFTPR), 9-74 post_FIFO head pointer register (OPHPR), 9-75 post_FIFO head pointer register (OPTPR), 9-75 PCI parity operation, 9-18 SDMA interface, 9-3 signals, 9-3 single beat read example, 9-10 single beat write example, 9-11 structure, 9-2 target-initiated terminations, 9-12 PDATx (port data) registers, 41-2 PDIRx (port data direction registers), 41-3 PDTEA (SDMA 60x bus transfer error address register), 19-4 PDTEM (SDMA 60x bus transfer error MSNUM register), 19-4 PISCR (periodic interrupt status and control register), 4-47 PITC (periodic interrupt timer count register), 4-48 PITR (periodic interrupt timer register), 4-49 PLL pins,, 10-5 PLPRCR,, 10-7 PODRx (port open-drain registers), 41-1 PORESET,, 6-14 Power consumption FCCs, 30-22 SCCs, 20-25 PPAR (port pin assignment register), 41-4 PPC_ACR (60x bus arbiter configuration register), 4-29 PPC_ALRH (60x bus arbitration high-level register), 4-30 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-17 PPC_ALRL (60x bus arbitration low-level register), 4-31 Programming examples serial communications controllers (SCCs) GSMR (general SCC mode register) AppleTalk mode, 26-4 HDLC bus protocol, 22-22 PSMR (protocol-specific mode register) AppleTalk mode, 26-4 TODR (transmit-on-demand register) AppleTalk mode, 26-4 transparent mode, 24-13 UART mode, 21-22 transparent mode NMSI programming example, 28-29 Promiscuous mode, see Transparent mode Promiscuous operation, 38-1 PSDMR (60x SDRAM mode register), 11-20 PSMR (protocol-specific mode register) AppleTalk mode, 26-4 BISYNC mode, 23-10 Ethernet mode, 25-14 HDLC bus protocol, programming, 22-22 HDLC mode, 22-7 overview, 20-9 transparent mode, 24-8 UART mode, 21-12 PSMR,, 36-20 PSMR, Ethernet mode register,, 36-20 PSORx (port special options registers), 41-4 PSRT (60x bus-assigned SDRAM refresh timer) register, 11-31 PURT (60x bus-assigned UPM refresh timer) register, 11-30 R RAM word, 11-70 RCCR (RISC controller configuration register), 14-10 Registers AppleTalk mode GSMR, 26-4 PSMR, 26-4 TODR, 26-4 ATM controller FCCE, 31-91 FCCM, 31-91 FPSMR (FCC protocol-specific mode register, 31-88 GFMR register, 31-88 BISYNC mode BDLE, 23-8 BSYNC, 23-7 PSMR, 23-10 SCCE, 23-15 SCCM, 23-15 SCCS, 23-16 communications processor (CP) RCCR, 14-10 RTSCR, 14-11 RTSR, 14-12 communications processor module (CPM) CPCR, 14-13 parallel I/O ports PDATx, 41-2 PDIRx, 41-3 PODRx, 41-1 PPAR, 41-4 PSORx, 41-4 CPM multiplexing CMXFCR, 16-13 CMXSCR, 16-16 CMXSI1CR, 16-12 CMXSI2CR, 16-12 CMXSMR, 16-19 CMXUAR, 16-7 DSR overview, 20-9 UART mode, 21-10 fast communications controller (FCC) FCCE, 37-14 FCCS, 37-16 FPSMR, 37-7 fast communications controllers (FCCs) Fast Ethernet mode FCCE, 36-21 FCCM, 36-21 FPSMR, 36-19 HDLC mode FCCM, 37-14 overview FCCEx, 30-15 FCCMx, 30-15 FCCSx, 30-15 FCRx, 30-14 FDSRx, 30-8 FPSMRx, 30-8 FTODRx, 30-9 GFMRx, 30-3 interrupts, 30-14 timing control, 30-17 GSMR AppleTalk mode, 26-4 overview, 20-3 HDLC mode PSMR, 22-7 SCCE, 22-12 SCCM, 22-12 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-18 Freescale Semiconductor SCCS, 22-14 I2C controller I2ADD, 40-6 I2BRG, 40-7 I2CER, 40-7 I2CMR, 40-7 I2COM, 40-8 I2MOD, 40-6 IDMA emulation DCM, 19-18 IDMR, 19-23 IDSR, 19-23 IEEE 1149.1 test access port boundary scan registers, 1-3 instruction register, 1-5 IMA FCC registers, 34-26 FPSMRx, 34-26 FTIRRx, 34-26 group tables IGRCNTL, 34-38 IGRSTATE, 34-39 IGTCNTL, 34-31 IGTSTATE, 34-32 IRGFS, 34-39 link tables ILRCNTL, 34-46 ILRSTATE, 34-47 ILTCNTL, 34-42 ILTSTATE, 34-43 ITINTSTAT, 34-43 memory controller 60x bus control registers, 11-12 BRn, 11-13 GPCM mode ORx, 11-17 L_TESCRx, 11-33 MPTPR, 11-32 MxMR, 11-26 SDRAM mode LSDMR, 11-24 LSRT, 11-32 ORx, 11-15 PSDMR, 11-20 PSRT, 11-31 TESCRx, 11-33 UPM mode LURT, 11-30 MDR, 11-28 ORx, 11-19 PURT, 11-30 register settings, 11-80 multi-channel controllers (MCCs) CHAMR, 29-8 CHAMR, transparent mode, 29-13, 29-15 MCCE, 29-37 MCCFx, 29-33 MCCM, 29-37 RSTATE, 29-10 TSTATE, 29-7 OCASSR, 32-36 PCI bridge BIST control, 9-53 bus arbiter configuration, 9-60 bus base class code register, 9-51 bus cache line size, 9-51 bus capabilities pointer, 9-56 bus function, 9-59 bus interrupt line, 9-57 bus interrupt pin, 9-57 bus latency timer, 9-52 bus MAX LAT, 9-58 bus MIN GNT, 9-58 bus programming interface register, 9-50 configuration registers, 9-45 device ID register, 9-47 discard timer control register (PTCR), 9-32 DMA registers DMA byte count registers (DMABCRx), 9-93 DMA current descriptor address registers (DMACDARx), 9-91 DMA destination address registers (DMADARx), 9-93 DMA mode registers (DMAMRx), 9-88 DMA next descriptor address registers (DMANDARx), 9-94 DMA source address registers (DMASARx), 9-92 DMA status registers (DMASRx), 9-90 door bell registers, 9-68 inbound (IDR), 9-68 outbound (ODR), 9-68 error address capture register (PCI_EACR), 9-39 error control capture register (PCI_ECCR), 9-40 error control register (ECR), 9-38 error data capture register (PCI_EDCR), 9-40 error mask register (EMR), 9-37 error status register (ESR), 9-35 general control register (PCI_GCR), 9-35 general purpose control register (GPCR), 9-33 general purpose local access base address registers (GPLABARx), 9-54 Hot Swap control status, 9-61 Hot Swap register block, 9-61 I20 unit MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-19 I2O registers inbound message interrupt mask register (IMIMR), 9-82 inbound FIFOs free_FIFO head pointer register (IFHPR), 9-71 free_FIFO tail pointer register (IFTPR), 9-71 I2O unit I2O registers inbound FIFO queue port register (IFQPR), 9-77 inbound message interrupt status register (IMISR), 9-81 messaging unit control register (MUCR), 9-83 outbound FIFO queue port register (OFQPR), 9-78 outbound message interrupt mask register (OMIMR), 9-80 outbound message interrupt status register (OMISR), 9-79 queue base address register (QBAR), 9-84 inbound FIFOs post_FIFL tail pointer register, 9-72 post_FIFO head pointer register (IPHPR), 9-72 outbound FIFOs free_FIFO tail pointer register (OFTPR), 9-74 post_FIFO head pointer register (OPHPR), 9-75 post_FIFO tail pointer register (OPTPR), 9-75 inbound base address registers (PIBARx), 9-42 inbound comparison mask registers (PICMRx), 9-43 inbound translation address registers (PITARx), 9-42 message registers, 9-66 inbound (IMRx), 9-66 outbound (OMRx), 9-67 outbound base address registers (POBARx), 9-31 outbound comparison mask registers (POCMRx), 9-31 outbound translation address registers (POTARx), 9-30 PCI bus command register, 9-47 PCI bus internal memory-mapped registers bass address (PIMMRBAR), 9-53 PCI bus status register, 9-48 reader type, 9-53 revision ID register, 9-49 subclass code register, 9-51 subsystem device ID, 9-56 subsystem vendor ID, 9-55 vendor ID register, 9-46 PCI-bridge I2O unit outbound FIFOs free_FIFO head pointer register (OFHPR), 9-74 PowerPC supervisor-level summary, A-1, A-3 user-level summary, A-1 PSMR AppleTalk mode, 26-4 BISYNC mode, 23-10 Ethernet mode, 25-14 overview, 20-9 transparent mode, 24-8 UART mode, 21-12 quick reference guide, A-1 reset mode, 5-5 reset status, 5-4 RFCR, 20-15 RISC timer tables RTMR, 14-29 TM_CMD, 14-29 SCCE BISYNC mode, 23-15 Ethernet mode, 25-20 transparent mode, 24-12 UART mode, 21-19 SCCM BISYNC mode, 23-15 Ethernet mode, 25-20 transparent mode, 24-12 UART mode, 21-19 SCCS BISYNC mode, 23-16 transparent mode, 24-13 UART mode, 21-21 SDMA channels LDTEA, 19-4 LDTEM, 19-4 PDTEA, 19-4 PDTEM, 19-4 SDMR, 19-4 SDSR, 19-3 serial interface (SI) SIxCMDR, 15-24 SIxGMR, 15-17 SIxMR, 15-17 SIxRSR, 15-23 SIxSTR, 15-25 serial management controllers GCI mode SMCE, 28-35 SMCM, 28-35 SMCMRs, 28-2 transparent mode SMCE, 28-28 SMCM, 28-28 UART mode RxBD, 28-13 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-20 Freescale Semiconductor SMCE, 28-18 SMCM, 28-18 TxBD, 28-17 serial management controllers (SMCs) GCI mode RxBD, 28-34 serial management controllers(SMCs) GCI mode TxBD, 28-34 serial peripheral interface (SPI) SPCOM, 39-10 SPIE, 39-9 SPIM, 39-9 SPMODE, 39-6 system interface unit (SIU) BCR, 4-26 IMMR, 4-36 L_TESCR1, 4-43 L_TESCR2, 4-44 LCL_ACR, 4-31 LCL_ALRH, 4-32 LCL_ALRL, 4-33 PISCR, 4-47 PITC, 4-48 PITR, 4-49 PPC_ACR, 4-29 PPC_ALRH, 4-30 PPC_ALRL, 4-31 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-25 SIMR_H, 4-22 SIMR_L, 4-23 SIPNR_H, 4-21 SIPNR_L, 4-22 SIPRR, 4-18 SIUMCR, 4-33 SIVEC, 4-24 SWR, 4-7 SWSR, 4-38 SYPCR, 4-37 TESCR1, 4-40 TESCR2, 4-42 TMCNT, 4-45 TMCNTAL, 4-46 TMCNTSC, 4-44 TC layer, 35-7 CDSMRx, 35-9 general registers, 35-11 TCGER, 35-11 TCGSR, 35-11 TCERx, 35-10 TCMODEx, 35-7 TCMRx, 35-11 TFCR, 20-15 timers TCN, 18-7 TCR, 18-7 TER, 18-7 TGCR, 18-3 TMR, 18-5 TRR, 18-6 TODR AppleTalk mode, 26-4 overview, 20-10 TOSEQ, 21-9 transparent mode PSMR, 24-8 SCCE, 24-12 SCCM, 24-12 SCCS, 24-13 UART mode DSR, 21-10 PSMR, 21-12 SCCE, 21-19 SCCM, 21-19 SCCS, 21-21 TOSEQ, 21-9 USB controller CPCR (CPM command register), 27-32 RFCR (receive function code register), 27-16 TFCR (transmit function code register), 27-16 USADR (USB slave address register), 27-17 USBER (USB event register), 27-20 USBMR (USB mask register), 27-21 USBS (USB status register), 27-21 USCOM (USB command register), 27-19 USEPn (USB endpoint registers 1–4), 27-18 USMOD (USB mode register), 27-17 registers Ethernet mode,, 36-20 transfer error status,, 4-43, 4-44 Reset actions, 5-2 causes, 5-1 external HRESET flow, 5-3 external SRESET flow, 5-3 power-on reset flow, 5-2 receiver reset sequence, SCC, 20-25 resetting registers and parameters for all channels, 14-14 software watchdog reset, 5-1 transmitter reset sequence, SCC, 20-25 RFCR (Rx buffer function code register) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-21 overview, 20-15 RISC microcontroller, seeCommunications processor (CP) RISC timer tables CP loading tracking, 14-32 features list, 14-27 initializing RISC timer tables, 14-30 interrupt handling, 14-31 overview, 14-27 parameter RAM, 14-27 RAM usage, 14-28 RTMR, 14-29 scan algorithm, 14-31 SET TIMER command, 14-30 table entries, 14-29 timer counts, comparing, 14-32 TM_CMD, 14-29 tracking CP loading, 14-32 RMR (reset mode) register, 5-5 RSR (reset status) register, 5-4 RSTATE (internal receiver state) register, 29-10 RTMR (RISC timer mask register), 14-29 RTSCR (RISC time-stamp control register), 14-11 RTSR (RISC time-stamp register), 14-12 S SCC memory map, 3-19 SCCE (SCC event) register BISYNC mode, 23-15 HDLC mode, 22-12 transparent mode, 24-12 UART mode, 21-19 SCCE register Ethernet mode, 25-20 SCCM (SCC mask) register BISYNC mode, 23-15 HDLC mode, 22-12 transparent mode, 24-12 UART mode, 21-19 SCCM register Ethernet mode, 25-20 SCCS (SCC status) register BISYNC mode, 23-16 HDLC mode, 22-14 transparent mode, 24-13 UART mode, 21-21 SCIT programming, 15-33 SCPRR_H (CPM high interrupt priority register), 4-19 SCPRR_L (CPM low interrupt priority register), 4-20 SDMA channels bus arbitration, 19-2 bus transfers, 19-2 LDTEA, 19-4 LDTEM, 19-4 overview, 19-1 PDTEA, 19-4 PDTEM, 19-4 programming model, 19-3 registers, 19-3 SDMR, 19-4 SDSR, 19-3 SDMR (SDMA mask register), 19-4 SDRAM interface, see SDRAM machine SDSR (SDMA status register), 19-3 Serial communications controllers (SCCs) AppleTalk mode connecting to AppleTalk, 26-2 operating LocalTalk frame, 26-1 overview, 26-1 programming example, 22-22, 26-4 programming the controller, 26-3 BISYNC mode commands, 23-4 control character recognition, 23-5 error handling, 23-9 frame reception, 23-3 frame transmission, 23-2 overview, 23-1 parameter RAM, 23-3 programming example, 23-18 programming the controller, 23-17 receiving synchronization sequence, 23-9 RxBD, 23-12 sending synchronization sequence, 23-9 TxBD, 23-14 Ethernet mode address recognition, 25-11 collision handling, 25-12 commands, 25-9 connecting to Ethernet, 25-4 error handling, 25-13 frame reception, 25-6 hash table algorithm, 25-12 loopback, 25-13 overview, 25-1 programming example, 25-22 programming the controller, 25-9 receive buffer, 25-16 transmit buffer, 25-18 HDLC mode accessing the bus, 22-18 bus controller, 22-16 collision detection, 22-16, 22-19 commands, 22-5 delayed RTS mode, 22-20 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-22 Freescale Semiconductor error handling, 22-5 features list, 22-1 GSMR, HDLC bus protocol programming, 22-22 interrupts, 22-13 memory map, 22-3 multi-master bus configuration, 22-17 overview, 22-1 parameter RAM, 22-3 performance, increasing, 22-19 programming example, 22-14, 22-22 programming the controller, 22-4 PSMR, 22-7 RxBD, 22-8 single-master bus configuration, 22-18 TxBD, 22-11 using the TSA, 22-21 overview buffer descriptors, 20-10 controlling SCC timing, 20-17 DPLL operation, 20-21 features, 20-2 initialization, 20-16 interrupt handling, 20-16 parameter RAM, 20-13 reconfiguration, 20-24 reset sequence, 20-25 switching protocols, 20-25 transparent mode achieving synchronization, 24-3 commands, 24-7 DSR receiver SYNC pattern lengths, 24-3 end of frame detection, 24-6 error handling, 24-8 frame reception, 24-2 frame transmission, 24-2 inherent synchronization, 24-6 in-line synchronization, 24-6 overview, 24-1 programming example, 24-13 RxBD, 24-9 synchronization signals, 24-3 synchronization, user-controlled, 24-5 transmit synchronization, 24-3 TxBD, 24-10 UART mode commands, 21-6 control character insertion, 21-9 data handling, character and message-based, 21-5 error reporting, 21-5 features list, 21-2 fractional stop bits, 21-10 handling errors, 21-11 hunt mode, 21-9 normal asynchronous mode, 21-2 overview, 21-1 parameter RAM, 21-3 programming example, 21-22 RxBD, 21-14 S-records loader application, 21-23 status reporting, 21-5 synchronous mode, 21-3 TxBD, 21-18 Serial configuration, 14-3 Serial interface (SI) enabling connections, 15-7 features, 15-3 GCI support, 15-31 IDL bus implementation programming the IDL, 15-29 IDL interface support, 15-25 overview, 15-4 programming GCI, 15-33 programming RAM entries, 15-10 registers, 15-17 see also CPM multiplexing logic (CMX) SI RAM, 15-8 Serial management controllers (SMCs) buffer descriptors, overview, 28-4 disabling SMCs on-the-fly, 28-8 disabling the receiver, 28-9 disabling the transmitter, 28-9 enabling the receiver, 28-9 enabling the transmitter, 28-9 features list, 28-2 GCI mode C/I channel handling the SMC, 28-32 reception process, 28-32 RxBD, 28-34 transmission process, 28-32 TxBD, 28-34 commands, 28-33 monitor channel reception process, 28-31 RxBD, 28-33 transmission process, 28-31 TxBD, 28-33 overview, 28-30 parameter RAM, 28-31 memory structure, 28-5 mode selection, 28-2 NMSI connection, receive and transmit, 28-2 parameter RAM GCI mode, 28-31 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-23 overview, 28-5, 28-30 transparent mode, 28-6 UART mode, 28-6 power, saving, 28-10 programming the controller, 28-11 protocol switching, 28-9 reinitializing the receiver, 28-9 reinitializing the transmitter, 28-9 selecting modes, 28-2 sending a break, 28-12 sending a preamble, 28-13 switching protocols, 28-9 transparent mode features list, 28-20 overview, 28-20 parameter RAM, 28-6 reception process, 28-21 RxBD, 28-26 TxBD, 28-27 UART mode character mode, 28-11 commands, 28-12 data handling, 28-11 error handling, 28-13 features list, 28-11 features not supported by SMCs, 28-10 frame format, 28-10 message-oriented mode, 28-11 overview, 28-10 parameter RAM, 28-6 programming example, 28-19 reception process, 28-11 RxBD, 28-13 transmission process, 28-11 TxBD, 28-17 Serial mode parameter RAM configuration, 34-27 Serial peripheral interface (SPI) block diagram, 39-1 clocking and pin functions, 39-2 commands, 39-12 configuring the SPI, 39-2 features list, 39-1 interrupt handling, 39-18 master mode, 39-3 maximum receive buffer length (MRBLR), 39-11 multi-master operation, 39-4 parameter RAM, 39-10 programming example master, 39-16 slave, 39-17 programming model, 39-6 RxBD, 39-14 slave mode, 39-4 SPCOM, 39-10 SPIE, 39-9 SPIM, 39-9 SPMODE, 39-6 TxBD, 39-15 SI memory map, 3-24 SI memory map,, 3-15, 3-16, 3-17, 3-18 SI RAM programming example, 15-14 SI,, 1-lxxxi SICR (SIU interrupt configuration register), 4-17 SICR,, 16-7 SIEXR (SIU external interrupt control register), 4-25 Signals 60x bus TBST, 8-12 TCn, 8-12 TSIZn, 8-12 TTn, 8-9 byte-select signals, 11-75 chip-select signals, 11-74 general-purpose signals, 11-76 IDMA emulation DACKx, 19-13 DONEx, 19-14 DREQx, 19-13 memory controller byte-select signals, 11-10 EAMUX, 11-42 PSDVAL, 11-10, 11-58 SDRAM interface signals, 11-33 UPM interface signals, 11-63 UPM signal negation, 11-78 UPWAIT, 11-78 overview, 6-2 SPISEL, 27-24, 27-25 signals, external description EXTCLK,, 6-15 SIPMR_H (SIU high interrupt mask register), 4-22 SIPMR_L (SIU low interrupt mask register), 4-23 SIPNR_H (SIU high interrupt pending register), 4-21 SIPNR_L (SIU low interrupt pending register), 4-22 SIPRR (SIU interrupt priority register), 4-18 SIU memory map,, 3-2 SIUMCR (SIU module configuration register), 4-33 SIVEC (SIU interrupt vector register), 4-24 SMC memory map, 3-23 SMC,, 16-1 SMCE (SMC event) register GCI mode, 28-35 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-24 Freescale Semiconductor transparent mode, 28-28 UART mode, 28-18 SMCM (SMC mask) register GCI mode, 28-35 transparent mode, 28-28 UART mode, 28-18 SMCMRs (SMC mode registers), 28-2 SPCOM, 27-19 SPCOM (SPI command) register, 39-10 SPI clocking and pin functions, 27-2 master mode, 27-5, 27-8 parameter RAM memory map, 27-12 programming model, 27-16 slave, 27-2 SPI block diagram, 27-5, 27-8 SPISEL, 27-24, 27-25 SPI block diagram, 27-5, 27-8 SPI buffer descriptor ring, 27-22 SPI memory map, 3-24 SPI receive buffer descriptor, 27-24 SPIE, 27-20 SPIE (SPI event) register, 39-9 SPIM (SPI mask) register, 39-9 SPMODE (SPI mode) register, 39-6 SWR (software watchdog register), 4-7 SWSR (software service register), 4-38 SYPCR (system protection control register), 4-37 System integration timers memory map, 3-5 System interface unit (SIU) 60x bus monitor function, 4-2 BCR, 4-26 block diagram, 4-1 bus monitor, 4-3 clocks, 4-3 configuration functions, 4-2 configuration/protection logic block diagram, 4-3 encoding the interrupt vector, 4-14 FCC relative priority, 4-12 highest priority interrupt, 4-13 IMMR, 4-36 interrupt controller features list, 4-7 interrupt source priorities, 4-9 interrupt vector calculation, 4-14 interrupt vector encoding, 4-14 interrupt vector generation, 4-14 L_TESCR1, 4-43 L_TESCR2, 4-44 LCL_ACR, 4-31 LCL_ALRH, 4-32 LCL_ALRL, 4-33 local bus monitor function, 4-2 masking interrupt sources, 4-13 MCC relative priority, 4-12 periodic interrupt timer (PIT), 4-5 periodic interrupt timer (PIT) function, 4-2 pin multiplexing, 4-51 PISCR, 4-47 PITC, 4-48 PITR, 4-49 port C interrupts, 4-16 PPC_ACR, 4-29 PPC_ALRH, 4-30 PPC_ALRL, 4-31 programming model, 4-17 registers, 4-17 SCC relative priority, 4-12 SCPRR_H, 4-19 SCPRR_L, 4-20 SICR, 4-17 SIEXR, 4-25 signal multiplexing, 4-51 SIMR_H, 4-22, 4-23 SIPNR_H, 4-21 SIPNR_L, 4-22 SIPRR, 4-18 SIUMCR, 4-33 SIVEC, 4-24 software watchdog timer, 4-6 SWR, 4-7 SWSR, 4-38 SYPCR, 4-37 system protection, 4-2 TESCR1, 4-40 TESCR2, 4-42 time counter (TMCNT) function, 4-2 overview, 4-4 timers, 4-3 TMCNT, 4-45 TMCNTAL, 4-46 TMCNTSC, 4-44 system interface unit,, 19-2 System register unit (SRU), 2-7 T TBST (transfer burst) signal, 8-12 TC layer block diagram, 35-4 cell counters, 35-12 corrected, TC_CCCx, 35-12 errored, TC_ECCx, 35-12 filtered, TC_FCCx, 35-13 IDLE, TC_ICCx, 35-12 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-25 received, TC_RCCx, 35-12 transmitted, TC_TCCx, 35-12 features, 35-1 functionality, 35-3 ATM cell functions 2-cell FIFO, 35-6 receive, 35-4 transmit, 35-6 UTOPIA interface receive, 35-7 transmit, 35-7 implementation example, 35-15 operating at higher frequencies, 35-16 programming a T1 application, 35-16 step 1, 35-17 step 2, 35-17 step 3, 35-17 step 4, 35-17 step 5, 35-17 step 6, 35-18 step 7, 35-18 programming and operating the TC layer, 35-13 programming FCC2, 35-13 programming mode, 35-7 signals, 35-7 TCN (timer counter registers), 18-7 TCn (transfer code) signals, 8-12 TCR (timer capture registers), 18-7 TDM,, 16-1 TER (timer event registers), 18-7 Terminology conventions, 1-lxxxvii TESCRx (60x bus error status and control registers), 4-40, 11-33 TFCR (Tx buffer function code register) overview, 20-15 TGCR (timer global configuration registers), 18-3 Timers block diagram, 18-1 bus monitoring, 18-3 cascaded mode block diagram, 18-3 features, 18-1 general-purpose units, 18-2 pulse measurement, 18-3 Time-slot assigner connecting to the TSA, 15-7 Time-slot assigner (TSA) synchronization in transparent mode, 24-6 Timing SCC timing, controlling, 20-17 TM_CMD (RISC timer command) register, 14-29 TMCNT (time counter register), 4-45 TMCNTAL (time counter alarm register), 4-46 TMCNTSC (time counter status and control register), 4-44 TMR (timer mode registers), 18-5 TODR (transmit-on-demand register) AppleTalk mode, 26-4 overview, 20-10 TOSEQ (transmit out-of-sequence) register, 21-9 Transmission convergence (TC) layer, 35-1 Transparent mode achieving synchronization, 24-3 commands, 24-7 DSR receiver SYNC pattern lengths, 24-3 end of frame detection, 24-6 error handling, 24-8 fast communications controllers (FCCs) features list, 38-1 receive operation, 38-2 synchronization achieving, 38-2 example, 38-3 external signals, 38-3 in-line pattern, 38-2 transmit operation, 38-2 frame reception, 24-2 frame transmission, 24-2 inherent synchronization, 24-6 in-line synchronization, 24-6 overview, 24-1 programming example, 24-13 RxBD, 24-9 serial management controllers (SMCs) features list, 28-20 overview, 28-20 parameter RAM, 28-6 reception process, 28-21 synchronization signals, 24-3 synchronization, user-controlled, 24-5 transmit synchronization, 24-3 TxBD, 24-10 TRR (timer reference registers), 18-6 TSIZn (transfer size) signals, 8-12 TSTATE (internal transmitter state) register, 29-7 TTn (transfer type) signals, 8-9 U UART mode commands, 21-6 control character insertion, 21-9 data handling, character and message-based, 21-5 error reporting, 21-5 features list, 21-2 fractional stop bits, 21-10 handling errors, 21-11 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-26 Freescale Semiconductor hunt mode, 21-9 normal asynchronous mode, 21-2 overview, 21-1 parameter RAM, 21-3 programming example, 21-22 RxBD, 21-14 serial management controllers character mode, 28-11 commands, 28-12 data handling, 28-11 error handling, 28-13 features list, 28-11 features not supported by SMCs, 28-10 frame format, 28-10 message-oriented mode, 28-11 overview, 28-10 parameter RAM, 28-6 programming example, 28-19 reception process, 28-11 RxBD, 28-13 transmission process, 28-11 TxBD, 28-17 S-records loader application, 21-23 status reporting, 21-5 synchronous mode, 21-3 TxBD, 21-18 Universal serial bus (USB) controller buffer descriptor ring, 27-22 clocking and pin functions, 27-2 commands CP commands, 27-32 RESTART Tx command, 27-33 STOP Tx command, 27-33 enabling, 27-1 endpoint parameter block, 27-13 EPxPTR, 27-13 error handling, 27-33 errors transmission errors, 27-33 features, 27-2 FRAME_N, 27-15 function mode, 27-4 transmit buffer descriptor (Tx BD), 27-26 transmit/receive, 27-5 host mode, 27-7 SOF transmission, 27-12 transmit buffer descriptor (Tx BD), 27-28 transmit/receive, 27-8 limitations, unsupported tasks, 27-2 overview, 27-1 parameter RAM, 27-12 memory map, 27-12 programming model, 27-16 receive buffer descriptor (Rx BD), 27-24 registers RFCR (receive function code register), 27-16 TFCR (transmit function code register), 27-16 USADR (USB slave address register), 27-17 USBER (USB slave address register), 27-20 USBMR (USB mask register), 27-21 USBS (USB status register), 27-21 USCOM (USB command register), 27-19 USEPn (USB endpoint registers 1–4), 27-18 USMOD (USB mode register), 27-17 tokens, 27-6, 27-10 UPMs (user-programmable machines) access times, handling devices, 11-102 address control bits, 11-77 address mulitplexing, 11-77 clock timing, 11-67 data sample control, 11-77 data valid, 11-77 differences between MPC8xx and MPC8280, 11-80 DRAM configuration example, 11-79 EDO interface example, 11-92 exception requests, 11-67 hierarchical bus interface example, 11-102 implementation differences with SDRAM machine and GPCM, 11-6 loop control, 11-76 memory access requests, 11-66 memory system interface example, 11-81 MPC8xx versus MPC8280, 11-80 overview, 11-63 programming the UPM, 11-67 RAM array, 11-69 RAM word, 11-70 refresh timer requests, 11-66 register settings, 11-80 requests, 11-65 signal negation, 11-78 software requests, 11-67 UPWAIT signal, 11-78 wait mechanism, 11-78 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor Index-27 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Index-28 Freescale Semiconductor Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA) I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I 1 2 3 II 4 5 III 6 7 8 9 10 11 12 13 IV 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Part I—Overview Overview G2_LE Core Memory Map Part II—Configuration and Reset System Interface Unit (SIU) Reset Part III—The Hardware Interface External Signals 60x Signals The 60x Bus PCI Bridge Clocks and Power Control Memory Controller Secondary (L2) Cache Support IEEE 1149.1 Test Access Port Part IV—Communications Processor Module Communications Processor Module Overview Serial Interface with Time-Slot Assigner CPM Multiplexing Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation Serial Communications Controllers (SCCs) SCC UART Mode SCC HDLC Mode SCC BISYNC Mode SCC Transparent Mode SCC Ethernet Mode SCC AppleTalk Mode Universal Serial Bus Controller Serial Management Controllers (SMCs) Multi-Channel Controllers (MCCs) Fast Communications Controllers (FCCs) ATM Controller and AAL0, AAL1, and AAL5 ATM AAL1 Circuit Emulation Service ATM AAL2 Inverse Multiplexing for ATM (IMA) ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index 35 36 37 38 39 40 41 A B GLO IND 35 36 37 38 39 40 41 A B GLO IND ATM Transmission Convergence Layer Fast Ethernet Controller FCC HDLC Controller FCC Transparent Controller Serial Peripheral Interface (SPI) I2C Controller Parallel I/O Ports Register Quick Reference Guide Revision History Glossary Index