Freescale Semiconductor
Technical Data
Document Number: MPC8272EC Rev. 2, 12/2008
MPC8272 PowerQUICC II™ Family Hardware Specifications
This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC8272 family of devices—the MPC8272, the MPC8248, the MPC8271, and the MPC8247. These devices are .13µm (HiP7) members of the PowerQUICC II™ family of integrated communications processors. They include on a single chip a 32-bit PowerPC™core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set; a modified communications processor module (CPM); and an integrated security engine (SEC) for encryption (the MPC8272 and the MPC8248 only). All four devices are collectively referred to throughout this hardware specification as “the MPC8272” unless otherwise noted.
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 12 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 16 Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 25 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 57 Document Revision History . . . . . . . . . . . . . . . . . . . 57
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Overview
1
Overview
Table 1. MPC8272 PowerQUICC II Family Functionality
Devices Functionality Package 1 Serial communications controllers (SCCs) QUICC multi-channel controller (QMC) Fast communication controllers (FCCs) I-Cache (Kbyte) D-Cache (Kbyte) Ethernet (10/100) UTOPIA II Ports Multi-channel controllers (MCCs) PCI bridge Transmission convergence (TC) layer Inverse multiplexing for ATM (IMA) Universal serial bus (USB) 2.0 full/low rate Security engine (SEC)
1
Table 1 shows the functionality supported by each device in the MPC8272 family.
MPC8272
MPC8248
MPC8271
MPC8247
516 PBGA 3 Yes 2 16 16 2 1 0 Yes — — 1 Yes 3 Yes 2 16 16 2 0 0 Yes — — 1 Yes 3 Yes 2 16 16 2 1 0 Yes — — 1 — 3 Yes 2 16 16 2 0 0 Yes — — 1 —
Refer to Table 2.
Devices in the MPC8272 family are available in two packages—the VR or ZQ package—as shown in Table 2. For package ordering information, refer to Section 10, “Ordering Information.”
Table 2. MPC8272 PowerQUICC II Device Packages
Code (Package) VR (516 PBGA—Lead free) MPC8272VR MPC8248VR Device MPC8271VR MPC8247VR MPC8271ZQ MPC8247ZQ ZQ (516 PBGA—Lead spheres) MPC8272ZQ MPC8248ZQ
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 2 Freescale Semiconductor
Overview
Figure 1 shows the block diagram of the MPC8272.
16 Kbytes I-Cache Security (SEC)1 I-MMU G2_LE Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge Memory Controller Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators 4 KB Interrupt Instruction Controller RAM 16 KB Data RAM Clock Counter Serial DMA Virtual IDMAs System Functions 60x Bus
PCI Bus
32 bits, up to 66 MHz
32-bit RISC Microcontroller and Program ROM
FCC1
FCC2
SCC1
SCC3
SCC4
SMC1
SMC2
SPI
I2C
USB 2.0
Time Slot Assigner Serial interface Serial Interface
2 TDM Ports
2 MII/RMII Ports
1 8-bit Utopia Port2
Non-Multiplexed I/O
Note 1 MPC8272/8248 only 2 MPC8272/8271 only
Figure 1. Block Diagram
1.1
Features
The major features of the MPC8272 are as follows: • Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 266-400 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface — Supports bus snooping for cache coherency
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 3
Overview
• • •
•
•
•
•
•
— Floating-point unit (FPU) supports floating-point arithmetic — Support for cache locking Low-power consumption Separate power supply for internal logic (1.5 V) and for I/O (3.3 V) Separate PLLs for G2_LE core and for the communications processor module (CPM) — G2_LE core and CPM can run at different frequencies for power/performance optimization — Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 7:1, and 8:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ,and 8:1 ratios 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs—up to two external masters — Supports single transfers and burst transfers — 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge — Programmable host bridge and agent — 32-bit data bus, 66 MHz, 3.3 V — Synchronous and asynchronous 60x and PCI clock modes — All internal address space available to external PCI host — DMA for memory block transfers — PCI-to-60x address remapping System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE 1149.1 JTAG test access port Eight bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals — Byte write enables — 32-bit address decodes with programmable bank size — Three user programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine — Byte selects for 64-bit bus width (60x) — Dedicated interface logic for SDRAM Disable CPU mode
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Overview
•
•
•
Integrated security engine (SEC) (MPC8272 and MPC8248 only) — Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications peripherals — Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.) Universal serial bus (USB) controller — Supports USB 2.0 full/low rate compatible — USB host mode – Supports control, bulk, interrupt, and isochronous data transfers – CRC16 generation and checking – NRZI encoding/decoding with bit stuffing – Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. – Flexible data buffers with multiple buffers per frame – Supports local loopback mode for diagnostics (12 Mbps only) — Supports USB slave mode – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers – CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate – Flexible data buffers with multiple buffers per frame – Automatic retransmission upon transmit error — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Two fast communication controllers (FCCs) supporting the following protocols: – 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) – Transparent – HDLC—up to T3 rates (clear channel) – One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155 Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 64-K external connections — Three serial communications controllers (SCCs) identical to those on the MPC860 supporting the digital portions of the following protocols:
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2
Freescale Semiconductor
5
Overview
•
Ethernet/IEEE 802.3 CDMA/CS HDLC/SDLC and HDLC bus Universal asynchronous receiver transmitter (UART) Synchronous UART Binary synchronous (BiSync) communications Transparent QUICC multichannel controller (QMC) up to 64 channels • Independent transmit and receive routing, frame synchronization. • Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM highways • Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN basic rate, ISDN primary rate, and user defined. • Subchanneling on each time slot. • Independent transmit and receive routing, frame synchronization and clocking • Concatenation of any not necessarily consecutive time slots to channels independently for Rx/Tx • Supports H1,H11, and H12 channels • Allows dynamic allocation of channels – SCC3 in NMSI mode is not usable when USB is enabled. — Two serial management controllers (SMCs), identical to those of the MPC860 – Provides management for BRI devices as general-circuit interface (GCI) controllers in time-division-multiplexed (TDM) channels – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One I2C controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to two TDM interfaces – Supports one group of two TDM channels – 1024 bytes of SI RAM — Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC, SCC, SMC, and USB serial channels — Four independent 16-bit timers that can be interconnected as two 32-bit timers PCI bridge — PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz — On-chip arbitration — Support for PCI to 60x memory and 60x memory to PCI streaming — PCI host bridge or peripheral capabilities
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2
– – – – – – –
6
Freescale Semiconductor
Operating Conditions
— Includes four DMA channels for the following transfers: – PCI-to-60x to 60x-to-PCI – 60x-to-PCI to PCI-to-60x – PCI-to-60x to PCI-to-60x – 60x-to-PCI to 60x-to-PCI — Includes the configuration registers required by the PCI standard (which are automatically loaded from the EPROM to configure the MPC8272) and message and doorbell registers — Supports the I2O standard — Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) — Support for 66-MHz, 3.3-V specification — 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port
2
Operating Conditions
Table 3. Absolute Maximum Ratings 1
Rating Core supply voltage 2 PLL supply voltage2 I/O supply voltage 3 Input voltage 4 Junction temperature Storage temperature range
1
Table 3 shows the maximum electrical ratings.
Symbol VDD VCCSYN VDDH VIN Tj TSTG
Value –0.3 – 2.25 –0.3 – 2.25 –0.3 – 4.0 GND(–0.3) – 3.6 120 (–55) – (+150)
Unit V V V V °C °C
Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms. 3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 4 lists recommended operational voltage conditions.
Table 4. Recommended Operating Conditions 1
Rating Core supply voltage PLL supply voltage I/O supply voltage Symbol VDD VCCSYN VDDH Value 1.425 – 1.575 1.425 – 1.575 3.135 – 3.465 Unit V V V
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 7
Operating Conditions
Table 4. Recommended Operating Conditions 1 (continued)
Rating Input voltage Junction temperature (maximum) Ambient temperature
1
Symbol VIN Tj TA
Value GND (–0.3) – 3.465 105 2 0–70
2
Unit V °C °C
Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions is not guaranteed. 2 Note that for extended temperature parts the range is (-40)T – 105Tj.
A
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or VCC). Figure 2 shows the undershoot and overshoot voltage of the 60x bus memory interface of the MPC8272. Note that in PCI mode the I/O interface is different.
4V GVDD + 5% GVDD
VIH
VIL
GND GND – 0.3 V GND – 1.0 V Not to exceed 10% of tSDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 8 Freescale Semiconductor
DC Electrical Characteristics
3
DC Electrical Characteristics
Table 5. DC Electrical Characteristics 1
Characteristic Symbol PORESET 2 VIH VIL VIHC VILC VDDH 4
4
Table 5 shows DC electrical characteristics.
Min 2.0 GND 2.4 GND — — — — 2.4
Max 3.465 0.8 3.465 0.4 10 10 1 1 —
Unit V V V V µA µA µA µA V
Input high voltage—all inputs except TCK, TRST and Input low voltage
3
CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = Hi-Z (off state) leakage current, VIN = VDDH Signal low input current, V IL = 0.8 V Signal high input current, VIH = 2.0 V Output high voltage, IOH = –2 mA except UTOPIA mode, and open drain pins In UTOPIA mode 5 (UTOPIA pins only): IOH = -8.0mA PA[8–31] PB[18–31] PC[0–1,4–29] PD[7–25, 29–31] In UTOPIA mode5 (UTOPIA pins only): IOL = 8.0mA PA[8–31] PB[18–31] PC[0–1,4–29] PD[7–25, 29–31]
IIN IOZ IL IH VOH
VOL
—
0.5
V
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 9
DC Electrical Characteristics
Table 5. DC Electrical Characteristics 1 (continued)
Characteristic IOL = 6.0mA BR BG/IRQ6 ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0–3] AACK ARTRY DBG/IRQ7 DBB/IRQ3 D[0-63] IRQ3/CKSTP_OUT/EXT_BR3 IRQ4/CORE_SRESET/EXT_BG3 IRQ5/TBEN/EXT_DBG3/CINT PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 BADDR31/IRQ5/CINT CPU_BR/INT_OUT IRQ0/NMI_OUT PORESET/PCI_RST HRESET SRESET RSTCONF Symbol VOL Min — Max 0.4 Unit V
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 10 Freescale Semiconductor
DC Electrical Characteristics
Table 5. DC Electrical Characteristics 1 (continued)
Characteristic IOL = 5.3mA CS[0-5] CS6/BCTL1/SMI CS7/TLBSYNC BADDR27/ IRQ1 BADDR28/ IRQ2 ALE/ IRQ4 BCTL0 PWE[0–7]/PSDDQM [0–7]/PBS[0–7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA /PUPMWAIT/PGPL4 PSDAMUX/PGPL5 PCI_CFG0 (PCI_HOST_EN) PCI_CFG1 (PCI_ARB_EN) PCI_CFG2 (DLL_ENABLE) MODCK1/RSRV/TC(0)/BNKSEL(0) MODCK2/CSE0/TC(1)/BNKSEL(1) MODCK3/CSE1/TC(2)/BNKSEL(2) IOL = 3.2mA PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ1/ CPI_HS_ES PCI_GNT0 PCI_GNT1/ CPI_HS_LES PCI_GNT2/ CPI_HS_ENUM PCI_RST PCI_INTA PCI_REQ2 DLLOUT PCI_AD(0-31) PCI_C(0–3)/BE(0-3) PA[8–31] PB[18–31] PC[0–1,4–29] PD[7–25, 29–31] TDO
1
Symbol VOL
Min —
Max 0.4
Unit V
The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs. 2 TCK, TRST and PORESET have min VIH = 2.5V 3 V for IIC interface does not match IIC standard, but does meet IIC standard for V IL OL and should not cause any compatibility issue. 4 The leakage current is measured for nominal VDDH,VCCSYN, and VDD. MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 11
Thermal Characteristics
5
MPC8272 and MPC8271 only.
4
Thermal Characteristics
Table 6 describes thermal characteristics. Refer to Table 2 for information on a given device’s package. Discussions of each characteristic are provided in sections 4.1 through 4.7. For the these discussions, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers.
Table 6. Thermal Characteristics
Characteristic Junction-to-ambient— single-layer board 1 Junction-to-ambient— four-layer board Junction-to-board Junction-to-case 3 Junction-to-package top 4
1 2 2
Symbol
Value 27
Unit °C/W
Air Flow Natural convection 1 m/s Natural convection
RθJA
21 19
RθJA RθJB RθJC RθJT
16 11 8 2
°C/W °C/W °C/W °C/W
1 m/s — — —
Assumes no thermal vias Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 4 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
4.1
Estimation with Junction-to-Ambient Thermal Resistance
C can be obtained from the equation:
An estimation of the chip junction temperature, TJ, in TJ = TA + (RθJA × PD) where:
TA = ambient temperature (ºC) RθJA = package junction-to-ambient thermal resistance (ºC/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
4.2
Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 12 Freescale Semiconductor
Thermal Characteristics
RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (ºC/W) RθJC = junction-to-case thermal resistance (ºC/W) RθCA = case-to-ambient thermal resistance (ºC/W) RθJC is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required.
4.3
Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages, especially PBGA packages, is strongly dependent on the board temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB + (RθJB × PD) where: RθJB = junction-to-board thermal resistance (ºC/W) TB = board temperature (ºC) PD = power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground plane.
4.4
Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application, or a more accurate and complex model of the package can be used in the thermal simulation.
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 13
Thermal Characteristics
4.5
Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: ΨJT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple wire.
4.6
Layout Practices
Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies. Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground using by-pass capacitors located as close as possible to the four sides of the package. For filtering high frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also recommnded. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner layers for power and GND planes. All output pins on the MPC8272 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized to minimize overdamped conditions and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
4.7
References
(415) 964-5111
Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) Specifications (Available from Global Engineering Documents)
800-854-7179 or 303-397-7956
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 14 Freescale Semiconductor
Power Dissipation
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
5
Power Dissipation
Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be included when determining whether to use a heat sink. For a complete list of possible clock configurations, refer to Section 7, “Clock Configuration Modes.”
Table 7. Estimated Power Dissipation for Various Configurations 1
PINT(W) 2, 3 Bus (MHz) CPM Multiplication Factor CPM (MHz) CPU Multiplication Factor CPU (MHz) Vddl 1.5 Volts Nominal 66.67 100 100 133
1 2
Maximum 1.2 1.3 1.5 1.8
3 2 2 2
200 200 200 267
4 3 4 3
266 300 400 400
1 1.1 1.3 1.5
Test temperature = 105° C PINT = IDD x VDD Watts 3 Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds: 66.7 MHz = 0.35 W (nominal), 0.4 W (maximum) 83.3 MHz = 0.4 W (nominal), 0.5 W (maximum) 100 MHz = 0.5 W (nominal), 0.6 W (maximum) 133 MHz = 0.7 W (nominal), 0.8 W (maximum)
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 15
AC Electrical Characteristics
6
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for 66.67-/83.33-/100-/133-MHz MPC8272 devices. Note that AC timings are based on a 50-pf load for MAX Delay and 10-pf load for MIN delay. Typical output buffer impedances are shown in Table 8.
Table 8. Output Buffer Impedances 1
Output Buffers 60x bus Memory controller Parallel I/O PCI
1
Typical Impedance (Ω ) 45 or 27 2 45 or 272 45 27
These are typical values at 65° C. Impedance may vary by ±25% with process and temperature. 2 Impedance value is selected through SIUMCR[20,21]. Refer to the MPC8280 PowerQUICC II Family Reference Manual.
6.1
CPM AC Characteristics
Table 9. AC Characteristics for CPM Outputs 1
Table 9 lists CPM output characteristics.
Spec Number Characteristic Max Min Maximum Delay 66 MHz 6 8 10 8 11 11 11 83 MHz 5.5 8 10 8 11 11 11 100 MHz 5.5 8 10 8 11 11 11
Value (ns) Minimum Delay 66 MHz 0.5 2 0 2 2.5 0.5 0.5 83 MHz 0.5 2 0 2 2.5 0.5 0.5 100 MHz 0.5 2 0 2 2.5 0.5 0.5 133 MHz 0.5 2 0 2 2.5 0.5 0.5
133 MHz 5.5 8 10 8 11 11 11
sp36a sp37a FCC outputs—internal clock (NMSI) sp36b sp37b FCC outputs—external clock (NMSI) sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI) sp38b sp39b SCC/SMC/SPI/I2C outputs—external clock (NMSI) sp40 sp42 sp41 sp43 TDM outputs/SI TIMER/IDMA outputs
sp42a sp43a PIO outputs
1
O utput specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 16 Freescale Semiconductor
AC Electrical Characteristics
Table 10 lists CPM input characteristics.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VCC; fall time refers to transitions from 90% to 10% of VCC.
Table 10. AC Characteristics for CPM Inputs 1
Spec Number Characteristic Setup Hold 66 MHz 6 2.5 6 4 3 8 Setup 83 MHz 6 2.5 6 4 3 8 100 MHz 6 2.5 6 4 3 8 133 MHz 6 2.5 6 4 3 8 66 MHz 0 2 0 2 2.5 0.5 Value (ns) Hold 83 MHz 0 2 0 2 2.5 0.5 100 MHz 0 2 0 2 2.5 0.5 133 MHz 0 2 0 2 2.5 0.5
sp16a sp17a FCC inputs—internal clock (NMSI) sp16b sp17b FCC inputs—external clock (NMSI) sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI) sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI) sp20 sp22
1
sp21 sp23
TDM inputs/SI PIO/TIMER/IDMA inputs
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
NOTE Although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge. Figure 3 shows the FCC internal clock.
BRG_OUT sp17a sp16a FCC input signals sp36a/sp37a FCC output signals
Note: When GFMR[TCI] = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.[TCI] = 1
Figure 3. FCC Internal Clock Diagram
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 17
AC Electrical Characteristics
Figure 4 shows the FCC external clock.
Serial ClKin sp17b sp16b FCC input signals sp36b/sp37b FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b FCC output signals
Note: When GFMR[TCI] = 1
Figure 4. FCC External Clock Diagram
Figure 5 shows the SCC/SMC/SPI/I2C external clock.
Serial CLKin sp18b SCC/SMC/SPI/I2C input signals
(See note)
new CLKin sp19b
sp38b/sp39b SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SPI: 1. Input sampled on the rising edge and output driven on the rising edge. 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge (shown). 4. Input sampled on the falling edge and output driven on the rising edge. Note: There are two possible timing conditions for SCC/SMC/I2C: 1. Input sampled on the falling edge and output driven on the falling edge (shown). 2. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC/SMC/SPI/I2C External Clock Diagram
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 18 Freescale Semiconductor
AC Electrical Characteristics
Figure 6 shows the SCC/SMC/SPI/I2C internal clock.
BRG_OUT sp18a SCC/SMC/SPI/I2C input signals
(See note)
sp19a
sp38a/sp39a SCC/SMC/SPI/I2C output signals
(See note)
Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC/SMC/SPI/I2C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Serial CLKin sp20 TDM input signals sp40/sp41 TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. sp21
Figure 7. TDM Signal Diagram
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 19
AC Electrical Characteristics
Figure 8 shows PIO and timer signals.
Sys clk
sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23 sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO and Timer Signal Diagram
6.2
SIU AC Characteristics
NOTE: CLKIN Jitter and Duty Cycle The CLKIN input to the MPC8272 should not exceed +/– 150 psec. This represents total input jitter—the combination of short term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN should not exceed the ratio of 40:60. NOTE: Spread Spectrum Clocking Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 60 KHz modulation rate regardless of input frequency. NOTE: PCI AC Timing The MPC8272 meets the timing requirements of PCI Specification Revision 2.2. Refer to Section 7, “Clock Configuration Modes,” and “Note: Tval (Output Hold)” to determine if a specific clock configuration is compliant.
Table 11 lists SIU input characteristics.
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 20 Freescale Semiconductor
AC Electrical Characteristics
NOTE: Conditions The following conditions must be met in order to operate the MPC8272 family devices with 133 MHz bus: single PowerQUICC II Bus mode must be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline mode (BRx[DR] = 1); internal arbiter and memory controller must be used. For expected load of above 40 pF, it is recommended that data and address buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0] = 1, SIUMCR[HLBE1] = 1).
Table 11. AC Characteristics for SIU Inputs 1
Spec Number Characteristic Setup Hold 66 MHz 6 5 N/A 5 Setup 83 MHz 5 4 4 4 100 MHz 3.5 3.5 2.5 3.5 133 MHz N/A N/A 1.5 N/A 66 MHz 0.5 0.5 N/A 0.5 Value (ns) Hold 83 MHz 0.5 0.5 0.5 0.5 100 MHz 0.5 0.5 0.5 0.5 133 MHz N/A N/A 0.5 N/A
sp11 sp12 sp13 sp15
1
sp10 AACK/TA/TS/DBG /BG/BR/ARTRY/TEA sp10 Data bus in normal mode sp10 Data bus in pipeline mode (without ECC and PARITY) sp10 All other pins
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.
Table 12 lists SIU output characteristics.
Table 12. AC Characteristics for SIU Outputs 1
Spec Number Characteristic Max Min 66 MHz PSDVAL/TEA /TA ADD/ADD_atr./BADDR/CI/GBL/WT Data bus 3 Memory controller signals/ALE All other signals 7 8 6.5 6 6 Maximum Delay 83 MHz 6 6.5 6.5 5.5 5.5 100 MHz 5.5 5.5 5.5 5.5 5.5 133 MHz N/A 4.5 2 4.5 4.5 N/A 66 MHz 1 1 0.8 1 1 Value (ns) Minimum Delay 83 MHz 1 1 0.8 1 1 100 MHz 1 1 0.8 1 1 133 MHz N/A 12 1 1 N/A
sp31 sp32 sp33 sp34 sp35
1
sp30 sp30 sp30 sp30 sp30
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2 Value is for ADD only; other sp32/sp30 signals are not applicable. 3 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 21
AC Electrical Characteristics
NOTE Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. Figure 9 shows the interaction of several bus signals.
CLKin sp11 AACK/TA/TS/ DBG/BG/BR input signals sp11a ARTRY /TEA input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals sp33 DATA bus output signals sp30 sp30 sp10 sp10 sp10 sp10
sp30
sp35
sp30
All other output signals (except AP) sp13 DATA bus pipeline mode input signal
sp10
Figure 9. Bus Signals
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 22 Freescale Semiconductor
AC Electrical Characteristics
Figure 10 shows signal behavior in MEMC mode.
CLKin
V_CLK
Memory controller signals
sp34/sp30
Figure 10. MEMC Mode Diagram NOTE
Generally, all MPC8272 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
Table 13. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 CLKin 3/10 CLKin 4/14 CLKin T3 1/2 CLKin 1/2 CLKin 1/2 CLKin T4 3/4 CLKin 8/10 CLKin 11/14 CLKin
Figure 11 is a representation of the information in Table 13.
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Figure 11. Internal Tick Spacing for Memory Controller Signals
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 23
AC Electrical Characteristics
NOTE
The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge.
6.3
JTAG Timings
Table 14. JTAG Timings1
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4V JTAG external clock rise and fall times TRST assert time Input setup times Boundary-scan data TMS, TDI Input hold times Boundary-scan data TMS, TDI Output valid times Boundary-scan data TDO Output hold times Boundary-scan data TDO tJTKLDX tJTKLOX 1 1 — — ns ns
5, 7 57 ,
Table 14 lists the JTAG timings.
Symbol2 fJTG tJTG tJTKHKL tJTGR and tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV
Min 0 30 15 0 25 4 4 10 10 — —
Max 33.3 — — 5 — — — — — 10 10
Unit MHz ns ns ns ns ns ns ns ns ns ns
Notes — — —
6
3, 6 4, 7 47 ,
4, 7 4, 7
5, 7 5. 7
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 24 Freescale Semiconductor
Clock Configuration Modes
Table 14. JTAG Timings1 (continued)
Parameter JTAG external clock to output high impedance Boundary-scan data TDO
1
Symbol2 tJTKLDZ tJTKLOZ
Min 1 1
Max 10 10
Unit ns ns
Notes
56
,
56 ,
2
3 4 5 6 7
All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. Non-JTAG signal input timing with respect to tTCLK. Non-JTAG signal output timing with respect to tTCLK. Guaranteed by design. Guaranteed by design and device characterization.
7
Clock Configuration Modes
As shown in Table 15, the clocking mode is set according to two sources: • PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” Refer to the Chapter 6, “External Signals,” and Chapter 9, “PCI Bridge,” in the MPC8272 PowerQUICC II™ Family Reference Manual. • PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. Refer to Chapter 5, “Reset,” in the MPC8272 PowerQUICC II™ Family Reference Manual.
Table 15. MPC8272 Clocking Modes
Pins Clocking Mode PCI_CFG[0] 1 0 0 1 1
1 2
PCI Clock Frequency Range (MHz)
Reference
PCI_MODCK 2 0 1 0 1 PCI agent PCI host 50–66 25–50 50–66 25–50 Table 16 Table 17 Table 18 Table 19
PCI_HOST_EN D etermines PCI clock frequency range.
Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 25
Clock Configuration Modes
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected clock operation mode as described in the following sections. NOTE Clock configurations change only after PORESET is asserted. NOTE: Tval (Output Hold) The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing.
7.1
PCI Host Mode
Table 16 and Table 17 show configurations for PCI host mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the bus clock.
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2
Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 60.0 50.0 60.0 60.0 60.0 50.0 50.0 50.0 66.7 66.7 80.0 80.0 80.0 66.7 66.7 66.7 2 2 2.5 2.5 2.5 3 3.5 3 120.0 133.3 100.0 133.3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 2.5 3 3 3.5 4 3 3.5 4 150.0 166.7 150.0 200.0 180.0 240.0 210.0 280.0 240.0 320.0 150.0 200.0 175.0 233.3 200.0 266.6 2 2 3 3 3 3 3 3 60.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7
Full Configuration Modes 0001_000 0001_001 0001_010 0001_011 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 3 3 3 3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 5 6 7 8 250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3 3 3 3 3 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7
0010_000 0010_001
50.0 50.0
66.7 66.7
4 4
200.0 266.6 200.0 266.6
5 6
250.0 333.3 300.0 400.0
4 4
50.0 50.0
66.7 66.7
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 26 Freescale Semiconductor
Clock Configuration Modes
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 0010_010 0010_011 Bus Clock (MHz) Low 50.0 50.0 High 66.7 66.7 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 50.0 50.0 High 66.7 66.7
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
4 4
200.0 266.6 200.0 266.6
7 8
350.0 466.6 400.0 533.3
4 4
0010_100 0010_101 0010_110
75.0 100.0 75.0 100.0 75.0 100.0
4 4 4
300.0 400.0 300.0 400.0 300.0 400.0
5 5.5 6
375.0 500.0 412.5 549.9 450.0 599.9
6 6 6
50.0 50.0 50.0
66.7 66.7 66.7
0011_000 0011_001 0011_010 0011_011
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
5 6 7 8
250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3
5 5 5 5
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
0100_000 0100_001 0100_010 0100_011 50.0 50.0 50.0 66.7 66.7 66.7 6 6 6 300.0 400.0 300.0 400.0 300.0 400.0
Reserved 6 7 8 300.0 400.0 350.0 466.6 400.0 533.3 6 6 6 50.0 50.0 50.0 66.7 66.7 66.7
0101_000 0101_001 0101_010 0101_011 0101_100
60.0 50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7 66.7
2 2 2 2 2
120.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
2.5 3 3.5 4 4.5
150.0 166.7 150.0 200.0 175.0 233.3 200.0 266.6 225.0 300.0
2 2 2 2 2
60.0 50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7 66.7
0101_101 0101_110 0101_111
83.3 111.1 83.3 111.1 83.3 111.1
3 3 3
250.0 333.3 250.0 333.3 250.0 333.3
3.5 4 4.5
291.7 388.9 333.3 444.4 375.0 500.0
5 5 5
50.0 50.0 50.0
66.7 66.7 66.7
0110_000 0110_001 0110_010
60.0 60.0 60.0
80.0 80.0 80.0
2.5 2.5 2.5
150.0 200.0 150.0 200.0 150.0 200.0
2.5 3 3.5
150.0 200.0 180.0 240.0 210.0 280.0
3 3 3
50.0 50.0 50.0
66.7 66.7 66.7
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 27
Clock Configuration Modes
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 0110_011 0110_100 0110_101 0110_110 Bus Clock (MHz) Low 60.0 60.0 60.0 60.0 High 80.0 80.0 80.0 80.0 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 50.0 50.0 50.0 50.0 High 66.7 66.7 66.7 66.7
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
2.5 2.5 2.5 2.5
150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
4 4.5 5 6
240.0 320.0 270.0 360.0 300.0 400.0 360.0 480.0
3 3 3 3
0111_000 0111_001 0111_010 0111_011 0111_100 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 3 3 3 3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
Reserved 3 3.5 4 4.5 150.0 200.0 175.0 233.3 200.0 266.6 225.0 300.0 3 3 3 3 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 1000_110 66.7 66.7 66.7 66.7 66.7 66.7 88.9 88.9 88.9 88.9 88.9 88.9 3 3 3 3 3 3 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 6 6.5 200.0 266.6 233.3 311.1 266.7 355.5 300.0 400.0 400.0 533.3 433.3 577.7 4 4 4 4 4 4 50.0 50.0 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 66.7 66.7
1001_000 1001_001 1001_010 1001_011 1001_100 57.1 57.1 57.1 76.2 76.2 76.2 3.5 3.5 3.5 200.0 266.6 200.0 266.6 200.0 266.6
Reserved Reserved 3.5 4 4.5 200.0 266.6 228.6 304.7 257.1 342.8 4 4 4 50.0 50.0 50.0 66.7 66.7 66.7
1001_101 1001_110 1001_111
85.7 114.3 85.7 114.3 85.7 114.3
3.5 3.5 3.5
300.0 400.0 300.0 400.0 300.0 400.0
5 5.5 6
428.6 571.4 471.4 628.5 514.3 685.6
6 6 6
50.0 50.0 50.0
66.7 66.7 66.7
1010_000
75.0 100.0
2
150.0 200.0
2
150.0 200.0
3
50.0
66.7
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 28 Freescale Semiconductor
Clock Configuration Modes
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1010_001 1010_010 1010_011 1010_100 Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 50.0 50.0 50.0 50.0 High 66.7 66.7 66.7 66.7
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
75.0 100.0 75.0 100.0 75.0 100.0 75.0 100.0
2 2 2 2
150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
2.5 3 3.5 4
187.5 250.0 225.0 300.0 262.5 350.0 300.0 400.0
3 3 3 3
1010_101 1010_110 1010_111
100.0 133.3 100.0 133.3 100.0 133.3
2 2 2
200.0 266.6 200.0 266.6 200.0 266.6
2.5 3 3.5
250.0 333.3 300.0 400.0 350.0 466.6
4 4 4
50.0 50.0 50.0
66.7 66.7 66.7
1011_000 1011_001 1011_010 1011_011 1011_100 1011_101 80.0 106.7 80.0 106.7 80.0 106.7 80.0 106.7 80.0 106.7 2.5 2.5 2.5 2.5 2.5 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 2.5 3 3.5 4 4.5 200.0 266.6 240.0 320.0 280.0 373.3 320.0 426.6 360.0 480.0 4 4 4 4 4 50.0 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 66.7
1101_000 1101_001 1101_010 1101_011 1101_100
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
2.5 2.5 2.5 2.5 2.5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
3 3.5 4 4.5 5
300.0 400.0 350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6
5 5 5 5 5
50.0 50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7 66.7
1101_101 1101_110
125.0 166.7 125.0 166.7
2 2
250.0 333.3 250.0 333.3
3 4
375.0 500.0 500.0 666.6
5 5
50.0 50.0
66.7 66.7
1110_000 1110_001 1110_010 1110_011 1110_100
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
3 3 3 3 3
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
3.5 4 4.5 5 5.5
350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
6 6 6 6 6
50.0 50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7 66.7
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 29
Clock Configuration Modes
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
1100_000 1100_001 1100_010
1
Reserved Reserved Reserved
2 3 4 5 6
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table 17 for lower range configurations. MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from SCCR[PCIDF] as follows: CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2
Mode 3 MODCK_HMODCK[1-3] Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 60.0 100.0 50.0 100.0 60.0 120.0 60.0 120.0 60.0 120.0 50.0 100.0 50.0 100.0 50.0 100.0 2 2 2.5 2.5 2.5 3 3 3 120.0 200.0 100.0 200.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 2.5 3 3 3.5 4 3 3.5 4 150.0 250.0 150.0 300.0 180.0 360.0 210.0 420.0 240.0 480.0 150.0 300.0 175.0 350.0 200.0 400.0 4 4 6 6 6 6 6 6 30.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0
Full Configuration Modes 0001_000 0001_001 50.0 100.0 50.0 100.0 3 3 150.0 300.0 150.0 300.0 5 6 250.0 500.0 300.0 600.0 6 6 25.0 25.0 50.0 50.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 30 Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 0001_010 0001_011 Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 25.0 25.0 High 50.0 50.0
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
50.0 100.0 50.0 100.0
3 3
150.0 300.0 150.0 300.0
7 8
350.0 700.0 400.0 800.0
6 6
0010_000 0010_001 0010_010 0010_011
50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
4 4 4 4
200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
5 6 7 8
250.0 500.0 300.0 600.0 350.0 700.0 400.0 800.0
8 8 8 8
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
0010_100 0010_101 0010_110
37.5 37.5 37.5
75.0 75.0 75.0
4 4 4
150.0 300.0 150.0 300.0 150.0 300.0
5 5.5 6
187.5 375.0 206.3 412.5 225.0 450.0
6 6 6
25.0 25.0 25.0
50.0 50.0 50.0
0011_000 0011_001 0011_010 0011_011
30.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
5 5 5 5
150.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0
5 6 7 8
150.0 250.0 150.0 300.0 175.0 350.0 200.0 400.0
5 5 5 5
30.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
0100_000 0100_001 0100_010 0100_011 25.0 25.0 25.0 50.0 50.0 50.0 6 6 6 150.0 300.0 150.0 300.0 150.0 300.0
Reserved 6 7 8 150.0 300.0 175.0 350.0 200.0 400.0 6 6 6 25.0 25.0 25.0 50.0 50.0 50.0
0101_000 0101_001 0101_010 0101_011 0101_100
60.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
2 2 2 2 2
120.0 200.0 100.0 200.0 100.0 200.0 100.0 200.0 100.0 200.0
2.5 3 3.5 4 4.5
150.0 250.0 150.0 300.0 175.0 350.0 200.0 400.0 225.0 450.0
4 4 4 4 4
30.0 25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0 50.0
0101_101 0101_110
42.9 41.7
83.3 83.3
3 3
128.6 250.0 125.0 250.0
3.5 4
150.0 291.7 166.7 333.3
5 5
25.7 25.0
50.0 50.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 31
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 0101_111 Bus Clock (MHz) Low 41.7 High 83.3 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 25.0 High 50.0
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
3
125.0 250.0
4.5
187.5 375.0
5
0110_000 0110_001 0110_010 0110_011 0110_100 0110_101 0110_110
60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0
2.5 2.5 2.5 2.5 2.5 2.5 2.5
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2.5 3 3.5 4 4.5 5 6
150.0 300.0 180.0 360.0 210.0 420.0 240.0 480.0 270.0 540.0 300.0 600.0 360.0 720.0
6 6 6 6 6 6 6
25.0 25.0 25.0 25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0 50.0 50.0 50.0
0111_000 0111_001 0111_010 0111_011 0111_100 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 3 3 3 3 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
Reserved 3 3.5 4 4.5 150.0 300.0 175.0 350.0 200.0 400.0 225.0 450.0 6 6 6 6 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 1000_110 66.7 133.3 66.7 133.3 66.7 133.3 66.7 133.3 66.7 133.3 66.7 133.3 3 3 3 3 3 3 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 3 3.5 4 4.5 6 6.5 200.0 400.0 233.3 466.7 266.7 533.3 300.0 600.0 400.0 800.0 433.3 866.7 8 8 8 8 8 8 25.0 25.0 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 50.0 50.0
1001_000 1001_001 1001_010 1001_011 1001_100 1001_101 57.1 114.3 57.1 114.3 57.1 114.3 42.9 85.7 3.5 3.5 3.5 3.5 200.0 400.0 200.0 400.0 200.0 400.0 150.0 300.0
Reserved Reserved 3.5 4 4.5 5 200.0 400.0 228.6 457.1 257.1 514.3 214.3 428.6 8 8 8 6 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 32 Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1001_110 1001_111 Bus Clock (MHz) Low 42.9 42.9 High 85.7 85.7 CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 25.0 25.0 High 50.0 50.0
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
3.5 3.5
150.0 300.0 150.0 300.0
5.5 6
235.7 471.4 257.1 514.3
6 6
1010_000 1010_001 1010_010 1010_011 1010_100
75.0 150.0 75.0 150.0 75.0 150.0 75.0 150.0 75.0 150.0
2 2 2 2 2
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2 2.5 3 3.5 4
150.0 300.0 187.5 375.0 225.0 450.0 262.5 525.0 300.0 600.0
6 6 6 6 6
25.0 25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0 50.0
1010_101 1010_110 1010_111
100.0 200.0 100.0 200.0 100.0 200.0
2 2 2
200.0 400.0 200.0 400.0 200.0 400.0
2.5 3 3.5
250.0 500.0 300.0 600.0 350.0 700.0
8 8 8
25.0 25.0 25.0
50.0 50.0 50.0
1011_000 1011_001 1011_010 1011_011 1011_100 1011_101 80.0 160.0 80.0 160.0 80.0 160.0 80.0 160.0 80.0 160.0 2.5 2.5 2.5 2.5 2.5 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 2.5 3 3.5 4 4.5 200.0 400.0 240.0 480.0 280.0 560.0 320.0 640.0 360.0 720.0 8 8 8 8 8 25.0 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 50.0
1101_000 1101_001 1101_010 1101_011 1101_100
50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
2.5 2.5 2.5 2.5 2.5
125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0
3 3.5 4 4.5 5
150.0 300.0 175.0 350.0 200.0 400.0 225.0 450.0 250.0 500.0
5 5 5 5 5
25.0 25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0 50.0
1101_101 1101_110
62.5 125.0 62.5 125.0
2 2
125.0 250.0 125.0 250.0
3 4
187.5 375.0 250.0 500.0
5 5
25.0 25.0
50.0 50.0
1110_000
50.0 100.0
3
150.0 300.0
3.5
175.0 350.0
6
25.0
50.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 33
Clock Configuration Modes
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1110_001 1110_010 1110_011 1110_100 Bus Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High PCI Clock (MHz) Low 25.0 25.0 25.0 25.0 High 50.0 50.0 50.0 50.0
CPM Multiplication Factor 4
CPU Multiplication Factor 5
PCI Division Factor 6
50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
3 3 3 3
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
4 4.5 5 5.5
200.0 400.0 225.0 450.0 250.0 500.0 275.0 550.0
6 6 6 6
1100_000 1100_001 1100_010
1
Reserved Reserved Reserved
2 3 4 5 6
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for higher range configurations. MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from PCIDF as follows: PCIDF = 3 > CPM_CLK/PCI_CLK = 4 PCIDF = 5 > CPM_CLK/PCI_CLK = 6 PCIDF = 7 > CPM_CLK/PCI_CLK = 8 PCIDF = 9 > CPM_CLK/PCI_CLK = 5 PCIDF = B > CPM_CLK/PCI_CLK = 6
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 34 Freescale Semiconductor
Clock Configuration Modes
7.2
PCI Agent Mode
Table 18 and Table 19 show configurations for PCI agent mode. The frequency values listed are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. Note that in PCI agent mode the input clock is PCI clock.
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2
Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 60.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7 2 2 3 3 3 3 4 4 120.0 133.3 100.0 133.3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0 200.0 266.6 200.0 266.6 2.5 3 3 4 3 3.5 3.5 3 150.0 166.7 150.0 200.0 150.0 200.0 200.0 266.6 180.0 240.0 210.0 280.0 233.3 311.1 240.0 320.0 2 2 3 3 2.5 2.5 3 2.5 60.0 50.0 50.0 50.0 60.0 60.0 66.7 66.7 66.7 66.7 66.7 80.0 80.0 88.9
80.0 106.7
Full Configuration Modes 0001_001 0001_010 0001_011 0001_100 60.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 2 2 2 2 120.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 5 6 7 8 150.0 166.7 150.0 200.0 175.0 233.3 200.0 266.6 4 4 4 4 30.0 25.0 25.0 25.0 33.3 33.3 33.3 33.3
0010_001 0010_010 0010_011 0010_100
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
3 3 3 3
150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
3 3.5 4 4.5
180.0 240.0 210.0 280.0 240.0 320.0 270.0 360.0
2.5 2.5 2.5 2.5
60.0 60.0 60.0 60.0
80.0 80.0 80.0 80.0
0011_000 0011_001 0011_010 0011_011 0011_100
Reserved Reserved Reserved Reserved Reserved
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 35
Clock Configuration Modes
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
0100_000 0100_001 0100_010 0100_011 0100_100 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 3 3 3 3 150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
Reserved 3 3.5 4 4.5 150.0 200.0 175.0 200.0 200.0 266.6 225.0 300.0 3 3 3 3 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7
0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 0101_110
50.0 50.0 50.0 50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7 66.7 66.7 66.7
5 5 5 5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
2.5 3 3.5 4 4.5 5 5.5
250.0 333.3 300.0 400.0 350.0 466.6 400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
2.5 2.5 2.5 2.5 2.5 2.5 2.5
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
0110_000 0110_001 0110_010 0110_011 0110_100 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 4 4 4 4 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 200.0 266.6 233.3 311.1 266.7 355.5 300.0 400.0 3 3 3 3 66.7 66.7 66.7 66.7 88.9 88.9 88.9 88.9
0111_000 0111_001 0111_010 0111_011
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
3 3 3 3
150.0 200.0 150.0 200.0 150.0 200.0 150.0 200.0
2 2.5 3 3.5
150.0 200.0 187.5 250.0 225.0 300.0 262.5 350.0
2 2 2 2
75.0 100.0 75.0 100.0 75.0 100.0 75.0 100.0
1000_000 1000_001 1000_010 1000_011 50.0 50.0 50.0 66.7 66.7 66.7 3 3 3 150.0 200.0 150.0 200.0 150.0 200.0
Reserved 2.5 3 3.5 150.0 166.7 180.0 240.0 210.0 280.0 2.5 2.5 2.5 60.0 60.0 60.0 80.0 80.0 80.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 36 Freescale Semiconductor
Clock Configuration Modes
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1000_100 1000_101 PCI Clock (MHz) Low 50.0 50.0 High 66.7 66.7 CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low 60.0 60.0 High 80.0 80.0
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
3 3
150.0 200.0 150.0 200.0
4 4.5
240.0 320.0 270.0 360.0
2.5 2.5
1001_000 1001_001 1001_010 1001_011 1001_100 50.0 50.0 66.7 66.7 4 4 200.0 266.6 200.0 266.6
Reserved Reserved Reserved 4 4.5 200.0 266.6 225.0 300.0 4 4 50.0 50.0 66.7 66.7
1010_000 1010_001 1010_010 1010_011 1010_100 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 4 4 4 4 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 3 3.5 4 4.5 200.0 266.6 233.3 311.1 266.7 355.5 300.0 400.0 3 3 3 3 66.7 66.7 66.7 66.7 88.9 88.9 88.9 88.9
1011_000 1011_001 1011_010 1011_011 1011_100 50.0 50.0 50.0 50.0 66.7 66.7 66.7 66.7 4 4 4 4 200.0 266.6 200.0 266.6 200.0 266.6 200.0 266.6
Reserved 2.5 3 3.5 4 200.0 266.6 240.0 320.0 280.0 373.3 320.0 426.6 2.5 2.5 2.5 2.5 80.0 106.7 80.0 106.7 80.0 106.7 80.0 106.7
1011_101 1011_110 1011_111
50.0 50.0 50.0
66.7 66.7 66.7
4 4 4
200.0 266.6 200.0 266.6 200.0 266.6
2.5 3 3.5
250.0 333.3 300.0 400.0 350.0 466.6
2 2 2
100.0 133.3 100.0 133.3 100.0 133.3
1100_101 1100_110 1100_111 1101_000
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
6 6 6 6
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
4 4.5 5 5.5
400.0 533.3 450.0 599.9 500.0 666.6 550.0 733.3
3 3 3 3
100.0 133.3 100.0 133.3 100.0 133.3 100.0 133.3
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 37
Clock Configuration Modes
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1101_001 1101_010 1101_011 1101_100 PCI Clock (MHz) Low 50.0 50.0 50.0 50.0 High 66.7 66.7 66.7 66.7 CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
6 6 6 6
300.0 400.0 300.0 400.0 300.0 400.0 300.0 400.0
3.5 4 4.5 5
420.0 559.9 480.0 639.9 540.0 719.9 600.0 799.9
2.5 2.5 2.5 2.5
120.0 160.0 120.0 160.0 120.0 160.0 120.0 160.0
1110_000 1110_001 1110_010 1110_011
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
2.5 3 3.5 4
312.5 416.6 375.0 500.0 437.5 583.3 500.0 666.6
2 2 2 2
125.0 166.7 125.0 166.7 125.0 166.7 125.0 166.7
1110_100 1110_101 1110_110 1110_111
50.0 50.0 50.0 50.0
66.7 66.7 66.7 66.7
5 5 5 5
250.0 333.3 250.0 333.3 250.0 333.3 250.0 333.3
4 4.5 5 5.5
333.3 444.4 375.0 500.0 416.7 555.5 458.3 611.1
3 3 3 3
83.3 111.1 83.3 111.1 83.3 111.1 83.3 111.1
1100_000 1100_001 1100_010
1
Reserved Reserved Reserved
2 3 4 5
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table 19 for lower range configurations. MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 38 Freescale Semiconductor
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2
Mode 3 MODCK_HMODCK[1-3] PCI Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
Default Modes (MODCK_H=0000) 0000_000 0000_001 0000_010 0000_011 0000_100 0000_101 0000_110 0000_111 30.0 25.0 25.0 25.0 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 50.0 4 4 6 6 6 6 8 8 120.0 200.0 100.0 200.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 200.0 400.0 200.0 400.0 2.5 3 3 4 3 3.5 3.5 3 150.0 250.0 150.0 300.0 150.0 300.0 200.0 400.0 180.0 360.0 210.0 420.0 233.3 466.7 240.0 480.0 2 2 3 3 2.5 2.5 3 2.5 60.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 60.0 120.0 60.0 120.0 66.7 133.3 80.0 160.0
Full Configuration Modes 0001_001 0001_010 0001_011 0001_100 30.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 4 4 4 4 120.0 200.0 100.0 200.0 100.0 200.0 100.0 200.0 5 6 7 8 150.0 250.0 150.0 300.0 175.0 350.0 200.0 400.0 4 4 4 4 30.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0
0010_001 0010_010 0010_011 0010_100
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
3 3.5 4 4.5
180.0 360.0 210.0 420.0 240.0 480.0 270.0 540.0
2.5 2.5 2.5 2.5
60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0
0011_000 0011_001 0011_010 0011_011 0011_100 37.5 32.1 28.1 25.0 50.0 50.0 50.0 50.0 4 4 4 4 150.0 200.0 128.6 200.0 112.5 200.0 100.0 200.0
Reserved 3 3.5 4 4.5 150.0 200.0 150.0 233.3 150.0 266.7 150.0 300.0 3 3 3 3 50.0 42.9 37.5 33.3 66.7 66.7 66.7 66.7
0100_000 0100_001 0100_010 0100_011 25.0 25.0 25.0 50.0 50.0 50.0 6 6 6 150.0 300.0 150.0 300.0 150.0 300.0
Reserved 3 3.5 4 150.0 300.0 175.0 350.0 200.0 400.0 3 3 3 50.0 100.0 50.0 100.0 50.0 100.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 39
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 0100_100 PCI Clock (MHz) Low 25.0 High 50.0 CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
6
150.0 300.0
4.5
225.0 450.0
3
50.0 100.0
0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 0101_110
30.0 25.0 25.0 25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0 50.0 50.0 50.0
5 5 5 5 5 5 5
150.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0
2.5 3 3.5 4 4.5 5 5.5
150.0 250.0 150.0 300.0 175.0 350.0 200.0 400.0 225.0 450.0 250.0 500.0 275.0 550.0
2.5 2.5 2.5 2.5 2.5 2.5 2.5
60.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
0110_000 0110_001 0110_010 0110_011 0110_100 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 8 8 8 8 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 3 3.5 4 4.5 200.0 400.0 233.3 466.7 266.7 533.3 300.0 600.0 3 3 3 3 66.7 133.3 66.7 133.3 66.7 133.3 66.7 133.3
0111_000 0111_001 0111_010 0111_011
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
2 2.5 3 3.5
150.0 300.0 187.5 375.0 225.0 450.0 262.5 525.0
2 2 2 2
75.0 150.0 75.0 150.0 75.0 150.0 75.0 150.0
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101 25.0 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 50.0 6 6 6 6 6 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
Reserved 2.5 3 3.5 4 4.5 150.0 300.0 180.0 360.0 210.0 420.0 240.0 480.0 270.0 540.0 2.5 2.5 2.5 2.5 2.5 60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0
1001_000 1001_001
Reserved Reserved
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 40 Freescale Semiconductor
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1001_010 1001_011 1001_100 25.0 25.0 50.0 50.0 8 8 200.0 400.0 200.0 400.0 PCI Clock (MHz) Low High CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
Reserved 4 4.5 200.0 400.0 225.0 450.0 4 4 50.0 100.0 50.0 100.0
1010_000 1010_001 1010_010 1010_011 1010_100 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 8 8 8 8 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 3 3.5 4 4.5 200.0 400.0 233.3 466.7 266.7 533.3 300.0 600.0 3 3 3 3 66.7 133.3 66.7 133.3 66.7 133.3 66.7 133.3
1011_000 1011_001 1011_010 1011_011 1011_100 25.0 25.0 25.0 25.0 50.0 50.0 50.0 50.0 8 8 8 8 200.0 400.0 200.0 400.0 200.0 400.0 200.0 400.0
Reserved 2.5 3 3.5 4 200.0 400.0 240.0 480.0 280.0 560.0 320.0 640.0 2.5 2.5 2.5 2.5 80.0 160.0 80.0 160.0 80.0 160.0 80.0 160.0
1011_101 1011_110 1011_111
25.0 25.0 25.0
50.0 50.0 50.0
8 8 8
200.0 400.0 200.0 400.0 200.0 400.0
2.5 3 3.5
250.0 500.0 300.0 600.0 350.0 700.0
2 2 2
100.0 200.0 100.0 200.0 100.0 200.0
1100_101 1100_110 1100_111 1101_000
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
4 4.5 5 5.5
200.0 400.0 225.0 450.0 250.0 500.0 275.0 550.0
3 3 3 3
50.0 100.0 50.0 100.0 50.0 100.0 50.0 100.0
1101_001 1101_010 1101_011 1101_100
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
6 6 6 6
150.0 300.0 150.0 300.0 150.0 300.0 150.0 300.0
3.5 4 4.5 5
210.0 420.0 240.0 480.0 270.0 540.0 300.0 600.0
2.5 2.5 2.5 2.5
60.0 120.0 60.0 120.0 60.0 120.0 60.0 120.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 41
Clock Configuration Modes
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) 1, 2 (continued)
Mode 3 MODCK_HMODCK[1-3] 1110_000 1110_001 1110_010 1110_011 PCI Clock (MHz) Low 25.0 25.0 28.6 25.0 High 50.0 50.0 50.0 50.0 CPM Clock (MHz) Low High CPU Clock (MHz) Low High Bus Clock (MHz) Low High
CPM Multiplication Factor 4
CPU Multiplication Factor 5
Bus Division Factor
5 5 5 5
125.0 250.0 125.0 250.0 142.9 250.0 125.0 250.0
2.5 3 3.5 4
156.3 312.5 187.5 375.0 250.0 437.5 250.0 500.0
2 2 2 2
62.5 125.0 62.5 125.0 71.4 125.0 62.5 125.0
1110_100 1110_101 1110_110 1110_111
25.0 25.0 25.0 25.0
50.0 50.0 50.0 50.0
5 5 5 5
125.0 250.0 125.0 250.0 125.0 250.0 125.0 250.0
4 4.5 5 5.5
166.7 333.3 187.5 375.0 208.3 416.7 229.2 458.3
3 3 3 3
41.7 41.7 41.7 41.7
83.3 83.3 83.3 83.3
1100_000 1100_001 1100_010
1
Reserved Reserved Reserved
2 3 4 5
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz. PCI_MODCK determines the PCI clock frequency range. Refer to Table 18 for higher range configurations. MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. CPM multiplication factor = CPM clock/bus clock CPU multiplication factor = Core PLL multiplication factor
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 42 Freescale Semiconductor
Pinout
8
Pinout
The figure and table below show the pin assignments and pinout for the 516 PBGA package. Figure 12 shows the pinout of the 516 PBGA package as viewed from the top surface.
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
Not to Scale
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
2
3
456
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 12. Pinout of the 516 PBGA Package (View from Top)
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 43
Pinout
Table 20 shows the pinout of the MPC8272. Note that the pins in the “MPC8272/8271 Only” column relate to Utopia functionality.
Table 20. Pinout
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 BR BG /IRQ6 ABB/IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 Ball MPC8272/MPC8271 Only A19 D2 C1 D1 A3 B5 D8 C6 A4 A6 B6 C7 B7 A7 D9 E11 C9 B9 D11 A9 B10 A10 B11 A11 D12 A12 D13 B13 C13
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 44 Freescale Semiconductor
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 A25 A26 A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG/IRQ7 DBB/IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Ball MPC8272/MPC8271 Only C14 B14 D14 E14 A14 B15 A15 B3 E8 D7 C4 E7 E3 E4 E5 C3 D5 D3 C2 F16 D18 AC1 AA1 V3 R5 P4 M4 J4 G1 W6 Y3
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 45
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 Ball MPC8272/MPC8271 Only V1 N6 P3 M2 J5 G3 AB3 Y1 T4 T3 P2 M1 J1 G4 AB2 W4 V2 T1 N5 L1 H1 G5 W5 W2 T5 T2 N1 K3 H2 F1 AA2
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 46 Freescale Semiconductor
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 IRQ3/CKSTP_OUT/EXT_BR3 IRQ4/CORE_SRESET/EXT_BG3 IRQ5/TBEN/EXT_DBG3/CINT PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 Ball MPC8272/MPC8271 Only W1 U3 R2 N2 L2 H4 F2 AB1 U4 U1 R3 N3 K2 H5 F4 AA3 U5 U2 P5 M3 K4 H3 E1 B16 C15 Y4 C19 AA4 AB6 D15 D16
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 47
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 Only C16 E17 B20 AE6 AD7 AF5 AC8 AF6 AD8 AC9 AB9 AB8 AC7 AF4 AF3 AD6 AE5 AE3 AF2 AC6 AC5 AD4 AB5 AE2 AD3 AB4 AC3 AD2 AC2 AD22 AC21
WT/BADDR30/IRQ3 BADDR31/IRQ5/CINT CPU_BR/INT_OUT CS0 CS1 CS2 CS3 CS4 CS5 CS6/BCTL1/SMI CS7/TLBISYNC BADDR27/IRQ1 BADDR28/IRQ2 ALE/IRQ4 BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4 PSDAMUX/PGPL5 PCI_MODE
1
PCI_CFG0 (PCI_HOST_EN)
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 48 Freescale Semiconductor
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 Ball MPC8272/MPC8271 Only AE22 AE23 AF12 AD15 AF16 AF15 AE15 AE14 AC17 AD14 AD13 AE20 AF14 AD20 AE13 AF21 AF22 AE21 AB14 AC22 AF7 AE10 AB10 AD10 AE9 AF8 AC10 AE11 AB11 AF10 AF9
PCI_CFG1 (PCI_ARB_EN) PCI_CFG2 (DLL_ENABLE) PCI_ PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM PCI_RST PCI_INTA PCI_REQ2 DLLOUT PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 49
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C0/BE0 PCI_C1/BE1 PCI_C2/BE2 PCI_C3/BE3 IRQ0/NMI_OUT TRST 2 TCK TMS TDI TDO Ball MPC8272/MPC8271 Only AB12 AC12 AD12 AF11 AB13 AE16 AF17 AD16 AC16 AF18 AB16 AD17 AF19 AB17 AF20 AE19 AC18 AB18 AD19 AD21 AC20 AE12 AF13 AC15 AE18 A17 E21 B22 C23 B24 A22
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 50 Freescale Semiconductor
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 TRIS PORESET2 /PCI_RST Ball MPC8272/MPC8271 Only B23 C24 D22 F22 A24 A20 C20 A21 D21 AF25 3 AA223 FCC1_UT_RXD0 FCC1_UT_RXD1 FCC1_UT_RXD2 FCC1_UT_RXD3 FCC1_UT_RXD4 FCC1_UT_RXD5 FCC1_UT_RXD6 FCC1_UT_RXD7 AB233 AD263 AD253 AA243 W223 Y243 T223 W263
HRESET SRESET RSTCONF MODCK1/RSRV/TC0/BNKSEL0 MODCK2/CSE0/TC1/BNKSEL1 MODCK3/CSE1/TC2/BNKSEL2 CLKIN1 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_MII_HDLC_RXD3 PA15/FCC1_MII_HDLC_RXD2 PA16/FCC1_MII_HDLC_RXD1 PA17/FCC1_MII_HDLC_RXD0/ FCC1_MII_TRAN_RXD/FCC1_RMII_RX D0 PA18/FCC1_MII_HDLC_TXD0/FCC1_M II_TRAN_TXD/ FCC1_RMII_TXD0 PA19/FCC1_MII_HDLC_TXD1/FCC1_R MII_TXD1 PA20/FCC1_MII_HDLC_TXD2 PA21/FCC1_MII_HDLC_TXD3 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RMIIRX_ER
FCC1_UT_TXD7
V263
FCC1_UT_TXD6 FCC1_UT_TXD5 FCC1_UT_TXD4 FCC1_UT_TXD3 FCC1_UT_TXD2 FCC1_UT_TXD1 FCC1_UT_TXD0 FCC1_UT_RXCLAV
R233 P253 N223 N263 N233 H263 G253 L223
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 51
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 PA27/FCC1_MII_RX_DV/FCC1_RMII_C RS_DV PA28/FCC1_MII_RMII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL Ball MPC8272/MPC8271 Only FCC1_UT_RXSOC FCC1_UT_RXENB FCC1_UT_TXSOC FCC1_UT_TXCLAV FCC1_UT_TXENB G243 G233 B263 A253 G223 T253 P223 L253 J263 U233 U263 M243 M233 H243 E253 D263 K213 D243 E233 AF233 AD233 AB223 AE243 AF243 AE263 AC243 AA233 AB253 V223 AA263
PB18/FCC2_MII_HDLC_RXD3 PB19/FCC2_MII_HDLC_RXD2 PB20/FCC2_MII_HDLC_RMII_RXD1 PB21/FCC2_MII_HDLC_RMII_RXD0/FCC2_TRAN_RXD PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/ FCC2_RMII_TXD0 PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1 PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2 PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2 PB26/FCC2_MII_CRS/L1RXDB2 PB27/FCC2_MII_COL/L1TXDB2 PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1 PB29/FCC2_MII_RMII_TX_EN PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV PB31/FCC2_MII_TX_ER PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2 PC1/BRGO6/L1RQA2 PC4/SMRXD1/SI2_L1ST4/FCC2_CD PC5/SMTXD1/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD/SI2_L1ST2 PC7/FCC1_CTS FCC1_UT_RXADDR2 FCC1_UT_TXADDR2
PC8/CD4/RTS1/SI2_L1ST2/CTS3 PC9/CTS4/L1TSYNCA2 PC10/CD3/USB_RN PC11/CTS3/USB_RP/L1TXD3A2 PC12 FCC1_UT_RXADDR1
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 52 Freescale Semiconductor
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 PC13/BRGO5 PC14/CD1 PC15/CTS1 PC16/CLK16 PC17/CLK15/BRGO8/DONE2 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/TGATE1 PC20/CLK12/USBOE PC21/CLK11/BRGO6/CP_INT PC22/CLK10/DONE3 FCC1_UT_TXPRTY Ball MPC8272/MPC8271 Only FCC1_UT_TXADDR1 FCC1_UT_RXADDR0 FCC1_UT_TXADDR0 V233 W243 U243 T233 T263 R263 P243 L263 L243 L233 K243 K233 F263 H233 K223 D253 F243 AB213 AC263 Y233 FCC1_UT_TXPRTY FCC1_UT_RXPRTY FCC1_UT_RXADDR4 FCC1_UT_TXADDR4 AA253 Y263 W253 V253 R243 P233 N253 K263 K253 J253 C263
PC23/CLK9/BRGO5/DACK3/CD1 PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1 PC25/CLK7/BRGO4/DACK2/SPISEL PC26/CLK6/TOUT3/TMCLK PC27/CLK5/BRGO3/TOUT1 FCC1_UT_RXPRTY
PC28/CLK4/TIN1/TOUT2/SPICLK PC29/CLK3/TIN2/BRGO2/CTS1 PD7/SMSYN2 PD14/I2CSCL PD15/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 FCC1_UT_TXADDR3
PD20/RTS4/L1RSYNCA2 PD21/TXD4/L1RXD0A2 PD22/RXD4/L1TXD0A2 PD23/RTS3/USB_TP PD24/TXD3/USB_TN PD25/RXD3/USB_RXD PD29/RTS1 FCC1_UT_RXADDR3
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 53
Pinout
Table 20. Pinout (continued)
Pin Name MPC8272/MPC8248 and MPC8271/MPC8247 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 No connect I/O power
4 4
Ball MPC8272/MPC8271 Only E243 B253 C18 K6 C21 D19 , J34, AD24 5 B4, F3, J2, N4, AD1, AD5, AE8, AC13, AD18, AB24, AB26, W23, R25, M25, F25, C25, C22, B17, B12, B8, E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9 F5, K5, M5, AA5, AB7, AA13, AA19, AA21, Y22, AC25, U22, R22, L21, H22, E22, E20, E15, F13, F11, F8, L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10 E19, E2, K1, Y2, AE1, AE4, AD9, AC14, AE17, AC19, AE25, V24, P26, M26, G26, E26, B21, C12, C11, C8, A8, B18, A18, A2, B1, B2, A5, C5, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17
Core Power
Ground
1 2
M ust be tied to ground. Should be tied to VDDH via a 2K Ω external pull-up resistor. 3 The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs. 4 This pin is not connected. It should be left floating. 5 M ust be pulled down or left floating
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 54 Freescale Semiconductor
Package
9
Package
Transfer molding compound
Plated substrate via
Figure 13 shows the side profile of the PBGA package.
Die attach Wire bonds
Ball bond Screen-printed solder mask Cu substrate traces
DIE
1 mm pitch
Resin glass epoxy
Figure 13. Side View of the PBGA Package Remove
Table 21 provides package parameters. Figure 14 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
Table 21. Package Parameters
Code VR, ZQ Type PBGA Outline (mm) 27 x 27 Interconnects 516 Pitch (mm) 1 Nominal Unmounted Height (mm) 2.25
NOTE: Temperature Reflow for the VR Package In the VR package, sphere composition is lead-free (refer to Table 2). This requires higher temperature reflow than what is required for other PowerQUICC II packages. Users should consult “Freescale PowerQUICC II™ Pb-Free Packaging Information” (MPC8250PBFREEPKG) available at www.freescale.com.
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 55
Package
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 56 Freescale Semiconductor
Ordering Information
10 Ordering Information
Figure 15 provides an example of the Freescale part numbering nomenclature for the MPC8272. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact a local Freescale sales office.
MPC 82XX C VR XXX X
Product Code Device Number Temperature Range Blank = 0 to 105 °C C = –40 to 105 °C Package ZQ = 516 PBGA (lead spheres) VR = 516 PBGA (no lead spheres) Die Revision Level
CPU/CPM/Bus Frequency (MHz) B = 66 E = 100 F = 133 I = 200 M = 266 P = 300 T = 400
Figure 15. Freescale Part Number Key
11 Document Revision History
Table 22 lists significant changes between revisions of this hardware specification.
Table 22. Document Revision History
Date 12/2008 Substantive Changes • Modified Figure 5, “SCC/SMC/SPI/I2C External Clock Diagram,” and added second section of figure notes. • In Table 11, modified “Data bus in pipeline mode” row and showed 66 MHz as “N/A.” • In Section 10, “Ordering Information,” added “F = 133” to CPU/CPM/Bus Frequency. • Added footnote concerning CPM_CLK/PCI_CLK ratio to column “PCI Division Factor” in Table 16, “Clock Configurations for PCI Host Mode (PCI_MODCK=0),” and Table 17, “Clock Configurations for PCI Host Mode (PCI_MODCK=1),.” • Removed overbar from DLL_ENABLE in Table 20, “Pinout.” • Section 6, “AC Electrical Characteristics,” removed deratings statement and clarified AC timing descriptions. • Added row for 133 MHz configurations to Table 7. • Inserted Section 6.3, “JTAG Timings.” • Added 133-MHz to the list of frequencies in the opening sentence of Section 6, “AC Electrical Characteristics”. • Added 133 MHz columns to Table 9, Table 10, Table 11, and Table 12. • Added footnote 2 to Table 12. • Added the conditions note directly above Table 11.
Revision 2
1.5 1.4 1.3 1.2
12/2006 05/2006 02/2006 09/2005
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 57
Document Revision History
Table 22. Document Revision History (continued)
Date 01/2005 12/2004 Substantive Changes • Modification for correct display of assertion level (“overbar”) for some signals • • • • • • • • • • • • • • • • • • • • • • • Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values Section 2: removed voltage tracking note Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset Table 4: Updated VDD and VCCSYN to 1.425 V - 1.575 V Table 5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external pullup removed. Section 4.6: Updated description of layout practices Table 5: Note 3 added regarding IIC compatibility Table 7: Updated nominal and maximum power dissipation values Table 8: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to reflect configurable impedance Section 6: Added sentence providing derating factor Section 6.1: added Note: Rise/Fall Time on CPM Input Pins Table 9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41, sp42, sp43, sp42a Table 10: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22 Section 6.2: added spread sprectrum clocking note Section 6.2: added CLKIN jitter note Table 11: combined specs sp11 and sp11a Table 12: sp30 Data Bus minimum delay values changed to 0.8 Section 7: unit of ns added to Tval notes Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz. Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz. Table 20: correct superscript of footnote number after pin AD22 Table 20: remove DONE3 from PC12 Table 20: signals referring to TDMs C2 and D2 removed
Revision 1.1 1.0
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 58 Freescale Semiconductor
Document Revision History
Table 22. Document Revision History (continued)
Date 12/2003 • • • • • Substantive Changes Table 1: New Table 2: New Table 4: Modification of VDD and VCCSYN to 1.45–1.60 V Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5) Table 5 and Table 20: Addition of muxed signals CPCI_HS_ES to PCI_REQ1 (AF14) CPCI_HS_LED to PCI_GNT1 (AE13) CPCI_HS_ENUM to PCI_GNT2 (AF21) Table 5 and Table 20: Modification of PCI signal names for consistency with PCI signal names on other PowerQUICC II devices: PCI_CFG0 (PCI_HOST_EN) (AC21) PCI_CFG1 (PCI_ARB_EN) (AE22) PCI_CFG2 (DLL_ENABLE) (AE23) PCI_PAR (AF12) PCI_FRAME (AD15) PCI_TRDY(AF16) PCI_IRDY (AF15) PCI_STOP (AE15) DEVSEL (AE14) PCI_IDSEL (AC17) PCI_PERR (AD14) PCI_SERR (AD13) PCI_REQ0–2 (AAE20, AF14, AB14) PCI_GNT0–2 (AD20, AE13, AF21) PCI_RST (AF22) PCI_INTA (AE21) PCI_C0-3 (AE12, AF13, AC15, AE18) PCI_AD0-31 Table 5 and Table 20: Corrected assertion level (added “ “) PCI_HOST_EN (AC21) and PCI_ARB_EN (AE22) Table 6: Addition of Rθ JT and note 4 Sections 4.1–4.5 and 4.7 on thermal characteristics: New Section 7, “Clock Configuration Modes”: Modification to first paragraph. Note that PCI_MODCK is a bit in the Hard Reset Configuration Word. It is not an input signal as it is in the MPC8280 Family and MPC8260 Family. Addition of “Note: Temperature Reflow for the VR Package" on page 55 Table 20: Addition of note 2 to TRST (E21) and PORESET (C24) Table 20: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.” Note 4 unchanged. Table 20: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged. Table 20: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition of note 1.
Revision 0.2
•
• • • •
• • • • • 0.1 9/2003 • • • • •
Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine) Table 5: Addition of note 2 to VIH Table 5: Changed IOL for 60x signals to 6.0 mA Modification of note 1 for Table 16, Table 17, Table 18, and Table 19 Table 20: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned to both CS5 and GND. AD8 is only assigned to CS5. • Table 20: Addition of note 4 to Thermal0 (D19) and Thermal1(J3) • Addition of ZQ package code to Figure 15
0
5/2003
NDA release
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2 Freescale Semiconductor 59
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Document Number: MPC8272EC Rev. 2 12/2008
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