MPC8315ECVRAGDA

Freescale Semiconductor Technical Data Document Number: MPC8315EEC Rev. 0, 05/2009 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications This document provides an overview of the MPC8315E PowerQUICC™ II Pro processor features, including a block diagram showing the major functional components. The MPC8315E contains a core built on Power Architecture™ technology. It is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several storage, consumer, and industrial applications, including main CPUs and I/O processors in network attached storage (NAS), voice over IP (VoIP) router/gateway, intelligent wireless LAN (WLAN), set top boxes, industrial controllers, and wireless access points. The MPC8315E extends the PowerQUICC II Pro family, adding higher CPU performance, new functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. Note that while the MPC8315E supports a security engine, the MPC8315 does not. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MPC8315E Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ethernet: Three-Speed Ethernet, MII Management . 24 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 53 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 80 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Thermal (Preliminary) . . . . . . . . . . . . . . . . . . . . . . 101 System Design Information . . . . . . . . . . . . . . . . . . 106 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 109 Document Revision History . . . . . . . . . . . . . . . . . . 110 1 Overview The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. © Freescale Semiconductor, Inc., 2009. All rights reserved. MPC8315E Features platform includes features such as dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface, and USB 2.0 with an on-chip USB 2.0 PHY. The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. A block diagram of the MPC8315E is shown in Figure 1. MPC8315E e300c3 Core with Power Management DUART I2C Timers GPIO 16-KB I-Cache Interrupt Controller FPU 16-KB D-Cache TDM Enhanced Local Bus, SPI DDR1/DDR2 Controller Security Engine 3.3 I/O Sequencer (IOS) PCI Express x1 PCI Express x1 USB 2.0 HS Host/Device/OTG SATA ULPI On-Chip HS PHY PHY SATA PHY eTSEC eTSEC RGMII, (R)MII RTBI, SGMII RGMII, (R)MII RTBI, SGMII PCI DMA Note: The MPC8315 do not include a security engine. Figure 1. MPC8315E Block Diagram 2 2.1 MPC8315E Features e300 Core The following features are supported in the MPC8315E. The e300 core has the following features: • Operates at up to 400 MHz • 16-Kbyte instruction cache, 16-Kbyte data cache • One floating point unit and two integer units MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 2 Freescale Semiconductor MPC8315E Features • • Software-compatible with the Freescale processor families implementing the PowerPC Architecture Performance monitor 2.2 Serial Interfaces The following interfaces are supported in the MPC8315E. • Two enhanced TSECs (eTSECs) • Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII) • Dual UART, one I2C, and one SPI interface 2.3 Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are: • Public key execution unit (PKEU) — RSA and Diffie-Hellman (to 4096 bits) — Programmable field size up to 2048 bits — Elliptic curve cryptography (1023 bits) — F2m and F(p) modes — Programmable field size up to 511 bits • Data encryption standard execution unit (DEU) — DES, 3DES — Two key (K1, K2) or three key (K1, K2, K3) — ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES • Advanced encryption standard unit (AESU) — Implements the Rinjdael symmetric key cipher — Key lengths of 128, 192, and 256 bits — ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes — XOR acceleration • Message digest execution unit (MDEU) — SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest — SHA-384/512 — MD5 with 128-bit message digest — HMAC with either algorithm • Random number generator (RNG) — Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62). MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 3 MPC8315E Features • Cyclical Redundancy Check Hardware Accelerator (CRCA) — Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials 2.4 DDR Memory Controller The DDR1/DDR2 memory controller includes the following features: • Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM • Support for up to 266 MHz data rate • Support for two physical banks (chip selects), each bank independently addressable • 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct x4 support) • Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit bus • Support for up to 16 simultaneous open pages • Supports auto refresh • On-the-fly power management using CKE • 1.8-/2.5-V SSTL2 compatible I/O 2.5 PCI Controller The PCI controller includes the following features: • Designed to comply with PCI Local Bus Specification Revision 2.3 • Single 32-bit data PCI interface operates at up to 66 MHz • PCI 3.3-V compatible (not 5-V compatible) • Support for host and agent modes • On-chip arbitration, supporting three external masters on PCI • Selectable hardware-enforced coherency 2.6 TDM Interface The TDM interface includes the following features: • Independent receive and transmit with dedicated data, clock and frame sync line • Separate or shared RCK and TCK whose source can be either internal or external • Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses • Up to 128 time slots, where each slot can be programmed to be active or inactive • 8- or 16-bit word widths • The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock • Signal (RCK) can be configured as either input or output MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 4 Freescale Semiconductor MPC8315E Features • • • • Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock Frame sync can be programmed as active low or active high Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame MSB or LSB first support 2.7 USB Dual-Role Controller The USB controller includes the following features: • Designed to comply with USB Specification, Rev. 2.0 • Supports operation as a stand-alone USB device — Supports one upstream facing port — Supports three programmable USB endpoints • Supports operation as a stand-alone USB host controller — Supports USB root hub with one downstream-facing port — Enhanced host controller interface (EHCI) compatible • Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is supported only in host mode. • Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY • Supports USB on-the-go mode, which includes both device and host functionality, when using an external ULPI PHY 2.8 Dual PCI Express Interfaces The PCI Express interfaces have the following features: • PCI Express 1.0a compatible • x1 link width • Selectable operation as root complex or endpoint • Both 32- and 64-bit addressing • 128-byte maximum payload size • Support for MSI and INTx interrupt messages • Virtual channel 0 only • Selectable Traffic Class • Full 64-bit decode with 32-bit wide windows • Dedicated descriptor based DMA engine per interface with separate read and write channels 2.9 Dual Serial ATA (SATA) Controllers The SATA controllers have the following features: • Designed to comply with Serial ATA Rev 2.5 Specification MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 5 MPC8315E Features • • • • • • • • • • • ATAPI 6+ Spread spectrum clocking on receive Asynchronous notification Hot plug including asynchronous signal recovery Link power management Native command queuing Staggered spin-up and port multiplier support SATA 1.5 and 3.0 Gbps operation Interrupt driven Power management support Error handling and diagnostic features — Far end/near end loopback — Failed CRC error reporting — Increased ALIGN insertion rates — Scrambling and CONT override 2.10 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs) The eTSECs include the following features: • Two SGMII/RGMII/MII/RMII/RTBI interfaces • Two controllers designed to comply with IEEE Std 802.3™, IEEE 802.3u™, IEEE 802.3x™, IEEE 802.3z™, IEEE 802.3au™, IEEE 802.3ab™, and IEEE Std 1588™ • Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating mode • MII management interface for external PHY control and status. 2.11 Integrated Programmable Interrupt Controller (IPIC) The integrated programmable interrupt controller (IPIC) provides a flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller and supports external and internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. 2.12 Power Management Controller (PMC) The MPC8315E supports a range of power management states that significantly lower power consumption under the control of the power management controller. The PMC includes the following features: • Provides power management when the device is used in both PCI host and agent modes • PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states • PME generation in PCI agent mode, PME detection in PCI host mode MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 6 Freescale Semiconductor MPC8315E Features • • • Wake-up from Ethernet (magic packet), USB, GPIO, and PCI (PME input as host) while in the D1, D2 and D3hot states A new low-power standby power management state called D3warm — The PMC, one Ethernet port, and the GTM block remain powered via a split power supply controlled through an external power switch — Wake-up events include Ethernet (magic packet), GTM, GPIO, or IRQ inputs and cause the device to transition back to normal operation — PCI agent mode is not be supported in D3warm state PCI Express-based PME events are not supported 2.13 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC8315E to exchange data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface (receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit. 2.14 DMA Controller, I2C, DUART, Enhanced Local Bus Controller (eLBC), and Timers The integrated four-channel DMA controller includes the following features: • Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) • Misaligned transfer capability for source/destination address • Supports external DREQ, DACK and DONE signals There is one I2C controller. This synchronous, multi-master buses can be connected to additional devices for expansion and system development. The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte FIFOs are supported for both the transmitter and the receiver. The enhanced local bus controller (eLBC) port allows connections with a wide variety of external DSPs and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices. The general-purpose chip select machine (GPCM) controls accesses to asynchronous devices using a simple handshake protocol. The three user programmable machines (UPMs) can be programmed to interface to synchronous devices or custom ASIC interfaces. Each chip select can be configured so that the associated chip interface can be controlled by the GPCM or UPM controller. Both may exist in the same system. The local bus can operate at up to 66 MHz. The system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two general-purpose timer blocks. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 7 Electrical Characteristics 3 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8315E, which is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but they are included for complete reference. These are not purely I/O buffer design specifications. 3.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 3.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings 1 Characteristic Symbol VDD AVDD GVDD GVDD NVDD Max Value –0.3 to 1.26 –0.3 to 1.26 –0.3 to 2.7 –0.3 to 1.9 –0.3 to 3.6 Unit V V V V V Notes — — — — 7 Table 1 provides the absolute maximum ratings. Core supply voltage PLL supply voltage DDR1 DRAM I/O supply voltage DDR2 DRAM I/O supply voltage PCI, local bus, DUART, system control and power management, I2C, Ethernet management, 1588 timer and JTAG I/O voltage USB, and eTSEC I/O voltage PHY voltage USB PHY LVDD USB_PLL_PWR1 USB_PLL_PWR3, USB_VDDA_BIAS, VDDA –0.3 to 2.75 or –0.3 to 3.6 –0.3 to 1.26 –0.3 to 3.6 V V V 6, 8 — — SERDES PHY XCOREVDD, XPADVDD, SDAVDD SATA_VDD, VDD1IO, VDD1ANA VDD33PLL, VDD33ANA –0.3 to 1.26 V — SATA PHY –0.3 to 1.26 V — –0.3 to 3.6 V — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 8 Freescale Semiconductor Electrical Characteristics Table 1. Absolute Maximum Ratings 1 (continued) Characteristic Input voltage DDR DRAM signals DDR DRAM reference eTSEC signals Local bus, DUART, SYS_CLKIN, system control and power management, I2C, and JTAG signals PCI SATA_CLKIN Storage temperature range Symbol MVIN MVREF LVIN NVIN Max Value –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (NVDD + 0.3) Unit V V V V Notes 2, 4 2, 4 3, 4 3, 4 NVIN NVIN TSTG –0.3 to (NVDD + 0.3) –0.3 to (NVDD + 0.3) –55 to150 V V °C 5 3, 4 — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: (N,L)VIN must not exceed (N,L)VDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. (M,N,L)V IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 5. NVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. 6. The max value of supply voltage shoud be selected based on the RGMII mode. 7. NVDD means NVDD1_OFF, NVDD1_ON, NVDD2_OFF, NVDD2_ON, NVDD3_OFF, NVDD4_OFF 8. LVDD means LVDD1_OFF and LVDD2_ON 3.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for theMPC8315E. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic SerDes internal digital power SerDes internal digital power SerDes I/O digital power SerDes I/O digital power SerDes analog power for PLL SerDes analog power for PLL Dedicated 3.3 V analog power for USB PLL Symbol XCOREVDD XCOREVSS XPADVDD XPADVSS SDAVDD SDAVSS USB_PLL_PWR3 Recommended Value1 1.0 ± 50 mv 0.0 1.0 ± 50 mv 0.0 1.0 ± 50 mv 0.0 3.3 ± 165mv Unit V V V V V V V Status in D3 Warm mode Switched Off — Switched Off — Switched Off — Switched Off Notes — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 9 Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Dedicated 1.0 Vanalog power for USB PLL Dedicated analog ground for USB PLL Dedicated USB power for USB bias circuit Dedicated USB ground for USB bias circuit Dedicated power for USB transceiver Dedicated ground for USB transceiver SATA digital power SATA digital ground SATA analog I/O power SATA analog I/O ground SATA core analog power SATA analog ground SATA analog power PLL SATA 3.3 analog power SATA reference analog ground Core supply voltage Core supply voltage Analog power for e300 core APLL Analog power for system APLL DDR and DDR2 DRAM I/O voltage Differential reference voltage for DDR and DDR2 controller Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage eTSEC/USBdr I/O supply eTSEC I/O supply Analog and digital ground Symbol USB_PLL_PWR1 USB_PLL_GND USB_VDDA_BIAS USB_VSSA_BIAS USB_VDDA USB_VSSA SATA_VDD SATA_VSS VDD1IO VSS1IO VDD1ANA VSS1ANA VDD33PLL VDD33ANA VSSRESREF VDD VDDC AVDD1 AVDD2 GVDD MVREF NVDD1_ON NVDD2_ON NVDD1_OFF NVDD2_OFF NVDD3_OFF NVDD4_OFF LVDD1_OFF LVDD2_ON VSS Recommended Value1 1.0 ± 50 mv 0.0 3.3 ± 300 mv 0.0 3.3 ± 300 mv 0.0 1.0 ± 50 mv 0.0 1.0 ± 50 mv 0.0 1.0 ± 50 mv 0.0 3.3 ± 165 mv 3.3 ± 165 mv 0.0 1.0 ± 50 mv 1.0 ± 50 mv 1.0 ± 50 mv 1.0 ± 50 mv 2.5 ± 200 mv 1.8 ± 100 mv GVDD /2 3.3 ± 300 mv 3.3 ± 300 mv 3.3 ± 300 mv 3.3 ± 300 mv 3.3 ± 300 mv 3.3 ± 300 mv 2.5 ± 125 mv 3.3 ± 300 mv 2.5 ± 125 mv 3.3 ± 300 mv 0.0 Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Status in D3 Warm mode Switched Off — Switched Off — Switched Off — Switched Off — Switched Off — Switched Off — Switched Off Switched Off — Switched Off Switched On Switched Off Switched On Switched Off Switched Off Switched On Switched On Switched Off Switched Off Switched Off Switched Off Switched Off Switched On — Notes — — — — — — — — — — — — — — — — — — — — — 1 1 2 2 2 2 — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 10 Freescale Semiconductor Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Junction temperature range Symbol Recommended Value1 0 to105 Unit °C Status in D3 Warm mode — Notes 3 TA/TJ Note: 1. The NVDDx_ON are static power supplies and can be connected together. 2. The NVDDx_OFF are switchable power supplies and can be connected together. 3. Minimum Temperature is specified with TA;maximum temperature is specified with TJ. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8315E. G/L/NVDD + 20% G/L/NVDD + 5% VIH G/L/NVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD 3.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Local bus interface utilities signals PCI signals Output Impedance (Ω ) 42 25 Supply Voltage NVDD = 3.3 V MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 11 Electrical Characteristics Table 3. Output Drive Capability (continued) Driver Type DDR signal1 DDR2 signal 1 DUART, system control, GPIO signals eTSEC 1 Output Impedance (Ω ) 18 18 Supply Voltage GVDD = 2.5 V GVDD = 1.8 V NVDD = 3.3 V NVDD = 3.3 V LVDD = 3.3 V / 2.5 V I2 C, JTAG,SPI 42 42 42 Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR). See the M PC8315E PowerQUICC II Pro Host Processor Reference Manual. 3.2 Power Sequencing The MPC8315E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages (GVDD, LVDDx_ON, LVDDx_OFF, NVDDx_ON and NVDDx_OFF) to be applied in any particular order. During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied before the core voltage, there may be a period of time when all input and output pins be actively driven and cause contention and/or excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the continuous core voltage (VDDC) before the continuous I/O voltages (LVDDx_ON and NVDDx_ON) and switchable core voltage (VDD) before the switchable I/O voltages (GVDD, LVDDx_OFF, and NVDDx_OFF). PORESET should be asserted before the continuous power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 3. Once all the power supplies are stable, wait for a minimum of 32 clock cycles before negating PORESET. The I/O power supply ramp-up slew rate should be slower than 4V/100 μs, this requirement is for ESD circuit. Figure 3 shows the power-up sequencing for switchable and continuous supplies. V Continuous I/O Voltage V Switchable I/O Voltage Continuous Core Voltage Switchable Core Voltage (VDD) 90% 0.7 V 90% 0.7 V t Power sequence for continuous power supplies t Power sequence for switchable power supplies Figure 3. Power-Up Sequencing MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 12 Freescale Semiconductor Electrical Characteristics When switching from normal mode to D3 warm (standby) mode, first turn off the switchable I/O voltage supply and then turn off the switchable core voltage supply. Similarly, when switching from D3 warm (standby) mode to normal mode, first turn on the switchable core voltage supply and then turn on the switchable I/O voltage supply. CAUTION When the device is in D3 warm (standby) mode, all external voltage supplies applied to any I/O pins, with the exception of wake-up pins, must be turned off. Applying supplied external voltage to any I/O pins, except the wake up pins, while the device is in D3 warm standby mode may cause permanent damage to the device. An example of the power-up sequence is shown in Figure 4 when implemented along with low power D3 warm mode. V Continuous I/O Voltage (LVDDx_ON, NVDDx_ON) Switchable I/O Voltage (GVDD, LVDDx_OFF, NVDDx_OFF) Continuous Core Voltage VDDC Switchable Core Voltage (VDD) 90% 0 PORESET t tSYS_CLK_IN / tPCI_SYNC_IN >= 32 clock Figure 4. Power Up Sequencing Example with Low power D3 Warm Mode The switchable and continuous supplies can be combined when the D3 warm mode is not used. The SATA power supplies VDD33PLL and VDD33ANA should go high after NVDD3_OFF supply and go low before NVDD3_OFF supply. The NVDD3_OFF voltage levels should not drop below the VDD33PLL, VDD33ANA voltages at any time. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 13 Power Characteristics Figure 5 shows the SATA power supplies. Voltage NVDD3_OFF tŠ0 NVDD3_OFF VDD33_PLL & VDD33_ANA Time Figure 5. SATA Power Supplies 4 Power Characteristics Table 4. MPC8315E Power Dissipation4 The estimated typical power dissipation for this family of devices is shown in Table . (Does not include I/O power dissipation) Core Frequency (MHz) 266 333 400 CSB Frequency (MHz) 133 133 133 Typical 1,3 1.116 1.142 1.167 Maximum 1,2 1.646 1.665 1.690 Unit W W W Note: 1. The values do not include I/O supply power, but do include core, AVDD, USB PLL, digital SerDes power, and SATA PHY power. C, 2. Maximum power is based on a voltage of V dd = 1.05V, a junction temperature of Tj = 105•C, and an artificial smoker test. 3. Typical power is based on a voltage of Vdd = 1.05V, and an artificial smoker test running at room temperature. The estimated typical I/O power dissipation for this family of devices is shown in Table 5. Table 5. MPC8315E Power Dissipation LVDD1_OFF/ LVDD2 VDD33PLL, _ON VDD33ANA LVDD2_ON (3.3V) (3.3V) (3.3V) — — — — — — SATA_VDD, XCOREVDD , XPADVDD, VDD1IO, SDAVDD VDD1ANA (1.0V) (1.0V) — — — — Interface GVDD GVDD NVDD Frequency (1.8 V) (2.5 V) (3.3 V) Unit DDR 1 Rs = 22Ω Rt = 50Ω 266MHz, 32 bits 200MHz, 32 bits — — 0.323 0.291 — — W W MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 14 Freescale Semiconductor Clock Input Timing Table 5. MPC8315E Power Dissipation (continued) LVDD1_OFF/ LVDD2 VDD33PLL, _ON VDD33ANA LVDD2_ON (3.3V) (3.3V) (3.3V) — — — — — — 0.008 0.078 — — — — 0.056 0.040 — — — — — — — — — — SATA_VDD, XCOREVDD , XPADVDD, VDD1IO, SDAVDD VDD1ANA (1.0V) (1.0V) — — — — — — — — — — — — — — — — Interface GVDD GVDD NVDD Frequency (1.8 V) (2.5 V) (3.3 V) Unit DDR 2 Rs = 22Ω Rt = 75Ω 266MHz, 32 bits 200MHz, 32bits 33 MHz 66 MHz 66 MHz 50 MHz 0.246 0.225 — — — — — — — — — — — — — — — — 0.120 0.249 — — — — W W W W W W W W PCI I/O load = 50pF Local bus I/O load = 20pF eTSEC I/O MII, 25MHz load = 20pF RGMII, Multiple by 125MHz number of (3.3V) interface used RGMII, 125MHz (2.5V) USBDR Controller (ULPI mode) load =20pF USBDR+ Internal PHY (UTMI mode) PCIe two x1lane SATA two ports Other I/O 60 MHz — — — 0.044 — — — — W — — — 0.078 — — — — W 480 MHz — — — 0.274 — — — — W 2.5 GHz 3.0 GHz — — — — — — — — — 0.015 — — — — — — — 0.021 — — 0.206 — 0.190 — — W W W 5 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8315E. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 15 Clock Input Timing 5.1 DC Electrical Characteristics Table 6 provides the clock input (SYS_CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8315E. Table 6. SYS_CLKIN DC Electrical Characteristics Parameter Input high voltage Input low voltage SYS_CLKIN input current SYS_CR_CLKIN input current PCI_SYNC_IN input current RTC_CLK input current USB_CLK_IN input current USB_CR_CLK_IN input current SATA_CLK_IN input current Condition — — 0 V ≤VIN ≤ NVDD 0 V ≤VIN ≤ NVDD 0 V ≤VIN ≤ NVDD 0 V ≤VIN ≤ NVDD 0 V ≤ VIN ≤ NVDD 0 V ≤VIN ≤ NVDD 0 V ≤VIN ≤ NVDD Symbol VIH VIL IIN IIN IIN IIN IIN IIN IIN Min 2.4 -0.3 — — — — — — — Max NVDD + 0.3 0.4 ±10 ±40 ±10 ±10 ±10 ±40 ±10 Unit V V μA μA μA μA μA μA μA 5.2 AC Electrical Characteristics The primary clock source for the MPC8315E can be one of two inputs, SYS_CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (SYS_CLKIN/PCI_CLK) AC timing specifications for the MPC8315E. Table 7. SYS_CLKIN AC Timing Specifications Parameter/Condition SYS_CLKIN/PCI_CLK frequency SYS_CLKIN/PCI_CLK cycle time SYS_CLKIN/PCI_CLK rise and fall time SYS_CLKIN/PCI_CLK duty cycle SYS_CLKIN/PCI_CLK jitter Symbol fSYS_CLKIN tSYS_CLKIN tKH, tKL tKHK/tSYS_CLKIN — Min 24 15 0.6 40 — Typical — — — — — Max 66 41.6 1.2 60 ±150 Unit MHz ns ns % ps Notes 1, 6, 7 6 2, 6 3, 6 4, 5, 6 Notes: 1. Caution: The system, core, and security block must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for SYS_CLKIN/PCI_CLK are measured at 0.4 and 2.4 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYS_CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be 1,000,000 16 Unit baud baud — Notes — 1 2 Table 22 lists the AC timing parameters for the DUART interface. Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. 9 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 24 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 9.1 eTSEC (10/100/1000 Mbps)—MII/RMII/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to all the media-independent interface (MII), reduced gigabit MII (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management data clock (MDC). The MII and RMII is defined for 3.3 V, while the RGMII, and RTBI can operate at 2.5 V. The RGMII and RTBI follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 9.3, “Ethernet Management Interface Electrical Characteristics.” 9.1.1 MII, RMII, RGMII, and RTBI DC Electrical Characteristics All MII, RMII drivers and receivers comply with the DC parametric attributes specified in Table 23 for 3.3-V operation and RGMII, RTBI drivers and receivers comply with the DC parametric attributes specified in Table 24. The RGMII and RTBI signals are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8–5. Table 23. MII/RMII (When Operating at 3.3 V) DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL — IOH = –4.0 mA IOL = 4.0 mA — — VIN 1= Conditions — LVDD = Min LVDD = Min — — LVDD Min 3.0 2.40 VSS 2.1 –0.3 — –600 Max 3.6 LVDD + 0.3 0.50 LVDD + 0.3 0.90 40 — Unit V V V V V μA μA VIN 1 = VSS Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 25 Ethernet: Three-Speed Ethernet, MII Management Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL — IOH = –1.0 mA IOL = 1.0 mA — — Conditions — LVDD = Min LVDD = Min LVDD = Min LVDD =Min VIN 1 = LVDD VIN 1 = VSS Min 2.37 2.00 VSS – 0.3 1.7 –0.3 — –15 Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 15 — Unit V V V V V μA μA Note: 1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 9.2 MII, RMII, RGMII, and RTBI AC Timing Specifications The AC timing specifications for MII, RMII, RGMII, and RTBI are presented in this section. 9.2.1 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 9.2.1.1 MII Transmit AC Timing Specifications Table 25. MII Transmit AC Timing Specifications Table 25 provides the MII transmit AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 300 mv. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) TX_CLK data clock fall VIH(max) to VIL(min) Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF Min — — 35 1 1.0 1.0 Typ 400 40 — 5 — — Max — — 65 15 4.0 4.0 Unit ns ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 26 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 10 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 10. MII Transmit AC Timing Diagram 9.2.1.2 MII Receive AC Timing Specifications Table 26. MII Receive AC Timing Specifications Table 26 provides the MII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 300 mv Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min) Symbol 1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF Min — — 35 10.0 10.0 1.0 1.0 Typ 400 40 — — — — — Max — — 65 — — 4.0 4.0 Unit ns ns % ns ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 11 provides the AC test load for eTSEC. Output Z0 = 50 Ω LVDD/2 RL = 5 0 Ω Figure 11. eTSEC AC Test Load MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 27 Ethernet: Three-Speed Ethernet, MII Management Figure 12 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 12. MII Receive AC Timing Diagram RMII AC Timing Specifications 9.2.2 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 9.2.2.1 RMII Transmit AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. Table 27 provides the RMII transmit AC timing specifications. Table 27. RMII Transmit AC Timing Specifications At recommended operating conditions with LVDD of 3.3 V ± 300 mv Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to RMII data TXD[1:0], TX_EN delay REF_CLK data clock rise VIL(min) to VIH(max) REF_CLK data clock fall VIH(max) to VIL(min) Symbol 1 tRMX tRMXH/tRMX tRMTKHDX tRMXR tRMXF Min — 35 2 1.0 1.0 Typ 20 — — — — Max — 65 10 4.0 4.0 Unit ns % ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 28 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 13 shows the RMII transmit AC timing diagram. tRMX REF_CLK tRMXH TXD[1:0] TX_EN tRMTKHDX tRMXF tRMXR Figure 13. RMII Transmit AC Timing Diagram 9.2.2.2 RMII Receive AC Timing Specifications Table 28. RMII Receive AC Timing Specifications Table 28 provides the RMII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 300 mv Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise VIL(min) to VIH(max) REF_CLK clock fall time V IH(max) to VIL(min) Symbol 1 tRMX tRMXH/tRMX tRMRDVKH tRMRDXKH tRMXR tRMXF Min — 35 4.0 2.0 1.0 1.0 Typ 20 — — — — — Max — 65 — — 4.0 4.0 Unit ns % ns ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 14 provides the AC test load. Output Z0 = 50 Ω RL = 5 0 Ω NVDD/2 Figure 14. AC Test Load MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 29 Ethernet: Three-Speed Ethernet, MII Management Figure 15 shows the RMII receive AC timing diagram. tRMX REF_CLK tRMXH RXD[1:0] CRS_DV RX_ER tRMRDVKH tRMRDXKH tRMXF Valid Data tRMXR Figure 15. RMII Receive AC Timing Diagram 9.2.3 RGMII and RTBI AC Timing Specifications Table 29. RGMII and RTBI AC Timing Specifications Table 29 presents the RGMII and RTBI AC timing specifications. At recommended operating conditions (see Table 2) Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration 3 4, 5 3, 5 2 Symbol 1 tSKRGT tSKRGT tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12 6 Min –0.6 1.0 7.2 45 40 — — — 47 Typ — — 8.0 50 50 — — 8.0 — Max 0.6 2.6 8.8 55 60 0.75 0.75 — 53 Unit ns ns ns % % ns ns ns % Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle tG125H/tG125 Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the RTBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Duty cycle reference is LVDD/2. 6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. GTX_CLK supply voltage is fixed at 3.3V inside the chip. If PHY supplies a 2.5 V Clock signal on this input, set TSCOMOBI bit of System I/O configuration register (SICRH) as 1. See the MPC8315E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 30 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 16 shows the RGMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGT TX_CLK (At PHY) TX_CTL RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CTL RX_CLK (At Controller) Figure 16. RGMII and RTBI AC Timing and Multiplexing Diagrams 9.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals management data input/output (MDIO) and management data clock (MDC). The electrical characteristics for MII, RMII, RGMII, and RTBI are specified in Section 9.1, “eTSEC (10/100/1000 Mbps)—MII/RMII/RGMII/RTBI Electrical Characteristics.” 9.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30. Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Symbol NVDD VOH VOL VIH VIL — IOH = –1.0 mA IOL = 1.0 mA — — Conditions — NVDD = Min NVDD = Min — — Min 3.0 2.10 VSS 2.00 — Max 3.6 NVDD + 0.3 0.50 — 0.80 Unit V V V V V MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 31 Ethernet: Three-Speed Ethernet, MII Management Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V (continued) Parameter Input high current Input low current Symbol IIH IIL Conditions NVDD = Max NVDD = Max VIN 1 = 2.1 V VIN = 0.5 V Min — –600 Max 40 — Unit μA μA Note: 1. Note that the symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2. 9.3.2 MII Management AC Electrical Specifications Table 31. MII Management AC Timing Specifications Table 31 provides the MII management AC timing specifications. At recommended operating conditions with LVDD is 3.3 V ± 300 mv Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Symbol 1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min — — 32 10 5 0 — — Typ 2.5 400 — — — — — — Max — — — 170 — — 10 10 Unit MHz ns ns ns ns ns ns ns Notes 2 — — 3 — — — — Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the maximum frequency is 4.16 MHz and the minimum frequency is 0.593 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns). MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 32 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Figure 17 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 17. MII Management Interface Timing Diagram 9.4 1588 Timer Specifications This section describes the DC and AC electrical specifications for the 1588 timer. 9.4.1 1588 Timer DC Specifications Table 32. GPIO DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ NVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 NVDD + 0.3 0.8 ±5 Unit V V V V V μA Table 33 provides the 1588 timer DC specifications. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 9.4.2 1588 Timer AC Specifications Table 33. 1588 Timer AC Specifications Parameter Symbol tTMRCK tTMRCKS tTMRCKH Min 0 — — Max 70 — — Unit MHz — — Notes 1 2, 3 2, 3 Table 33 provides the 1588 timer AC specifications. Timer clock cycle time Input setup to timer clock Input hold from timer clock MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 33 Ethernet: Three-Speed Ethernet, MII Management Table 33. 1588 Timer AC Specifications (continued) Parameter Output clock to output valid Timer alarm to output valid Symbol tGCLKNV tTMRAL Min 0 — Max 6 — Unit ns — 2 Notes Note: 1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. 2. Asynchronous signals. 3. Inputs need to be stable at least one TMR clock. 9.5 SGMII Interface Electrical Characteristics Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes interface of MPC8315E as shown in Figure 18, where CTX is the external (on board) AC-Coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XCOREVSS. The reference circuit of the SerDes transmitter and receiver is shown in Figure 49. When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this eTSEC port can be left floating. The input signals should be terminated based on the guidelines described in Section 26.4, “Connection Recommendations,” as long as such termination does not violate the desired POR configuration requirement on these pins, if applicable. When operating in SGMII mode, the TSEC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference clock is required on SD_REF_CLK and SD_REF_CLK pins. 9.5.1 DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK The characteristics and DC requirements of the separate SerDes reference clock are described in Section 15, “High-Speed Serial Interfaces (HSSI).” 9.5.2 AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK Table 34 lists the SGMII SerDes reference clock AC requirements. Please note that SD_REF_CLK and SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. Table 34. SD_REF_CLK and SD_REF_CLK AC R equirements Symbol tREF tREFCJ tREFPJ REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles Phase jitter. Deviation in edge location with respect to mean edge location Parameter Description Min — –50 Typical 8 — — Max 100 50 Units ns ps ps Notes — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 34 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 9.5.3 SGMII Transmitter and Receiver DC Electrical Characteristics Table 35 and Table 36 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD_TX[n] and SD_TX[n]) as depicted in Figure . Table 35. SGMII DC Transmitter Electrical Characteristics Parameter Supply Voltage Output high voltage Output low voltage Output ringing Symbol XCOREVDD VOH VOL VRING Min 0.95 — XCOREVDD-Typ/2 - |VOD|-max/2 — 323 296 269 Output differential voltage2, 3, 5 |VOD| 243 215 189 162 Output offset voltage Output impedance (single-ended) Mismatch in a pair Change in VOD between “0” and “1” Change in VOS between “0” and “1” Output current on short to GND VOS RO Δ RO Δ |VOD| Δ VOS ISA, ISB 425 40 — — — — 376 333 292 250 500 — — — — — 545 483 424 362 575 60 10 25 25 40 mV Ω % mV mV mA mV Typ 1.0 — — — 500 459 417 Max 1.05 XCOREVDD -Typ/2 + |VOD|-max/2 — 10 725 665 604 Unit V mV mV % Notes — 1 1 — Equalization setting: 1.0x Equalization setting: 1.09x Equalization setting: 1.2x Equalization setting: 1.33x Equalization setting: 1.5x Equalization setting: 1.71x Equalization setting: 2.0x 1, 4 — — — — — Note: 1. This will not align to DC-coupled SGMII. XCOREVDD-Typ=1.0V. 2. |VOD| = |VTXn - VTXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|. 3. The |VOD| value shown in the table assumes the following transmit equalization setting in the TXEQA (for SerDes lane A) or TXEQE (for SerDes lane E) bit field of MPC8315E’s SerDes Control Register 0: • The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. 4. VOS is also referred to as output common mode voltage. 5. The |VOD| value shown in the Typ column is based on the condition of XCOREVDD-Typ=1.0V, no common mode offset variation (VOS = 500 mV), SerDes transmitter is terminated with 100-Ω differential load between TX[n] and TX[n]. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 35 Ethernet: Three-Speed Ethernet, MII Management 50 Ω TXn CTX RXm 50 Ω Transmitter 50 Ω TXn MPC8315E SGMII SerDes Interface RXn 50 Ω CTX RXm Receiver 50 Ω 50 Ω CTX TXm Receiver Transmitter 50 Ω 50 Ω RXn CTX TXm Figure 18. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8315E SGMII SerDes Interface 50 Ω TXn Transmitter 50 Ω TXn 50 Ω 50 Ω Vos VOD Figure 19. SGMII Transmitter DC Measurement Circuit Table 36. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage range Input differential voltage EQ = 0 EQ = 1 Symbol XCOREVDD — VRX_DIFFp-p 100 175 Min 0.95 Typ 1.0 N/A — — 1200 Max 1.05 Unit V — mV Notes — 1 2, 4 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 36 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Table 36. SGMII DC Receiver Electrical Characteristics (continued) Parameter Loss of signal threshold EQ = 0 EQ = 1 Input AC common mode voltage Receiver differential input impedance Receiver common mode input impedance Common mode input voltage VCM_ACp-p ZRX_DIFF ZRX_CM VCM Symbol VLOS Min 30 65 — 80 20 — Typ — — — 100 — Vxcorevss Max 100 175 100 120 35 — mV Ω Ω V 5 — — 6 Unit mV Notes 3, 4 Note: 1. Input must be externally AC-coupled. 2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage 3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI Express Differential Receiver (RX) Input Specifications section for further explanation. 4. The EQ shown in the table refers to the RXEQA or RXEQE bit field of MPC8315E’s SerDes Control Register 0. 5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage. 6. On-chip termination to XCOREVSS. 9.5.4 SGMII AC Timing Specifications This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are measured at the transmitter outputs (TX[n] and TX[n]) or at the receiver inputs (RX[n] and RX[n]) as depicted in Figure 21 respectively. 9.5.4.1 SGMII Transmit AC Timing Specifications Table 37. SGMII Transmit AC Timing Specifications Table 37 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided. At recommended operating conditions with XCOREVDD = 1.0V ± 5%. Parameter Deterministic Jitter Total Jitter Unit Interval VOD fall time (80%-20%) VOD rise time (20%-80%) Notes: 1. Each UI is 800 ps ± 100 ppm. Symbol JD JT UI tfall trise Min — — 799.92 50 50 Typ — — 800 — — Max 0.17 0.35 800.08 120 120 Unit UI p-p UI p-p ps ps ps Notes — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 37 Ethernet: Three-Speed Ethernet, MII Management 9.5.4.2 SGMII Receive AC Timing Specifications Table 38 provides the SGMII receive AC timing specifications. Source synchronous clocking is not supported. Clock is recovered from the data. Figure 20 shows the SGMII Receiver Input Compliance Mask eye diagram. Table 38. SGMII Receive AC Timing Specifications At recommended operating conditions with XCOREVDD = 1.0V ± 5%. Parameter Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Sinusoidal Jitter Tolerance Total Jitter Tolerance Bit Error Ratio Unit Interval AC Coupling Capacitor Symbol JD JDR JSIN JT BER UI CTX Min 0.37 0.55 0.1 0.65 — 799.92 5 Typ — — — — — 800 — Max — — — — 10-12 800.08 200 Unit UI p-p UI p-p UI p-p UI p-p Notes 1 1 1 1 — ps nF 2 3 Notes: 1. Measured at receiver. 2. Each UI is 800 ps ± 100 ppm. 3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs. 4. Refer to RapidIOTM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 38 Freescale Semiconductor USB VRX_DIFFp-p-max/2 Receiver Differential Input Voltage VRX_DIFFp-p-min/2 0 − VRX_DIFFp-p-min/2 − V RX_DIFFp-p-max/2 0 0.275 0.4 Time (UI) 0.6 0.725 1 Figure 20. SGMII Receiver Input Compliance Mask Figure 21. SGMII AC Test/Measurement Load 10 USB 10.1 USB Dual-Role Controllers This section provides the AC and DC electrical specifications for the USB-ULPI interface. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 39 USB 10.1.1 USB DC Electrical Characteristics Table 39. USB DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — LVDD – 0.2 — Max LVDD + 0.3 0.8 ±5 — 0.2 Unit V V μA V V Table 39 lists the DC electrical characteristics for the USB interface. High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Note: 1. The symbol VIN, in this case, represents the NV IN symbol referenced in Table 1 and Table 2. 10.1.2 USB AC Electrical Specifications Table 40. USB General Timing Parameters Parameter Symbol 1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 — 1 Max — — — 9 — Unit ns ns ns ns ns Notes 1, 2 1, 4 1, 4 1 1 Table 40 lists the general timing parameters of the USB-ULPI interface. USB clock cycle time Input setup to USB clock—all inputs Input hold to USB clock—all inputs USB clock to output valid—all outputs Output hold from USB clock—all outputs Notes: 1. The symbols used for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t USKHOX symbolizes USB timing (US) for the us clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from NVDD/2 of the rising edge of USB clock to 0.4 × NVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 22 and Figure 23 provide the AC test load and signals for the USB, respectively. Output Z0 = 50 Ω RL = 5 0 Ω NVDD/2 Figure 22. USB AC Test Load MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 40 Freescale Semiconductor USB USBDR_CLK tUSIVKH Input Signals tUSIXKH tUSKHOV Output Signals tUSKHOX Figure 23. USB Signals 10.2 On-Chip USB PHY This section provides the AC and DC electrical specifications for the USB PHY interface of the MPC8315E. For details refer to Tables 7-7 through 7-10, and Table 7-14 in the USB 2.0 Specifications document, and the pull-up/down resistors ECN updates, all available at www.usb.org. Table 41 provides the USB clock input (USB_CLK_IN) DC timing specifications. Table 41. USB_CLK_IN DC Electrical Characteristics Parameter Input high voltage Input low voltage Symbol VIH VIL Min 2.7 –0.3 Max NVDD + 0.3 0.4 Unit V V Table 42 provides the USB clock input (USB_CLK_IN) AC timing specifications. Table 42. USB_CLK_IN AC Timing Specifications Parameter/Condition Frequency range Clock frequency tolerance Reference clock duty cycle Total input jitter/Time interval error Conditions — — Measured at 1.6 V Peak to peak value measured with a second order high-pass filter of 500 KHz bandwidth Symbol fUSB_CLK_IN tCLK_TOL tCLK_DUTY tCLK_PJ Min — –0.05 40 — Typical 24 0 50 — Max — 0.05 60 200 Unit MHz % % ps MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 41 Local Bus 11 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8315E. 11.1 Local Bus DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the local bus interface. Table 43. DC Electrical Characteristics (when Operating at 3.3 V) Parameter Output high voltage (NVDD = min, IOH = –2 mA) Output low voltage (NVDD = min, IOL = 2 m A) Input high voltage Input low voltage Input high current (VIN = 0 V or VIN = NVDD) Symbol VOH VOL VIH VIL IIN Min NVDD – 0.2 — 2 –0.3 — Max — 0.2 NVDD + 0.3 0.8 ±5 Unit V V V V μA 11.2 Local Bus AC Electrical Specifications Table 44 describes the general timing parameters of the local bus interface of the MPC8315E. Table 44. Local Bus General Timing Parameters Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Symbol 1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 Min 15 7 1.0 1.5 3 2.5 Max — — — — — — Unit ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 42 Freescale Semiconductor Local Bus Table 44. Local Bus General Timing Parameters (continued) Parameter Local bus clock to output valid Local bus clock to output high impedance for LAD Symbol 1 tLBKHOV tLBKHOZ Min — — Max 3 4 Unit ns ns Notes 3 8 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from NVDD/2 of the rising/falling edge of LCLK0 to 0.4 × NVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10pF less than the load on LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD output pins. 8. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 24 provides the AC test load for the local bus. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 24. Local Bus AC Test Load MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 43 Local Bus Figure 25 through Figure 27 show the local bus signals. LCLK[n] tLBIVKH Input Signals: LAD[0:15] tLBIVKH Input Signal: LGTA tLBIXKH O utput Signals: tLBKHOV tLBIXKH tLBIXKH LBCTL/LBCKE/LOE/ Output Signals: LAD[0:15] tLBKHOV tLBKHOZ tLBOTOT LALE Figure 25. Local Bus Signals, Nonspecial Signals Only LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 44 Freescale Semiconductor JTAG LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 12 JTAG This section describes the DC and AC electrical specifications for the IEEE Std 1149.1™ (JTAG) interface. 12.1 JTAG DC Electrical Characteristics Table 45. JTAG Interface DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL Condition — — — IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.1 –0.3 — 2.4 — — Max NVDD + 0.3 0.8 ±5 — 0.5 0.4 Unit V V μA V V V Table 45 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 45 JTAG 12.2 JTAG AC Timing Specifications This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface. Table 46 provides the JTAG AC timing specifications as defined in Figure 29 through Figure 32. Table 46. JTAG AC Timing Specifications (Independent of SYS_CLKIN) 1 At recommended operating conditions (see Table 2) Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol 2 fJTG t JTG tJTKHKL tJTGR, tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ Min 0 30 15 0 25 4 4 10 10 2 2 2 2 2 2 Max 33.3 — — 2 — — — Unit MHz ns ns ns ns ns Notes — — — — 3 4 ns — — ns 11 11 ns — — ns 19 9 4 5 5 5, 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Table 28). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 46 Freescale Semiconductor JTAG Figure 28 provides the AC test load for TDO and the boundary-scan outputs of the MPC8315E. Output Z0 = 50 Ω NVDD/2 R L = 50 Ω Figure 28. AC Test Load for the JTAG Interface Figure 29 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (NVDD/2) VM VM tJTGR tJTGF Figure 29. JTAG Clock Input Timing Diagram Figure 30 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (NVDD/2) VM Figure 30. TRST Timing Diagram Figure 31 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (NVDD/2) Output Data Valid Input Data Valid VM Figure 31. Boundary-Scan Timing Diagram MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 47 I2C Figure 32 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (NVDD/2) Output Data Valid Input Data Valid VM Figure 32. Test Access Port Timing Diagram 13 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8315E. 13.1 I2C DC Electrical Characteristics Table 47. I2C DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the I2C interface. At recommended operating conditions with NVDD of 3.3 V ± 300 mv Parameter Input high voltage level Input low voltage level Low level output voltage High level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Symbol VIH VIL VOL VOH tI2KLKV tI2KHKL CI Min 0.7 × NVDD –0.3 0 0.8 × NVDD 20 + 0.1 × CB 0 — Max NVDD + 0.3 0.3 × NVDD 0.2 × NVDD NVDD + 0.3 250 50 10 Unit V V V V ns ns pF Notes — — 1 — 2 3 — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 48 Freescale Semiconductor I2C Table 47. I2C DC Electrical Characteristics (continued) At recommended operating conditions with NVDD of 3.3 V ± 300 mv Parameter Input current (0 V ≤VIN ≤ NVDD) Symbol IIN Min — Max ±5 Unit μA Notes 4 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. See the MPC8315E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off. 13.2 I2C AC Electrical Specifications Table 48. I2C AC Electrical Specifications Table 48 provides the AC timing parameters for the I2C interface. All values refer to VIH (min) and VIL (max) levels (see Table 47) Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Symbol 1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 — 02 Max 400 — — — — — — 0.9 3 300 — — — Unit kHz μs μs μs μs ns μs tI2CF 4 tI2PVKH tI2KHDX VNL — 0.6 1.3 0.1 × NVDD ns μs μs V MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 49 PCI Table 48. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 47) Parameter Noise margin at the HIGH level for each connected device (including hysteresis) Symbol 1 VNH Min 0.2 × NVDD Max — Unit V Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8315E provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. MPC8315E does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC parameter. Figure 33 provides the AC test load for the I2C. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 33. I2C AC Test Load Figure 34 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 34. I2C Bus AC Timing Diagram 14 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8315E. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 50 Freescale Semiconductor PCI 14.1 PCI DC Electrical Characteristics Table 49. PCI DC Electrical Characteristics 1 Parameter Symbol VIH VIL VOH VOL IIN Test Condition VOUT ≥ VOH (min) or VOUT ≤ VOL (max) NVDD = min, IOH = –500 μA NVDD = min, IOL = 1500 μA 0 V ≤ VIN ≤ NVDD Min 0.5 x NVDD –0.5 0.9 x NVDD — — Max NVDD + 0.3 0.3 × NVDD — 0.1 x NVDD ± 10 Unit V V V V μA Table 49 provides the DC electrical characteristics for the PCI interface. High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Note: 1. Note that the symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2. 14.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8315E is configured as a host or agent device. Table 50 shows the PCI AC timing specifications at 66 MHz. . Table 50. PCI AC Timing Specifications at 66 MHz Parameter Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min — 1 — 3.3 0 Max 6.0 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock Notes: 1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 51 PCI Table 51 shows the PCI AC Timing Specifications at 33 MHz. Table 51. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min — 2 — 4.0 0 Max 11 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 Notes: 1. Note that the symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 35 provides the AC test load for PCI. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 35. PCI AC Test Load Figure 36 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 36. PCI Input AC Timing Measurement Conditions MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 52 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Figure 37 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 37. PCI Output AC Timing Measurement Condition 15 High-Speed Serial Interfaces (HSSI) This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 15.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (TXn and TXn) or a receiver input (RXn and RXn). Each signal swings between A Volts and B Volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-Ended Swing The transmitter output signals and the receiver input signals TXn, TXn, RXn and RXn each have a peak-to-peak swing of A – B Volts. This is also referred as each signal wire’s Single-Ended Swing. 2. Differential Output Voltage, VOD (or Differential Output Swing): The Differential Output Voltage (or Swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VTXn – VTXn. The VOD value can be either positive or negative. 3. Differential Input Voltage, VID (or Differential Input Swing): The Differential Input Voltage (or Swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VRXn – VRXn. The VID value can be either positive or negative. 4. Differential Peak Voltage, VDIFFp MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 53 High-Speed Serial Interfaces (HSSI) The peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak Voltage, VDIFFp = |A – B| Volts. 5. Differential Peak-to-Peak, VDIFFp-p Because the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B) Volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as Differential Peak-to-Peak Voltage, VDIFFp-p = 2*VDIFFp = 2 * |(A - B)| Volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2*|VOD|. 6. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (TXn, for example) from the non-inverting signal (TXn, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 47 as an example for differential waveform. 7. Common Mode Voltage, Vcm The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VTXn + VTXn )/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It’s also referred as the DC offset in some occasion. TXn or RXn A Volts Vcm = (A + B) / 2 TXn or RXn B Volts Differential Swing, VID or VOD = A - B Differential Peak Voltage, VDIFFp = |A - B| Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown) Figure 38. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 54 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. 15.2 SerDes Reference Clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK for PCI Express and SGMII interface. The following sections describe the SerDes reference clock requirements and some application information. 15.2.1 SerDes Reference Clock Receiver Characteristics Figure 39 shows a receiver reference diagram of the SerDes reference clocks. • The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2. • SerDes Reference Clock Receiver Reference Circuit Structure — The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown in Figure 39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω termination to XCOREVSS followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. • The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4V (0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above XCOREVSS. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the differential input has a single-ended swing from 0V to 800mV with the common mode voltage at 400mV. — If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 ohms to XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 55 High-Speed Serial Interfaces (HSSI) 50 Ω SD_REF_CLK Input Amp SD_REF_CLK 50 Ω Figure 39. Receiver of SerDes Reference Clocks 15.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8315E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in section 15.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement for DC-coupled connection scheme. — For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to XCOREVSS. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (XCOREVSS). Figure 41 shows the SerDes reference clock input requirement for AC-coupled connection scheme. • Single-ended Mode — The reference clock can also be single-ended. The SD_REF_CLK input amplitude (single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax) with SD_REF_CLK either left unconnected or tied to ground. — The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled externally. For the best noise performance, the reference of the clock could be DC MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 56 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use. 200 mV < Input Amplitude or Differential Peak < 800 mV Vmax < 800 mV SD_REF_CLK 100 mV < Vcm < 400 mV SD_REF_CLK Vmin > 0 V Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200 mV < Input Amplitude or Differential Peak < 800 mV SD_REF_CLK Vmax < Vcm + 400 mV Vcm SD_REF_CLK Vmin > Vcm – 400 mV Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV < SD_REF_CLK Input Amplitude < 800 mV SD_REF_CLK 0V SD_REF_CLK Figure 42. Single-Ended Reference Clock Input DC Requirements 15.2.3 Interfacing With Other Differential Signaling Levels With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 57 High-Speed Serial Interfaces (HSSI) Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection. LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 43 to Figure 46 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it’s very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8315E SerDes reference clock receiver requirement provided in this document. Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8315E SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω SD_REF_CLK 50 Ω MPC8315E Clock Driver 33 Ω CLK_Out 100 Ω differential PWB trace SerDes Refer. CLK Receiver SD_REF_CLK 50 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. Clock driver vendor dependent source termination resistor Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver. Since LVDS clock driver’s common mode voltage is higher than the MPC8315E SerDes reference clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 58 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component. LVDS CLK Driver Chip CLK_Out 10 nF SD_REF_CLK 50 Ω MPC8315E Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver CLK_Out 10 nF SD_REF_CLK 50 Ω Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with MPC8315E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45 assumes that the LVPECL clock driver’s output impedance is 50Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140Ω to 240Ω depending on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8315E SerDes reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 59 High-Speed Serial Interfaces (HSSI) LVPECL CLK Driver Chip CLK_Out R2 10 nF SD_REF_CLK MPC8315E 50 Ω Clock Driver R1 100 Ω differential PWB trace R2 10 nF SD_REF_CLK R1 SerDes Refer. CLK Receiver CLK_Out 50 Ω Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8315E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 33 Ω CLK_Out SD_REF_CLK 50 Ω MPC8315E Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver 50 Ω SD_REF_CLK 50 Ω Figure 46. Single-Ended Connection (Reference Only) 15.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 60 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Table 52 describes some AC parameters common to SGMIIPCI Express protocols. Table 52. SerDes Reference Clock Common AC Parameters At recommended operating conditions with XCOREVDD= 1.0V ± 5% Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage Rising edge rate (SDn_REF_CLK) to falling edge rate (SDn_REF_CLK) matching Symbol Rise Edge Rate Fall Edge Rate VIH VIL Rise-Fall Matching Min 1.0 1.0 +200 — — Max 4.0 4.0 — –200 20 Unit V/ns V/ns mV mV % Notes 2, 3 2, 3 2 2 1, 4 Notes: 1. Measurement taken from single ended waveform. 2. Measurement taken from differential waveform. 3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 47. 4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 48. VIH = +200 0.0 V VIL = –200 SDn_REF_CL K minus Figure 47. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK SDn_REF_CLK Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 61 PCI Express The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based on application usage. Refer to the following sections for detailed information: • Section 9.5.2, “AC Requirements for SGMII SD_REF_CLK and SD_REF_CLK” • Section 16.2, “AC Requirements for PCI Express SerDes Clocks” 15.2.4.1 Spread Spectrum Clock SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 15.3 SerDes Transmitter and Receiver Reference Circuits TXn 50 Ω Transmitter 50 Ω TXn RXn 50 Ω 50 Ω Receiver RXn Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 49. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below (PCI Express or SGMII) in this document based on the application usage: • Section 9.5, “SGMII Interface Electrical Characteristics” • Section 16, “PCI Express” Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. 16 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8315E. 16.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 15.2, “SerDes Reference Clocks.” MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 62 Freescale Semiconductor PCI Express 16.2 AC Requirements for PCI Express SerDes Clocks Table 53. SD_REF_CLK and SD_REF_CLK AC Requirements Table 53 lists the PCI Express SerDes clock AC requirements. Symbol tREF tREFCJ tREFPJ REFCLK cycle time Parameter Description Min — — –50 Typ 10 — — Max — 100 50 Units ns ps ps Notes — — — REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles. Phase jitter. Deviation in edge location with respect to mean edge location. 16.3 Clocking Dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. 16.4 Physical Layer Specifications Following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer please use the PCI Express Base Specification, Rev. 1.0a. 16.4.1 Differential Transmitter (TX) Output Table 54 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 54. Differential Transmitter (TX) Output Specifications Parameter Unit interval Symbol UI Comments Min Typical 400 Max 400.12 Units ps Notes 1 Each UI is 400 ps ± 300 ppm. 399.88 UI does not account for Spread Spectrum Clock dictated variations. VTX-DIFFp-p = 2*|VTX-D+ VTX-D-| Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. The maximum Transmitter jitter can be derived as TTX-MAX-JITTER = 1 - UTX-EYE= 0.3 UI. 0.8 –3.0 Differential peak-to-peak output voltage De-Emphasized differential output voltage (ratio) VTX-DIFFp-p VTX-DE-RATIO — –3.5 1.2 -4.0 V dB 2 2 Minimum TX eye width TTX-EYE 0.70 — — UI 2, 3 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 63 PCI Express Table 54. Differential Transmitter (TX) Output Specifications (continued) Parameter Maximum time between the jitter median and maximum deviation from the median Symbol TTX-EYE-MEDIAN-toMAX-JITTER Comments Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. — VTX-CM-ACp = RMS(|VTXD+ + VTXD-|/2 - VTX-CM-DC) VTX-CM-DC = DC(avg) of |VTX-D+ + VTX-D-|/2 |VTX-CM-DC (during L0) VTX-CM-Idle-DC (During Electrical Idle) | 175 mV 0.4 UI = TRX-EYE-MIN Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification 16.5.1 Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in Figure 52. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 70 Freescale Semiconductor Serial ATA (SATA) Figure 52. Compliance Test/Measurement Load 17 Serial ATA (SATA) The serial ATA (SATA) of the MPC8315E is designed to comply with Serial ATA 2.5 Specification. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. 17.1 Requirements for SATA REF_CLK The reference clock for MPC8315E is a single ended input clock required for the SATA Interface operation. The AC requirements for the SATA reference clock are listed in the Table 56. Table 56. Reference Clock Input Requirements Parameter Frequency range Symbol tCLK_REF tCLK_TOL Conditions — Min 50 Typical 75 Max 150 Unit MHz Notes 1 Clock frequency tolerance — -350 0 +350 ppm — Input High Voltage VCLK_INHI — 2.0 — — V — Input Low Voltage VCLK_INLo — — — 0.7 V — Reference clock rise and fall time tCLK_RISE/ 20% to 80% of nominal amplitude tCLK_FALL Reference clock duty cycle tCLK_DUTY measured at 1.6V — 40 — 50 2 60 ns % — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 71 Serial ATA (SATA) Table 56. Reference Clock Input Requirements (continued) Parameter Total reference clock jitter, phase noise integration from 100 Hz to 3 MHz Symbol tCLK_PJ Conditions peak to peak jitter at refClk input Min — Typical — Max 100 Unit ps Notes — Notes: 1. Only 50/75/100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system. TH Ref_CLK TL Figure 53. Reference Clock Timing Waveform 17.2 SATA AC Electrical Characteristics Table 57. SATA AC Electrical Characteristics Parameter Symbol Min Typical Max Units Notes — tCH_SPEED — — TUI 666.4333 333.3333 1.5 3.0 — — ps Gbps — Table 57 provides the general AC parameters for the SATA interface. Channel Speed 1.5G 3.0G Unit Interval 1.5G 3.0G MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 72 Freescale Semiconductor Timers 17.3 Out-of-Band (OOB) Electrical Characteristics Table 59 provides the Out-of-Band (OOB) Electrical characteristics for the Sata interface of the MPC8315. Table 59. Out-of-Band (OOB) Electrical Characteristics Parameter OOB Signal Detection Threshhold 1.5G 3.0G UI During OOB Signaling COMINIT/ COMRESET and COMWAKE Transmit Burst Length COMINIT/ COMRESET Transmit Gap Length COMWAKE Transmit Gap Length Symbol Min Typical Max Units Notes — VSATA_OOBDETE TSATA_UIOOB TSATA_UIOOBTXB TSATA_UIOOBTXGap — TSATA_UIOOBTX WakeGap 50 75 — — 100 125 666.67 160 480 160 200 200 — — — — mVp-p ps UI — UI — UI — — — 18 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8315E. 18.1 Timers DC Electrical Characteristics Table 60 provides the DC electrical characteristics for the timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 60. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ NVDD Min 2.4 — — 2.1 –0.3 — Max — 0.5 0.4 NVDD + 0.3 0.8 ±5 Unit V V V V V μA MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 73 GPIO 18.2 Timers AC Timing Specifications Table 61. Timers Input AC Timing Specifications Characteristic Symbol 1 tTIWID Min 20 Unit ns Table 61 provides the timers input and output AC timing specifications. Timers inputs—minimum pulse width Notes: 1. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers input are required to be valid for at least tTIWID ns to ensure proper operation. Figure 54 provides the AC test load for the Timers. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 54. Timers AC Test Load 19 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8315E. 19.1 GPIO DC Electrical Characteristics Table 62. GPIO DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ NVDD Min 2.4 — — 2.1 –0.3 — Max — 0.5 0.4 NVDD + 0.3 0.8 ±5 Unit V V V V V μA Table 62 provides the DC electrical characteristics for the GPIO. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 74 Freescale Semiconductor IPIC 19.2 GPIO AC Timing Specifications Table 63. GPIO Input AC Timing Specifications Characteristic Symbol 1 tPIWID Min 20 Unit ns Table 63 provides the GPIO input and output AC timing specifications. GPIO inputs—minimum pulse width Notes: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. Figure 55 provides the AC test load for the GPIO. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 55. GPIO AC Test Load 20 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8315E. 20.1 IPIC DC Electrical Characteristics Table 64. IPIC DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL Condition — — — IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.1 –0.3 — 2.4 — — Max NVDD + 0.3 0.8 ±5 — 0.5 0.4 Unit V V μA V V V Table 64 provides the DC electrical characteristics for the external interrupt pins. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 75 SPI 20.2 IPIC AC Timing Specifications Table 65. IPIC Input AC Timing Specifications Characteristic Symbol 1 tPIWID Min 20 Unit ns Table 65 provides the IPIC input and output AC timing specifications. IPIC inputs—minimum pulse width Note: 1. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 21 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8315E. 21.1 SPI DC Electrical Characteristics Table 66. SPI DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOH VOL VOL Condition — — — IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA Min 2.1 –0.3 — 2.4 — — Max NVDD + 0.3 0.8 ±5 — 0.5 0.4 Unit V V μA V V V Table 66 provides the DC electrical characteristics for the SPI. Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage 21.2 SPI AC Timing Specifications Table 67. SPI AC Timing Specifications 1 Characteristic Symbol 2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH Min — 0.5 — 2 6 0 8.5 — — — Max 6 Unit ns ns ns ns ns ns Table 67 and provide the SPI input and output AC timing specifications. SPI outputs valid—master mode (internal clock) delay SPI outputs hold—master mode (internal clock) delay SPI outputs valid—slave mode (external clock) delay SPI outputs hold—slave mode (external clock) delay SPI inputs—master mode (internal clock) input setup time SPI inputs—master mode (internal clock)input hold time MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 76 Freescale Semiconductor SPI Table 67. SPI AC Timing Specifications 1 Characteristic SPI inputs—slave mode (external clock) input setup time SPI inputs—slave mode (external clock) input hold time Symbol 2 tNEIVKH tNEIXKH Min 4 2 Max — — Unit ns ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). Figure 56 provides the AC test load for the SPI. Output Z0 = 50 Ω NVDD/2 RL = 5 0 Ω Figure 56. SPI AC Test Load Figure 57 and Figure 58 represents the AC timing from Table 67. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 57 shows the SPI timing in slave mode (external clock). SPICLK (Input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOV Note: The clock edge is selectable on SPI. Figure 57. SPI AC Timing in Slave Mode (External Clock) Diagram MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 77 TDM Figure 58 shows the SPI timing in master mode (internal clock). SPICLK (Output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOV Note: The clock edge is selectable on SPI. Figure 58. SPI AC Timing in Master Mode (Internal Clock) Diagram 22 TDM This section describes the DC and AC electrical specifications for the TDM of the MPC8315E. 22.1 TDM DC Electrical Characteristics Table 68. TDM DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ NVDD Min 2.4 — — 2.1 –0.3 — Max — 0.5 0.4 NVDD + 0.3 0.8 ±5 Unit V V V V V μA Table 68 provides the DC electrical characteristics TDM. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 22.2 TDM AC Electrical Characteristics Table 69. TDM AC Timing specifications Parameter/Condition Symbol tDM tDM_HIGH tDM_LOW tDMIVKH tDMRDIXKH Min 20.0 8.0 8.0 3.0 3.5 Max — — — — — Units ns ns ns ns ns Table 69 provides the TDM AC timing specifications. TDMxRCK/TDMxTCK TDMxRCK/TDMxTCK high pulse width TDMxRCK/TDMxTCK low pulse width TDM all input setup time TDMxRD hold time MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 78 Freescale Semiconductor TDM Table 69. TDM AC Timing specifications Parameter/Condition TDMxTFS/TDMxRFS input hold time TDMxTCK High to TDMxTD output active TDMxTCK High to TDMxTD output valid TDMxTD hold time TDMxTCK High to TDMxTD output high impedance TDMxTFS/TDMxRFS output valid TDMxTFS/TDMxRFS output hold time Symbol tDMFSIXKH tDM_OUTAC tDMTKHOV tDMTKHOX tDM_OUTHI tDMFSKHOV tDMFSKHOX Min 2.0 4.0 — 2.0 — — 2.5 Max — — 14.0 — 10.0 13.5 — Units ns ns ns ns ns ns ns Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTDMIVKH symbolizes TDM timing (DM) with respect to the time the input signals (I) reach the valid state (V) relative to the TDM Clock, tTC, reference (K) going to the high (H) state or setup time. Also, output signals (O), hold (X). 2. Output values are based on 30 pF capacitive load. 3. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. Figure 51 shows the TDM receive signal timing. tDM tDM_HIGH TDMxRCK tDM_LOW tDMIVKH TDMxRD tDMRDIXKH tDMIVKH TDMxRFS tDMFSIXKH tDMFSKHOV ~ ~ TDMxRFS (output) tDMFSKHOX Figure 59. TDM Receive Signals MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 79 Package and Pin Listings Figure 60 shows the TDM transmit signal timing. tDM tDM_HIGH TDMxTCK tDM_LOW tDM_OUTHI tDMTKHOV TDMxTD TDMxRCK tDMFSKHOV TDMxTFS (output) ~~ ~~ tDM_OUTAC tDMTKHOX tDMFSKHOX tDMIVKH TDMxTFS (input) tDMFSIXKH Figure 60. TDM Transmit Signals 23 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8315E is available in a thermally enhanced plastic ball grid array (TEPBGA II), see Section 23.1, “Package Parameters for the MPC8315E TEPBGA II,” and Section 23.2, “Mechanical Dimensions of the TEPBGA II,” for information on the TEPBGA II. 23.1 Package Parameters for the MPC8315E TEPBGA II The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, TEPBGA II. Package outline 29 mm × 29 mm Interconnects 620 Pitch 1 mm Module height (typical) 2.23 mm Solder balls 96.5 Sn/3.5 Ag (VR package) Ball diameter (typical) 0.6 mm MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 80 Freescale Semiconductor Package and Pin Listings 23.2 Mechanical Dimensions of the TEPBGA II Figure 61 the mechanical dimensions and bottom surface nomenclature of the 620-pin TEPBGA II package. Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 61. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II 23.3 Pinout Listings Table 70 provides the pin-out listing for the TEPBGA II package. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 81 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing Signal Package Pin Number DDR Memory Controller Interface MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] MEMC_MDQ[4] MEMC_MDQ[5] MEMC_MDQ[6] MEMC_MDQ[7] MEMC_MDQ[8] MEMC_MDQ[9] MEMC_MDQ[10] MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] AF16 AE17 AH17 AG17 AG18 AH18 AD18 AF19 AH19 AD19 AG20 AH20 AH21 AE21 AH22 AD21 AG10 AH9 AH8 AD11 AH7 AG7 AF8 AD10 AE9 AH6 AH5 AG6 AH4 AE6 AD8 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Pin Type Power Supply Notes MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 82 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal MEMC_MDQ[31] MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS [0] MEMC_MCS [1] Package Pin Number AF5 AE18 AE20 AE10 AF6 AF17 AG21 AG9 AF7 AH16 AH15 AG15 AD15 AE15 AH14 AG14 AF14 AE14 AH13 AH12 AF13 AD13 AG12 AH11 AH10 AE12 AF11 AE5 AD7 AG4 AH3 AD5 Pin Type I/O O O O O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 83 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal MEMC_MCKE MEMC_MCK[0] MEMC_MCK [0] MEMC_MCK[1] MEMC_MCK [1] MEMC_MODT[0] MEMC_MODT[1] MEMC_MVREF Package Pin Number AE4 AF4 AF3 AF1 AE1 AE3 AD4 AD12 Local Bus Controller Interface LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 AB28 AB27 AC28 AA24 AC27 AD28 AB25 AC26 AD27 AB24 AE28 AE27 AE26 AF28 AC24 AD25 V24 V25 W26 W28 U24 W24 Y28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF — — — — — — — — — — — — — — — — — — — — — — — Pin Type O O O O O O O I Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes 3 — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 84 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal LA23 LA24 LA25 LCS[0] LCS[1] LCS[2] LCS[3] LWE [0] /LFWE/LBS LWE [1] LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LFRE/LOE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 LCLK1 Package Pin Number AH23 AH24 AG23 AD22 AF25 AG24 AF24 AE23 AG26 AH26 AF26 Y27 AA28 Y25 Y24 AA26 AF22 AH25 AD24 DUART UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS[1]/MSRCID2 (DDR ID)/LSRCID2 UART_RTS[1]/MSRCID3 (DDR ID)/LSRCID3 UART_SOUT2/MSRCID4 (DDR ID)/LSRCID4 UART_SIN2/MDVAL (DDR ID)/LDVAL UART_CTS[2] UART_RTS[2] C15 B16 D16 B17 A16 C16 A17 A18 I2C interface IIC_SDA/CKSTOP_OUT IIC_SCL/CKSTOP_IN N1 N2 I/O I/O NVDD4_OFF NVDD4_OFF 2 2 O I/O I/O O O I/O I O NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF — — — — — — — — Pin Type O O O O O O O O O O O O O O O I/O O O O Power Supply NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF NVDD3_OFF Notes — — — — — — — — — — — — — — — 2 — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 85 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal Package Pin Number Interrupts MCP_OUT IRQ [0]/MCP_IN IRQ [1] IRQ [2] IRQ [3] IRQ [4] IRQ [5]/CORE_SRESET_IN IRQ [6] /CKSTOP_OUT IRQ [7]/CKSTOP_IN W1 Y3 E1 A7 AA1 Y5 AA2 AA4 AA5 Configuration CFG_CLKIN_DIV EXT_PWR_CTRL PMC_PWR_OK JTAG TCK TDI TDO TMS TRST TDM GPIO_18/TDM_RCK GPIO_20/TDM_RD GPIO_19/TDM_RFS GPIO_21/TDM_TCK GPIO_23/TDM_TD GPIO_22/TDM_TFS SATA PINRXMINUSA PINRXMINUSB PINRXPLUSA N28 U28 M28 I I I VDD1IO VDD1IO VDD1IO — — — AB1 AC1 AB3 AB5 AC3 AC2 I/O I/O I/O I/O I/O I/O NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF — — — — — — E5 B4 C4 C3 C2 I I O I I NVDD1_ON NVDD1_ON NVDD1_ON NVDD1_ON NVDD1_ON — 4 3 4 4 A5 D3 D4 I O I NVDD1_ON NVDD1_ON — — — — O I I I I I I I/O I NVDD1_OFF NVDD1_OFF NVDD1_ON NVDD1_ON NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF 2 — — — — — — — — Pin Type Power Supply Notes MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 86 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PINRXPLUSB PINTXMINUSA PINTXMINUSB PINTXPLUSA PINTXPLUSB SATA_ANAVIZ SATA_CLK_IN SATA_VDD SATA_VDD SATA_VSS SATA_VSS VSSRESREF RESREF VDD33ANA VDD33PLL TEST TEST_MODE DEBUG QUIESCE B5 System Control HRESET PORESET Clocks SYS_XTAL_IN SYS_XTAL_OUT SYS_CLK_IN USB_XTAL_IN USB_XTAL_OUT USB_CLK_IN PCI_SYNC_OUT RTC_CLK L27 J28 K28 A15 B14 B15 J27 K26 I O I I O I O I NVDD2_ON NVDD2_ON NVDD2_ON NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_ON NVDD2_ON — — — — — — 3 — B6 A6 I/O I NVDD1_ON NVDD1_ON 1 — O NVDD1_ON — D6 I NVDD1_ON 6 Package Pin Number T28 M25 P26 N25 R26 U26 V27 N27 U23 M27 V28 T26 T25 U27 T27 Pin Type I O O O O O I I I I I I I I I Power Supply VDD1IO VDD1IO VDD1IO VDD1IO VDD1IO — NVDD3_OFF — — — — — — — — Notes — — — — — — — — — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 87 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PCI_SYNC_IN MISC AVDD1 AVDD2 THERM0 DMA_DACK0/GPIO_13 DMA_DREQ0/GPIO_12 DMA_DONE0/GPIO_14 NC, No Connect NC, No Connect PCI PCI_INTA PCI_RESET_OUT PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] B18 A20 J25 J24 K24 H27 H28 H26 G27 G28 F26 F28 G25 F27 E27 E28 D28 D27 B25 D24 B26 O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF — — — — — — — — — — — — — — — — — — — — — AC15 M23 L25 AC4 AD1 AD2 A2 U25 I I I I/O I/O I/O — — — — NVDD2_ON NVDD1_OFF NVDD1_OFF NVDD1_OFF — — — — 7 — — — — — Package Pin Number K27 Pin Type I Power Supply NVDD2_ON Notes — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 88 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_C/BE[0] PCI_C/BE[1] PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM Package Pin Number C24 A26 E20 A23 C22 E19 A22 C20 B21 D19 A19 A21 B19 H24 C27 A25 E21 G24 C28 A24 D25 D23 E22 D26 C25 D21 E18 C18 E17 B20 D17 E15 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I I/O O O Power Supply NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF Notes — — — — — — — — — — — — — — — — — — 5 5 5 5 5 — 5 5 — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 89 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_PME Package Pin Number L24 E23 F24 E25 B23 ETSEC1/_USBULPI GPIO_24/TSEC1_COL/USBDR_TXDRXD0 GPIO_25/TSEC1_CRS/USBDR_TXDRXD1 TSEC1_GTX_CLK/USBDR_TXDRXD2 TSEC1_RX_CLK/USBDR_TXDRXD3 TSCE1_RX_DV/USBDR_TXDRXD4 TSEC1_RXD[3]/USBDR_TXDRXD5 TSEC1_RXD[2]/USBDR_TXDRXD6 TSEC1_RXD[1]/USBDR_TXDRXD7/TSEC_TMR_CLK TSEC1_RXD[0]/USBDR_NXT/TSEC_TMR_TRIG1 TSEC1_RX_ER/USBDR_DIR/TSEC_TMR_TRIG2 TSEC1_TX_CLK/USBDR_CLK GPIO_28/TSEC1_TXD[3]/TSEC_TMR_GCLK GPIO_29/TSEC1_TXD[2]/TSEC_TMR_PP1 GPIO_30/TSEC1_TXD[1]/TSEC_TMR_PP2 TSEC1_TXD[0]/USBDR_STP/TSEC_TMR_PP3 GPIO_31/TSEC1_TX_EN/TSEC_TMR_ALARM1 TSEC1_TX_ER/TSEC_TMR_ALARM2 TSEC_GTX_CLK125 TSEC_MDC/LB_POR_CFG_BOOT_ECC TSEC_MDIO J1 H1 K5 J4 J2 G1 H3 J5 H2 H5 G2 F3 F2 F1 G4 F4 G5 D1 E3 E2 ETSEC2 GPIO_26/TSEC2_COL GPIO_27/TSEC2_CRS TSEC2_GTX_CLK TSEC2_RX_CLK TSCE2_RX_DV A8 E9 B10 B8 C9 I/O I/O O I I LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON — — — — — I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I/O I/O O I/O O I I/O I/O LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF LVDD1_OFF NVDD1_ON NVDD1_ON NVDD1_ON — — 3 — — — — — — — — — — — — — — — 9 2 Pin Type I O O O I/O Power Supply NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF NVDD2_OFF Notes — — — — 2 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 90 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal TSEC2_RXD[3] TSEC2_RXD[2] TSEC2_RXD[1] TSEC2_RXD[0] TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TXD[3]/CFG_RESET_SOURCE[0] TSEC2_TXD[2]/CFG_RESET_SOURCE[1] TSEC2_TXD[1]/CFG_RESET_SOURCE[2] TSEC2_TXD[0]/CFG_RESET_SOURCE[3] TSEC2_TX_EN TSEC2_TX_ER Package Pin Number C10 D10 A9 B9 A10 D8 D11 C7 E8 B7 D12 B11 SGMII / PCIe PHY TXA TXA RXA RXA TXB TXB RXB RXB SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SDAVDD SD_PLL_TPA_ANA SDAVSS P4 N4 R1 P1 U4 V4 U1 V1 N3 R4 R5 T2 V5 T3 T4 T5 USB Phy USB_DP USB_DM A11 A12 I/O I/O USB_VDDA USB_VDDA — — O O I I O O I I I I I O I I O I XPADVDD XPADVDD XCOREVDD XCOREVDD XPADVDD XPADVDD XCOREVDD XCOREVDD XCOREVDD XCOREVDD XCOREVDD — XPADVDD — — — — — — — — — — — — — — — — — — — Pin Type I I I I I I I/O I/O I/O I/O O O Power Supply LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON LVDD2_ON Notes — — — — — — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 91 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal USB_VBUS USB_TPA USB_RBIAS USB_PLL_PWR3 USB_PLL_GND0 & USB_PLL_GND1 USB_PLL_PWR1 USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA GPIO GPIO_0/DMA_DREQ1/GTM1_TOUT1 GPIO_1/DMA_DACK1/GTM1_TIN2/GTM2_TIN1 GPIO_2/DMA_DONE1/GTM1_TGATE2/GTM2_TGAT E1 GPIO_3/GTM1_TIN3/GTM2_TIN4 GPIO_4/GTM1_TGATE3/GTM2_TGATE4 GPIO_5/GTM1_TOUT3/GTM2_TOUT1 GPIO_6/GTM1_TIN4/GTM2_TIN3 GPIO_7/GTM1_TGATE4/GTM2_TGATE3 GPIO_8/USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_ TIN2 GPIO_9/USBDR_PWRFAULT/GTM1_TGATE1/GTM2_ TGATE2 GPIO_10/USBDR_PCTL0/GTM1_TOUT2/GTM2_TOU T1 GPIO_11/USBDR_PCTL1/GTM1_TOUT4/GTM2_TOU T3 SPI SPIMOSI/GPIO_15 SPIMISO/GPIO_16 SPICLK SPISEL/GPIO_17 W3 W4 Y1 W2 I/O I/O I/O I/O NVDD1_OFF NVDD1_OFF NVDD1_OFF NVDD1_OFF — — — — C5 A4 K3 K1 K2 L5 L3 L1 M1 M2 M5 M4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NVDD1_ON NVDD1_ON NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF NVDD4_OFF — — — — — — — — — — — — Package Pin Number C12 A14 D14 A13 D13 B13 E14 C14 E13 E12 Pin Type I O I I I I I I I I Power Supply — — — — — — — — — — Notes — — 8 — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 92 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal Package Pin Number Power and Ground Supplies GVDD Y11, Y12, Y14, Y15, Y17, AC8, AC11, AC14, AC17, AD6, AD9, AD17, AE8, AE13, AE19, AF10, AF15, AF21, AG2, AG3, AG8, AG13, AG19, AH2 H6, J3, L6, L9, M9 C11, D9, E10, F11, J12 U9, V9, W10, Y4, Y6, AA3, AB4 B1, B2, C1, D5, E7, F5, F9, J11, K10 B22, B27, C19, E16, F15, F18, F21, F25, H25, J17, J18, J23, L20, M20 L26, N19 U20, V20, V23, V26, W19, Y18, Y26, AA23, AA25, AC20, AC25, AD23, AE25, AG25, AG27 K4, L2, M6, N10 J15, K15, K16, K17, K18, K19, L10, L19, M10, T10, U10, U19, V10, V19, W11, W12, W13, W14, W15, W16, W17, W18 P23, R23, T19 M26, N26, P28, R28 J14, K11, K12, K13, K14, M19 I — — Pin Type Power Supply Notes LVDD1_OFF LVDD2_ON NVDD1_OFF NVDD1_ON NVDD2_OFF I I I I I — — — — — — — — — — NVDD2_ON NVDD3_OFF I I — — — — NVDD4_OFF VDD I I — — — — VDD1ANA VDD1IO VDDC I I I — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 93 Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal VSS Package Pin Number A3, A27, B3, B12, B24, B28, C6, C8, C13, C17, C21, C23, C26, D2, D7, D15, D18, D20, D22, E4, E6, E11, E24, E26, F8, F12, F14, F17, F20, G3, G26, H4, H23, J6, J26, K25, L4, L11, L12, L13, L14, L15, L16, L17, L18, L23, L28, M3, M11, M12, M13, M14, M15, M16, M17, M18, N5, N11, N12, N13, N14, N15, N16, N17, N18, P6, P11, P12, P13, P14, P15, P16, P17, P18, R6, R11, R12, R13, R14, R15, R16, R17, R18, T11, T12, T13, T14, T15, T16, T17, T18, U5, U6, U11, U12, U13, U14, U15, U16, U17, U18, V6, V11, V12, V13, V14, V15, V16, V17, V18, W5, W25, W27, Y2, Y23, AA6, AA27, AB2, AB26, AC5, AC9, AC12, AC18, AC21, AD3, AD14, AD16, AD20, AD26, AE2, AE7, AE11, AE16, AE22, AE24, AF2, AF9, AF12, AF18, AF20, AF23, AF27, AG1, AG5, AG11, AG16, AG22, AG28, AH27 P24, R19, R20, R24 M24, N24, P19, P20, P25, P27, R25, R27, T24 P2, P10, R2, T1 R3, R10, U2, V2 P3, R9, U3 Pin Type I Power Supply — Notes — VSS1ANA VSS1IO XCOREVDD XCOREVSS XPADVDD I I I I I — — — — — — — — — — MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 94 Freescale Semiconductor Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal XPADVSS Package Pin Number P5, P9, V3 Pin Type I Power Supply — Notes — Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to NVDD. 2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to NVDD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation. 6. This pin must always be tied to VSS. 7. Thermal sensitive resistor. 8. This pin should be connected to USB_VSSA_BIAS through 10K precision resistor. 9. The LB_POR_CFG_BOOT_ECC functionality for this pin is only available in MPC8315E revision 1.1. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a tri-state buffer is needed. 10.This pin should be connected to an external 2.7 K ±1% resistor connected to VSS. The resistor should be placed as close as possible to the input. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 95 Clocking 24 Clocking Figure 62 shows the internal distribution of clocks within the MPC8315E. MPC8315E USB Mac USB PHY PLL TDM x M1 e300c3 core Core PLL core_clk /n mux to DDR memory controller DDR Clock Divider /2 MEMC_MCK MEMC_MCK DDR Memory Device USB_CLK_IN USB_CR_CLK_IN Crystal USB_CR_CLK_OUT x L2 System PLL Clock Unit csb_clk ddr_clk lbc_clk /n To local bus LBC Clock Divider LCLK[0:1] /1,/2 Local Bus Memory Device CFG_CLKIN _DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT GTX_CLK125 125-MHz source eTSEC Protocol Converter PCI Express Protocol Converter csb_clk to rest of the device PCI_CLK/ PCI_SYNC_IN 1 0 3 PCI Clock Divider (÷2) PCI_SYNC_OUT PCI_CLK_OUT[0:2] RTC RTC_CLK (32 kHz) Sys Ref PCVTR Mux SD_REF_CLK SD_REF_CLK_B 125/100 MHz SATA Controller + PLL SerDes PHY SATA PHY PLL SATA_CLK_IN 50/75/100/ 125/150 MHz 1 2 Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. Multiplication factor L = 2, 3, 4 and 5. Value is decided by RCWLR[SPMF]. Figure 62. MPC8315E Clock Subsystem MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 96 Freescale Semiconductor Clocking The primary clock source can be one of two inputs, SYS_CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, SYS_CLKIN is its primary input clock. SYS_CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_SYS_CLKIN_DIV configuration input selects whether SYS_CLKIN or SYS_CLKIN/2 is driven out on the PCI_SYNC_OUT signal. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the SYS_CLKIN signal should be tied to GND. As shown in Figure 62, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN × (1 + ~ CFG_SYS_CLKIN_DIV)} × SPMF In PCI host mode, PCI_SYNC_IN × (1 + ~ CFG_SYS_CLKIN_DIV) is the SYS_CLKIN frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8315E PowerQUICC II Pro Host Processor Reference Manual for more information on the clock subsystem. The internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk × (1 + RCWL[DDRCM]) Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk × (1 + RCWL[LBIUCM]) Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LCLK[0:1]). The LBIU clock divider ratio is controlled by LCCR[CLKDIV]. In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 71 specifies which units have a configurable clock frequency. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 97 Clocking Table 71. Configurable Clock Units Unit eTSEC1 eTSEC2 Security Core, I2C, SAP, TPR USB DR PCI and DMA complex PCIe Serial ATA Default Frequency Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk Off, csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk csb_clk csb_clk csb_clk csb_clk csb_clk csb_clk Table 72 provides the operating frequencies for the TEPBGA II under recommended operating conditions (see Table 2). Table 72. Operating Frequencies for TEPBGA II Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR1/2 memory bus frequency Local bus frequency (LCLKn)3 PCI input frequency (SYS_CLKIN or PCI_CLK) (MCK)2 Max Operating Frequency 400 133 133 66 24-66 Unit MHz MHz MHz MHz MHz Notes: 1. The SYS_CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCK, LCLK[0:1], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The DDR data rate is 2x the DDR memory bus frequency. 3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]). 24.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 73 shows the multiplication factor encodings for the system PLL. NOTE If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL VCO frequency = (CSB frequency) × (System PLL VCO Divider). If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 450–750 MHz. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 98 Freescale Semiconductor Clocking Table 73. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110–1111 System PLL Multiplication Factor Reserved Reserved ×2 ×3 ×4 ×5 Reserved As described in Section 24, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_SYS_CLKIN_DIV configuration input signal select the ratio between the primary clock input (SYS_CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 74 and Table 75 shows the expected frequency values for the CSB frequency for select csb_clk to SYS_CLKIN/PCI_SYNC_IN ratios. Table 74. CSB Frequency Options for Host Mode csb_clk : Input Clock Ratio 2 2:1 3:1 4:1 5:1 96 120 100 133 — Input Clock Frequency (MHz)2 24 33.33 66.67 133 — — — CFG_SYS_CLKIN_DIV at Reset1 High/Low 3 High/Low High/Low High/Low 1 2 SPMF 0010 0011 0100 0101 CFG_SYS_CLKIN_DIV select the ratio between SYS_CLKIN and PCI_SYNC_OUT. SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. 3 In the Host mode it does not matter if the value is High or Low. Table 75. CSB Frequency Options for Agent Mode csb_clk : Input Clock Ratio 2 2: 1 3: 1 4: 1 5: 1 120 100 133 — Input Clock frequency (MHz)2 25 33.33 66.67 133 — — — CFG_SYS_CLKIN_DIV at Reset1 SPMF High High High High 1 2 0010 0011 0100 0101 CFG_SYS_CLKIN_DIV doubles csb_clk if set low. SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 99 Clocking 24.2 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 76 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 76 should be considered as reserved. NOTE Core VCO frequency = core frequency × VCO divider VCO divider has to be set properly so that the core VCO frequency is in the range of 400–800 MHz. Table 76. e300 Core PLL Configuration RCWL[COREPLL] VCO Divider1 core_clk : csb_clk Ratio 0–1 nn 11 00 01 00 01 00 01 00 01 00 01 1 2–5 0000 nnnn 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 6 0 n 0 0 1 1 0 0 1 1 0 0 PLL bypassed (PLL off, csb_clk clocks core directly) N/A 1:1 1:1 1.5:1 1.5:1 2:1 2:1 2.5:1 2.5:1 3:1 3:1 PLL bypassed (PLL off, csb_clk clocks core directly) N/A 2 4 2 4 2 4 2 4 2 4 Core VCO frequency = core frequency × VCO divider. 24.3 Suggested PLL Configurations To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are configured separately. Both of the domains has one common input clock. Table 77 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks. Table 77. Suggested PLL Configurations Conf. No. 1 2 SPMF 0100 0100 Core\PLL 0000100 0000101 Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz) 33.33 25 133.33 100 266.66 250 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 100 Freescale Semiconductor Thermal (Preliminary) Table 77. Suggested PLL Configurations Conf. No. 3 4 5 6 7 8 9 SPMF 0010 0100 0101 0010 0101 0100 0010 Core\PLL 0000100 0000101 0000101 0000101 0000110 0000110 0000110 Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz) 66.67 33.33 25 66.67 25 33.33 66.67 133.33 133.33 125 133.33 125 133.33 133.33 266.66 333.33 312.5 333.33 375 400 400 25 Thermal (Preliminary) This section describes the thermal specifications of the MPC8315E. 25.1 Thermal Characteristics Table 78. Package Thermal Characteristics for TEPBGA II Characteristic Board type Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural convection Symbol Value 23 16 18 13 8 6 6 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Notes 1, 2 1, 2, 3 1, 3 1, 3 4 5 6 Table 78 provides the package thermal characteristics for the 620 29 × 29 mm TEPBGA II. Junction to ambient natural convection Junction to ambient natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to package top RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 101 Thermal (Preliminary) 25.2 Thermal Management Information For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. 25.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance TJ = TA + (RθJA × PD) where: TJ = junction temperature (°C) TA = ambient temperature for the package (°C) RθJA = junction to ambient thermal resistance (°C/W) PD = power dissipation in the package (W) An estimation of the chip junction temperature, TJ, can be obtained from the equation: The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible. 25.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (°C) TB = board temperature at the package perimeter (°C) RθJB = junction to board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 102 Freescale Semiconductor Thermal (Preliminary) 25.2.3 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TJ = junction temperature (°C) TT = thermocouple temperature on top of package (°C) ΨJT = junction to ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 25.2.4 Heat Sinks and Junction-to-Case Thermal Resistance In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction to ambient thermal resistance (°C/W) RθJC = junction to case thermal resistance (°C/W) RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 103 Thermal (Preliminary) Table 79. Heat Sinks and Junction-to-Case Thermal Resistance of MPC8315E TEPBGA II 29 × 29 mm TEBGA II Heat Sink Assuming Thermal Grease Air Flow Junction-to-Ambient Thermal Resistance 14.4 11.4 10.1 8.9 12.3 9.3 8.5 7.9 12.5 9.7 8.5 7.7 10.9 8.5 7.5 7.1 AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 35 x 31 x 23 mm Pin Fin AAVID 35 x 31 x 23 mm Pin Fin AAVID 35 x 31 x 23 mm Pin Fin AAVID 35 x 31 x 23 mm Pin Fin AAVID 43 x 41 x 16.5 mm Pin Fin AAVID 43 x 41 x 16.5 mm Pin Fin AAVID 43 x 41 x 16.5 mm Pin Fin AAVID 43 x 41 x 16.5 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Natural Convection 0.5 m/s 1 m/s 2 m/s Natural Convection 0.5 m/s 1 m/s 2 m/s Natural Convection 0.5 m/s 1 m/s 2 m/s Natural Convection 0.5 m/s 1 m/s 2 m/s Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com 603-224-9988 408-749-7601 MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 104 Freescale Semiconductor Thermal (Preliminary) International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) 408-436-8770 Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics 800-522-6752 Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105 Internet: www.tycoelectronics.com Wakefield Engineering 603-635-2800 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Corporate Center PO BOX 994 Midland, MI 48686-0994 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 781-935-4850 800-248-2481 888-642-7674 800-347-4572 25.3 Heat Sink Attachment When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 105 System Design Information lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (45 Newtons). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. 25.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance. TJ = TC + (RθJC x PD) Where TC is the case temperature of the package RθJC is the junction-to-case thermal resistance PD is the power dissipation 26 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8315E. 26.1 System Clocking The MPC8315E includes two PLLs. 1. The platform PLL (AVDD2) generates the platform clock from the externally supplied SYS_CLKIN input. The frequency ratio between the platform and SYS_CLKIN is selected using the platform PLL ratio configuration bits as described in Section 24.1, “System PLL Configuration.” 2. The e300 Core PLL (AVDD1) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 24.2, “Core PLL Configuration.” 26.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme such as the following. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 106 Freescale Semiconductor System Design Information There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits as illustrated in Figure 63, one to each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Note that the RC filter results in lower voltage level on AVDD. This does not imply that the DC specification can be relaxed. Figure 63 shows the PLL power supply filter circuit. 10 Ω VDD 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors AVDD (or L2AV DD) GND Figure 63. PLL Power Supply Filter Circuit 26.3 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8315E system, and the MPC8315E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, NVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing thick and short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, NVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON). MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 107 System Design Information 26.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to NVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, NVDD, and GND pins of the device. 26.5 Output Buffer DC Impedance The MPC8315E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD or GND. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (see Figure 64). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. NVDD RN SW2 Data Pad SW1 RP OGND Figure 64. Driver Impedance Measurement The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = (1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 – 1). The drive current is then Isource = V1/Rsource. Table 80 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal NVDD, 105°C. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 108 Freescale Semiconductor Ordering Information Table 80. Impedance Characteristics Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target NA PCI Signals (Not Including PCI Output Clocks) 25 Target 25 Target NA PCI Output Clocks (Including PCI_SYNC_OUT) 42 Target 42 Target NA Impedance DDR DRAM Symbol Unit RN RP Differential 20 Target 20 Target NA Z0 Z0 ZDIFF Ω Ω Ω Note: Nominal supply voltages. See Table 1, Tj = 105° C. 26.6 Configuration Pin Multiplexing The MPC8315E provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 26.7 Pull-Up Resistor Requirements The MPC8315E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins including I2C pins, Ethernet Management MDIO pin and EPIC interrupt pins. For more information on required pull up resistors and the connections required for JTAG interface, see AN3438, MPC8315 Design Checklist 27 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 27.1, “Part Numbers Fully Addressed by this Document.” 27.1 Part Numbers Fully Addressed by this Document Table 81 provides the Freescale part numbering nomenclature for the MPC8315E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 109 Document Revision History Table 81. Part Numbering Nomenclature MPC Product Code MPC 8315 Part Identifier 8315 E Encryption Acceleration Blank = Not included E = included C Temperature Range 3 Blank = 0 to 105° C C = –40 to 105° C VR Package 1 VR= Pb Free TEPBGA II AG e300 Core Frequency 2 AD = 266 MHz AF = 333 MHz AG = 400 MHz D DDR Frequency A Revision Level D = 266 MHz Contact local Freescale sales office Notes: 1. See Section 23, “Package and Pin Listings,” for more information on available package types. 2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by electric may support other maximum core frequencies. 3. Contact your local Freescale field applications engineer (FAE). Table shows the SVR settings by device and package type. Table 82. SVR Settings Device MPC8315E MPC8315 MPC8314E MPC8314 Package TEPBGA II TEPBGA II TEPBGA II TEPBGA II SVR (Rev 1.0) 0x80B4_0010 0x80B5_0010 0x80B6_0010 0x80B7_0010 SVR (Rev 1.1) 0x80B4_0011 0x80B5_0011 0x80B6_0011 0x80B7_0011 SVR (Rev 1.2) 0x80B4_0012 0x80B5_0012 0x80B6_0012 0x80B7_0012 Notes: 1. PVR = 8085_0020 for all devices and revisions in this table. 28 Document Revision History Table 83 provides a revision history for this hardware specification. Table 83. Document Revision History Revision 0 Date 05/2009 Initial public release. Substantive Change(s) MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 110 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 111 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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Freescale and the Freescale logo are trademarks or registered trademarks of Freescale Semiconductor, Inc. in the U.S. and other countries. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. IEEE 802.3, 802.11, 1588, and 1149.1 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8315EEC Rev. 0 05/2009