MPC8323ECZQAFDCA

Freescale Semiconductor Technical Data Document Number: MPC8323EEC Rev. 3, 02/2010 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications This document provides an overview of the MPC8323E PowerQUICC™ II Pro processor features. The MPC8323E is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including ADSL SOHO and residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8323E extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. This document describes the MPC8323E, and unless otherwise noted, the information also applies to the MPC8323, MPC8321E, and MPC8321. To locate published errata or updates for this document, refer to the MPC8323E product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ethernet and MII Management . . . . . . . . . . . . . . . . . 19 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 HDLC, BISYNC, Transparent, and Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 System Design Information . . . . . . . . . . . . . . . . . . . 76 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 Document Revision History . . . . . . . . . . . . . . . . . . . 80 © 2010 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture™ technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. A new communications complex based on QUICC Engine™ technology forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A block diagram of the MPC8323E is shown in Figure 1. MPC8323E e300c2 Core 16 KB I-Cache Integer Unit (IU1) 16 KB D-Cache Integer Unit (IU2) Security Engine (SEC 2.2) System Interface Unit (SIU) Memory Controllers GPCM/UPM 32-Bit DDR1/DDR2 Interface Unit PCI Controller Local Bus Bus Arbitration Multi-User RAM Serial DMA and 2 Virtual DMAs DUART I2C 4 Channel DMA UCC2 UCC3 UCC4 UCC5 Interrupt Controller USB SPI SPI Protection and Configuration System Reset Clock Synthesizer DDR PCI Local Classic G2 MMUs Timers, Power Management, and JTAG/COP QUICC Engine Block Baud Rate Generators Parallel I/O UCC1 Accelerators Single 32-Bit RISC CP Time Slot Assigner Serial Interface 4 TDM Ports 3 MII/RMII 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial ATM, HDLC, UART, and BISYNC—and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM support for up to OC-3 speeds. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 2 Freescale Semiconductor Overview NOTE The QUICC Engine block can also support a UTOPIA level 2 capable of supporting 31 multi-PHY (MPC8323E- and MPC8323-specific). The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. In summary, the MPC8323E family provides users with a highly integrated, fully programmable communications processor. This helps ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.1 MPC8323E Features Major features of the MPC8323E are as follows: • High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for ATM or IP/Ethernet packet processing (or both). • MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards. • Single platform architecture supports the convergence of IP packet networks and ATM networks. • DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1 and DDR2. • An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches, and dual integer units. • Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus interface up to 66-MHz operation, and USB 2.0 (full-/low-speed). • Security engine provides acceleration for control and data plane security protocols. • High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. 1.1.1 Protocols The protocols are as follows: • ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1) • Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) • Support for IMA and ATM transmission convergence sub-layer • ATM OAM handling features compatible with ITU-T I.610 • IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing • Extensive support for ATM statistics and Ethernet RMON/MIB statistics • Support for 64 channels of HDLC/transparent M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Overview 1.1.2 Serial Interfaces The MPC8323E serial interfaces are as follows: • Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only) • Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII • Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM) • Support for dual UART and SPI interfaces and a single I2C interface 1.2 QUICC Engine Block The QUICC Engine block is a versatile communications complex that integrates several communications peripheral controllers. It provides on-chip system design for a variety of applications, particularly in communications and networking systems. The QUICC Engine block has the following features: • One 32-bit RISC controller for flexible support of the communications peripherals • Serial DMA channel for receive and transmit on all serial channels • Five universal communication controllers (UCCs) supporting the following protocols and interfaces (not all of them simultaneously): — 10/100 Mbps Ethernet/IEEE 802.3® standard — IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing — ATM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not support the UTOPIA interface) — HDLC /transparent up to 70-Mbps full-duplex — HDLC bus up to 10 Mbps — Asynchronous HDLC — UART — BISYNC up to 2 Mbps — QUICC multi-channel controller (QMC) for 64 TDM channels • One UTOPIA interface (UPC1) supporting 31 multi-PHYs (MPC8323E- and MPC8323-specific) • Two serial peripheral interfaces (SPI). SPI2 is dedicated to Ethernet PHY management. • Four TDM interfaces • Thirteen independent baud rate generators and 19 input clock pins for supplying clocks to UCC serial channels • Four independent 16-bit timers that can be interconnected as two 32-bit timers The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and FCC (fast Ethernet, HDLC, transparent, and ATM). M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 4 Freescale Semiconductor Overview 1.3 Security Engine The security engine is optimized to handle all the algorithms associated with IPSec, IEEE 802.11i® standard, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are: • Data encryption standard execution unit (DEU), supporting DES and 3DES • Advanced encryption standard unit (AESU), supporting AES • Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any algorithm • One crypto-channel supporting multi-command descriptor chains 1.4 DDR Memory Controller The MPC8323E DDR1/DDR2 memory controller includes the following features: • Single 32-bit interface supporting both DDR1 and DDR2 SDRAM • Support for up to 266-MHz data rate • Support for two ×16 devices • Support for up to 16 simultaneous open pages • Supports auto refresh • On-the-fly power management using CKE • 1.8-/2.5-V SSTL2 compatible I/O • Support for 1 chip select only • FCRAM, ECC, hardware/software calibration, bit deskew, QIN stage, or atomic logic are not supported. 1.5 PCI Controller The MPC8323E PCI controller includes the following features: • PCI Specification Revision 2.3 compatible • Single 32-bit data PCI interface operates up to 66 MHz • PCI 3.3-V compatible (not 5-V compatible) • Support for host and agent modes • On-chip arbitration, supporting three external masters on PCI • Selectable hardware-enforced coherency 1.6 Programmable Interrupt Controller (PIC) The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The PIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 35 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 5 Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8323E. The MPC8323E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD AVDDn GVDD OV DD MVIN MVREF OVIN Max Value –0.3 to 1.26 –0.3 to 1.26 –0.3 to 2.75 –0.3 to 1.98 –0.3 to 3.6 –0.3 to (GV DD + 0.3) –0.3 to (GV DD + 0.3) –0.3 to (OV DD + 0.3) Unit V V V V V V V Notes — — — — 2 2 3 Table 1 provides the absolute maximum ratings. Core supply voltage PLL supply voltage DDR1 and DDR2 DRAM I/O voltage PCI, local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, and JTAG I/O voltage Input voltage DDR1/DDR2 DRAM signals DDR1/DDR2 DRAM reference Local bus, DUART, CLKIN, system control and power management, I2C, SPI, and JTAG signals PCI Storage temperature range OVIN TSTG –0.3 to (OV DD + 0.3) –55 to 150 V °C 5 — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 6 Freescale Semiconductor Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8323E. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage DDR1 and DDR2 DRAM I/O voltage PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage Junction temperature Symbol VDD AVDD GVDD OV DD TA/TJ Recommended Value 1.0 V ± 50 mV 1.0 V ± 50 mV 2.5 V ± 125 mV 1.8 V ± 90 mV 3.3 V ± 300 mV 0 to 105 Unit V V V V °C Notes 1 1 1 1 2 Note: 1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 2. Minimum temperature is specified with TA; maximum temperature is specified with TJ. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8323E G/OVDD + 20% G/OVDD + 5% VIH G/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 7 Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Local bus interface utilities signals PCI signals DDR1 signal DDR2 signal DUART, system control, I2C, SPI, JTAG GPIO signals Output Impedance (Ω ) 42 25 18 18 42 42 GVDD = 2.5 V GVDD = 1.8 V OVDD = 3.3 V OVDD = 3.3 V Supply Voltage OVDD = 3.3 V 2.1.4 Input Capacitance Specification Table 4. Input Capacitance Specification Parameter/Condition Symbol CI CICLKIN Min 6 10 Max 8 — Unit pF pF Notes — 1 Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E. Input capacitance for all pins except CLKIN Input capacitance for CLKIN Note: 1. The external clock generator should be able to drive 10 pF. 2.2 Power Sequencing The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. Note that there is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD and OVDD) do not have any ordering requirements with respect to one another. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 8 Freescale Semiconductor Power Characteristics V I/O Voltage (GVDD and OVDD) Core Voltage (VDD) 90% 0.7 V 0 PORESET t tSYS_CLK_IN/tPCI_SYNC_IN >= 32 clocks Figure 3. MPC8323E Power-Up Sequencing Example 3 Power Characteristics Table 5. MPC8323E Power Dissipation CSB Frequency (MHz) 133 133 QUICC Engine Frequency (MHz) 200 200 Core Frequency (MHz) 266 333 Typical 0.74 0.78 Maximum 1.48 1.62 Unit W W Notes 1, 2, 3 1, 2, 3 The estimated typical power dissipation for this family of MPC8323E devices is shown in Table 5. Notes: 1. The values do not include I/O supply power (OVDD and GVDD) or AV DD. For I/O power values, see Table 6. 2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone benchmark application. The measurements were taken on the MPC8323MDS evaluation board using WC process silicon. 3. Maximum power is based on a voltage of VDD = 1.07 V, WC process, a junction TJ = 110°C, and an artificial smoke test. Table 6 shows the estimated typical I/O power dissipation for the device. Table 6. Estimated Typical I/O Power Dissipation Interface DDR I/O 65% utilization 2.5 V Rs = 2 0 Ω Rt = 5 0 Ω 1 pair of clocks Parameter 266 MHz, 1 × 32 bits GVDD (1.8 V) 0.212 GVDD (2.5 V) OVDD (3.3 V) Unit 0.367 — W Comments — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 9 Clock Input Timing Table 6. Estimated Typical I/O Power Dissipation (continued) Local bus I/O load = 25 pF 1 pair of clocks PCI I/O load = 30 pF QUICC Engine block and other I/Os 66 MHz, 32 bits — — 0.12 W — 66 MHz, 32 bits UTOPIA 8-bit 31 PHYs TDM serial TDM nibble HDLC/TRAN serial HDLC/TRAN nibble DUART MIIs RMII Ethernet management USB SPI Timer output — — — — — — — — — — — — — — — — — — — — — — — — — — 0.057 0.041 0.001 0.004 0.003 0.025 0.017 0.009 0.009 0.002 0.001 0.001 0.002 W W W W W W W W W W W W W — Mutiply by number of interfaces used. NOTE AVDDn (1.0 V) is estimated to consume 0.05 W (under normal operating conditions and ambient temperature). 4 Clock Input Timing NOTE The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VCC; fall time refers to transitions from 90% to 10% of VCC. This section provides the clock input DC and AC electrical characteristics for the MPC8323E. 4.1 DC Electrical Characteristics Table 7. CLKIN DC Electrical Characteristics Parameter Condition — — Symbol VIH VIL Min 2.7 –0.3 Max OVDD + 0.3 0.4 Unit V V Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E. Input high voltage Input low voltage M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 10 Freescale Semiconductor RESET Initialization Table 7. CLKIN DC Electrical Characteristics (continued) CLKIN input current PCI_SYNC_IN input current PCI_SYNC_IN input current 0 V ≤ VIN ≤ OVDD 0 V ≤ VIN ≤ 0.5 V or OVDD – 0.5 V ≤ VIN ≤ OV DD 0.5 V ≤ VIN ≤ OVDD – 0.5 V IIN IIN IIN — — — ±5 ±5 ±50 μA μA μA 4.2 AC Electrical Characteristics The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the MPC8323E. Table 8. CLKIN AC Timing Specifications Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN rise and fall time PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tPCH, tPCL tKHK/tCLKIN — Min 25 15 0.6 0.6 40 — Typical — — 0.8 0.8 — — Max 66.67 — 4 1.2 60 ±150 Unit MHz ns ns ns % ps Notes 1 — 2 2 3 4, 5 Notes: 1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter. 5 RESET Initialization This section describes the AC electrical specifications for the reset initialization timing requirements of the MPC8323E. Table 9 provides the reset initialization AC timing specifications for the reset component(s). Table 9. RESET Initialization Timing Specifications Parameter/Condition Required assertion time of HRESET or SRESET (input) to activate reset flow Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8323E is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8323E is in PCI agent mode Min 32 32 32 Max — — — Unit tPCI_SYNC_IN tCLKIN tPCI_SYNC_IN Notes 1 2 1 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 11 RESET Initialization Table 9. RESET Initialization Timing Specifications (continued) HRESET/SRESET assertion (output) HRESET negation to SRESET negation (output) Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8323E is in PCI host mode Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8323E is in PCI agent mode Input hold time for POR config signals with respect to negation of HRESET Time for the MPC8323E to turn off POR configuration signals with respect to the assertion of HRESET Time for the MPC8323E to turn on POR configuration signals with respect to the negation of HRESET 512 16 4 — — — tPCI_SYNC_IN tPCI_SYNC_IN tCLKIN 1 1 2 4 — tPCI_SYNC_IN 1 0 — 1 — 4 — ns ns tPCI_SYNC_IN — 3 1, 3 Notes: 1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details. 2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details. 3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. Table 10 provides the PLL lock times. Table 10. PLL Lock Times Parameter/Condition PLL lock times Min — Max 100 Unit μs Notes — 5.1 Reset Signals DC Electrical Characteristics Table 11. Reset Signals DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V μA Notes 1 1 1 1 — — Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 9. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Note: 1. This specification applies when operating from 3.3 V supply. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 12 Freescale Semiconductor DDR1 and DDR2 SDRAM 6 DDR1 and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR1 and DDR2 SDRAM interface of the MPC8323E. Note that DDR1 SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is Dn_GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR1 and DDR2 SDRAM. 6.1 DDR1 and DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8323E when Dn_GVDD(typ) = 1.8 V. Table 12. DDR2 SDRAM DC Electrical Characteristics for Dn_GVDD(typ) = 1.8 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.35 V) Output low current (VOUT = 0.280 V) Symbol Dn_GVDD MVREFnREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 × Dn_GVDD MVREFnREF – 0.04 MVREFnREF + 0.125 –0.3 –9.9 –13.4 13.4 Max 1.89 0.51 × Dn_GVDD MVREFnREF + 0.04 Dn_GV DD + 0.3 MVREFnREF – 0.125 9.9 — — Unit V V V V V μA mA mA Notes 1 2 3 — — 4 — — Notes: 1. Dn_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. MVREF nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREFnREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREFnREF. This rail should track variations in the DC level of MVREFnREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD. Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V. Table 13. DDR2 SDRAM Capacitance for Dn_GVDD(typ) = 1.8 V Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. Dn_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25 °C, VOUT = Dn_GVDD ÷ 2, VOUT (peak-to-peak) = 0.2 V. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 13 DDR1 and DDR2 SDRAM Table 14 provides the recommended operating conditions for the DDR1 SDRAM component(s) of the MPC8323E when Dn_GVDD(typ) = 2.5 V. Table 14. DDR1 SDRAM DC Electrical Characteristics for Dn_GVDD(typ) = 2.5 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Symbol Dn_GVDD MVREFnREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 × Dn_GVDD MVREFnREF – 0.04 MVREFnREF + 0.15 –0.3 –9.9 –16.2 16.2 Max 2.625 0.51 × Dn_GVDD MVREFnREF + 0.04 Dn_GV DD + 0.3 MVREFnREF – 0.15 –9.9 — — Unit V V V V V μA mA mA Notes 1 2 3 — — 4 — — Notes: 1. Dn_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times. 2. MVREF nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREFnREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREFnREF. This rail should track variations in the DC level of MVREFnREF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD. Table 15 provides the DDR1 capacitance Dn_GVDD(typ) = 2.5 V. Table 15. DDR1 SDRAM Capacitance for Dn_GVDD(typ) = 2.5 V Interface Parameter/Condition Input/output capacitance: DQ,DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. D n_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25° C, VOUT = Dn_GVDD ÷ 2, VOUT (peak-to-peak) = 0.2 V. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 14 Freescale Semiconductor DDR1 and DDR2 SDRAM 6.2 DDR1 and DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR1 and DDR2 SDRAM interface. 6.2.1 DDR1 and DDR2 SDRAM Input AC Timing Specifications Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Table 16 provides the input AC timing specifications for the DDR2 SDRAM (Dn_GVDD(typ) = 1.8 V). At recommended operating conditions with D n_GVDD of 1.8 ± 5%. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — MVREFnREF + 0.25 Max MVREFnREF – 0.25 — Unit V V Notes — — Table 17 provides the input AC timing specifications for the DDR1 SDRAM (Dn_GVDD(typ) = 2.5 V). Table 17. DDR1 SDRAM Input AC Timing Specifications for 2.5 V Interface At recommended operating conditions with D n_GVDD of 2.5 ± 5%. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — MVREFnREF + 0.31 Max MVREFnREF – 0.31 — Unit V V Notes — — Table 18 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface. Table 18. DDR1 and DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%. Parameter Controller skew for MDQS—MDQ/MDM 266 MHz 200 MHz Symbol tCISKEW Min Max Unit ps Notes 1, 2 –750 –1250 750 1250 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 15 DDR1 and DDR2 SDRAM Figure 4 shows the input timing diagram for the DDR controller. MCK[n] MCK[n] tMCK MDQS[n] MDQ[x] D0 tDISKEW D1 tDISKEW Figure 4. DDR Input Timing Diagram 6.2.2 DDR1 and DDR2 SDRAM Output AC Timing Specifications Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications Table 19 provides the output AC timing specifications for the DDR1 and DDR2 SDRAM interfaces. At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%. Parameter MCK cycle time, (MCK/MCK crossing) ADDR/CMD output setup with respect to MCK 266 MHz 200 MHz ADDR/CMD output hold with respect to MCK 266 MHz 200 MHz MCS output setup with respect to MCK 266 MHz 200 MHz MCS output hold with respect to MCK 266 MHz 200 MHz MCK to MDQS Skew Symbol1 tMCK tDDKHAS Min 7.5 2.5 3.5 Max 10 — — Unit ns ns Notes 2 3 tDDKHAX 2.5 3.5 tDDKHCS 2.5 3.5 tDDKHCX 2.5 3.5 tDDKHMH –0.6 — — 0.6 — — — — ns 3 ns 3 ns 3 ns 4 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 16 Freescale Semiconductor DDR1 and DDR2 SDRAM Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with D n_GVDD of (1.8 or 2.5 V) ± 5%. Parameter MDQ/MDM output setup with respect to MDQS 266 MHz 200 MHz MDQ/MDM output hold with respect to MDQS 266 MHz 200 MHz MDQS preamble start MDQS epilogue end Symbol1 tDDKHDS, tDDKLDS Min Max Unit ns Notes 5 0.9 1.0 tDDKHDX, tDDKLDX 1100 1200 tDDKHMP tDDKHME –0.5 × tMCK – 0.6 –0.6 — — ps — — –0.5 × tMCK + 0.6 0.6 ns ns 6 6 5 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK m emory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 17 DDR1 and DDR2 SDRAM Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK MCK tMCK tDDKHMH(max) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH Figure 6 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS,tDDKHCS tDDKHAX,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 6. DDR1 and DDR2 SDRAM Output Timing Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 18 Freescale Semiconductor DUART 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8323E. 7.1 DUART DC Electrical Characteristics Table 20. DUART DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OV DD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V μA Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8323E. High-level input voltage Low-level input voltage OVDD High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Input current (0 V ≤ VIN ≤ OV DD)1 Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2. 7.2 DUART AC Electrical Specifications Table 21. DUART AC Timing Specifications Parameter Value 256 > 1,000,000 16 Unit baud baud — 1 2 Notes Table 21 provides the AC timing parameters for the DUART interface of the MPC8323E. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 8 8.1 Ethernet and MII Management Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics This section provides the AC and DC electrical characteristics for Ethernet and MII management. The electrical characteristics specified here apply to all MII (media independent interface) and RMII (reduced media independent interface), except MDIO (management data input/output) and MDC M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 19 Ethernet and MII Management (management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 22. The potential applied to the input of a MII or RMII receiver may exceed the potential of the receiver’s power supply (that is, a MII driver powered from a 3.6-V supply driving VOH into a MII receiver powered from a 2.5-V supply). Tolerance for dissimilar MII driver and receiver supply potentials is implicit in these specifications. Table 22. MII and RMII DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN Conditions — IOH = –4.0 mA IOL = 4.0 mA — — OVDD = Min OVDD = Min — — Min 2.97 2.40 GND 2.0 –0.3 — Max 3.63 OVDD + 0.3 0.50 OVDD + 0.3 0.90 ±5 Unit V V V V V μA 0 V ≤ VIN ≤ OVDD 8.2 MII and RMII AC Timing Specifications The AC timing specifications for MII and RMII are presented in this section. 8.2.1 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.1.1 MII Transmit AC Timing Specifications Table 23. MII Transmit AC Timing Specifications Table 23 provides the MII transmit AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR Min — — 35 1 1.0 Typical 400 40 — 5 — Max — — 65 15 4.0 Unit ns ns % ns ns M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 20 Freescale Semiconductor Ethernet and MII Management Table 23. MII Transmit AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition TX_CLK data clock fall VIH(max) to VIL(min) Symbol1 tMTXF Min 1.0 Typical — Max 4.0 Unit ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 7 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 7. MII Transmit AC Timing Diagram 8.2.1.2 MII Receive AC Timing Specifications Table 24. MII Receive AC Timing Specifications Table 24 provides the MII receive AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR Min — — 35 10.0 10.0 1.0 Typical 400 40 — — — — Max — — 65 — — 4.0 Unit ns ns % ns ns ns M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 21 Ethernet and MII Management Table 24. MII Receive AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition RX_CLK clock fall time VIH(max) to VIL(min) Symbol1 tMRXF Min 1.0 Typical — Max 4.0 Unit ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 8 provides the AC test load. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 8. AC Test Load Figure 9 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 9. MII Receive AC Timing Diagram 8.2.2 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 22 Freescale Semiconductor Ethernet and MII Management 8.2.2.1 RMII Transmit AC Timing Specifications Table 25. RMII Transmit AC Timing Specifications Table 23 provides the RMII transmit AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to RMII data TXD[1:0], TX_EN delay REF_CLK data clock rise VIL(min) to VIH(max) REF_CLK data clock fall VIH(max) to VIL(min) Symbol1 tRMX tRMXH/tRMX tRMTKHDX tRMXR tRMXF Min — 35 2 1.0 1.0 Typical 20 — — — — Max — 65 10 4.0 4.0 Unit ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 10 shows the RMII transmit AC timing diagram. tRMX REF_CLK tRMXH TXD[1:0] TX_EN tRMTKHDX tRMXF tRMXR Figure 10. RMII Transmit AC Timing Diagram 8.2.2.2 RMII Receive AC Timing Specifications Table 26. RMII Receive AC Timing Specifications Table 24 provides the RMII receive AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise VIL(min) to VIH(max) Symbol1 tRMX tRMXH/tRMX tRMRDVKH tRMRDXKH tRMXR Min — 35 4.0 2.0 1.0 Typical 20 — — — — Max — 65 — — 4.0 Unit ns % ns ns ns M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 23 Ethernet and MII Management Table 26. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter/Condition REF_CLK clock fall time V IH(max) to VIL(min) Symbol1 tRMXF Min 1.0 Typical — Max 4.0 Unit ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 11 provides the AC test load. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 11. AC Test Load Figure 12 shows the RMII receive AC timing diagram. tRMX REF_CLK tRMXH RXD[1:0] CRS_DV RX_ER tRMRDVKH tRMRDXKH tRMXF Valid Data tRMXR Figure 12. RMII Receive AC Timing Diagram 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics.” M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 24 Freescale Semiconductor Ethernet and MII Management 8.3.1 MII Management DC Electrical Characteristics MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 27. Table 27. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN Conditions — IOH = –1.0 mA IOL = 1.0 mA — — 0 V ≤ VIN ≤ OVDD OVDD = Min OVDD = Min Min 2.97 2.10 GND 2.00 — — Max 3.63 OVDD + 0.3 0.50 — 0.80 ±5 Unit V V V V V μA 8.3.2 MII Management AC Electrical Specifications Table 28. MII Management AC Timing Specifications Table 28 provides the MII management AC timing specifications. At recommended operating conditions with OVDD is 3.3 V ± 10%. Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Symbol1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min — — 32 10 5 0 — — Typical 2.5 400 — — — — — — Max — — — 70 — — 10 10 Unit MHz ns ns ns ns ns ns ns Notes — — — — — — — — Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 25 Local Bus Figure 13 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 13. MII Management Interface Timing Diagram 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8323E. 9.1 Local Bus DC Electrical Characteristics Table 29. Local Bus DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OV DD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V μA Table 29 provides the DC electrical characteristics for the local bus interface. High-level input voltage Low-level input voltage High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Input current 9.2 Local Bus AC Electrical Specifications Table 30. Local Bus General Timing Parameters Parameter Symbol1 tLBK tLBIVKH tLBIXKH tLBOTOT1 Min 15 7 1.0 1.5 Max — — — — Unit ns ns ns ns Notes 2 3, 4 3, 4 5 Table 30 describes the general timing parameters of the local bus interface of the MPC8323E. Local bus cycle time Input setup to local bus clock (LCLKn) Input hold from local bus clock (LCLKn) LALE output fall to LAD output transition (LATCH hold time) M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 26 Freescale Semiconductor Local Bus Table 30. Local Bus General Timing Parameters (continued) Parameter LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock (LCLK n) to output valid Local bus clock (LCLK n) to output high impedance for LAD/LDP Local bus clock (LCLK n) duty cycle Local bus clock (LCLK n) jitter specification Delay between the input clock (PCI_SYNC_IN) of local bus output clock (LCLKn) Symbol1 tLBOTOT2 tLBOTOT3 tLBKHOV tLBKHOZ tLBDC tLBRJ tLBCDL Min 3 2.5 — — 47 — — Max — — 3 4 53 400 1.7 Unit ns ns ns ns % ps ns Notes 6 7 3 8 — — — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t LBK clock reference (K) goes high (H), in this case for clock one(1). 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 14 provides the AC test load for the local bus. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 14. Local Bus C Test Load M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 27 Local Bus Figure 15 through Figure 17 show the local bus signals. LCLK[n] tLBIXKH tLBIVKH Input Signals: LAD[0:15] tLBIVKH Input Signal: LGTA tLBIXKH tLBKHOV Output Signals: LBCTL/LBCKE/LOE tLBKHOV Output Signals: LAD[0:15] tLBOTOT LALE tLBKHOZ tLBIXKH Figure 15. Local Bus Signals, Nonspecial Signals Only LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:15]/LDP[0:3] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ tLBIXKH tLBIXKH tLBKHOZ Figure 16. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 28 Freescale Semiconductor JTAG LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ tLBIXKH tLBIXKH tLBKHOZ Figure 17. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 10 JTAG This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG) interface of the MPC8323E. 10.1 JTAG DC Electrical Characteristics Table 31 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8323E. Table 31. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Symbol VOH VOL VOL VIH Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — Min 2.4 — — 2.5 Max — 0.5 0.4 OVDD + 0.3 Unit V V V V M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 29 JTAG Table 31. JTAG Interface DC Electrical Characteristics (continued) Characteristic Input low voltage Input current Symbol VIL IIN Condition — 0 V ≤ VIN ≤ OVDD Min –0.3 — Max 0.8 ±5 Unit V μA 10.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8323E. Table 32 provides the JTAG AC timing specifications as defined in Figure 19 through Figure 22. Table 32. JTAG AC Timing Specifications (Independent of CLKIN)1 At recommended operating conditions (see Table 2). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO Symbol2 fJTG t JTG tJTKHKL tJTGR, tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX Min 0 30 11 0 25 4 4 10 10 2 2 2 2 Max 33.3 — — 2 — — — Unit MHz ns ns ns ns ns Notes — — — — 3 4 ns — — ns 15 15 ns — — 5 5 4 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 30 Freescale Semiconductor JTAG Table 32. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued) At recommended operating conditions (see Table 2). Parameter JTAG external clock to output high impedance: Boundary-scan data TDO Symbol2 Min Max Unit ns Notes tJTKLDZ tJTKLOZ 2 2 19 9 5, 6 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 14). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the MPC8323E. Output Z0 = 50 Ω OVDD/2 RL = 5 0 Ω Figure 18. AC Test Load for the JTAG Interface Figure 19 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 19. JTAG Clock Input Timing Diagram Figure 20 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM Figure 20. TRST Timing Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 31 JTAG Figure 21 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 21. Boundary-Scan Timing Diagram Figure 22 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 22. Test Access Port Timing Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 32 Freescale Semiconductor I2C 11 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8323E. 11.1 I2C DC Electrical Characteristics Table 33. I2C DC Electrical Characteristics Table 33 provides the DC electrical characteristics for the I2C interface of the MPC8323E. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current (0 V ≤ VIN ≤ OV DD) Symbol VIH VIL VOL tI2KLKV tI2KHKL CI IIN Min 0.7 × OV DD –0.3 0 20 + 0.1 × CB 0 — — Max OVDD + 0.3 0.3 × OV DD 0.4 250 50 10 ±5 Unit V V V ns ns pF μA Notes — — 1 2 3 — 4 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for information on the digital filter used. 4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off. 11.2 I2C AC Electrical Specifications Table 34. I2C AC Electrical Specifications Table 34 provides the AC timing parameters for the I2C interface of the MPC8323E. All values refer to VIH (min) and VIL (max) levels (see Table 33). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 — 02 Max 400 — — — — — — 0.93 Unit kHz μs μs μs μs ns μs M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 33 I2C Table 34. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 33). Parameter Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol1 tI2CR Min 20 + 0.1 Cb4 20 + 0.1 Cb4 0.6 1.3 0.1 × OV DD 0.2 × OV DD Max 300 300 — — — — Unit ns ns μs μs V V tI2CF tI2PVKH tI2KHDX VNL VNH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8323E provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Figure 23 provides the AC test load for the I2C. Output Z0 = 50 Ω RL = 5 0 Ω OV DD/2 Figure 23. I2C AC Test Load Figure 24 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 24. I2C Bus AC Timing Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 34 Freescale Semiconductor PCI 12 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8323E. 12.1 PCI DC Electrical Characteristics Table 35. PCI DC Electrical Characteristics1,2 Parameter Symbol VIH VIL VOH VOL IIN Test Condition VOUT ≥ VOH (min) or VOUT ≤ VOL (max) OVDD = min, IOH = –100 μA OVDD = min, IOL = 100 μA 0 V ≤ VIN ≤ OVDD Min 2 –0.3 OV DD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V μA Table 35 provides the DC electrical characteristics for the PCI interface of the MPC8323E. High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Notes: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2. 2. Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications. 12.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8323E. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8323E is configured as a host or agent device. Table 36 shows the PCI AC timing specifications at 66 MHz. . Table 36. PCI AC Timing Specifications at 66 MHz Parameter Symbol1 tPCKHOV Min — 1 — 3.0 0 Max 6.0 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 Clock to output valid Output hold from clock Clock to output high impedence Input setup to clock Input hold from clock tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 35 PCI Table 37 shows the PCI AC timing specifications at 33 MHz. Table 37. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedence Input setup to clock Input hold from clock Symbol1 tPCKHOV Min — 2 — 3.0 0 Max 11 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 25 provides the AC test load for PCI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 25. PCI AC Test Load Figure 26 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 26. PCI Input AC Timing Measurement Conditions M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 36 Freescale Semiconductor Timers Figure 27 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 27. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8323E. 13.1 Timer DC Electrical Characteristics Table 38 provides the DC electrical characteristics for the MPC8323E timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 38. Timer DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V μA 13.2 Timer AC Timing Specifications Table 39. Timer Input AC Timing Specifications1 Characteristic Symbol2 tTIWID Min 20 Unit ns Table 39 provides the timer input and output AC timing specifications. Timers inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 37 GPIO Figure 28 provides the AC test load for the timers. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 28. Timers AC Test Load 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8323E. 14.1 GPIO DC Electrical Characteristics Table 40. GPIO DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V μA Notes 1 1 1 1 — — Table 11 provides the DC electrical characteristics for the MPC8323E GPIO. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Note: 1. This specification applies when operating from 3.3-V supply. 14.2 GPIO AC Timing Specifications Table 41. GPIO Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 41 provides the GPIO input and output AC timing specifications. GPIO inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 38 Freescale Semiconductor IPIC Figure 29 provides the AC test load for the GPIO. Output Z0 = 50 Ω RL = 5 0 Ω OVDD /2 Figure 29. GPIO AC Test Load 15 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8323E. 15.1 IPIC DC Electrical Characteristics Table 42. IPIC DC Electrical Characteristics1,2 Characteristic Symbol VIH VIL IIN VOL VOL Condition — — — IOL = 6.0 mA IOL = 3.2 mA Min 2.0 –0.3 — — — Max OVDD + 0.3 0.8 ±5 0.5 0.4 Unit V V μA V V Table 42 provides the DC electrical characteristics for the external interrupt pins of the MPC8323E. Input high voltage Input low voltage Input current Output low voltage Output low voltage Notes: 1. This table applies for pins IRQ [0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts. 2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins. 15.2 IPIC AC Timing Specifications Table 43. IPIC Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 43 provides the IPIC input and output AC timing specifications. IPIC inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 39 SPI 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8323E. 16.1 SPI DC Electrical Characteristics Table 44. SPI DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V μA Table 44 provides the DC electrical characteristics for the MPC8323E SPI. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 16.2 SPI AC Timing Specifications Table 45. SPI AC Timing Specifications1 Characteristic Symbol2 tNIKHOV tNEKHOV tNIIVKH tNIIXKH tNEIVKH tNEIXKH Min 0.5 2 6 0 4 2 Max 6 8 — — — — Unit ns ns ns ns ns ns Table 45 and provide the SPI input and output AC timing specifications. SPI outputs—Master mode (internal clock) delay SPI outputs—Slave mode (external clock) delay SPI inputs—Master mode (internal clock) input setup time SPI inputs—Master mode (internal clock) input hold time SPI inputs—Slave mode (external clock) input setup time SPI inputs—Slave mode (external clock) input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI m emory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). Figure 30 provides the AC test load for the SPI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 30. SPI AC Test Load M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 40 Freescale Semiconductor TDM/SI Figure 31 and Figure 32 represent the AC timing from Table 45. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 31 shows the SPI timing in slave mode (external clock). SPICLK (Input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOV Note: The clock edge is selectable on SPI. Figure 31. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 32 shows the SPI timing in master mode (internal clock). SPICLK (Output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOV Note: The clock edge is selectable on SPI. Figure 32. SPI AC Timing in Master Mode (Internal Clock) Diagram 17 TDM/SI This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the MPC8323E. 17.1 TDM/SI DC Electrical Characteristics Table 46. TDM/SI DC Electrical Characteristics Characteristic Symbol VOH VOL VIH Condition IOH = –2.0 mA IOL = 3.2 mA — Min 2.4 — 2.0 Max — 0.5 OVDD + 0.3 Unit V V V Table 46 provides the DC electrical characteristics for the MPC8323E TDM/SI. Output high voltage Output low voltage Input high voltage M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 41 TDM/SI Table 46. TDM/SI DC Electrical Characteristics (continued) Characteristic Input low voltage Input current Symbol VIL IIN Condition — 0 V ≤ VIN ≤ OVDD Min –0.3 — Max 0.8 ±5 Unit V μA 17.2 TDM/SI AC Timing Specifications Table 47. TDM/SI AC Timing Specifications1 Characteristic Symbol2 tSEKHOV tSEKHOX tSEIVKH tSEIXKH Min 2 2 5 2 Max 12 10 — — Unit ns ns ns ns Table 47 provides the TDM/SI input and output AC timing specifications. TDM/SI outputs—External clock delay TDM/SI outputs—External clock High Impedance TDM/SI inputs—External clock input setup time TDM/SI inputs—External clock input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Figure 33 provides the AC test load for the TDM/SI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 33. TDM/SI AC Test Load Figure 34 represents the AC timing from Table 47. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. TDM/SICLK (Input) tSEIVKH tSEIXKH Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) tSEKHOV tSEKHOX Note: The clock edge is selectable on TDM/SI. Figure 34. TDM/SI AC Timing (External Clock) Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 42 Freescale Semiconductor UTOPIA 18 UTOPIA This section describes the UTOPIA DC and AC electrical specifications of the MPC8323E. NOTE The MPC8321E and MPC8321 do not support UTOPIA. 18.1 UTOPIA DC Electrical Characteristics Table 48. UTOPIA DC Electrical Characteristics Characteristic Symbol VOH VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±5 Unit V V V V μA Table 48 provides the DC electrical characteristics for the MPC8323E UTOPIA. Output high voltage Output low voltage Input high voltage Input low voltage Input current 18.2 UTOPIA AC Timing Specifications Table 49. UTOPIA AC Timing Specifications1 Characteristic Symbol2 tUIKHOV tUEKHOV tUIKHOX tUEKHOX tUIIVKH tUEIVKH tUIIXKH tUEIXKH Min 0 1 0 1 8 4 0 1 Max 5.5 8 5.5 8 — — — — Unit ns ns ns ns ns ns ns ns Table 49 provides the UTOPIA input and output AC timing specifications. UTOPIA outputs—Internal clock delay UTOPIA outputs—External clock delay UTOPIA outputs—Internal clock high impedance UTOPIA outputs—External clock high impedance UTOPIA inputs—Internal clock input setup time UTOPIA inputs—External clock input setup time UTOPIA inputs—Internal clock input hold time UTOPIA inputs—External clock input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA outputs internal timing (UI) for the time tUTOPIA m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 43 UTOPIA Figure 35 provides the AC test load for the UTOPIA. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 35. UTOPIA AC Test Load Figure 36 and Figure 37 represent the AC timing from Table 49. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 36 shows the UTOPIA timing with external clock. UTOPIACLK (Input) tUEIVKH Input Signals: UTOPIA tUEKHOV Output Signals: UTOPIA tUEKHOX tUEIXKH Figure 36. UTOPIA AC Timing (External Clock) Diagram Figure 37 shows the UTOPIA timing with internal clock. UTOPIACLK (Output) tUIIVKH Input Signals: UTOPIA tUIKHOV Output Signals: UTOPIA tUIKHOX tUIIXKH Figure 37. UTOPIA AC Timing (Internal Clock) Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 44 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART 19 HDLC, BISYNC, Transparent, and Synchronous UART This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC, transparent, and synchronous UART of the MPC8323E. 19.1 HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Table 50 provides the DC electrical characteristics for the MPC8323E HDLC, BISYNC, transparent, and synchronous UART protocols. Table 50. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VIH VIL IIN Condition IOH = –2.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±5 Unit V V V V μA 19.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications Table 51 provides the input and output AC timing specifications for HDLC, BISYNC, and transparent UART protocols. Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1 Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Symbol2 tHIKHOV tHEKHOV tHIKHOX tHEKHOX tHIIVKH tHEIVKH tHIIXKH Min 0 1 0 1 6 4 0 Max 5.5 10 5.5 8 — — — Unit ns ns ns ns ns ns ns M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 45 HDLC, BISYNC, Transparent, and Synchronous UART Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1 (continued) Characteristic Inputs—External clock input hold time Symbol2 tHEIXKH Min 1 Max — Unit ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 52. Synchronous UART AC Timing Specifications1 Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Inputs—External clock input hold time Symbol2 tUAIKHOV tUAEKHOV tUAIKHOX tUAEKHOX tUAIIVKH tUAEIVKH tUAIIXKH tUAEIXKH Min 0 1 0 1 6 4 0 1 Max 5.5 10 5.5 8 — — — — Unit ns ns ns ns ns ns ns ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUAIKHOX symbolizes the outputs internal timing (UAI) for the time tserial m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Figure 38 provides the AC test load. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 38. AC Test Load Figure 39 and Figure 40 represent the AC timing from Table 51. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 46 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Figure 39 shows the timing with external clock. Serial CLK (Input) tHEIVKH Input Signals: (See Note) tHEKHOV Output Signals: (See Note) tHEKHOX Note: The clock edge is selectable. tHEIXKH Figure 39. AC Timing (External Clock) Diagram Figure 40 shows the timing with internal clock. Serial CLK (Output) tHIIVKH Input Signals: (See Note) tHIKHOV Output Signals: (See Note) tHIKHOX Note: The clock edge is selectable. tHIIXKH Figure 40. AC Timing (Internal Clock) Diagram M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 47 USB 20 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8323E. 20.1 USB DC Electrical Characteristics Table 53. USB DC Electrical Characteristics1 Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OV DD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V μA Table 53 provides the DC electrical characteristics for the USB interface. High-level input voltage Low-level input voltage High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Input current Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2. 20.2 USB AC Electrical Specifications Table 54. USB General Timing Parameters Parameter Symbol1 tUSCK tUSCK tUSTSPN tUSRSPND tUSRPND Min 20.83 166.67 — — — Max — — 5 10 100 Unit ns ns ns ns ns Notes Full speed 48 MHz Low speed 6 MHz — Full speed transitions Low speed transitions Table 54 describes the general timing parameters of the USB interface of the MPC8323E. USB clock cycle time USB clock cycle time Skew between TXP and TXN Skew among RXP, RXN, and RXD Skew among RXP, RXN, and RXD Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(state)(signal) for receive signals and t(first two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND symbolizes USB timing (US) for the USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, tUSTSPN symbolizes USB timing (US) for the USB transmit signals skew (TS) between TXP and TXN (PN). 2. Skew measurements are done at OVDD/2 of the rising or falling edge of the signals. Figure 41 provide the AC test load for the USB. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 41. USB AC Test Load M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 48 Freescale Semiconductor Package and Pin Listings 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8323E is available in a thermally enhanced Plastic Ball Grid Array (PBGA); see Section 21.1, “Package Parameters for the MPC8323E PBGA,” and Section 21.2, “Mechanical Dimensions of the MPC8323E PBGA,” for information on the PBGA. 21.1 Package Parameters for the MPC8323E PBGA The package parameters are as provided in the following list. The package type is 27 mm × 27 mm, 516 PBGA. Package outline 27 mm × 27 mm Interconnects 516 Pitch 1.00 mm Module height (typical) 2.25 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) Ball diameter (typical) 0.6 mm 21.2 Mechanical Dimensions of the MPC8323E PBGA Figure 42 shows the mechanical dimensions and bottom surface nomenclature of the MPC8323E, 516-PBGA package. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 49 Package and Pin Listings Notes: 1.All dimensions are in millimeters. 2.Dimensions and tolerances per ASME Y14.5M-1994. 3.Maximum solder ball diameter measured parallel to datum A. 4.Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8323E PBGA M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 50 Freescale Semiconductor Package and Pin Listings 21.3 Pinout Listings Table 55. MPC8323E PBGA Pinout Listing Signal Package Pin Number DDR Memory Controller Interface Pin Type Power Supply Notes Table 55 shows the pin list of the MPC8323E. MEMC_MDQ0 MEMC_MDQ1 MEMC_MDQ2 MEMC_MDQ3 MEMC_MDQ4 MEMC_MDQ5 MEMC_MDQ6 MEMC_MDQ7 MEMC_MDQ8 MEMC_MDQ9 MEMC_MDQ10 MEMC_MDQ11 MEMC_MDQ12 MEMC_MDQ13 MEMC_MDQ14 MEMC_MDQ15 MEMC_MDQ16 MEMC_MDQ17 MEMC_MDQ18 MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 MEMC_MDQ27 MEMC_MDQ28 AE9 AD10 AF10 AF9 AF7 AE10 AD9 AF8 AE6 AD7 AF6 AC7 AD8 AE7 AD6 AF5 AD18 AE19 AF17 AF19 AF18 AE18 AF20 AD19 AD21 AF22 AC21 AF21 AE21 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD — — — — — — — — — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 51 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal MEMC_MDQ29 MEMC_MDQ30 MEMC_MDQ31 MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS0 MEMC_MDQS1 MEMC_MDQS2 MEMC_MDQS3 MEMC_MBA0 MEMC_MBA1 MEMC_MBA2 MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS Package Pin Number AD20 AF23 AD22 AC9 AD5 AE20 AE22 AE8 AE5 AC19 AE23 AD16 AD17 AE17 AD12 AE12 AF12 AC13 AD13 AE13 AF13 AC15 AD15 AE15 AF15 AE16 AF16 AB16 AC17 AE11 AD11 AC11 Pin Type IO IO IO O O O O IO IO IO IO O O O O O O O O O O O O O O O O O O O O O Power Supply GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD Notes — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 52 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal MEMC_MCKE MEMC_MCK MEMC_MCK MEMC_MODT Package Pin Number AD14 AF14 AE14 AF11 Local Bus Controller Interface LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LCS0 N25 P26 P25 R26 R25 T26 T25 U25 M24 N24 P24 R24 T24 U24 U26 V26 K25 L25 L26 L24 M26 M25 N26 AC24 AC25 AB23 AB24 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O O O O OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD — — — — — — — — — — — — — — — — — — — — — — — — — — 4 Pin Type O O O O Power Supply GVDD GVDD GVDD GVDD Notes 3 — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 53 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal LCS1 LCS2 LCS3 LWE0 LWE1 LBCTL RST_LALE/M1LALE/M2LALE CFG_RESET_SOURCE[0]/LSDA10/LGPL0 CFG_RESET_SOURCE[1]/LSDWE/LGPL1 LSDRAS/LGPL2/LOE CFG_RESET_SOURCE[2]/LSDCAS/LGPL3 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 PD_XLB_CLOCK_OUT/LCLK0/ PD_MG2XLB_ENC_CLOCK/CORE_CLK_OUT PD_XLB2MG_DDR_CLOCK/LCLK1/ PD_MG2XLB_ENC_SYNC DUART UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS1/MSRCID2 (DDR ID)/LSRCID2 UART_RTS1/MSRCID3 (DDR ID)/LSRCID3 UART_SOUT2/MSRCID4 (DDR ID)/LSRCID4 UART_SIN2/MDVAL (DDR ID)/LDVAL UART_CTS2 UART_RTS2 I2C interface IIC_SDA/CKSTOP_OUT IIC_SCL/CKSTOP_IN AE24 AF24 Programmable Interrupt Controller MCP_OUT IRQ0/MCP_IN IRQ1 AD25 AD26 K1 O I IO OV DD OV DD OV DD — — — IO IO OV DD OV DD 2 2 G1 G2 H3 K3 H2 H1 J3 K4 IO IO IO IO IO IO IO IO OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD — — — — — — — — Package Pin Number AB25 AA23 AA24 Y23 W25 V25 V24 L23 K23 J23 H23 G23 AC22 Y24 Y25 Pin Type O O O O O O O IO IO O IO IO O O O Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes 4 4 4 4 4 4 — — — 4 — 4 4 — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 54 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal IRQ2 IRQ3 IRQ4 IRQ5 IRQ6/CKSTOP_OUT IRQ7/CKSTOP_IN CFG_CLKIN_DIV CFG_LBIU_MUX_EN JTAG TCK TDI TDO TMS TRST TEST TEST_MODE PMC QUIESCE T23 System Control HRESET PORESET SRESET Clocks CLKIN CLKIN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN/PCI_CLK PCI_CLK0/clkpd_cerisc1_ipg_clkout/DPTC_OSC PCI_CLK1/clkpd_half_cemb4ucc1_ipg_clkout/ CLOCK_XLB_CLOCK_OUT PCI_CLK2/clkpd_third_cesog_ipg_clkout/ cecl_ipg_ce_clock R3 P4 V1 U23 V2 T3 U2 R4 I O O I I O O O OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD — — 3 — — — — — AC23 AD23 AD24 IO I IO OV DD OV DD OV DD 1 — 2 O OV DD — N23 I OV DD 6 W26 Y26 AA26 AB26 AC26 I I O I I OV DD OV DD OV DD OV DD OV DD — 4 3 4 4 Package Pin Number K2 J2 J1 AE26 AE25 AF25 F1 M23 Pin Type I I I I IO I I I Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 55 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal Package Pin Number Power and Ground Supplies AVDD1 AVDD2 AVDD3 AVDD4 MVREF1 P3 AA1 AB15 C24 AB8 I I I I I AV DD1 AV DD2 AV DD3 AV DD4 DDR reference voltage DDR reference voltage — — — — — Pin Type Power Supply Notes MVREF2 AB17 I — PCI PCI_INTA /IRQ_OUT PCI_RESET_OUT PCI_AD0/MSRCID0 (DDR ID) PCI_AD1/MSRCID1 (DDR ID) PCI_AD2/MSRCID2 (DDR ID) PCI_AD3/MSRCID3 (DDR ID) PCI_AD4/MSRCID4 (DDR ID) PCI_AD5/MDVAL (DDR ID) PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14/ECID_TMODE_IN PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 AF2 AE2 L1 L2 M1 M2 L3 N1 N2 M3 P1 R1 N3 N4 T1 R2 T2 U1 Y2 Y1 AA2 AB1 O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD 2 — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 56 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C_BE0 PCI_C_BE1 PCI_C_BE2 PCI_C_BE3 PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN Package Pin Number AB2 Y4 AC1 AA3 AA4 AD1 AD2 AB3 AB4 AE1 AC3 AC4 M4 T4 Y3 AC2 U3 W1 W4 W2 V4 W3 P2 U4 V3 AD4 AE3 AF3 AD3 AE4 AF4 L4 Pin Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I IO IO IO I I IO O O I Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes — — — — — — — — — — — — — — — — — 5 5 5 5 5 — 5 5 — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 57 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal Package Pin Number CE/GPIO GPIO_PA0/SER1_TXD[0]/TDMA_TXD[0]/USBTXN GPIO_PA1/SER1_TXD[1]/TDMA_TXD[1]/USBTXP GPIO_PA2/SER1_TXD[2]/TDMA_TXD[2] GPIO_PA3/SER1_TXD[3]/TDMA_TXD[3] GPIO_PA4/SER1_RXD[0]/TDMA_RXD[0]/USBRXP GPIO_PA5/SER1_RXD[1]/TDMA_RXD[1]/USBRXN GPIO_PA6/SER1_RXD[2]/TDMA_RXD[2]/USBRXD GPIO_PA7/SER1_RXD[3]/TDMA_RXD[3] GPIO_PA8/SER1_CD/TDMA_REQ/USBOE GPIO_PA9 TDMA_CLKO GPIO_PA10/SER1_CTS/TDMA_RSYNC GPIO_PA11/TDMA_STROBE GPIO_PA12/SER1_RTS/TDMA_TSYNC GPIO_PA13/CLK9/BRGO9 GPIO_PA14/CLK11/BRGO10 GPIO_PA15/BRGO7 GPIO_PA16/ LA0 (LBIU) GPIO_PA17/ LA1 (LBIU) GPIO_PA18/Enet2_TXD[0]/SER2_TXD[0]/ TDMB_TXD[0]/LA2 (LBIU) GPIO_PA19/Enet2_TXD[1]/SER2_TXD[1]/ TDMB_TXD[1]/LA3 (LBIU) GPIO_PA20/Enet2_TXD[2]/SER2_TXD[2]/ TDMB_TXD[2]/LA4 (LBIU) GPIO_PA21/Enet2_TXD[3]/SER2_TXD[3]/ TDMB_TXD[3]/LA5 (LBIU) GPIO_PA22/Enet2_RXD[0]/SER2_RXD[0]/ TDMB_RXD[0]/LA6 (LBIU) GPIO_PA23/Enet2_RXD[1]/SER2_RXD[1]/ TDMB_RXD[1]/LA7 (LBIU) GPIO_PA24/Enet2_RXD[2]/SER2_RXD[2]/ TDMB_RXD[2]/LA8 (LBIU) GPIO_PA25/Enet2_RXD[3]/SER2_RXD[3]/ TDMB_RXD[3]/LA9 (LBIU) G3 F3 F2 E3 E2 E1 D3 D2 D1 C3 C2 C1 B1 H4 G4 J4 K24 K26 G25 G26 H25 H26 C25 C26 D25 D26 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD — — — — — — — — — — — — — — — — — — — — — — — — — — Pin Type Power Supply Notes M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 58 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PA26/Enet2_RX_ER/SER2_CD/TDMB_REQ/ LA10 (LBIU) GPIO_PA27/Enet2_TX_ER/TDMB_CLKO/LA11 (LBIU) GPIO_PA28/Enet2_RX_DV/SER2_CTS/ TDMB_RSYNC/LA12 (LBIU) GPIO_PA29/Enet2_COL/RXD[4]/SER2_RXD[4]/ TDMB_STROBE/LA13 (LBIU) GPIO_PA30/Enet2_TX_EN/SER2_RTS/ TDMB_TSYNC/LA14 (LBIU) GPIO_PA31/Enet2_CRS/SDET LA15 (LBIU) GPIO_PB0/Enet3_TXD[0]/SER3_TXD[0]/ TDMC_TXD[0] GPIO_PB1/Enet3_TXD[1]/SER3_TXD[1]/ TDMC_TXD[1] GPIO_PB2/Enet3_TXD[2]/SER3_TXD[2]/ TDMC_TXD[2] GPIO_PB3/Enet3_TXD[3]/SER3_TXD[3]/ TDMC_TXD[3] GPIO_PB4/Enet3_RXD[0]/SER3_RXD[0]/ TDMC_RXD[0] GPIO_PB5/Enet3_RXD[1]/SER3_RXD[1]/ TDMC_RXD[1] GPIO_PB6/Enet3_RXD[2]/SER3_RXD[2]/ TDMC_RXD[2] GPIO_PB7/Enet3_RXD[3]/SER3_RXD[3]/ TDMC_RXD[3] GPIO_PB8/Enet3_RX_ER/SER3_CD/TDMC_REQ GPIO_PB9/Enet3_TX_ER/TDMC_CLKO GPIO_PB10/Enet3_RX_DV/SER3_CTS/ TDMC_RSYNC GPIO_PB11/Enet3_COL/RXD[4]/SER3_RXD[4]/ TDMC_STROBE GPIO_PB12/Enet3_TX_EN/SER3_RTS/ TDMC_TSYNC GPIO_PB13/Enet3_CRS/SDET GPIO_PB14/CLK12 GPIO_PB15 UPC1_TxADDR[4] GPIO_PB16 UPC1_RxADDR[4] Package Pin Number E26 F25 E25 J25 F26 J26 A13 B13 A14 B14 B8 A8 A9 B9 A11 B11 A10 A15 B12 B15 D9 D14 B16 Pin Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes — — — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 59 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PB17/BRGO1/CE_EXT_REQ1 GPIO_PB18/Enet4_TXD[0]/SER4_TXD[0]/ TDMD_TXD[0] GPIO_PB19/Enet4_TXD[1]/SER4_TXD[1]/ TDMD_TXD[1] GPIO_PB20/Enet4_TXD[2]/SER4_TXD[2]/ TDMD_TXD[2] GPIO_PB21/Enet4_TXD[3]/SER4_TXD[3]/ TDMD_TXD[3] GPIO_PB22/Enet4_RXD[0]/SER4_RXD[0]/ TDMD_RXD[0] GPIO_PB23/Enet4_RXD[1]/SER4_RXD[1]/ TDMD_RXD[1] GPIO_PB24/Enet4_RXD[2]/SER4_RXD[2]/ TDMD_RXD[2] GPIO_PB25/Enet4_RXD[3]/SER4_RXD[3]/ TDMD_RXD[3] GPIO_PB26/Enet4_RX_ER/SER4_CD/TDMD_REQ GPIO_PB27/Enet4_TX_ER/TDMD_CLKO GPIO_PB28/Enet4_RX_DV/SER4_CTS/ TDMD_RSYNC GPIO_PB29/Enet4_COL/RXD[4]/SER4_RXD[4]/ TDMD_STROBE GPIO_PB30/Enet4_TX_EN/SER4_RTS/ TDMD_TSYNC GPIO_PB31/Enet4_CRS/SDET GPIO_PC0/UPC1_TxDATA[0]/SER5_TXD[0] GPIO_PC1/UPC1_TxDATA[1]/SER5_TXD[1] GPIO_PC2/UPC1_TxDATA[2]/SER5_TXD[2] GPIO_PC3/UPC1_TxDATA[3]/SER5_TXD[3] GPIO_PC4/UPC1_TxDATA[4] GPIO_PC5/UPC1_TxDATA[5] GPIO_PC6/UPC1_TxDATA[6] GPIO_PC7/UPC1_TxDATA[7] GPIO_PC8/UPC1_RxDATA[0]/SER5_RXD[0] GPIO_PC9/UPC1_RxDATA[1]/SER5_RXD[1] Package Pin Number D10 C10 C9 D8 C8 C15 C14 D13 C13 C12 D11 D12 D7 C11 C7 A18 A19 B18 B19 A24 B24 A23 B26 A21 B20 Pin Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OVDD OVDD Notes — — — — — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 60 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PC10/UPC1_RxDATA[2]/SER5_RXD[2] GPIO_PC11/UPC1_RxDATA[3]/SER5_RXD[3] GPIO_PC12/UPC1_RxDATA[4] GPIO_PC13/UPC1_RxDATA[5]/LSRCID0 GPIO_PC14/UPC1_RxDATA[6]/LSRCID1 GPIO_PC15/UPC1_RxDATA[7]/LSRCID2 GPIO_PC16/UPC1_TxADDR[0] GPIO_PC17/UPC1_TxADDR[1]/LSRCID3 GPIO_PC18/UPC1_TxADDR[2]/LSRCID4 GPIO_PC19/UPC1_TxADDR[3]/LDVAL GPIO_PC20/UPC1_RxADDR[0] GPIO_PC21/UPC1_RxADDR[1] GPIO_PC22/UPC1_RxADDR[2] GPIO_PC23/UPC1_RxADDR[3] GPIO_PC24/UPC1_RxSOC/SER5_CD GPIO_PC25/UPC1_RxCLAV GPIO_PC26/UPC1_RxPRTY/CE_EXT_REQ2 GPIO_PC27/UPC1_RxEN GPIO_PC28/UPC1_TxSOC GPIO_PC29/UPC1_TxCLAV/SER5_CTS GPIO_PC30/UPC1_TxPRTY GPIO_PC31/UPC1_TxEN/SER5_RTS GPIO_PD0/SPIMOSI GPIO_PD1/SPIMISO GPIO_PD2/SPICLK GPIO_PD3/SPISEL GPIO_PD4/SPI_MDIO/CE_MUX_MDIO GPIO_PD5/SPI_MDC/CE_MUX_MDC GPIO_PD6/CLK8/BRGO16/CE_EXT_REQ3 GPIO_PD7/GTM1_TIN1/GTM2_TIN2/CLK5 GPIO_PD8/GTM1_TGATE1/GTM2_TGATE2/CLK6 GPIO_PD9/GTM1_TOUT1 Package Pin Number B21 A20 D19 C18 D18 A25 C21 D22 C23 D23 C17 D17 C16 D16 A16 D20 E23 B17 B22 A17 A22 C20 A2 B2 B3 A3 A4 B4 F24 G24 H24 D24 Pin Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 61 Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal GPIO_PD10/GTM1_TIN2/GTM2_TIN1/CLK17 GPIO_PD11/GTM1_TGATE2/GTM2_TGATE1 GPIO_PD12/GTM1_TOUT2/GTM2_TOUT1 GPIO_PD13/GTM1_TIN3/GTM2_TIN4/BRGO8 GPIO_PD14/GTM1_TGATE3/GTM2_TGATE4 GPIO_PD15/GTM1_TOUT3 GPIO_PD16/GTM1_TIN4/GTM2_TIN3 GPIO_PD17/GTM1_TGATE4/GTM2_TGATE3 GPIO_PD18/GTM1_TOUT4/GTM2_TOUT3 GPIO_PD19/CE_RISC1_INT/CE_EXT_REQ4 GPIO_PD20/CLK18/BRGO6 GPIO_PD21/CLK16/BRGO5/UPC1_CLKO GPIO_PD22/CLK4/BRGO9/UCC2_CLKO GPIO_PD23/CLK3/BRGO10/UCC3_CLKO GPIO_PD24/CLK10/BRGO2/UCC4_CLKO GPIO_PD25/CLK13/BRGO16/UCC5_CLKO GPIO_PD26/CLK2/BRGO4/UCC1_CLKO GPIO_PD27/CLK1/BRGO3 GPIO_PD28/CLK19/BRGO11 GPIO_PD29/CLK15/BRGO8 GPIO_PD30/CLK14 GPIO_PD31/CLK7/BRGO15 Package Pin Number J24 B25 C4 D4 D5 A5 B5 C5 A6 B6 D21 C19 A7 B7 A12 B10 E4 F4 D15 C6 D6 E24 Power anf Ground Supplies GV DD AA8, AA10, AA11, AA13, AA14, AA16, AA17, AA19, AA21, AB9, AB10, AB11, AB12, AB14, AB18, AB20, AB21, AC6, AC8, AC14, AC18 E5, E6, E8, E9, E10, E12, E14, E15, E16, E18, E19, E20, E22, F5, F6, F8, F10, F14, F16, F19, F22, G22, H5, H6, H21, J5, J22, K21, K22, L5, L6, L22, M5, M22, N5, N21, N22, P6, P22, P23, R5, R23, T5, T21, T22, U6, U22, V5, V22, W22, Y5, AB5, AB6, AC5 GVDD — — Pin Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power Supply OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD OV DD Notes — — — — — — — — — — — — — — — — — — — — — — OVDD OV DD — — M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 62 Freescale Semiconductor Package and Pin Listings Table 55. MPC8323E PBGA Pinout Listing (continued) Signal VDD Package Pin Number K10, K11, K12, K13, K14, K15, K16, K17, L10, L17, M10, M17, N10, N17, P10, P17, R10, R17, T10, T17, U10, U11, U12, U13, U14, U15, U16, U17 B23, E7, E11, E13, E17, E21, F11, F13, F17, F21, F23, G5, H22, K5, K6, L11, L12, L13, L14, L15, L16, L21, M11, M12, M13, M14, M15, M16, N6, N11, N12, N13, N14, N15, N16, P5, P11, P12, P13, P14, P15, P16, P21, R11, R12, R13, R14, R15, R16, R22, T6, T11, T12, T13, T14, T15, T16, U5, U21, V23, W5, W6, W21, W23, W24, Y22, AA5, AA6, AA22, AA25, AB7, AB13, AB19, AB22, AC10, AC12, AC16, AC20 No Connect NC C22 — — — Pin Type VDD Power Supply — Notes — VSS VSS — — Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD. 2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. These JTAG and local bus pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull up if the chip is in PCI host mode. Follow the PCI specification’s recommendation. 6. This pin must always be tied to GND. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 63 Clocking 22 Clocking Figure 43 shows the internal distribution of clocks within the MPC8323E. e300c2 core MPC8323E Core PLL core_clk csb_clk to DDR memory controller DDR Clock Divider /2 MEMC_MCK MEMC_MCK DDR Memory Device QUICC Engine PLL Clock Unit System PLL ddr_clk ce_clk to QUICC Engine block lbc_clk /n LBC Clock Divider Local Bus Memory Device LCLK[0:1] to local bus csb_clk to rest of the device PCI_CLK/ PCI_SYNC_IN CFG_CLKIN_DIV CLKIN Crystal CLKIN PCI Clock Divider (÷2) 3 1 0 PCI_SYNC_OUT PCI_CLK_OUT[0:2] Figure 43. MPC8323E Clock Subsystem The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode, respectively. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 64 Freescale Semiconductor Clocking 22.1 Clocking in PCI Host Mode When the MPC8323E is configured as a PCI host device (RCWH[PCIHOST] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the PCI_SYNC_OUT and PCI_CLK_OUT multiplexors. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system. 22.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:2]) When the MPC8323E is configured as a PCI host, it provides three separate clock output signals, PCI_CLK_OUT[0:2], for external PCI agents. When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its corresponding OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other. 22.2 Clocking in PCI Agent Mode When the MPC8323E is configured as a PCI agent device, PCI_CLK is the primary input clock. In agent mode, the CLKIN signal should be tied to GND, and the clock output signals, PCI_CLK_OUTn and PCI_SYNC_OUT, are not used. 22.3 System Clock Domains As shown in Figure 43, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create three major clock domains: • The coherent system bus clock (csb_clk) • The QUICC Engine clock (ce_clk) • The internal clock for the DDR controller (ddr_clk) • The internal clock for the local bus controller (lb_clk) The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF In PCI host mode, PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300c2 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See the “Reset Configuration” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for more information. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 65 Clocking The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation: When CLKIN is the primary input clock, ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF) When PCI_CLK is the primary input clock, ce_clk = [primary clock input × CEPMF × (1 + ~CFG_CLKIN_DIV)] ÷ (1 + CEPDF) See the “QUICC Engine PLL Multiplication Factor” section and the “QUICC Engine PLL Division Factor” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for more information. The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. See the “LBC Bus Clock and Clock Ratios” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for more information. In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 56 specifies which units have a configurable clock frequency. Refer to the “System Clock Control Register (SCCR)” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for a detailed description. Table 56. Configurable Clock Units Unit Security core, I2C, SAP, TPR PCI and DMA complex Default Frequency Options Off, csb_clk/2, csb_clk/3 Off, csb_clk csb_clk csb_clk NOTE Setting the clock ratio of these units must be performed prior to any access to them. Table 57 provides the operating frequencies for the 8323E PBGA under recommended operating conditions (see Table 2). Table 57. Operating Frequencies for PBGA Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) QUICC Engine frequency (ce_clk) Max Operating Frequency 333 133 200 Unit MHz MHz MHz M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 66 Freescale Semiconductor Clocking Table 57. Operating Frequencies for PBGA (continued) Characteristic1 DDR1/DDR2 memory bus frequency (MCLK)2 Local bus frequency (LCLKn) 3 Max Operating Frequency 133 66 66 Unit MHz MHz MHz PCI input frequency (CLKIN or PCI_CLK) 1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2 The DDR1/DDR2 data rate is 2× the DDR1/DDR2 memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the csb_clk frequency (depending on RCWL[LBCM]). 22.4 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor encodings for the system PLL. NOTE System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 300–600 MHz. Table 58. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111–1111 System PLL Multiplication Factor Reserved Reserved ×2 ×3 ×4 ×5 ×6 Reserved As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 67 Clocking shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. Table 59. CSB Frequency Options Input Clock Frequency (MHz)2 CFG_CLKIN_DIV_B at Reset1 SPMF csb_clk : Input Clock Ratio 2 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 25 33.33 66.67 csb_clk Frequency (MHz) High High High High High High High High High High High High High High High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low 1 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 133 100 100 125 133 133 100 133 CFG_CLKIN_DIV_B is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV_B must be pulled up (high) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 68 Freescale Semiconductor Clocking 22.5 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values not listed in Table 60 should be considered reserved. Table 60. e300 Core PLL Configuration RCWL[COREPLL] core_clk : csb_clk Ratio 0-1 nn 2-5 0000 6 n PLL bypassed (PLL off, csb_clk clocks core directly) 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly) ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 NOTE Core VCO frequency = core frequency × VCO divider VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 500–800 MHz. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 69 Clocking 22.6 QUICC Engine PLL Configuration The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 61 shows the multiplication factor encodings for the QUICC Engine PLL. Table 61. QUICC Engine PLL Multiplication Factors QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF) Reserved ×2 ×3 ×4 ×5 ×6 ×7 ×8 Reserved RCWL[CEPMF] RCWL[CEPDF] 00000–00001 00010 00011 00100 00101 00110 00111 01000 01001–11111 0 0 0 0 0 0 0 0 0 The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 62. Table 62. QUICC Engine PLL VCO Divider RCWL[CEVCOD] 00 01 10 11 VCO Divider 4 8 2 Reserved NOTE The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine VCO frequency is in the range of 300–600 MHz. The QUICC Engine frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC Engine frequencies should be selected according to the performance requirements. The QUICC Engine VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF) QUICC Engine VCO Frequency = ce_clk × VCO divider × (1 + CEPDF) M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 70 Freescale Semiconductor Thermal 22.7 Suggested PLL Configurations To simplify the PLL configurations, the MPC8323E might be separated into two clock domains. The first domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs are configured separately. Both of the domains has one common input clock. Table 63 shows suggested PLL configurations for 33, 25, and 66 MHz input clocks. Table 63. Suggested PLL Configurations Input Clock Frequency (MHz) 33.33 25 66.67 33.33 25 66.67 CSB Frequency (MHz) 133.33 100 133.33 133.33 125 133.33 Core Frequency (MHz) 266.66 250 266.66 333.33 312.5 333.33 QUICC Engine Frequency (MHz) 200 200 200 200 200 200 Conf No. SPMF Core PLL CEMF CEDF 1 2 3 4 5 6 0100 0100 0010 0100 0101 0010 0000100 0000101 0000100 0000101 0000101 0000101 0110 1000 0011 0110 1000 0011 0 0 0 0 0 0 23 Thermal This section describes the thermal specifications of the MPC8323E. 23.1 Thermal Characteristics Table 64. Package Thermal Characteristics for PBGA Characteristic Board type Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — — Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC Value 28 21 23 18 13 9 Unit °C/W °C/W °C/W °C/W °C/W °C/W Notes 1, 2 1, 2 ,3 1, 3 1, 3 4 5 Table 64 provides the package thermal characteristics for the 516 27 × 27 mm PBGA of the MPC8323E. Junction-to-ambient natural convection Junction-to-ambient natural convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board Junction-to-case M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 71 Thermal Table 64. Package Thermal Characteristics for PBGA (continued) Characteristic Junction-to-package top Board type Natural convection Symbol ΨJT Value 2 Unit °C/W Notes 6 Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 23.2 Thermal Management Information For the following sections, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers. 23.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where: TJ = junction temperature (°C) TA = ambient temperature for the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 23.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 72 Freescale Semiconductor Thermal (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (°C) TB = board temperature at the package perimeter (°C) RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 23.2.3 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TJ = junction temperature (°C) TT = thermocouple temperature on top of package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 23.2.4 Heat Sinks and Junction-to-Case Thermal Resistance In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 73 Thermal where: RθJA = junction-to-ambient thermal resistance (°C/W) RθJC = junction-to-case thermal resistance (°C/W) RθCA = case-to-ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com 603-224-9988 408-567-8082 International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com 408-436-8770 800-522-2800 M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 74 Freescale Semiconductor Thermal Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 603-635-5102 781-935-4850 800-248-2481 888-642-7674 800-347-4572 23.3 Heat Sink Attachment When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force. If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. 23.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 Freescale Semiconductor 75 System Design Information interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. TJ = TC + (RθJC × PD) where: TC = case temperature of the package (°C) RθJC = junction-to-case thermal resistance (°C/W) PD = power dissipation (W) 24 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8323E. 24.1 System Clocking The MPC8323E includes three PLLs. • The system PLL (AVDD2) generates the system clock from the externally supplied CLKIN input. The frequency ratio between the system and CLKIN is selected using the system PLL ratio configuration bits as described in Section 22.4, “System PLL Configuration.” • The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio configuration bits as described in Section 22.5, “Core PLL Configuration.” • The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC Engine block generates or uses external sources for all required serial interface clocks. 24.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins. The voltage level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 44, one to each of the five AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. M PC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 76 Freescale Semiconductor System Design Information Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV DD pin, which is on the periphery of package, without the inductance of vias. Figure 44 shows the PLL power supply filter circuit. VDD 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors (