MPC8358E_11

Freescale Semiconductor Technical Data Document Number: MPC8358EEC Rev. 3, 01/2011 MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications This document provides an overview of the MPC8358E PowerQUICC II Pro processor revision 2.1 PBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure, and telecommunications markets. Target applications include next generation DSLAMs, network interface cards for 3G base stations (Node Bs), routers, media gateways, and high end IADs. The device extends current PowerQUICC II Pro offerings, adding higher CPU performance, additional functionality, faster interfaces, and robust interworking between protocols while addressing the requirements related to time-to-market, price, power, and package size. This device can be used for the control plane and also has data plane functionality. For functional characteristics of the processor, refer to the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, Rev. 3. To locate any updates for this document, refer to the MPC8360E product summary page on our website listed on the back cover of this document or contact your Freescale sales office. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . 12 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 13 RESET Initialization . . . . . . . . . . . . . . . . . . . . 15 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 UCC Ethernet Controller: Three-Speed Ethernet, MII Management . . . . . . . . . . . . . . . . . . . . . . . 25 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I 2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 59 HDLC, BISYNC, Transparent, and Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Package and Pin Listings . . . . . . . . . . . . . . . . . 65 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 System Design Information . . . . . . . . . . . . . . . 89 Ordering Information . . . . . . . . . . . . . . . . . . . . 92 Document Revision History . . . . . . . . . . . . . . 94 © 2011 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview This section describes a high-level overview including features and general operation of the MPC8358E PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™ 603e instruction set. The new QUICC Engine module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’s enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. Figure 1 shows the MPC8358E block diagram. e300 Core 32KB I-Cache 32KB D-Cache Security Engine System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration Multi-User RAM DUART Serial DMA & 2 Virtual DMAs Dual I2C 4 Channel DMA Interrupt Controller UCC1 UCC2 UCC3 UCC4 UCC5 UCC8 SPI1 SPI2 USB Protection & Configuration System Reset Clock Synthesizer DDRC PCI Local Classic G2 MMUs FPU JTAG/COP Power Management Timers QUICC Engine Module Baud Rate Generators Parallel I/O Accelerators Dual 32-Bit RISC CP Time Slot Assigner Serial Interface 4 TDM Ports 6 MII/ RMII 2 GMII/ RGMII/TBI/RTBI 1 UTOPIA/POS (31/124 MPHY) Figure 1. MPC8358E Block Diagram Major features of the MPC8358E are as follows: • e300 PowerPC processor core (enhanced version of the MPC603e core) — Operates at up to 400 MHz (for the MPC8358E) — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 2 Freescale Semiconductor Overview — — — — • 32-Kbyte instruction cache, 32-Kbyte data cache Lockable portion of L1 cache Dynamic power management Software-compatible with the Freescale processor families implementing the Power Architecture™ technology QUICC Engine unit — Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 400 MHz (for the MPC8358E) — Serial DMA channel for receive and transmit on all serial channels — QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™) — Six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously): – IEEE 1588 protocol supported – 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1 – 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2 – 9.6-Kbyte jumbo frames – ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T I.363.5 – ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2 – ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64-Kbyte simultaneous ATM channels – ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000 – IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1) – ATM Transmission Convergence layer support in accordance with ITU-T I.432 – ATM OAM handling features compatible with ITU-T I.610 – PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686, and 3153 – IP support for IPv4 packets including TOS, TTL, and header checksum processing – Ethernet over first mile IEEE 802.3ah – Shim header – Ethernet-to-Ethernet/AAL5/AAL2 inter-working – L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags 1.SMII or SGMII media-independent interface is not currently supported. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Overview • – ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports – Extensive support for ATM statistics and Ethernet RMON/MIB statistics – AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate – Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY – POS hardware; microcode must be loaded as an IRAM package – Transparent up to 70-Mbps full-duplex – HDLC up to 70-Mbps full-duplex – HDLC BUS up to 10 Mbps – Asynchronous HDLC – UART – BISYNC up to 2 Mbps – User-programmable Virtual FIFO size – QUICC multichannel controller (QMC) for 64 TDM channels — One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management — Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel — Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC serial channels — Four independent 16-bit timers that can be interconnected as four 32-bit timers — Interworking functionality: – Layer 2 10/100-Base T Ethernet switch – ATM-to-ATM switching (AAL0, 2, 5) – Ethernet-to-ATM switching with L3/L4 support – PPP interworking Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs). — Public key execution unit (PKEU) supporting the following: – RSA and Diffie-Hellman – Programmable field size up to 2048 bits – Elliptic curve cryptography – F2m and F(p) modes – Programmable field size up to 511 bits — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 4 Freescale Semiconductor Overview • • — Advanced encryption standard unit (AESU) — Implements the Rinjdael symmetric key cipher — Key lengths of 128, 192, and 256 bits, two key – ECB, CBC, CCM, and counter modes — ARC four execution unit (AFEU) – Implements a stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — Message digest execution unit (MDEU) – SHA with 160-, 224-, or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either SHA or MD5 algorithm — Random number generator (RNG) — Four crypto-channels, each supporting multi-command descriptor chains – Static and/or dynamic assignment of crypto-execution units via an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes — Storage/NAS XOR parity generation accelerator for RAID applications DDR SDRAM memory controller on the MPC8358E — Programmable timing supporting both DDR1 and DDR2 SDRAM — On the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus — 32- or 64-bit data interface, up to 266 MHz (for the MPC8358E) data rate — Four banks of memory, each up to 1 Gbyte — DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports — Full ECC support — Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2) — Contiguous or discontiguous memory mapping — Read-modify-write support — Sleep mode support for self refresh SDRAM — Supports auto refreshing — Supports source clock mode — On-the-fly power management using CKE — Registered DIMM support — 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 — External driver impedance calibration — On-die termination (ODT) PCI interface — PCI Specification Revision 2.3 compatible M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 5 Overview • • • — Data bus widths: – Single 32-bit data PCI interface that operates at up to 66 MHz — PCI 3.3-V compatible (not 5-V compatible) — PCI host bridge capabilities on both interfaces — PCI agent mode supported on PCI interface — Support for PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Support for posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration, supporting five masters on PCI — Support for accesses to all PCI address spaces — Parity support — Selectable hardware-enforced coherency — Address translation units for address mapping between host and peripheral — Dual address cycle supported when the device is the target — Internal configuration registers accessible from PCI Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 133 MHz — Eight chip selects support eight external slaves — Up to eight-beat burst transfers — 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for 8 external and 35 internal discrete interrupt sources — Support for one external (optional) and seven internal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source Dual industry-standard I2C interfaces — Two-wire interface M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 6 Freescale Semiconductor Electrical Characteristics — — — — • • • • • Multiple master support Master or slave I2C mode support On-chip digital filtering rejects spikes on the bus System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller — Four independent virtual channels — Concurrent execution across multiple channels with programmable bandwidth control — All channels accessible by local core and remote PCI masters — Misaligned transfer capability — Data chaining and direct mode — Interrupt on completed segment and chain — DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions. DUART — Two 4-wire interfaces (RxD, TxD, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D System timers — Periodic interrupt timer — Real-time clock — Software watchdog timer — Eight general-purpose timers IEEE Std. 1149.1™-compliant, JTAG boundary scan Integrated PCI bus and SDRAM clock generation 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8358E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 7 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD –0.3 to 1.32 AVDD –0.3 to 1.32 GVDD DDR DDR2 –0.3 to 2.75 –0.3 to 1.89 LVDD OV DD MVIN MVREF LVIN OVIN –0.3 to 3.63 –0.3 to 3.63 –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (OVDD + 0.3) V V V V V V — — 2, 5 2, 5 4, 5 3, 5 Max Value Unit V V V Notes — — — Table 1 provides the absolute maximum ratings. Core supply voltage PLL supply voltage DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals Local bus, DUART, CLKIN, system control and power management, I2C, SPI, and JTAG signals PCI Storage temperature range OVIN TSTG –0.3 to (OVDD + 0.3) –55 to 150 V °C 6 — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 8 Freescale Semiconductor Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage DDR and DDR2 DRAM I/O supply voltage DDR DDR2 Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage PCI, local bus, DUART, system control and power management, I2C, SPI, and JTAG I/O voltage Junction temperature LVDD0 LVDD1 LVDD2 OV DD TJ Symbol VDD AVDD GVDD 2.5 V ± 125 mV 1.8 V ± 90 mV 3.3 V ± 330 mV 2.5 V ± 125 mV 3.3 V ± 330 mV 2.5 V ± 125 mV 3.3 V ± 330 mV 2.5 V ± 125 mV 3.3 V ± 330 mV 0 to 105 –40 to 105 V V V V °C — — — — — Recommended Value 1.2 V ± 60 mV 1.2 V ± 60 mV Unit V V V Notes 1 1 — Notes: 1. GV DD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 9 Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the device. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. Note that tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform –3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) 4 ns (Max) Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 10 Freescale Semiconductor Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Local bus interface utilities signals PCI signals PCI output clocks (including PCI_SYNC_OUT) DDR signal DDR2 signal 10/100/1000 Ethernet signals DUART, system control, GPIO signals 1 Output Impedance (Ω) 42 25 42 20 36 (half-strength mode)1 18 36 (half-strength mode)1 42 42 42 Supply Voltage OVDD = 3.3 V GVDD = 2.5 V GVDD = 1.8 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V LVDD = 2.5/3.3 V I2C, SPI, JTAG DDR output impedance values for half strength mode are verified by design and not tested. 2.2 Power Sequencing This section details the power sequencing considerations for the MPC8358E. 2.2.1 Power-Up Sequencing MPC8358E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD, LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 11 Power Characteristics Voltage I/O Voltage (GVDD, LV DD, OVDD) Core Voltage (VDD, AVDD) 0.7 V 90% Time Figure 4. Power Sequencing Example I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another. 2.2.2 Power-Down Sequencing The MPC8358E does not require the core supply voltage and I/O supply voltages to be powered down in any particular order. 3 Power Characteristics Table 4. MPC8358E PBGA Core Power Dissipation1 Core Frequency (MHz) 266 400 400 CSB Frequency (MHz) 266 266 266 QUICC Engine Frequency (MHz) 266 266 400 Typical 2.2 2.4 2.5 Maximum 2.3 2.5 2.6 Unit W W W Notes 2, 3, 4 2, 3, 4 2, 3, 4 The estimated typical power dissipation values are shown in Table 4. Notes: 1. The values do not include I/O supply power (OV DD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5. 2. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark application. 3. Thermal solutions will likely need to design to a value higher than typical power on the end application, TA target, and I/O power. 4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105°C, and an artificial smoke test. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 12 Freescale Semiconductor Clock Input Timing Table 5 shows the estimated typical I/O power dissipation for the device. Table 5. Estimated Typical I/O Power Dissipation Interface DDR I/O 65% utilization 2.5 V Rs = 2 0 Ω Rt = 5 0 Ω 2 pairs of clocks Parameter 200 MHz, 1x32 bits 200 MHz, 1x64 bits 200 MHz, 2x32 bits 266 MHz, 1x32 bits 266 MHz, 1x64 bits 266 MHz, 2x32 bits Local Bus I/O Load = 25 pf 3 pairs of clocks 133 MHz, 32 bits 83 MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits PCI I/O Load = 30 pF 10/100/1000 Ethernet I/O Load = 20 pF 33 MHz, 32 bits 66 MHz, 32 bits MII or RMII GMII or TBI RGMII or RTBI Other I/O — GVDD (1.8 V) 0.3 0.4 0.6 0.35 0.46 0.7 — — — — — — — — — — GVDD (2.5 V) 0.46 0.58 0.92 0.56 0.7 1.11 — — — — — — — — — — OV DD (3.3 V) — — — — — — 0.22 0.14 0.12 0.09 0.05 0.07 — — — 0.1 LVDD (3.3 V) — — — — — — — — — — — — 0.01 0.04 — — LVDD (2.5 V) — — — — — — — — — — — — — — 0.04 — Unit W W W W W W W W W W W W W W W W — Comments — — — — — — — — — — — — Multiply by number of interfaces used. 4 Clock Input Timing NOTE The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VDD; fall time refers to transitions from 90% to 10% of VDD. This section provides the clock input DC and AC electrical characteristics for the MPC8358E. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 13 Clock Input Timing 4.1 DC Electrical Characteristics Table 6. CLKIN DC Electrical Characteristics Parameter Condition — — 0 V ≤ VIN ≤ OVDD 0 V ≤ VIN ≤ 0.5V or OV DD – 0.5V ≤ VIN ≤ OVDD 0.5 V ≤ VIN ≤ OVDD – 0.5 V Symbol VIH VIL IIN IIN IIN Min 2.7 –0.3 — — — Max OVDD + 0.3 0.4 ±10 ±10 ±100 Unit V V μA μA μA Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device. Input high voltage Input low voltage CLKIN input current PCI_SYNC_IN input current PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the device. Table 7. CLKIN AC Timing Specifications Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tKHK/tCLKIN — Min — 15 0.6 40 — Typical — — 1.0 — — Max 66.67 — 2.3 60 ±150 Unit MHz ns ns % ps Notes 1 — 2 3 4, 5 Notes: 1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be 1,000,000 16 Unit baud baud — Notes — 1 2 Table 23 provides the AC timing parameters for the DUART interface of the device. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. 8 UCC Ethernet Controller: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 25 UCC Ethernet Controller: Three-Speed Ethernet, MII Management 8.1 Three-Speed Ethernet Controller (10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII (media independent interface), RMII (reduced media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and MDC (management data clock). The MII, RMII, GMII, and TBI interfaces are only defined for 3.3 V, while the RGMII and RTBI interfaces are only defined for 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for the MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 10/100/1000 Ethernet DC Electrical Characteristics The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC). The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification Version 1.2. Table 24. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V) Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol LVDD VOH VOL VIH VIL IIN IOH = –4.0 mA IOL = 4.0 mA — — Conditions — LVDD = M in LVDD = M in — — Min 2.97 2.40 GND 2.0 –0.3 — Max 3.63 LVDD + 0.3 0.50 LVDD + 0.3 0.90 ±10 Unit V V V V V μA Notes 1 — — — — — 0 V ≤ VIN ≤ LVDD Note: 1. GMII/MII pins that are not needed for RGMII, RMII, or RTBI operation are powered by the OV DD supply. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 26 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Table 25. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V) Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol LVDD VOH VOL VIH VIL IIN IOH = –1.0 mA IOL = 1.0 mA — — Conditions — LVDD = M in LVDD = M in LVDD = M in LVDD = M in Min 2.37 2.00 GND – 0.3 1.7 –0.3 — Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 ±10 Unit V V V V V μA 0 V ≤ VIN ≤ LVDD 8.2 GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This sections describe the GMII transmit and receive AC timing specifications. 8.2.1.1 GMII Transmit AC Timing Specifications Table 26. GMII Transmit AC Timing Specifications Table 26 provides the GMII transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, (20% to 80%) GTX_CLK clock fall time, (80% to 20%) GTX_CLK125 clock period GTX_CLK125 reference clock duty cycle measured at LVDD/2 Symbol1 tGTX tGTXH/tGTX tGTKHDX tGTKHDV tGTXR tGTXF tG125 tG125H/tG125 Min — 40 0.5 — — — — 45 Typ 8.0 — — — — 8.0 — Max — 60 — 5.0 1.0 1.0 — 55 Unit ns % ns ns ns ns % Notes — — — — — 2 2 Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming convention. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 27 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 9 shows the GMII transmit AC timing diagram. tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTXF tGTXR Figure 9. GMII Transmit AC Timing Diagram 8.2.1.2 GMII Receive AC Timing Specifications Table 27. GMII Receive AC Timing Specifications Table 27 provides the GMII receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, (20% to 80%) RX_CLK clock fall time, (80% to 20%) Symbol1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF Min — 40 2.0 0.3 — — Typ 8.0 — — — — — Max — 60 — — 1.0 1.0 Unit ns % ns ns ns ns Notes — — — — — — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 28 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 10 shows the GMII receive AC timing diagram. tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR Figure 10. GMII Receive AC Timing Diagram 8.2.2 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.2.1 MII Transmit AC Timing Specifications Table 28. MII Transmit AC Timing Specifications Table 28 provides the MII transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise time, (20% to 80%) TX_CLK data clock fall time, (80% to 20%) Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTKHDV tMTXR tMTXF Min — — 35 1 — 1.0 1.0 Typ 400 40 — 5 — — Max — — 65 — 15 4.0 4.0 Unit ns ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 29 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 11 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 11. MII Transmit AC Timing Diagram 8.2.2.2 MII Receive AC Timing Specifications Table 29. MII Receive AC Timing Specifications Table 29 provides the MII receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time, (20% to 80%) RX_CLK clock fall time, (80% to 20%) Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF Min — — 35 10.0 10.0 1.0 1.0 Typ 400 40 — — — — — Max — — 65 — — 4.0 4.0 Unit ns ns % ns ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 12 provides the AC test load. Output Z0 = 50 Ω RL = 5 0 Ω LVDD/2 Figure 12. AC Test Load M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 30 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 13 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 13. MII Receive AC Timing Diagram 8.2.3 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.3.1 RMII Transmit AC Timing Specifications Table 30. RMII Transmit AC Timing Specifications Table 30 provides the RMII transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to RMII data TXD[1:0], TX_EN delay REF_CLK data clock rise time REF_CLK data clock fall time Symbol1 tRMX tRMXH/tRMX tRMTKHDX tRMTKHDV tRMXR tRMXF Min — 35 2 — 1.0 1.0 Typ 20 — — — — Max — 65 — 10 4.0 4.0 Unit ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 31 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 14 shows the RMII transmit AC timing diagram. tRMX REF_CLK tRMXH TXD[1:0] TX_EN tRMTKHDX tRMXF tRMXR Figure 14. RMII Transmit AC Timing Diagram 8.2.3.2 RMII Receive AC Timing Specifications Table 31. RMII Receive AC Timing Specifications Table 31 provides the RMII receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise time REF_CLK clock fall time Symbol1 tRMX tRMXH/tRMX tRMRDVKH tRMRDXKH tRMXR tRMXF Min — 35 4.0 2.0 1.0 1.0 Typ 20 — — — — — Max — 65 — — 4.0 4.0 Unit ns % ns ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 15 provides the AC test load. Output Z0 = 50 Ω RL = 5 0 Ω LVDD/2 Figure 15. AC Test Load M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 32 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 16 shows the RMII receive AC timing diagram. tRMX REF_CLK tRMXH RXD[1:0] CRS_DV RX_ER tRMRDVKH tRMRDXKH tRMXF Valid Data tRMXR Figure 16. RMII Receive AC Timing Diagram 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.4.1 TBI Transmit AC Timing Specifications Table 32. TBI Transmit AC Timing Specifications Table 32 provides the TBI transmit AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TBI data TCG[9:0] delay GTX_CLK clock rise time, (20% to 80%) GTX_CLK clock fall time, (80% to 20%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle Symbol1 tTTX tTTXH/tTTX tTTKHDX tTTKHDV tTTXR tTTXF tG125 tG125H/tG125 Min — 40 0.9 — — — — 45 Typ 8.0 — — — — 8.0 — Max — 60 — 5.0 1.0 1.0 — 55 Unit ns % ns ns ns ns ns Notes — — — — 2 — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 33 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 17 shows the TBI transmit AC timing diagram. tTTX GTX_CLK tTTXH TXD[7:0] TX_EN TX_ER tTTXF tTTXR tTTKHDX Figure 17. TBI Transmit AC Timing Diagram 8.2.4.2 TBI Receive AC Timing Specifications Table 33. TBI Receive AC Timing Specifications Table 33 provides the TBI receive AC timing specifications. At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%. Parameter/Condition PMA_RX_CLK clock period PMA_RX_CLK skew RX_CLK duty cycle RCG[9:0] setup time to rising PMA_RX_CLK RCG[9:0] hold time to rising PMA_RX_CLK RX_CLK clock rise time, VIL(min) to VIH(max) RX_CLK clock fall time, V IH(max) to VIL(min) Symbol1 tTRX tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR tTRXF Min — 7.5 40 2.5 1.0 0.7 0.7 Typ 16.0 — — — — — — Max — 8.5 60 — — 2.4 2.4 Unit ns ns % ns ns ns ns Notes — — — 2 2 — — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of odd numbered RCG are measured from riding edge of PMA_RX_CLK0. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 34 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management Figure 18 shows the TBI receive AC timing diagram. tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Even RCG Odd RCG tTRXR Figure 18. TBI Receive AC Timing Diagram 8.2.5 RGMII and RTBI AC Timing Specifications Table 34. RGMII and RTBI AC Timing Specifications Table 34 presents the RGMII and RTBI AC timing specifications. At recommended operating conditions with LVDD of 2.5 V ± 5%. Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20–80%) Fall time (20–80%) GTX_CLK125 reference clock period Symbol1 tSKRGTKHDX tSKRGTKHDV tSKRGDXKH tSKRGDVKH tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG125 Min –0.5 — 1.1 — 7.2 45 40 — — — Typ — — 8.0 50 50 — — 8.0 Max — 0.5 — 2.6 8.8 55 60 0.75 0.75 — Unit ns ns ns % % ns ns ns Notes 2 3 4, 5 3, 5 — — 6 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 35 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Table 34. RGMII and RTBI AC Timing Specifications (continued) At recommended operating conditions with LVDD of 2.5 V ± 5%. Parameter/Condition GTX_CLK125 reference clock duty cycle Symbol1 tG125H/tG125 Min 47 Typ — Max 53 Unit % Notes — Notes: 1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (Rx) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5. Duty cycle reference is LVDD/2. 6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. 7. In rev. 2.1 silicon, due to errata, tSKRGTKHDX minimum is –0.65 ns for UCC2 option 1 and –0.9 for UCC2 option 2, and tSKRGTKHDV maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. UCC1 does meet tSKRGTKHDX minimum for rev. 2.1 silicon. Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGTKHDX TXD[8:5][3:0] TXD[7:4][3:0] TXD[8:5] TXD[3:0] TXD[7:4] TXD[4] TXEN TXD[9] TXERR tSKRGTKHDX TX_CLK (At PHY) TX_CTL RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGTKHDX RXD[4] RXDV RXD[9] RXERR tSKRGTKHDX RX_CTL RX_CLK (At PHY) Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 36 Freescale Semiconductor UCC Ethernet Controller: Three-Speed Ethernet, MII Management 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, TBI, and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller (10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics.” 8.3.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 35. Table 35. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN Conditions — IOH = –1.0 mA IOL = 1.0 mA — — 0 V ≤ VIN ≤ OVDD OVDD = Min OVDD = Min Min 2.97 2.10 GND 2.00 — — Max 3.63 OVDD + 0.3 0.50 — 0.80 ±10 Unit V V V V V μA 8.3.2 MII Management AC Electrical Specifications Table 36. MII Management AC Timing Specifications Table 36 provides the MII management AC timing specifications. At recommended operating conditions with LVDD is 3.3 V ± 10%. Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time Symbol1 fMDC tMDC tMDCH tMDTKHDX tMDTKHDV tMDRDVKH tMDRDXKH tMDCR Min — — 32 10 — 10 0 — Typ 2.5 400 — — — — — Max — — — — 110 — — 10 Unit MHz ns ns ns ns ns ns Notes 2 — — 3 — — — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 37 UCC Ethernet Controller: Three-Speed Ethernet, MII Management Table 36. MII Management AC Timing Specifications (continued) At recommended operating conditions with LVDD is 3.3 V ± 10%. Parameter/Condition MDC fall time Symbol1 tMDHF Min — Typ — Max 10 Unit ns Notes — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDRDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of 300 MHz, the delay is 63 ns). Figure 20 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDRDVKH tMDRDXKH MDIO (Output) tMDTKHDX tMDHF tMDCR Figure 20. MII Management Interface Timing Diagram 8.3.3 IEEE 1588 Timer AC Specifications Table 37. IEEE 1588 Timer AC Specifications Parameter Symbol tTMRCK tTMRCKS tTMRCKH tGCLKNV Min 0 — — 0 Max 70 — — 6 Unit MHz — — ns Notes 1 2, 3 2, 3 — Table 37 provides the IEEE 1588 timer AC specifications. Timer clock frequency Input setup to timer clock Input hold from timer clock Output clock to output valid M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 38 Freescale Semiconductor Local Bus Table 37. IEEE 1588 Timer AC Specifications (continued) Parameter Timer alarm to output valid Symbol tTMRAL Min — Max — Unit — Notes 2 Notes: 1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. The minimum and maximum requirement for both rtc_clock and tmr_clock are the same. 2. These are asynchronous signals. 3. Inputs need to be stable at least one TMR clock. 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8358E. 9.1 Local Bus DC Electrical Characteristics Table 38. Local Bus DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OV DD – 0.4 — — Max OVDD + 0.3 0.8 — 0.2 ±10 Unit V V V V μA Table 38 provides the DC electrical characteristics for the local bus interface. High-level input voltage Low-level input voltage High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Input current 9.2 Local Bus AC Electrical Specifications Table 39. Local Bus General Timing Parameters—DLL Enabled Parameter Symbol1 tLBK tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT1 tLBOTOT2 tLBOTOT3 Min 7.5 1.7 1.9 1.0 1.0 1.5 3.0 2.5 Max — — — — — — — — Unit ns ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 3, 4 3, 4 5 6 7 Table 39 describes the general timing parameters of the local bus interface of the device. Local bus cycle time Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 39 Local Bus Table 39. Local Bus General Timing Parameters—DLL Enabled (continued) Parameter Local bus clock to LALE rise Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHLR tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOX1 tLBKHOX2 tLBKHOZ Min — — — — 1.0 1.0 — Max 4.5 4.5 4.5 4.5 — — 3.8 Unit ns ns ns ns ns ns ns Notes — — 3 3 3 3 — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Table 40 describes the general timing parameters of the local bus interface of the device. Table 40. Local Bus General Timing Parameters—DLL Bypass Mode Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid Symbol1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHOV Min 15 7 1.0 1.5 3 2.5 — Max — — — — — — 3 Unit ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 3 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 40 Freescale Semiconductor Local Bus Table 40. Local Bus General Timing Parameters—DLL Bypass Mode (continued) Parameter Local bus clock to output high impedance for LAD/LDP Symbol1 tLBKHOZ Min — Max 4 Unit ns Notes — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins. 7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 21 provides the AC test load for the local bus. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 21. Local Bus C Test Load M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 41 Local Bus Figure 22 through Figure 27 show the local bus signals. LSYNC_IN tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV Output (Address) Signal: LAD[0:31] tLBKHLR LALE tLBOTOT tLBKHOZ tLBKHOX tLBKHOV tLBKHOX tLBIXKH tLBKHOV tLBKHOZ tLBKHOX Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) LCLK[n] tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output Signals: LAD[0:31]/LDP[0:3] tLBOTOT LALE tLBKHOV tLBIXKH tLBIXKH tLBKHOV tLBKHOZ Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 42 Freescale Semiconductor Local Bus LSYNC_IN T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Enabled) LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Bypass Mode) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 43 Local Bus LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH tLBIXKH tLBIXKH tLBKHOZ Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Bypass Mode) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 44 Freescale Semiconductor JTAG LSYNC_IN T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Enabled) 10 JTAG This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8358E. 10.1 JTAG DC Electrical Characteristics Table 41. JTAG interface DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.5 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±10 Unit V V V V V μA Table 41 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the device. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 45 JTAG 10.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device. Table 42 provides the JTAG AC timing specifications as defined in Figure 29 through Figure 32. Table 42. JTAG AC Timing Specifications (Independent of CLKIN)1 At recommended operating conditions (see Table 2). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock duty cycle JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol 2 fJTG tJTG tJTKHKL/tJTG tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ Min 0 30 45 0 25 4 4 10 10 2 2 2 2 2 2 Max 33.3 — 55 2 — — — Unit MHz ns % ns ns ns Notes — — — — 3 4 ns — — ns 11 11 ns — — ns 19 9 5, 6 6 5 5 4 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 21). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 46 Freescale Semiconductor JTAG Figure 28 provides the AC test load for TDO and the boundary-scan outputs of the device. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 28. AC Test Load for the JTAG Interface Figure 29 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 29. JTAG Clock Input Timing Diagram Figure 30 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD /2) VM Figure 30. TRST Timing Diagram Figure 31 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OV DD/2) Output Data Valid Input Data Valid VM Figure 31. Boundary-Scan Timing Diagram M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 47 JTAG Figure 32 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 32. Test Access Port Timing Diagram M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 48 Freescale Semiconductor I2C 11 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8358E. 11.1 I2C DC Electrical Characteristics Table 43. I2C DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the I2C interface of the device. At recommended operating conditions with OVDD of 3.3 V ± 10%. Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current (0 V ≤ VIN ≤ OV DD) Symbol VIH VIL VOL tI2KLKV tI2KHKL CI IIN Min 0.7 × OV DD –0.3 0 20 + 0.1 × CB 0 — — Max OVDD + 0.3 0.3 × OV DD 0.4 250 50 10 ±10 Unit V V V ns ns pF μA Notes — — 1 2 3 — 4 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8360E Integrated Communications Processor Family Reference Manual for information on the digital filter used. 4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. 11.2 I2C AC Electrical Specifications Table 44. I2C AC Electrical Specifications Table 44 provides the AC timing parameters for the I2C interface of the device. All values refer to VIH (min) and VIL (max) levels (see Table 43). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH Min 0 1.3 0.6 0.6 0.6 100 Max 400 — — — — — Unit kHz μs μs μs μs ns M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 49 I2C Table 44. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 43). Parameter Data hold time: CBUS compatible masters I2C bus devices Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol1 tI2DXKL Min Max Unit μs — 02 tI2CR tI2CF tI2PVKH tI2KHDX VNL VNH 20 + 0.1 Cb4 20 + 0.1 Cb4 0.6 1.3 0.1 × OV DD 0.2 × OV DD — 0.93 300 300 — — — — ns ns μs μs V V Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Figure 33 provides the AC test load for the I2C. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 33. I2C AC Test Load Figure 34 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL 2 tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF tI2CH Sr tI2SVKH tI2PVKH P S Figure 34. I C Bus AC Timing Diagram M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 50 Freescale Semiconductor PCI 12 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8358E. 12.1 PCI DC Electrical Characteristics Table 45. PCI DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Test Condition VOUT ≥ VOH (min) or VOUT ≤ VOL (max) IOH = –500 μA IOL = 1500 μA 0V≤ VIN1 ≤ OVDD Min 0.5 × OVDD -0.5 0.9 × OVDD — — Max OVDD + 0.5 0.3 × OVDD — 0.1 × OVDD ±10 Unit V V V V μA Table 45 provides the DC electrical characteristics for the PCI interface of the device. High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Note: 1. Note that the symbol VIN, in this case, represents the OV IN symbol referenced in Table 1 and Table 2. 12.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. Table 46 provides the PCI AC timing specifications at 66 MHz. . Table 46. PCI AC Timing Specifications at 66 MHz Parameter Symbol1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min — 1 — 3.0 0.3 Max 6.0 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 51 PCI Table 47. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedance Input setup to clock Input hold from clock Symbol1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min — 2 — 7.0 0.3 Max 11 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 35 provides the AC test load for PCI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 35. PCI AC Test Load Figure 36 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 36. PCI Input AC Timing Measurement Conditions M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 52 Freescale Semiconductor Timers Figure 37 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 37. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8358E. 13.1 Timers DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 48. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±10 Unit V V V V V μA 13.2 Timers AC Timing Specifications Table 49. Timers Input AC Timing Specifications1 Characteristic Symbol2 tTIWID Typ 20 Unit ns Table 49 provides the timer input and output AC timing specifications. Timers inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 53 GPIO Figure 38 provides the AC test load for the timers. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 38. Timers AC Test Load 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8358E. 14.1 GPIO DC Electrical Characteristics Table 50. GPIO DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±10 Unit V V V V V μA Notes 1 1 1 1 — — Table 50 provides the DC electrical characteristics for the device GPIO. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Note: This specification applies when operating from 3.3-V supply. 14.2 GPIO AC Timing Specifications Table 51. GPIO Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Typ 20 Unit ns Table 51 provides the GPIO input and output AC timing specifications. GPIO inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 54 Freescale Semiconductor IPIC Figure 39 provides the AC test load for the GPIO. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 39. GPIO AC Test Load 15 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8358E. 15.1 IPIC DC Electrical Characteristics Table 52. IPIC DC Electrical Characteristics Characteristic Symbol VIH VIL IIN VOL VOL Condition — — — IOL = 6.0 mA IOL = 3.2 mA Min 2.0 –0.3 — — — Max OVDD + 0.3 0.8 ±10 0.5 0.4 Unit V V μA V V Table 52 provides the DC electrical characteristics for the external interrupt pins of the IPIC. Input high voltage Input low voltage Input current Output low voltage Output low voltage Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts. 2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins. 15.2 IPIC AC Timing Specifications Table 53. IPIC Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 53 provides the IPIC input and output AC timing specifications. IPIC inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8358E. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 55 SPI 16.1 SPI DC Electrical Characteristics Table 54. SPI DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±10 Unit V V V V V μA Table 54 provides the DC electrical characteristics for the device SPI. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 16.2 SPI AC Timing Specifications Table 55. SPI AC Timing Specifications1 Characteristic Symbol2 tNIKHOX tNIKHOV tNEKHOX tNEKHOV tNIIVKH tNIIXKH tNEIVKH tNEIXKH Min 0.4 — 2 — 8 0 4 2 Max — 8 — 8 — — — — Unit ns ns ns ns ns ns Table 55 and provide the SPI input and output AC timing specifications. SPI outputs—Master mode (internal clock) delay SPI outputs—Slave mode (external clock) delay SPI inputs—Master mode (internal clock) input setup time SPI inputs—Master mode (internal clock) input hold time SPI inputs—Slave mode (external clock) input setup time SPI inputs—Slave mode (external clock) input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI m emory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). Figure 40 provides the AC test load for the SPI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 40. SPI AC Test Load M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 56 Freescale Semiconductor TDM/SI Figure 41 and Figure 42 represent the AC timing from Table 55. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 41 shows the SPI timing in slave mode (external clock). SPICLK (Input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOV Note: The clock edge is selectable on SPI. Figure 41. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 42 shows the SPI timing in Master mode (internal clock). SPICLK (Output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOV Note: The clock edge is selectable on SPI. Figure 42. SPI AC Timing in Master Mode (Internal Clock) Diagram 17 TDM/SI This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the MPC8358E. 17.1 TDM/SI DC Electrical Characteristics Table 56. TDM/SI DC Electrical Characteristics Characteristic Symbol VOH VOL VIH Condition IOH = –2.0 mA IOL = 3.2 mA — Min 2.4 — 2.0 Max — 0.5 OVDD + 0.3 Unit V V V Table 56 provides the DC electrical characteristics for the device TDM/SI. Output high voltage Output low voltage Input high voltage M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 57 TDM/SI Table 56. TDM/SI DC Electrical Characteristics (continued) Characteristic Input low voltage Input current Symbol VIL IIN Condition — 0 V ≤ VIN ≤ OVDD Min –0.3 — Max 0.8 ±10 Unit V μA 17.2 TDM/SI AC Timing Specifications Table 57. TDM/SI AC Timing Specifications1 Characteristic Symbol2 tSEKHOV tSEKHOX tSEIVKH tSEIXKH Min 2 2 5 2 Max3 10 10 — — Unit ns ns ns ns Table 57 provides the TDM/SI input and output AC timing specifications. TDM/SI outputs—External clock delay TDM/SI outputs—External clock high impedance TDM/SI inputs—External clock input setup time TDM/SI inputs—External clock input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). 3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx]. See the MPC8360E Integrated Communications Processor Family Reference Manual for more details. Figure 43 provides the AC test load for the TDM/SI. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 43. TDM/SI AC Test Load Figure 44 represents the AC timing from Table 55. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 58 Freescale Semiconductor UTOPIA/POS Figure 44 shows the TDM/SI timing with external clock. TDM/SICLK (Input) tSEIVKH tSEIXKH Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) tSEKHOV tSEKHOX Note: The clock edge is selectable on TDM/SI Figure 44. TDM/SI AC Timing (External Clock) Diagram 18 UTOPIA/POS This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8358E. 18.1 UTOPIA/POS DC Electrical Characteristics Table 58. UTOPIA DC Electrical Characteristics Characteristic Symbol VOH VOL VIH VIL IIN Condition IOH = –8.0 mA IOL = 8.0 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±10 Unit V V V V μA Table 58 provides the DC electrical characteristics for the device UTOPIA. Output high voltage Output low voltage Input high voltage Input low voltage Input current 18.2 UTOPIA/POS AC Timing Specifications Table 59. UTOPIA AC Timing Specifications1 Characteristic Symbol2 tUIKHOV tUEKHOV tUIKHOX tUEKHOX tUIIVKH Min 0 1 0 1 6 Max 11.5 11.6 8.0 10.0 — Unit ns ns ns ns ns Notes — — — — — Table 59 provides the UTOPIA input and output AC timing specifications. UTOPIA outputs—Internal clock delay UTOPIA outputs—External clock delay UTOPIA outputs—Internal clock high impedance UTOPIA outputs—External clock high impedance UTOPIA inputs—Internal clock input setup time M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 59 UTOPIA/POS Table 59. UTOPIA AC Timing Specifications1 (continued) Characteristic UTOPIA inputs—External clock input setup time UTOPIA inputs—Internal clock input hold time UTOPIA inputs—External clock input hold time Symbol2 tUEIVKH tUIIXKH tUEIXKH Min 4.2 2.4 1 Max — — — Unit ns ns ns Notes — — — Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA outputs internal timing (UI) for the time tUTOPIA m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Figure 45 provides the AC test load for the UTOPIA. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 45. UTOPIA AC Test Load Figure 46 and Figure 47 represent the AC timing from Table 55. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 46 shows the UTOPIA timing with external clock. UtopiaCLK (Input) tUEIVKH Input Signals: UTOPIA tUEKHOV Output Signals: UTOPIA tUEKHOX tUEIXKH Figure 46. UTOPIA AC Timing (External Clock) Diagram M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 60 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Figure 47 shows the UTOPIA timing with internal clock. UtopiaCLK (Output) tUIIVKH Input Signals: UTOPIA tUIKHOV Output Signals: UTOPIA tUIKHOX tUIIXKH Figure 47. UTOPIA AC Timing (Internal Clock) Diagram 19 HDLC, BISYNC, Transparent, and Synchronous UART This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC, transparent, and synchronous UART protocols of the MPC8358E. 19.1 HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Table 60 provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and synchronous UART protocols. Table 60. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VIH VIL IIN Condition IOH = –2.0 mA IOL = 3.2 mA — — 0 V ≤ VIN ≤ OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±10 Unit V V V V μA M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 61 HDLC, BISYNC, Transparent, and Synchronous UART 19.2 HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications Table 61 and Table 62 provide the input and output AC timing specifications for HDLC, BISYNC, transparent, and synchronous UART protocols. Table 61. HDLC, BISYNC, and Transparent AC Timing Specifications1 Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Inputs—External clock input hold time Symbol2 tHIKHOV tHEKHOV tHIKHOX tHEKHOX tHIIVKH tHEIVKH tHIIXKH tHEIXKH Min 0 1 -0.5 1 8.5 4 1.4 1 Max 11.2 10.8 5.5 8 — — — — Unit ns ns ns ns ns ns ns ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 62. Synchronous UART AC Timing Specifications1 Characteristic Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Inputs—External clock input hold time Symbol2 tUAIKHOV tUAEKHOV tUAIKHOX tUAEKHOX tUAIIVKH tUAEIVKH tUAIIXKH tUAEIXKH Min 0 1 0 1 6 8 1 1 Max 11.3 14 11 14 — — — — Unit ns ns ns ns ns ns ns ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial m emory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 62 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Figure 48 provides the AC test load. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 48. AC Test Load 19.3 AC Test Load Figure 49 and Figure 50 represent the AC timing from Table 61 and Table 62. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 49 shows the timing with external clock. Serial CLK (Input) tHEIVKH Input Signals: (See Note) tHEKHOV Output Signals: (See Note) Note: The clock edge is selectable. tHEKHOX tHEIXKH Figure 49. AC Timing (External Clock) Diagram Figure 50 shows the timing with internal clock. Serial CLK (Output) tHIIVKH Input Signals: (See Note) tHIKHOV Output Signals: (See Note) tHIKHOX Note: The clock edge is selectable. tHIIXKH Figure 50. AC Timing (Internal Clock) Diagram M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 63 USB 20 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8358E. 20.1 USB DC Electrical Characteristics Table 63. USB DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OV DD – 0.4 — — Max OVDD + 0.3 0.8 — 0.2 ±10 Unit V V V V μA Table 63 provides the DC electrical characteristics for the USB interface. High-level input voltage Low-level input voltage High-level output voltage, IOH = –100 μA Low-level output voltage, IOL = 100 μA Input current 20.2 USB AC Electrical Specifications Table 64. USB General Timing Parameters Parameter Symbol1 tUSCK tUSCK tUSTSPN tUSRSPND tUSRPND Min 20.83 166.67 — — — Max — — 5 10 100 Unit ns ns ns ns ns Notes Full speed 48 MHz Low speed 6 MHz — Full speed transitions Low speed transitions Table 64 describes the general timing parameters of the USB interface of the device. USB clock cycle time USB clock cycle time Skew between TXP and TXN Skew among RXP, RXN, and RXD Skew among RXP, RXN, and RXD Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(state)(signal) for receive signals and t(first two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND symbolizes USB timing (US) for the USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, tUSTSPN symbolizes USB timing (US) for the USB transmit signals skew (TS) between TXP and TXN (PN). 2.Skew measurements are done at OVDD/2 of the rising or falling edge of the signals. Figure 51 provide the AC test load for the USB. Output Z0 = 50 Ω RL = 5 0 Ω OVDD/2 Figure 51. USB AC Test Load M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 64 Freescale Semiconductor Package and Pin Listings 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8358E is available in a plastic ball grid array (PBGA), see Section 21.1, “Package Parameters for the PBGA Package,” and Section 21.2, “Mechanical Dimensions of the PBGA Package,” for information on the package. 21.1 Package Parameters for the PBGA Package The package parameters for rev 2.0 silicon are as provided in the following list. The package type is 29 mm x 29 mm, 668 plastic ball grid array (PBGA). Package outline 29 mm x 29 mm Interconnects 668 Pitch 1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) Ball diameter (typical) 0.64 mm M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 65 Package and Pin Listings 21.2 Mechanical Dimensions of the PBGA Package Figure 52 depicts the mechanical dimensions and bottom surface nomenclature of the 668-PBGA package. Figure 52. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 66 Freescale Semiconductor Package and Pin Listings 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement must exclude any effect of mark on top surface of package. 6. Distance from the seating plane to the encapsulant material. 21.3 Pinout Listings Refer to AN3097, “MPC8360/MPC8358E PowerQUICC Design Checklist,” for proper pin termination and usage. Table 65 shows the pin list of the MPC8358E PBGA package. Table 65. MPC8358E PBGA Pinout Listing Signal Package Pin Number DDR SDRAM Memory Controller Interface MEMC_MDQ[0:63] AD20, AG24, AF24, AH24, AF23, AE22, AH26, AD21, AH25, AD22, AF27, AB24, AG25, AC22, AE25, AC24, AD25, AB25, AC25, AG28, AD26, AE23, AG26, AC26, AD27, V25, AA28, AA25, Y26, W27, U24, W24, E28, H24, E26, D25, G27, H25, G26, F26, F27, F25, D26, F24, G25, E27, D27, C28, C27, F22, B26, F21, B28, E22, D24, C24, A25, E20, F20, D20, A23, C21, C23, E19 N26, N24, J26, H28, N28, P24, L26, K24 AG23, AD23, AE26, V28, G28, D28, D23, B24, U27 AH23, AH27, AF28, T28, H26, E25, B25, A24, R28 V26, W28, Y28 L25, M25, M24, K28, P28, T24, M27, R25, P25, L28, U26, M28, L27, K27, H27 AE21, AC19, E23, B23 R27 W25 R24 T26, U28, J25, F28 AD24, AE28 AG22, AG27, A26, C26, P26, E21 AF22, AF26, A27, B27, N27, D22 F19, AA27 PCI PCI_INTA/ PF[5] PCI_RESET_OUT/ PF[6] PCI_AD[0:31]/ PG[0:31] PCI_C_BE[0:3]/ PF[7:10] R3 P6 AB5, AC5, AG1, AA5, AF2, AD4, Y6, AF1, AE2, AC4, AD3, AE1, Y4, AC3, AD2, AD1, AB2, Y3, AA1, Y1, W1, V6, W3, V4, T5, W2, V5, V1, U4, V2, U2, T2 Y5, AC2, Y2, U5 I/O I/O I/O LVDD2 LVDD2 LVDD2 2 — — I/O GVDD — Pin Type Power Supply Notes MEMC_MECC[0:7] MEMC_MDM[0:8] MEMC_MDQS[0:8] MEMC_MBA[0:2] MEMC_MA[0:14] MEMC_MODT[0:3] MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS[0:3] MEMC_MCKE[0:1] MEMC_MCK[0:5] MEMC_MCK[0:5] MDIC[0:1] I/O O I/O O O — O O O O O O O I/O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD — — — — — 6 — — — — — — — 11 I/O OVDD — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 67 Package and Pin Listings Table 65. MPC8358E PBGA Pinout Listing (continued) Signal PCI_PAR/ PF[11] PCI_FRAME/ PF[12] PCI_TRDY / PF[13] PCI_IRDY/ PF[14] PCI_STOP / PF[15] PCI_DEVSEL/ PF[16] PCI_IDSEL/ PF[17] PCI_SERR/ PF[18] PCI_PERR/ PF[19] PCI_REQ[0:2]/ PF[20:22] PCI_GNT[0:2]/ PF[23:25] PCI_MODE M66EN/ CE_PF[4] AA4 W4 W5 AB3 AB1 AA2 U6 AC1 W6 R2, T4, U1 T3, R5, T1 AE5 AH3 Local Bus Controller Interface LAD[0:31] AC11, AE10, AD10, AD11, AE11, AG11, AH11, AH12, AG12, AF12, AD12, AE12, AC12, AH13, AG13, AF13, AE13, AH14, AD13, AG14, AF14, AH15, AE14, AG15, AC13, AD14, AC14, AH16, AC15, AG16, AE15, AF16 AD15, AG17, AC16, AF17 AH17, AD16, AH18, AG18, AE17 AD18, AH20, AG20, AE19, AC18, AH21 AG21, AH22, AC20, AD19 AF18 AF10 AC17 I/O OVDD — Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD LVDD2 LVDD2 OVDD OVDD Notes — 5 5 5 5 5 — 5 5 — — — — LDP[0:3] LA[27:31] LCS [0:5] LWE[0:3] LBCTL LALE LGPL0/ LSDA10/ cfg_reset_source0 LGPL1/ LSDWE/ cfg_reset_source1 I/O O O O O O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD — — — — — — — AD17 I/O OVDD — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 68 Freescale Semiconductor Package and Pin Listings Table 65. MPC8358E PBGA Pinout Listing (continued) Signal LGPL2/ LSDRAS / LOE LGPL3/ LSDCAS/ cfg_reset_source2 LGPL4/ LGTA/ LUPWAIT/ LPBSE LGPL5/ cfg_clkin_div LCKE LCLK[0] LCLK[1]/ LCS[6] LCLK[2]/ LCS[7] LSYNC_OUT LSYNC_IN AH19 Package Pin Number Pin Type O Power Supply OVDD Notes — AE18 I/O OVDD — AG19 I/O OVDD — AF19 AD8 AC9 AG6 AE7 AG4 AC8 Programmable Interrupt Controller I/O O O O O O I OVDD OVDD OVDD OVDD OVDD OVDD OVDD — — — — — — — MCP_OUT IRQ0/ MCP_IN IRQ[1:2] IRQ[3]/ CORE_SRESET IRQ[4:5] IRQ[6:7] AG3 AH4 AG5, AH5 AD7 AC7, AD6 AC6, AC10 DUART O I I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD 2 — — — — — UART1_SOUT UART1_SIN UART1_CTS UART1_RTS AE3 AE4 AG2 AA6 I 2C O I/O I/O O Interface I/O I/O I/O I/O QUICC Engine OVDD OVDD OVDD OVDD — — — — IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL AB6 AD5 AF3 AH2 OVDD OVDD OVDD OVDD 2 2 2 2 CE_PA[0] F6 I/O LVDD0 — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 69 Package and Pin Listings Table 65. MPC8358E PBGA Pinout Listing (continued) Signal CE_PA[1:2] CE_PA[3:7] CE_PA[8] CE_PA[9:12] CE_PA[13:14] CE_PA[15] CE_PA[16] CE_PA[17:21] CE_PA[22] CE_PA[23:26] CE_PA[27:28] CE_PA[29] CE_PA[30] CE_PA[31] CE_PB[0:27] A22, C20 C3, D3, C2, D2, B1 F18 E3, C1, B2, D1 B21, D19 E4 E18 M2, N5, N3, N4, N2 F17 N1, P1, P2, P4 A21, E17 P5 B20 M4 D18, C18, A20, B19, F16, E16, B18, A19, C17, D16, E15, A18, F15, B17, A17, D15, B16, A16, C15, B15, A15, E14, F14, D14, C14, B14, A14, E13 F13, D13 N6, M1 C13, B13, A13 R1 F4, E2 D12, E12, F12, B12, A12, A11, B11, K5, K6, J1, J2, J3, H1, J4, H6, J5, M5, L1, M3, F5, B22 H2, H3, G6, G1, H4, H5, G2, G3, F1, J6, F2, G4, E1, G5, B3, A3, D4, C4, A2, E5, B4, F8, A4, D5, C5, B5, E6, E8 D8, A7, A5, E7, D6, F9, B6, A6, D7, C7, B7, E9, C8, E11, C11, F11, A10, B10, C10, E10, D10, A9, B9, C9, D9, F10, A8, B8, M6, K1, L3, L2 L6, K2, L5, K4 Clocks PCI_CLK[0]/ PF[26] PCI_CLK[1:2]/ PF[27:28] CLKIN PCI_SYNC_IN PCI_SYNC_OUT/ PF[29] R6 U3, T6 AH6 AF7 AF6 JTAG TCK AD9 I OVDD — I/O I/O I I I/O LVDD2 OVDD OVDD OVDD OVDD — — — — 3 Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply OVDD LVDD0 OVDD LVDD0 OVDD LVDD0 OVDD LVDD1 OVDD LVDD1 OVDD LVDD1 OVDD LVDD1 OVDD Notes — — — — — — — — — — — — — — — CE_PC[0:1] CE_PC[2:3] CE_PC[4:6] CE_PC[7] CE_PC[8:9] CE_PC[10:30] CE_PD[0:27] CE_PE[0:31] I/O I/O I/O I/O I/O I/O I/O I/O OVDD LVDD1 OVDD LVDD2 LVDD0 OVDD OVDD OVDD — — — — — — — — CE_PF[0:3] I/O OVDD — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 70 Freescale Semiconductor Package and Pin Listings Table 65. MPC8358E PBGA Pinout Listing (continued) Signal TDI TDO TMS TRST AE8 AG7 AH7 AG8 Test TEST TEST_SEL AF9 AE27 PMC QUIESCE AF4 System Control PORESET HRESET SRESET AE9 AG9 AH10 Thermal Management THERM0 THERM1 K25 AA26 Power and Ground Signals AVDD1 AF8 Power for LBIU DLL (1.2 V) Power for CE PLL (1.2 V) Power for e300 PLL (1.2 V) Power for system PLL (1.2 V) — AVDD1 — I I GVDD GVDD — — I I/O I/O OVDD OVDD OVDD — 1 2 O OVDD — I I OVDD GVDD 7 9 Package Pin Number Pin Type I O I I Power Supply OVDD OVDD OVDD OVDD Notes 4 3 4 4 AVDD2 AH8 AVDD2 — AVDD5 AB26 AVDD5 — AVDD6 AH9 AVDD6 — GND C16, D11, D21, E24, F7, J10, J12, J15, J16, J17, J28, K11, K13, K14, K17, K18, L4, L9, L11, L12, L13, L14, L15, L16, L17, L18, L19, L24, M10, M11, M14, M15, M18, M19, N11, N18, N25, P9, P11, P18, P19, R9, R11, R14, R15, R18, R19, R26, T10, T11, T14, T15, T18, T25, U10, U11, U18, V9, V11, V14, V15, V18, V24, V27, W18, W19, Y11, Y14, Y18, Y19, Y25, Y27, AB4, AB27, AC27, AE20, AE24, AF5, AF15, AG10 — — M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 71 Package and Pin Listings Table 65. MPC8358E PBGA Pinout Listing (continued) Signal GVDD Package Pin Number C19, C22, C25, G24, J18, J19, J20, J24, K19, K20, K26, L20, M20, M26, N19, N20, P20, P27, R20, T19, T20, T27, U19, U20, U25, V19, V20, W20, W26, Y20, AA24, AB28, AC21, AC28, AD28, AF21, AF25 Pin Type Power for DDR DRAM I/O Voltage (2.5 V or 1.8 V) — — — Power for Core (1.2 V) Power Supply GVDD Notes — LVDD0 LVDD1 LVDD2 VDD F3, J9 P3, P10 R4, R10 M12, M13, M16, M17, N10, N12, N13, N14, N15, N16, N17, P12, P13, P14, P15, P16, P17, R12, R13, R16, R17, T12, T13, T16, T17, U12, U13, U14, U15, U16, U17, V12, V13, V16, V17, W11, W12, W13, W15, W16, W17, Y16, Y17 C6, C12, D17, J11, J13, J14, K3, K9, K10, K12, K15, K16, L10, M9, N9, T9, U9, V3, V10, W9, W10, W14, Y9, Y10, Y12, Y13, Y15, AA3, AE6, AE16, AF11, AF20 LVDD0 LVDD1 LVDD2 VDD — 10 10 — OVDD PCI, 10/100 Ethernet, and other Standard (3.3 V) I OVDD — MVREF1 J27 DDR Referenc e Voltage DDR Referenc e Voltage — MVREF2 Y24 I — No Connect NC F23, G23, H23, J23, K23, L23, M23, N23, P23, R23, T23, U23, V23, W23, Y23, AA23, AB23, AC23 — — — Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD. 2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD. 3. This output is actively driven during reset rather than being three-stated during reset. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5.This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation. 6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance. 7. This pin must always be tied to GND. 8. This pin must always be left not connected. 9. This pin must always be tied to GVDD. 10. Refers to MPC8360E PowerQUICC II™ Pro Integrated Communications Processor Reference Manual section on “RGMII Pins” for information about the two UCC2 Ethernet interface options. 11. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω resistor for DDR2. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 72 Freescale Semiconductor Clocking 22 Clocking Figure 53 shows the internal distribution of clocks within the MPC8358E. MPC8358E e300 Core Core PLL core_clk csb_clk ce_clk to QUICC Engine Block DDRC /2 ddr1_clk QUICC Engine PLL Clock Unit lb_clk /n LBIU DLL csb_clk to Rest of the Device CFG_CLKIN_DIV CLKIN PCI Clock Divider PCI_CLK_OUT[0:2] PCI_CLK/ PCI_SYNC_IN LCLK[0:2] Local Bus LSYNC_OUT Memory Device LSYNC_IN MEMC1_MCK[0:5] DDRC Memory MEMC1_MCK[0:5] Device System PLL PCI_SYNC_OUT Figure 53. MPC8358E Clock Subsystem The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKDRV]. When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected (RCWH[PCICKDRV] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 73 Clocking input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn, respectively. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to GND. When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is disabled (RCWH[PCICKDRV] = 0), clock distribution and balancing done externally on the board. Therefore, PCI_SYNC_IN is the primary input clock. As shown in Figure 53, the primary clock input (frequency) is multiplied by the QUICC Engine block phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent system bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the local bus interface unit and DDR2 memory controller (lb_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent mode, CFG_CLKIN_DIV must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the PCI_CLK frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for more information on the clock subsystem. The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation: ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF) The internal ddr1_clk frequency is determined by the following equation: ddr1_clk = csb_clk × (1 + RCWL[DDR1CM]) Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the DDRC1 clock divider (÷2) to create the differential DDRC1 memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk. The internal lb_clk frequency is determined by the following equation: lb_clk = csb_clk × (1 + RCWL[LBCM]) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 74 Freescale Semiconductor Clocking Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV]. In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 66 specifies which units have a configurable clock frequency. Table 66. Configurable Clock Units Unit Security core PCI and DMA complex 1 Default Frequency Options Off, csb_clk1, csb_clk/2, csb_clk/3 Off, csb_clk csb_clk/3 csb_clk With limitation, only for slow csb_clk rates, up to 166 MHz. Table 67 provides the operating frequencies for the PBGA package under recommended operating conditions (see Table 2). All frequency combinations shown in the table below may not be available. Maximum operating frequencies depend on the part ordered, see Section 25.1, “Part Numbers Fully Addressed by this Document,” for part ordering details and contact your Freescale sales representative or authorized distributor for more information. Table 67. Operating Frequencies for the PBGA Package Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) QUICC Engine frequency (ce_clk) DDR and DDR2 memory bus frequency (MCLK)2 Local bus frequency (LCLKn)3 PCI input frequency (CLKIN or PCI_CLK) Security core maximum internal operating frequency 1 400 MHz 266–400 133–266 266–400 100–133 16.67–133 25–66.67 133 Unit MHz MHz MHz MHz MHz MHz MHz The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBCM]). M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 75 Clocking 22.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. Table 68 shows the multiplication factor encodings for the system PLL. Table 68. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 System PLL Multiplication Factor × 16 Reserved ×2 ×3 ×4 ×5 ×6 ×7 ×8 ×9 × 10 × 11 × 12 × 13 × 14 × 15 The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 69. Table 69. System PLL VCO Divider RCWL[SVCOD] 00 01 10 11 VCO Divider 4 8 2 Reserved NOTE The VCO divider must be set properly so that the system VCO frequency is in the range of 600–1400 MHz. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 76 Freescale Semiconductor Clocking The system VCO frequency is derived from the following equations: • csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF • System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM] are cleared) OR • System VCO frequency = 2 × csb_clk × VCO divider (if either RCWL[DDRCM] or RCWL[LBCM] are set). As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 70 shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. Table 70. CSB Frequency Options Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at Reset1 SPMF csb_clk: Input Clock Ratio2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High High High High 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 2:1 3:1 4:1 5:1 100 133 166 100 116 133 150 166 183 200 216 233 250 266 133 200 266 333 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333 133 200 266 333 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 77 Clocking Table 70. CSB Frequency Options (continued) Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at Reset1 SPMF csb_clk: Input Clock Ratio2 16.67 25 33.33 66.67 csb_clk Frequency (MHz) High High High High High High High High High High High 1 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 200 233 CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. 22.2 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 71 shows the encodings for RCWL[COREPLL]. COREPLL values not listed in Table 71 should be considered reserved. Table 71. e300 Core PLL Configuration RCWL[COREPLL] 0–1 nn 2–5 0000 6 n core_clk:csb_clk Ratio VCO divider PLL bypassed PLL bypassed (PLL off, csb_clk (PLL off, csb_clk clocks core directly) clocks core directly) 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 00 01 10 11 00 01 10 0001 0001 0001 0001 0001 0001 0001 0 0 0 0 1 1 1 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 78 Freescale Semiconductor Clocking Table 71. e300 Core PLL Configuration (continued) RCWL[COREPLL] 0–1 11 00 01 10 11 00 01 10 11 00 01 10 11 2–5 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 6 1 0 0 0 0 1 1 1 1 0 0 0 0 core_clk:csb_clk Ratio 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 VCO divider ÷8 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 ÷2 ÷4 ÷8 ÷8 NOTE Core VCO frequency = Core frequency × VCO divider. The VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 800–1800 MHz. Having a core frequency below the CSB frequency is not a possible option because the core frequency must be equal to or greater than the CSB frequency. 22.3 QUICC Engine Block PLL Configuration The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters. Table 72 shows the multiplication factor encodings for the QUICC Engine block PLL. Table 72. QUICC Engine Block PLL Multiplication Factors QUICC Engine PLL RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF]) 00000 00001 00010 00011 00100 0 0 0 0 0 × 16 Reserved ×2 ×3 ×4 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 79 Clocking Table 72. QUICC Engine Block PLL Multiplication Factors (continued) QUICC Engine PLL RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF]) 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00011 00101 00111 01001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ×5 ×6 ×7 ×8 ×9 × 10 × 11 × 12 × 13 × 14 × 15 × 16 × 17 × 18 × 19 × 20 × 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 30 × 31 × 1.5 × 2.5 × 3.5 × 4.5 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 80 Freescale Semiconductor Clocking Table 72. QUICC Engine Block PLL Multiplication Factors (continued) QUICC Engine PLL RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF]) 01011 01101 01111 10001 10011 10101 10111 11001 11011 11101 1 1 1 1 1 1 1 1 1 1 × 5.5 × 6.5 × 7.5 × 8.5 × 9.5 × 10.5 × 11.5 × 12.5 × 13.5 × 14.5 Note: 1. Reserved modes are not listed. The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in Table 73. Table 73. QUICC Engine Block PLL VCO Divider RCWL[CEVCOD] 00 01 10 11 VCO Divider 4 8 2 Reserved NOTE The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine block VCO frequency is in the range of 600–1400 MHz. The QUICC Engine block frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC Engine block frequencies should be selected according to the performance requirements. The QUICC Engine block VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF) QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF) M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 81 Clocking 22.4 Suggested PLL Configurations To simplify the PLL configurations, the device might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine block PLL. The clock domains are independent, and each of their PLLs are configured separately. Both of the domains has one common input clock. Table 74 shows suggested PLL configurations for 33 and 66 MHz input clocks and illustrates each of the clock domains separately. Any combination of clock domains setting with same input clock are valid. Refer to Section 22, “Clocking,” for the appropriate operating frequencies for your device. Table 74. Suggested PLL Configurations Conf No.1 CORE PLL Input CSB Freq Core Freq Clock Freq (MHz) (MHz) (MHz) QUICC Engine Freq (MHz) 400 533 667 (MHz) (MHz) (MHz) SPMF CEPMF CEPDF 33 MHz CLKIN/PCI_SYNC_IN Options s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 c1 c2 c3 c4 0100 0100 0101 0101 0110 0110 0111 0111 0111 1000 1000 1000 1001 1001 1001 1010 1010 1010 æ æ æ æ 0000100 0000101 0000100 0000101 0000100 0000110 0000011 0000100 0000101 0000011 0000100 0000101 0000010 0000011 0000100 0000010 0000011 0000100 æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ 01001 01100 01110 01111 æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ æ 0 0 0 0 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 133 133 166 166 200 200 233 233 233 266 266 266 300 300 300 333 333 333 — — — — 266 333 333 416 400 600 350 466 583 400 533 667 300 450 600 333 500 667 — — — — — — — — — — — — — — — — — — — — — — 300 400 466 500 ∞ ∞ ∞ — ∞ — ∞ — — ∞ — — ∞ — — ∞ — — ∞ ∞ — — ∞ ∞ ∞ ∞ ∞ — ∞ ∞ — ∞ ∞ — ∞ ∞ — ∞ ∞ — ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 82 Freescale Semiconductor Clocking Table 74. Suggested PLL Configurations (continued) Conf No.1 c5 c6 CORE PLL æ æ Input CSB Freq Core Freq Clock Freq (MHz) (MHz) (MHz) 33 33 — — — — QUICC Engine Freq (MHz) 533 566 400 533 667 (MHz) (MHz) (MHz) — — ∞ — ∞ ∞ SPMF CEPMF CEPDF æ æ 10000 10001 0 0 66 MHz CLKIN/PCI_SYNC_IN Options s1h s2h s3h s4h s5h s6h s7h s8h s9h c1h c2h c3h c4h c5h 1 0011 0011 0011 0100 0100 0100 0101 0101 0101 æ æ æ æ æ 0000110 0000101 0000110 0000011 0000100 0000101 0000010 0000011 0000100 æ æ æ æ æ æ æ æ æ æ æ æ æ æ 00101 00110 00111 01000 01001 æ æ æ æ æ æ æ æ æ 0 0 0 0 0 66 66 66 66 66 66 66 66 66 66 66 66 66 66 200 200 200 266 266 266 333 333 333 — — — — — 400 500 600 400 533 667 333 500 667 — — — — — — — — — — — — — — 333 400 466 533 600 ∞ — — ∞ — — ∞ — — ∞ ∞ — — — ∞ ∞ — ∞ ∞ — ∞ ∞ — ∞ ∞ ∞ ∞ — ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The postfix “h” stands for “high input clock.’”The index is a serial number. The following steps describe how to use Table 74. See Example 1. 1. Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz. 2. Select a suitable CSB and core clock rates from Table 74. Copy the SPMF and CORE PLL configuration bits. 3. Select a suitable QUICC Engine block clock rate from Table 74. Copy the CEPMF and CEPDF configuration bits. 4. Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively. Example 1. Sample Table Use QUICC Engine Freq (MHz) 300 SPMF CORE PLL 0000011 CEPMF CEPDF Input Clock (MHz) 33 CSB Freq (MHz) 266 Core Freq (MHz) 400 400 (MHz) ∞ 1000 01001 0 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 83 Thermal • To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and QUICC Engine clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. ‘s10’ and ‘c1’ are selected from Table 74. SPMF is 1000, CORPLL is 0000011, CEPMF is 01001, and CEPDF is 0. 23 Thermal This section describes the thermal specifications of the MPC8358E. 23.1 Thermal Characteristics Table 75. Package Thermal Characteristics for the PBGA Package Characteristic Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC ψ JT Value 20 14 15 11 6 4 4 Unit °C/W °C/W °C/W •C/W C/W •C/W C/W •C/W C/W •C/W C/W Notes 1, 2 1, 2, 3 1, 3 1, 3 4 5 6 Table 75 provides the package thermal characteristics for the 668 29 mm x 29 mm PBGA package. Junction-to-ambient Natural Convection on single layer board (1s) Junction-to-ambient Natural Convection on four layer board (2s2p) Junction-to-ambient (@1 m/s) on single layer board (1s) Junction-to-ambient (@ 1 m/s) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal Junction-to-Package Natural Convection on Top Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 and JEDEC JESD51-9 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM). 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 23.2 Thermal Management Information For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 5 for typical power dissipations values. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 84 Freescale Semiconductor Thermal 23.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where: TJ = junction temperature (°C) TA = ambient temperature for the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single-layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 23.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package will be approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (°C) TB = board temperature at the package perimeter (°C) RθJA = junction to board thermal resistance (°C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 85 Thermal 23.2.3 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TJ = junction temperature (°C) TT = thermocouple temperature on top of package (°C) ΨJT = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 23.2.4 Heat Sinks and Junction-to-Ambient Thermal Resistance In some application environments, a heat sink will be required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (°C/W) RθJC = junction-to-case thermal resistance (°C/W) RθCA = case-to-ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the airflow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, airflow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 86 Freescale Semiconductor Thermal Table 76 shows heat sinks and junction-to-ambient thermal resistance for PBGA package. Table 76. Heat Sinks and Junction-to-Ambient Thermal Resistance of PBGA Package 29 × 29 mm PBGA Heat Sink Assuming Thermal Grease Air Flow Thermal Resistance AAVID 30 AAVID 30 AAVID 30 × 30 × 9.4 mm Pin Fin × 30 × 9.4 mm Pin Fin × 30 × 9.4 mm Pin Fin Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s 12.6 8.2 7.0 10.5 6.6 6.1 9.0 5.6 5.1 9.0 5.7 5.1 AAVID 31 × 35 × 23 mm Pin Fin AAVID 31 × 35 × 23 mm Pin Fin AAVID 31 × 35 × 23 mm Pin Fin Wakefield, 53 × 53 Wakefield, 53 × 53 Wakefield, 53 × 53 × 25 mm Pin Fin × 25 mm Pin Fin × 25 mm Pin Fin MEI, 75 × 85 × 12 no adjacent board, extrusion MEI, 75 × 85 × 12 no adjacent board, extrusion MEI, 75 × 85 × 12 no adjacent board, extrusion Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com 603-224-9988 408-749-7601 818-842-7277 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 87 Thermal Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-millennium.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 408-436-8770 800-522-6752 603-635-5102 Interface material vendors include the following: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 781-935-4850 800-248-2481 888-642-7674 800-347-4572 23.3 Heat Sink Attachment When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is 10 lb force (4.5 kg force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 88 Freescale Semiconductor System Design Information 23.3.1 Experimental Determination of the Junction Temperature with a Heat Sink When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. TJ = TC + (RθJC × PD) where: TJ = junction temperature (°C) TC = case temperature of the package (°C) RθJC = junction to case thermal resistance (°C/W) PD = power dissipation (W) 24 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8358E. Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097). 24.1 System Clocking The device includes two PLLs, as follows. • The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 22.1, “System PLL Configuration.” • The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 22.2, “Core PLL Configuration.” 24.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 54, one to each of the five AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 89 System Design Information This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 54 shows the PLL power supply filter circuit. 10 Ω V DD 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND AVDDn Figure 54. PLL Power Supply Filter Circuit 24.3 Decoupling Recommendations Due to large address and data buses as well as high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON). 24.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the device. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 90 Freescale Semiconductor System Design Information 24.5 Output Buffer DC Impedance The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 55). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. OVDD RN SW2 Data Pad SW1 RP OGND Figure 55. Driver Impedance Measurement The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = 1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 – 1). The drive current is then Isource = V1/Rsource. Table 77 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105°C. Table 77. Impedance Characteristics Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target Impedance PCI DDR DRAM Symbol Unit RN RP 25 Target 25 Target 20 Target 20 Target Z0 Z0 W W M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 91 Ordering Information Table 77. Impedance Characteristics (continued) Local Bus, Ethernet, DUART, Control, Configuration, Power Management NA Impedance PCI DDR DRAM Symbol Unit Differential NA NA ZDIFF W Note: Nominal supply voltages. See Table 1, TJ = 105° C. 24.6 Configuration Pin Muxing The device provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 24.7 Pull-Up Resistor Requirements The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins including I2C pins, Ethernet Management MDIO pin, and EPIC interrupt pins. For more information on required pull-up resistors and the connections required for the JTAG interface, see MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097). 25 Ordering Information 25.1 Part Numbers Fully Addressed by this Document Table 78 provides the Freescale part numbering nomenclature for the MPC8358E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 92 Freescale Semiconductor Ordering Information includes an application modifier, which may specify special application conditions. Each part number also contains a revision code that refers to the die mask revision number. Table 78. Part Numbering Nomenclature1 MPC nnnn e t pp Package2 aa Processor Frequency3 a Platform Frequency a QUICC Engine Frequency A Die Revision Product Part Encryption Temperature Code Identifier Acceleration Range MPC 8358 Blank = Not included E = included Blank = ZQ = PBGA e300 core speed D = 266 MHz D = 266 MHz A = revision 0 ° C TA to G = 400 MHz 2.1 silicon VR = PBGA AD = 266 MHz AG = 400 MHz (no lead) 105 ° C TJ C= –40° C TA to 105° C TJ 1 Not all processor, platform, and QUICC Engine block frequency combinations are supported. For available frequency combinations, contact your local Freescale sales office or authorized distributor. 2 See Section 21, “Package and Pin Listings,” for more information on available package types. 3 Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by part number specifications may support other maximum core frequencies. Table 79 shows the SVR settings by device and package type. Table 79. SVR Settings Device MPC8358E MPC8358 Package PBGA PBGA SVR (Rev. 2.1) 0x804E_0021 0x804F_0021 M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 Freescale Semiconductor 93 Document Revision History 26 Document Revision History Table 80 provides a revision history for this hardware specification. Table 80. Revision History Rev. Number 3 Date 01/2011 Substantive Change(s) • Updated references to the LCRR register throughout • Removed references to DDR DLL mode in Section 6.2.2, “DDR and DDR2 SDRAM Output AC Timing Specifications.” • Changed “Junction-to-Case” to “Junction-to-Ambient” in Section 23.2.4, “Heat Sinks and Junction-to-Ambient Thermal Resistance,” and Table 76, “Heat Sinks and Junction-to-Ambient Thermal Resistance of PBGA Package,” titles. • • • • • • • • • • • • • • • • • • • 1 Changed references to RCWH[PCICKEN] to RCWH[PCICKDRV]. In Table 2, added extended temperature characteristics. Added Figure 5, “DDR Input Timing Diagram.” In Figure 52, “Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package,” removed watermark. In Table 4, “MPC8358E PBGA Core Power Dissipation1,” added row for 400/266/400 part offering. Updated the title of Table 18,”DDR SDRAM Input AC Timing Specifications.” In Table 19, “DDR and DDR2 SDRAM Input AC Timing Specifications Mode,” changed table subtitle. In Table 26–Table 29, and Table 32—Table 33, changed the rise and fall time specifications to reference 20–80% and 80–20% of the voltage supply, respectively. In Table 37, “IEEE 1588 Timer AC Specifications,” changed first parameter to “Timer clock frequency.” In Table 44, “I2C AC Electrical Specifications,” changed units to “ns” for tI2DVKH. In Table 65 “MPC8358E PBGA Pinout Listing, added note 7: “This pin must always be tied to GND” to the TEST pin. In Table 67, “Operating Frequencies for the PBGA Package,” and Table 78, “Part Numbering Nomenclature,” updated for 400 MHz QE part offering In Section 4, “Clock Input Timing,” added note regarding rise/fall time on QUICC Engine block input pins. Added Section 4.3, “Gigabit Reference Clock Input Timing.” Updated Section 8.1.1, “10/100/1000 Ethernet DC Electrical Characteristics.” In Section 21.3, “Pinout Listings,” added sentence stating “Refer to AN3097, ‘MPC8360/MPC8358E PowerQUICC Design Checklist,’ for proper pin termination and usage.” In Section 22, “Clocking,” removed statement: “The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.” In Section 22.1, “System PLL Configuration,” updated the system VCO frequency conditions. In Table 78, added extended temperature characteristics. 2 03/2010 12/2007 Initial release. M PC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 94 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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Freescale, the Freescale logo, and PowerQUICC are trademarks of Freescale Semiconductor, Inc. Reg. U.S. Pat. & Tm. Off. QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2011 Freescale Semiconductor, Inc. Document Number: MPC8358EEC Rev. 3 01/2011