MPC8360TZUALDHA

Freescale Semiconductor Technical Data Document Number: MPC8360EEC Rev. 2, 12/2007 MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications This document provides an overview of the MPC8360E/58E PowerQUICC™ II Pro processor revision 2.x TBGA features, including a block diagram showing the major functional components. This device is a cost-effective, highly integrated communications processor that addresses the needs of the networking, wireless infrastructure and telecommunications markets. Target applications include next generation DSLAMs, network interface cards for 3G basestations (Node Bs), routers, media gateways and high end IADs. The device extends current PowerQUICC II Pro offerings, adding higher CPU performance, additional functionality, faster interfaces and robust interworking between protocols while addressing the requirements related to time-to-market, price, power, and package size. This device can be used for the control plane along with data plane functionality. For functional characteristics of the processor, refer to the MPC8360E Integrated Communications Processor Family Reference Manual, Rev. 2. To locate any published errata or updates for this document, contact your Freescale sales office. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UCC Ethernet Controller: Three-Speed Ethernet, MII Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 HDLC, BISYNC, Transparent, and Synchronous UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . 68 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 System Design Information . . . . . . . . . . . . . . . . . . . 104 Document Revision History. . . . . . . . . . . . . . . . . . . 108 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 108 © Freescale Semiconductor, Inc., 2007. All rights reserved. Overview 1 Overview This section describes a high-level overview including features and general operation of the MPC8360E/58E PowerQUICC™ II Pro processor. A major component of this device is the e300 core which includes 32 Kbytes of instruction and data cache and is fully compatible with the PowerPC™ 603e instruction set. The new QUICC Engine™ module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module's enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. e300 Core 32KB I-Cache 32KB D-Cache Security Engine System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration Multi-User RAM DUART Serial DMA & 2 Virtual DMAs Dual I2C 4 Channel DMA Interrupt Controller UCC1 UCC2 UCC3 UCC4 UCC5 UCC6 UCC7 UCC8 MCC SPI1 SPI2 USB Protection & Configuration System Reset Clock Synthesizer DDRC1 DDRC2 PCI Local Classic G2 MMUs FPU JTAG/COP Power Management Timers QUICC Engine Module Baud Rate Generators Parallel I/O Accelerators Dual 32-bit RISC CP Time Slot Assigner Serial Interface 8 TDM Ports 8 MII/ RMII 2 GMII/ RGMII/TBI/RTBI 2 UTOPIA/POS (124 MPHY) Figure 1. MPC8360E Block Diagram MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 2 Freescale Semiconductor Overview e300 Core 32KB I-Cache 32KB D-Cache Security Engine System Interface Unit (SIU) Memory Controllers GPCM/UPM/SDRAM 32/64 DDR Interface Unit PCI Bridge Local Bus Bus Arbitration DDRC PCI Local Classic G2 MMUs FPU JTAG/COP Power Management Timers QUICC Engine Module Baud Rate Generators Parallel I/O UCC1 UCC2 UCC3 UCC4 UCC5 UCC8 SPI1 SPI2 USB Accelerators Multi-User RAM Serial DMA & 2 Virtual DMAs DUART Dual I2C 4 Channel DMA Interrupt Controller Protection & Configuration System Reset Clock Synthesizer Dual 32-bit RISC CP Time Slot Assigner Serial Interface 4 TDM Ports 6 MII/ RMII 2 GMII/ RGMII/TBI/RTBI 1 UTOPIA/POS (31/124 MPHY) Figure 2. MPC8358E Block Diagram Major features of the MPC8360E/58E are as follows: • e300 PowerPC processor core (enhanced version of the MPC603e core) — Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) — High-performance, superscalar processor core — Floating-point, integer, load/store, system register, and branch processing units — 32-Kbyte instruction cache, 32-Kbyte data cache — Lockable portion of L1 cache — Dynamic power management — Software-compatible with the Freescale processor families implementing the Power Architecture™ technology • QUICC Engine unit — Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E) — Serial DMA channel for receive and transmit on all serial channels MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Overview — QE peripheral request interface (for SEC, PCI, IEEE® Std 1588™) — Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them simultaneously): – IEEE Std. 1588 protocol supported – 10/100 Mbps Ethernet/IEEE Std. 802.3® CDMA/CS interface through a media-independent interface (MII, RMII, RGMII)1 – 1000 Mbps Ethernet/IEEE Std. 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2 – 9.6K jumbo frames – ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1 and AAL5 in accordance ITU-T I.363.5 – ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2 – ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up to 64K simultaneous ATM channels – ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000 – IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1) – ATM Transmission Convergence layer support in accordance with ITU-T I.432 – ATM OAM handling features compatible with ITU-T I.610 – PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs: 1661, 1662, 1990, 2686 and 3153 – IP support for IPv4 packets including TOS, TTL and header checksum processing – Ethernet over first mile IEEE Std. 802.3ah® – Shim header – Ethernet-to-Ethernet/AAL5/AAL2 inter-working – L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q® VLAN tags – ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM ports to Ethernet ports – Extensive support for ATM statistics and Ethernet RMON/MIB statistics – AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate – Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY – POS hardware; microcode must be loaded as an IRAM package – Transparent up to 70-Mbps full-duplex – HDLC up to 70-Mbps full-duplex – HDLC BUS up to 10 Mbps 1. SMII or SGMII media-independent interface is not currently supported MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 4 Freescale Semiconductor Overview • – Asynchronous HDLC – UART – BISYNC up to 2 Mbps – User-programmable Virtual FIFO size – QUICC Multichannel Controller (QMC) for 64 TDM channels — One multichannel communication controller (MCC) only on the MPC8360E supporting the following: – 256 HDLC or transparent channels – 128 SS7 channels – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces — Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY — Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management — Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel — Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels (MCC is only available on the MPC8360E) — Four independent 16-bit timers that can be interconnected as four 32-bit timers — Interworking functionality: – Layer 2 10/100-Base T Ethernet switch – ATM-to-ATM switching (AAL0, 2, 5) – Ethernet-to-ATM switching with L3/L4 support – PPP interworking Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs). — Public key execution unit (PKEU) supporting the following: – RSA and Diffie-Hellman – Programmable field size up to 2048 bits – Elliptic curve cryptography – F2m and F(p) modes – Programmable field size up to 511 bits — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Overview • — Implements the Rinjdael symmetric key cipher — Key lengths of 128, 192, and 256 bits, two key – ECB, CBC, CCM, and counter modes — ARC four execution unit (AFEU) – Implements a stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — Message digest execution unit (MDEU) – SHA with 160-, 224-, or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either SHA or MD5 algorithm — Random number generator (RNG) — Four crypto-channels, each supporting multi-command descriptor chains – Static and/or dynamic assignment of crypto-execution units via an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes — Storage/NAS XOR parity generation accelerator for RAID applications Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the MPC8358E — Programmable timing supporting both DDR1 and DDR2 SDRAM — On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E, the DDR bus can be configured as a 32-bit or a 64-bit bus — 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate — Four banks of memory, each up to 1 Gbyte — DRAM chip configurations from 64 Mbits to 1 Gigabit with x8/x16 data ports — Full ECC support (when the MPC8360E is configured as 2x32 bit DDR memory controllers, both support ECC) — Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2) — Contiguous or discontiguous memory mapping — Read-modify-write support — Sleep mode support for self refresh SDRAM — Supports auto refreshing — Supports source clock mode — On-the-fly power management using CKE — Registered DIMM support — 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 — External driver impedance calibration — On-die termination (ODT) MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 6 Freescale Semiconductor Overview • • • PCI interface — PCI Specification Revision 2.3 compatible — Data bus widths: – Single 32-bit data PCI interface that operates at up to 66 MHz — PCI 3.3-V compatible (not 5-V compatible) — PCI host bridge capabilities on both interfaces — PCI agent mode supported on PCI interface — Support for PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Support for posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration, supporting five masters on PCI — Support for accesses to all PCI address spaces — Parity support — Selectable hardware-enforced coherency — Address translation units for address mapping between host and peripheral — Dual address cycle supported when the device is the target — Internal configuration registers accessible from PCI Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 133 MHz — Eight chip selects support eight external slaves — Up to eight-beat burst transfers — 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for 8 external and 35 internal discrete interrupt sources — Support for one external (optional) and seven internal machine checkstop interrupt sources — Programmable highest priority request — Four groups of interrupts with programmable priority — External and internal interrupts directed to communication processor — Redirects interrupts to external INTA pin when in core disable mode — Unique vector number for each interrupt source MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Electrical Characteristics • • • • • • Dual industry-standard I2C interfaces — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus — System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller — Four independent virtual channels — Concurrent execution across multiple channels with programmable bandwidth control — All channels accessible by local core and remote PCI masters — Misaligned transfer capability — Data chaining and direct mode — Interrupt on completed segment and chain — DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions. DUART — Two 4-wire interfaces (RxD, TxD, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D System timers — Periodic interrupt timer — Real-time clock — Software watchdog timer — Eight general-purpose timers IEEE Std. 1149.1™ compliant, JTAG boundary scan Integrated PCI bus and SDRAM clock generation 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 8 Freescale Semiconductor Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD –0.3 to 1.32 –0.3 to 1.37 AV DD –0.3 to 1.32 –0.3 to 1.37 GVDD DDR DDR2 –0.3 to 2.75 –0.3 to 1.89 LVDD OVDD MVIN MVREF LVIN OVIN –0.3 to 3.63 –0.3 to 3.63 –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (OV DD + 0.3) V V V V V V 2, 5 2, 5 4, 5 3, 5 V V Max Value Unit V Notes Table 1 provides the absolute maximum ratings. Core supply voltage For QE frequencies