MPC8535EAVTANG

Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC8535EEC Rev. 2, 09/2009 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications • High-performance, 32-bit e500 core, scaling up to 1.25 GHz, that implements the Power Architecture™ technology – 36-bit physical addressing – Double-precision embedded floating point APU using 64-bit operands – Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands – Memory management unit (MMU) • Integrated L1/L2 cache – L1 cache—32-Kbyte data and 32-Kbyte instruction – L2 cache—512-Kbyte (8-way set associative) • DDR2/DDR3 SDRAM memory controller with full ECC support – One 64-bit/32-bit data bus – Up to 250-MHz clock (500-MHz data rate) – Supporting up to 16 Gbytes of main memory – Using ECC, detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble – Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode – Both hardware and software options to support battery-backed main memory • Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP. – XOR engine for parity checking in RAID storage applications • Enhanced Serial peripheral interfaces (eSPI) – Support boot capability from eSPI • Two enhanced three-speed Ethernet controllers (eTSECs) with SGMII support – Three-speed support (10/100/1000 Mbps) – Two IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588™-compatible controllers FC-PBGA–783 29 mm × 29 mm • • • • • • • • • • • • – Support for various Ethernet physical interfaces: GMII, TBI, RTBI, RGMII, MII, RGMII, RMII, and SGMII – Support TCP/IP acceleration and QOS features – MAC address recognition and RMON statistics support – Support ARP parsing and generating wake-up events based on the parsing results while in deep sleep mode – Support accepting and storing packets while in deep sleep mode High-speed interfaces (multiplexed) supporting: – Two PCI Express interfaces – PCI Express 1.0a compatible – One x4/x2/x1 PCI Express interface – Two x2/x1 ports – One SGMII interface – One Serial ATA (SATA) Controller supports SATA I and SATA II data rates PCI 2.2 compatible PCI controller Two universal serial bus (USB) dual-role controllers comply with USB specification revision 2.0 133-MHz, 32-bit, enhanced local bus (eLBC) with memory controller Enhanced secured digital host controller (eSDHC) used for SD/MMC card interface – Support boot capability from eSDHC Integrated four-channel DMA controller Dual I2C and dual universal asynchronous receiver/transmitter (DUART) support Programmable interrupt controller (PIC) Power management, low standby power – Support Doze, Nap, Sleep, Jog, and Deep Sleep mode – PMC wake on: LAN activity, USB connection or remote wakeup, GPIO, internal timer, or external interrupt event System performance monitor IEEE Std 1149.1™-compatible, JTAG boundary scan 783-pin FC-PBGA package, 29 mm × 29 mm This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. Table of Contents 1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .3 1.1 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.1 Overall DC Electrical Characteristics . . . . . . . . . . . . . .21 2.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.6 DDR2 and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . .31 2.7 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.9 Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.10 Ethernet Management Interface Electrical Characteristics 60 2.11 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.12 enhanced Local Bus Controller (eLBC) . . . . . . . . . . . .65 2.13 Enhanced Secure Digital Host Controller (eSDHC) . . .74 2.14 Programmable Interrupt Controller (PIC) . . . . . . . . . . .76 2.15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 2.16 Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.17 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.18 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 2.19 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.20 High-Speed Serial Interfaces . . . . . . . . . . . . . . . . . . . .90 3 2.21 PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.23 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 2.24 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . 113 3.1 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.2 Power Supply Design and Sequencing . . . . . . . . . . . 113 3.3 Pin States in Deep Sleep State . . . . . . . . . . . . . . . . . 114 3.4 Decoupling Recommendations . . . . . . . . . . . . . . . . . 114 3.5 SerDes Block Power Supply Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 3.6 Connection Recommendations . . . . . . . . . . . . . . . . . 115 3.7 Pull-Up and Pull-Down Resistor Requirements . . . . . 115 3.8 Output Buffer DC Impedance . . . . . . . . . . . . . . . . . . 115 3.9 Configuration Pin Muxing . . . . . . . . . . . . . . . . . . . . . 116 3.10 JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . 117 3.11 Guidelines for High-Speed Interface Termination . . . 119 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.1 Part Numbers Fully Addressed by This Document . . 121 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.1 Package Parameters for the MPC8535E FC-PBGA . 122 5.2 Mechanical Dimensions of the MPC8535E FC-PBGA123 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 124 4 5 6 7 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor Figure 1 shows the major functional units within the MPC8535E. e500 Core 32-Kbyte D-Cache 32-Kbyte I-Cache 512-Kbyte L2 Cache Power Management MPC8535E Performance Monitor Timers Enhanced Local Bus SEC OpenPIC Coherency Module eSPI DUART 2x I2C 64-bit Async DDR2/DDR3 Queue SDRAM Controller with ECC SD MMC USB Host/ Device ULPI USB Host/ Device ULPI Gigabit Ethernet w/ IEEE 1588 Gigabit Ethernet w/ IEEE 1588 SGMII SerDes PCI 32 SATA PCI-e DMA PCI-e 4 Lane SerDes Figure 1. MPC8535E Block Diagram 1 Pin Assignments and Reset States NOTE The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software NOTE The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to Table 1 for more details. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 Pin Map 1.1 Pin Map See Table 1 for the MPC8535E pinout, which is a subset of the MPC8536E. Figure 2 provides a bottom view of the pin map of the MPC8536E. A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MDQ [44] B GVDD MDQ [40] MDQ [45] C MDQS [5] MDM [5] MDQ [41] MCS [2] MRAS D MDQ [32] MDQS [5] MCS [0] GVDD E MDQ [46] GVDD F MDQ [47] MDQ [42] MDQ [33] G MDQ [34] MDQ [43] GVDD MDM [4] MDQ [37] MCS [3] GVDD MA [1] H GND MDQ [35] MDQ [38] J MDQ [56] MDQ [60] MDQ [52] MDQ [39] MDQS [4] MCK [2] K MDQ [57] MDQ [61] GVDD MDQ [53] MDQS [4] MCK [2] GND L GND MDM [7] MDM [6] MDQ [49] MDQ [48] M GVDD MDQS [7] MDQS [6] MDQS [6] N MDQS [7] P MDQ [58] MDM [62] MDQ [51] MDQ [55] R MDQ [59] MDQ [63] GVDD Rvsd T U V W Y AA AB AC AD AE AF AG AH USB1_ DIR USB1_ PWRFAULT AVDD_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_ USB1_D USB1_D USB1_ RXD SRDS2 RX_CLK RXD TX_EN RX_DV CLK STP [0] [2] [5] [7] [3] [1] AGND_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D USB1_ RXD SRDS2 RXD NXT RX_DV GTX_CLK RXD [1] [3] [4] [6] [1] [0] [3] SD2_ PLL_ TPA TSEC3_ RX_ER TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ USB1_ USB2_D USB2_D PCTL0/ RXD RXD TXD RXD RX_CLK RXD [0] [1] GPIO[6] [2] [0] [3] [2] [7] GND TVDD TSEC1_ TXD [1] GND LVDD USB1_ TSEC1_ PCTL1/ TX_CLK GPIO[7] GND OVDD GND OVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND MDQ [50] MDQ [54] GVDD GND MBA [0] MA [10] MAPAR_ OUT GND MCK [3] MCK [0] MA [3] MA [6] MA [11] MAPAR_ ERR GND MDQ [26] MDQ [30] MDQS [3] MDQ [25] MDQ [29] MDQ [11] MDQ [15] MDQS [1] MDQ [9] MDQ [8] MDQ [12] MDQ [0] GND MDQ [36] MODT [0] MODT [2] USB3_D USB3_D [1] [0] MWE MBA [1] GND GND USB2_D USB2_D USB3_D USB3_D [3] [2] [2] [3] GND GVDD MODT [3] MA [13] GVDD MCS [1] MODT [1] MCK [5] GND GND Rvsd TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD GTX_CLK TX_EN TXD TXD TXD TX_ER [1] [2] [4] [6] USB2_ USB2_D USB2_D USB3_D USB3_ [4] CLK [4] [5] CLK NC MA [0] MCK [3] MCK [0] GND GVDD SD2_ SD2_ IMP_CAL REF_ _TX CLK SD2_ PLL_ TPD Rsvd SD2_ REF_ CLK S2GND DMA_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D SD2_RX DACK[0]/ USB2_D OVDD USB3_D USB3_D S2VDD S2GND TXD RXD RXD TXD RXD CLK125 COL [5] [6] [7] [0] [6] GPIO[10] [0] [5] [4] [0] [4] SD2_ TSEC3_ S2VDD SD2_RX IMP_CAL TXD [0] _RX [2] SD2_RX S2GND [1] NC TVDD GND TSEC_ 1588_TRIG _IN[1] GND LVDD TSEC1_ USB2_ RXD NXT [6] USB2_ STP GND USB2_ DIR USB3_ USB3_D NXT [7] USB3_ DIR USB2_ PCTL0/ GPIO[8] USB3_ STP Rsvd GVDD MA [2] GVDD MA [5] MECC [3] NC MCAS NC MCK [5] SEE DETAIL A GND MA [4] GVDD MA [8] MA [14] GVDD GND MA [7] MA [15] MECC [2] GND GVDD MCKE [2] GVDD MECC [0] MCKE [3] MCKE [0] MCK [1] GVDD MCK [4] NC NC TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_ TSEC1_ USB2_ PWRTXD TXD TXD 1588_TRIG TXD RXD TXD FAULT [5] [5] [7] _IN[0] [3] [5] [6] SEE DETAIL B USB2_ PCTL1/ GPIO[9] GND NC MA [12] MECC [7] MDQS [8] MECC [1] GVDD MDQ [23] GVDD MCK [1] MCKE [1] GVDD MA [9] MBA [2] MDQ [27] MDQ [31] MDQS [3] MDM [3] MDQ [24] MDQ [28] MDQ [10] MDQ [14] MDQS [1] MDM [1] MDQ [13] MDQ [5] MDQ [1] LDP [2] GND TSEC3_ TSEC3_ TSEC3_ TSEC_ TSEC1_ TSEC1_ GND NC Rsvd 1588_ TXD COL TX_ER RX_ER CRS CLK [4] SDHC_ DMA_ TSEC_ TSEC_ EC_ TSEC3_ TSEC3_ 1588_CLK 1588_TRIG DAT[7]/SPI DREQ[0]/ NC NC NC NC X2GND MDC CRS TX_CLK _OUT _OUT[1] _CS[3] GPIO[14] TSEC_ TSEC_ TSEC_ DMA_ DMA_ EC_ SD2_TX SD2_TX 1588_PULSE 1588_TRIG1588_PULSE MSRCID DDONE[0]/ DDONE[1]/ X2GND X2VDD X2VDD MDIO GPIO[12] GPIO[13] [4] [1] [0] _OUT2 _OUT[0] _OUT1 SD2_RX S2GND S2VDD [1] TSEC3_ TSEC3_ MSRCID MSRCID UART_ SD2_TX X2GND SD2_TX X2VDD X2GND TXD CTS RXD [2] [0] [1] [0] [7] [7] [1] GND VDD_ CORE GND VDD_ CORE GND LCS7/ DMA_ DDONE2 LA [27] VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT XVDD GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND VDD_ PLAT XVDD TSEC3_ MDVAL MSRCID RXD [1] [6] VDD_ CORE GND VDD_ CORE GND VDD_ PLAT GND SENSEVDD_ CORE SENSEVSS VDD_ PLAT MSRCID [3] CLK_ OUT PCI1_ REQ [1] SENSEVDD_ PLAT GND UART_ SOUT [1] TEST_ SEL GND UART_ RTS [0] SDHC_ SPI_ SPI_ DAT[4]/SPI CLK MOSI _CS[0] SDHC_ SPI_ GND DAT[6]/SPI MISO _CS[2] DMA_ DACK[1]/ GPIO[11] UART_ CTS [0] SDHC_ DAT[5]/SPI OVDD _CS[1] GND UART_ SIN [0] DMA_ DREQ[1]/ GPIO[15] UART_ SDHC_ SDHC_ SOUT WP/GPIO CMD [0] [5] SDHC_ SDHC_ OVDD CD/GPIO DAT [3] [4] UART_ SIN [1] PCI1_ REQ [2] PCI1_ GNT [2] RTC IRQ [5] IRQ [1] PCI1_ AD [18] IRQ [3] SDHC_ SDHC_ DAT DAT [1] [0] SDHC_ SDHC_ DAT CLK [2] IIC2_ SDA HRESET_ REQ SYSCLK IIC2_ SCL GND MECC [6] GND NC MDM [8] MECC [5] GVDD GND MCK [4] GVDD VDD_ CORE GVDD MDIC [1] LA [28] LA [29] LCS [0] MDQS [8] GND MECC [4] GVDD GVDD GVDD MDIC [0] LCS5/ DMA_ DREQ2 LA [30] LGPL3/ LFWP LCS [2] LCS [3] LWE[3]/ LBS[3] LWE[1]/ LBS[1] GND MCP UART_ GND RTS [1] IRQ[10]/ IRQ[9]/ DMA_ OVDD DDRCLK DMA_ DACK[2] DREQ[2] IRQ[11]/ PCI1_GNT OVDD UDE [4]/GPIO DMA_ DDONE[2] [3] PCI1_ AD [31] OVDD PCI1_ AD [27] PCI1_ AD [22] PCI1_ AD [21] PCI1_ IRDY PCI1_ AD [28] PCI1_ AD [26] IRQ_ OUT OVDD PCI1_ AD [19] PCI1_ AD [16] GND PCI1_REQ [4]/GPIO [1] PCI1_ IDSEL PCI1_ AD [23] PCI1_ AD [20] PCI1_ AD [17] PCI1_ FRAME GND GND MDQ [19] GVDD MDQS [2] GND MDQ [18] MDQS [2] GVDD MDQ [16] GND GND LCS6/ DMA_ DACK2 GND PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] PCI1_ GNT [1] PCI1_ AD [30] PCI1_ REQ [0] PCI1_ AD [29] PCI1_ AD [25] GND L2_ TSTCLK GND LCS [4] LA [31] OVDD PCI1_ AD [24] PCI1_ C_BE [3] GND PCI1_ C_BE [2] PCI1_ STOP PCI1_ C_BE [1] GND PCI1_ AD [7] OVDD AVDD_ HRESET CORE IRQ [4] CKSTP_ OUT GND MDM [2] MDQ [17] GVDD MDQ [3] MDQ [6] MDQ [22] MDQ [21] MDQ [20] BVDD GND BVDD NC LCS [1] LGPL2/ LOE/ LFRE BVDD LGPL5 PCI1_ OVDD GND GNT [0] TRIG_ IRQ GND OUT/READY TRIG_IN [7] /QUIESCE XGND SD1_TX [6] XVDD CKSTP_ AVDD_ PLAT IN AVDD_ SRESET DDR GND GND MDQ [7] GVDD LAD [27] LAD [24] LDP [3] LAD [22] LAD [21] LAD [20] LGPL4/ LGTA/ LGPL0/ LGPL1/ LUPWAIT/ LFCLE LFALE LPBSE/ XGND LFRB SD1_TX [1] SD1_TX [1] SD1_TX [3] SD1_TX [4] SD1_TX [4] XGND AVDD_ OVDD ASLEEP PCI1 PCI1_ TRDY PCI1_ SERR PCI1_ AD [15] OVDD PCI1_ AD [4] PCI1_ AD [2] IIC1_ SCL IRQ [0] TRST IIC1_ SDA PCI1_ AD [11] PCI1_ AD [12] PCI1_ C_BE [0] PCI1_ CLK TMS GVDD MDQ [2] MDQS [0] GVDD MDM [0] LAD [25] GND LAD [29] LAD [31] LAD [30] LAD [28] LAD [26] BVDD LWE0/ LBS0 / LFWE GND LAD [0] LAD [3] LAD [4] LAD [7] LDP [0] LAD [11] LAD [10] LAD [1] LAD [2] XVDD XGND SEE DETAIL C BVDD LAD [23] LAD [19] LAD [18] LWE[2]/ LBS[2] LCLK [0] LCLK [2] BVDD LCLK [1] SD1_TX XGND [3] XVDD Rsvd XVDD SD1_TX [5] SD1_TX [5] SGND L1_ SD1_TX XGND TSTCLK [6] XVDD SD1_TX [7] SD1_TX [7] SVDD SD1_RX [4] IRQ [6] SD1_TX XGND [0] SD1_TX [0] XGND XVDD SD1_TX [2] SD1_TX [2] SGND SEE DETAIL D IRQ [8] PCI1_ PAR XVDD IRQ [2] PCI1_ AD [13] PCI1_ AD [5] PCI1_ PCI1_ PERR DEVSEL OVDD PCI1_ AD [14] PCI1_ AD [9] PCI1_ AD [1] GND GND BVDD LAD [5] LAD [6] XGND Rsvd XVDD XGND GND PCI1_ AD [10] PCI1_ AD [8] PCI1_ AD [3] PCI1_ AD [6] TCK MDQS [0] MDQ [4] NC SVDD SVDD SGND SVDD SGND SGND GND LBCTL NC SVDD SD1_RX [1] SD1_RX [1] SGND SGND SD1_RX [3] SVDD SD1_RX [3] SD1_RX SV DD [2] SD1_RX SGND [2] SVDD NC SD1_ PLL_ TPA AGND_ SRDS SD1_ PLL_ TPD SGND SVDD SD1_RX LSSD_ [6] MODE GND LAD [16] LAD [15] LDP [1] BVDD LAD [14] LAD [13] LALE GND LAD [9] LAD [8] SD1_ IMP_CAL SGND _RX SVDD SD1_RX [0] SD1_RX [0] SGND SD1_ REF_ CLK SD1_ REF_ CLK SVDD SD1_RX [4] NC AVDD_ SRDS SVDD SGND SD1_RX [5] SD1_RX [5] SD1_RX POWER_ PCI1_ AD OK [6] [0] SGND SD1_RX [7] GND GND LSYNC_ IN GND LAD [17] GND LAD [12] SVDD POWER_ OVDD EN SD1_ SGND IMP_CAL _TX TDO MVREF GND AVDD_ LSYNC_ OUT LBIU SGND SVDD SGND SVDD SD1_RX [7] TDI A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH Figure 2. MPC8535E Pin Map Bottom View MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 4 Freescale Semiconductor Pin Map A 1 MDQ [44] B GVDD MDQ [40] MDQ [45] C MDQS [5] MDM [5] MDQ [41] MCS [2] D MDQ [32] MDQS [5] MCS [0] E MDQ [46] F MDQ [47] MDQ [42] MDQ [33] G MDQ [34] MDQ [43] H GND J MDQ [56] MDQ [60] MDQ [52] MDQ [39] MDQS [4] MCK [2] K MDQ [57] MDQ [61] L GND M GVDD N MDQS [7] P MDQ [58] MDM [62] MDQ [51] MDQ [55] 2 GVDD MDQ [35] MDQ [38] MDM [7] MDM [6] MDQ [49] MDQ [48] SD2_ IMP_CAL _TX SD2_ PLL_ TPD Rsvd MDQS [7] MDQS [6] MDQS [6] GND 3 GND GND GVDD GVDD MDQ [50] MDQ [54] 4 MBA [0] MA [10] MAPAR_ OUT MWE GVDD MDQ [36] MODT [0] MODT [2] GND MDM [4] MDQ [37] MCS [3] GVDD GND MDQ [53] MDQS [4] MCK [2] 5 MBA [1] MRAS GND GVDD MODT [3] MA [13] GVDD GND SD2_ REF_ CLK SD2_ REF_ CLK S2GND GVDD GND 6 NC GND GVDD MCS [1] MODT [1] MCK [5] MCKE [3] MCKE [0] MCK [1] S2GND SD2_RX [0] SD2_RX [0] S2GND 7 GND MA [0] MCK [3] MCK [0] GVDD NC MCAS NC GND S2VDD SD2_RX [1] SD2_RX [1] NC 8 MCK [3] MCK [0] MA [3] MA [6] MA [11] MAPAR_ ERR GND MA [2] GND GVDD GND MA [1] MCK [5] GND 9 GVDD MA [4] MA [8] MA [14] MA [7] MA [15] MECC [2] GVDD NC NC Rsvd S2VDD S2GND 10 GND MA [5] MECC [3] NC MCKE [2] GVDD MCKE [1] NC X2GND NC 11 GVDD MA [12] MECC [7] MDQS [8] MECC [1] GVDD GVDD MCK [1] GND X2VDD SD2_TX [1] SD2_TX [1] VDD_ CORE X2GND SD2_TX [0] SD2_TX [0] VDD_ CORE 12 MA [9] MBA [2] MDQ [27] GND GND NC MECC [0] GVDD GND GVDD X2GND X2VDD 13 MECC [6] MDQS [8] MDM [8] MECC [5] GND MCK [4] MCK [4] VDD_ CORE GVDD GND GND 14 GVDD GVDD MECC [4] GVDD GND VDD_ CORE GND VDD_ CORE GND DETAIL A Figure 3. MPC8535E Pin Map Detail A MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 5 Pin Map R MDQ [59] MDQ [63] T AVDD_ SRDS2 AGND_ SRDS2 SD2_ PLL_ TPA TSEC3_ RX_ER U V W Y AA AB AC AD USB1_ CLK AE AF AG USB1_ STP OVDD AH USB1_ DIR USB1_ PWRFAULT TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D RXD RX_CLK RXD TX_EN RX_DV [0] [2] [3] [1] USB1_D USB1_D [7] [5] USB1_ NXT 1 TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ USB1_D USB1_D USB1_D USB1_D RXD RXD RX_DV GTX_CLK RXD [6] [1] [3] [4] [1] [0] [3] TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ RXD RXD TXD RXD RXD RX_CLK [2] [0] [3] [2] [7] GND TVDD TSEC1_ TXD [1] GND LVDD TSEC1_ TX_CLK USB1_ PCTL0/ GPIO[6] USB1_ PCTL1/ GPIO[7] GND USB2_D USB2_D [0] [1] OVDD 2 GVDD GND USB3_D USB3_D [1] [0] 3 Rvsd USB2_D USB2_D USB3_D USB3_D [3] [2] [2] [3] USB2_D USB2_D USB3_D [4] [4] [5] USB2_D [7] GND SDHC_ DAT[4]/SPI _CS[0] GND DMA_ DACK[1]/ GPIO[11] UART_ CTS [0] GND IRQ[9]/ DMA_ DREQ[2] OVDD OVDD USB2_ DIR SPI_ MOSI USB3_ CLK 4 Rvsd TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD TXD GTX_CLK TX_EN TX_ER [1] [2] [4] [6] USB2_ CLK 5 S2VDD DMA_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ EC_GTX_ TSEC1_ USB2_D DACK[0]/ TXD RXD RXD TXD RXD COL [6] CLK125 GPIO[10] [0] [5] [4] [0] [4] TVDD GND TSEC_ 1588_TRIG _IN[1] GND LVDD TSEC1_ RXD [6] USB2_ NXT USB2_ PWRFAULT USB2_ STP SPI_ CLK SPI_ MISO USB3_D USB3_D [5] [6] USB3_ NXT USB3_ DIR USB3_D [7] USB3_ STP Rsvd 6 SD2_ TSEC3_ IMP_CAL TXD _RX [2] NC 7 TSEC_ TSEC1_ TSEC1_ TSEC1_ TSEC3_ TSEC3_ TSEC3_ 1588_TRIG TXD RXD TXD TXD TXD TXD _IN[0] [5] [5] [7] [3] [5] [6] TSEC3_ TSEC3_ TSEC3_ TXD COL TX_ER [4] 8 NC NC USB2_ TSEC_ TSEC1_ TSEC1_ PCTL1/ GND 1588_ RX_ER CRS GPIO[9] CLK TSEC_ SDHC_ SDHC_ TSEC_ DMA_ TSEC3_ TSEC3_ 1588_CLK 1588_TRIG EC_ DAT[7]/SPI DREQ[0]/ DAT[5]/SPI MDC CRS TX_CLK _OUT _OUT[1] _CS[3] GPIO[14] _CS[1] EC_ MDIO UART_ CTS [1] GND DMA_ DMA_ DDONE[0]/ DDONE[1]/ GPIO[12] GPIO[13] UART_ SOUT [1] TEST_ SEL GND UART_ RTS [0] OVDD GND UART_ SIN [0] DDRCLK SDHC_ USB2_ DAT[6]/SPI PCTL0/ GPIO[8] _CS[2] UART_ SOUT [0] OVDD UART_ SIN [1] PCI1_ REQ [2] PCI1_ GNT [2] SDHC_ WP/GPIO [5] SDHC_ DAT [3] SDHC_ DAT [0] SDHC_ CLK IIC2_ SDA 9 OVDD DMA_ DREQ[1]/ GPIO[15] UART_ RTS [1] IRQ[10]/ DMA_ DACK[2] SDHC_ CMD SDHC_ CD/GPIO [4] SDHC_ DAT [1] SDHC_ DAT [2] SYSCLK 10 TSEC_ TSEC_ TSEC_ X2VDD 1588_PULSE 1588_TRIG 1588_PULSE MSRCID [4] _OUT[0] _OUT2 _OUT1 X2GND TSEC3_ TSEC3_ MSRCID MSRCID TXD RXD [0] [2] [7] [7] VDD_ CORE TSEC3_ RXD [6] VDD_ CORE MDVAL MSRCID [1] MSRCID [3] 11 12 GND 13 VDD_ CORE GND GND MCP UDE PCI1_GNT IRQ[11]/ DMA_ [4]/GPIO DDONE[2] [3] 14 DETAIL B Figure 4. MPC8535E Pin Map Detail B MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 6 Freescale Semiconductor Pin Map DETAIL C 15 MDQ [26] MDQ [30] MDQS [3] MDQ [25] MDQ [29] MDQ [11] MDQ [15] MDQS [1] MDQ [9] MDQ [8] MDQ [12] MDQ [0] MDQ [31] MDQS [3] MDM [3] MDQ [24] MDQ [28] MDQ [10] MDQ [14] MDQS [1] MDM [1] MDQ [13] MDQ [5] MDQ [1] LDP [2] GND GVDD GND GVDD GND MDIC [0] LCS5/ DMA_ DREQ2 LA [30] LGPL3/ LFWP LCS [2] LCS [3] LWE[3]/ LBS[3] LWE[1]/ LBS[1] LWE[2]/ LBS[2] LCLK [0] LCLK [2] GND LCS6/ DMA_ DACK2 GND MDIC [1] LA [28] LA [29] LCS [0] GND VDD_ CORE GND VDD_ CORE 16 MDQ [19] MDQ [23] MDQ [18] MDQS [2] GND LCS [4] LA [31] VDD_ CORE GND VDD_ CORE GND 17 GVDD GND MDQ [22] MDQ [21] MDQ [20] GND LCS7/ DMA_ DDONE2 LA [27] VDD_ PLAT GND VDD_ PLAT 18 MDQS [2] MDM [2] MDQ [17] GVDD MDQ [16] GND BVDD GND VDD_ PLAT GND 19 NC LCS [1] LGPL2/ LOE/ LFRE LAD [31] LAD [30] LAD [28] LAD [26] BVDD LGPL5 VDD_ PLAT GND VDD_ PLAT XVDD 20 GND GVDD GND BVDD LGPL0/ LFCLE BVDD LWE0/ LBS0/ LFWE BVDD LGPL4/ LGTA/ LGPL1/ LUPWAIT/ XGND LFALE LPBSE/ LFRB GND LAD [1] LAD [2] XVDD SD1_TX [1] SD1_TX [1] XGND 21 GVDD MDQ [3] MDQ [6] MDQ [7] GND XGND 22 MDQ [2] MDQS [0] GVDD LAD [29] LAD [0] LAD [3] LAD [4] LAD [7] LDP [0] LAD [11] LAD [10] SD1_TX [0] SD1_TX [0] XGND SD1_TX [2] SD1_TX [2] SGND 23 GND LAD [27] LAD [24] LDP [3] LAD [22] LAD [21] LAD [20] BVDD BVDD XVDD 24 GVDD MDQS [0] MDQ [4] LAD [23] LAD [19] LAD [18] LCLK [1] LAD [5] LAD [6] NC 25 MDM [0] LAD [25] GND LBCTL NC SD1_ IMP_CAL _RX SVDD SVDD SD1_RX [1] SD1_RX [1] SGND 26 GND LAD [16] LAD [15] LDP [1] BVDD LAD [14] LAD [13] LALE GND SGND 27 GND GND LSYNC_ IN LSYNC_ OUT GND GND LAD [9] LAD [8] SD1_RX [0] SD1_RX [0] 28 MVREF GND AVDD_ LBIU LAD [17] LAD [12] SGND SVDD A B C D E F G H J K L M N P Figure 5. MPC8535E Pin Map Detail C MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 7 Pin Map DETAIL D GND VDD_ CORE GND SENSEVDD_ CORE SENSEVSS VDD_ PLAT CLK_ OUT PCI1_ REQ [1] SENSEVDD_ PLAT PCI1_ GNT [0] PCI1_REQ PCI1_GNT [3]/GPIO [3]/GPIO [0] [2] PCI1_ GNT [1] PCI1_ AD [30] OVDD IRQ [7] PCI1_ REQ [0] PCI1_ AD [29] PCI1_ AD [25] GND L2_ TSTCLK L1_ TSTCLK IRQ [6] PCI1_ AD [31] OVDD PCI1_ AD [27] PCI1_ AD [22] PCI1_ AD [21] PCI1_ IRDY PCI1_ PERR IRQ [8] IRQ [2] PCI1_ AD [28] PCI1_ AD [26] IRQ_ OUT OVDD PCI1_ AD [19] PCI1_ AD [16] PCI1_ DEVSEL PCI1_ PAR PCI1_ AD [13] PCI1_ AD [5] LSSD_ MODE GND PCI1_REQ [4]/GPIO [1] PCI1_ IDSEL PCI1_ AD [23] PCI1_ AD [20] PCI1_ AD [17] PCI1_ FRAME RTC HRESET_ REQ HRESET IIC2_ SCL AVDD_ CORE CKSTP_ OUT AVDD_ PLAT AVDD_ DDR AVDD_ PCI1 15 VDD_ CORE GND VDD_ CORE OVDD PCI1_ AD [24] PCI1_ C_BE [3] GND PCI1_ C_BE [2] PCI1_ STOP PCI1_ C_BE [1] GND PCI1_ AD [7] OVDD PCI1_ AD [0] SVDD IRQ [5] IRQ [1] PCI1_ AD [18] IRQ [3] 16 GND VDD_ PLAT GND IRQ [4] CKSTP_ IN SRESET 17 VDD_ PLAT GND VDD_ PLAT GND 18 GND VDD_ PLAT XVDD GND TRIG_ OUT/READY TRIG_IN /QUIESCE XGND SD1_TX [6] SD1_TX [6] XVDD 19 SD1_TX [3] SD1_TX [3] XVDD SD1_TX [4] SD1_TX [4] XVDD OVDD PCI1_ TRDY PCI1_ SERR PCI1_ AD [15] OVDD PCI1_ AD [4] PCI1_ AD [2] OVDD ASLEEP 20 XGND XVDD SD1_TX [5] SD1_TX [5] SGND XGND GND IIC1_ SCL IRQ [0] TRST 21 Rsvd XGND SD1_TX [7] SD1_TX [7] SVDD OVDD PCI1_ AD [14] PCI1_ AD [9] PCI1_ AD [1] GND IIC1_ SDA PCI1_ AD [11] PCI1_ AD [12] PCI1_ C_BE [0] PCI1_ CLK 22 XGND Rsvd XVDD XGND XVDD GND PCI1_ AD [10] PCI1_ AD [8] PCI1_ AD [3] PCI1_ AD [6] TCK 23 SVDD SVDD SGND SVDD SGND SGND 24 SGND SD1_RX [3] SD1_RX [3] SVDD SVDD NC SD1_ PLL_ TPA AGND_ SRDS SD1_ PLL_ TPD SGND SD1_RX [4] SD1_RX [4] SVDD SVDD SD1_RX [6] 25 SVDD SD1_RX [2] SD1_RX [2] SGND SD1_ REF_ CLK SD1_ REF_ CLK SVDD SGND SD1_RX POWER_ OK [6] SGND SD1_RX [7] SD1_RX [7] 26 NC AVDD_ SRDS SD1_RX [5] SD1_RX [5] POWER_ EN SD1_ IMP_CAL _TX TMS 27 SGND SGND SVDD SGND TDO TDI 28 R T U V W Y AA AB AC AD AE AF AG AH Figure 6. MPC8535E Pin Map Detail D MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 8 Freescale Semiconductor Pin Map Table 1 provides the pin-out listing for the MPC8535E 783 FC-PBGA package. 3 Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number PCI Pin Type Power Supply Notes PCI1_AD[31:0] Muxed Address / data AB15,Y17,AA17,AC15, AB17,AC16,AA18, AD17,AE17,AB18, AB19,AE18,AC19, AF18,AE19,AC20, AF23,AE23,AC23, AH24,AH23,AG24, AE24,AG25,AD24, AG27,AC24,AF25, AG26,AF26,AE25, AD26 AD18, AD20,AD22, AH25 AC22 AE20 AF21 AB20 AD21 AC21 AE16 AB21 AF22 AE15,Y15 AF13,W16 AA16 AC14, AA15 AF14,Y16 W18 AH26 I/O OVDD — PCI1_C_BE[3:0] PCI1_PAR PCI1_FRAME PCI1_TRDY PCI1_IRDY PCI1_STOP PCI1_DEVSEL PCI1_IDSEL PCI1_PERR PCI1_SERR PCI1_REQ [4:3]/GPIO[1:0] PCI1_REQ [2:1] PCI1_REQ[0] PCI1_GNT[4:3]/GPIO[3:2] PCI1_GNT[2:1] PCI1_GNT[0] PCI1_CLK Command/Byte Enable Parity Frame Target Ready Initiator Ready Stop Device Select Init Device Select Parity Error System Error Request Request Request Grant Grant Grant PCI Clock I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I I/O O O I/O I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 29 29 2,29 2,29 2,29 2,29 2,29 29 2,29 2,4,29 — 29 29 5,9,25,29 29 29 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 9 Pin Map Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes DDR SDRAM Memory Interface MDQ[0:63] Data A26,B26,C22,D21,D25, B25,D22,E21,A24,A23, B20,A20,A25,B24,B21, A21,E19,D19,E16,C16, F19,F18,F17,D16,B18, A18,A15,B14,B19,A19, A16,B15,D1,F3,G1,H2, E4,G5,H3,J4,B2,C3,F2, G2,A2,B3,E1,F1,L5,L4, N3,P3,J3,K4,N4,P4,J1, K1,P1,R1,J2,K2,P2,R2 G12,D14,F11,C11, G14,F14,C13,D12 A13 A6 C25,B23,D18,B17,G4, C2,L3,L2,F13 D24,B22,C18,A17,J5, C1,M4,M2,E13 C23,A22,E17,B16,K5, D2,M3,N1,D13 B7,G8,C8,A10,D9,C10, A11,F9,E9,B12,A5, A12,D11,F7,E10,F10 A4,B5,B13 B4 C5 E7 D3,H6,C4,G6 H10,K10,G10,H9 A9,J11,J6,A8,J13,H8 B9,H11,K6,B8,H13,J8 E5,H7,E6,F6 H15,K15 Local Bus Controller Interface I/O GVDD — MECC[0:7] MAPAR_ERR MAPAR_OUT MDM[0:8] MDQS [0:8] MDQS[0:8] MA[0:15] Error Correcting Code Address Parity Error Address Parity Out Data Mask Data Strobe Data Strobe Address I/O I O O I/O I/O O GVDD GVDD GVDD GVDD GVDD GVDD GVDD — — — — — — — MBA[0:2] MWE MRAS MCAS MCS [0:3] MCKE[0:3] MCK[0:5] MCK [0:5] MODT[0:3] MDIC[0:1] Bank Select Write Enable Row Address Strobe Column Address Strobe Chip Select Clock Enable Differential Clock 3 Pairs / DIMM Differential Clock 3 Pairs / DIMM On Die Termination Calibration O O O O O O O O O I/O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD — — — — — 11 — — — 26 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 10 Freescale Semiconductor Pin Map Table 1. MPC8535E Pinout Listing Signal LAD[0:31] Signal Name Muxed data / address Package Pin Number K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 K26,G28,B27,E25 L19 K16,K17,H17,G17 K18,G19,H19,H20,G16 Pin Type I/O Power Supply BVDD Notes 5,9,29 LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LFWE LWE[1:3]/LBS[1:3] LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE/LFRE Data parity Burst address Port address Chip selects I/O O O O I/O O O O O O O O O O BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD 29 5,9,29 5,7,9,29 29 1,29 1,29 1,29 5,9,29 5,9,29 5,8,9,29 5,8,9,29 5,9,29 5,9,29 5,8,9,29 Chips selects / DMA Request H16 Chips selects / DMA Ack Chips selects / DMA Done Write enable / Byte select Write enable / Byte select Buffer control Address latch enable J16 L18 J22 H22,H23,H21 J25 J26 UPM general purpose line 0 / J20 FLash command latch enable UPM general purpose line 1 / K20 Flash address latch enable UPM general purpose line 2 / G20 Output enable/Flash read enable UPM general purpose line 3 / H18 Flash write protect UPM general purpose line 4 / L20 Target Ack/Wait/SDRAM parity byte select/Flash Ready-busy UPM general purpose line 5 / K19 Amux Local bus clock Synchronization Local bus DLL H24,J24,H25 D27 D28 DMA LGPL3/LFWP LGPL4/LGTA /LUPWAIT /LPBSE/LFRB O I/O BVDD BVDD 5,9,29 29 LGPL5 LCLK[0:2] LSYNC_IN LSYNC_OUT O O I O BVDD BVDD BVDD BVDD 5,9,29 29 29 29 DMA_DACK[0:1] /GPIO[10:11] DMA Acknowledge AD6,AE10 O OVDD — MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 11 Pin Map Table 1. MPC8535E Pinout Listing Signal DMA_DREQ [0:1] /GPIO[14:15] DMA_DDONE [0:1] /GPIO[12:13] DMA_DREQ[2]/LCS[5] DMA_DACK[2]/LCS[6] DMA_DDONE[2]/LCS[7] DMA_DREQ[3]/IRQ[9] DMA_DACK[3]/IRQ[10] DMA_DDONE[3]/IRQ[11] Signal Name DMA Request DMA Done Package Pin Number AB10,AD11 AA11,AB11 Pin Type I O I/O O O I I/O I/O Power Supply OVDD OVDD BVDD BVDD BVDD OVDD OVDD OVDD Notes — — 1,29 1,29 1,29 1 1 1 Chips selects / DMA Request H16 Chips selects / DMA Ack Chips selects / DMA Done External interrupt/DMA request External interrupt/DMA Ack J16 L18 AE13 AD13 External interrupt/DMA done AD14 USB Port 1 USB1_D[7:0] USB1_NXT USB1_DIR USB1_STP USB1_PWRFAULT USB1_PCTL0/GPIO[6] USB1_PCTL1/GPIO[7] USB1_CLK USB1 Data bits USB1 Next data USB1 Data Direction USB1 Stop USB1 bus power fault. USB1 Port control 0 USB1 Port control 1 USB1 bus clock AF1,AE2,AE1,AD2, AC2,AC1,AB2,AB1 AF2 AH1 AG1 AH2 AC3 AC4 AD1 USB Port 2 I/O I I O I O O I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD — — — 5,9 — — — — USB2_D[7:0] USB2_NXT USB2_DIR USB2_STP USB2_PWRFAULT USB2_PCTL0/GPIO[8] USB2_PCTL1/GPIO[9] USB2_CLK USB2 Data bits USB2 Next data USB2 Data Direction USB2 Stop USB2 bus power fault. USB2 Port control 0 USB2 Port control 1 USB2 bus clock AE6,AC6,AF5,AE5, AF4,AE4,AE3,AD3 AC7 AF7 AD7 AC8 AG9 AC9 AD5 — I/O I I O I O O I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD — — — 5,9 — — — — Reserved Reserved — — AH8 AH7,AG6,AH6,AG5, AG4,AH4,AG3,AH3, AG7, AG8, AH9,AH5 — — — — — 27 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 12 Freescale Semiconductor Pin Map Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes Programmable Interrupt Controller MCP UDE IRQ[0:8] Machine check processor Unconditional debug event External interrupts Y14 AB14 AG22,AF17,AB23, AF19,AG17,AF16, AA22,Y19,AB22 AE13 AD13 I I I OVDD OVDD OVDD — — — IRQ[9]/DMA_DREQ[3] IRQ[10]/DMA_DACK[3] IRQ[11]/DMA_DDONE[3] IRQ_OUT External interrupt/DMA request External interrupt/DMA Ack I I/O I/O O OVDD OVDD OVDD OVDD 1 1 1 2,4 External interrupt/DMA done AD14 Interrupt output AC17 Ethernet Management Interface EC_MDC EC_MDIO Management data clock Management data In/Out Y10 Y11 O I/O OVDD OVDD 5,9,22 — Gigabit Reference Clock EC_GTX_CLK125 Reference clock AA6 I LVDD 31 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_TXD[7:0] TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK TSEC1_GTX_CLK TSEC1_CRS TSEC1_COL TSEC1_RXD[7:0] TSEC1_RX_DV TSEC1_RX_ER TSEC1_RX_CLK Transmit data Transmit Enable Transmit Error Transmit clock In Transmit clock Out Carrier sense Collision detect Receive data Receive data valid Receive data error Receive clock AA8,AA5,Y8,Y5,W3, W5,W4,W6 W1 AB5 AB4 W2 AA9 AB6 AB3,AB7,AB8,Y6,AA2, Y3,Y1,Y2 AA1 Y9 AA3 O O O I O I/O I I I I I LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD 5,9,22 23 5,9 — — 17 — — — — — Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[7:0] TSEC3_TX_EN TSEC3_TX_ER Transmit data Transmit Enable Transmit Error T12,V8,U8,V9,T8,T7, T5,T6 V5 U9 O O O LVDD LVDD LVDD 5,9,22 23 5,9 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 13 Pin Map Table 1. MPC8535E Pinout Listing Signal TSEC3_TX_CLK TSEC3_GTX_CLK TSEC3_CRS TSEC3_COL TSEC3_RXD[7:0] TSEC3_RX_DV TSEC3_RX_ER TSEC3_RX_CLK Signal Name Transmit clock In Transmit clock Out Carrier sense Collision detect Receive data Receive data valid Receive data error Receive clock Package Pin Number U10 U5 T10 T9 U12,U13,U6,V6,V1,U3, U2,V3 V2 T4 U1 IEEE 1588 TSEC_1588_CLK TSEC_1588_TRIG_IN[0:1] Clock In Trigger In W9 W8,W7 U11,W10 V10 V11 T11 eSDHC SDHC_CMD SDHC_CD/GPIO[4] SDHC_DAT[0:3] SDHC_DAT[4:7] / SPI_CS[0:3] SDHC_CLK SDHC_WP /GPIO[5] Command line Card detection Data line AH10 AH11 AG12,AH12,AH13, AG11 I/O I I/O I/O I/O I OVDD OVDD OVDD OVDD OVDD OVDD 29 — 29 29 29 1, 32 I I O O O O LVDD LVDD LVDD LVDD LVDD LVDD 29 29 5,9,29 5,9,29 5,9,29 5,9,29 Pin Type I O I/O I I I I I Power Supply LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD Notes — — 17 — — — — — TSEC_1588_TRIG_OUT[0:1] Trigger Out TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT1 TSEC_1588_PULSE_OUT2 Clock Out Pulse Out1 Pulse Out2 8-bit MMC Data line / SPI chip AE8,AC10,AF9,AA10 select SD/MMC/SDIO clock Card write protection AG13 AG10 eSPI SPI_MOSI SPI_MISO SPI_CLK SPI_CS[0:3] / SDHC_DAT[4:7] Master Out Slave In Master In Slave Out eSPI clock AF8 AD9 AD8 I/O I I/O I/O OVDD OVDD OVDD OVDD 29 29 29 29 eSPI chip select / SDHC 8-bit AE8,AC10,AF9,AA10 MMC data DUART UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] Clear to send Ready to send Receive data AE11,Y12 AB12,AD12 AC12,AF12 I O I OVDD OVDD OVDD 29 29 29 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 14 Freescale Semiconductor Pin Map Table 1. MPC8535E Pinout Listing Signal UART_SOUT[0:1] Signal Name Transmit data Package Pin Number AF10,AA12 I2C interface IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA Serial clock Serial data Serial clock Serial data AG21 AH22 AH15 AG14 SerDes1(x4) SD1_TX[7:4] SD1_TX[7:4] SD1_RX[7:4] SD1_RX[7:4] Reserved Reserved SD1_PLL_TPD SD1_REF_CLK SD1_REF_CLK Reserved Reserved — Transmit Data (+) Transmit Data(-) Receive Data(+) Receive Data(–) — — PLL test point Digital PLL Reference clock PLL Reference clock complement — Y23,W21,V23,U21 Y22,W20,V22,U20 AC28,AB26,AA28,Y26 AC27,AB25,AA27,Y25 R21,P23,N21,M23, R20,P22,N20,M22 T26,R28,P26,N28, T25,R27,P25,N27 V28 U28 U27 T22 T23 SerDes2(x1) SD2_TX[0] SD2_TX[0] SD2_RX[0] SD2_RX[0] Reserved Reserved SD2_PLL_TPD SD2_REF_CLK SD2_REF_CLK Reserved Reserved Transmit data(+) Transmit data(-) Receive data(+) Receive data(-) — — PLL test point Digital PLL Reference clock PLL Reference clock complement — — P11 P12 P6 P7 M11,M12 N8, N9 L7 M6 M7 L8 L9 O O I I — — O I I — — X2VDD X2VDD X2VDD X2VDD — — X2VDD X2VDD X2VDD X2VDD X2VDD — — — — 18 34 18 — — 18 18 O O I I — — O I I — — XVDD XVDD XVDD XVDD — — XVDD XVDD XVDD — — — — — — 18 33 18 — — 18 18 I/O I/O I/O I/O OVDD OVDD OVDD OVDD 4,21,29 4,21,29 4,21,29 4,21,29 Pin Type O Power Supply OVDD Notes 5,9,22, 10,29 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15 Pin Map Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes General-Purpose Input/Output GPIO[0:1]/PCI1_REQ[3:4] GPIO[2:3]/PCI1_GNT[3:4] GPIO[4]/SDHC_CD GPIO[5]/SDHC_WP GPIO[6]/USB1_PCTL0 GPIO[7]/USB1_PCTL1 GPIO[8]/USB2_PCTL0 GPIO[9]/USB2_PCTL1 GPIO[10:11] /DMA_DACK[0:1] GPIO[12:13] /DMA_DDONE[0:1] GPIO[14:15] /DMA_DREQ[0:1] GPIO/PCI request GPIO/PCI grant GPIO/SDHC card detection Y15,AE15 AA15,AC14 AH11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD — — — 32 — — — — — — — GPIO/SDHC write protection AG10 GPIO/USB1 PCTL0 GPIO/USB1 PCTL1 GPIO/USB2 PCTL0 GPIO/USB2 PCTL1 GPIO/DMA Ack GPIO/DMA done GPIO/DMA request AC3 AC4 AG9 AC9 AD6,AE10 AA11,AB11 AB10,AD11 System Control HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT Hard reset Hard reset - request Soft reset CheckStop in CheckStop Output AG16 AG15 AG19 AG18 AH17 Debug I O I I O OVDD OVDD OVDD OVDD OVDD — 22 — — 2,4 TRIG_IN TRIG_OUT/READY /QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT Trigger in Trigger out/Ready/Quiesce W19 V19 I O O O O O OVDD OVDD OVDD OVDD OVDD OVDD — 22 6,9 6,9,22 6,22 11 Memory debug source port ID W12,W13 Memory debug source port ID V12, W14,W11 Memory debug data valid Clock Out V13 W15 Clock RTC SYSCLK DDRCLK Real time clock System clock / PCI clock DDR clock AF15 AH14 AC13 JTAG I I I OVDD OVDD OVDD — — 30 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 16 Freescale Semiconductor Pin Map Table 1. MPC8535E Pinout Listing Signal TCK TDI TDO TMS TRST Signal Name Test clock Test data in Test data out Test mode select Test reset Package Pin Number AG28 AH28 AF28 AH27 AH21 DFT L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL L1 test clock L2 test clock LSSD Mode Test select AA21 AA20 AC25 AA13 Power Management ASLEEP POWER_OK POWER_EN Asleep Power OK Power enable AG20 AC26 AE27 Power and Ground Signals OVDD General I/O supply Y18,AG2,AD4,AB16, AF6,AC18,AB13,AD10, AE14,AD16,AD25, AF27,AE22,AF11, AF20,AF24 — AA7, AA4 — OVDD — O I O OVDD OVDD OVDD 9,16,22 — — I I I I OVDD OVDD OVDD OVDD 19 19 19 19 Pin Type I I O I I Power Supply OVDD OVDD OVDD OVDD OVDD Notes — 12 11 12 12 PVDD LVDD — GMAC 1 I/O supply — Power for TSEC1 interfaces Power for TSEC3 interfaces Power for DDR DRAM I/O 3.3 V LVDD — — TVDD GMAC 3 I/O supply V4,U7 TVDD — GVDD SSTL2 DDR supply B1,B11,C7,C9,C14, C17,D4,D6,R3,D15,E2, E8,C24,E18,F5,E14, C21,G3,G7,G9,G11, H5,H12,E22,F15,J10, K3,K12,K14,H14,D20, E11,M1,N5 L23,J18,J23,J19,F20, F23,H26,J21 M27,N25,P28,R24, R26,T24,T27,U25, W24,W26,Y24,Y27, AA25,AB28,AD27 GVDD — BVDD SVDD Local bus I/O supply SerDes 1 core logic supply Power for Local Bus — BVDD SVDD — — MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17 Pin Map Table 1. MPC8535E Pinout Listing Signal XVDD Signal Name SerDes 1 transceiver supply Package Pin Number M21,N23,P20,R22,T20, U23,V21,W22,Y20, AA23 R6,N7,M9 R11,N12,L11 P13,U16,L16,M15,N14, R14,P15,N16,M13, U14,T13,L14,T15,R16, K13 T19,T17,V17,U18,R18, N18,M19,P19,P17,M17 AH16 AH18 AH19 C28 AH20 W28 T1 V15 W17 D5,AE7,F4,D26,D23, C12,C15,E20,D8,B10, AF3,E3,J14,K21,F8,A3, F16,E12,E15,D17,L1, F21,H1,G13,G15,G18, C6,A14,A7,G25,H4, C20,J12,J15,J17,F27, M5,J27,K11,L26,K7, K8,T14,V14,M16,M18, P14,N15,N17,N19,N2, P5,P16,P18,M14,R15, R17,R19,T16,T18,L17, U15,U17,U19,V18,C27, Y13,AE26,AA19,AE21, B28,AC11,AD19,AD23, L15,AD15,AG23,AE9, A27,V7,Y7,AC5,U4,Y4, AE12,AB9,AA14,N13, R13,L13 M20,M24,N22,P21, R23,T21,U22,V20, W23, Y21 Pin Type — Power Supply XVDD Notes — S2VDD X2VDD VDD_CORE SerDes 2 core logic supply SerDes 2 transceiver supply Core, L2 logic supply — — — S2VDD X2VDD VDD_CORE — — — VDD_PLAT AVDD_CORE AVDD_PLAT AVDD_DDR AVDD_LBIU AVDD_PCI1 AVDD_SRDS AVDD_SRDS2 SENSEVDD_CORE SENSEVDD_PLAT GND Platform logic supply CPU PLL supply Platform PLL supply DDR PLL supply Local Bus PLL supply PCI PLL supply SerDes 1 PLL supply SerDes 2 PLL supply — — Ground — — — — — — — — — — — VDD_PLAT AVDD_CORE AV DD_PLAT AVDD_DDR AVDD_LBIU AVDD_PCI1 AV DD_SRDS AVDD_SRDS2 VDD_CORE VDD_PLAT — — 20,28 20 20 20 20 20 20 13 13 — XGND SerDes 1Transceiver pad GND (xpadvss) — — — MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 18 Freescale Semiconductor Pin Map Table 1. MPC8535E Pinout Listing Signal SGND Signal Name SerDes 1 Transceiver core logic GND (xcorevss) Package Pin Number M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 R12,M10,N11,L12 P8,P9,N6,M8 V27 T2 V16 Analog Signals MVREF SSTL2 reference voltage A28 Reference voltage for DDR — — — — — — — — GVDD/2 — Pin Type — Power Supply — Notes — X2GND S2GND AGND_SRDS AGND_SRDS2 SENSEVSS SerDes 2 Transceiver pad GND (xpadvss) SerDes 2 Transceiver core logic GND (xcorevss) SerDes 1 PLL GND SerDes 2 PLL GND GND Sensing — — — — — — — — — — — — — — 13 SD1_IMP_CAL_RX SD1_IMP_CAL_TX SD1_PLL_TPA SD2_IMP_CAL_RX SD2_IMP_CAL_TX SD2_PLL_TPA Reserved Reserved Rx impedance calibration Tx impedance calibration PLL test point analog Rx impedance calibration Tx impedance calibration PLL test point analog — — M26 AE28 V26 R7 L6 T3 R4 R5 200Ω (±1%) to GND 100Ω (±1%) to GND AVDD_SRD S analog 200Ω (±1%) to GND 100Ω (±1%) to GND AVDD_SRD S2 analog — — — — 18 — — 18 — — No Connect Pins NC — C19,D7,D10,L10,R10, B6,F12,J7,P10,M25, W27,N24,N10,R8,J9, K9,V25,R9 — — — MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 19 Pin Map Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes Notes: 1. All multiplexed signals may be listed only once and may not re-occur. 2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OVDD. 3. This pin must always be pulled-high. 4. This pin is an open drain signal. 5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 6. Treat these pins as no connects (NC) unless using debug address functionality. 7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See Section 22.2, “CCB/SYSCLK PLL Ratio.” 8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See the Section 22.3, “e500 Core PLL Ratio.” 9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 10.For proper state of these signals during reset, UART_SOUT[1] must be pulled down to GND through a resistor. UART_SOUT[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the net at reset, then a pullup is needed on UART_SOUT[0]. 11.This output is actively driven during reset rather than being three-stated during reset. 12.These JTAG pins have weak internal pull-up P-FETs that are always enabled. 13.These pins are connected to the VDD_CORE/V DD_PLAT/GND planes internally and may be used by the core power supply to improve tracking and regulation. 15. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD and pull-down resistor pads to GND on board to support future debug testing when needed. 16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state during reset. 17. This pin is only an output in FIFO mode when used as Rx Flow Control. 18. Do not connect. 19.These must be pulled up (100 Ω- 1 kΩ) to OVDD. 20. Independent supplies derived from board VDD. 21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OVDD. 22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0], EC_MDC, TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, M SRCID[2:4], ASLEEP. 23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 24. General-Purpose POR configuration of user system. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 20 Freescale Semiconductor O verall DC Electrical Characteristics Table 1. MPC8535E Pinout Listing Signal Signal Name Package Pin Number Pin Type Power Supply Notes 25. When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as “No Connect” or terminated through 2–10 K Ω pull-up resistors with the default of internal arbiter if the address pins are not connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is any other PCI device connected on the bus. 26.MDIC[0] is grounded through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor and MDIC[1] is connected to GVDD through an 18.2-Ω (full-strength mode) or 36.4-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR IOs. 27.Connect to GND through a pull down 1 kΩ resistor. 28. It must be the same as VDD_CORE 29. The output pads are tristated and the receivers of pad inputs are disabled during the Deep Sleep state when GCR[DEEPSLEEP_Z] =1. 30. DDRCLK input is only required when the DDR controller is running in asynchronous mode. When the DDR controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the MPC8536E PowerQUICC™ III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”, section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding DDR controller operation in asynchronous and synchronous modes. 31. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND. 32. SDHC_WP is active low signal, which follows SDHC Host controller specification. However, it is reversed polarity for SD/MMC card specification. 33. Must connect to XGND. 34. Must connect to X2GND 2 2.1 Electrical Characteristics Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 2. Absolute Maximum Ratings1 Characteristic Symbol VDD_CORE VDD_PLAT AVDD_CORE AVDD SVDD, S2VDD XVDD, X2VDD Max Value –0.3 to 1.21 –0.3 to 1.1 –0.3 to 1.21 –0.3 to 1.1 –0.3 to 1.1 –0.3 to 1.1 Unit Notes V V V V V V — — — — — — Table 2 provides the absolute maximum ratings. Core supply voltage Platform supply voltage PLL core supply voltage PLL other supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers and PCI Express MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21 Overall DC Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Characteristic DDR SDRAM Controller I/O supply voltage DDR2 SDRAM Interface DDR3 SDRAM Interface LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage Local bus I/O voltage OVDD BVDD Symbol GVDD Max Value –0.3 to 1.98 –0.3 to 1.65 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (TVDD + 0.3) –0.3 to (BVDD + 0.3) –0.3 to (OVDD + 0.3) –55 to 150 V V V V 2 2 — — Unit Notes V — Three-speed Ethernet I/O, MII management voltage Input voltage DDR2/DDR3 DRAM signals DDR2/DDR3 DRAM reference Three-speed Ethernet signals Local bus signals PCI, DUART, SYSCLK, system control and power management, I2C, and JTAG signals MVIN MVREF LV IN TV IN BV IN OVIN TSTG V V V — V 0C 3 — 3 — 3 — Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. The 3.63-V maximum is only supported when the port is configured in GMII, MII, RMII or TBI modes; otherwise the 2.75V maximum applies. See Section 2.9.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” for details on the recommended operating conditions per protocol. 3. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 2.1.2 Recommended Operating Conditions Table 3 provides the recommended operating conditions for this device. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 3. Recommended Operating Conditions Characteristic Core supply voltage Platform supply voltage PLL core supply voltage PLL other supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers and PCI Express Symbol VDD_CORE VDD_PLAT AVDD_CORE AVDD SVDD XVDD Recommended Value Unit Notes 1.0 ± 50 mV 1.0 ± 50 mV 1.0 ± 50 mV 1.0 ± 50 mV 1.0 ± 50 mV 1.0 ± 50 mV V V V V V V — — 2 2 — — MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 22 Freescale Semiconductor O verall DC Electrical Characteristics Table 3. Recommended Operating Conditions (continued) Characteristic DDR2 SDRAM Interface DDR SDRAM Controller I/O supply DDR3 SDRAM Interface voltage Three-speed Ethernet I/O voltage Symbol GVDD Recommended Value Unit Notes 1.8 V ± 90 mV 1.5 V ± 75 mV LVDD (eTSEC1) TVDD (eTSEC3) PCI, DUART, system control and power management, I2C, USB, eSDHC, eSPI and JTAG I/O voltage Local bus I/O voltage OVDD BVDD 3.3 V ± 165 mV 2.5 V ± 125 mV 3.3 V ± 165 mV 2.5 V ± 125 mV 3.3 V ± 165 mV 3.3 V ± 165 mV 2.5 V ± 125 mV 1.8 V ± 90 mV GND to GV DD GVDD/2 ± 1% GND to LVDD GND to TVDD GND to BVDD GND to OV DD TA= 0 (min) to TJ= 90(max) TA TJ TA= 0 (min) to TJ= 105 (max) TA= -40 (min) to TJ= 105 (max) °C 6 V V 4 — V 5 V 3 Input voltage DDR2 and DDR3 SDRAM Interface signals DDR2 and DDR3 SDRAM Interface reference Three-speed Ethernet signals Local bus signals PCI, Local bus, DUART, SYSCLK, system control and power management, I2C, and JTAG signals MVIN MVREF LV IN TVIN BVIN OVIN V V V V V 3 — 5 — 4 Operating Temperature range Commercial Industrial standard temperature range Extended temperature range Notes: 2. This voltage is the input to the filter discussed in Section 3.2.1, “PLL Power Supply Filtering,” and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Minimum temperature is specified with TA; maximum temperature is specified with TJ. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23 Overall DC Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8535E. B/G/L/OV DD + 20% B/G/L/OVDD + 5% VIH B/G/L/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tCLOCK1 Note: 1. tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK references SYSCLK. For DDR, tCLOCK references MCLK. For eTSEC, tCLOCK references EC_GTX_CLK125. For eLBC, tCLOCK references LCLK. For PCI, tCLOCK references PCI1_CLK or SYSCLK. 2. With the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3). Figure 7. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD The core voltage must always be provided at nominal 1.0 V (See Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface uses differential receivers referenced by the externally supplied MV REFn signal (nominally set to GVDD/2) as is appropriate for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 24 Freescale Semiconductor Power Sequencing 2.1.3 Output Driver Characteristics Table 4. Output Drive Capability Driver Type Programmable Output Impedance (Ω) 25 35 45(default) 45(default) 125 Supply Voltage BVDD = 3.3 V BVDD = 2.5 V BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V OVDD = 3.3 V GVDD = 1.8 V GVDD = 1.5 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V 2 Notes 1 Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Local bus interface utilities signals PCI signals 25 42 (default) DDR2 signal DDR3 signal TSEC signals DUART, system control, JTAG I2C 16 32 (half strength mode) 20 40 (half strength mode) 42 42 150 3 2 — — — Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI1_GNT1 signal at reset. 3. The drive strength of the DDR2 or DDR3 interface in half-strength mode is at Tj = 105°C and at GVDD (min) 2.2 1. 2. 3. Power Sequencing VDD_PLAT, VDD_CORE (if POWER_EN is not used to control VDD_CORE), AVDD, BVDD, LVDD, OVDD, SVDD,S2V DD, TVDD, XVDD and X2VDD [Wait for POWER_EN to assert], then VDD_CORE (if POWER_EN is used to control VDD_CORE) GVDD The MPC8535E requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up: All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. From a system standpoint, if any of the I/O power supplies ramp prior to the VDD platform supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 25 Power Characteristics 2.3 Power Characteristics Table 5. MPC8535E Power Dissipation 5 The estimated power dissipation for the core complex bus (CCB) versus the core frequency for this family of PowerQUICC III devices is shown in Table 5. Core CCB DDR VDD Frequen Frequen Frequen Platfor Power Mode m cy cy cy (MHz) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) 1000 400 400 1.0 800 400 400 1.0 600 400 400 1.0 (MHz) (MHz) (V) VDD Core (V) Junction Tempera ture (°C) 105 /90 Core Power mean7 — — 1.5 Platform Power9 Notes mean7 — — 1.5 1.4 1.4 1.0 0.6 — — 1.5 1.4 1.4 1.0 0.6 — — 1.5 1.4 1.4 1.0 0.6 Max 4.1/3.3 3.7/2.9 — 1.9 1.5 1.5 0 4.5/3.7 3.9/3.1 — 2.1 1.5 1.5 0 4.8/4.0 4.1/3.3 — 2.2 1.6 1.6 0 Max 4.7/3.7 4.7/3.7 — 1.9 1.9 1.6 1.1 4.7/3.7 4.7/3.7 — 1.9 1.9 1.6 1.1 4.7/3.7 4.7/3.7 — 1.9 1.9 1.6 1.1 1, 3, 8 1, 4, 8 1, 2 1 1 1 6 1, 3, 8 1, 4, 8 1, 2 1 1 1 1,6 1, 3, 8 1, 4, 8 1, 2 1 1 1 1, 6 1.0 65 1.2 0.8 0.8 35 105 / 90 0 — — 1.7 1.0 65 1.3 0.8 0.8 35 105 / 90 0 — — 1.9 1.0 65 1.4 0.8 0.8 35 0 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 26 Freescale Semiconductor Power Characteristics Table 5. MPC8535E Power Dissipation (continued)5 VDD DDR CCB Core Frequen Frequen Frequen Platfor Power Mode cy cy m cy (MHz) Maximum (A) Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) 35 1250 500 500 1.0 1.0 (MHz) (MHz) (V) VDD Core (V) Junction Tempera ture (°C) 105 / 90 65 Core Power mean7 — — 2.2 1.6 0.8 0.8 0 2.4 1.6 1.6 0 Platform Power9 Notes Max 5.3/4.4 4.4/3.6 mean7 — — 1.7 1.5 1.5 1.1 0.6 2.1 2.1 1.7 1.2 Max 5.0/4.0 5.0/4.0 1, 3, 8 1, 4, 8 1 1 1 1 1, 6 Notes: 1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and configurations. The values do not include power dissipation for I/O supplies. 2. Typical power is an average value measured at the nominal recommended core voltage (VDD) and 65°C junction temperature (see Table 3) while running the Dhrystone benchmark. 3. Maximum power is the maximum power measured with the worst process and recommended core and platform voltage (VDD) at maximum operating junction temperature (see Table 3) while running a smoke test which includes an entirely L1-cache-resident, contrived sequence of instructions which keep the execution unit maximally busy. 4. Thermal power is the maximum power measured with worst case process and recommended core and platform voltage (V DD) at maximum operating junction temperature (see Table 3) while running the Dhrystone benchmark. 6. Maximum power is the maximum number measured with USB1, eTSEC1, and DDR blocks enabled. The Mean power is the mean power measured with only external interrupts enabled and DDR in self refresh. 7. Mean power is provided for information purposes only and is the mean power consumed by a statistically significant range of devices. 8. Maximum operating junction temperature (see Table 3) for Commercial Tier is 90 0C, for Industrial Tier is 105 0C. 9. Platform power is the power supplied to all the V DD_PLAT pins. See Section 2.23.6.1, “SYSCLK to Platform Frequency Options,” for the full range of CCB frequencies that MPC8535E supports. MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27 Input Clocks 2.4 2.4.1 Input Clocks System Clock Timing Table 6. SYSCLK AC Timing Specifications Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8535E. At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV. Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHK/tSYSCLK — Min 33 7.5 0.6 40 — Typical — — 1.0 — — Max 133 30 2.1 60 +/-150 Unit MHz ns ns % ps Notes 1 — 2 — 3, 4 Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. The SYSCLK driver’s closed loop jitter bandwidth should be