MPC8540VTAQFB

Freescale Semiconductor Technical Data MPC8540EC Rev. 4, 12/2006 MPC8540 Integrated Processor Hardware Specifications The MPC8540 integrates a PowerPC™ processor core built on Power Architecture™ technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8540 is a member of the PowerQUICC™ III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8540 PowerQUICC™ III Integrated Host Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ethernet: Three-Speed,10/100, MII Management . . 22 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 66 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 System Design Information . . . . . . . . . . . . . . . . . . . 89 Document Revision History . . . . . . . . . . . . . . . . . . . 96 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 101 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. Overview 1 Overview The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major functional units within the MPC8540. DDR SDRAM ROM, SDRAM, GPIO IRQs DDR SDRAM Controller 256KB L2-Cache/ SRAM e500 Coherency Module e500 Core 32 KB L1 I Cache 32 KB L1 D Cache Local Bus Controller Programmable Interrupt Controller Core Complex Bus RapidIO Controller OCeaN MII 10/100 ENET PCI/PCI-X Controller 4ch DMA Controller Serial DUART TSEC I2C I2C Controller TSEC 10/100/1G 10/100/1G RapidIO-8 16 Gb/s PCI-X 64b 133 MHz MII, GMII,TBI, RTBI, RGMII MII, GMII,TBI, RTBI, RGMII Figure 1. MPC8540 Block Diagram 1.1 Key Features The following lists an overview of the MPC8540 feature set. • High-performance, 32-bit Book E–enhanced core that implements the Power Architecture — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data — Memory management unit (MMU) especially designed for embedded applications — Enhanced hardware and software debug support — Performance monitor facility (similar to but different from the MPC8540 performance monitor described in Chapter 18, “Performance Monitor.” MPC8540 Integrated Processor Hardware Specifications, Rev. 4 2 Freescale Semiconductor Overview • • • 256 Kbyte L2 cache/SRAM — Can be configured as follows – Full cache mode (256-Kbyte cache). – Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks) – Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM) — Full ECC support on 64-bit boundary in both cache and SRAM modes — Cache mode supports instruction caching, data caching, or both — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing) — Eight-way set-associative cache organization (1024 sets of 32-byte cache lines) — Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions — Global locking and flash clearing done through writes to L2 configuration registers — Instruction and data locks can be flash cleared separately — Read and write buffering for internal bus accesses — SRAM features include the following: – I/O devices access SRAM regions by marking transactions as snoopable (global) – Regions can reside at any aligned location in the memory map – Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than cache-line accesses. Address translation and mapping unit (ATMU) — Eight local access windows define mapping within local 32-bit address space — Inbound and outbound ATMUs map to larger external address spaces – Three inbound windows plus a configuration window on PCI/PCI-X – Four inbound windows plus a default and configuration window on RapidIO – Four outbound windows plus default translation for PCI – Eight outbound windows plus default translation for RapidIO DDR memory controller — Programmable timing supporting DDR-1 SDRAM — 64-bit data interface, up to 333-MHz data rate — Four banks of memory supported, each up to 1 Gbyte — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full ECC support — Page mode support (up to 16 simultaneous open pages) — Contiguous or discontiguous memory mapping MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 3 Overview • • • — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self refresh SDRAM — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access via JTAG port — 2.5-V SSTL2 compatible I/O RapidIO interface unit — 8-bit RapidIO I/O and messaging protocols — Source-synchronous double data rate (DDR) interfaces — Supports small type systems (small domain, 8-bit device ID) — Supports four priority levels (ordering within a level) — Reordering across priority levels — Maximum data payload of 256 bytes per packet — Packet pacing support at the physical layer — CRC protection for packets — Supports atomic operations increment, decrement, set, and clear — LVDS signaling RapidIO–compliant message unit — One inbound data message structure (inbox) — One outbound data message structure (outbox) — Supports chaining and direct modes in the outbox — Support of up to 16 packets per message — Support of up to 256 bytes per packet and up to 4 Kbytes of data per message — Supports one inbound doorbell message structure Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing MPC8540 Integrated Processor Hardware Specifications, Rev. 4 4 Freescale Semiconductor Overview • • • • • • — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs — Interrupt summary registers allow fast identification of interrupt source I2C controller — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC DUART — Two 4-wire interfaces (SIN, SOUT, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D 10/100 fast Ethernet controller (FEC) — Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance port Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 166 MHz — Eight chip selects support eight external slaves — Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit) Two three-speed (10/100/1Gb) Ethernet controllers (TSECs) — Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support for different Ethernet physical interfaces: – 10/100/1Gb Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII – 10 Mbps IEEE 802.3 MII – 1000 Mbps IEEE 802.3z TBI – 10/100/1Gb Mbps RGMII/RTBI — Full- and half-duplex support MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 5 Overview • • • — Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs — MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache. OCeaN switch fabric — Four-port crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes Integrated DMA controller — Four-channel controller — All channels accessible by both the local and remote masters — Extended DMA functions (advanced chaining and striding capability) — Support for scatter and gather transfers — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no-snoop) — Ability to start and flow control each DMA channel from external 3-pin interface — Ability to launch DMA from single write transaction PCI/PCI-X controller — PCI 2.2 and PCI-X 1.0 compatible — 64- or 32-bit PCI port supports at 16 to 66 MHz — 64-bit PCI-X support up to 133 MHz — Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency MPC8540 Integrated Processor Hardware Specifications, Rev. 4 6 Freescale Semiconductor Electrical Characteristics • • • • • Power management — Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download IEEE 1149.1-compliant, JTAG boundary scan 783 FC-PBGA package 2 Electrical Characteristics This section provides the electrical specifications and thermal characteristics for the MPC8540. The MPC8540 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 7 Electrical Characteristics 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Core supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz PLL supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz DDR DRAM I/O voltage Three-speed Ethernet I/O voltage PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals PCI/PCI-X, Local bus, RapidIO, 10/100 Ethernet, DUART, SYSCLK, system control and power management, I2C, and JTAG signals Storage temperature range Symbol VDD –0.3 to 1.32 –0.3 to 1.43 AVDD –0.3 to 1.32 –0.3 to 1.43 GVDD LVDD OVDD –0.3 to 3.63 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 V V V 3 V Max Value Unit V Notes MVIN MVREF LVIN OVIN –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (OVDD + 0.3) V V V V 2, 5 2, 5 4, 5 5 TSTG –55 to 150 •C Notes: 1.Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2.Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3.Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4.Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5.(M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 8 Freescale Semiconductor Electrical Characteristics 2.1.2 Power Sequencing The MPC8540 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. VDD, AVDD 2. GVDD, LVDD, OVDD (I/O supplies) Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. NOTE If the items on line 2 must precede items on line 1, please ensure that the delay will not exceed 500 ms and the power sequence is not done greater than once per day in production environment. NOTE From a system standpoint, if the I/O power supplies ramp prior to the VDD core supply, the I/Os on the MPC8540 may drive a logic one or zero during power-up. 2.1.3 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8540. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz PLL supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz DDR DRAM I/O voltage Three-speed Ethernet I/O voltage PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage GVDD LVDD OVDD AVDD 1.2 V ± 60 mV 1.3 V ± 50 mV 2.5 V ± 125 mV 3.3 V ± 165 mV 2.5 V ± 125 mV 3.3 V ± 165 mV V V V Symbol VDD 1.2 V ± 60 mV 1.3 V ± 50 mV V Recommended Value Unit V MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 9 Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals Die-junction temperature Symbol MVIN MVREF LVIN OVIN Recommended Value GND to GVDD GND to GVDD/2 GND to LVDD GND to OVDD Unit V V V V Tj 0 to 105 •C Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8540. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tSYS1 Note: tSYS refers to the clock period associated with the SYSCLK signal. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD The MPC8540 core voltage must always be provided at nominal 1.2 V (see Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 10 Freescale Semiconductor Power Characteristics 2.1.4 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Programmable Output Impedance (Ω ) 25 42 (default) PCI signals 25 42 (default) DDR signal TSEC/10/100 signals DUART, system control, I2C, JTAG RapidIO N/A (LVDS signaling) 20 42 42 N/A GVDD = 2.5 V LVDD = 2.5/3.3 V OVDD = 3.3 V 2 Supply Voltage OVDD = 3.3 V Notes Local bus interface utilities signals 1 Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset. 3 Power Characteristics The estimated power dissipation on the VDD supply for the MPC8540 is shown in Table 4. Table 4. MPC8540 VDD Power Dissipation 1,2 CCB Frequency (MHz) 200 Core Typical Power3,4 Frequency (MHz) 400 500 600 267 533 667 800 4.6 4.9 5.3 5.5 5.9 6.4 Maximum Power5 7.2 7.5 7.9 8.2 8.7 10.2 W Unit W MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 11 Power Characteristics Table 4. MPC8540 VDD Power Dissipation 1,2 CCB Frequency (MHz) 333 Core Typical Power3,4 Frequency (MHz) 667 833 1000 6 Maximum Power5 9.3 10.9 15.9 Unit W 6.3 6.9 11.3 Notes: 1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. 2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Any customer design must take these considerations into account to ensure the maximum 105 °C junction temperature is not exceeded on this device. 3. Typical Power is based on a nominal voltage of VDD = 1.2 V, a nominal process, a junction temperature of Tj = 105 °C, and a Dhrystone 2.1 benchmark application. 4. Thermal solutions will likely need to design to a number higher than Typical Power based on the end application, TA target, and I/O power. 5. Maximum power is based on a nominal voltage of VDD = 1.2 V, worst case process, a junction temperature of Tj = 105 °C, and an artificial smoke test. 6. The nominal recommended VDD is 1.3 V for this speed grade. The estimated power dissipation on the AVDD supplies for the MPC8540 PLLs is shown in Table 5. Table 5. MPC8540 AVDD Power Dissipation AVDDn AVDD1 AVDD2 Typical1 0.007 0.014 Unit W W Notes: 1. VDD = 1.2 V (1.3 V for 1.0 GHz device), TJ = 105°C Table 6 provides estimated I/O power numbers for each block: DDR, PCI, Local Bus, RapidIO, TSEC, and FEC. Table 6. Estimated Typical I/O Power Consumption Interface DDR I/O Parameter CCB = 200 MHz CCB = 266 MHz CCB = 300 MHz CCB = 333 MHz GVDD (2.5 V) 0.46 0.59 0.66 0.73 OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Units W Notes 1 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 12 Freescale Semiconductor Power Characteristics Table 6. Estimated Typical I/O Power Consumption (continued) Interface PCI/PCI-X I/O Parameter 32-bit, 33 MHz 32-bit 66 MHz 64-bit, 66 MHz 64-bit, 133 MHz Local Bus I/O 32-bit, 33 MHz 32-bit, 66 MHz 32-bit, 133 MHz 32-bit, 167 MHz RapidIO I/O TSEC I/O 500 MHz data rate MII GMII, TBI (2.5 V) GMII, TBI (3.3 V) RGMII, RTBI FEC I/O MII 10 70 40 mW 7 GVDD (2.5 V) OVDD (3.3 V) 0.04 0.07 0.14 0.25 0.07 0.13 0.24 0.30 0.96 10 40 W mW 4 5, 6 W 3 LVDD (3.3 V) LVDD (2.5 V) Units W Notes 2 Notes: 1. GVDD=2.5, ECC enabled, 66% bus utilization, 33% write cycles, 10pF load on data, 10pF load on address/command, 10pF load on clock 2. OVDD=3.3, 30pF load per pin, 54% bus utilization, 33% write cycles 3. OVDD=3.3, 25pF load per pin, 5pF load on clock, 40% bus utilization, 33% write cycles 4. VDD=1.2, OVDD=3.3 5. LVDD=2.5/3.3, 15pF load per pin, 25% bus utilization 6. Power dissipation for one TSEC only 7. OVDD=3.3, 20pF load per pin, 25% bus utilization MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 13 Clock Timing 4 Clock Timing 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8540. Table 7. SYSCLK AC Timing Specifications Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHKL/tSYSCLK — Min — 6.0 0.6 40 — Typical — — 1.0 — — Max 166 — 1.2 60 +/- 150 Unit MHz ns ns % ps 2 3 4, 5 Notes 1 Notes: 1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation regardless of the input frequency. 4.2 TSEC Gigabit Reference Clock Timing Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the MPC8540. Table 8. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK125 rise and fall time LVDD=2.5 LVDD=3.3 EC_GTX_CLK125 duty cycle GMII, TBI RGMII, RTBI tG125H/tG125 45 47 — 55 53 Symbol fG125 tG125 tG125R, tG125F Min — — — Typical 125 8 — 0.75 1 % 1,3 Max — — Unit MHz ns ns 2 Notes Notes: 1. Timing is guaranteed by design and characterization. 2. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for LVDD=2.5V, and from 0.6 and 2.7V for LVDD=3.3V. 3. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 14 Freescale Semiconductor RESET Initialization 4.3 RapidIO Transmit Clock Input Timing Table 9 provides the RapidIO transmit clock input (RIO_TX_CLK_IN) AC timing specifications for the MPC8540. Table 9. RIO_TX_CLK_IN AC Timing Specifications Parameter/Condition RIO_TX_CLK_IN frequency RIO_TX_CLK_IN cycle time RIO_TX_CLK_IN duty cycle Symbol fRCLK tRCLK tRCLKH/tRCLK Min 125 — 48 Typical — — — Max — 8 52 Unit MHz ns % 1 Notes Notes: 1. Requires ±100 ppm long term frequency stability. Timing is guaranteed by design and characterization. 4.4 Real Time Clock Timing Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8540. Table 10. RTC AC Timing Specifications Parameter/Condition RTC clock high time RTC clock low time Symbol tRTCH tRTCL Min 2x tCCB_CLK 2x tCCB_CLK Typical — — Max — — Unit ns ns Notes 5 RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8540. Table 7 provides the RESET initialization AC timing specifications for the MPC8540. Table 11. RESET Initialization Timing Specifications Parameter/Condition Required assertion time of HRESET Minimum assertion time for SRESET PLL input setup time with stable SYSCLK before HRESET negation Input setup time for POR configs (other than PLL config) with respect to negation of HRESET Input hold time for POR configs (including PLL config) with respect to negation of HRESET Min 100 512 100 4 2 Max — — — — — Unit μs SYSCLKs μs SYSCLKs SYSCLKs 1 1 1 Notes MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 15 DDR SDRAM Table 11. RESET Initialization Timing Specifications (continued) Parameter/Condition Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Min — Max 5 Unit SYSCLKs Notes 1 Notes: 1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8540. See the MPC8540 Integrated Processor Preliminary Reference Manual for more details. Table 12 provides the PLL and DLL lock times. Table 12. PLL and DLL Lock Times Parameter/Condition PLL lock times DLL lock times Min — 7680 Max 100 122,880 Unit μs CCB Clocks 1, 2 Notes Notes: 1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The CCB clock is determined by the SYSCLK × platform PLL ratio. 6 DDR SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8540. 6.1 DDR SDRAM DC Electrical Characteristics Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8540. Table 13. DDR SDRAM DC Electrical Characteristics Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 × GVDD MVREF – 0.04 MVREF + 0.18 –0.3 –10 –15.2 15.2 Max 2.625 0.51 × GVDD MVREF + 0.04 GVDD + 0.3 MVREF – 0.18 10 — — Unit V V V V V μA mA mA Notes 1 2 3 4 4 5 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 16 Freescale Semiconductor DDR SDRAM Table 13. DDR SDRAM DC Electrical Characteristics Parameter/Condition MVREF input leakage current Symbol IVREF Min — Max 100 Unit μA Notes Notes: 1.GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2.MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. 3.VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4.VIH can tolerate an overshoot of 1.2V over GVDD for a pulse width of ≤3 ns, and the pulse width cannot be greater than tMCK. VIL can tolerate an undershoot of 1.2V below GND for a pulse width of ≤3 ns, and the pulse width cannot be greater than tMCK. 5.Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD. Table 14 provides the DDR capacitance. Table 14. DDR SDRAM Capacitance Parameter/Condition Input/output capacitance: DQ, DQS, MSYNC_IN Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1.This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V. 6.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR SDRAM Input AC Timing Specifications Table 15 provides the input AC timing specifications for the DDR SDRAM interface. Table 15. DDR SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of 2.5 V ± 5%. Parameter AC input low voltage AC input high voltage MDQS—MDQ/MECC input skew per byte For DDR = 333 MHz For DDR ≤ 266 MHz Symbol VIL VIH tDISKEW Min — MVREF + 0.31 -750 -1125 Max MVREF – 0.31 GVDD + 0.3 750 1125 Unit V V ps Notes 1, 2 Note: 1.Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n=8). 2.For timing budget analysis, the MPC8540 consumes ±550 ps of the total budget. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 17 DDR SDRAM MDQS[n] MDQ[n] tDISKEW tDISKEW Figure 3. DDR SDRAM Interface Input Timing 6.2.2 DDR SDRAM Output AC Timing Specifications For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of self-refresh after an HRESET before a precharge occurs. This will not necessarily be the case for chip selects MCS0 and MCS3. 6.2.2.1 DLL Enabled Mode Table 16 and Table 17 provide the output AC timing specifications and measurement conditions for the DDR SDRAM interface with the DDR DLL enabled. Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode At recommended operating conditions with GVDD of 2.5 V ± 5%. Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) On chip Clock Skew MCK[n] duty cycle ADDR/CMD output valid ADDR/CMD output invalid Write CMD to first MDQS capture edge MDQ/MECC/MDM output setup with respect to MDQS 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 333 MHz 266 MHz 200 MHz MDQS preamble start Symbol 1 tMCK tMCKSKEW tMCKH/tMCK tDDKHOV tDDKHOX tDDSHMH tDDKHDS, tDDKLDS Min 6 — 45 — 1 tMCK + 1.5 Max 10 150 55 3 — tMCK + 4.0 — Unit ns ps % ns ns ns ps Notes 2 3, 8 8 4, 9 4, 9 5 6, 9 900 1100 1200 tDDKHDX, tDDKLDX 900 1100 1200 tDDSHMP 0.75 × tMCK + 1.5 0.75 × tMCK + 4.0 ns 7, 8 — ps 6, 9 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 18 Freescale Semiconductor DDR SDRAM Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued) At recommended operating conditions with GVDD of 2.5 V ± 5%. Parameter MDQS epilogue end Symbol 1 tDDSHME Min 1.5 Max 4.0 Unit ns Notes 7, 8 Notes: 1.The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (OX or DX). For example, tDDKHOV symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (O) are valid (V) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2.All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3.Maximum possible clock skew between a clock MCK[n] and its relative inverse clock MCK[n], or between a clock MCK[n] and a relative clock MCK[m] or MSYNC_OUT. Skew measured between complementary signals at GVDD/2. 4.ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK and MDQ/MECC/MDM/MDQS. 5.Note that tDDSHMH follows the symbol conventions described in note 1. For example, tDDSHMH describes the DDR timing (DD) from the rising edge of the MSYNC_IN clock (SH) until the MDQS signal is valid (MH). tDDSHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. These controls allow the relationship between the synchronous clock control timing and the source-synchronous DQS domain to be modified by the user. For best turnaround times, these may need to be set to delay tDDSHMH an additional 0.25tMCK. This will also affect tDDSHMP and tDDSHME accordingly. See the MPC8540 PowerQUICC III Integrated Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 6.Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8540. 7.All outputs are referenced to the rising edge of MSYNC_IN (S) at the pins of the MPC8540. Note that tDDSHMP follows the symbol conventions described in note 1. For example, tDDSHMP describes the DDR timing (DD) from the rising edge of the MSYNC_IN clock (SH) for the duration of the MDQS signal precharge period (MP). 8.Guaranteed by design. 9.Guaranteed by characterization. Figure 4 provides the AC test load for the DDR bus. Output Z0 = 50 Ω RL = 50 Ω GVDD/2 Figure 4. DDR AC Test Load Table 17. DDR SDRAM Measurement Conditions Symbol VTH VOUT Notes: 1.Data input threshold measurement point. 2.Data output measurement point. DDR MVREF ± 0.31 V 0.5 × GVDD Unit V V Notes 1 2 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 19 DDR SDRAM Figure 5 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] MSYNC_OUT DLL Phase Alignment MSYNC_IN tDDKHOV tDDKHOX ADDR/CMD Write A0 tDDSHMH MDQS[n] tDDSHMP tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDSHME NOOP tMCK tMCK tMCKH Figure 5. DDR SDRAM Output Timing Diagram 6.2.2.2 Load Effects on Address/Command Bus Table 18 provides approximate delay information that can be expected for the address and command signals of the DDR controller for various loadings. These numbers are the result of simulations for one topology. The delay numbers will strongly depend on the topology used. These delay numbers show the total delay for the address and command to arrive at the DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. Table 18. Expected Delays for Address/Command Load 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF) + 40 pF compensation capacitor 36 devices (108 pF) + 80 pF compensation capacitor Delay 3.0 3.6 5.0 5.2 Unit ns ns ns ns MPC8540 Integrated Processor Hardware Specifications, Rev. 4 20 Freescale Semiconductor DUART 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8540. 7.1 DUART DC Electrical Characteristics Table 19 provides the DC electrical characteristics for the DUART interface of the MPC8540. Table 19. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA OVDD – 0.2 — — V 0.2 V Note: 1.Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 7.2 DUART AC Electrical Specifications Table 20 provides the AC timing parameters for the DUART interface of the MPC8540. Table 20. DUART AC Timing Specifications Parameter Minimum baud rate Maximum baud rate Oversample rate Value fCCB_CLK / 1048576 fCCB_CLK / 16 16 Unit baud baud — Notes 3 1, 3 2, 3 Notes: 1.Actual attainable baud rate will be limited by the latency of interrupt processing. 2.The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 3.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 21 Ethernet: Three-Speed,10/100, MII Management 8 Ethernet: Three-Speed,10/100, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100, and MII management. 8.1 Three-Speed Ethernet Controller (TSEC) (10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII (media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII, MII, and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.4, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 TSEC DC Electrical Characteristics All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 21 and Table 22. The potential applied to the input of a GMII, MII, TBI, RGMII, or RTBI receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from a 3.6 V supply driving VOH into a GMII receiver powered from a 2.5 V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. Table 21. GMII, MII, and TBI DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage (LVDD = Min, IOH = –4.0 mA) Output low voltage (LVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN 1 = LVDD) Input low current (VIN 1 = GND) Symbol LVDD VOH VOL VIH VIL IIH IIL Min 3.13 2.40 Max 3.47 LVDD + 0.3 0.50 Unit V V GND V 1.70 –0.3 — LVDD + 0.3 0.90 40 V V μA μA –600 — Note: 1.The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 22 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management Table 22. GMII, MII, RGMII, RTBI, and TBI DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage (LVDD = Min, IOH = –1.0 mA) Output low voltage (LVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (VIN 1 = LVDD) Input low current (VIN 1 = GND) Symbol LVDD VOH VOL VIH VIL IIH IIL Min 2.37 2.00 Max 2.63 LVDD + 0.3 0.40 Unit V V GND – 0.3 V 1.70 –0.3 — LVDD + 0.3 0.70 10 V V μA μA –15 — Note: 1.Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1and Table 2. 8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.2.1.1 GMII Transmit AC Timing Specifications Table 23. GMII Transmit AC Timing Specifications Table 23 provides the GMII transmit AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay Symbol 1 tGTX tGTXH/tGTX tGTKHDV tGTKHDX 3 Min — 40 2.5 0.5 Typ 8.0 — — — Max — 60 — 5.0 Unit ns % ns ns MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 23 Ethernet: Three-Speed,10/100, MII Management Table 23. GMII Transmit AC Timing Specifications (continued) At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition GTX_CLK data clock rise and fall time Symbol 1 tGTXR, tGTXF 2,4 Min — Typ — Max 1.0 Unit ns Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by characterization. 4.Guaranteed by design. Figure 6 shows the GMII transmit AC timing diagram. tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTKHDV tGTXF tGTXR Figure 6. GMII Transmit AC Timing Diagram 8.2.1.2 GMII Receive AC Timing Specifications Table 24. GMII Receive AC Timing Specifications Table 24 provides the GMII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK Symbol 1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH Min — 40 2.0 0.5 Typ 8.0 — — — Max — 60 — — Unit ns ns ns ns MPC8540 Integrated Processor Hardware Specifications, Rev. 4 24 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management Table 24. GMII Receive AC Timing Specifications (continued) At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition RX_CLK clock rise and fall time Symbol 1 tGRXR, tGRXF 2,3 Min — Typ — Max 1.0 Unit ns Note: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 7 provides the AC test load for TSEC. Output Z0 = 50 Ω RL = 50 Ω LVDD/2 Figure 7. TSEC AC Test Load Figure 8 shows the GMII receive AC timing diagram. tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF tGRXR Figure 8. GMII Receive AC Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 25 Ethernet: Three-Speed,10/100, MII Management 8.2.2 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.2.1 MII Transmit AC Timing Specifications Table 25. MII Transmit AC Timing Specifications Table 25 provides the MII transmit AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise and fall time Symbol 1 tMTX 2 tMTX tMTXH/tMTX tMTKHDX tMTXR, tMTXF 2,3 Min — — 35 1 1.0 Typ 400 40 — 5 — Max — — 65 15 4.0 Unit ns ns % ns ns Note: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 9 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 9. MII Transmit AC Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 26 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management 8.2.2.2 MII Receive AC Timing Specifications Table 26. MII Receive AC Timing Specifications Table 26 provides the MII receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise and fall time Symbol 1 tMRX 3 tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR, tMRXF 2,3 Min — — 35 10.0 10.0 1.0 Typ 400 40 — — — — Max — — 65 — — 4.0 Unit ns ns % ns ns ns Note: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 10 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 10. MII Receive AC Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 27 Ethernet: Three-Speed,10/100, MII Management 8.2.3 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.3.1 TBI Transmit AC Timing Specifications Table 27. TBI Transmit AC Timing Specifications Table 27 provides the TBI transmit AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle TCG[9:0] setup time GTX_CLK going high TCG[9:0] hold time from GTX_CLK going high GTX_CLK clock rise and fall time Symbol 1 tTTX tTTXH/tTTX tTTKHDV tTTKHDX tTTXR, tTTXF 2,3 Min — 40 2.0 1.0 — Typ 8.0 — — — — Max — 60 — — 1.0 Unit ns % ns ns ns Notes: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 11 shows the TBI transmit AC timing diagram. tTTX GTX_CLK tTTXH tTTXF tTTXR TCG[9:0] tTTKHDV tTTKHDX Figure 11. TBI Transmit AC Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 28 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management 8.2.3.2 TBI Receive AC Timing Specifications Table 28. TBI Receive AC Timing Specifications Table 28 provides the TBI receive AC timing specifications. At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%. Parameter/Condition RX_CLK clock period RX_CLK skew RX_CLK duty cycle RCG[9:0] setup time to rising RX_CLK RCG[9:0] hold time to rising RX_CLK RX_CLK clock rise time and fall time Symbol 1 tTRX tSKTRX tTRXH/tTRX tTRDVKH tTRDXKH tTRXR, tTRXF 2,3 Min Typ 16.0 Max Unit ns 7.5 40 2.5 1.5 0.7 — — — — — 8.5 60 — — 2.4 ns % ns ns ns Note: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. Figure 12 shows the TBI receive AC timing diagram. tTRX RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Valid Data Valid Data tTRXR Figure 12. TBI Receive AC Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 29 Ethernet: Three-Speed,10/100, MII Management 8.2.4 RGMII and RTBI AC Timing Specifications Table 29 presents the RGMII and RTBI AC timing specifications. Table 29. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LVDD of 2.5 V ± 5%. Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period3 Duty cycle for 1000Base-T 4 2 Symbol 1 tSKRGT 5 tSKRGT tRGT 6 tRGTH/tRGT 6 Min –500 1.0 7.2 45 40 — Typ 0 — 8.0 50 50 — Max 500 2.8 8.8 55 60 0.75 Unit ps ns ns % % ns Duty cycle for 10BASE-T and 100BASE-TX 3 Rise and fall time tRGTH/tRGT 6 tRGTR, tRGTF 6,7 Notes: 1.Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2.The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to meet this specification. However, as stated above, this device will function with only 1.0 ns of delay. 3.For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4.Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned between. 5.Guaranteed by characterization. 6.Guaranteed by design. 7.Signal timings are measured at 0.5 V and 2.0 V voltage levels. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 30 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management Figure 13 shows the RGMII and RTBI AC timing and multiplexing diagrams. tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TXD[9] TXERR tSKRGT TX_CLK (At PHY) TX_CTL TXD[4] TXEN RXD[8:5][3:0] RXD[7:4][3:0] RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT RX_CTL RX_CLK (At PHY) Figure 13. RGMII and RTBI AC Timing and Multiplexing Diagrams 8.3 10/100 Ethernet Controller (10/100 Mbps)—MII Electrical Characteristics The electrical characteristics specified here apply to the MII (media independent interface) signals except MDIO (management data input/output) and MDC (management data clock). The MII interface can be operated at 3.3 or 2.5 V. Whether the MII interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The electrical characteristics for MDIO and MDC are specified in Section 2.1.3, “Recommended Operating Conditions.” 8.3.1 MII DC Electrical Characteristics All MII drivers and receivers comply with the DC parametric attributes specified in Table 30. The potential applied to the input of a MII receiver may exceed the potential of the receiver’s power supply (that is, a MII driver powered from a 3.6-V supply driving VOH into a MII receiver powered from a 2.5-V supply). Tolerance for dissimilar MII driver and receiver supply potentials is implicit in these specifications. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 31 Ethernet: Three-Speed,10/100, MII Management Table 30. MII DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage (OVDD = Min, IOH = –4.0 mA) Output low voltage (OVDD = Min, IOL = 4.0 mA) Input high voltage Input low voltage Input high current (VIN= OVDD 1) Input low current (VIN= GND 1) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.13 2.40 Max 3.47 OVDD + 0.3 0.50 Unit V V GND V 1.70 –0.3 — — 0.90 40 V V μA μA –600 — Note: 1.Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 8.3.2 MII AC Electrical Specifications This section describes the MII transmit and receive AC specifications. 8.3.2.1 MII Transmit AC Timing Specifications Table 31. MII Transmit AC Timing Specifications Table 31 provides the MII transmit AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise and fall time Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR, tMTXF 2,3 Min — — 35 1 1.0 Typ 400 40 — 5 — Max — — 65 15 4.0 Unit ns ns % ns ns Note: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) from the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII (M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 32 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management Figure 14 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 14. MII Transmit AC Timing Diagram 8.3.2.2 MII Receive AC Timing Specifications Table 32. MII Receive AC Timing Specifications Parameter/Condition Symbol 1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR, tMRXF 2,3 Min — — 35 10.0 10.0 1.0 Typ 400 40 — — — — Max — — 65 — — 4.0 Unit ns ns % ns ns ns Table 32 provides the MII receive AC timing specifications. RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[7:0], TX_DV, TX_ER setup time to RX_CLK RXD[7:0], TX_DV, TX_ER hold time to RX_CLK RX_CLK clock rise and fall time Note: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKH symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the high (H) state or hold time. Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 33 Ethernet: Three-Speed,10/100, MII Management Figure 15 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 15. MII Receive AC Timing Diagram 8.4 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller (TSEC) (10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.” 8.4.1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 33. Table 33. MII Management DC Electrical Characteristics Parameter Supply voltage (3.3 V) Output high voltage (OVDD = Min, IOH = –1.0 mA) Output low voltage (OVDD = Min, IOL = 1.0 mA) Input high voltage Input low voltage Input high current (OVDD = Max, VIN 1 = 2.1 V) Input low current (OVDD = Max, VIN = 0.5 V) Symbol OVDD VOH VOL VIH VIL IIH IIL Min 3.13 2.10 Max 3.47 OVDD + 0.3 0.50 Unit V V GND V 1.70 — — — 0.90 40 V V μA μA –600 — Note: 1.Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 34 Freescale Semiconductor Ethernet: Three-Speed,10/100, MII Management 8.4.2 MII Management AC Electrical Specifications Table 34 provides the MII management AC timing specifications. Table 34. MII Management AC Timing Specifications At recommended operating conditions with OVDD is 3.3 V ± 5%. Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Symbol 1 fMDC tMDC tMDCH tMDKHDV tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min 0.893 96 32 Typ — — — Max 10.4 1120 — 2*[1/(fccb_clk/8)] Unit MHz ns ns ns ns ns ns ns ns Notes 2, 4 3 3 10 5 0 — — — — — — — 2*[1/(fccb_clk/8)] — — 10 10 4 4 Notes: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a CCB clock of 333 MHz, the maximum frequency is 10.4 MHz and the minimum frequency is 1.5 MHz). 3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a CCB clock of 333 MHz, the delay is 48 ns). 4.Guaranteed by design. Figure 16 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDKHDV MDIO (Output) tMDKHDX tMDDXKH tMDCF tMDCR Figure 16. MII Management Interface Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 35 Local Bus 9 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8540. 9.1 Local Bus DC Electrical Characteristics Table 35 provides the DC electrical characteristics for the local bus interface. Table 35. Local Bus DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current (VIN 1 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = –2 mA) Low-level output voltage (OVDD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA OVDD - 0.2 — — V 0.2 V Note: 1.Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 9.2 Local Bus AC Electrical Specifications Table 36 describes the general timing parameters of the local bus interface of the MPC8540 with the DLL enabled. Table 36. Local Bus General Timing Parameters - DLL Enabled Parameter Local bus cycle time LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) POR Configuration Symbol 1 tLBK tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT Min 6.0 — 1.8 1.7 0.5 1.0 1.5 Max — 150 — — — — — Unit ns ps ns ns ns ns ns Notes 2 3, 9 4, 5, 8 4, 5 4, 5, 8 4, 5 6 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 36 Freescale Semiconductor Local Bus Table 36. Local Bus General Timing Parameters - DLL Enabled (continued) Parameter Local bus clock to output valid (except LAD/LDP and LALE) POR Configuration TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) tLBKHOV4 TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) tLBKHOZ2 — tLBKHOZ1 tLBKHOX2 tLBKHOX1 — 0.7 1.6 0.7 1.6 — 2.5 3.8 2.5 3.8 ns 7, 9 ns 7, 9 — ns 4, 8 tLBKHOV3 — tLBKHOV2 — Symbol 1 tLBKHOV1 Min — Max 2.0 3.5 2.2 3.7 2.3 3.8 2.3 — ns ns 4, 8 4, 8 ns 4, 8 ns 4, 8 Unit ns Notes 4, 8 Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Notes: 1.The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2.All timings are in reference to LSYNC_IN for DLL enabled mode. 3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at OVDD/2. 4.All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 5.Input timings are measured at the pin. 6.The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5]. 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8.Guaranteed by characterization. 9.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 37 Local Bus Table 37 describes the general timing parameters of the local bus interface of the MPC8540 with the DLL bypassed. Table 37. Local Bus General Timing Parameters—DLL Bypassed Parameter Local bus cycle time Internal launch/capture clock to LCLK delay LCLK[n] skew to LCLK[m] or LSYNC_OUT Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) Local bus clock to data valid for LAD/LDP TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) Local bus clock to address valid for LAD TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) tLBKLOZ1 tLBKLOX2 tLBKHOV4 tLBKLOX1 — -3.2 -2.3 -3.2 -2.3 — 0.2 1.5 ns 7 — ns 4 tLBKLOV3 — tLBKLOV2 — POR Configuration Symbol 1 tLBK tLBKHKT tLBKSKEW tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT tLBKLOV1 Min 6.0 2.3 — 5.7 5.6 -1.8 -1.3 1.5 — Max — 3.9 150 — — — — — -0.3 1.2 -0.1 1.4 0 1.5 0 — ns ns 4 4 ns 4 ns 4 Unit ns ns ps ns ns ns ns ns ns Notes 2 8 3, 9 4, 5 4, 5 4, 5 4, 5 6 4 Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 38 Freescale Semiconductor Local Bus Table 37. Local Bus General Timing Parameters—DLL Bypassed (continued) Parameter Local bus clock to output high impedance for LAD/LDP POR Configuration TSEC2_TXD[6:5] = 00 TSEC2_TXD[6:5] = 11 (default) Symbol 1 tLBKLOZ2 Min — Max 0.2 1.5 Unit ns Notes 7 Notes: 1.The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2.All timings are in reference to local bus clock for DLL bypass mode. Timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK by tLBKHKT. 3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at OVDD/2. 4.All signals are measured from OVDD/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OVDD of the signal in question for 3.3-V signaling levels. 5.Input timings are measured at the pin. 6.The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5]. 7.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8.Guaranteed by characterization. 9.Guaranteed by design. Figure 17 provides the AC test load for the local bus. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 17. Local Bus AC Test Load MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 39 Local Bus Figure 18 through Figure 23 show the local bus signals. LSYNC_IN tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV3 Output (Address) Signal: LAD[0:31] tLBOTOT tLBKHOV4 LALE tLBKHOZ2 tLBKHOX2 tLBKHOV1 tLBKHOZ1 tLBKHOX1 tLBIXKH2 tLBIXKH1 tLBKHOV2 tLBKHOZ2 tLBKHOX2 Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 40 Freescale Semiconductor Local Bus Internal launch/capture clock tLBKHKT LCLK[n] tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH2 Input Signal: LGTA tLBKLOV1 Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] tLBKLOV2 Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKLOV3 Output (Address) Signal: LAD[0:31] tLBKLOV4 LALE tLBOTOT tLBKLOX2 tLBKLOX1 tLBIXKH2 tLBKLOZ1 tLBIXKH1 tLBKLOZ2 Figure 19. Local Bus Signals (DLL Bypass Mode) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 41 Local Bus LSYNC_IN T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 42 Freescale Semiconductor Local Bus Internal launch/capture clock T1 T3 tLBKHKT LCLK tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKLOX1 tLBKLOZ1 tLBIXKH2 tLBIXKH1 Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 43 Local Bus LSYNC_IN T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBIVKH1 tLBIXKH1 tLBIXKH2 tLBKHOZ1 tLBKHOZ1 Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 44 Freescale Semiconductor Local Bus Internal launch/capture clock T1 T2 T3 T4 tLBKHKT LCLK tLBKLOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKLOX1 tLBKLOZ1 tLBIXKH2 tLBIXKH1 Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode) MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 45 JTAG 10 JTAG This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8540. Table 38 provides the JTAG AC timing specifications as defined in Figure 25 through Figure 28. Table 38. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions (see Table 2). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol 2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV tJTKLDX tJTKLOX Min 0 30 15 0 25 4 0 20 25 4 4 Max 33.3 — — 2 — — — Unit MHz ns ns ns ns ns Notes 6 3 4 ns — — ns 20 25 ns 5 ns tJTKLDZ tJTKLOZ 3 3 19 9 5, 6 5 4 Notes: 1.All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see Figure 24). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3.TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4.Non-JTAG signal input timing with respect to tTCLK. 5.Non-JTAG signal output timing with respect to tTCLK. 6.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 46 Freescale Semiconductor JTAG Figure 24 provides the AC test load for TDO and the boundary-scan outputs of the MPC8540. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 24. AC Test Load for the JTAG Interface Figure 25 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 25. JTAG Clock Input Timing Diagram Figure 26 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM Figure 26. TRST Timing Diagram Figure 27 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 27. Boundary-Scan Timing Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 47 I2C Figure 28 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 28. Test Access Port Timing Diagram 11 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8540. 11.1 I2C DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8540. Table 39. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) Capacitance for each I/O pin Symbol VIH VIL VOL tI2KHKL II CI Min 0.7 × OVDD –0.3 0 0 –10 — Max OVDD+ 0.3 0.3 × OVDD 0.2 × OVDD 50 10 10 Unit V V V ns μA pF Notes 1 2 3 Notes: 1.Output voltage (open drain or open collector) condition = 3 mA sink current. 2.Refer to the MPC8540 Integrated Processor Preliminary Reference Manual for information on the digital filter used. 3.I/O pins will obstruct the SDA and SCL lines if OVDD is switched off. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 48 Freescale Semiconductor I2C 11.2 I2C AC Electrical Specifications Table 40 provides the AC timing parameters for the I2C interface of the MPC8540. Table 40. I2C AC Electrical Specifications All values refer to VIH (min) and VIL (max) levels (see Table 39). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol 1 fI2C tI2CL 6 tI2CH 6 tI2SVKH 6 tI2SXKL 6 tI2DVKH 6 tI2DXKL Min 0 1.3 0.6 0.6 0.6 100 — 02 Max 400 — — — — — — 0.9 3 — — — — Unit kHz μs μs μs μs ns μs tI2PVKH tI2KHDX VNL VNH 0.6 1.3 0.1 × OVDD 0.2 × OVDD μs μs V V Notes: 1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2.MPC8540 provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3.The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4.CB = capacitance of one bus line in pF. 6.Guaranteed by design. Figure 17 provides the AC test load for the I2C. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 29. I2C AC Test Load MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 49 PCI/PCI-X Figure 30 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF Figure 30. I2C Bus AC Timing Diagram 12 PCI/PCI-X This section describes the DC and AC electrical specifications for the PCI/PCI-X bus of the MPC8540. 12.1 PCI/PCI-X DC Electrical Characteristics Table 41 provides the DC electrical characteristics for the PCI/PCI-X interface of the MPC8540. Table 41. PCI/PCI-X DC Electrical Characteristics 1 Parameter High-level input voltage Low-level input voltage Input current (VIN 2 = 0 V or VIN = VDD) High-level output voltage (OVDD = min, IOH = –100 μA) Low-level output voltage (OVDD = min, IOL = 100 μA) Symbol VIH VIL IIN VOH VOL Min 2 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V μA OVDD – 0.2 — — V 0.2 V Notes: 1.Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications. 2.Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 50 Freescale Semiconductor PCI/PCI-X 12.2 PCI/PCI-X AC Electrical Specifications This section describes the general AC timing parameters of the PCI/PCI-X bus of the MPC8540. Note that the SYSCLK signal is used as the PCI input clock. Table 42 provides the PCI AC timing specifications at 66 MHz. Table 42. PCI AC Timing Specifications at 66 MHz Parameter SYSCLK to output valid Output hold from SYSCLK SYSCLK to output high impedance Input setup to SYSCLK Input hold from SYSCLK REQ64 to HRESET 9 setup Symbol 1 tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Min — 2.0 — 3.0 0 10 × tSYS 0 10 Max 6.0 — 14 — — — 50 — Unit ns ns ns ns ns clocks ns clocks Notes 2 2, 9 2, 3, 10 2, 4, 9 2, 4, 9 5, 6, 10 6, 10 7, 10 time tPCRVRH tPCRHRX tPCRHFV HRESET to REQ64 hold time HRESET high to first FRAME assertion Notes: 1.Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2.See the timing measurement conditions in the PCI 2.2 Local Bus Specifications. 3.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4.Input timings are measured at the pin. 5.The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see Section 15, “Clocking.” 6.The setup and hold time is with respect to the rising edge of HRESET. 7.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus Specifications. 8.The reset assertion timing requirement for HRESET is 100 μs. 9.Guaranteed by characterization. 10.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 51 PCI/PCI-X Figure 17 provides the AC test load for PCI and PCI-X. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 31. PCI/PCI-X AC Test Load Figure 32 shows the PCI/PCI-X input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 32. PCI-PCI-X Input AC Timing Measurement Conditions Figure 33 shows the PCI/PCI-X output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output Figure 33. PCI-PCI-X Output AC Timing Measurement Condition Table 43 provides the PCI-X AC timing specifications at 66 MHz. Table 43. PCI-X AC Timing Specifications at 66 MHz Parameter SYSCLK to signal valid delay Output hold from SYSCLK SYSCLK to output high impedance Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion Symbol tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCRVRH tPCRHRX tPCRHFV Min — 0.7 — 1.7 0.5 10 0 10 Max 3.8 — 7 — — — 50 — Unit ns ns ns ns ns clocks ns clocks Notes 1, 2, 3, 7, 8 1, 10 1, 4, 8, 11 3, 5 10 11 11 9, 11 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 52 Freescale Semiconductor PCI/PCI-X Table 43. PCI-X AC Timing Specifications at 66 MHz (continued) Parameter PCI-X initialization pattern to HRESET setup time HRESET to PCI-X initialization pattern hold time Symbol tPCIVRH tPCRHIX Min 10 0 Max — 50 Unit clocks ns Notes 11 6, 11 Notes: 1.See the timing measurement conditions in the PCI-X 1.0a Specification. 2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and load circuit. 3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused. 4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is asserted. 7.A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency. 8.Device must meet this specification independent of how many outputs switch simultaneously. 9.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification. 10.Guaranteed by characterization. 11.Guaranteed by design. Table 44 provides the PCI-X AC timing specifications at 133 MHz. Table 44. PCI-X AC Timing Specifications at 133 MHz Parameter SYSCLK to signal valid delay Output hold from SYSCLK SYSCLK to output high impedance Input setup time to SYSCLK Input hold time from SYSCLK REQ64 to HRESET setup time HRESET to REQ64 hold time HRESET high to first FRAME assertion PCI-X initialization pattern to HRESET setup time Symbol tPCKHOV tPCKHOX tPCKHOZ tPCIVKH tPCIXKH tPCRVRH tPCRHRX tPCRHFV tPCIVRH Min — 0.7 — 1.4 0.5 10 0 10 10 Max 3.8 — 7 — — — 50 — — Unit ns ns ns ns ns clocks ns clocks clocks Notes 1, 2, 3, 7, 8 1, 11 1, 4, 8, 12 3, 5, 9, 11 11 12 12 10, 12 12 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 53 RapidIO Table 44. PCI-X AC Timing Specifications at 133 MHz (continued) Parameter HRESET to PCI-X initialization pattern hold time Symbol tPCRHIX Min 0 Max 50 Unit ns Notes 6, 12 Notes: 1.See the timing measurement conditions in the PCI-X 1.0a Specification. 2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and load circuit. 3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused. 4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is asserted. 7.A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency. 8.Device must meet this specification independent of how many outputs switch simultaneously. 9.The timing parameter tPCIVKH is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a Specification. 10.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification. 11.Guaranteed by characterization. 12.Guaranteed by design. 13 RapidIO This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8540. 13.1 RapidIO DC Electrical Characteristics RapidIO driver and receiver DC electrical characteristics are provided in Table 45 and Table 46, respectively. Table 45. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Characteristic Differential output high voltage Differential output low voltage Differential offset voltage Output high common mode voltage Output low common mode voltage Symbol VOHD VOLD ΔVOSD VOHCM VOLCM Min 247 –454 — 1.125 1.125 Max 454 –247 50 1.375 1.375 Unit mV mV mV V V Notes 1, 2 1, 2 1,3 1, 4 1, 5 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 54 Freescale Semiconductor RapidIO Table 45. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%. Characteristic Common mode offset voltage Differential termination Short circuit current (either output) Bridged short circuit current Symbol ΔVOSCM RTERM |ISS| |ISB| Min — 90 — — Max 50 220 24 12 Unit mV W mA mA Notes 1, 6 7 8 Notes: 1.Bridged 100-Ω load. 2.See Figure 34(a). 3.Differential offset voltage = |VOHD+VOLD|. See Figure 34(b). 4.VOHCM = (VOA + VOB)/2 when measuring VOHD. 5.VOLCM = (VOA + VOB)/2 when measuring VOLD. 6.Common mode offset ΔVOSCM = |VOHCM – VOLCM|. See Figure 34(c). 7.Outputs shorted to VDD or GND. 8.Outputs shorted together. Table 46. RapidIO 8/16 LP-LVDS Receiver DC Electrical Characteristics Characteristic Voltage at either input Differential input high voltage Differential input low voltage Common mode input range (referenced to receiver ground) Input differential resistance Notes: 1.Over the common mode range. 2.Limited by VI. See Figure 41. Symbol VI VIHD VILD VICM RIN Min 0 100 –600 0.050 90 Max 2.4 600 –100 2.350 110 Unit V mV mV V W 1 1 2 Notes MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 55 RapidIO Figure 34 shows the DC driver signal levels. VOA RTERM 100 Ω (no m) VOB VOD = VOA – VOB 454 mV V 247 mV VOHD VOLCM –247 mV VOLD –454 mV Differential Specifications Common-Mode Specifications (c) 0 1.125 V (a) VOSCM = (VOA + VOB)/2 VOHCM 1.375 V ΔVOS V VOD = VOA – VOB –V + ΔVOD –V –V – ΔVOD (b) Note: VOA refers to voltage at output A; VOB refers to voltage at output B. Figure 34. DC Driver Signal Levels 13.2 RapidIO AC Electrical Specifications This section contains the AC electrical specifications for a RapidIO 8/16 LP-LVDS device. The interface defined is a parallel differential low-power high-speed signal interface. Note that the source of the transmit clock on the RapidIO interface is dependent on the settings of the LGPL[0:1] signals at reset. Note that the default setting makes the core complex bus (CCB) clock the source of the transmit clock. See Chapter 4 of the Reference Manual for more details on reset configuration settings. 13.3 RapidIO Concepts and Definitions This section specifies signals using differential voltages. Figure 35 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows: • The transmitter output and receiver input signals TD, TD, RD, and RD each have a peak-to-peak swing of A-B volts. • The differential output signal of the transmitter, VOD, is defined as VTD – VTD. • The differential input signal of the receiver, VID, is defined as VRD – VRD. • The differential output signal of the transmitter or input signal of the receiver, ranges from A – B volts to – (A – B) volts. • The peak differential signal of the transmitter output or receiver input, is A – B volts. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 56 Freescale Semiconductor RapidIO • The peak-to-peak differential signal of the transmitter output or receiver input, is 2 × (A – B) volts. AV BV TD or RD TD or RD Figure 35. Differential Peak-to-Peak Voltage of Transmitter or Receiver To illustrate these definitions using numerical values, consider the case where a LVDS transmitter has a common mode voltage of 1.2 V and each signal has a swing that goes between 1.4 and 1.0 V. Using these values, the peak-to-peak voltage swing of the signals TD, TD, RD, and RD is 400 mV. The differential signal ranges between 400 and –400 mV. The peak differential signal is 400 mV, and the peak-to-peak differential signal is 800 mV. A timing edge is the zero-crossing of a differential signal. Each skew timing parameter on a parallel bus is synchronously measured on two signals relative to each other in the same cycle, such as data to data, data to clock, or clock to clock. A skew timing parameter may be relative to the edge of a signal or to the middle of two sequential edges. Static skew represents the timing difference between signals that does not vary over time regardless of system activity or data pattern. Path length differences are a primary source of static skew. Dynamic skew represents the amount of timing difference between signals that is dependent on the activity of other signals and varies over time. Crosstalk between signals is a source of dynamic skew. Eye diagrams and compliance masks are a useful way to visualize and specify driver and receiver performance. This technique is used in several serial bus specifications. An example compliance mask is shown in Figure 36. The key difference in the application of this technique for a parallel bus is that the data is source synchronous to its bus clock while serial data is referenced to its embedded clock. Eye diagrams reveal the quality (cleanness, openness, goodness) of a driver output or receiver input. An advantage of using an eye diagram and a compliance mask is that it allows specifying the quality of a signal without requiring separate specifications for effects such as rise time, duty cycle distortion, data dependent dynamic skew, random dynamic skew, etc. This allows the individual semiconductor manufacturer maximum flexibility to trade off various performance criteria while keeping the system performance constant. In using the eye pattern and compliance mask approach, the quality of the signal is specified by the compliance mask. The mask specifies the maximum permissible magnitude of the signal and the minimum permissible eye opening. The eye diagram for the signal under test is generated according to the specification. Compliance is determined by whether the compliance mask can be positioned over the eye diagram such that the eye pattern falls entirely within the unshaded portion of the mask. Serial specifications have clock encoded with the data, but the LP-LVDS physical layer defined by RapidIO is a source synchronous parallel port so additional specifications to include effects that are not found in serial links are required. Specifications for the effect of bit to bit timing differences caused by static skew have been added and the eye diagrams specified are measured relative to the associated clock in order to include clock to data effects. With the transmit output (or receiver input) eye diagram, the user can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the appropriate software. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 57 RapidIO Z Differential (V) Y 0 –Y DV –Z 0 X1 X2 1–X2 1–X1 1 Time (UI) Figure 36. Example Compliance Mask Y = minimum data valid amplitude Z = maximum amplitude 1 UI = 1 unit interval = 1/baud rate X1 = end of zero crossing region X2 = beginning of data valid window DV = data valid window = 1 – 2 × X2 The waveform of the signal under test must fall within the unshaded area of the mask to be compliant. Different masks are used for the driver output and the receiver input allowing each to be separately specified. 13.3.1 RapidIO Driver AC Timing Specifications Driver AC timing specifications are provided in Table 47, Table 48, and Table 49. A driver shall comply with the specifications for each data rate/frequency for which operation of the driver is specified. Unless otherwise specified, these specifications are subject to the following conditions. • The specifications apply over the supply voltage and ambient temperature ranges specified by the device vendor. • The specifications apply for any combination of data patterns on the data signals. • The output of a driver shall be connected to a 100 Ω, ±1%, differential (bridged) resistive load. • Clock specifications apply only to clock signals. • Data specifications apply only to data signals (FRAME, D[0:7]). Table 47. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate Range Characteristic Symbol Min Differential output high voltage Differential output low voltage VOHD VOLD 200 –540 Max 540 –200 mV mV 1 1 Unit Notes MPC8540 Integrated Processor Hardware Specifications, Rev. 4 58 Freescale Semiconductor RapidIO Table 47. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate (continued) Range Characteristic Symbol Min Duty cycle VOD rise time, 20%–80% of peak-to-peak differential signal swing VOD fall time, 20%–80% of peak-to-peak differential signal swing Data valid Skew of any two data outputs Skew of single data outputs to associated clock DC tFALL tRISE DV tDPAIR tSKEW,PAIR 48 200 200 1260 — –180 Max 52 — — — 180 180 % ps ps ps ps ps 4, 6 5, 6 2, 6 3, 6 6 Unit Notes Notes: 1.See Figure 37. 2.Requires ±100 ppm long term frequency stability. 3.Measured at VOD = 0 V. 4.Measured using the RapidIO transmit mask shown in Figure 37. 5.See Figure 42. 6.Guaranteed by design. Table 48. RapidIO Driver AC Timing Specifications—750 Mbps Data Rate Range Characteristic Symbol Min Differential output high voltage Differential output low voltage Duty cycle VOD rise time, 20%–80% of peak-to-peak differential signal swing VOD fall time, 20%–80% of peak-to-peak differential signal swing Data valid Skew of any two data outputs Skew of single data outputs to associated clock VOHD VOLD DC tFALL tRISE DV tDPAIR tSKEW,PAIR 200 –540 48 133 133 800 — –133 Max 540 –200 52 — — — 133 133 mV mV % ps ps ps ps ps 1 1 2, 6 3, 6 6 6 4, 6 5, 6 Unit Notes Notes: 1.See Figure 37. 2.Requires ±100 ppm long term frequency stability. 3.Measured at VOD = 0 V. 4.Measured using the RapidIO transmit mask shown in Figure 37. 5.See Figure 42. 6.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 59 RapidIO Table 49. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate Range Characteristic Symbol Min Differential output high voltage Differential output low voltage Duty cycle VOD rise time, 20%–80% of peak to peak differential signal swing VOD fall time, 20%–80% of peak to peak differential signal swing Data valid Skew of any two data outputs Skew of single data outputs to associated clock VOHD VOLD DC tFALL tRISE DV tDPAIR tSKEW,PAIR 200 –540 48 100 100 575 — –100 Max 540 –200 52 — — — 100 100 mV mV % ps ps ps ps ps 1 1 2, 6 3, 6 6 6 4, 6 5, 6 Unit Notes Notes: 1.See Figure 37. 2.Requires ±100 ppm long term frequency stability. 3.Measured at VOD = 0 V. 4.Measured using the RapidIO transmit mask shown in Figure 37. 5.See Figure 42. 6.Guaranteed by design. The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window (DV) specification shall be determined by generating an eye pattern for each of the data signals and comparing the eye pattern of each data signal with the RapidIO transmit mask shown in Figure 37. The value of X2 used to construct the mask shall be (1 – DVmin)/2. A signal is compliant with the data valid window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye pattern falls entirely within the unshaded portion of the mask. VOHDmax VOHDmin VOD (mV) 0 VOLDmax DV VOLDmin 0 X2 1–X2 1 Time (UI) Figure 37. RapidIO Transmit Mask MPC8540 Integrated Processor Hardware Specifications, Rev. 4 60 Freescale Semiconductor RapidIO The eye pattern for a data signal is generated by making a large number of recordings of the signal and then overlaying the recordings. The number of recordings used to generate the eye shall be large enough that further increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies with the RapidIO transmit mask to one that does not. Each data signal in the interface shall be carrying random or pseudo-random data when the recordings are made. If pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long enough that increasing the length of the sequence does not cause the resulting eye pattern to change from one that complies with the RapidIO transmit mask to one that does not comply with the mask. The data carried by any given data signal in the interface may not be correlated with the data carried by any other data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as the timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid. While the method used to make the recordings and overlay them to form the eye pattern is not specified, the method used shall be demonstrably equivalent to the following method. The signal under test is repeatedly recorded with a digital oscilloscope in infinite persistence mode. Each recording is triggered by a zero-crossing of the clock associated with the data signal under test. Roughly half of the recordings are triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock zero-crossings. Each recording is at least 1.9 UI in length (to ensure that at least one complete eye is formed) and begins 0.5 UI before the trigger point (0.5 UI before the associated clock zero-crossing). Depending on the length of the individual recordings used to generate the eye pattern, one or more complete eyes will be formed. Regardless of the number of eyes, the eye whose center is immediately to the right of the trigger point is the eye used for compliance testing. An example of an eye pattern generated using the above method with recordings 3 UI in length is shown in Figure 38. In this example, there is no skew between the signal under test and the associated clock used to trigger the recordings. If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. . 0.5 UI 1.0 UI 1.0 UI + VOD 0 – Oscilloscope (Recording) Trigger Point Eye Used for Compliance Testing Eye Pattern Figure 38. Example Driver Output Eye Pattern MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 61 RapidIO 13.3.2 RapidIO Receiver AC Timing Specifications The RapidIO receiver AC timing specifications are provided in Table 50. A receiver shall comply with the specifications for each data rate/frequency for which operation of the receiver is specified. Unless otherwise specified, these specifications are subject to the following conditions. • The specifications apply over the supply voltage and ambient temperature ranges specified by the device vendor. • The specifications apply for any combination of data patterns on the data signals. • The specifications apply over the receiver common mode and differential input voltage ranges. • Clock specifications apply only to clock signals. • Data specifications apply only to data signals (FRAME, D[0:7]) Table 50. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate Range Characteristic Symbol Min Duty cycle of the clock input Data valid Allowable static skew between any two data inputs within a 8-/9-bit group Allowable static skew of data inputs to associated clock DC DV tDPAIR tSKEW,PAIR 47 1080 — –300 380 300 Max 53 % ps ps ps 1, 5 2 3 4 Unit Notes Notes: 1.Measured at VID = 0 V. 2.Measured using the RapidIO receive mask shown in Figure 39. 3.See Figure 42. 4.See Figure 41 and Figure 42. 5.Guaranteed by design. Table 51. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate Range Characteristic Symbol Min Duty cycle of the clock input Data valid Allowable static skew between any two data inputs within a 8-/9-bit group Allowable static skew of data inputs to associated clock DC DV tDPAIR tSKEW,PAIR 47 600 — –267 Max 53 — 400 267 % ps ps ps 1, 5 2 3 4 Unit Notes Notes: 1.Measured at VID = 0 V. 2.Measured using the RapidIO receive mask shown in Figure 39. 3.See Figure 42. 4.See Figure 41 and Figure 42. 5.Guaranteed by design. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 62 Freescale Semiconductor RapidIO Table 52. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate Range Characteristic Symbol Min Duty cycle of the clock input Data valid Allowable static skew between any two data inputs within a 8-/9-bit group Allowable static skew of data inputs to associated clock DC DV tDPAIR tSKEW,PAIR 47 425 — –200 Max 53 — 300 200 % ps ps ps 1, 5 2 3 4 Unit Notes Notes: 1.Measured at VID = 0 V. 2.Measured using the RapidIO receive mask shown in Figure 39. 3.See Figure 42. 4.See Figure 41 and Figure 42. 5.Guaranteed by design. The compliance of receiver input signals RD[0:15] and RFRAME with their minimum data valid window (DV) specification shall be determined by generating an eye pattern for each of the data signals and comparing the eye pattern of each data signal with the RapidIO receive mask shown in Figure 39. The value of X2 used to construct the mask shall be (1 – DVmin)/2. The ±100 mV minimum data valid and ±600 mV maximum input voltage values are from the DC specification. A signal is compliant with the data valid window specification if and only if the receive mask can be positioned on the signal’s eye pattern such that the eye pattern falls entirely within the unshaded portion of the mask. 600 100 VID (mV) 0 –100 DV –600 0 X2 1–X2 1 Time (UI) Figure 39. RapidIO Receive Mask The eye pattern for a data signal is generated by making a large number of recordings of the signal and then overlaying the recordings. The number of recordings used to generate the eye shall be large enough that further increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies with the RapidIO receive mask to one that does not. Each data signal in the interface shall be carrying random or pseudo-random data when the recordings are made. If pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 63 RapidIO enough that increasing the length of the sequence does not cause the resulting eye pattern to change from one that complies with the RapidIO receive mask to one that does not comply with the mask. The data carried by any given data signal in the interface may not be correlated with the data carried by any other data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as the timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid. While the method used to make the recordings and overlay them to form the eye pattern is not specified, the method used shall be demonstrably equivalent to the following method. The signal under test is repeatedly recorded with a digital oscilloscope in infinite persistence mode. Each recording is triggered by a zero-crossing of the clock associated with the data signal under test. Roughly half of the recordings are triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock zero-crossings. Each recording is at least 1.9 UI in length (to ensure that at least one complete eye is formed) and begins 0.5 UI before the trigger point (0.5 UI before the associated clock zero-crossing). Depending on the length of the individual recordings used to generate the eye pattern, one or more complete eyes will be formed. Regardless of the number of eyes, the eye whose center is immediately to the right of the trigger point is the eye used for compliance testing. An example of an eye pattern generated using the above method with recordings 3 UI in length is shown in Figure 40. In this example, there is no skew between the signal under test and the associated clock used to trigger the recordings. If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. 0.5 UI 1.0 UI 1.0 UI + VID 0 – Oscilloscope (Recording) Trigger Point Eye Used for Compliance Testing Eye Pattern Figure 40. Example Receiver Input Eye Pattern MPC8540 Integrated Processor Hardware Specifications, Rev. 4 64 Freescale Semiconductor RapidIO Figure 41 shows the definitions of the data to clock static skew parameter tSKEW,PAIR and the data valid window parameter DV. The data and frame bits are those that are associated with the clock. The figure applies for all zero-crossings of the clock. All of the signals are differential signals. VD represents VOD for the transmitter and VID for the receiver. The center of the eye is defined as the midpoint of the region in which the magnitude of the signal voltage is greater than or equal to the minimum DV voltage. VD Clock x 1.0 UI Nominal 0.5 UI VD Clock x tSKEW,PAIR 0.5 DV D[0:7]/D[8:15], FRAME 0.5 DV VHDmim VHDmim VD = 0 V VD = 0 V Eye Opening DV Figure 41. Data to Clock Skew Figure 42 shows the definition of the data to data static skew parameter tDPAIR and how the skew parameters are applied. Center Point for Clock CLK0 (CLK1) 1.0 UI Nominal 0.5 UI Center point of the data valid window of the earliest allowed data bit for data grouped late with respect to clock D[0:7]/D[8:15], FRAME Center point of the data valid window of the latest allowed data bit for data grouped late with respect to clock tDPAIR tSKEW,PAIR Figure 42. Static Skew Diagram MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 65 Package and Pin Listings 14 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. 14.1 Package Parameters for the MPC8540 FC-PBGA The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783 flip chip plastic ball grid array (FC-PBGA). Die size 12.2 mm × 9.5 mm Package outline 29 mm × 29 mm Interconnects 783 Pitch 1 mm Minimum module height 3.07 mm Maximum module height 3.75 mm Solder Balls 62 Sn/36 Pb/2 Ag Ball diameter (typical) 0.5 mm 14.2 Mechanical Dimensions of the MPC8540 FC-PBGA Figure 43 the mechanical dimensions and bottom surface nomenclature of the MPC8540, 783 FC-PBGA package. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 66 Freescale Semiconductor Package and Pin Listings Figure 43. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8540 FC-PBGA NOTES 1. 2. 3. 4. 5. All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Capacitors may not be present on all devices. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 67 Package and Pin Listings 6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. The socket lid must always be oriented to A1. 14.3 Pinout Listings Table 53 provides the pin-out listing for the MPC8540, 783 FC-PBGA package. Table 53. MPC8540 Pinout Listing Signal Package Pin Number PCI/PCI-X PCI_AD[63:0] AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14, V15, W15, Y15, AA15, AB15, AC15, AD15, AG15, AH15, V16, W16, AB16, AC16, AD16, AE16, AF16, V17, W17, Y17, AA17, AB17, AE17, AF17, AF18, AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9, AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11, AG11, AH11, V12, W12, Y12, AB12, AD12, AE12, AG12, AH12, V13, Y13, AB13, AC13 AG13, AH13, V14, W14, AH8, AB10, AD11, AC12 AA11 Y14 AC10 AG10 AD10 V11 AH10 AA9 AE13 AD13 W11 Y11 AF5 AF3, AE4, AG4, AE5 AE6 AG5, AH5, AF6, AG6 I/O OVDD 17 Pin Type Power Supply Notes PCI_C_BE[7:0] PCI_PAR PCI_PAR64 PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_REQ64 PCI_ACK64 PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ[1:4] PCI_GNT[0] PCI_GNT[1:4] I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I/O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 17 2 2 2 2 2 5, 10 2 2 2, 4 5, 9 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 68 Freescale Semiconductor Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal Package Pin Number DDR SDRAM Memory Interface MDQ[0:63] M26, L27, L22, K24, M24, M23, K27, K26, K22, J28, F26, E27, J26, J23, H26, G26, C26, E25, C24, E23, D26, C25, A24, D23, B23, F22, J21, G21, G22, D22, H21, E21, N18, J18, D18, L17, M18, L18, C18, A18, K17, K16, C16, B16, G17, L16, A16, L15, G15, E15, C14, K13, C15, D15, E14, D14, D13, E13, D12, A11, F13, H13, A13, B12 N20, M20, L19, E19, C21, A21, G19, A19 L24, H28, F24, L21, E18, E16, G14, B13, M19 L26, J25, D25, A22, H18, F16, F14, C13, C20 B18, B19 N19, B21, F21, K21, M21, C23, A23, B24, H23, G24, K19, B25, D27, J14, J13 D17 F17 J16 H16, G16, J15, H15 E26, E28 J20, H25, A15, D20, F28, K14 F20, G27, B15, E20, F27, L14 M28 N28 Local Bus Controller Interface LA[27] LA[28:31] LAD[0:31] U18 T18, T19, T20, T21 AD26, AD27, AD28, AC26, AC27, AC28, AA22, AA23, AA26, Y21, Y22, Y26, W20, W22, W26, V19, T22, R24, R23, R22, R21, R18, P26, P25, P20, P19, P18, N22, N23, N24, N25, N26 V21 V20 U23 U27, U28, V18 Y27, Y28, W27, W28, R27 R28 O O I/O OVDD OVDD OVDD 5, 9 7, 9 I/O GVDD Pin Type Power Supply Notes MECC[0:7] MDM[0:8] MDQS[0:8] MBA[0:1] MA[0:14] MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MSYNC_IN MSYNC_OUT I/O O I/O O O O O O O O O O I O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD 11 LALE LBCTL LCKE LCLK[0:2] LCS[0:4] LCS5/DMA_DREQ2 O O O O O I/O OVDD OVDD OVDD OVDD OVDD OVDD 8, 9 9 18 1 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 69 Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LDP[0:3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/ LPBSE LGPL5 LSYNC_IN LSYNC_OUT P27 P28 AA27, AA28, T26, P21 U19 U22 V28 V27 V23 V22 T27 T28 Package Pin Number Pin Type O O I/O O O O O I/O O I O O O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 1, 5, 9 1, 5, 9 5, 9 5, 9 8, 9 5, 9 22 5, 9 Notes 1 1 LWE[0:1]/LSDDQM[0:1]/LBS AB28, AB27 [0:1] LWE[2:3]/LSDDQM[2:3]/LBS T23, P24 [2:3] DMA DMA_DREQ[0:1] DMA_DACK[0:1] DMA_DDONE[0:1] H5, G4 H6, G5 H7, G6 DUART UART_SIN[0:1] UART_SOUT[0:1] UART_CTS[0:1] UART_RTS[0:1] AE2, AD5 AE3, AD2 U9, U7 AD6, AD1 Programmable Interrupt Controller MCP UDE IRQ[0:7] IRQ8 IRQ9/DMA_DREQ3 IRQ10/DMA_DACK3 IRQ11/DMA_DDONE3 AG17 AG16 AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25 AB20 Y20 AF26 AH24 I O O OVDD OVDD OVDD I O I O OVDD OVDD OVDD OVDD I I I I I I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD 9 1 1 1 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 70 Freescale Semiconductor Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal IRQ_OUT AB21 Ethernet Management Interface EC_MDC EC_MDIO F1 E1 Gigabit Reference Clock EC_GTX_CLK125 E2 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_TXD[7:4] TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER TSEC1_TX_CLK TSEC1_GTX_CLK TSEC1_CRS TSEC1_COL TSEC1_RXD[7:0] TSEC1_RX_DV TSEC1_RX_ER TSEC1_RX_CLK A6, F7, D7, C7 B7, A7, G8, E8 C8 B8 C6 B6 C3 G7 D4, B4, D3, D5, B5, A5, F6, E6 D2 E5 D6 Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:2] TSEC2_TXD[1:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK TSEC2_CRS TSEC2_COL TSEC2_RXD[7:0] TSEC2_RX_DV TSEC2_RX_ER B10, A10, J10, K11,J11, H11 G11, E11 B11 D11 D10 C10 D9 F8 F9, E9, C9, B9, A9, H9, G10, F10 H8 A8 O O O O I O I I I I I LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD 18 11 5, 9 O O O O I O I I I I I I LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD LVDD 18 5, 9 9, 19 11 I LVDD O I/O OVDD OVDD 5, 9 Package Pin Number Pin Type O Power Supply OVDD Notes 2, 4 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 71 Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal TSEC2_RX_CLK E10 10/100 Ethernet (MII) Interface FEC_TXD[3:0] FEC_TX_EN FEC_TX_ER FEC_TX_CLK FEC_CRS FEC_COL FEC_RXD[3:0] FEC_RX_DV FEC_RX_ER FEC_RX_CLK M1, N1, N4, N5 P11 P10 V6 N10 N11 N9, N8, N7, N6 P8 P9 V9 RapidIO Interface RIO_RCLK RIO_RCLK RIO_RD[0:7] RIO_RD[0:7] RIO_RFRAME RIO_RFRAME RIO_TCLK RIO_TCLK RIO_TD[0:7] RIO_TD[0:7] RIO_TFRAME RIO_TFRAME RIO_TX_CLK_IN RIO_TX_CLK_IN Y25 Y24 T25, U25, V25, W25, AA25, AB25, AC25, AD25 T24, U24, V24, W24, AA24, AB24, AC24, AD24 AE27 AE26 AC20 AE21 AE18, AC18, AD19, AE20, AD21, AE22, AC22, AD23 AD18, AE19, AC19, AD20, AC21, AD22, AE23, AC23 AE24 AE25 AF24 AF25 I2C interface IIC_SDA IIC_SCL AH22 AH23 I/O I/O OVDD OVDD 4, 20 4, 20 I I I I I I O O O O O O I I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 11 11 O O O I I I I I I I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Package Pin Number Pin Type I Power Supply LVDD Notes MPC8540 Integrated Processor Hardware Specifications, Rev. 4 72 Freescale Semiconductor Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal Package Pin Number System Control HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT AH16 AG20 AF20 M11 G1 Debug TRIG_IN TRIG_OUT/READY MSRCID[0:1] MSRCID[2:4] MDVAL N12 G2 J9, G3 F3, F5, F2 F4 Clock SYSCLK RTC CLK_OUT AH21 AB23 AF22 JTAG TCK TDI TDO TMS TRST AF21 AG21 AF19 AF23 AG23 DFT LSSD_MODE L1_TSTCLK L2_TSTCLK TEST_SEL AG19 AB22 AG22 AH20 Thermal Management THERM0 THERM1 AG2 AH3 I I — — 14 14 I I I I OVDD OVDD OVDD OVDD 21 21 21 3 I I O I I OVDD OVDD OVDD OVDD OVDD 12 11 12 12 I I O OVDD OVDD OVDD 11 I O O O O OVDD OVDD OVDD OVDD OVDD 6, 9, 19 5, 6, 9 6 6 I O I I O OVDD OVDD OVDD OVDD OVDD 2, 4 Pin Type Power Supply Notes MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 73 Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal Package Pin Number Power Management ASLEEP AG18 Power and Ground Signals AVDD1 AVDD2 GND AH19 AH18 A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17, C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9, G12, G25, H4, H12, H14, H17, H20, H22, H27, J19, J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12, M14, M16, M22, M27, N2, N13, N15, N17, P12, P14, P16, P23, R13, R15, R17, R20, R26, T3, T8, T10, T12, T14, T16, U6, U13, U15, U16, U17, U21, V7, V10, V26, W5, W18, W23, Y8, Y16, AA6, AA13, AB4, AB11, AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4, AF10, AF13, AF15, AF27, AG3, AG7, AG26 A14, A20, A25, A26, A27, A28, B17, B22, B28, C12, C28, D16, D19, D21, D24, D28, E17, E22, F12, F15, F19, F25, G13, G18, G20, G23, G28, H19, H24, J12, J17, J22, J27, K15, K20, K25, L13, L23, L28, M25, N21 A4, C5, E7, H10 Power for e500 PLL (1.2 V) Power for CCB PLL (1.2 V) — AVDD1 AVDD2 — I/O 9, 19 Pin Type Power Supply Notes GVDD Power for DDR DRAM I/O Voltage (2.5 V) GVDD LVDD Reference Voltage; Three-Speed Ethernet I/O (2.5 V, 3.3 V) Reference Voltage Signal; DDR — LVDD MVREF No Connects N27 AH26, AH27, AH28, AG28, AF28, AE28, AH1, AG1, AH2, B1, B2, A2, A3, AH25, H1, H2, J1, J2, J3, J4, J5, J6, J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8, L9, L10, L11, M10, M9, M8, M7, M6, M3, M2, P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, T9, T6, T5, T4, T1, U1, U2, U3, U4, U8, U10, V5, V4, V3, V2, V1, W1, W2, W3, W6, W7, W8, W9, Y1, Y2, Y3, Y4, Y5, Y6, Y9, AA8, AA7, AA4, AA3, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4, AC3, AC2, AC1 MVREF — 16 OVDD D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, PCI/PCI-X, T2, T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, RapidIO, 10/100 Y23, AA5, AA12, AA16, AA20, AB7, AB9, AB26, Ethernet, and other AC5, AC11, AC17, AD4, AE1, AE8, AE10, AE15, Standard AF7, AF12, AG27, AH4 (3.3 V) OVDD MPC8540 Integrated Processor Hardware Specifications, Rev. 4 74 Freescale Semiconductor Package and Pin Listings Table 53. MPC8540 Pinout Listing (continued) Signal RESERVED SENSEVDD SENSEVSS VDD Package Pin Number C1, T11, U11, AF1 L12 K12 M13, M15, M17, N14, N16, P13, P15, P17, R12, R14, R16, T13, T15, T17, U12, U14, AH17 Pin Type — Power for Core (1.2 V) — Power for Core (1.2 V) Power Supply — VDD — VDD Notes 15 13 13 Notes: 1.All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2. 2.Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD. 3.This pin must always be tied to GND. . 4.This pin is an open drain signal. 5.This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8540 is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended to be high during reset. 6.Treat these pins as no connects (NC) unless using debug address functionality. 7.The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See Section 15.2, “Platform/System PLL Ratio.” 8.The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.” 9.Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan. 10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit PCI device. Refer to the PCI Specification. 11.This output is actively driven during reset rather than being three-stated during reset. 12.These JTAG pins have weak internal pull-up P-FETs that are always enabled. 13.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking and regulation. 14.Internal thermally sensitive resistor. 15.No connections should be made to these pins. 16.These pins are not connected for any functional use. 17.PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OVDD when using 64-bit buffer mode (pins PCI_AD[63:32] and PCI_C_BE[7:4]). 18.Note that these signals are POR configurations for Rev. 1.x and notes 5 and 9 apply to these signals in Rev. 1.x but not in later revisions. 19 If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a logic –1 state during reset. 20.Recommend a pull-up resistor (~1 KΩ) b placed on this pin to OVDD. 21.These are test signals for factory use only and must be pulled up (100 Ω - 1 kΩ) to OVDD for normal machine operation. 22.If this signal is used as both an input and an output, a weak pull-up (~10 kΩ) is required on this pin. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 75 Clocking 15 Clocking This section describes the PLL configuration of the MPC8540. Note that the platform clock is identical to the CCB clock. 15.1 Clock Ranges Table 54 provides the clocking specifications for the processor core and Table 55 provides the clocking specifications for the memory bus. Table 54. Processor Core Clocking Specifications Maximum Processor Core Frequency Characteristic 667 MHz Min e500 core processor frequency 400 Max 667 833 MHz Min 400 Max 833 Min 400 1 GHz Max 1000 MHz 1, 2, 3 Unit Notes Notes: 1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings. 2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz. 3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage. Table 55. Memory Bus Clocking Specifications Maximum Processor Core Frequency Characteristic 667 MHz Min Memory bus frequency 100 Max 166 833 MHz Min 100 Max 166 Min 100 1 GHz Max 166 MHz 1, 2, 3 Unit Notes Notes: 1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings. 2.The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency. 3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 76 Freescale Semiconductor Clocking 15.2 Platform/System PLL Ratio The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on LA[28:31] at power up, as shown in Table 56. There is no default for this PLL ratio; these signals must be pulled to the desired values. Table 56. CCB Clock Ratio Binary Value of LA[28:31] Signals 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Ratio Description 16:1 ratio CCB clock: SYSCLK (PCI bus) Reserved 2:1 ratio CCB clock: SYSCLK (PCI bus) 3:1 ratio CCB clock: SYSCLK (PCI bus) 4:1 ratio CCB clock: SYSCLK (PCI bus) 5:1 ratio CCB clock: SYSCLK (PCI bus) 6:1 ratio CCB clock: SYSCLK (PCI bus) Reserved 8:1 ratio CCB clock: SYSCLK (PCI bus) 9:1 ratio CCB clock: SYSCLK (PCI bus) 10:1 ratio CCB clock: SYSCLK (PCI bus) Reserved 12:1 ratio CCB clock: SYSCLK (PCI bus) Reserved Reserved Reserved 15.3 e500 Core PLL Ratio Table 57 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 57. Table 57. e500 Core to CCB Ratio Binary Value of LALE, LGPL2 Signals 00 01 10 11 Ratio Description 2:1 e500 core:CCB 5:2 e500 core:CCB 3:1 e500 core:CCB 7:2 e500 core:CCB MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 77 Clocking 15.4 Frequency Options Table 58 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK ratio in comparison to the memory bus speed. Table 58. Frequency Options with Respect to Memory Bus Speeds CCB to SYSCLK Ratio 16.67 25 33.33 41.63 SYSCLK (MHz) 66.67 83 100 111 133.33 Platform/CCB Frequency (MHz) 2 3 4 5 6 8 9 10 12 16 200 267 200 225 250 300 200 267 300 333 208 250 333 200 267 333 250 333 200 300 222 333 267 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 78 Freescale Semiconductor Thermal 16 Thermal This section describes the thermal specifications of the MPC8540. 16.1 Thermal Characteristics Table 59 provides the package thermal characteristics for the MPC8540. Table 59. Package Thermal Characteristics Characteristic Junction-to-ambient Natural Convection on four layer board (2s2p) Junction-to-ambient (@100 ft/min or 0.5 m/s) on four layer board (2s2p) Junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal Symbol RθJMA RθJMA RθJMA RθJB RθJC Value 16 14 12 7.5 0.8 Unit °C/W °C/W •C/W •C/W •C/W Notes 1, 2 1, 2 1, 2 3 4 Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2. Per JEDEC JESD51-6 with the board horizontal. 3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the interface layer. 16.2 Thermal Management Information This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in Figure 44. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 79 Thermal FC-PBGA Package Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Lid Die Printed-Circuit Board Figure 44. Package Exploded Cross-Sectional View with Several Heat Sink Options The system board designer can choose between several types of heat sinks to place on the MPC8540. There are several commercially-available heat sinks from the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-millennium.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 80 Freescale Semiconductor Thermal Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the MPC8540 to function in various environments. 16.2.1 Recommended Thermal Model For system thermal modeling, the MPC8540 thermal model is shown in Figure 45. Five cuboids are used to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block 29x29x1.47 mm with the conductivity adjusted accordingly. For modeling, the planar dimensions of the die are rounded to the nearest mm, so the die is modeled as 10x12 mm at a thickness of 0.76 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and substrate assuming a conductivity of 0.6 in-plane and 1.9 W/m•K in the thickness dimension of 0.76 mm. The lid attach adhesive is also modeled as a collapsed resistance with dimensions of 10x12x0.050 mm and the conductivity of 1 W/m•K. The nickel plated copper lid is modeled as 12x14x1 mm. Note that the die and lid are not centered on the substrate; there is a 1.5 mm offset documented in the case outline drawing in Figure 43. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 81 Thermal Conductivity Value Unit Lid (12 × 14 × 1 mm) kx ky kz 360 360 360 z W/(m × K) Lid Die Substrate and solder balls Side View of Model (Not to Scale) Adhesive Bump/underfill Lid Adhesive—Collapsed resistance (10 × 12 × 0.050 mm) kx ky kz Die (10 × 12 × 0.76 mm) 1 1 1 x Substrate Bump/Underfill—Collapsed resistance (10 × 12 × 0.070 mm) kx ky kz 0.6 0.6 1.9 y Top View of Model (Not to Scale) Heat Source Substrate and Solder Balls (29 × 29 × 1.47 mm) kx ky kz 10.2 10.2 1.6 Figure 45. MPC8540 Thermal Model 16.2.2 Internal Package Conduction Resistance For the packaging technology, shown in Table 59, the intrinsic internal conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance • The die junction-to-board thermal resistance Figure 46 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 82 Freescale Semiconductor Thermal External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance) Figure 46. Package with Heat Sink Mounted to a Printed-Circuit Board The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the lid, then through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 16.2.3 Thermal Interface Materials A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 47 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 44). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink, the heat sink should be slowly removed. Heating the heat sink to 40-50•C with an air gun can soften the interface material and make the removal easier. The use of an adhesive for heat sink attach is not recommended. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 83 Thermal 2 Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 47. Thermal Performance of Select Thermal Interface Materials The system board designer can choose between several types of thermal interface. There are several commercially-available thermal interfaces provided by the following vendors: Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 781-935-4850 800-248-2481 888-642-7674 800-347-4572 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 84 Freescale Semiconductor Thermal Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 888-246-9050 16.2.4 Heat Sink Selection Examples The following section provides a heat sink selection example using one of the commercially available heat sinks. 16.2.4.1 Case 1 For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: TJ = TI + TR + (θJC + θINT + θSA) × PD where TJ is the die-junction temperature TI is the inlet cabinet ambient temperature TR is the air temperature rise within the computer cabinet θJC is the junction-to-case thermal resistance θINT is the adhesive or interface material thermal resistance θSA is the heat sink base-to-ambient thermal resistance PD is the power dissipated by the device During operation the die-junction temperatures (TJ) should be maintained within the range specified in Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (TA) may range from 30° to 40°C. The air temperature rise within a cabinet (TR) may be in the range of 5° to 10°C. The thermal resistance of some thermal interface material (θINT) may be about 1°C/W. Assuming a TI of 30 C, a TR of 5 C, a FC-PBGA package θJC = 0.8, and a power consumption (PD) of 7.0 W, the following expression for TJ is obtained: Die-junction temperature: TJ = 30°C + 5°C + (0.8°C/W + 1.0°C/W + θSA) × 7.0 W The heat sink-to-ambient thermal resistance (θSA) versus airflow velocity for a Thermalloy heat sink #2328B is shown in Figure 48. Assuming an air velocity of 2 m/s, we have an effective θSA+ of about 3.3 C/W, thus TJ = 30 C + 5 C + (0.8 C/W +1.0 C/W + 3.3 C/W) × 7.0 W, resulting in a die-junction temperature of approximately 71 C which is well within the maximum operating temperature of the component. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 85 Thermal 8 7 Heat Sink Thermal Resistance (°C/W) Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Figure 48. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity 16.2.4.2 Case 2 Every system application has different conditions that the thermal management solution must solve. As an alternate example, assume that the air reaching the component is 85 C with an approach velocity of 1 m/sec. For a maximum junction temperature of 105 C at 7 W, the total thermal resistance of junction to case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than 2.8 C/W. The value of the junction to case thermal resistance in Table 59 includes the thermal interface resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be less than 2 C/W. Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in Figure 49 and Figure 50. This design has several significant advantages: • The heat sink is clipped to a plastic frame attached to the application board with screws or plastic inserts at the corners away from the primary signal routing areas. • The heat sink clip is designed to apply the force holding the heat sink in place directly above the die at a maximum force of less than 10 lbs. • For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 86 Freescale Semiconductor Thermal The spring mounting should be designed to apply the force only directly above the die. By localizing the force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the package. Figure 49 and Figure 50 provide exploded views of the plastic fence, heat sink, and spring clip. Figure 49. Exploded Views (1) of a Heat Sink Attachment using a Plastic Force MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 87 Thermal Figure 50. Exploded Views (2) of a Heat Sink Attachment using a Plastic Fence The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system level design and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junction temperature: airflow, board population (local heat flux of adjacent components), system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 88 Freescale Semiconductor System Design Information 17 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8540. 17.1 System Clocking The MPC8540includes two PLLs. 1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 15.2, “Platform/System PLL Ratio.” 2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and the platform clock is selected using the e500 PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio.” 17.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 and AVDD2, respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide three independent filter circuits as illustrated in Figure 51, one to each of the three AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias. Figure 51 shows the PLL power supply filter circuit. 10 Ω VDD 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors AVDD (or L2AVDD) GND Figure 51. PLL Power Supply Filter Circuit MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 89 System Design Information 17.3 Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8540 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8540 system, and the MPC8540 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the MPC8540. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON). 17.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the MPC8540. 17.5 Output Buffer DC Impedance The MPC8540 drivers are characterized over process, voltage, and temperature. There are two driver types: a push-pull single-ended driver (open drain for I2C) for all buses except RapidIO, and a current-steering differential driver for the RapidIO port. To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 52). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 90 Freescale Semiconductor System Design Information OVDD RN SW2 Data Pad SW1 RP OGND Figure 52. Driver Impedance Measurement The output impedance of the RapidIO port drivers targets 200-Ω differential resistance. The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = 1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1/V2 – 1). The drive current is then Isource = V1/Rsource. Table 60 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105°C. Table 60. Impedance Characteristics Local Bus, Ethernet, DUART, Control, Configuration, Power Management 43 Target 43 Target NA Impedance PCI/PCI-X DDR DRAM RapidIO Symbol Unit RN RP Differential 25 Target 25 Target NA 20 Target 20 Target NA NA NA 200 Target Z0 Z0 ZDIFF W W W Note: Nominal supply voltages. See Table 1, Tj = 105°C. 17.6 Configuration Pin Muxing The MPC8540 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 91 System Design Information While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices. 17.7 Pull-Up Resistor Requirements The MPC8540 requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins including EPIC interrupt pins. I2C open drain type pins should be pulled up with ~1 kΩ resistors. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 54. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong enough to restore these signals to a logical 1 during reset. Three test pins also require pull-up resistors (100 Ω - 1 kΩ). These pins are L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine operation. Refer to the PCI 2.2 specification for all pull-ups required for PCI. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 92 Freescale Semiconductor System Design Information 17.8 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1 specification, but is provided on all processors that implement the Power Architecture. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 53 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 53, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 53 is common to all known emulators. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 93 System Design Information COP_TDO COP_TDI NC COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CHKSTP_OUT 1 3 5 7 9 11 13 15 2 4 6 8 10 12 KEY No pin 16 NC COP_TRST COP_VDD_SENSE COP_CHKSTP_IN NC NC GND Figure 53. COP Connector Physical Pinout 17.8.1 Termination of Unused Signals If the JTAG interface and COP header will not be used, Freescale recommends the following connections: • TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 54. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. • Tie TCK to OVDD through a 10 kΩ resistor. This will prevent TCK from changing state and reading incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 94 Freescale Semiconductor System Design Information OVDD SRESET HRESET 10 kΩ 10 kΩ SRESET 6 HRESET1 From Target Board Sources (if any) 13 11 COP_HRESET COP_SRESET 10 kΩ 10 kΩ 5 10 kΩ 10 kΩ TRST1 1 3 5 7 9 11 2 4 6 8 10 12 4 6 5 COP Header 15 14 3 COP_TRST COP_VDD_SENSE2 NC COP_CHKSTP_OUT 10 kΩ 10 kΩ COP_CHKSTP_IN 10 Ω CKSTP_OUT KEY 13 No pin 8 COP_TMS 9 COP_TDO COP_TDI COP_TCK 7 2 10 12 16 NC NC 4 CKSTP_IN TMS TDO TDI 10 kΩ TCK 15 16 COP Connector Physical Pinout 1 3 Notes: 1. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. 6. Asserting SRESET causes a machine check interrupt to the e500 core. Figure 54. JTAG Interface Connection MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 95 Document Revision History 18 Document Revision History Table 61 provides a revision history for this hardware specification. Table 61. Document Revision History Rev. No. 4 3.5 3.4 Substantive Change(s) Updated Note in Section 2.1.2, “Power Sequencing.” Updated back page information. Updated Section 2.1.2, “Power Sequencing.” Replaced Section 17.8, “JTAG Configuration Signals.” Corrected MVREF Max Value in Table 1. Corrected MVREF Max Value in Table 2. Added new revision level information to Table 62 Updated MVREF Max Value in Table 1. Removed Figure 3. In Table 4, replaced TBD with power numbers and added footnote. Updated specs and footnotes in Table 8. Corrected max number for MVREF in Table 13. Changed parameter “Clock cycle duration” to “Clock period” in Table 29. Added note 4 to tLBKHOV1 and removed LALE reference from tLBKHOV3 in Table 36 and Table 37. Updated LALE signal in Figure 18 and Figure 19. Modified Figure 22. Modified Figure 54. 3.3 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 96 Freescale Semiconductor Document Revision History Table 61. Document Revision History (continued) Rev. No. 3.2 Substantive Change(s) Updated Table 1 and Table 2 with 1.0 GHz device parameter requirements. Added Section 2.1.2, “Power Sequencing”. Updated Table 4 with Maximum power data. Updated Table 4 and Table 5 with 1 GHz speed grade information. Updated Table 6 with corrected typical I/O power numbers. Updated Table 7 Note 2 lower voltage measurement point. Replaced Table 7 Note 5 with spread spectrum clocking guidelines. Added to Table 8 rise and fall time information. Added Section 4.4, “Real Time Clock Timing”. Added precharge information to Section 6.2.2, “DDR SDRAM Output AC Timing Specifications”. Updated Table 20 minimum and maximum baud rates. Removed VIL and VIH references from Table 23, Table 24, Table 25, and Table 26. Added reference level note to Table 23, Table 24, Table 25, Table 26, Table 27, Table 28, and Table 29. Updated TXD references to TCG in Section 8.2.3.1, “TBI Transmit AC Timing Specifications”. Updated PMA_RX_CLK references to RX_CLK in Section 8.2.3.2, “TBI Receive AC Timing Specifications”. Updated tTTKHDX value in Table 27. Updated RXD references to RCG in Section 8.2.3.2, “TBI Receive AC Timing Specifications”. Updated Table 29 Note 2. Removed VIL and VIH references from Table 31, and Table 32. Added reference level note to Table 31, and Table 32. Corrected Figure 14 and Figure 15. Corrected Table 34 fMDC and tMDC to reflect the correct minimum operating frequency. Updated Table 34 tMDKHDV and tMDKHDX values for clarification. Added tLBKHKT and updated Note 2 in Table 37. Corrected LGTA timing references in Figure 18. Updated Figure 19, Figure 21, and Figure 23. Updated Figure 43. Clarified Table 53 Note 5. Updated Table 54 and Table 55 with 1 GHz information. Added heat sink removal discussion to Section 16.2.3, “Thermal Interface Materials”. Corrected and added 1 GHz part number to Table 62. Updated Table 4 and Table 5. Added Table 6. Added MCK duty cycle to Table 16. Updated fMDC, tMDC, tMDKHDV, and tMDKHDX parameters in Table 34. Added LALE to tLBKHOV3 parameter in Table 36 and Table 37, and updated Figure 18 and Figure 19. Corrected active level designations of some of the pins in Table 53. Updated Table 62. 3.1 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 97 Document Revision History Table 61. Document Revision History (continued) Rev. No. 3.0 Substantive Change(s) Table 1—Corrected MII management voltage reference Section 2.1.3—New Table 2—Corrected MII management voltage reference Table 4—Added VDD power table Table 5—Added AVDD power table Table 7—New Table 8—New Table 9—New Table 13—Added overshoot/undershoot note. Figure 3—New Table 16—Restated tMCKSKEW1 as tMCKSKEW, removed tMCKSKEW2; added speed-specific minimum values for 333, 266, and 200 MHz; updated tDDSHME values. Updated chapter to reflect that GMII, MII and TBI can be run with 2.5V signalling. Table 34—Added MDIO output valid timing Table 36—Updated tLBIVKH1, tLBIXKH1, and tLBOTOT. Table 37—New Table 19, Table 21, Table 23—Updated clock reference Table 44—Updated tPCIVKH Section 14.1— Changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75 Table 53.—Updated MII management voltage reference and added note 20. Section 16.2.4.1—Changed θJC from 0.3 to 0.8; changed die-junction temperature from 67 to 71 Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...” MPC8540 Integrated Processor Hardware Specifications, Rev. 4 98 Freescale Semiconductor Document Revision History Table 61. Document Revision History (continued) Rev. No. 2.0 Substantive Change(s) Section 1.1—Updated features list to coincide with latest version of the reference manual Table 1 and Table 2—Addition of SYSCLK to OVIN Table 2—Addition of notes 1 and 2 Table 3—Addition of note 1 Table 5—New Section 4—New Table 13—Addition of IVREF Removed Figure 4 DDR SRAM Input TIming Diagram Table 15—Modified maximum values for tDISKEW Table 16—Added MSYNC_OUT to tMCKSKEW2 Figure 4—New Section 6.2.1—Removed Figure 4, “DDR SDRAM Input Timing Diagram” Section 8.1—Removed references to 2.5 V from first paragraph Figure 7—New Table 21 and Table 22—Modified “conditions” for IIH and I IL Table 23—Addition of min and max for GTX_CLK125 reference clock duty cycle Table 27 —Addition of min and max for GTX_CLK125 reference clock duty cycle Table 29—Addition of min and max for GTX_CLK125 reference clock duty cycle Table 30—VOH min and conditions; IIH and I IL conditions Table 31—Min and max for tMTXR and tMTXF Table 32—Min and max for tMRXR and tMRXF Figure 22 and Figure 23—Changed LSYNC_IN to Internal clock at top of each figure Figure 17—New Figure 17—New Table 36—Removed row for tLBKHOX3 Table 43—New (AC timing of PCI-X at 66 MHz) Table 53—Addition of note 19 Figure 54—Addition of jumper and note at top of diagram Table 55: Changed max bus freq for 667 core to 166 Section 16.2.1—Modified first paragraph Figure 45—Modified Figure 46—New Table 59—Modified thermal resistance data Section 16.2.4.2—Modified first and second paragraphs MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 99 Document Revision History Table 61. Document Revision History (continued) Rev. No. 1.2 Substantive Change(s) Section 1.1.1—Updated feature list. Section 1.2.1.1—Updated notes for Table 1. Section 1.2.1.2—Removed 5-V PCI interface overshoot and undershoot figure. Section 1.2.1.3—Added this section to summarize impedance driver settings for various interfaces. Section 1.4—Updated rows in Reset Initialization timing specifications table. Added a table with DLL and PLL timing specifications. Section 1.5.2.2—Updated note 6 of DDR SDRAM Output AC Timing Specifications table. Section 1.7—Changed the minimum input low current from -600 to -15 μA for the RGMII DC electrical characteristics. Section 1.8.2—Changed LCS[3:4] to TSEC1_TXD[6:5] in. Updated notes regarding LCS[3:4]. Section 1.13.2—Updated the mechanical dimensions diagram for the package. Section 1.13.3—Updated the notes for LBCTL, TRIG_OUT, and ASLEEP. Corrected pin assignments for IIC_SDA and IIC_SCL. Corrected reserved pin assignment of V11 to U11. V11 is actually PCI_STOP. Section 1.14.1—Updated the table for frequency options with respect to platform/CCB frequencies. Section 1.14.4—Edited Frequency options with respect to memory bus speeds. Section 1.6.1—Added symbols and note for the GTX_CLK125 timing parameters. Section 1.11.3—Updated pin list table: LGPL5/LSDAMUX to LGPL5, LA[27:29] and LA[30:31] to LA[27:31], FEC_TXD[0:3] to FEC_TXD[3:0], FEC_RXD[0:3] to FEC_RXD[3:0], TRST to TRST, added GBE Clocking section and EC_GTX_CLK125 signal. Updated thermal model information to match current offering. Original Customer Version. 1.1 1 MPC8540 Integrated Processor Hardware Specifications, Rev. 4 100 Freescale Semiconductor Device Nomenclature 19 Device Nomenclature Ordering information for the parts fully covered by this specification document is provided in Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.” 19.1 Nomenclature of Parts Fully Addressed by this Document Table 62 provides the Freescale part numbering nomenclature for the MPC8540. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. Table 62. Part Numbering Nomenclature MPC Product Code MPC nnnn Part Identifier 8540 t Temperature Range1 Blank = 0 to 105°C C = –40 to 105°C pp Package 2 ff(f) Processor Frequency 3, 4 c Platform Frequency L = 333 MHz J = 266 MHz r Revision Level B = Rev. 2.0 (SVR = 0x80300020) C = Rev. 2.1 (SVR = 0x80300021) B = Rev. 2.0 (SVR = 0x80300020) C = Rev. 2.1 (SVR = 0x80300021) PX = FC-PBGA 833 = 833 MHz VT = FC-PBGA 667 = 667 MHz (Pb-free) MPC 8540 Blank = 0 to 105°C C = –40 to 105°C PX = FC-PBGA AQ = 1.0 GHz VT = FC-PBGA (Pb-free) F = 333 MHz Notes: 1.For Temperature Range=C, Processor Frequency is limited to 667 MHz. 2.See Section 14, “Package and Pin Listings,” for more information on available package types. 3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. The core must be clocked at a minimum frequency of 400MHz. A device must not be used beyond the core frequency or platform frequency indicated on the device. 4.Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. A lower maximum power value should not be assumed for design purposes even when running at a lower frequency. MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 101 Device Nomenclature 19.2 Part Marking Parts are marked as the example shown in Figure 55. MPCnnnntppfffcr MPC85nn ATWLYYWWA xPXxxxn MMMMM ATWLYYWWA MMMMM CCCCC YWWLAZ CCCCC Notes: MMMMM is the 5-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. YWWLAZ is the assembly traceability code. 85xx FC-PBGA Figure 55. Part Marking for FC-PBGA Device MPC8540 Integrated Processor Hardware Specifications, Rev. 4 102 Freescale Semiconductor Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK MPC8540 Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 103 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. The PowerPC name is a trademark of IBM Corp. and is used under license. The described product is a PowerPC microprocessor. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. Document Number: MPC8540EC Rev. 4 12/2006