MPC8560

Freescale Semiconductor Technical Data MPC8540EC Rev. 3.1, 12/2004 MPC8560 Integrated Processor Hardware Specifications The MPC8560 contains a PowerPC™ processor core. The MPC8560 integrates a processor that implements the PowerPC architecture with system logic required for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8560 PowerQUICC III™ Integrated Communications Processor Preliminary Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet: Three-Speed, MII Management . . . . . . . . 25 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 72 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 System Design Information . . . . . . . . . . . . . . . . . . . 96 Document Revision History . . . . . . . . . . . . . . . . . . 102 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 105 1 Overview The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major functional units within the MPC8560. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. © Freescale Semiconductor, Inc., 2004. All rights reserved. Overview DDR SDRAM DDR SDRAM Controller I2C Controller 256KB L2-Cache/ SRAM e500 Coherency Module e500 Core 32 KB L1 I Cache 32 KB L1 D Cache GPIO 32b IRQs Local Bus Controller Programmable Interrupt Controller Serial DMA ROM I-Memory Core Complex Bus CPM RapidIO Controller OCeaN PCI Controller DMA Controller MPHY UTOPIAs TC - Layer Time Slot Assigner Time Slot Assigner RapidIO-8 16 Gb/s PCI 64b 133 MHz MCC MCC FCC FCC FCC SCC SCC SCC SCC SPI I2C Serial Interfaces MIIs, RMIIs TDMs I/Os DPRAM RISC Engine Parallel I/O Baud Rate Generators Timers CPM Interrupt Controller 10/100/1000 MAC 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs Figure 1. MPC8560 Block Diagram 1.1 Key Features The following lists an overview of the MPC8560 feature set. • High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data — Memory management unit (MMU) especially designed for embedded applications — Enhanced hardware and software debug support — Performance monitor facility (similar to but different from the MPC8560 performance monitor described in Chapter 18, “Performance Monitor.” High-performance RISC CPM operating at up to 333 MHz — CPM software compatibility with previous PowerQUICC families — One instruction per clock — Executes code from internal ROM or instruction RAM — 32-bit RISC architecture — Tuned for communication environments: instruction set supports CRC computation and bit manipulation. — Internal timer • MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 2 Freescale Semiconductor Overview • — Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller — Handles serial protocols and virtual DMA. — Three full-duplex fast serial communications controllers (FCCs) that support the following protocols: – ATM protocol through UTOPIA interface (FCC1 and FCC2 only) – IEEE802.3/Fast Ethernet – HDLC – Totally transparent operation — Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces — Four full-duplex serial communications controllers (SCCs) that support the following protocols: – High level/synchronous data link control (HDLC/SDLC) – LocalTalk (HDLC-based local area network protocol) – Universal asynchronous receiver transmitter (UART) – Synchronous UART (1x clock mode) – Binary synchronous communication (BISYNC) – Totally transparent operation — Serial peripheral interface (SPI) support for master or slave — I2C bus controller — Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats: – T1/CEPT lines – T3/E3 – Pulse code modulation (PCM) highway interface – ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers — General-purpose parallel ports—16 parallel I/O lines with interrupt capability — Supports inverse muxing of ATM cells (IMA) 256 Kbyte L2 cache/SRAM — Can be configured as follows – Full cache mode (256-Kbyte cache). – Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks) – Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM) — Full ECC support on 64-bit boundary in both cache and SRAM modes MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 3 Overview • • • — Cache mode supports instruction caching, data caching, or both — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing) — Eight-way set-associative cache organization (1024 sets of 32-byte cache lines) — Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions — Global locking and flash clearing done through writes to L2 configuration registers — Instruction and data locks can be flash cleared separately — Read and write buffering for internal bus accesses — SRAM features include the following: – I/O devices access SRAM regions by marking transactions as snoopable (global) – Regions can reside at any aligned location in the memory map – Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than cache-line accesses. Address translation and mapping unit (ATMU) — Eight local access windows define mapping within local 32-bit address space — Inbound and outbound ATMUs map to larger external address spaces – Three inbound windows plus a configuration window on PCI/PCI-X – Four inbound windows plus a default and configuration window on RapidIO – Four outbound windows plus default translation for PCI – Eight outbound windows plus default translation for RapidIO DDR memory controller — Programmable timing supporting DDR-1 SDRAM — 64-bit data interface, up to 333-MHz data rate — Four banks of memory supported, each up to 1 Gbyte — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full ECC support — Page mode support (up to 16 simultaneous open pages) — Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self refresh SDRAM — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access via JTAG port — 2.5-V SSTL2 compatible I/O RapidIO interface unit — 8-bit RapidIO I/O and messaging protocols — Source-synchronous double data rate (DDR) interfaces — Supports small type systems (small domain, 8-bit device ID) MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 4 Freescale Semiconductor Overview • • • • • — Supports four priority levels (ordering within a level) — Reordering across priority levels — Maximum data payload of 256 bytes per packet — Packet pacing support at the physical layer — CRC protection for packets — Supports atomic operations increment, decrement, set, and clear — LVDS signaling RapidIO–compliant message unit — One inbound data message structure (inbox) — One outbound data message structure (outbox) — Supports chaining and direct modes in the outbox — Support of up to 16 packets per message — Support of up to 256 bytes per packet and up to 4 Kbytes of data per message — Supports one inbound doorbell message structure Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs — Interrupt summary registers allow fast identification of interrupt source I2C controller — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 166 MHz — Eight chip selects support eight external slaves MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 5 Overview • • • — Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit) Two three-speed (10/100/1Gb) Ethernet controllers (TSECs) — Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support for different Ethernet physical interfaces: – 10/100/1Gb Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII – 10 Mbps IEEE 802.3 MII – 1000 Mbps IEEE 802.3z TBI – 10/100/1Gb Mbps RGMII/RTBI — Full- and half-duplex support — Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs — MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache. OCeaN switch fabric — Four-port crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes Integrated DMA controller — Four-channel controller — All channels accessible by both the local and remote masters — Extended DMA functions (advanced chaining and striding capability) — Support for scatter and gather transfers — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no-snoop) MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 6 Freescale Semiconductor Overview • • • • • • — Ability to start and flow control each DMA channel from external 3-pin interface — Ability to launch DMA from single write transaction PCI/PCI-X controller — PCI 2.2 and PCI-X 1.0 compatible — 64- or 32-bit PCI port supports at 16 to 66 MHz — 64-bit PCI-X support up to 133 MHz — Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency Power management — Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle. System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download IEEE 1149.1-compliant, JTAG boundary scan 783 FC-PBGA package MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 7 Electrical Characteristics 2 Electrical Characteristics This section provides the electrical specifications and thermal characteristics for the MPC8560. The MPC8560 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 8 Freescale Semiconductor Electrical Characteristics 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Core supply voltage For devices rated at 667 and 833 MHz PLL supply voltage For devices rated at 667 and 833 MHz DDR DRAM I/O voltage Three-speed Ethernet I/O voltage CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII management, DUART, system control and power management, I2C, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals CPM, Local bus, RapidIO, 10/100 Ethernet, SYSCLK, system control and power management, I2C, and JTAG signals PCI/PCI-X Storage temperature range GVDD LVDD OVDD Symbol VDD –0.3 to 1.32 AVDD –0.3 to 1.32 –0.3 to 3.63 –0.3 to 3.63 –0.3 to 2.75 –0.3 to 3.63 V V V 3 V Max Value Unit V Notes MVIN MVREF LVIN OVIN –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (LVDD + 0.3) –0.3 to (OVDD + 0.3) V V V V 2, 5 2, 5 4, 5 5 OVIN TSTG –0.3 to (OVDD + 0.3) –55 to 150 V °C 6 Notes: 1.Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2.Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3.Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4.Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5.(M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 9 Electrical Characteristics 2.1.2 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8560. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage For devices rated at 667 and 833 MHz PLL supply voltage For devices rated at 667 and 833 MHz DDR DRAM I/O voltage Three-speed Ethernet I/O voltage CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, system control and power management, I2C, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management, DUART, SYSCLK, system control and power management, I2C, and JTAG signals Die-junction temperature GVDD LVDD OVDD AVDD 1.2 V ± 60 mV 2.5 V ± 125 mV 3.3 V ± 165 mV 2.5 V ± 125 mV 3.3 V ± 165 mV V V V Symbol VDD 1.2 V ± 60 mV V Recommende d Value Unit V MVIN MVREF LVIN OVIN GND to GVDD GND to GVDD GND to LVDD GND to OVDD V V V V Tj 0 to 105 °C MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 10 Freescale Semiconductor Electrical Characteristics Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560. G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tSYS1 Note: 1. Note that tSYS refers to the clock period associated with the SYSCLK signal. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD The MPC8560 core voltage must always be provided at nominal 1.2 V (see Table 2 for actual recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard. Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8560 for the 3.3-V signals, respectively. 11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform –3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min) 4 ns (Max) Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 11 Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 3. Output Drive Capability Driver Type Programmable Output Impedance (Ω ) 25 42 (default) PCI signals 25 42 (default) DDR signal TSEC/10/100 signals DUART, system control, I2C, JTAG RapidIO N/A (LVDS signaling) 20 42 42 N/A GVDD = 2.5 V LVDD = 2.5/3.3 V OVDD = 3.3 V 2 Supply Voltage OVDD = 3.3 V Notes Local bus interface utilities signals 1 Notes: 1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset. MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 12 Freescale Semiconductor Power Characteristics 3 Power Characteristics Table 4. MPC8560 VDD Power Dissipation CCB Frequency 200 Core Frequency 400 500 600 700 267 533 667 800 300 600 750 333 667 833 Notes: 1. VDD = 1.2 V, TA = 70°C, TJ = 105°C Typical1 5.1 5.4 5.8 6.1 6.0 6.4 6.9 6.4 6.9 6.8 7.4 W W W Unit W The estimated power dissipation on the VDD supply for the MPC8560 is shown in Table 4. The estimated power dissipation on the AVDD supplies for the MPC8560 PLLs is shown in Table 5. Table 5. MPC8560 AVDD Power Dissipation AVDDn AVDD1 AVDD2 AVDD3 Typical1 0.007 0.014 0.004 Unit W W W Notes: 1. VDD = 1.2 V, TA = 70°C, TJ = 105°C MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 13 Power Characteristics Table 6 provides estimated I/O power numbers for each block: DDR, PCI, Local Bus, RapidIO, TSEC, and CPM. Table 6. Estimated Typical I/O Power Consumption Interface DDR I/O Parameter CCB = 200 MHz CCB = 266 MHz CCB = 300 MHz CCB = 333 MHz PCI/PCI-X I/O 32-bit, 33 MHz 32-bit 66 MHz 64-bit, 66 MHz 64-bit, 133 MHz Local Bus I/O 32-bit, 33 MHz 32-bit, 66 MHz 32-bit, 83 MHz 32-bit, 100 MHz 32-bit, 133 MHz 32-bit, 167 MHz RapidIO I/O TSEC I/O MII GMII, TBI (2.5 V) GMII, TBI (3.3 V) RGMII, RTBI CPM-FCC MII RMII HDLC 16 Mbps UTOPIA-8 SPHY UTOPIA-8 MPHY UTOPIA-16 SPHY UTOPIA-16 MPHY CPM-SCC HDLC 16 Mbps 17 15 9 66 111 104 149 4 mW 7 68 41 mW 7 GVDD (2.5 V) 0.50 0.65 0.72 0.80 0.05 0.08 0.15 0.28 0.08 0.14 0.17 0.21 0.27 0.33 0.96 10 39 W mW 4 5, 6 W 3 W 2 OVDD (3.3 V) LVDD (3.3 V) LVDD (2.5 V) Units W Notes 1 MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 14 Freescale Semiconductor Power Characteristics Table 6. Estimated Typical I/O Power Consumption (continued) Interface TDMA or TDMB Parameter Nibble mode Per channel GVDD (2.5 V) OVDD (3.3 V) 11 5 LVDD (3.3 V) LVDD (2.5 V) Units mW Notes 7 Notes: 1. GVDD=2.625, ECC enabled, 66% bus utilization, 33% write cycles, 10pF load on data, 10pF load on address/command, 10pF load on clock 2. OVDD=3.465, 30pF load per pin, 54% bus utilization, 33% write cycles 3. OVDD=3.465, 25pF load per pin, 5pF load on clock, 40% bus utilization, 33% write cycles 4. VDD=1.265, OVDD=3.465 5. LVDD=2.625/3.465, 15pF load per pin, 25% bus utilization 6. Power dissipation for one TSEC only 7. OVDD=3.465, 10pF load per pin, 50% bus utilization MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 Freescale Semiconductor 15 Power Characteristics MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1 16 Freescale Semiconductor Clock Timing 4 Clock Timing 4.1 System Clock Timing Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8560. Table 7. SYSCLK AC Timing Specifications Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle SYSCLK jitter Symbol fSYSCLK tSYSCLK tKH, tKL tKHKL/tSYSCLK — Min — 6.0 0.6 40 — Typical — — 1.0 — — Max 166 — 1.2 60 +/- 150 Unit MHz ns ns % ps 2 3 4, 5 Notes 1 Notes: 1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be