MPC860SR

Freescale Semiconductor Technical Data MPC860EC Rev. 7, 09/2004 MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC860 family. 1 Overview The MPC860 Power Quad Integrated Communications Controller (PowerQUICC™) is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this hardware specification. The MPC860 implements the PowerPC architecture and contains a superset of Freescale’s MC68360 Quad Integrated Communications Controller (QUICC™), referred to here as the QUICC, RISC Communications Proccessor Module (CPM). The CPM from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated. Table 1 shows the functionality supported by the members of the MPC860 family. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 6 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Calculation and Measurement . . . . . . . . . . . 9 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 41 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 43 UTOPIA AC Electrical Specifications . . . . . . . . . . . 67 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 68 Mechanical Data and Ordering Information . . . . . . . 71 Document Revision History . . . . . . . . . . . . . . . . . . . 77 © Freescale Semiconductor, Inc., 2004. All rights reserved. Features Table 1. MPC860 Family Functionality Cache (Kbytes) Part Instruction Cache 4 4 16 4 4 4 16 4 Data Cache 4 4 8 4 4 4 8 4 10T Up to 2 Up to 2 Up to 2 Up to 4 Up to 4 Up to 4 Up to 4 1 Ethernet ATM 10/100 — 1 1 — — 1 1 1 — Yes Yes — Yes Yes Yes Yes 2 2 2 4 4 4 4 1 1 1 1 1 1 1 1 2 SCC Reference 1 MPC860DE MPC860DT MPC860DP MPC860EN MPC860SR MPC860T MPC860P MPC855T 1 Supporting documentation for these devices refers to the following: 1. MPC860 PowerQUICC Family User’s Manual (MPC860UM, Rev. 3) 2. MPC855T User’s Manual (MPC855TUM/D, Rev. 1) 2 • Features Embedded single-issue, 32-bit PowerPCTM core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch without conditional execution. — 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1) – 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instruction caches are two-way, set-associative with 128 sets. – 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way, set-associative with 128 sets. – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully-associative instruction, and data TLBs — MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip-emulation debug mode Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Operates at up to 80 MHz Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller The following list summarizes the key MPC860 features: • • • • MPC860 Family Hardware Specifications, Rev. 7 2 Freescale Semiconductor Features • • • • • — Each bank can be a chip select or RAS to support a DRAM bank. — Up to 15 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbyte to 256 Mbyte) — Selectable write protection — On-chip bus arbitration logic General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture. System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) Interrupts — Seven external interrupt request (IRQ) lines — 12 port pins with interrupt capability — 23 internal interrupt sources — Programmable priority between SCCs — Programmable highest priority request 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using ATM over UTOPIA interface) ATM support compliant with ATM forum UNI 4.0 specification — Cell processing up to 50–70 Mbps at 50-MHz system clock — Cell multiplexing/demultiplexing — Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software implementation of other protocols. — ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and unspecified bit rate (UBR) and providing control mechanisms enabling software support of available bit rate (ABR) — Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and byte-aligned serial (for example, T1/E1/ADSL) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 3 Features • • • • • • — UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or 1/3. — Serial-mode ATM connection supports transmission convergence (TC) function for T1/E1/ADSL lines, cell delineation, cell payload scrambling/descrambling, automatic idle/unassigned cell insertion/stripping, header error control (HEC) generation, checking, and statistics. Communications processor module (CPM) — RISC communications processor (CP) — Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) — Supports continuous mode transmission and reception on all serial channels — Up to 8 Kbytes of dual-port RAM — 16 serial DMA (SDMA) channels — Three parallel I/O registers with open-drain capability Four baud-rate generators (BRGs) — Independent (can be tied to any SCC or SMC) — Allows changes during operation — Autobaud support option Four serial communications controllers (SCCs) — Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation (available only on specially programmed devices) — HDLC/SDLC (all channels supported at 2 Mbps) — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support point-to-point protocol (PPP) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame-based with optional cyclic redundancy check (CRC)) Two SMCs (serial management channels) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division multiplexed (TDM) channels One SPI (serial peripheral interface) — Supports master and slave modes — Supports multimaster operation on the same bus One I2C (inter-integrated circuit) port — Supports master and slave modes MPC860 Family Hardware Specifications, Rev. 7 4 Freescale Semiconductor Maximum Tolerated Ratings • • • • • • • — Multiple-master environment support Time-slot assigner (TSA) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking — Allows dynamic changes — Can be internally connected to six serial channels (four SCCs and two SMCs) Parallel interface port (PIP) — Centronics interface support — Supports fast connection between compatible ports on the MPC860 or the MC68360 PCMCIA interface — Master (socket) interface, release 2.1 compliant — Supports two independent PCMCIA sockets — Supports eight memory or I/O windows Low power support — Full on—all units fully powered — Doze—core functional units disabled except time base decrementer, PLL, memory controller, RTC, and CPM in low-power standby — Sleep—all units disabled except RTC and PIT, PLL active for fast wake up — Deep sleep—all units disabled including PLL except RTC and PIT — Power down mode—all units powered down except PLL, RTC, PIT, time base, and decrementer Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break-point internally. 3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK 357-pin ball grid array (BGA) package 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC860. Table 2 provides the maximum ratings. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or Vdd). MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 5 Thermal Characteristics Table 2. Maximum Tolerated Ratings (GND = 0 V) Rating Supply voltage 1 Symbol VDDH VDDL KAPWR VDDSYN Input voltage 2 Temperature 3 (standard) Vin TA(min) Tj(max) Temperature (extended) 3 Value –0.3 to 4.0 –0.3 to 4.0 –0.3 to 4.0 –0.3 to 4.0 GND – 0.3 to VDDH 0 95 –40 95 –55 to 150 Unit V V V V V °C °C °C °C °C TA(min) Tj(max) Storage temperature range 1 2 Tstg The power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be applied to its inputs). 3 Minimum temperatures are guaranteed as ambient temperature, T . Maximum temperatures are guaranteed as A junction temperature, Tj. 4 Thermal Characteristics Table 3. Package Description Package Designator ZP ZQ / VR Package Code (Case No.) 5050 (1103-01) 5058 (1103D-02) Package Description PBGA 357 25*25*0.9P1.27 PBGA 357 25*25*1.2P1.27 Table 4 shows the thermal characteristics for the MPC860. MPC860 Family Hardware Specifications, Rev. 7 6 Freescale Semiconductor Power Dissipation Table 4. MPC860 Thermal Resistance Data Rating Mold Compound Thickness Junction-to-ambient 1 Environment Symbol ZP MPC860P 0.85 ZQ / VR MPC860P 1.15 34 22 27 18 13 8 2 Unit mm °C/W Natural convection Single-layer board (1s) Four-layer board (2s2p) RθJA 2 34 22 27 18 14 6 2 RθJMA 3 RθJMA 3 Airflow (200 ft/min) Single-layer board (1s) Four-layer board (2s2p) RθJMA3 RθJB RθJC Junction-to-board Junction-to-case 5 4 Junction-to-package top 1 6 Natural convection ΨJT 2 3 4 5 6 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. 5 Power Dissipation Table 5. Power Dissipation (PD) Die Revision D.4 (1:1 mode) D.4 (2:1 mode) 1 2 Table 5 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice the bus speed. Frequency (MHz) 50 66 66 80 Typical 1 656 TBD 722 851 Maximum 2 735 TBD 762 909 Unit mW mW mW mW Typical power dissipation is measured at 3.3 V. Maximum power dissipation is measured at 3.5 V. NOTE Values in Table 5 represent VDDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 7 DC Characteristics 6 DC Characteristics Table 6. DC Electrical Specifications Characteristic Operating voltage at 40 MHz or less Symbol VDDH, VDDL, VDDSYN KAPWR (power-down mode) KAPWR (all other operating modes) Operating voltage greater than 40 MHz VDDH, VDDL, KAPWR, VDDSYN KAPWR (power-down mode) KAPWR (all other operating modes) Input high voltage (all inputs except EXTAL and EXTCLK) Input low voltage 1 EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK, and DSDI pins) Input leakage current, Vin = 3.6 V (except TMS, TRST, DSCK, and DSDI pins) Input leakage current, Vin = 0 V (except TMS, TRST, DSCK, and DSDI pins) Input capacitance 2 Output high voltage, IOH = –2.0 mA, VDDH = 3.0 V (except XTAL, XFC, and open-drain pins) Output low voltage IOL = 2.0 mA, CLKOUT IOL = 3.2 mA 3 IOL = 5.3 mA 4 IOL = 7.0 mA, TXD1/PA14, TXD2/PA12 IOL = 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET 1 Table 6 provides the DC electrical characteristics for the MPC860. Min 3.0 2.0 VDDH – 0.4 3.135 2.0 VDDH – 0.4 2.0 GND 0.7 × (VDDH) — — — — 2.4 — Max 3.6 3.6 VDDH 3.465 3.6 VDDH 5.5 0.8 VDDH + 0.3 100 10 10 20 — 0.5 Unit V V V V V V V V V µA µA µA pF V V VIH VIL VIHC Iin IIn IIn Cin VOH VOL VIL(max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard. 2 Input capacitance is periodically sampled. MPC860 Family Hardware Specifications, Rev. 7 8 Freescale Semiconductor Thermal Calculation and Measurement 3 A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/ VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/ PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/ PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/ PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/ DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/ L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3] 4 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/ GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30) 7 Thermal Calculation and Measurement For the following discussions, PD = (VDD × IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: TJ = TA + (RθJA × PD) where: TA = ambient temperature (ºC) RθJA = package junction-to-ambient thermal resistance (ºC/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction-to-ambient thermal resistance (ºC/W) RθJC = junction-to-case thermal resistance (ºC/W) RθCA = case-to-ambient thermal resistance (ºC/W) RθJC is device related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 9 Thermal Calculation and Measurement printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages, especially PBGA packages, is strongly dependent on the board temperature; see Figure 1. Junction Temperature Rise Above Ambient Divided by Package Power Board Temperature Rise Above Ambient Divided by Package Power Figure 1. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB + (RθJB × PD) where: RθJB = junction-to-board thermal resistance (ºC/W) TB = board temperature (ºC) PD = power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground plane. MPC860 Family Hardware Specifications, Rev. 7 10 Freescale Semiconductor Layout Practices 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: ΨJT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 7.6 References Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) Specifications (Available from Global Engineering Documents) JEDEC Specifications (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54. 2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. 8 Layout Practices Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VDD power supply should be bypassed to ground using at least four 0.1 µF-bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. A four-layer board employing two inner layers as VCC and GND planes is recommended. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 11 Bus Signal Timing All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6 inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. 9 Bus Signal Timing Table 7 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz. The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus). The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. Table 7. Bus Operation Timings 33 MHz Num Characteristic Min B1 B1a B1b B1c B1d B1e B1f B1g B1h B2 B3 B4 B533 B7 CLKOUT period EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF 10 MHz and MF < 10) CLKOUT phase jitter (EXTCLK > 15 MHz and MF 500) 1 40 MHz Min 25.00 –0.90 –2.30 –0.60 –2.00 — — — — 10.00 10.00 — — 6.25 Max 30.30 0.90 2.30 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — 50 MHz Min 20.00 –0.90 –2.30 –0.60 –2.00 — — — — 8.00 8.00 — — 5.00 Max 30.30 0.90 2.30 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — 66 MHz Unit Min 15.15 –0.90 –2.30 –0.60 –2.00 — — — — 6.06 6.06 — — 3.80 Max 30.30 0.90 2.30 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — ns ns ns ns ns % % % % ns ns ns ns ns Max 30.30 0.90 2.30 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — 30.30 –0.90 –2.30 –0.60 –2.00 — — — — 12.12 12.12 — — 7.58 Frequency jitter on EXTCLK 2 CLKOUT pulse width low CLKOUT width high CLKOUT rise time 3 CLKOUT fall time3 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) invalid MPC860 Family Hardware Specifications, Rev. 7 12 Freescale Semiconductor Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B7a B7b CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR invalid CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS invalid 4 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31), DP(0:3) valid CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP, PTR valid CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid 4 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z CLKOUT to TS, BB assertion CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) CLKOUT to TS, BB negation 7.58 7.58 Max — — Min 6.25 6.25 Max — — Min 5.00 5.00 Max — — Min 3.80 3.80 Max — — ns ns 40 MHz 50 MHz 66 MHz Unit B8 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns B8a B8b 7.58 7.58 14.33 14.33 6.25 6.25 13.00 13.00 5.00 5.00 11.75 11.75 3.80 3.80 10.04 10.04 ns ns B9 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns B11 B11a 7.58 2.50 13.58 9.25 6.25 2.50 12.25 9.25 5.00 2.50 11.00 9.25 3.80 2.50 11.29 9.75 ns ns B12 7.58 2.50 14.33 11.00 6.25 2.50 13.00 11.00 5.00 2.50 11.75 11.00 3.80 2.50 8.54 9.00 ns ns B12a CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) B13 CLKOUT to TS, BB High-Z 7.58 2.50 21.58 15.00 6.25 2.50 20.25 15.00 5.00 2.50 19.00 15.00 3.80 2.50 14.04 15.00 ns ns B13a CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) B14 B15 B16 CLKOUT to TEA assertion CLKOUT to TEA High-Z TA, BI valid to CLKOUT (setup time) 2.50 2.50 9.75 10.00 8.50 1.00 2.00 10.00 15.00 — — — — — 2.50 2.50 9.75 10.00 8.50 1.00 2.00 10.00 15.00 — — — — — 2.50 2.50 9.75 10.00 8.50 1.00 2.00 10.00 15.00 — — — — — 2.50 2.50 6.00 4.50 4.00 2.00 2.00 9.00 15.00 — — — — — ns ns ns ns ns ns ns B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time) B16b BB, BG, BR, valid to CLKOUT (setup time) 5 B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) B17a CLKOUT to KR, RETRY, CR valid (hold time) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 13 Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B18 B19 B20 B21 B22 D(0:31), DP(0:3) valid to CLKOUT rising edge (setup time) 6 CLKOUT rising edge to D(0:31), DP(0:3) valid (hold time) 6 D(0:31), DP(0:3) valid to CLKOUT falling edge (setup time) 7 CLKOUT falling edge to D(0:31), DP(0:3) valid (hold time) 7 CLKOUT rising edge to CS asserted GPCM ACS = 00 6.00 1.00 4.00 2.00 7.58 — 7.58 Max — — — — 14.33 8.00 14.33 Min 6.00 1.00 4.00 2.00 6.25 — 6.25 Max — — — — 13.00 8.00 13.00 Min 6.00 1.00 4.00 2.00 5.00 — 5.00 Max — — — — 11.75 8.00 11.75 Min 6.00 2.00 4.00 2.00 3.80 — 3.80 Max — — — — 10.04 8.00 10.54 ns ns ns ns ns ns ns 40 MHz 50 MHz 66 MHz Unit B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0, and CSNT = 0 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 0 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns B24 5.58 — 4.25 — 3.00 — 1.79 — ns B24a A(0:31) and BADDR(28:30) to CS 13.15 asserted GPCM ACS = 11, TRLX = 0 B25 B26 B27 CLKOUT rising edge to OE, WE(0:3) asserted CLKOUT rising edge to OE negated — 2.00 — 9.00 9.00 — — 9.00 10.50 — 2.00 29.25 35.50 — — 9.00 9.00 — — 9.00 8.00 — 2.00 23.00 28.00 — — 9.00 9.00 — — 9.00 5.58 — 2.00 16.94 20.73 — — 9.00 9.00 — — 9.00 ns ns ns ns ns ns A(0:31) and BADDR(28:30) to CS 35.88 asserted GPCM ACS = 10, TRLX = 1 B27a A(0:31) and BADDR(28:30) to CS 43.45 asserted GPCM ACS = 11, TRLX = 1 B28 CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 — B28a CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX = 0, 1, CSNT = 1, EBDF = 0 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns MPC860 Family Hardware Specifications, Rev. 7 14 Freescale Semiconductor Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0, 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B28c CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX = 0, 1, CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1 B28d CLKOUT falling edge to CS negated GPCM write access TRLX = 0, 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 B29 WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access CSNT = 0, EBDF = 0 — Max 14.33 Min — Max 13.00 Min — Max 11.75 Min — Max 10.54 ns 40 MHz 50 MHz 66 MHz Unit 10.86 17.99 8.88 16.00 7.00 14.13 5.18 12.31 ns — 17.99 — 16.00 — 14.13 — 12.31 ns 5.58 — 4.25 — 3.00 — 1.79 — ns B29a WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 B29b CS negated to D(0:31), DP(0:3), High-Z GPCM write access, ACS = 00, TRLX = 0, 1, and CSNT = 0 B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 B29e CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B29f WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 13.15 — 10.5 — 8.00 — 5.58 — ns 5.58 — 4.25 — 3.00 — 1.79 — ns 13.15 — 10.5 — 8.00 — 5.58 — ns 43.45 — 35.5 — 28.00 — 20.73 — ns 43.45 — 35.5 — 28.00 — 29.73 — ns 8.86 — 6.88 — 5.00 — 3.18 — ns B29g CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 B29h WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 1 8.86 — 6.88 — 5.00 — 3.18 — ns 38.67 — 31.38 — 24.50 — 17.83 — ns MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 15 Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min CS negated to D(0:31), DP(0:3) High-Z GPCM write access, How to Reach Us: 1, CSNT = 1, ACS = 10, or TRLX = Home Page:ACS = 11, EBDF = 1 www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-0047 Japan 0120 191014 +81 3 3440 3569 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@ hibbertgroup.com 40 MHz Min 31.38 Max — 50 MHz Min 24.50 Max — 66 MHz Unit Min 17.83 Max — ns Max — B29i 38.67 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004. MPC860EC Rev. 7 09/2004 Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B30 CS, WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access 8 5.58 Max — Min 4.25 Max — Min 3.00 Max — Min 1.79 Max — ns 40 MHz 50 MHz 66 MHz Unit B30a WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT =1 ACS = 10, or ACS = 11, EBDF = 0 B30b WE(0:3) negated to A(0:31), invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31), Invalid GPCM, write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, ACS = 11, EBDF = 1 B30d WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT =1. CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 B31 CLKOUT falling edge to CS valid—as requested by control bit CST4 in the corresponding word in UPM 13.15 — 10.50 — 8.00 — 5.58 — ns 43.45 — 35.50 — 28.00 — 20.73 — ns 8.36 — 6.38 — 4.50 — 2.68 — ns 38.67 — 31.38 — 24.50 — 17.83 — ns 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B31a CLKOUT falling edge to CS valid—as requested by control bit CST1 in the corresponding word in UPM B31b CLKOUT rising edge to CS valid—as requested by control bit CST2 in the corresponding word in UPM B31c CLKOUT rising edge to CS valid—as requested by control bit CST3 in the corresponding word in UPM 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.04 ns MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 17 Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B31d CLKOUT falling edge to CS valid—as requested by control bit CST1 in the corresponding word in UPM, EBDF = 1 B32 CLKOUT falling edge to BS valid—as requested by control bit BST4 in the corresponding word in UPM 13.26 Max 17.99 Min 11.28 Max 16.00 Min 9.40 Max 14.13 Min 7.58 Max 12.31 ns 40 MHz 50 MHz 66 MHz Unit 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B32a CLKOUT falling edge to BS valid—as requested by control bit BST1 in the corresponding word in UPM, EBDF = 0 B32b CLKOUT rising edge to BS valid—as requested by control bit BST2 in the corresponding word in UPM B32c CLKOUT rising edge to BS valid—as requested by control bit BST3 in the corresponding word in UPM B32d CLKOUT falling edge to BS valid—as requested by control bit BST1 in the corresponding word in UPM, EBDF = 1 B33 CLKOUT falling edge to GPL valid—as requested by control bit GxT4 in the corresponding word in UPM 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns 13.26 17.99 11.28 16.00 9.40 14.13 7.58 12.31 ns 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns B33a CLKOUT rising edge to GPL valid—as requested by control bit GxT3 in the corresponding word in UPM B34 A(0:31), BADDR(28:30), and D(0:31) to CS valid—as requested by control bit CST4 in the corresponding word in UPM 7.58 14.33 6.25 13.00 5.00 11.75 3.80 10.54 ns 5.58 — 4.25 — 3.00 — 1.79 — ns B34a A(0:31), BADDR(28:30), and D(0:31) to CS valid—as requested by control bit CST1 in the corresponding word in UPM B34b A(0:31), BADDR(28:30), and D(0:31) to CS valid—as requested by control bit CST2 in the corresponding word in UPM 13.15 — 10.50 — 8.00 — 5.58 — ns 20.73 — 16.75 — 13.00 — 9.36 — ns MPC860 Family Hardware Specifications, Rev. 7 18 Freescale Semiconductor Bus Signal Timing Table 7. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B35 A(0:31), BADDR(28:30) to CS valid—as requested by control bit BST4 in the corresponding word in UPM 5.58 Max — Min 4.25 Max — Min 3.00 Max — Min 1.79 Max — ns 40 MHz 50 MHz 66 MHz Unit B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid—as requested by control bit BST1 in the corresponding word in UPM B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid—as requested by control bit BST2 in the corresponding word in UPM B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid—as requested by control bit GxT4 in the corresponding word in UPM UPWAIT valid to CLKOUT falling edge 9 CLKOUT falling edge to UPWAIT valid 9 AS valid to CLKOUT rising edge 10 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge TS valid to CLKOUT rising edge (setup time) CLKOUT rising edge to TS valid (hold time) AS negation to memory controller signals negation 13.15 — 10.50 — 8.00 — 5.58 — ns 20.73 — 16.75 — 13.00 — 9.36 — ns 5.58 — 4.25 — 3.00 — 1.79 — ns B37 B38 B39 B40 B41 B42 B43 1 2 6.00 1.00 7.00 7.00 7.00 2.00 — — — — — — — TBD 6.00 1.00 7.00 7.00 7.00 2.00 — — — — — — — TBD 6.00 1.00 7.00 7.00 7.00 2.00 — — — — — — — TBD 6.00 1.00 7.00 7.00 7.00 2.00 — — — — — — — TBD ns ns ns ns ns ns ns 3 4 5 6 7 Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time) then the maximum allowed jitter on EXTAL can be up to 2%. The timings specified in B4 and B5 are based on full strength clock. The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for BG output is relevant when the MPC860 is selected to work with internal bus arbiter. The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing for BG input is relevant when the MPC860 is selected to work with external bus arbiter. The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 19 Bus Signal Timing 8 9 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17. 10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 20. Figure 2 is the control timing diagram. 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs A B C D Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 2.0 V CLKOUT Figure 2. Control Timing Figure 3 provides the timing for the external clock. MPC860 Family Hardware Specifications, Rev. 7 20 Freescale Semiconductor Bus Signal Timing CLKOUT B1 B1 B4 B5 B3 B2 Figure 3. External Clock Timing Figure 4 provides the timing for the synchronous output signals. CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 4. Synchronous Output Signals Timing MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 21 Bus Signal Timing Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 TS, BB B13a B11a TA, BI B14 B15 TEA B12a B12 Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 6. Synchronous Input Signals Timing Figure 7 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. MPC860 Family Hardware Specifications, Rev. 7 22 Freescale Semiconductor Bus Signal Timing CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 7. Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 23 Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31], DP[0:3] B19 B26 B23 B12 Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC860 Family Hardware Specifications, Rev. 7 24 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B24 OE B18 D[0:31], DP[0:3] B19 B25 B26 Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] B22c B22b B12 B23 CSx B24a B25 B26 OE B18 D[0:31], DP[0:3] B19 Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 25 Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22a B12 B23 CSx B27 OE B27a B22b B22c B26 B18 B19 D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11) Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. MPC860 Family Hardware Specifications, Rev. 7 26 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B9 B29b B12 B30 B23 B28 B29 Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 27 Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29a B29f B29c B29g B28b B28d B30a B30c B12 B23 B9 Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1) MPC860 Family Hardware Specifications, Rev. 7 28 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B29d B29h B29e B29i B28b B28d B30b B30d B12 B23 B29b B9 Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1) Figure 16 provides the timing for the external bus controlled by the UPM. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 29 Bus Signal Timing CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3], BS_B[0:3] B35 B36 B35a B35b B33a B33 GPL_A[0:5], GPL_B[0:5] Figure 16. External Bus Timing (UPM Controlled Signals) Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. MPC860 Family Hardware Specifications, Rev. 7 30 Freescale Semiconductor Bus Signal Timing CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 31 Bus Signal Timing CLKOUT B41 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx B42 Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 21 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 21. Asynchronous External Master—Control Signals Negation Timing MPC860 Family Hardware Specifications, Rev. 7 32 Freescale Semiconductor Bus Signal Timing Table 8 provides interrupt timing for the MPC860. Table 8. Interrupt Timing All Frequencies Num Characteristic 1 Min I39 I40 I41 I42 I43 1 Unit Max — — — — — ns ns ns ns — IRQx valid to CLKOUT rising edge (setup time) IRQx hold time after CLKOUT IRQx pulse width low IRQx pulse width high IRQx edge-to-edge time 6.00 2.00 3.00 3.00 4 × TCLOCKOUT The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level-sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC860 is able to support. Figure 22 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 22. Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 IRQx I43 I43 I42 Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 33 Bus Signal Timing Table 9 shows the PCMCIA timing for the MPC860. Table 9. PCMCIA Timing 33 MHz Num Characteristic Min P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 1 40 MHz Min 16.75 23.00 6.25 7.25 6.25 6.25 Max — — 14.25 — 14.25 14.25 11.00 2.00 6.25 11.00 14.25 14.25 4.25 8.00 2.00 — — — 50 MHz Min 13.00 18.00 5.00 6.00 5.00 5.00 — 2.00 5.00 — 3.00 8.00 2.00 Max — — 13.00 — 13.00 13.00 11.00 11.00 13.00 13.00 — — — 66 MHz Unit Min 9.36 13.15 3.79 4.84 3.79 3.79 — 2.00 3.79 — 1.79 8.00 2.00 Max — — 11.84 — 11.84 11.84 11.00 11.00 10.04 11.84 — — — ns ns ns ns ns ns ns ns ns ns ns ns ns Max — — 15.58 — 15.58 15.58 11.00 11.00 15.58 15.58 — — — A(0:31), REG valid to PCMCIA Strobe asserted 1 20.73 A(0:31), REG valid to ALE negation 1 28.30 CLKOUT to REG valid CLKOUT to REG invalid CLKOUT to CE1, CE2 asserted CLKOUT to CE1, CE2 negated CLKOUT to PCOE, IORD, PCWE, IOWR assert time CLKOUT to PCOE, IORD, PCWE, IOWR negate time CLKOUT to ALE assert time CLKOUT to ALE negate time PCWE, IOWR negated to D(0:31) invalid 1 WAITA and WAITB valid to CLKOUT rising edge 1 CLKOUT rising edge to WAITA and WAITB invalid 1 7.58 8.58 7.58 7.58 — 2.00 7.58 — 5.58 8.00 2.00 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC860 PowerQUICC User’s Manual. Figure 24 provides the PCMCIA access cycle timing for the external bus read. MPC860 Family Hardware Specifications, Rev. 7 34 Freescale Semiconductor Bus Signal Timing CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 Figure 24. PCMCIA Access Cycle Timing External Bus Read Figure 25 provides the PCMCIA access cycle timing for the external bus write. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 35 Bus Signal Timing CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCWE, IOWR P52 ALE B8 D[0:31] B9 P53 P52 P51 P54 P49 P45 P47 Figure 25. PCMCIA Access Cycle Timing External Bus Write Figure 26 provides the PCMCIA WAIT signal detection timing. CLKOUT P55 P56 WAITx Figure 26. PCMCIA WAIT Signal Detection Timing Table 10 shows the PCMCIA port timing for the MPC860. MPC860 Family Hardware Specifications, Rev. 7 36 Freescale Semiconductor Bus Signal Timing Table 10. PCMCIA Port Timing 33 MHz Num Characteristic Min P57 P58 P59 P60 1 40 MHz Min — 21.75 5.00 1.00 Max 19.00 — — — 50 MHz Min — 18.00 5.00 1.00 Max 19.00 — — — 66 MHz Unit Min — 14.36 5.00 1.00 Max 19.00 — — — ns ns ns ns Max 19.00 — — — CLKOUT to OPx valid HRESET negated to OPx drive 1 IP_Xx valid to CLKOUT rising edge CLKOUT rising edge to IP_Xx invalid — 25.73 5.00 1.00 OP2 and OP3 only Figure 27 provides the PCMCIA output port timing for the MPC860. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 27. PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC860. CLKOUT P59 P60 Input Signals Figure 28. PCMCIA Input Port Timing Table 11 shows the debug port timing for the MPC860. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 37 Bus Signal Timing Table 11. Debug Port Timing All Frequencies Num Characteristic Min P61 P62 P63 P64 P65 P66 P67 DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 3 × TCLOCKOUT 1.25 × TCLOCKOUT 0.00 8.00 5.00 0.00 0.00 Max — — 3.00 — — 15.00 2.00 — — ns ns ns ns ns Unit Figure 29 provides the input timing for the debug port clock. DSCK D61 D61 D63 D62 D62 D63 Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 30. Debug Port Timings MPC860 Family Hardware Specifications, Rev. 7 38 Freescale Semiconductor Bus Signal Timing Table 12 shows the reset timing for the MPC860. Table 12. Reset Timing 33 MHz Num Characteristic Min R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width — Configuration data to HRESET rising edge setup time Configuration data to RSTCONF rising edge setup time Configuration data hold time after RSTCONF negation Configuration data hold time after HRESET negation HRESET and RSTCONF asserted to data out drive RSTCONF negated to data out high impedance CLKOUT of last rising edge before chip three-state HRESET to data out high impedance DSDI, DSCK setup DSDI, DSCK hold time SRESET negated to CLKOUT rising edge for DSDI and DSCK sample — — 515.1 5 — 504.5 5 350.0 0 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 — — Min — — 425.0 0 — 425.0 0 350.0 0 0.00 0.00 — — — — — 25.00 25.00 25.00 Max 20.00 20.00 Min — — 340.0 0 — 350.0 0 350.0 0 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 Min — — 257.5 8 — 277.2 7 350.0 0 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 ns ns ns ns ns ns ns ns ns ns 40 MHz 50 MHz 66 MHz Unit R80 R81 R82 90.91 0.00 242.4 2 — — — 75.00 0.00 200.0 0 — — — 60.00 0.00 160.0 0 — — — 45.45 0.00 121.2 1 — — — ns ns ns Figure 31 shows the reset timing for the data bus configuration. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 39 Bus Signal Timing HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 Figure 31. Reset Timing—Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 32. Reset Timing—Data Bus Weak Drive During Configuration Figure 33 provides the reset timing for the debug port configuration. MPC860 Family Hardware Specifications, Rev. 7 40 Freescale Semiconductor IEEE 1149.1 Electrical Specifications CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 Figure 33. Reset Timing—Debug Port Configuration 10 IEEE 1149.1 Electrical Specifications Table 13 provides the JTAG timings for the MPC860 shown in Figure 34 through Figure 37. Table 13. JTAG Timing All Frequencies Num Characteristic Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to output valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid 100.00 40.00 0.00 5.00 25.00 — 0.00 — 100.00 40.00 — — — 50.00 50.00 Max — — 10.00 — — 27.00 — 20.00 — — 50.00 50.00 50.00 — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 41 IEEE 1149.1 Electrical Specifications TCK J82 J82 J84 J83 J83 J84 Figure 34. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 TDO J89 Figure 35. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 36. JTAG TRST Timing Diagram TCK J92 Output Signals J93 Output Signals J95 Output Signals J96 J94 Figure 37. Boundary Scan (JTAG) Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 42 Freescale Semiconductor CPM Electrical Characteristics 11 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC860. 11.1 PIP/PIO AC Electrical Specifications Table 14 provides the PIP/PIO AC timings as shown in Figure 38 through Figure 42. Table 14. PIP/PIO Timing All Frequencies Num Characteristic Min 21 22 23 24 25 26 27 28 29 30 31 1 Unit Max — — — — — — 2 — — — 25 ns CLK CLK ns CLK CLK CLK CLK ns ns ns Data-in setup time to STBI low Data-in hold time to STBI high STBI pulse width STBO pulse width Data-out setup time to STBO low Data-out hold time from STBO high STBI low to STBO low (Rx interlock) STBI low to STBO high (Tx interlock) Data-in setup time to clock high Data-in hold time from clock high Clock low to data-out valid (CPU writes data, control, or direction) 0 2.5 – t3 1 1.5 1 CLK – 5 ns 2 5 — 2 15 7.5 — t3 = Specification 23. DATA-IN 21 23 STBI 27 24 STBO 22 Figure 38. PIP Rx (Interlock Mode) Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 43 CPM Electrical Characteristics DATA-OUT 25 24 STBO (Output) 28 23 STBI (Input) 26 Figure 39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN 21 23 STBI (Input) 22 24 STBO (Output) Figure 40. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT 25 24 STBO (Output) 26 23 STBI (Input) Figure 41. PIP TX (Pulse Mode) Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 44 Freescale Semiconductor CPM Electrical Characteristics CLKO 29 30 DATA-IN 31 DATA-OUT Figure 42. Parallel I/O Data-In/Data-Out Timing Diagram 11.2 Port C Interrupt AC Electrical Specifications Table 15 provides the timings for port C interrupts. Table 15. Port C Interrupt Timing ≥ 33.34 MHz 1 Num Characteristic Min 35 36 1 Unit Max — — ns ns Port C interrupt pulse width low (edge-triggered mode) Port C interrupt minimum time between active edges 55 55 External bus frequency of greater than or equal to 33.34 MHz. Figure 43 shows the port C interrupt detection timing. 36 Port C (Input) 35 Figure 43. Port C Interrupt Detection Timing 11.3 IDMA Controller AC Electrical Specifications Table 16 provides the IDMA controller timings as shown in Figure 44 through Figure 47. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 45 CPM Electrical Characteristics Table 16. IDMA Controller Timing All Frequencies Num Characteristic Min 40 41 42 43 44 45 46 DREQ setup time to clock high DREQ hold time from clock high SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time (applies to external TA) 7 3 — — — — 7 Max — — 12 12 20 15 — ns ns ns ns ns ns ns Unit CLKO (Output) 41 40 DREQ (Input) Figure 44. IDMA External Requests Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 46 Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 46 TA (Input) 43 SDACK Figure 45. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 DATA 44 TA (Output) SDACK Figure 46. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 47 CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 45 TA (Output) SDACK Figure 47. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 11.4 Baud Rate Generator AC Electrical Specifications Table 17 provides the baud rate generator timings as shown in Figure 48. Table 17. Baud Rate Generator Timing All Frequencies Num Characteristic Min 50 51 52 BRGO rise and fall time BRGO duty cycle BRGO cycle — 40 40 Max 10 60 — ns % ns Unit 50 BRGOX 51 52 50 51 Figure 48. Baud Rate Generator Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 48 Freescale Semiconductor CPM Electrical Characteristics 11.5 Timer AC Electrical Specifications Table 18 provides the general-purpose timer timings as shown in Figure 49. Table 18. Timer Timing All Frequencies Num Characteristic Min 61 62 63 64 65 TIN/TGATE rise and fall time TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO low to TOUT valid 10 1 2 3 3 Max — — — — 25 ns CLK CLK CLK ns Unit CLKO 60 61 TIN/TGATE (Input) 61 65 TOUT (Output) 64 63 62 Figure 49. CPM General-Purpose Timers Timing Diagram 11.6 Serial Interface AC Electrical Specifications Table 19 provides the serial interface timings as shown in Figure 50 through Figure 54. Table 19. SI Timing All Frequencies Num Characteristic Min 70 71 71a 72 73 74 L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 L1RCLK, L1TCLK width low (DSC = 0) 2 L1RCLK, L1TCLK width high (DSC = 0) 3 Unit Max SYNCCLK/2.5 — — 15.00 — — MHz ns ns ns ns ns — P + 10 P + 10 — 20.00 35.00 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 49 CPM Electrical Characteristics Table 19. SI Timing (continued) All Frequencies Num Characteristic Min 75 76 77 78 78A 79 80 80A 81 82 83 83a 84 85 86 87 88 1 2 Unit Max 15.00 — — 45.00 45.00 45.00 55.00 55.00 42.00 16.00 or SYNCCLK/2 — — 30.00 — — — 0.00 ns ns ns ns ns ns ns ns ns MHz ns ns ns L1TCL K ns ns ns L1RSYNC, L1TSYNC rise/fall time L1RXD valid to L1CLK edge (L1RXD setup time) L1CLK edge to L1RXD invalid (L1RXD hold time) L1CLK edge to L1ST(1–4) valid 4 L1SYNC valid to L1ST(1–4) valid L1CLK edge to L1ST(1–4) invalid L1CLK edge to L1TXD valid L1TSYNC valid to L1TXD valid 4 L1CLK edge to L1TXD high impedance L1RCLK, L1TCLK frequency (DSC =1) L1RCLK, L1TCLK width low (DSC =1) L1RCLK, L1TCLK width high (DSC = 1)3 — 17.00 13.00 10.00 10.00 10.00 10.00 10.00 0.00 — P + 10 P + 10 — 1.00 42.00 42.00 — L1CLK edge to L1CLKO valid (DSC = 1) L1RQ valid before falling edge of L1GR setup time2 L1GR hold time L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) L1TSYNC4 The ratio SYNCCLK/L1RCLK must be greater than 2.5/1. These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. MPC860 Family Hardware Specifications, Rev. 7 50 Freescale Semiconductor CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 72 L1RCLK (FE=1, CE=1) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RXD (Input) 76 78 L1ST(4-1) (Output) 79 BIT0 77 70 71a Figure 50. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 51 CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 72 82 L1RCLK (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RXD (Input) 76 78 L1ST(4-1) (Output) 79 BIT0 77 83a 84 L1CLKO (Output) Figure 51. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC860 Family Hardware Specifications, Rev. 7 52 Freescale Semiconductor CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 72 L1TCLK (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNC (Input) 74 80a L1TXD (Output) BIT0 80 78 L1ST(4-1) (Output) 79 81 70 Figure 52. SI Transmit Timing Diagram (DSC = 0) MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 53 CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 72 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input) 73 74 L1TXD (Output) BIT0 80 78a L1ST(4-1) (Output) 78 84 L1CLKO (Output) 79 81 83a Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC860 Family Hardware Specifications, Rev. 7 54 Freescale Semiconductor Freescale Semiconductor 1 73 71 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 71 74 B17 B16 72 77 B17 B16 B15 B14 B13 76 78 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 81 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 85 86 87 L1RCLK (Input) L1RSYNC (Input) 80 L1TXD (Output) Figure 54. IDL Timing L1RXD (Input) MPC860 Family Hardware Specifications, Rev. 7 L1ST(4-1) (Output) L1RQ (Output) L1GR (Input) CPM Electrical Characteristics 55 CPM Electrical Characteristics 11.7 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Table 20. NMSI External Clock Timing All Frequencies Num Characteristic Min 100 101 102 103 104 105 106 107 108 1 2 Unit Max — — 15.00 50.00 50.00 — — — — ns ns ns ns ns ns ns ns ns RCLK1 and TCLK1 width high 1 RCLK1 and TCLK1 width low RCLK1 and TCLK1 rise/fall time TXD1 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD1 setup time to RCLK1 rising edge RXD1 hold time from RCLK1 rising edge 2 1/SYNCCLK 1/SYNCCLK + 5 — 0.00 0.00 5.00 5.00 5.00 5.00 CD1 setup Time to RCLK1 rising edge The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1. Also applies to CD and CTS hold time when they are used as external sync signals. Table 21 provides the NMSI internal clock timing. Table 21. NMSI Internal Clock Timing All Frequencies Num Characteristic Min 100 102 103 104 105 106 107 108 1 2 Unit Max SYNCCLK/3 — 30.00 30.00 — — — — MHz ns ns ns ns ns ns ns RCLK1 and TCLK1 frequency 1 RCLK1 and TCLK1 rise/fall time TXD1 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD1 setup time to RCLK1 rising edge RXD1 hold time from RCLK1 rising edge 2 CD1 setup time to RCLK1 rising edge 0.00 — 0.00 0.00 40.00 40.00 0.00 40.00 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1. Also applies to CD and CTS hold time when they are used as external sync signals. Figure 55 through Figure 57 show the NMSI timings. MPC860 Family Hardware Specifications, Rev. 7 56 Freescale Semiconductor CPM Electrical Characteristics RCLK1 102 106 RxD1 (Input) 107 108 CD1 (Input) 102 101 100 107 CD1 (SYNC Input) Figure 55. SCC NMSI Receive Timing Diagram TCLK1 102 102 101 100 TxD1 (Output) 103 105 RTS1 (Output) 104 104 CTS1 (Input) 107 CTS1 (SYNC Input) Figure 56. SCC NMSI Transmit Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 57 CPM Electrical Characteristics TCLK1 102 102 101 100 TxD1 (Output) 103 RTS1 (Output) 104 105 CTS1 (Echo Input) 107 104 Figure 57. HDLC Bus Timing Diagram 11.8 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 58 through Figure 62. Table 22. Ethernet Timing All Frequencies Num Characteristic Min 120 121 122 123 124 125 126 127 128 129 130 131 132 133 CLSN width high RCLK1 rise/fall time RCLK1 width low RCLK1 clock period 1 RXD1 setup time RXD1 hold time RENA active delay (from RCLK1 rising edge of the last data bit) RENA width low TCLK1 rise/fall time TCLK1 width low TCLK1 clock period1 40 — 40 80 20 5 10 100 — 40 99 10 10 10 Max — 15 — 120 — — — — 15 — 101 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TXD1 active delay (from TCLK1 rising edge) TXD1 inactive delay (from TCLK1 rising edge) TENA active delay (from TCLK1 rising edge) MPC860 Family Hardware Specifications, Rev. 7 58 Freescale Semiconductor CPM Electrical Characteristics Table 22. Ethernet Timing (continued) All Frequencies Num Characteristic Min 134 135 136 137 138 139 1 2 Unit Max 50 50 50 — 20 20 ns ns ns CLK ns ns TENA inactive delay (from TCLK1 rising edge) RSTRT active delay (from TCLK1 falling edge) RSTRT inactive delay (from TCLK1 falling edge) REJECT width low CLKO1 low to SDACK asserted 2 10 10 10 1 — — CLKO1 low to SDACK negated 2 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure 58. Ethernet Collision Timing Diagram RCLK1 121 124 RxD1 (Input) 125 126 127 RENA(CD1) (Input) 121 123 Last Bit Figure 59. Ethernet Receive Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 59 CPM Electrical Characteristics TCLK1 128 131 TxD1 (Output) 132 133 TENA(RTS1) (Input) 134 128 121 129 RENA(CD1) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 60. Ethernet Transmit Timing Diagram RCLK1 RxD1 (Input) 0 1 Start Frame De- 1 BIT1 BIT2 136 125 RSTRT (Output) Figure 61. CAM Interface Receive Start Timing Diagram REJECT 137 Figure 62. CAM Interface REJECT Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 60 Freescale Semiconductor CPM Electrical Characteristics 11.9 SMC Transparent AC Electrical Specifications Table 23 provides the SMC transparent timings as shown in Figure 63. Table 23. SMC Transparent Timing All Frequencies Num SMCLK clock period 1 SMCLK width low SMCLK width high SMCLK rise/fall time SMTXD active delay (from SMCLK falling edge) SMRXD/SMSYNC setup time RXD1/SMSYNC hold time Characteristic Min 150 151 151A 152 153 154 155 1 Unit Max — — — 15 50 — — ns ns ns ns ns ns ns 100 50 50 — 10 20 5 SYNCCLK must be at least twice as fast as SMCLK. SMCLK 152 152 151 151 150 SMTXD (Output) 154 155 SMSYNC 154 155 SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. NOTE 153 Figure 63. SMC Transparent Timing Diagram 11.10SPI Master AC Electrical Specifications Table 24 provides the SPI master timings as shown in Figure 64 and Figure 65. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 61 CPM Electrical Characteristics Table 24. SPI Master Timing All Frequencies Num Characteristic Min 160 161 162 163 164 165 166 167 MASTER cycle time MASTER clock (SCK) high or low time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 50 0 — 0 — — Max 1024 512 — — 20 — 15 15 tcyc tcyc ns ns ns ns ns ns Unit SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb Data 165 167 SPIMOSI (Output) msb Data lsb 166 lsb 164 166 msb msb 167 167 160 166 Figure 64. SPI Master (CP = 0) Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 62 Freescale Semiconductor CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 65. SPI Master (CP = 1) Timing Diagram 11.11SPI Slave AC Electrical Specifications Table 25 provides the SPI slave timings as shown in Figure 66 and Figure 67. Table 25. SPI Slave Timing All Frequencies Num Characteristic Min 170 171 172 173 174 175 176 177 Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time 2 15 15 1 1 20 20 — Max — — — — — — — 50 tcyc ns ns tcyc tcyc ns ns ns Unit MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 63 CPM Electrical Characteristics SPISEL (Input) 172 174 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) msb 175 176 SPIMOSI (Input) msb Data Data 179 181 182 lsb msb lsb 181 182 178 Undef msb 182 170 181 171 Figure 66. SPI Slave (CP = 0) Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 64 Freescale Semiconductor CPM Electrical Characteristics SPISEL (Input) 172 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) Undef 175 176 SPIMOSI (Input) msb msb Data 179 181 182 Data lsb msb lsb 182 178 msb 182 181 181 170 174 Figure 67. SPI Slave (CP = 1) Timing Diagram 11.12I2C AC Electrical Specifications Table 26 provides the I2C (SCL < 100 kHz) timings. Table 26. I2C Timing (SCL < 100 kHZ) All Frequencies Num 200 200 202 203 204 205 206 207 208 209 Characteristic Min SCL clock frequency (slave) SCL clock frequency (master) 1 Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 — Max 100 100 — — — — — — — 1 kHz kHz µs µs µs µs µs µs ns µs Unit MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 65 CPM Electrical Characteristics Table 26. I2C Timing (SCL < 100 kHZ) (continued) All Frequencies Num 210 211 1 Characteristic Min SDL/SCL fall time Stop condition setup time — 4.7 Max 300 — Unit ns µs SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2). The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1. Table 27 provides the I2C (SCL > 100 kHz) timings. Table 27. . I2C Timing (SCL > 100 kHZ) All Frequencies Num 200 200 202 203 204 205 206 207 208 209 210 211 1 Characteristic SCL clock frequency (slave) SCL clock frequency (master) 1 Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time Expression Min fSCL fSCL 0 BRGCLK/16512 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 0 1/(40 * fSCL) — — 1/2(2.2 * fSCL) Max BRGCLK/48 BRGCLK/48 — — — — — — — 1/(10 * fSCL) 1/(33 * fSCL) — Unit Hz Hz s s s s s s s s s s SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2). The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1. Figure 68 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 68. I2C Bus Timing Diagram MPC860 Family Hardware Specifications, Rev. 7 66 Freescale Semiconductor UTOPIA AC Electrical Specifications 12 UTOPIA AC Electrical Specifications Table 28 shows the AC electrical specifications for the UTOPIA interface. Table 28. UTOPIA AC Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (Internal clock option) Duty cycle Frequency U1a UtpClk rise/fall time (external clock option) Duty cycle Frequency U2 U3 U4 U5 RxEnb and TxEnb active delay UTPB, SOC, Rxclav and Txclav setup time UTPB, SOC, Rxclav and Txclav hold time UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) Output Input Input Output Input Direction Output Min — 50 — — 40 — 2 8 1 2 Max 3.5 50 50 3.5 60 50 16 — — 16 Unit ns % MHz ns % MHz ns ns ns ns Figure 69 shows signal timings during UTOPIA receive operations. U1 U1 UtpClk U5 PHREQn U3 3 U4 4 HighZ at MPHY U2 2 RxClav HighZ at MPHY RxEnb UTPB SOC U3 3 U4 4 Figure 69. UTOPIA Receive Timing Figure 70 shows signal timings during UTOPIA transmit operations. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 67 FEC Electrical Characteristics U1 1 U1 UtpClk U5 5 PHSELn U3 3 U4 4 HighZ at MPHY U2 2 TxClav HighZ at MPHY TxEnb UTPB SOC U5 5 Figure 70. UTOPIA Transmit Timing 13 FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 13.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK) The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency – 1%. Table 29 provides information on the MII receive signal timing. Table 29. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% Max — — 65% 65% Unit ns ns MII_RX_CL K period MII_RX_CL K period Figure 71 shows MII receive signal timing. MPC860 Family Hardware Specifications, Rev. 7 68 Freescale Semiconductor FEC Electrical Characteristics M3 MII_RX_CLK (Input) M4 MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 71. MII Receive Signal Timing Diagram 13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. Table 30 provides information on the MII transmit signal timing. Table 30. MII Transmit Signal Timing Num M5 M6 M7 M8 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MII_TX_CLK pulse width high MII_TX_CLK pulse width low Min 5 — 35 35% Max — 25 65% 65% MII_TX_CLK period MII_TX_CLK period Unit ns Figure 72 shows the MII transmit signal timing diagram. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 69 FEC Electrical Characteristics M7 MII_TX_CLK (Input) M5 M8 MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER M6 Figure 72. MII Transmit Signal Timing Diagram 13.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 31 provides information on the MII async inputs signal timing. Table 31. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max — Unit MII_TX_CLK period Figure 73 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 73. MII Async Inputs Timing Diagram 13.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 32 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 32. MII Serial Management Channel Timing Num M10 M11 M12 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup Min 0 — 10 Max — 25 — Unit ns ns ns MPC860 Family Hardware Specifications, Rev. 7 70 Freescale Semiconductor Mechanical Data and Ordering Information Table 32. MII Serial Management Channel Timing Num M13 M14 M15 Characteristic MII_MDIO (input) to MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width low Min 0 40% 40% Max — 60% 60% Unit ns MII_MDC period MII_MDC period Figure 74 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (Output) M10 MII_MDIO (Output) M11 MII_MDIO (Input) M12 M13 Figure 74. MII Serial Management Channel Timing Diagram 14 Mechanical Data and Ordering Information Table 33 provides information on the MPC860 Revision D.4 derivative devices. Table 33. MPC860 Family Revision D.4 Derivatives Device MPC855T MPC860DE MPC860DT MPC860DP Number of SCCs 1 1 2 Ethernet Support 2 Multichannel (Mbps) HDLC Support 10/100 10 10/100 10/100 Yes N/A Yes Yes ATM Support Yes N/A Yes Yes MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 33. MPC860 Family Revision D.4 Derivatives (continued) Device MPC860EN MPC860SR MPC860T MPC860P 1 2 Number of SCCs 1 4 Ethernet Support 2 Multichannel (Mbps) HDLC Support 10 10 10/100 10/100 N/A Yes Yes Yes ATM Support N/A Yes Yes Yes Serial communications controller (SCC) Up to 4 channels at 40 MHz or 2 channels at 25 MHz Table 34 identifies the packages and operating frequencies available for the MPC860. Table 34. MPC860 Family Package/Frequency Availability Package Type Ball grid array ZP suffix — Leaded ZQ suffix — Leaded VR suffix — Lead-Free are available as needed Freq (MHz) / Temp (Tj) 50 0° to 95°C Package ZP/ZQ 1 Order Number MPC855TZQ50D4 MPC860DEZQ50D4 MPC860DTZQ50D4 MPC860ENZQ50D4 MPC860SRZQ50D4 MPC860TZQ50D4 MPC860DPZQ50D4 MPC860PZQ50D4 MPC855TZQ50D4R2 MPC860DEZQ50D4R2 MPC860ENZQ50D4R2 MPC860SRZQ50D4R2 MPC860TZQ50D4R2 MPC860DPZQ50D4R2 KMPC855TZQ50D4 KMPC860DEZQ50D4 KMPC860DTZQ50D4 KMPC860TZQ50D4 KMPC860SRZQ50D4 MPC855TZQ66D4 MPC860DEZQ66D4 MPC860DTZQ66D4 MPC860ENZQ66D4 MPC860SRZQ66D4 MPC860TZQ66D4 MPC860DPZQ66D4 MPC860PZQ66D4 MPC860SRZQ66D4R2 MPC860PZQ66D4R2 Tape and Reel Sample 66 0° to 95°C ZP/ZQ 1 Tape and Reel MPC860 Family Hardware Specifications, Rev. 7 72 Freescale Semiconductor Mechanical Data and Ordering Information Table 34. MPC860 Family Package/Frequency Availability (continued) Package Type Freq (MHz) / Temp (Tj) Package Sample Order Number KMPC855TZQ66D4 KMPC860SRZQ66D4 KMPC860TZQ66D4 KMPC860ENZQ66D4 KMPC860PZQ66D4 MPC855TZQ80D4 MPC860DEZQ80D4 MPC860DTZQ80D4 MPC860ENZQ80D4 MPC860SRZQ80D4 MPC860TZQ80D4 MPC860DPZQ80D4 MPC860PZQ80D4 MPC860PZQ80D4R2 KMPC855TZQ80D4 KMPC860DEZQ80D4 KMPC860DTZQ80D4 KMPC860ENZQ80D4 KMPC860SRZQ80D4 KMPC860TZQ80D4 KMPC860DPZQ80D4 KMPC860PZQ80D4 MPC855TCZQ50D4 MPC860DECZQ50D4 MPC860DTCZQ50D4 MPC860ENCZQ50D4 MPC860SRCZQ50D4 MPC860TCZQ50D4 MPC860DPCZQ50D4 MPC860PCZQ50D4 MPC855TCZQ50D4R2 MPC855TCZQ66D4 MPC860ENCZQ66D4 MPC860SRCZQ66D4 MPC860TCZQ66D4 MPC860DPCZQ66D4 MPC860PCZQ66D4 80 0° to 95°C ZP/ZQ 1 Tape and Reel Sample Ball grid array (CZP suffix) CZP suffix — Leaded CZQ suffix — Leaded CVR suffix — Lead-Free are available as needed 50 –40° to 95°C ZP/ZQ 1 Tape and Reel 66 –40° to 95°C ZP/ZQ 1 1 The ZP package is no longer recommended for use. The ZQ package replaces the ZP package. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 73 Mechanical Data and Ordering Information 14.1 Pin Assignments Figure 75 shows the top view pinout of the PBGA package. For additional information, see the MPC860 PowerQUICC User’s Manual, or the MPC855T User’s Manual. NOTE: This is the top view of the device. W PD10 PD8 PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 DP2 CLKOUT IPA3 V PD14 PD13 PD9 PD6 M_Tx_EN IRQ0 D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP3 DP0 N/C VSSSYN1 U PA0 PA1 PB14 PD15 PC5 PC4 PD4 PD11 PD5 PD7 IRQ1 D8 D23 D17 D11 D9 D16 D15 D19 D22 D21 D25 D26 D31 D30 IPA6 IPA5 IPA0 IPA4 IPA1 IPA2 IPA7 N/C VSSSYN T VDDH D12 VDDH XFC VDDSYN PC6 PA2 PB15 PD12 R VDDH WAIT_B WAIT_A PORESET KAPWR P PA4 PB17 PA3 VDDL GND GND VDDL RSTCONF SRESET XTAL N PB19 PA5 PB18 PB16 HRESET TEXP EXTCLK EXTAL M PA7 PC8 PA6 PC7 MODCK2 BADDR28 BADDR29 VDDL L PB22 PC9 PA8 PB20 OP0 AS OP1 MODCK1 K PC10 PA9 PB23 PB21 GND BADDR30 IPB6 ALEA IRQ4 J PC11 PB24 PA10 PB25 IPB5 IPB1 IPB2 ALEB H VDDL M_MDIO TDI TCK M_COL IRQ2 IPB0 IPB7 G TRST TMS TDO PA11 GND VDDH GND VDDH BR IRQ6 IPB4 IPB3 F PB26 PC12 PA12 VDDL VDDL TS IRQ3 BURST E PB27 PC13 PA13 PB29 CS3 BI BG BB D PB28 PC14 PA14 PC15 A8 N/C N/C A15 A19 A25 A18 BSA0 GPLA0 N/C CS6 CS2 GPLA5 BDIP TEA C PB30 PA15 PB31 A3 A9 A12 A16 A20 A24 A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7 CS0 TA GPLA4 B A0 A1 A4 A6 A10 A13 A17 A21 A23 A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4 A A2 19 18 A5 17 A7 16 A11 15 A14 14 A27 13 A29 12 A30 11 A28 10 A31 9 VDDL BSA2 8 7 WE1 6 WE3 5 CS4 4 CE2A 3 CS1 2 1 Figure 75. Pinout of the PBGA Package 14.2 Mechanical Dimensions of the PBGA Package Figure 76 shows the mechanical dimensions of the ZP PBGA package. MPC860 Family Hardware Specifications, Rev. 7 74 Freescale Semiconductor Mechanical Data and Ordering Information C 4X D 0.2 A 0.2 C 0.25 C 0.35 C E2 E D2 TOP VIEW B A2 A3 A1 A D1 18X e W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 SIDE VIEW E1 MILLIMETERS MIN MAX --2.05 0.50 0.70 0.95 1.35 0.70 0.90 0.60 0.90 25.00 BSC 22.86 BSC 22.40 22.60 1.27 BSC 25.00 BSC 22.86 BSC 22.40 22.60 DIM A A1 A2 A3 b D D1 D2 e E E1 E2 357X b BOTTOM VIEW 0.3 M C A B 0.15 M C NOTE 1. 2. 3. Dimensions and tolerance per ASME Y14.5M, 1994 Dimensions in millimeters Dimension b is the maximum solder ball diameter Figure 76. Mechanical Dimensions and Bottom Surface Nomenclature of the ZP PBGA Package Figure 77 shows the mechanical dimensions of the ZQ PBGA package. MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 75 Mechanical Data and Ordering Information NOTE 1. 2. 3. All Dimensions in millimeters Dimensions and tolerance per ASME Y14.5M, 1994 Maximum Solder Ball Diameter measured parallel to Datum A Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the ZQ PBGA Package MPC860 Family Hardware Specifications, Rev. 7 76 Freescale Semiconductor Document Revision History 15 Document Revision History Table 35 lists significant changes between revisions of this hardware specification. Table 35. Document Revision History Revision 5.1 6 6.1 Date 11/2001 10/2002 11/2002 Changes • Revised template format, removed references to MAC functionality, changed Table 7 B23 max value @ 66 MHz from 2ns to 8ns, added this revision history table • Added the MPC855T. Corrected Figure 25 on page 36. • Corrected UTOPIA RXenb* and TXenb* timing values • Changed incorrect usage of Vcc to Vdd • Corrected dual port RAM to 8 Kbytes • Changed B28a through B28d and B29d to show that TRLX can be 0 or 1 • Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family Users Manual • Nontechnical reformatting • •Added Section 11.2 on the Port C interrupt pins • •Nontechnical reformatting • Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard • Replaced the thermal characteristics in Table 4 by the ZQ package • Add the new parts to the Ordering and Availablity Chart in Table 34 • Added the mechanical spec of the ZQ package in Figure 77 • Removed all of the old revisions from Table 5 6.2 8/2003 6.3 7.0 9/2003 9/2004 MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 77 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 Family Hardware Specifications, Rev. 7 78 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 79 How to Reach Us: Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004. MPC860EC Rev. 7 09/2004