MR2A16A_1

Freescale Semiconductor Data Sheet Document Number: MR2A16A Rev. 4, 6/2007 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM Introduction The MR2A16A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 262,144 words of 16 bits. The MR2A16A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for significant system design flexibility without bus contention. Because the MR2A16A has separate byte-enable controls (LB and UB), individual bytes can be written and read. MRAM is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. The MR2A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. The MR2A16A is available in a 400-mil, 44-lead plastic small-outline TSOP type-II package with an industry-standard center power and ground SRAM pinout. The MR2A16A is available in Commercial (0˚C to 70˚C), Industrial (-40˚C to 85˚C) and Extended (-40˚C to 105˚C) ambient temperature ranges. Features • • MR2A16A 44-TSOP Case 924A-02 Single 3.3-V power supply Commercial temperature range (0˚C to 70˚C), Industrial temperature range (-40˚C to 85˚C) and Extended temperature range (-40˚C to 105˚C) Symmetrical high-speed read and write with fast access time (35 ns) Flexible data bus control — 8 bit or 16 bit access Equal address and chip-enable access times Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss All inputs and outputs are transistor-transistor logic (TTL) compatible Fully static operation Full nonvolatile operation with 20 years minimum data retention • • • • • • • © Freescale Semiconductor, Inc., 2004, 2006, 2007. All rights reserved. Device Pin Assignment OUTPUT ENABLE BUFFER G UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE A[17:0] ADDRESS BUFFERS 18 8 10 ROW DECODER COLUMN DECODER SENSE AMPS UPPER BYTE OUTPUT BUFFER LOWER BYTE OUTPUT BUFFER 8 FINAL WRITE DRIVERS UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER 8 8 E CHIP ENABLE BUFFER 256K x 16 BIT MEMORY ARRAY 16 8 8 W WRITE ENABLE BUFFER 8 DQU[15:8] 16 8 UB LB BYTE ENABLE BUFFER LB UB UPPER BYTE WRITE ENABLE LOWER BYTE WRITE ENABLE 8 DQL[7:0] Figure 1. Block Diagram Device Pin Assignment A0 A1 A2 A3 A4 E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 NC A14 A13 A12 A11 A10 Table 1. Pin Functions Signal Name A[17:0] E W G UB LB DQL[7:0] DQU[15:8] VDD VSS NC Function Address input Chip enable Write enable Output enable Upper byte select Lower byte select Data I/O, lower byte Data I/O, upper byte Power supply Ground Do not connect this pin Figure 2. MR2A16A in 44-Pin TSOP Type II Package MR2A16A Data Sheet, Rev. 4 2 Freescale Semiconductor Electrical Specifications Table 2. Operating Modes E1 H L L L L L L L L G1 X H X L L L X X X W1 X H X H H H L L L LB1 X X H L H L L H L UB1 X X H H L L H L L Mode Not selected Output disabled Output disabled Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write VDD Current ISB1, ISB2 IDDA IDDA IDDA IDDA IDDA IDDA IDDA IDDA DQL[7:0]2 Hi-Z Hi-Z Hi-Z DOut Hi-Z DOut DIn Hi-Z DIn DQU[15:8]2 Hi-Z Hi-Z Hi-Z Hi-Z DOut DOut Hi-Z DIn DIn NOTES: 1 H = high, L = low, X = don’t care 2 Hi-Z = high impedance Electrical Specifications Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 3 Electrical Specifications Table 3. Absolute Maximum Ratings1 Parameter Supply voltage2 pin2 dissipation3 Voltage on any Package power Symbol VDD VIn IOut PD TBias Tstg TLead Hmax_write Value –0.5 to 4.0 –0.5 to VDD + 0.5 ±20 0.600 –10 to 85 –45 to 95 –45 to 110 –55 to 150 260 15 25 25 100 100 100 Unit V V mA W ˚C ˚C ˚C Oe Output current per pin Temperature under bias MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Storage temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Maximum magnetic field during read or standby MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Hmax_read Oe NOTES: 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to V . SS 3 Power dissipation capability depends on package characteristics and use environment. MR2A16A Data Sheet, Rev. 4 4 Freescale Semiconductor Electrical Specifications Table 4. Operating Conditions Parameter Power supply voltage MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Write inhibit voltage MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Input high voltage Input low voltage Operating temperature MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) Symbol VDD Min 3.01 3.02 3.02 2.5 2.5 2.5 2.2 –0.54 0 -40 -40 Typ 3.3 3.3 3.3 2.7 2.7 2.7 — — Max 3.6 3.6 3.6 3.01 3.02 3.02 VDD + 0.33 0.8 70 85 105 Unit V VWI V VIH VIL TA V V ˚C NOTES: 1 After power up or if V DD falls below VWI, a waiting period of 2 μs must be observed, and E and W must remain high for 2 μs. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 2 After power up or if V DD falls below VWI, a waiting period of 2 ms must be observed, and E and W must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 3 V (max) = V IH DD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 4 V (min) = –0.5 Vdc; V (min) = –2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA. IL IL MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 5 Electrical Specifications Direct Current (dc) Table 5. dc Characteristics Parameter Input leakage current Output leakage current Output low voltage (IOL = +4 mA) (IOL = +100 μA) Output high voltage (IOH = –4 mA) (IOH = –100 mA) Symbol Ilkg(I) Ilkg(O) VOL Min — — — Typ — — — Max ±1 ±1 0.4 VSS + 0.2 — Unit μA μA V VOH 2.4 VDD – 0.2 — V Table 6. Power Supply Characteristics Parameter ac active supply current — read (IOut = 0 mA, VDD = max) MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) modes1 IDDR 55 TBD TBD 80 TBD TBD mA Symbol Typ Max Unit ac active supply current — write modes1 (VDD = max) MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) ac standby current (VDD = max, E = VIH) (no other restrictions on other inputs) MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) CMOS standby current (E ≥ VDD – 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) (VDD = max, f = 0 MHz) MR2A16ATS35C (Commercial) MR2A16ACYS35 (Industrial) MR2A16AVYS35 (Extended) IDDW 105 TBD TBD 155 TBD TBD mA ISB1 18 TBD TBD 28 TBD TBD mA ISB2 9 TBD TBD 12 TBD TBD mA NOTES: 1 All active current measurements are measured with one address transition per cycle. MR2A16A Data Sheet, Rev. 4 6 Freescale Semiconductor Electrical Specifications Table 7. Capacitance1 Parameter Address input capacitance Control input capacitance Input/output capacitance Symbol CIn CIn CI/O Typ — — — Max 6 6 8 Unit pF pF pF NOTES: 1 f = 1.0 MHz, dV = 3.0 V, TA = 25˚C, periodically sampled rather than 100% tested. Table 8. ac Measurement Conditions Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Value 1.5 V 1.5 V 0 or 3.0 V 2 ns See Figure 3A See Figure 3B +3.3 V ZD = 50 Ω OUTPUT RL = 50 Ω VL = 1.5 V OUTPUT 600 Ω 5 pF 725 Ω A B Figure 3. Output Load for ac Test MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 7 Timing Specifications Timing Specifications Read Mode Table 9. Read Cycle Timing1, 2 Parameter Read cycle time Address access time Enable access time3 Output enable access time Byte enable access time Output hold from address change Enable low to output active4, 5 active4, 5 active4, 5 Hi-Z4, 5 Output enable low to output Byte enable low to output Enable high to output Byte high to output Symbol tAVAV tAVQV tELQV tGLQV tBLQV tAXQX tELQX tGLQX tBLQX tEHQZ tGHQZ tBHQZ Min 35 — — — — 3 3 0 0 0 0 0 Max — 35 35 15 15 — — — — 15 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns Hi-Z4, 5 Output enable high to output Hi-Z4, 5 NOTES: 1 W is high for read cycle. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read and write cycles. 3 Addresses valid before or at the same time E goes low. 4 This parameter is sampled and not 100% tested. 5 Transition is measured ±200 mV from steady-state voltage. MR2A16A Data Sheet, Rev. 4 8 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID NOTES: 1 Device is continuously selected (E ≤ VIL, G ≤ VIL). Figure 4. Read Cycle 11 tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX LB, UB (BYTE ENABLE) tBLQV tBLQX Q (DATA OUT) DATA VALID tBHQZ tGHQZ tEHQZ Figure 5. Read Cycle 2 MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 9 Timing Specifications Write Mode Table 10. Write Cycle Timing 1 (W Controlled)1, 2, 3, 4, 5 Parameter Write cycle time6 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Write pulse width (G high) Write pulse width (G low) Data valid to end of write Data hold time Write low to data Hi-Z7, 8, 9 active7, 8, 9 Write high to output Write recovery time Symbol tAVAV tAVWL tAVWH tAVWH tWLWH tWLEH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 35 0 18 20 15 15 10 0 0 3 12 Max — — — — — — — — 12 — — Unit ns ns ns ns ns ns ns ns ns ns ns NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 This parameter is sampled and not 100% tested. 8 Transition is measured ±200 mV from steady-state voltage. 9 At any given voltage or temperature, t WLQZ max < tWHQX min. MR2A16A Data Sheet, Rev. 4 10 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH tAVWL tWHAX W (WRITE ENABLE) LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWLQZ Q (DATA OUT) Hi-Z Hi-Z tWHQX DATA VALID tWHDX Figure 6. Write Cycle 1 (W Controlled) MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 11 Timing Specifications Table 11. Write Cycle Timing 2 (E Controlled)1, 2, 3, 4, 5 Parameter Write cycle time6 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Enable to end of write (G high) Enable to end of write (G low)7, 8 Data valid to end of write Data hold time Write recovery time Symbol tAVAV tAVEL tAVEH tAVEH tELEH tELWH tELEH tELWH tDVEH tEHDX tEHAX Min 35 0 18 20 15 15 10 0 12 Max — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. 8 If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. MR2A16A Data Sheet, Rev. 4 12 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tELWH tEHAX LB, UB (BYTE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) Hi-Z Figure 7. Write Cycle 2 (E Controlled) MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 13 Timing Specifications Table 12. Write Cycle Timing 3 (LB/UB Controlled)1, 2, 3, 4, 5, 6 Parameter Write cycle time7 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Byte pulse width (G high) Byte pulse width (G low) Data valid to end of write Data hold time Write recovery time Symbol tAVAV tAVBL tAVBH tAVBH tBLEH tBLWH tBLEH tBLWH tDVBH tBHDX tBHAX Min 35 0 18 20 15 15 10 0 12 Max — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 7 All write cycle timings are referenced from the last valid address to the first transition address. MR2A16A Data Sheet, Rev. 4 14 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVBH E (CHIP ENABLE) tAVBL tBLEH tBLWH tBHAX LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) DATA VALID Q (DATA OUT) Hi-Z Hi-Z Figure 8. Write Cycle 3 (LB/UB Controlled) MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 15 Ordering Information Ordering Information This product is available in Commercial, Industrial, and Extended temperature versions. Freescale's semiconductor products can be classified into the following tiers: "Commercial", "Industrial" and “Extended.” A product should only be used in applications appropriate to its tier as shown below. For questions, please contact a Freescale sales representative. • • Commercial — Typically 5 year applications - personal computers, PDA's, portable telecom products, consumer electronics, etc. Industrial, Extended — Typically 10 year applications - installed telecom equipment, workstations, servers, etc. These products can also be used in Commercial applications. Current Part Numbering System (Industrial and Extended devices) (Order by Full Part Number) MR Freescale MRAM Memory Prefix Density Code (0 = 1 Mb, 1 = 2 Mb, 2 = 4 Mb, 4 = 16 Mb) Memory Type (A = async, S = sync) 2 A 16 A V YS 35 Timing Set (35 = 35 ns) Package Type (YS = TSOP II) Operating Temperature Range (C = -40°C to 85°C, V = -40°C to 105°C) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) Legacy Part Numbering System (Commercial devices) (Order by Full Part Number) MR Freescale MRAM Memory Prefix Density Code (0 = 1 Mb, 1 = 2 Mb, 2 = 4 Mb, 4 = 16 Mb) Memory Type (A = async, S = sync) 2 A 16 A TS 35 C Operating Temperature Range (C = 0°C to 70°C) Timing Set (35 = 35 ns) Package Type (TS = TSOP II) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) MR2A16A Data Sheet, Rev. 4 16 Freescale Semiconductor Package Information Package Information Table 13. Package Information Device MR2A16A Pin Count 44 Package Type TSOP Type II Designator TS/YS Case No. 924A-02 Document No. 98ASS23673W RoHS Compliant True Revision History Revision History Revision Date Description of Change Added new Industrial and Extended temperature product information; updated part ordering information; changed to 2 ms delay after power up; power supply characteristics values updated to TBD for industrial and extended temperature devices. 4 18 Jun 2007 Mechanical Drawing The following pages detail the package available to MR2A16A. MR2A16A Data Sheet, Rev. 4 Freescale Semiconductor 17 How to Reach Us: USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Japan: Freescale Semiconductor Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor H.K. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004, 2006, 2007. MR2A16A Rev. 4, 6/2007