MSC7119

Freescale Semiconductor Data Sheet Document Number: MSC7119 Rev. 8, 4/2008 MSC7119 Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC • StarCore® SC1400 DSP extended core with one SC1400 DSP core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, programmable interrupt controller (PIC), and low-power Wait and Stop processing modes. • 192 Kbyte M2 memory for critical data and temporary data buffering. • 8 Kbyte boot ROM. • AHB-Lite crossbar switch that allows parallel data transfers between four master ports and six slave ports, where each port connects to an AHB-Lite bus; fixed or round robin priority programmable at each slave port; programmable bus parking at each slave port; low power mode. • Internal PLL generates up to 300 MHz clock for the SC1400 core and up to 150 MHz for the crossbar switch, DMA channels, M2 memory, and other peripherals. • Clock synthesis module provides predivision of PLL input clock; independent clocking of the internal timers and DDR module; programmable operation in the SC1400 low power Stop mode; independent shutdown of different regions of the device. • Enhanced 16-bit wide host interface (HDI16) provides a glueless connection to industry-standard microcomputers, microprocessors, and DSPs and can also operate with an 8-bit host data bus, making if fully compatible with the DSP56300 HI08 from the external host side. • DDR memory controller that supports byte enables for up to a 32-bit data bus; glueless interface to 150 MHz 14-bit page mode DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte; and 16-bit or 32-bit external data bus. • Programmable memory interface with independent read buffers, programmable predictive read feature for each buffer, and a write buffer. • System control unit performs software watchdog timer function; includes programmable bus time-out monitors on AHB-Lite slave buses; includes bus error detection and programmable time-out monitors on AHB-Lite master buses; and has address out-of-range detection on each crossbar switch buses. • Event port collects and counts important signal events including DMA and interrupt requests and trigger events such as interrupts, breakpoints, DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. MAP-BGA–400 17 mm × 17 mm • Multi-channel DMA controller with 32 time-multiplexed unidirectional channels, priority-based time-multiplexing between channels using 32 internal priority levels, fixed- or round-robin-priority operation, major-minor loop structure, and DONE or DRACK protocol from requesting units. • Two independent TDM modules with independent receive and transmit, programmable sharing of frame sync and clock, programmable word size (8 or 16-bit), hardware-base A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to 128 channels, with glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses. • Ethernet controller with support for 10/100 Mbps MII/RMII designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™; with internal receive and transmit FIFOs and a FIFO controller; direct access to internal memories via its own DMA controller; full and half duplex operation; programmable maximum frame length; virtual local area network (VLAN) tag and priority support; retransmission of transmit FIFO following collision; CRC generation and verification for inbound and outbound packets; and address recognition including promiscuous, broadcast, individual address. hash/exact match, and multicast hash match. • UART with full-duplex operation up to 5.0 Mbps. • Up to 41 general-purpose input/output (GPIO) ports. • I2C interface that allows booting from EEPROM devices up to 1 Mbyte. • Two quad timer modules, each with sixteen configurable 16-bit timers. • fieldBIST™ unit detects and provides visibility into unlikely field failures for systems with high availability to ensure structural integrity, that the device operates at the rated speed, is free from reliability defects, and reports diagnostics for partial or complete device inoperability. • Standard JTAG interface allows easy integration to system firmware and internal on-chip emulation (OCE10) module. • Optional booting external host via 8-bit or 16-bit access through the HDI16, I2C, or SPI using in the boot ROM to access serial SPI Flash/EEPROM devices; different clocking options during boot with the PLL on or off using a variety of input frequency ranges. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Table of Contents 1 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19 2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19 2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41 3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41 3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42 3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49 3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .54 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . Asynchronous Input Signal Timing . . . . . . . . . . . . . . . Serial Management Channel Timing . . . . . . . . . . . . . Read Timing Diagram, Single Data Strobe . . . . . . . . Read Timing Diagram, Double Data Strobe . . . . . . . . Write Timing Diagram, Single Data Strobe. . . . . . . . . Write Timing Diagram, Double Data Strobe . . . . . . . . Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . Test Access Port Timing Diagram . . . . . . . . . . . . . . . TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . . Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . . Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . . Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . . Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . . PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . SSTL Termination Techniques . . . . . . . . . . . . . . . . . . SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 29 30 30 31 33 33 34 34 35 35 36 37 37 37 38 38 39 40 40 40 43 44 45 46 47 48 54 55 3 4 5 6 7 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. MSC7119 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3 MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Timing Diagram for a Reset Configuration Write . . . . 25 DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26 DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27 DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 28 MSC7119 Data Sheet, Rev. 8 2 Freescale Semiconductor JTAG Port JTAG DMA (32 Channel) AMDMA ASM2 MUX 64 128 128 64 to IPBus SC1400 Core OCE10 M2 SRAM (192 KB) Boot ROM (8 KB) External Memory Interface External Bus 32 Trace Buffer (8 KB) DSP Extended Core 64 128 ASEMI 64 from IPBus Interrupt Control Fetch Unit Instruction Cache (16 KB) Extended Core Interface AMIC 128 Interrupts HDI16 Port TDM AHB-Lite Crossbar Switch MUX ASTH 64 Host Interface (HDI16) 32 2 TDMs APB Bridge PLL/Clock APB AMEC 64 ASAPB 32 PLL/Clock I2C RS-232 GPIO I2C UART GPIO System Ctrl 64 64 64 64 ASIB 32 IB Bridge 128 M1 SRAM (256 KB) ASM1 P XA XB AMENT 32 Watchdog Event Port BTMs Events Ethernet MAC Note: The arrows show the direction of the transfer. MII/RMII to EMI to DMA to/from OCE10 Timers IPBus Figure 1. MSC7119 Block Diagram MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 3 Pin Assignments 1 1.1 Pin Assignments MAP-BGA Ball Layout Diagrams Top View 1 2 GND This section includes diagrams of the MSC7119 package ball grid array layouts and pinout allocation tables. Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. 3 DQM1 4 DQS2 5 CK 6 CK 7 HD15 8 HD12 9 HD10 10 HD7 11 HD6 12 HD4 13 HD1 14 HD0 15 GND 16 BM3 17 NC 18 NC 19 NC 20 NC A GND B VDDM NC CS0 DQM2 DQS3 DQS0 CKE WE HD14 HD11 HD8 HD5 HD2 NC BM2 NC NC NC NC NC C D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS HD13 HD9 HD3 NC NC NC NC NC NC NC NC D VDDM D28 D27 GND VDDM VDDM VDDM VDDM VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDC NC NC NC E GND D26 D31 VDDM VDDM VDDC VDDC VDDC VDDC VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDC VDDC NC NC NC F VDDM D15 D29 VDDC VDDC VDDC GND GND GND VDDM VDDM GND GND GND VDDIO VDDC VDDC NC NC NC G GND D13 GND VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC NC NC H D14 D12 D11 VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC HA2 HA1 J D10 VDDM D9 VDDM VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDC HA3 HACK HREQ K D0 GND D8 VDDC VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC HA0 HDDS HDS L D1 GND D3 VDDC VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDIO VDDC HCS2 HCS1 HRW M D2 VDDM D5 VDDM VDDM GND GND GND GND GND GND GND GND GND GND VDDC VDDC SDA UTXD URXD N D4 D6 VREF VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDC VDDC CLKIN SCL VSSPLL P D7 D17 D16 VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC PORESET TPSEL VDDPLL R GND D19 D18 VDDM VDDM VDDM GND VDDM GND VDDM GND GND VDDIO GND VDDIO VDDIO VDDC TDO EE0 TEST0 T VDDM D20 D22 VDDM VDDM VDDC VDDM VDDM VDDC VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDC VDDC MDIO TMS HRESET U GND D21 D23 VDDM VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC COL TCK TRST V VDDM NC A13 A11 A10 A5 A2 BA0 NC EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS TDI W GND VDDM A12 A8 A7 A6 A3 NC EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC Y VDDM GND A9 A1 A0 A4 BA1 NMI EVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1 GND RX_DV Figure 2. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View MSC7119 Data Sheet, Rev. 8 4 Freescale Semiconductor Pin Assignments Bottom View 20 A NC 19 NC 18 NC 17 NC 16 BM3 15 GND 14 HD0 13 HD1 12 HD4 11 HD6 10 HD7 9 HD10 8 HD12 7 HD15 6 CK 5 CK 4 DQS2 3 DQM1 2 GND 1 GND B NC NC NC NC NC BM2 NC HD2 HD5 HD8 HD11 HD14 WE CKE DQS0 DQS3 DQM2 CS0 NC VDDM C NC NC NC NC NC NC NC NC HD3 HD9 HD13 CAS RAS DQS1 DQM0 DQM3 CS1 D25 D30 D24 D NC NC NC VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDDM VDDM VDDM VDDM GND D27 D28 VDDM E NC NC NC VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDD VDD VDD VDD VDDM VDDM D31 D26 GND F NC NC NC VDD VDD VDDIO GND GND GND VDDM VDDM GND GND GND VDD VDD VDD D29 D15 VDDM G NC NC NC VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM GND D13 GND H HA1 HA2 NC VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM D11 D12 D14 J HREQ HACK HA3 VDD VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM VDDM D9 VDDM D10 K HDS HDDS HA0 VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDD D8 GND D0 L HRW HCS1 HCS2 VDD VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDD D3 GND D1 M URXD UTXD SDA VDD VDD GND GND GND GND GND GND GND GND GND GND VDDM VDDM D5 VDDM D2 N VSSPLL SCL CLKIN VDD VDD VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM VREF D6 D4 P VDDPLL TPSEL PORESET VDD VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM D16 D17 D7 R TEST0 EE0 TDO VDD VDDIO VDDIO GND VDDIO GND GND VDDM GND VDDM GND VDDM VDDM VDDM D18 D19 GND T HRESET TMS MDIO VDD VDD VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDD VDDM VDDM VDD VDDM VDDM D22 D20 VDDM U TRST TCK COL VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDM D23 D21 GND V TDI CRS TX_EN RXD0 RXD2 TX_ER T1TD T1RFS T0TCK EVNT4 EVNT0 NC BA0 A2 A5 A10 A11 A13 NC VDDM W MDC RX_ER TXCLK TXD1 RXD3 TXD2 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1 NC A3 A6 A7 A8 A12 VDDM GND Y RX_DV GND RXD1 TXD0 RXCLK TXD3 T1TCK T1RCK TOTD T0RD T0RCK EVNT3 NMI BA1 A4 A0 A1 A9 GND VDDM Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 5 Pin Assignments 1.2 Signal List By Ball Location Table 1. MSC7119 Signals by Ball Designator Signal Names Table 1 lists the signals sorted by ball number and configuration. Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled GND GND DQM1 DQS2 CK CK GPIC7 GPIC4 GPIC2 reserved reserved reserved reserved reserved GND BM3 GPID8 NC NC NC NC VDDM NC CS0 DQM2 DQS3 DQS0 CKE WE GPIC6 GPIC3 GPIC0 reserved reserved GPOC6 GPOC3 GPOC0 GPOD8 GPOC7 GPOC4 GPOC2 Hardware Controlled Primary Alternate A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 reserved HD14 HD11 HD8 HD5 HD2 MSC7119 Data Sheet, Rev. 8 6 Freescale Semiconductor Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled NC BM2 GPID7 NC NC NC NC NC D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS GPIC5 GPIC1 reserved NC NC NC NC NC NC NC NC VDDM D28 D27 GND VDDM VDDM VDDM VDDM VDDM GPOC5 GPOC1 HD13 HD9 HD3 GPOD7 reserved Hardware Controlled GPO Enabled Primary Alternate B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 7 Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDC NC NC NC GND D26 D31 VDDM VDDM VDDC VDDC VDDC VDDC VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDC VDDC NC NC NC VDDM D15 D29 VDDC VDDC Hardware Controlled Primary Alternate D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 MSC7119 Data Sheet, Rev. 8 8 Freescale Semiconductor Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled VDDC GND GND GND VDDM VDDM GND GND GND VDDIO VDDC VDDC NC NC NC GND D13 GND VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC NC NC D14 Hardware Controlled Primary Alternate F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 9 Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled D12 D11 VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC reserved reserved D10 VDDM D9 VDDM VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDC HA2 HA1 Hardware Controlled GPO Enabled Primary Alternate H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 MSC7119 Data Sheet, Rev. 8 10 Freescale Semiconductor Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) GPIC11 reserved HDSP reserved D0 GND D8 VDDC VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC reserved reserved reserved D1 GND D3 VDDC VDDM GND GND GND GND GND GND GND GND HA0 HDDS HDS/HDS or HWR/HWR Software Controlled Interrupt Enabled GPO Enabled GPOC11 Hardware Controlled Primary HA3 HACK/HACK or HRRQ/HRRQ HREQ/HREQ or HTRQ/HTRQ Alternate J18 J19 J20 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 11 Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled VDDIO VDDIO VDDIO VDDC GPIB11 reserved reserved D2 VDDM D5 VDDM VDDM GND GND GND GND GND GND GND GND GND GND VDDC VDDC GPIA14 GPIA12 GPIA13 IRQ15 IRQ3 IRQ2 D4 D6 VREF VDDM VDDM VDDM GND GND GND GPOA14 GPOA12 GPOA13 SDA UTXD URXD GPOB11 HCS2/HCS2 HCS1/HCS1 HRW or HRD/HRD Hardware Controlled Primary Alternate L14 L15 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N6 N7 N8 N9 MSC7119 Data Sheet, Rev. 8 12 Freescale Semiconductor Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled GND GND GND GND GND VDDIO VDDC VDDC CLKIN GPIA15 IRQ14 VSSPLL D7 D17 D16 VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC PORESET TPSEL VDDPLL GND D19 D18 VDDM VDDM GPOA15 SCL Hardware Controlled Primary Alternate N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 13 Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled GPO Enabled VDDM GND VDDM GND VDDM GND GND VDDIO GND VDDIO VDDIO VDDC TDO reserved TEST0 VDDM D20 D22 VDDM VDDM VDDC VDDM VDDM VDDC VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDC VDDC reserved TMS HRESET GND MDIO EE0/DBREQ Hardware Controlled Primary Alternate R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 MSC7119 Data Sheet, Rev. 8 14 Freescale Semiconductor Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled D21 D23 VDDM VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC reserved TCK TRST VDDM NC A13 A11 A10 A5 A2 BA0 NC reserved SWTE GPIA8 GPIA4 GPIA0 GPIA28 GPID6 GPIA22 IRQ22 GPIA16 IRQ12 IRQ6 IRQ1 IRQ11 IRQ17 GPOA16 GPOA8 GPOA4 GPOA0 GPOA28 GPOD6 GPOA22 TX_ER RXD2 RXD0 EVNT0 EVNT4 T0TCK T1RFS T1TD reserved reserved COL Hardware Controlled GPO Enabled Primary Alternate U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 15 Pin Assignments Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled IRQ24 reserved TDI GND VDDM A12 A8 A7 A6 A3 NC GPIA17 BM0 GPIA10 GPIA7 GPIA3 GPIA1 GPID4 GPIA27 GPIA19 GPIA23 GPIA26 H8BIT IRQ18 IRQ19 IRQ23 IRQ26 reserved VDDM GND A9 A1 A0 A4 BA1 reserved BM1 GPIA11 GPIA9 GPIA6 GPIA5 IRQ0 GPIC15 IRQ4 NMI GPOC15 GPOA11 GPOA9 GPOA6 GPOA5 reserved EVNT3 T0RCK T0RD T0TD T1RCK GPIC14 IRQ5 IRQ7 IRQ8 IRQ10 IRQ13 GPOA17 GPOC14 GPOA10 GPOA7 GPOA3 GPOA1 GPOD4 GPOA27 GPOA19 GPOA23 GPOA26 TXD2 RXD3 TXD1 TXCLK or REFCLK RX_ER MDC EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS reserved reserved CLKO Hardware Controlled GPO Enabled GPOA24 Primary TX_EN CRS Alternate V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 GPIA24 MSC7119 Data Sheet, Rev. 8 16 Freescale Semiconductor Electrical Characteristics Table 1. MSC7119 Signals by Ball Designator (continued) Signal Names Number End of Reset GPI Enabled (Default) Software Controlled Interrupt Enabled IRQ9 IRQ16 GPID5 GPIA20 GPIA21 IRQ20 IRQ21 GND GPIA25 IRQ25 GPOA25 RX_DV or CRS_DV Hardware Controlled GPO Enabled GPOA2 GPOA29 GPOD5 GPOA20 GPOA21 TXD3 RXCLK TXD0 RXD1 Primary T1TCK Alternate Y14 Y15 Y16 Y17 Y18 Y19 Y20 GPIA2 GPIA29 reserved reserved 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC711x Reference Manual. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 17 Electrical Characteristics Table 2 describes the maximum electrical ratings for the MSC7119. Table 2. Absolute Maximum Ratings Rating Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Input voltage Reference voltage Maximum operating temperature Minimum operating temperature Storage temperature range Notes: 1. 2. 3. Symbol VDDC VDDM VDDPLL VDDIO VIN VREF TJ TA TSTG Value 1.5 4.0 1.5 –0.2 to 4.0 (GND – 0.2) to 4.0 4.0 105 –40 –55 to +150 Unit V V V V V V °C °C °C Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 3.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (TJ). 2.2 Recommended Operating Conditions Table 3. Recommended Operating Conditions Rating Symbol VDDC VDDM VDDPLL VDDIO VREF TJ TA Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Value 1.14 to 1.26 2.38 to 2.63 1.14 to 1.26 3.14 to 3.47 1.19 to 1.31 maximum: 105 minimum: –40 Unit V V V V V °C °C Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Reference voltage Operating temperature range MSC7119 Data Sheet, Rev. 8 18 Freescale Semiconductor Electrical Characteristics 2.3 Thermal Characteristics Table 4. Thermal Characteristics for MAP-BGA Package MAP-BGA 17 Characteristic Symbol Natural Convection 39 23 12 7 2 Table 4 describes thermal characteristics of the MSC7119 for the MAP-BGA package. × 17 mm5 200 ft/min (1 m/s) airflow 31 20 Unit Junction-to-ambient1, 2 Junction-to-ambient, four-layer board1, 3 Junction-to-board4 Junction-to-case5 Junction-to-package-top6 Notes: 1. RθJA RθJA RθJB RθJC Ψ JT °C/W °C/W °C/W °C/W °C/W 2. 3. 4. 5. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Section 3.1, Thermal Design Considerations explains these characteristics in detail. 2.4 Note: DC Electrical Characteristics The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO and VDDC vary by +2 percent or both vary by –2 percent). Table 5. DC Electrical Characteristics Characteristic Symbol VDDC VDDPLL VDDM VDDIO voltage2 3 This section describes the DC electrical characteristics for the MSC7119. Min 1.14 2.375 3.135 0.49 × VDDM VREF – 0.04 2.4 VREF + 0.28 –0.3 –1.0 — Typical 1.2 2.5 3.3 1.25 VREF 3.0 VDDM GND 0.09 — Max 1.26 2.625 3.465 0.51 × VDDM VREF + 0.04 3.465 VDDM + 0.3 VREF – 0.18 1 5 Unit V V V V V V V V µA µA Core and PLL voltage DRAM interface I/O voltage1 I/O voltage DRAM interface I/O reference VREF VTT VIHCLK VIHM VILM IIN IVREF DRAM interface I/O termination voltage Input high CLKIN voltage DRAM interface input high I/O voltage DRAM interface input low I/O voltage Input leakage current, VIN = VDDIO VREF input leakage current MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 19 Electrical Characteristics Table 5. DC Electrical Characteristics (continued) Characteristic Tri-state (high impedance off state) leakage current, VIN = VDDIO Signal low input current, VIL = 0.4 V Signal high input current, VIH = 2.0 V Output high voltage, IOH = –2 mA, except open drain pins Output low voltage, IOL= 5 mA Typical power at 300 MHz Notes: 1. 2. 3. 4. 5. 5 Symbol IOZ IL IH VOH VOL P Min –1.0 –1.0 –1.0 2.0 — — Typical 0.09 0.09 0.09 3.0 0 324.0 Max 1 1 1 — 0.4 — Unit µA µA µA V V mW The value of VDDM at the MSC7119 device must remain within 50 mV of VDDM at the DRAM device at all times. VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not exceed ±2% of the DC value. VTT is not applied directly to the MSC7119 device. It is the level measured at the far end signal termination. It should be equal to VREF. This rail should track variations in the DC level of VREF. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ VOUT ≤ VDDM. The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 300 MHz, 1.2 V core). Table 6 lists the DDR DRAM capacitance. Table 6. DDR DRAM Capacitance Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: These values were measured under the following conditions: • VDDM = 2.5 V ± 0.125 V • f = 1 MHz • TA = 25°C • VOUT = VDDM/2 • VOUT (peak to peak) = 0.2 V Symbol CIO CDIO Max 30 30 Unit pF pF MSC7119 Data Sheet, Rev. 8 20 Freescale Semiconductor Electrical Characteristics 2.5 AC Timings This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the following equations to compute the delay: — Standard interface: 2.45 + (0.054 × Cload) ns — DDR interface: 1.6 + (0.002 × Cload) ns 2.5.1 Clock and Timing Signals The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core, reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see Section 2.5.2 for the allowable ranges when using the PLL). Table 6. Maximum Frequencies Characteristic Core clock frequency (CLOCK) External output clock frequency (CLKO) Memory clock frequency (CK, CK) TDM clock frequency (TxRCK, TxTCK) Maximum in MHz 300 75 150 50 Table 7. Clock Frequencies in MHz Characteristic CLKIN frequency CLOCK frequency CK, CK frequency TDMxRCK, TDMxTCK frequency CLKO frequency AHB/IPBus/APB clock frequency Note: The rise and fall time of external clocks should be 5 ns maximum Symbol FCLKIN FCORE FCK FTDMCK FCKO FBCK Min 10 — — — — — Max 100 300 150 50 75 150 Table 8. System Clock Parameters Characteristic CLKIN frequency CLKIN slope CLKIN frequency jitter (peak-to-peak) CLKO frequency jitter (peak-to-peak) Min 10 — — — Max 100 5 1000 150 Unit MHz ns ps ps MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 21 Electrical Characteristics 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7119 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • • • • PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency FCLKIN. The output of the divider block is the input to the multiplier block. PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the loop frequency FLOOP. RNG field. Selects the available PLL frequency range for FVCO, either FLOOP when the RNG bit is set (1) or FLOOP/2 when the RNG bit is cleared (0). CKSEL field. Selects FCLKIN, FVCO, or FVCO/2 as the source for the core clock. There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x Reference Manual for details on the clock programming model. 2.5.2.1 • • PLL Multiplier Restrictions There are two restrictions for correct usage of the PLL block: The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10–25 MHz. The output frequency of the PLL multiplier must be in the range 266–532 MHz. When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet these constraints. 2.5.2.2 Input Division Factors and Corresponding CLKIN Frequency Range The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9. Table 9. CLKIN Frequency Ranges by Divide Factor Value PLLDVF Field Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Note: Input Divide Factor 1 2 3 4 5 6 7 8 9 10 CLKIN Frequency Range 10 to 25 MHz 20 to 50 MHz 30 to 75 MHz 40 to 100 MHz 50 to 100 MHz 60 to 100 MHz 70 to 100 MHz 80 to 100 MHz 90 to 100 MHz 100 MHz Input Division by 1 Input Division by 2 Input Division by 3 Input Division by 4 Input Division by 5 Input Division by 6 Input Division by 7 Input Division by 8 Input Division by 9 Input Division by 10 Comments The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10. MSC7119 Data Sheet, Rev. 8 22 Freescale Semiconductor Electrical Characteristics 2.5.2.3 Multiplication Factor Range The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10. Table 10. PLLMLTF Ranges Multiplier Block (Loop) Output Range 266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz Note: Minimum PLLMLTF Value 266/Divided Input Clock Maximum PLLMLTF Value 532/Divided Input Clock This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the frequency of the Divided Input Clock. 2.5.2.4 Allowed Core Clock Frequency Range The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown in Table 11. Table 11. Fvco Frequency Ranges CLKCTRL[RNG] Value 1 0 Note: Allowed Range of Fvco 266 ≤ Fvco ≤ 532 MHz 133 ≤ Fvco ≤ 266 MHz This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG]. This bit along with the CKSEL determines the frequency range of the core clock. Table 12. Resulting Ranges Permitted for the Core Clock CLKCTRL[CKSEL] 11 11 01 01 Note: CLKCTRL[RNG] 1 0 1 0 Resulting Division Factor 1 2 2 4 Allowed Range of Core Clock 266 ≤ core clock ≤ 300 MHz 133 ≤ core clock ≤ 266 MHz 133 ≤ core clock ≤ 266 MHz 66.5 ≤ core clock ≤ 133 MHz Comments Limited by maximum core frequency Limited by range of PLL Limited by range of PLL Limited by range of PLL This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL]. 2.5.2.5 Core Clock Frequency Range When Using DDR Memory The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this restriction. Table 13. Core Clock Ranges When Using DDR DDR Type DDR 200 (PC-1600) DDR 266 (PC-2100) DDR 333 (PC-2600) Allowed Frequency Range for DDR CK 83–100 MHz 83–133 MHz 83–150 MHz Corresponding Range for the Core Clock 166 ≤ core clock ≤ 200 MHz 166 ≤ core clock ≤ 266 MHz 166 ≤ core clock ≤ 300 MHz Comments Core limited to 2 × maximum DDR frequency Core limited to 2 × maximum DDR frequency Core limited to 2 × maximum DDR frequency MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 23 Electrical Characteristics 2.5.3 Reset Timing The MSC7119 device has several inputs to the reset logic. All MSC7119 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 14 describes the reset sources. Table 14. Reset Sources Name Power-on reset (PORESET) Direction Input Description Initiates the power-on reset flow that resets the MSC7119 and configures various attributes of the MSC7119. On PORESET, the entire MSC7119 device is reset. SPLL and DLL states are reset, HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The system is configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC7119. While HRESET is asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400 extended core is reset. When the MSC7119 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the MSC7119 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic asserts an internal reset signal that generates an internal soft reset sequence. External Hard reset (HRESET) Input/ Output Software watchdog reset Bus monitor reset JTAG EXTEST, CLAMP, or HIGHZ command Internal Internal Internal Table 15 summarizes the reset actions that occur as a result of the different reset sources. Table 15. Reset Actions for Each Reset Source Power-On Reset (PORESET) Reset Action/Reset Source External only Hard Reset (HRESET) External or Internal (Software Watchdog or Bus Monitor) No Soft Reset (SRESET) JTAG Command: EXTEST, CLAMP, or HIGHZ No Configuration pins sampled (refer to Section 2.5.3.1 for details). PLL and clock synthesis states Reset HRESET Driven Software watchdog and bus time-out monitor registers Clock synthesis modules (STOPCTRL, HLTREQ, and HLTACK) reset Extended core reset Peripheral modules reset Yes Yes Yes Yes Yes No Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes 2.5.3.1 Power-On Reset (PORESET) Pin Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after external power to the MSC7119 reaches at least 2/3 VDD. MSC7119 Data Sheet, Rev. 8 24 Freescale Semiconductor Electrical Characteristics 2.5.3.2 • • Reset Configuration The MSC7119 has two mechanisms for writing the reset configuration: From a host through the host interface (HDI16) From memory through the I2C interface Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and operating conditions: • • • • BM[0–1] SWTE H8BIT HDSP 2.5.3.3 Reset Timing Tables Table 16. Timing for a Reset Configuration Write Table 16 and Figure 4 describe the reset timing for a reset configuration write. No. 1 2 Note: Characteristics Required external PORESET duration minimum Delay from PORESET deassertion to HRESET deassertion Timings are not tested, but are guaranteed by design. Expression 16/FCLKIN 521/FCLKIN Unit clocks clocks 1 PORESET Input Configuration Pins are sampled PORESET Internal HRESET Output(I/O) 2 Figure 4. Timing Diagram for a Reset Configuration Write MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 25 Electrical Characteristics 2.5.4 DDR DRAM Controller Timing This section provides the AC electrical characteristics for the DDR DRAM interface. 2.5.4.1 DDR DRAM Input AC Timing Specifications Table 17. DDR DRAM Input AC Timing Table 17 provides the input AC timing specifications for the DDR DRAM interface. No. — — 201 202 Notes: AC input low voltage AC input high voltage Parameter Symbol VIL VIH — — Min — VREF + 0.31 — — Max VREF – 0.31 VDDM + 0.3 900 900 Unit V V ps ps Maximum Dn input setup skew relative to DQSn input Maximum Dn input hold skew relative to DQSn input 1. 2. 3. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7). See Table 18 for tCK value. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is done internally. DQSn 202 202 Dn D0 D1 201 Note: DQS centering is done internally. 201 Figure 5. DDR DRAM Input Timing Diagram 2.5.4.2 DDR DRAM Output AC Timing Specifications Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM interface. Table 18. DDR DRAM Output AC Timing No. 200 Parameter CK cycle time, (CK/CK crossing)1 • 100 MHz (DDR200) • 150 MHz (DDR300) An/RAS/CAS/WE/CKE output setup with respect to CK An/RAS/CAS/WE/CKE output hold with respect to CK CSn output setup with respect to CK CSn output hold with respect to CK CK to DQSn2 Symbol tCK Min Max Unit 10 6.67 tDDKHAS tDDKHAX tDDKHCS tDDKHCX tDDKHMH 0.5 × tCK – 1000 0.5 × tCK – 1000 0.5 × tCK – 1000 0.5 × tCK – 1000 –600 — — — — — — 600 ns ns ps ps ps ps ps 204 205 206 207 208 MSC7119 Data Sheet, Rev. 8 26 Freescale Semiconductor Electrical Characteristics Table 18. DDR DRAM Output AC Timing (continued) No. 209 Parameter Dn/DQMn output setup with respect to DQSn3 Dn/DQMn output hold with respect to DQSn3 DQSn preamble start4 DQSn epilogue end5 1. 2. Symbol tDDKHDS, tDDKLDS tDDKHDX, tDDKLDX tDDKHMP tDDKHME Min 0.25 × tCK – 750 0.25 × tCK – 750 –0.25 × tCK –600 Max — Unit ps 210 — ps 211 212 Notes: — 600 ps ps 3. 4. 5. All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V. tDDKHMH can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 600 ps before the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval from –600 to +600 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference Manual for details. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe should be centered inside of the data eye. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this reason, we reference from DQSn. All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation. Figure 6 shows the DDR DRAM output timing diagram. CK CK 204 An RAS CAS WE CKE DQMn 206 205 207 Write A0 NOOP 211 208 DQSn 209 212 209 D0 D1 210 210 200 Dn Figure 6. DDR DRAM Output Timing Diagram MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 27 Electrical Characteristics Figure 7 provides the AC test load for the DDR DRAM bus. Output Z0 = 50 Ω VOUT RL = 50 Ω Figure 7. DDR DRAM AC Test Load Table 19. DDR DRAM Measurement Conditions Symbol VTH1 VOUT 2 1. 2. Data input threshold measurement point. Data output measurement point. DDR DRAM VREF ± 0.31 V 0.5 × VDDM Unit V V Notes: 2.5.5 No. 300 301 302 303 304 305 306 307 308 309 310 311 Notes: TDM Timing Table 20. TDM Timing Characteristic TDMxRCK/TDMxTCK TDMxRCK/TDMxTCK High Pulse Width TDMxRCK/TDMxTCK Low Pulse Width TDM all input Setup time TDMxRD Hold time TDMxTFS/TDMxRFS input Hold time TDMxTCK High to TDMxTD output active TDMxTCK High to TDMxTD output valid TDMxTD hold time TDMxTCK High to TDMxTD output high impedance TDMxTFS/TDMxRFS output valid TDMxTFS/TDMxRFS output hold time 1. 2. Expression TC 0.4 × TC 0.4 × TC Min 20.0 8.0 8.0 3.0 3.5 2.0 4.0 — 2.0 — — 2.5 Max — — — — — — — 14.0 — 10.0 13.5 — Units ns ns ns ns ns ns ns ns ns ns ns ns Output values are based on 30 pF capacitive load. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge. 300 301 TDMxRCK 303 TDMxRD 305 303 TDMxRFS 310 ~ ~ TDMxRFS (output) 311 304 302 Figure 8. TDM Receive Signals MSC7119 Data Sheet, Rev. 8 28 Freescale Semiconductor Electrical Characteristics 300 301 TDMxTCK 307 302 309 ~~ ~~ 306 TDMxTD TDMxRCK 310 TDMxTFS (output) 303 TDMxTFS (input) 305 308 311 Figure 9. TDM Transmit Signals 2.5.6 2.5.6.1 No. 800 Ethernet Timing Receive Signal Timing Table 21. Receive Signal Timing Characteristics Receive clock period: • MII: RXCLK (max frequency = 25 MHz) • RMII: REFCLK (max frequency = 50 MHz) Receive clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK Receive clock pulse width low—as a percent of clock period: • MII: RXCLK • RMII: REFCLK RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time Min 40 20 35 14 7 35 14 7 4 2 Max — — 65 — — 65 — — — — Unit ns ns % ns ns % ns ns ns ns 801 802 803 804 800 802 Receive clock RXDn RX_DV CRS_DV RX_ER 803 Valid 804 801 Figure 10. Ethernet Receive Signal Timing MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 29 Electrical Characteristics 2.5.6.2 No. 800 Transmit Signal Timing Table 22. Transmit Signal Timing Characteristics Transmit clock period: • MII: TXCLK • RMII: REFCLK Transmit clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK Transmit clock pulse width low—as a percent of clock period: • MII: RXCLK • RMII: REFCLK Transmit clock to TXDn, TX_EN, TX_ER invalid Transmit clock to TXDn, TX_EN, TX_ER valid Min 40 20 35 14 7 35 14 7 4 — Max — — 65 — — 65 — — — 14 Unit ns ns % ns ns % ns ns ns ns 801 802 805 806 800 801 Transmit clock 805 TXDn TX_EN TX_ER Valid 802 806 Figure 11. Ethernet Receive Signal Timing 2.5.6.3 Asynchronous Input Signal Timing Table 23. Asynchronous Input Signal Timing No. 807 Characteristics • MII: CRS and COL minimum pulse width (1.5 × TXCLK period) • RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) Min 60 30 Max — — Unit ns ns CRS COL CRS_DV 807 Figure 12. Asynchronous Input Signal Timing MSC7119 Data Sheet, Rev. 8 30 Freescale Semiconductor Electrical Characteristics 2.5.6.4 Management Interface Timing Table 24. Ethernet Controller Management Interface Timing No. 808 809 810 811 812 813 814 MDC period MDC pulse width high MDC pulse width low Characteristics Min 400 160 160 0 — 10 10 Max — — — — 15 — — Unit ns ns ns ns ns ns ns MDS falling edge to MDIO output invalid (minimum propagation delay) MDS falling edge to MDIO output valid (maximum propagation delay) MDIO input to MDC rising edge setup time MDC rising edge to MDIO input hold time 808 809 810 MDC (output) 811 MDIO (output) 812 813 814 MDIO (input) Figure 13. Serial Management Channel Timing MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 31 Electrical Characteristics 2.5.7 No. 40 44a 44b 44c HDI16 Signals Table 25. Host Interface (HDI16) Timing1, 2 Characteristics3 Expression Value Unit 45 46 47 48 49 50 51 52 53 54 55 56 57 58 61 62 63 64 Notes: Host Interface Clock period TCORE Note 1 ns Read data strobe minimum assertion width4 Note 11 ns 2.0 × TCORE + 9.0 HACK read minimum assertion width 1.5 × TCORE Note 11 ns Read data strobe minimum deassertion width4 HACK read minimum deassertion width 2.5 × TCORE Note 11 ns Read data strobe minimum deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK minimum deassertion width after “Last Data Register” reads5,6 1.5 × TCORE Write data strobe minimum assertion width8 Note 11 ns HACK write minimum assertion width Write data strobe minimum deassertion width8 HACK write minimum deassertion width after ICR, CVR and Data Register writes5 2.5 × TCORE Note 11 ns Host data input minimum setup time before write data strobe deassertion8 Host data input minimum setup time before HACK write deassertion — 2.5 ns Host data input minimum hold time after write data strobe deassertion8 Host data input minimum hold time after HACK write deassertion — 2.5 ns Read data strobe minimum assertion to output data active from high impedance4 HACK read minimum assertion to output data active from high impedance — 1.0 ns Read data strobe maximum assertion to output data valid4 HACK read maximum assertion to output data valid (2.0 × TCORE) + 8.0 Note 11 ns Read data strobe maximum deassertion to output data high impedance4 HACK read maximum deassertion to output data high impedance — 9.0 ns Output data minimum hold time after read data strobe deassertion4 — 1.0 ns Output data minimum hold time after HACK read deassertion HCS[1–2] minimum assertion to read data strobe assertion4 — 0.5 ns HCS[1–2] minimum assertion to write data strobe assertion8 — 0.0 ns HCS[1–2] maximum assertion to output data valid (2.0 × TCORE) + 6.0 Note 11 ns — 0.5 ns HCS[1–2] minimum hold time after data strobe deassertion9 HA[0–2], HRW minimum setup time before data strobe assertion9 — 5.0 ns HA[0–2], HRW minimum hold time after data strobe deassertion9 — 5.0 ns Maximum delay from read data strobe deassertion to host request (3.0 × TCORE) + 6.0 Note 11 ns deassertion for “Last Data Register” read4, 5, 10 Maximum delay from write data strobe deassertion to host request deassertion for “Last Data Register” write5,8,10 (3.0 × TCORE) + 6.0 Note 11 ns Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. (2.0 × TCORE) + 1.0 Note 11 ns Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion (5.0 × TCORE) + 6.0 Note 11 ns 1. TCORE = core clock period. At 300 MHz, TCORE = 3.333 ns. 2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, CL = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings. 4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode. 5. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe (HDS/HDS) in the single data strobe mode. 10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full 11. Compute the value using the expression. 12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe modes is based on timings 57 and 58. MSC7119 Data Sheet, Rev. 8 32 Freescale Semiconductor Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal timing. HA[0–2] 57 53 HCS[1–2] 57 58 58 56 HRW 44a HDS 44b 51 55 50 49 HD[0–15] HREQ (single host request) HRRQ (double host request) 61 52 44c Figure 14. Read Timing Diagram, Single Data Strobe HA[0–2] 57 53 HCS[1–2] 44a HRD 58 56 44b 51 55 50 49 HD[0–15] 52 44a 61 HREQ (single host request) HRRQ (double host request) Figure 15. Read Timing Diagram, Double Data Strobe MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 33 HA[0–2] 57 54 HCS[1–2] 57 58 56 58 HRW 45 HDS 46 47 48 HD[0–15] HREQ (single host request) HTRQ (double host request) 62 Figure 16. Write Timing Diagram, Single Data Strobe HA[0–2] 57 54 HCS[1–2] 58 56 45 HWR 46 47 48 HD[0–15] HREQ (single host request) HTRQ (double host request) 62 Figure 17. Write Timing Diagram, Double Data Strobe MSC7119 Data Sheet, Rev. 8 34 Freescale Semiconductor HREQ (Output) 64 63 44a RX[0–3] Read 44b HACK 50 51 49 HD[0–15] (Output) Data Valid 52 Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0 HREQ (Output) 64 45 TX[0–3] Write 46 63 HACK 47 48 HD[0–15] (Input) Data Valid Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 35 2.5.8 I2C Timing Table 26. I2C Timing Fast No. 450 451 452 453 454 455 456 457 458 459 460 Note: SCL clock frequency Characteristic Min 0 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.1 2 × 1/FBCK 0 250 — — (SCL clock period/2) – 0.7 (SCL clock period/2) – 0.3 Unit Max 400 — — — — — — 700 300 — — kHz μs μs μs μs μs ns ns ns μs μs Hold time START condition SCL low period SCL high period Repeated START set-up time (not shown in figure) Data hold time Data set-up time SDA and SCL rise time SDA and SCL fall time Set-up time for STOP Bus free time between STOP and START SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance on SDA and SCL is 400 pF. 453 Start Condition SCL 451 1 2 458 457 Stop Condition 9 A C K Start Condition 3 4 5 452 6 7 8 SDA Data Byte 457 458 459 460 Start Condition SCL SDA Data Byte Figure 20. I2C Timing Diagram MSC7119 Data Sheet, Rev. 8 36 Freescale Semiconductor 2.5.9 No. — — 400 401 402 UART Timing Table 27. UART Timing Characteristics Internal bus clock (APBCLK) Internal bus clock period (1/APBCLK) URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time Expression FCORE/2 TAPBCLK 16 × TAPBCLK Min — 6.67 106.67 — — Max 150 — — 5 5 Unit MHz ns ns ns ns 401 401 UTXD, URXD inputs 400 400 Figure 21. UART Input Timing 402 UTXD Output 402 Figure 22. UART Output Timing 2.5.10 Number 65 66 Notes: 1. 2. 3. EE Timing Table 28. EE0 Timing Characteristics EE0 input to the core EE0 output from the core Type Asynchronous Synchronous to core clock Min 4 core clock periods 1 core clock period The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 24 shows the signal behavior of the EE pin. 65 EE0 In 66 EE0 Out Figure 23. EE Pin Timing MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 37 2.5.11 Number 67 68 Notes: 1. 2. 3. Event Timing Table 29. EVNT Signal Timing Characteristics EVNT as input EVNT as output Type Asynchronous Synchronous to core clock Min 1.5 × APBCLK periods 1 APBCLK period Refer to Table 27 for a definition of the APBCLK period. Direction of the EVNT signal is configured through the GPIO and Event port registers. Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality. Figure 24 shows the signal behavior of the EVNT pins. 67 EVNT in 68 EVNT out Figure 24. EVNT Pin Timing 2.5.12 Number 601 602 603 604 Notes: 1. 2. 3. 4. GPIO Timing Table 30. GPIO Signal Timing1,2,3 Characteristics GPI4.5 GPO5 Port A edge-sensitive interrupt Port A level-sensitive interrupt Type Asynchronous Synchronous to core clock Asynchronous Asynchronous Min 1.5 × APBCLK periods 1 APBCLK period 1.5 × APBCLK periods 3 × APBCLK periods6 5. 6. Refer to Table 27 for a definition of the APBCLK period. Direction of the GPIO signal is configured through the GPIO port registers. Refer to Section 1.5 for details on GPIO pin functionality. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and dependence on the state of the DSP core. It is guaranteed by design. The output signals cannot toggle faster than 75 MHz. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is acknowledged. Figure 25 shows the signal behavior of the GPI/GPO pins. 601 GPI 602 GPO Figure 25. GPI/GPO Pin Timing MSC7119 Data Sheet, Rev. 8 38 Freescale Semiconductor 2.5.13 JTAG Signals Table 31. JTAG Timing All frequencies No. Characteristics Min Max 40.0 Unit 700 TCK frequency of operation (1/(TC × 3) Note: TC = 1/CLOCK which is the period of the core clock. The TCK frequency must less than 1/3 of the core frequency with an absolute maximum limit of 40 MHz. TCK cycle time TCK clock pulse width measured at VM = 1.6 V TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time 0.0 MHz 701 702 703 704 705 706 707 708 709 710 711 712 Note: 25.0 11.0 0.0 5.0 14.0 0.0 0.0 5.0 14.0 0.0 0.0 100.0 — — 3.0 — — 20.0 20.0 — — 24.0 10.0 — ns ns ns ns ns ns ns ns ns ns ns ns All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. 701 702 TCK (Input) VIH 703 VM VIL 703 VM Figure 26. Test Clock Input Timing Diagram MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 39 TCK (Input) VIH VIL 704 705 Data Inputs 706 Data Outputs 707 Data Outputs Input Data Valid Output Data Valid Figure 27. Boundary Scan (JTAG) Timing Diagram VIH VIL 708 TDI TMS (Input) 710 TDO (Output) 711 TDO (Output) Output Data Valid Input Data Valid 709 TCK (Input) Figure 28. Test Access Port Timing Diagram TRST (Input) 712 Figure 29. TRST Timing Diagram MSC7119 Data Sheet, Rev. 8 40 Freescale Semiconductor Hardware Design Considerations 3 3.1 Hardware Design Considerations Thermal Design Considerations TJ = TA + (RθJA × PD) where TA = ambient temperature near the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD × VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) Eqn. 1 This section described various areas to consider when incorporating the MSC7119 device into a system design. An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following: The power dissipation values for the MSC7119 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine TJ: TJ = TT + (ΨJT × PD) where TT = thermocouple (or infrared) temperature on top of the package (°C) ΨJT = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) Eqn. 2 MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 41 Hardware Design Considerations 3.2 Power Supply Design Considerations This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2. 3.2.1 Power Supply Table 32. MSC7119 Voltages Voltage Core Memory Reference I/O The MSC7119 requires four input voltages, as shown in Table 32. Symbol VDDC VDDM VREF VDDIO Value 1.2 V 2.5 V 1.25 V 3.3 V You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8 (Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements. 3.2.2 Power Sequencing One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied. The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing of ESD devices, and excessive currents, which all lead to severe device damage. Note: There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated for current spike risks based on actual information for the specific application. MSC7119 Data Sheet, Rev. 8 42 Freescale Semiconductor Hardware Design Considerations 3.2.2.1 1. 2. 3. 4. Case 1 The power-up sequence is as follows: Turn on the VDDIO (3.3 V) supply first. Turn on the VDDC (1.2 V) supply second. Turn on the VDDM (2.5 V) supply third. Turn on the VREF (1.25 V) supply fourth (last). The power-down sequence is as follows: 1. 2. 3. 4. • • • Turn off the VREF (1.25 V) supply first. Turn off the VDDM (2.5 V) supply second. Turn off the VDDC (1.2 V) supply third. Turn of the VDDIO (3.3 V) supply fourth (last). Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms. Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for power-up and power-down. Refer to Figure 30 for relative timing for power sequencing case 1. Ramp-up Ramp-down VDDIO = 3.3 V Use the following guidelines: VDDM = 2.5 V Voltage VREF = 1.25 V VDDC = 1.2 V