MSC8103VT1200F

Freescale Semiconductor Technical Data MSC8103 Rev. 12, 5/2008 MSC8103 Network Digital Signal Processor CPM MCC / UART / HDLC / Transparent / Ethernet / Fast Ethernet / ATM / SCC 3 × FCC 2 × MCC 4 × SCC 2 × SMC SPI I2C UTOPIA Interface MII Interrupt Controller Timers Parallel I/O Baud Rate Generators Dual Ported RAM Bridge 2 × SDMA RISC 64-bit Local Bus MEMC DMA Engine SIU 64-bit System Bus MEMC PIT System Protection Reset Control Clock Control SIC_EXT Interrupts SIC 64/32-bit System Bus TDMs { •• • Serial Interface and TSA The Freescale MSC8103 16-bit DSP is a member of the family of DSPs based on the StarCore SC140 DSP core. The MSC8103 is available in two core speed levels: 275 and 300 MHz. What’s New? Rev. 12 includes the following changes: • Table 2-4 changes VIL reference for signal low input current to 0.8 V. Other Peripherals Extended Core Program Sequencer SC140 Core JTAG Address Register File Address ALU EOnCE™ Clock/PLL Data ALU Register File Data ALU Q2PPC Bridge 128-bit QBus PIC Interrupts 8/16-bit Host Interface Boot ROM HDI16 SRAM 512 KB L1 Interface Power Management 128-bit P-Bus 64-bit XA Data Bus 64-bit XB Data Bus Figure 1. MSC8103 Block Diagram The Freescale MSC8103 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very flexible system integration unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8103 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8103 CPM is a 32-bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones. The MSC8103 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8103 offers 1200 DSP MMACS performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O). © Freescale Semiconductor, Inc., 2001, 2008. All rights reserved. Table of Contents MSC8103 Features .................................................................................................................................................................................... iii Target Applications .....................................................................................................................................................................................iv Product Documentation ..............................................................................................................................................................................iv Chapter 1 Signals/Connections 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power Signals ........................................................................................................................................................................ 1-4 Clock Signals ......................................................................................................................................................................... 1-4 Reset, Configuration, and EOnCE Event Signals.................................................................................................................. 1-5 System Bus, HDI16, and Interrupt Signals............................................................................................................................ 1-6 Memory Controller Signals ................................................................................................................................................. 1-13 CPM Ports............................................................................................................................................................................ 1-15 JTAG Test Access Port Signals............................................................................................................................................ 1-36 Reserved Signals.................................................................................................................................................................. 1-36 Absolute Maximum Ratings .................................................................................................................................................. 2-1 Recommended Operating Conditions .................................................................................................................................... 2-2 Thermal Characteristics ......................................................................................................................................................... 2-2 DC Electrical Characteristics................................................................................................................................................. 2-3 Clock Configuration .............................................................................................................................................................. 2-4 AC Timings............................................................................................................................................................................ 2-7 FC-PBGA Package Description............................................................................................................................................. 3-1 Lidded FC-PBGA Package Mechanical Drawing ............................................................................................................... 3-31 Thermal Design Considerations............................................................................................................................................. 4-1 Electrical Design Considerations........................................................................................................................................... 4-1 Power Considerations ............................................................................................................................................................ 4-2 Layout Practices..................................................................................................................................................................... 4-3 Chapter 2 Physical and Electrical Specifications 2.1 2.2 2.3 2.4 2.5 2.6 Chapter 3 Packaging 3.1 3.2 Chapter 4 Design Considerations 4.1 4.2 4.3 4.4 Ordering and Contact Information ...............................................................................................................................Back Cover Data Sheet Conventions pin and pinout Although the device package does not have pins, the term pins and pin-out are used for convenience and indicate specific signal locations within the ball-grid array. OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MSC8103 Network Digital Signal Processor, Rev. 12 ii Freescale Semiconductor MSC8103 Features • SC140 core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MMACS running at 300 MHz — Very low power dissipation — Variable-length execution set (VLES) execution model — JTAG/Enhanced OnCE debug port Communications processor module (CPM) — Programmable protocol machine using a 32-bit RISC engine — 155 Mbps ATM interface (including AAL 0/1/2/5) — 10/100 Mbit Ethernet interface — Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface — HDLC support up to T3 rates, or 256 channels 64- or 32-bit wide bus interface — Support for bursts for high efficiency — Glueless interface to 60x-compatible bus systems — Multi-master support Programmable memory controller — Control for up to eight banks of external memory — User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals — Dedicated pipelined SDRAM memory interface Large internal SRAM — 256K 16-bit words (512 KB) — Unified program and data space configurable by the application — Word and byte addressable DMA controller — 16 DMA channels, FIFO based, with burst capabilities — Sophisticated addressing capabilities Small foot print package — 17 mm × 17 mm lidded FC-PBGA package with lead-bearing or lead-free spheres Very low power consumption — Separate power supply for internal logic (1.6 V) and for I/O (3.3 V) Enhanced 16-bit parallel host interface (HDI16) — Supports a variety of microcontroller, microprocessor, and DSP bus interfaces Phase-lock loops (PLLs) — System PLL — CPM DPLLs (SCC and SCM) Process technology — 0.13 micron copper interconnect process technology • • • • • • • • • • MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor iii Target Applications The MSC8103 targets applications requiring very high performance, very large amounts of internal memory, and such networking capabilities as: • • • • Third-generation wideband wireless infrastructure systems Packet Telephony systems Multi-channel modem banks Multi-channel xDSL Product Documentation The documents listed in Table 1 are required for a complete description of the MSC8103 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for details): • • • • A local Freescale distributor A Freescale Semiconductor sales office A Freescale Semiconductor Literature Distribution Center The world wide web (WWW) Table 1. MSC8103 Documentation Name MSC8103 Technical Data MSC8101 User’s Guide Description MSC8103 features list and physical, electrical, timing, and package specifications Detailed functional description of the MSC8101 memory configuration, operation, and register programming. All details apply to the MSC8103. Detailed description of the MSC8103 processor core and instruction set Detailed description of the SC140 family processor core and instruction set Documents describing specific applications or optimized device operation including code examples Order Number MSC8103/D MSC8101UG/D MSC8103 Reference Manual SC140 DSP Core Reference Manual Application Notes MSC8103RM/D MNSC140CORE/D See the MSC8103 product website MSC8103 Network Digital Signal Processor, Rev. 12 iv Freescale Semiconductor Signals/Connections 1 The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8103 external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the MSC8103 communications processor module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered sequentially. Table 1-1. Functional Group Power (VCC, VDD, and GND) Clock Reset, configuration, and EOnCE System bus, HDI16, and interrupts Memory controller CPM input/output parallel ports Port A Port B Port C Port D JTAG test access port (TAP) Reserved (denotes connections that are always reserved) MSC8103 Functional Signal Groupings Number of Signal Connections 80 6 11 133 27 26 14 18 8 5 5 Detailed Description Table 1-2 on page 1-4 Table 1-3 on page 1-4 Table 1-4 on page 1-5 Table 1-5 on page 1-7 Table 1-6 on page 1-13 Table 1-7 on page 1-16 Table 1-8 on page 1-21 Table 1-9 on page 1-24 Table 1-10 on page 1-33 Table 1-11 on page 1-36 Table 1-12 on page 1-36 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-1 Signals/Connections 32 5 4 1 1 3 1 1 1 1 1 1 1 1 32 16 4 1 VDD VDDH VCCSYN VCCSYN1 GND GNDSYN GNDSYN1 → 14 → 25 →1 →1 → 37 →1 →1 P O W E R Port A PA[31–6] For the signals multiplexed on Ports A–D, see Figure 1-2 Port B PB[31–18] Port C PC[31–22, 15–12, 7–4] Port D PD[31–29, 19–16, 7] ↔ 26 C P M I / O P O R T S ↔ ↔ ↔ ↔ ↔ → ↔ ↔ ↔ ↔ ↔ ← ↔ ↔ ↔ A[0–31] TT[0–4] TSIZ[0–3] TBST IRQ1 Reserved BR BG ABB TS AACK ARTRY DBG DBB D[0–31] GBL BADDR[29–31] IRQ[2–3, 5] IRQ2 IRQ3 HDI16 Signals HD[0–15] HA[0–3] HCS1 Single DS Double DS HRW HRD/HRD HDS/HDS HWR/HWR Single HR Double HR HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ HDSP HDDS H8BIT HCS2 Reserved DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 Reserved IRQ1 Reserved Reserved DREQ3 DREQ4 DACK3 DACK4 EXT_Br2 EXT_BG2 EXT_DBG2 EXT_BR3 EXT_BG3 EXT_DBG3 IRQ6 IRQ7 ↔ 14 ↔ D[32–47] ↔ D[48–51] ↔ D52 ↔ D53 ↔ D54 ↔ ↔ ↔ ↔ ↔ ↔ ↔ D55 D56 D57 D58 D59 D60 D[61–63] ↔ 18 6 0 x B U S 1 1 1 1 1 1 1 1 4 1 ↔ 8 TMS TDI TCK TRST TDO → → → → ← 1 1 1 1 1 J T A G ← Reserved ↔ IRQ1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ← → ↔ ↔ IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 TA TEA NMI NMI_OUT PSDVAL IRQ7 EOnCE Event EED EE0 EE1 EE[2–3] EE[4–5] RESET Configuration DBREQ HPE BTM[0–1] PORESET RSTCONF HRESET SRESET ↔ ↔ ↔ ↔ ↔ → → ↔ ↔ 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 2 INT_OUT CLKIN BNKSEL[0–2] TC[0–2] MODCK[1–3] CLKOUT DLLIN → → ← → 1 3 1 1 → CS[0–7] → BCTL1 → BADDR[27–28] → → → → → → → ↔ → ALE BCTL0 PWE[0–7] PSDA10 PSDWE POE PSDCAS PGTA PSDAMUX M E M C TEST THERM[1–2] SPARE1, SPARE5 → ↔ ↔ 1 2 2 1 1 8 1 1 1 1 1 1 PSDDQM[0–7] PSDRAS PUPMWAIT PPBS PBS[0–7] PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 Note: Refer to the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details on how to configure these pins. Figure 1-1. MSC8103 External Signals MSC8103 Network Digital Signal Processor, Rev. 12 1-2 Freescale Semiconductor FCC1 HDLC/ Ethernet transp. HDLC MII Serial Nibble COL TXENB TXCLAV TXCLAV0 CRS RTS TXSOC (master) TX_ER RXENB TX_EN RXSOC RX_DV (slave) RXCLAV RXCLAV0 RX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD3 TXD3 TXD5 TXD2 TXD2 TXD6 TXD1 TXD1 TXD7 TXD0 TXD TXD0 RXD7 RXD0 RXD RXD0 RXD6 RXD1 RXD1 RXD5 RXD2 RXD2 RXD4 RXD3 RXD3 RXD3 RXD2 RXD1 RXD0 FCC2 HDLC/ Ethernet transp. HDLC MII Serial Nibble TX_ER RX_DV TX_EN RX_ER RTS COL CRS TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TXD RXD TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 Ext. Req. EXT1 SCC1 CTS/CLSN CTS/CLSN FCC1 ATM/UTOPIA MPHY MPHY Master Master mux poll dir. poll or Slave GPIO PA31 PA30 PA29 PA28 PA27 SDMA MSNUM0 MSNUM1 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 BRGs Clocks Timers PB18 BRG1O CLK1 TGATE1 PC31 BRG2O CLK2 TOUT1 PC30 BRG3O SIU Timer Input BRG4O CLK5 TMCLK DMA DACK2 Ext. Req. EXT2 SCC1 CTS/CLSN CD/RENA LIST1 SMTXD CTS/CLSN CD/RENA LIST2 LIST4 LIST3 LIST1 LIST2 SMC1 SMTXD SMRXD RXD TXD RTS/TENA LIST3 LIST4 DRACK1/DONE1 DRACK2/DONE2 SPI BRG1O SPISEL SPICLK SPIMOSI BRG2O SPIMISO SMSYN DREQ2 DACK1 DREQ1 BRG5O BRG6O BRG7O BRG8O CLK3 TIN2 PC29 SMC2 SMTXD SMRXD SMSYN SCC2 RXD TXD RTS/TENA SI1 TDMA1 Serial Nibble L1TXD L1TXD0 L1RXD L1RXD0 L1TSYNC L1RSYNC SI2 TDMB2 L1TXD L1RXD L1RSYNC L1TSYNC TDMC2 L1TXD L1RXD L1TSYNC L1RSYNC TDMD2 L1TXD L1RXD L1TSYNC L1RSYNC MSNUM2 MSNUM3 MSNUM4 MSNUM5 L1TXD3 L1RXD3 L1RXD2 L1RXD1 L1TXD2 L1TXD1 I2C SDA SCL TIN1/ CLK4 PC28 TOUT2 CLK5 TGATE2 PC27 CLK6 TOUT3 PC26 CLK7 CLK8 CLK9 CLK10 TIN4 TIN3/ TOUT4 PC25 PC24 PC23 PC22 PC15 PC14 PC13 PC12 PC7 PC6 PC5 PC4 PD31 PD30 PD29 PD19 PD18 PD17 PD16 PD7 TXADDR0 RXADDR0 TXADDR1 RXADDR1 TXADDR2/ TXADDR2 TXCLAV1 RXADDR2/ RXADDR2 RXCLAV1 FCC1 CTS CD FCC2 CTS CD RXADDR3 RXCLAV2 TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2 Figure 1-2. CPM Port A–D Pin Multiplexed Functionality MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-3 Signals/Connections 1.1 Power Signals Table 1-2. Power Name VDD Power and Ground Signal Inputs Description Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. SC140 PLL Power VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. System Ground An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors. System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground. SC140 PLL Ground 1 Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path to ground. VDDH VCCSYN VCCSYN1 GND GNDSYN GNDSYN1 1.2 Clock Signals Table 1-3. Signal Name CLKIN MODCK1 Input Input Clock Signals Signal Description Type Clock In Primary clock input to the MSC8103 PLL. Clock Mode Input 1 Defines the operating mode of internal clock circuits. Transfer Code 0 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 0 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Clock Mode Input 2 Defines the operating mode of internal clock circuits. Transfer Code 1 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 1 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Clock Mode Input 3 Defines the operating mode of internal clock circuits. Transfer Code 2 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. Bank Select 2 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. TC0 Output BNKSEL0 MODCK2 Output Input TC1 Output BNKSEL1 MODCK3 Output Input TC2 Output BNKSEL2 Output MSC8103 Network Digital Signal Processor, Rev. 12 1-4 Freescale Semiconductor Reset, Configuration, and EOnCE Event Signals Table 1-3. Signal Name CLKOUT DLLIN Clock Signals (Continued) Signal Description Type Output Input Clock Out The system bus clock. DLLIN Synchronizes with an external device. Note: When the DLL is disabled, connect this signal to GND. 1.3 Reset, Configuration, and EOnCE Event Signals Table 1-4. Signal Name DBREQ Reset, Configuration, and EOnCE Event Signals Signal Description Type Input Debug Request Determines whether to go into SC140 Debug mode when PORESET is deasserted. Enhanced OnCE (EOnCE) Event 0 After PORESET is deasserted, you can configure EE0 as an input (default) or an output. EE01 Input Output HPE Input Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event. Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment. Host Port Enable When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits wide, and the Host must program the reset configuration word. EOnCE Event 1 After PORESET is deasserted, you can configure EE1 as an input (default) or an output. EE11 Input Output EE21 Enable Address Event Detection Channel 1 or generate an EOnCE event. Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external debugging equipment. EOnCE Event 2 After PORESET is deasserted, you can configure EE2 as an input (default) or an output. Input Enable Address Event Detection Channel 2 or generate an EOnCE event or enable the Event Counter. Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment. EOnCE Event 3 After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ERCV Register. Output EE31 Input Output Enable Address Event Detection Channel 3 or generate one of the EOnCE events. The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-5 Signals/Connections Table 1-4. Signal Name BTM[0–1] Reset, Configuration, and EOnCE Event Signals (Continued) Signal Description Boot Mode 0–1 Determines the MSC8103 boot mode when PORESET is deasserted. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to set these pins. EOnCE Event 4 After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT Register. Type Input EE41 Input Output EE51 Enable Address Event Detection Channel 4 or generate an EOnCE event. The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment. EOnCE Event 5 After PORESET is deasserted, you can configure EE5 as an input (default) or an output. Input Output EED1 Enable Address Event Detection Channel 5. Detection by Address Event Detection Channel 5. Triggers external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET is deasserted, you can configure EED as an input (default) or output: Input Output PORESET RSTCONF Input Input Enable the Data Event Detection Channel. Detection by the Data Event Detection Channel. Triggers external debugging equipment. Power-On Reset When asserted, this line causes the MSC8103 to enter power-on reset state. Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of the MSC8103 Reference Manual. Hard Reset When asserted, this open-drain line causes the MSC8103 to enter the hard reset state. Soft Reset When asserted, this open-drain line causes the MSC8103 to enter the soft reset state. HRESET SRESET Note: Input Input See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins. 1.4 System Bus, HDI16, and Interrupt Signals The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group. Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line during PORESET. The configuration word must then be loaded from the host. The configuration word must set the Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur. MSC8103 Network Digital Signal Processor, Rev. 12 1-6 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1 and two IRQ7 input lines. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Table 1-5. Signal A[0–31] System Bus, HDI16, and Interrupt Signals Description Data Flow Input/Output Address Bus When the MSC8103 is in external master bus mode, these pins function as the address bus. The MSC8103 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8103 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8103 memory controller. Bus Transfer Type The bus master drives these pins during the address tenure to specify the type of transaction. Transfer Size The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers four quad words). Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Global1 When a master within the chip initiates a bus transaction, it drives this pin. When an external master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system. The primary configuration is reserved. Burst Address 291 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. The primary configuration is reserved. Burst Address 301 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. The primary configuration is reserved. Burst Address 311 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TT[0–4] TSIZ[0–3] Input/Output Input/Output TBST Input/Output IRQ1 Input GBL Input/Output Reserved BADDR29 Output Output IRQ2 Input Reserved BADDR30 Output Output IRQ3 Input Reserved BADDR31 Output Output IRQ5 Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-7 Signals/Connections Table 1-5. Signal BR System Bus, HDI16, and Interrupt Signals (Continued) Description Bus Request An output when an external arbiter is used. The MSC8103 asserts this pin to request ownership of the bus. An input when an internal arbiter is used. An external master should assert this pin to request bus ownership from the internal arbiter. Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin to grant bus ownership to an external bus master. An input when an external arbiter is used. The external arbiter should assert this pin to grant bus ownership to the MSC8103. Address Bus Busy1 The MSC8103 asserts this pin for the duration of the address bus tenure. Following an address acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8103 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8103 does not assume bus ownership while it this pin is asserted by an external bus master. Interrupt Request 21 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8103 asserts this signal when one of its internal bus masters (SC140 core or DMA controller) begins an address tenure. When the MSC8103 senses this pin being asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8103 resources, memory controller support). Address Acknowledge A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal terminates the address tenure. Address Retry Assertion of this signal indicates that the bus transaction should be retried by the bus master. The MSC8103 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations. Data Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin as an output to grant data bus ownership to an external bus master. An input when an external arbiter is used. The external arbiter should assert this pin as an input to grant data bus ownership to the MSC8103. Data Bus Busy1 The MSC8103 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8103 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. The MSC8103 does not assume data bus ownership while DBB is asserted by an external bus master. Interrupt Request 31 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Bus Most Significant Word In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode. 2 Data Flow Input/Output Output Input BG Input/Output Output Input ABB Input/Output Output Input IRQ2 Input TS Input/Output AACK Input/Output ARTRY Input DBG Input/Output Output Input DBB Input/Output Output Input IRQ3 Input D[0–31] Input/Output MSC8103 Network Digital Signal Processor, Rev. 12 1-8 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Table 1-5. Signal D[32–47] System Bus, HDI16, and Interrupt Signals (Continued) Description Data Bus Bits 32–47 In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. Host Data2 When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data bus. Data Bus Bits 48–51 In write transactions the bus master drives the valid data on these pins. In read transactions the slave drives the valid data on these pins. Host Address Line 0–33 When the HDI16 interface bus is enabled, these lines address internal host registers. Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Chip Select3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. Data Bus Bit 53 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Read Write Select3 When the HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW). Host Read Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable. Data Bus Bit 54 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Data Strobe3 When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable. Host Write Data Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable. Data Bus Bit 55 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Request3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host request output (HREQ/HREQ). The polarity of the host request is programmable. The host request may be programmed as a driven or open-drain output. Transmit Host Request3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. Data Flow Input/Output HD[0–15] Input/Output D[48–51] Input/Output HA[0–3] D52 Input Input/Output HCS1 Input D53 Input/Output HRW Input HRD/HRD Input D54 Input/Output HDS/HDS Input HWR/HWR Input D55 Input/Output HREQ/HREQ Output HTRQ/HTRQ Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-9 Signals/Connections Table 1-5. Signal D56 System Bus, HDI16, and Interrupt Signals (Continued) Description Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Acknowledge3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable. Receive Host Request3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. Data Bus Bit 57 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Data Strobe Polarity3 When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP). Data Bus Bit 58 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Dual Data Strobe3 When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS). Data Bus Bit 59 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. H8BIT3 When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode. Data Bus Bit 60 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. Host Chip Select 3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. Data Bus Bits 61–63 Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. These dedicated signals are reserved when the HDI16 is enabled.3 Data Flow Input/Output HACK/HACK Output HRRQ/HRRQ Output D57 Input/Output HDSP D58 Input Input/Output HDDS D59 Input Input/Output H8BIT D60 Input Input/Output HCS2 Input D[61–63] Input/Output Reserved Reserved DP0 Input Input/Output The primary configuration is reserved. Data Parity 01 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity zero pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0–7]. External Bus Request 21,2 An external master asserts this pin to request bus ownership from the internal arbiter. EXT_BR2 Input MSC8103 Network Digital Signal Processor, Rev. 12 1-10 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Table 1-5. Signal IRQ1 System Bus, HDI16, and Interrupt Signals (Continued) Description Interrupt Request 1 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 11 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity one pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8–15]. External Bus Grant 21,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 21 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity two pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16–23]. External Data Bus Grant 21,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 31 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity three pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24–31]. External Bus Request 31,2 An external master asserts this pin to request bus ownership from the internal arbiter. Interrupt Request 41 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 41 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity four pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32–39]. DMA Request 31 An external peripheral uses this pin to request DMA service. External Bus Grant 31,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. 1 Data Flow Input DP1 Input/Output EXT_BG2 IRQ2 Output Input DP2 Input/Output EXT_DBG2 IRQ3 Output Input DP3 Input/Output EXT_BR3 IRQ4 Input Input DP4 Input/Output DREQ3 Input EXT_BG3 Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-11 Signals/Connections Table 1-5. Signal IRQ5 System Bus, HDI16, and Interrupt Signals (Continued) Description Interrupt Request 5 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 51 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity five pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40–47]. DMA Request 41 An external peripheral uses this pin to request DMA service. External Data Bus Grant 31,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 61 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 61 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity six pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48–55]. DMA Acknowledge 31 The DMA controller drives this output to acknowledge the DMA transaction on the bus. Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Data Parity 71 The master or slave that drives the data bus also drives the data parity signals. The value driven on the data parity seven pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56–63]. DMA Acknowledge1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer. Transfer Error Acknowledge Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103 internal bus monitor can assert this pin if it identifies a bus transfer that is hung. Non-Maskable Interrupt When an external device asserts this line, the MSC8103 NMI input is asserted. Non-Maskable Interrupt Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt, pending in the MSC8103 internal interrupt controller, is waiting to be handled by an external host. Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three times without TA, and finally both pins are asserted to terminate the transfer. 1 Data Flow Input DP5 Input/Output DREQ4 Input EXT_DBG3 IRQ6 Output Input DP6 Input/Output DACK3 IRQ7 Output Input DP7 Input/Output DACK4 TA Output Input/Output TEA Input/Output NMI NMI_OUT Input Output PSDVAL Input/Output MSC8103 Network Digital Signal Processor, Rev. 12 1-12 Freescale Semiconductor Memory Controller Signals Table 1-5. Signal IRQ7 System Bus, HDI16, and Interrupt Signals (Continued) Description Interrupt Request 7 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Interrupt Output1 Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in the MSC8103 internal interrupt controller. 1 Data Flow Input INT_OUT Output Notes: 1. 2. 3. See the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8103 master device. See the Bus Configuration Register (BCR) description in the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8103 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8103 to obtain master control of the bus. See the host interface (HDI16) chapter in the MSC8103 Reference Manual for details on how to configure these pins. 1.5 Memory Controller Signals Refer to the memory controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed information about configuring these signals. Table 1-6. Signal CS[0–7] BCTL1 Memory Controller Signals Description Data Flow Output Output Chip Select Enable specific memory devices or peripherals connected to MSC8103 buses. Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details. Burst Address 27–28 Two of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. Address Latch Enable Controls the external address latch used in external master bus configuration. Buffer Control 0 Controls buffers on the data bus. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details. Bus Write Enable Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for write operations. Bus SDRAM DQM Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. Bus UPM Byte Select Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. BADDR[27–28] Output ALE BCTL0 Output Output PWE[0–7] Output PSDDQM[0–7] Output PBS[0–7] Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-13 Signals/Connections Table 1-6. Signal PSDA10 Memory Controller Signals (Continued) Description Data Flow Output Bus SDRAM A10 Output from the bus SDRAM controller. This pin is part of the address when a row address is driven. It is part of the command when a column address is driven. Bus UPM General-Purpose Line 0 One of six general-purpose output lines of the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM Write Enable Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal. Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. Bus SDRAM RAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal. Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM CAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address Strobe (CAS) input signal. Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. GPCM TA Terminates transactions during GPCM operation. Requires an external pull up resistor for proper operation. Bus UPM Wait Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device is ready for the operation to continue. Bus Parity Byte Select In systems that store data parity in a separate chip, this output is the byte-select for that chip. Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. Bus SDRAM Address Multiplexer Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode. Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PGPL0 Output PSDWE Output PGPL1 Output POE Output PSDRAS Output PGPL2 Output PSDCAS Output PGPL3 Output PGTA Input PUPMWAIT Input PPBS Output PGPL4 Output PSDAMUX Output PGPL5 Output MSC8103 Network Digital Signal Processor, Rev. 12 1-14 Freescale Semiconductor CPM Ports 1.6 CPM Ports The MSC8103 CPM supports the subset of MPC8260 signals as described below. • The MSC8103 CPM includes the following set of communication controllers: • Two full-duplex fast serial communications controllers (FCCs) that support: — Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8103 can operate as one of the following: ° ° ° UTOPIA slave device UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0–30 (address 31 is reserved as a null port). — IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) — High-level data link control (HDLC) Protocol: ° ° Serial mode—Transfers data one bit at a time Nibble mode—Transfers data four bits at a time — Transparent mode serial operation • One FCC that operates with the TSA only • Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to four TDM interfaces • Two full-duplex serial communications controllers (SCCs) that support the following protocols: — IEEE 802.3/fast Ethernet through a media-independent interface (MII) — HDLC Protocol: ° ° Serial mode—Transfers data one bit at a time Nibble mode—Transfers data four bits at a time — — — — — — Synchronous data link control (SDLC) LocalTalk (HDLC-based local area network protocol) Universal asynchronous receiver/transmitter (UART) Synchronous UART (1x clock mode) Binary synchronous (BISYNC) communication Transparent mode serial operation • Two additional SCCs that operate with the TSA only • Two full-duplex serial management controllers (SMCs) that support the following protocols: — General circuit interface (GCI)/integrated services digital network (ISDN) monitor and C/I channels (TSA only) — UART — Transparent mode serial operation • Serial peripheral interface (SPI) support for master or slave operation • Inter-integrated circuit (I2C) bus controller • Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2, TDMC2, and TDMD2, which operate only in serial mode. The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by Ports A–D. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-15 Signals/Connections 1.6.1 Port A Signals Table 1-7. Name Port A Signals GeneralPurpose I/O PA31 Peripheral Controller: Dedicated Signal Protocol FCC1: TXENB UTOPIA master Dedicated I/O Data Direction Output Description FCC1: UTOPIA Master Transmit Enable Asserted by the MSC8103 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0–7]). FCC1: UTOPIA Slave Transmit Enable Asserted by an external UTOPIA master PHY when there is valid transmit cell data (TXD[0–7]). FCC1: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when collision is detected. FCC1: UTOPIA Slave Transmit Cell Available Asserted by the MSC8103 (UTOPIA slave PHY) when the MSC8103 can accept one complete ATM cell. FCC1: UTOPIA Master Transmit Cell Available Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling Asserted by an external UTOPIA slave PHY using direct polling to indicate that it can accept one complete ATM cell. FCC1: Request To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: Media Independent Interface Carrier Sense Asserted by an external fast Ethernet PHY to indicate activity on the cable. FCC1: UTOPIA Transmit Start of Cell Asserted by the MSC8103 (UTOPIA master PHY) when TXD[0–7] contains the first valid byte of the cell. FCC1: Media Independent Interface Transmit Error Asserted by the MSC8103 to force propagation of transmit errors. FCC1: UTOPIA Master Receive Enable Asserted by the MSC8103 (UTOPIA master PHY) to indicate that RXD[0–7] and RXSOC are to be sampled at the end of the next cycle. RXD[0–7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: UTOPIA Master Receive Enable Asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to be sampled at the end of the next cycle. RXD[0–7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: Media Independent Interface Transmit Enable Asserted by the MSC8103 when transmitting data. FCC1: TXENB UTOPIA slave Input FCC1: COL MII PA30 FCC1: TXCLAV UTOPIA slave Input Output FCC1: TXCLAV UTOPIA master, or Input FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling Input FCC1: RTS HDLC, Serial and Nibble Output FCC1: CRS MII PA29 FCC1: TXSOC UTOPIA master Input Output FCC1: TX_ER MII PA28 FCC1: RXENB UTOPIA master Output Output FCC1: RXENB UTOPIA slave Input FCC1: TX_EN MII Output MSC8103 Network Digital Signal Processor, Rev. 12 1-16 Freescale Semiconductor CPM Ports Table 1-7. Name GeneralPurpose I/O PA27 Port A Signals (Continued) Peripheral Controller: Dedicated Signal Protocol FCC1: RXSOC UTOPIA slave Dedicated I/O Data Direction Output Description FCC1: UTOPIA Receive Start of Cell Asserted by the MSC8103 (UTOPIA slave) for an external PHY when RXD[0–7] contains the first valid byte of the cell. FCC1: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense but not RX_DV indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. FCC1: UTOPIA Slave Receive Cell Available Asserted by the MSC8103 (UTOPIA slave PHY) when one complete ATM cell is available for transfer. FCC1: UTOPIA Master Receive Cell Available Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. FCC1: UTOPIA Transmit Data Bit 0 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. Module Serial Number Bit 0 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA Transmit Data Bit 1 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 1 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. Module Serial Number Bit 1 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA Transmit Data Bit 2 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 2 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: RX_DV MII Input PA26 FCC1: RXCLAV UTOPIA slave Output FCC1: RXCLAV UTOPIA master, or Input RXCLAV0 UTOPIA master, Multi-PHY, direct polling FCC1: RX_ER MII PA25 FCC1: TXD0 UTOPIA Input Input Output SDMA: MSNUM0 Output PA24 FCC1: TXD1 UTOPIA Output SDMA: MSNUM1 Output PA23 FCC1: TXD2 UTOPIA Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-17 Signals/Connections Table 1-7. Name GeneralPurpose I/O PA22 Port A Signals (Continued) Peripheral Controller: Dedicated Signal Protocol FCC1: TXD3 UTOPIA Dedicated I/O Data Direction Output Description FCC1: UTOPIA Transmit Data Bit 3 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: UTOPIA Transmit Data Bit 4 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 3 TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. FCC1: UTOPIA Transmit Data Bit 5 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 2 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is bit 2 of the transmit data. TXD3 is the most significant bit. FCC1: UTOPIA Transmit Data Bit 6 The MSC8103MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 1 TXD[3–0] is supported by MII and HDLC transparent nibble modes in FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit. FCC1: UTOPIA Transmit Data Bit 7. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 0 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Transmit Data Bit This is the single transmit data bit in supported by HDLC serial and transparent modes. PA21 FCC1: TXD4 UTOPIA Output FCC1: TXD3 MII and HDLC nibble PA20 FCC1: TXD5 UTOPIA Output Output FCC1: TXD2 MII and HDLC nibble PA19 FCC1: TXD6 UTOPIA Output Output FCC1: TXD1 MII and HDLC nibble PA18 FCC1: TXD7 UTOPIA Output Output FCC1: TXD0 MII and HDLC nibble Output FCC1: TXD HDLC serial and transparent Output MSC8103 Network Digital Signal Processor, Rev. 12 1-18 Freescale Semiconductor CPM Ports Table 1-7. Name GeneralPurpose I/O PA17 Port A Signals (Continued) Peripheral Controller: Dedicated Signal Protocol FCC1: RXD7 UTOPIA Dedicated I/O Data Direction Input Description FCC1: UTOPIA Receive Data Bit 7. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 0 RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Receive Data Bit This is the single receive data bit supported by HDLC and transparent modes. FCC1: UTOPIA Receive Data Bit 6. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 1 This is bit 1 of the receive nibble data. RXD3 is the most significant bit. FCC1: UTOPIA Receive Data Bit 5 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 2 This is bit 2 of the receive nibble data. RXD3 is the most significant bit. FCC1: UTOPIA Receive Data Bit 4. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 3 RXD3 is the most significant bit of the receive nibble bit. FCC1: UTOPIA Receive Data Bit 3 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 2 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: RXD0 MII and HDLC nibble Input FCC1: RXD HDLC serial and transparent PA16 FCC1: RXD6 UTOPIA Input Input FCC1: RXD1 MII and HDLC nibble PA15 FCC1: RXD5 UTOPIA Input Input RXD2 MII and HDLC nibble PA14 FCC1: RXD4 UTOPIA Input Input FCC1: RXD3 MII and HDLC nibble PA13 FCC1: RXD3 UTOPIA Input Input SDMA: MSNUM2 Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-19 Signals/Connections Table 1-7. Name GeneralPurpose I/O PA12 Port A Signals (Continued) Peripheral Controller: Dedicated Signal Protocol FCC1: RXD2 UTOPIA Dedicated I/O Data Direction Input Description FCC1: UTOPIA Receive Data Bit 2 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 2 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 3 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 1 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 1 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 4 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 0 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD0 is the least significant bit of the receive data. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 5 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). See also PC15. Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0 L1TXD0 is the least significant bit of the TDM nibble data. SMC2: Serial Management Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0 L1RXD0 is the least significant bit received in nibble mode. Time-Division Multiplexing A1: Layer 1 Serial Receive Data TDMA1 receives serial data from L1RXD. SDMA: MSNUM3 Output PA11 FCC1: RXD1 UTOPIA Input SDMA: MSNUM4 Output PA10 FCC1: RXD0 UTOPIA Input SDMA: MSNUM5 Output PA9 SMC2: SMTXD Output SI1 TDMA1: L1TXD0 TDM nibble PA8 SMC2: SMRXD Output Input SI1 TDMA1: L1RXD0 TDM nibble SI1 TDMA1: L1RXD TDM serial Input Input MSC8103 Network Digital Signal Processor, Rev. 12 1-20 Freescale Semiconductor CPM Ports Table 1-7. Name GeneralPurpose I/O PA7 Port A Signals (Continued) Peripheral Controller: Dedicated Signal Protocol SMC2: SMSYN Dedicated I/O Data Direction Input Description SMC2: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). Time-Division Multiplexing A1: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with time-slot assigner chapter in the MSC8103 Reference Manual. Time-Division Multiplexing A1: Layer 1 Receive Synchronization. The synchronizing signal for the receive channel. SI1 TDMA1: L1TSYNC TDM nibble and TDM serial Input PA6 SI1 TDMA1: L1RSYNC TDM nibble and TDM serial Input 1.6.2 Port B Signals Table 1-8. Name Port B Signals GeneralPurpose I/O PB31 Peripheral Controller: Dedicated I/O Protocol FCC2: TX_ER MII SCC2: RXD Dedicated I/O Data Direction Output Description FCC2: Media Independent Interface Transmit Error Asserted by the MSC8103 to force propagation of transmit errors. SCC2: Receive Data SCC2 receives serial data from RXD. Time-Division Multiplexing B2: Layer 1 Transmit Data TDMB2 transmits serial data out of L1TXD. SCC2: Transmit Data. SCC2 transmits serial data out of TXD. FCC2: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense, but not RX_DV, indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. Time-Division Multiplexing B2: Layer 1 Receive Data TDMB2 receives serial data from L1RXD. FCC2: Media Independent Interface Transmit Enable Asserted by the MSC8103 when transmitting data. Time-Division Multiplexing B2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. Input SI2 TDMB2: L1TXD TDM serial PB30 SCC2: TXD Output Output FCC2: RX_DV MII Input SI2 TDMB2: L1RXD TDM serial PB29 FCC2: TX_EN MII SI2 TDMB2: L1RSYNC TDM serial Input Output Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-21 Signals/Connections Table 1-8. Name GeneralPurpose I/O PB28 Port B Signals (Continued) Peripheral Controller: Dedicated I/O Protocol FCC2: RTS HDLC serial, HDLC nibble, and transparent Dedicated I/O Data Direction Output Description FCC2: Request to Send One of the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC2: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. SCC2: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. Time-Division Multiplexing B2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the serial interface with time-slot assigner chapter in the MSC8103 Reference Manual. FCC2: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when a collision is detected. Time-Division Multiplexing C2: Layer 1 Transmit Data TDMC2 transmits serial data out of L1TXD. FCC2: Media Independent Interface Carrier Sense Input Asserted by an external fast Ethernet PHY to indicate activity on the cable. Time-Division Multiplexing C2: Layer 1 Receive Data TDMC2 receives serial data from L1RXD. FCC2: MII and HDLC Nibble Transmit Data Bit 3 TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 3 L1TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing C2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. FCC2: MII and HDLC Nibble: Transmit Data Bit 2 TXD2 is bit 2 of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3 L1RXD3 is bit 3 and the most significant bit of the receive data nibble. Time-Division Multiplexing C2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. FCC2: RX_ER MII Input SCC2: RTS, TENA Output SI2 TDMB2: L1TSYNC TDM serial Input PB27 FCC2: COL MII SI2 TDMC2: L1TXD TDM serial Input Output Input PB26 FCC2: CRS MII SI2 TDMC2: L1RXD TDM serial PB25 FCC2: TXD3 MII and HDLC nibble Input Output SI1 TDMA1: L1TXD3 TDM nibble Output SI2 TDMC2: L1TSYNC TDM serial PB24 FCC2: TXD2 MII and HDLC nibble SI1 TDMA1: L1RXD3 nibble SI2 TDMC2: L1RSYNC serial Input Output Input Input MSC8103 Network Digital Signal Processor, Rev. 12 1-22 Freescale Semiconductor CPM Ports Table 1-8. Name GeneralPurpose I/O PB23 Port B Signals (Continued) Peripheral Controller: Dedicated I/O Protocol FCC2: TXD1 MII and HDLC nibble SI1 TDMA1: L1RXD2 TDM nibble SI2 TDMD2: L1TXD TDM serial Dedicated I/O Data Direction Output Description FCC2: MII and HDLC Nibble: Transmit Data Bit 1 TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2 L1RXD2 is bit 2 of the receive data nibble. Time-Division Multiplexing D2: Layer 1 Transmit Data TDMA1 transmits serial data out of L1TXD. FCC2: MII and HDLC Nibble Transmit Data Bit 0 TXD0 is bit 0 and the least significant bit of the transmit data nibble. FCC2: HDLC Serial and Transparent Transmit Data Serial data is transmitted via TXD. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1 L1RXD1 is bit 1 of the receive data nibble. Time-Division Multiplexing D2: Layer 1 Receive Data Serial data is received via L1RXD. FCC2: MII and HDLC Nibble Receive Data Bit 0 RXD0 is bit 0 and the least significant bit of the receive data nibble. FCC2: HDLC Serial and Transparent Receive Data Serial data is received via RXD. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2 L1TXD2 is bit 2 of the transmit data nibble. Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD1 is bit 1 of the receive data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1 L1TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data The synchronizing signal for the receive channel. FCC2: MII and HDLC Nibble Receive Data Bit 2 RXD2 is bit 2 of the receive data nibble. Input Output Output PB22 FCC2: TXD0 MII and HDLC nibble FCC2: TXD HDLC serial and transparent SI1 TDMA1: L1RXD1 TDM nibble SI2 TDMD2: L1RXD TDM serial Output Input Input Input PB21 FCC2: RXD0 MII and HDLC nibble FCC2: RXD HDLC serial and transparent SI1 TDMA1: L1TXD2 TDM nibble SI2 TDMD2: L1TSYNC TDM serial Input Output Input PB20 FCC2: RXD1 MII and HDLC nibble SI1 TDMA1: L1TXD1 TDM nibble SI2 TDMD2: L1RSYNC TDM serial Input Output Input Input PB19 FCC2: RXD2 MII and HDLC nibble I2C: SDA Input/ Output I2C: Inter-Integrated Circuit Serial Data The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-23 Signals/Connections Table 1-8. Name GeneralPurpose I/O PB18 Port B Signals (Continued) Peripheral Controller: Dedicated I/O Protocol FCC2: RXD3 MII and HDLC nibble I2C: SCL Dedicated I/O Data Direction Input Description FCC2: MII and HDLC Nibble Receive Data Bit 3 RXD3 is bit 3 and the most significant bit of the receive data nibble. I2C: Inter-Integrated Circuit Serial Clock The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. Input/Output 1.6.3 Port C Signals Table 1-9. Name Port C Signals GeneralPurpose I/O PC31 Peripheral Controller: Dedicated I/O Protocol BRG1O Dedicated I/O Data Direction Output Description Baud-Rate Generator 1 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 below), it is the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. Clock 1 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 1/2: Timer Gate 1 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. CLK1 Input TIMER1/2: TGATE1 Input MSC8103 Network Digital Signal Processor, Rev. 12 1-24 Freescale Semiconductor CPM Ports Table 1-9. Name GeneralPurpose I/O PC30 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol BRG2O Dedicated I/O Data Direction Output Description Baud-Rate Generator 2 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Clock 2 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 1: Timer Out 1 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. External Request 1 Asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. Baud-Rate Generator 3 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Clock 3 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 2 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. SCC1: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC15. CLK2 Input Timer1: TOUT1 Output EXT1 Input PC29 BRG3O Output CLK3 Input TIN2 Input SCC1: CTS, CLSN Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-25 Signals/Connections Table 1-9. Name GeneralPurpose I/O PC28 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol BRG4O Dedicated I/O Data Direction Output Description Baud-Rate Generator 4 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Clock 4 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 1 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Timer 2: Timer Output 2 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC13. Baud-Rate Generator 5 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Clock 5 When selected, CLK5 is a source for the SIU timers via BRG1O. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. Timer 3/4: Timer Gate 2 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. CLK4 Input TIN1 Input Timer2: TOUT2 Output SCC2: CTS, CLSN Input PC27 BRG5O Output CLK5 Input TIMER3/4: TGATE2 Input MSC8103 Network Digital Signal Processor, Rev. 12 1-26 Freescale Semiconductor CPM Ports Table 1-9. Name GeneralPurpose I/O PC26 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol BRG6O Dedicated I/O Data Direction Output Description Baud-Rate Generator 6 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 6 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer 3: Timer Out 3 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. Timer Clock When selected, TMCLK is the designated input to the SIU timers. When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. Baud-Rate Generator 7 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Clock 7 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 4 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. DMA: Data Acknowledge 2 DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. CLK6 Input Timer3: TOUT3 Output TMCLK Input PC25 BRG7O Output CLK7 Input TIN4 Input DMA: DACK2 Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-27 Signals/Connections Table 1-9. Name GeneralPurpose I/O PC24 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol BRG8O Dedicated I/O Data Direction Output Description Baud-Rate Generator 8 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Clock 8 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer Input 3 A timer can have one of the following sources: another timer, system clock, system clock divided by 16, or a timer input. The CPM supports up to four timer inputs. The timer inputs can be captured on the rising, falling, or both edges. Timer 4: Timer Out 4 The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. DMA: Data Request 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Clock 9 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. DMA: Data Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. External Request 2 External request input line 2 asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC controller configuration register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. CLK8 Input TIN3 Input Timer4: TOUT4 Output DMA: DREQ2 Input PC23 CLK9 Input DMA: DACK1 Output EXT2 Input MSC8103 Network Digital Signal Processor, Rev. 12 1-28 Freescale Semiconductor CPM Ports Table 1-9. Name GeneralPurpose I/O PC22 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol SI1: L1ST1 Dedicated I/O Data Direction Output Description Serial Interface 1: Layer 1 Strobe 1 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Clock 10 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. CLK10 Input DMA: DREQ1 Input/ Output DMA: Request 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Output SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PA9. SCC1: Clear To Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC29. FCC1: UTOPIA Master Transmit Address Bit 0 This is master transmit address bit 0. FCC1: UTOPIA Slave Transmit Address Bit 0 This is slave transmit address bit 0. Serial Interface 1: Layer 1 Strobe 2 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also be generate output wave forms for such applications as stepper-motor control. SCC1: Carrier Detect, Receive Enable Typically used in conjunction with RTS supported by SCC1. The MSC8103MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0 This is master receive address bit 0. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0 This is slave receive address bit 0. PC15 SMC2: SMTXD SCC1: CTS/CLSN Input FCC1: TXADDR0 UTOPIA master FCC1: TXADDR0 UTOPIA slave PC14 SI1: L1ST2 Output Input Output SCC1: CD, RENA Input FCC1: RXADDR0 UTOPIA master FCC1: RXADDR0 UTOPIA slave Output Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-29 Signals/Connections Table 1-9. Name GeneralPurpose I/O PC13 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol SI1: L1ST4 Dedicated I/O Data Direction Output Description Serial Interface 1: Layer 1 Strobe 4 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC28. FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1 This is master transmit address bit 1. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1 This is slave transmit address bit 1. Serial Interface 1: Layer 1 Strobe 3 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: Carrier Detect, Request Enable Typically used in conjunction with RTS supported by SCC2. The MSC8103 SCC2 transmitter requests to the receiver that it sends data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1 This is master receive address bit 1. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1 This is slave receive address bit 1. SCC2: CTS,CLSN Input FCC1:TXADDR1 UTOPIA master FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3 Output Input Output SCC2: CD, RENA Input FCC1: RXADDR1 UTOPIA master FCC1: RXADDR1 UTOPIA slave Output Input MSC8103 Network Digital Signal Processor, Rev. 12 1-30 Freescale Semiconductor CPM Ports Table 1-9. Name GeneralPurpose I/O PC7 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol SI2: L1ST1 Dedicated I/O Data Direction Output Description Serial Interface 2: Strobe 1 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC1: Clear To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CTS is asynchronous with the data. FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2 This is master transmit address bit 2. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2 This is slave transmit address bit 2. FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Serial Interface 2: Layer 1 Strobe 2 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC1: Carrier Detect In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CD is an input asynchronous with the data. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2 This is master receive address bit 2. FCC1: UTOPIA Slave Receive Address Bit 2 This is slave receive address bit 2. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: CTS HDLC serial, HDLC nibble, and transparent FCC1: TXADDR2 UTOPIA master FCC1: TXADDR2 UTOPIA slave FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling PC6 SI2: L1ST2 Input Output Input Input Output FCC1: CD HDLC serial, HDLC nibble, and transparent FCC1: RXADDR2 UTOPIA master FCC1: RXADDR2 UTOPIA slave FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling Input Output Input Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-31 Signals/Connections Table 1-9. Name GeneralPurpose I/O PC5 Port C Signals (Continued) Peripheral Controller: Dedicated I/O Protocol SMC1: SMTXD Dedicated I/O Data Direction Output Description SMC1: Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Serial Interface 2: Layer 1 Strobe 3 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: Clear To Send In the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). CTS is asynchronous with the data. SMC1: Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Serial Interface 2: Layer 1 Strobe 4 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: Carrier Detect In the standard modem interface signals supported by FCC2 (RTS, CTS and CD). CD is asynchronous with the data. SI2: L1ST3 Output FCC2: CTS HDLC serial, HDLC nibble, and transparent PC4 SMC1: SMRXD Input Input SI2: L1ST4 Output FCC2: CD HDLC serial, HDLC nibble, and transparent Input MSC8103 Network Digital Signal Processor, Rev. 12 1-32 Freescale Semiconductor CPM Ports 1.6.4 Port D Signals Table 1-10. Name Dedicated I/O Data Direction Input Port D Signals GeneralPurpose I/O PD31 Peripheral Controller: Dedicated I/O Protocol SCC1: RXD Description SCC1: Receive Data SCC1 receives serial data from RXD. DMA: Data Request Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: Done 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. SCC1: Transmit Data SCC1 transmits serial data out of TXD. DMA: Data Request Acknowledge 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: Done 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. SCC1: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3 This is master receive address bit 3. FCC1: UTOPIA Slave Receive Address Bit 3 This is slave receive address bit 3. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. DMA: DRACK1 Output DMA: DONE1 Input/ Output PD30 SCC1: TXD Output DMA: DRACK2 Output DMA: DONE2 Input/ Output PD29 SCC1: RTS, TENA Output FCC1: RXADDR3 UTOPIA master FCC1: RXADDR3 UTOPIA slave FCC1: RXCLAV2 UTOPIA multi-PHY master, direct polling Output Input Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-33 Signals/Connections Table 1-10. Name GeneralPurpose I/O PD19 Port D Signals (Continued) Peripheral Controller: Dedicated I/O Protocol FCC1: TXADDR4 UTOPIA master FCC1: TXADDR4 UTOPIA slave FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling Dedicated I/O Data Direction Output Description FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling This is master transmit address bit 4. FCC1: UTOPIA Slave Transmit Address Bit 4 This is slave transmit address bit 4. FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Baud Rate Generator 1 Output The CPM supports up to 8 BRGs for use internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 above), it is the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 above), the BRG1O input to the SIU timers is disabled. SPI: Select The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPISEL is the enable input to the SPI slave. In a multimaster environment, SPISEL (always an input) detects an error when more than one master is operating. SPI masters must output a slave select signal to enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI SPISEL while it is master causes an error. FCC1: UTOPIA Master Receive Address Bit 4 This is master receive address bit 4. FCC1: UTOPIA Slave Receive Address Bit 4 This is slave receive address bit 4. FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. SPI: Clock The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured. When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI. Input Input BRG1O Output SPI: SPISEL Input PD18 FCC1: RXADDR4 UTOPIA master FCC1: RXADDR4 UTOPIA slave FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling Output Input Input SPI: SPICLK Input/ Output MSC8103 Network Digital Signal Processor, Rev. 12 1-34 Freescale Semiconductor CPM Ports Table 1-10. Name GeneralPurpose I/O PD17 Port D Signals (Continued) Peripheral Controller: Dedicated I/O Protocol BRG2O Dedicated I/O Data Direction Output Description Baud Rate Generator 2 Output The CPM supports up to 8 BRGs for use internally to the MSC8103 and/or to provide an output to one of the 8 BRG pins. FCC1: UTOPIA Receive Parity This is the odd parity bit for RXD[0–7]. SPI: Master Output Slave Input The SPI interface comprises our signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiplemaster environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. FCC1: UTOPIA Transmit Parity This is the odd parity bit for TXD[0–7]. SPI: Master Input Slave Output The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. SMC1: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent or generalcircuit interface (GCI). FCC1: UTOPIA Master Transmit Address Bit 3 This is master transmit address bit 3. FCC1: UTOPIA Slave Transmit Address Bit 3 This is slave transmit address bit 3. FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: RXPRTY UTOPIA SPI: SPIMOSI Input Input/ Output PD16 FCC1: TXPRTY UTOPIA SPI: SPIMISO Output Input/ Output PD7 SMC1: SMSYN Input FCC1: TXADDR3 UTOPIA master FCC1: TXADDR3 UTOPIA slave FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling Output Input Input MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-35 Signals/Connections 1.7 JTAG Test Access Port Signals The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. Signal Name TCK TDI JTAG Test Access Port Signals Signal Description Type Input Input Test Clock A test clock signal for synchronizing JTAG test logic. Test Data Input A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data Output A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. Test Mode Select Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. Test Reset Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up. TDO Output TMS Input TRST Input 1.8 Reserved Signals Table 1-12. Signal Name TEST THERM[1–2] SPARE1, 5 Reserved Signals Signal Description Type Input — — Test Used for manufacturing testing. You must connect this input to GND. Leave disconnected. Spare Pins Leave disconnected for backward compatibility with future revisions of this device. MSC8103 Network Digital Signal Processor, Rev. 12 1-36 Freescale Semiconductor Physical and Electrical Specifications 2 This document contains detailed information on environmental limits, power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8103 communications processor, mask set 2K87M. For additional information, see the MSC8103 Reference Manual. 2.1 Absolute Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8103. Table 2-1. Rating Core supply voltage PLL supply voltage I/O supply voltage Input voltage3 Maximum operating temperature range4 Storage temperature range Notes: 1. 2. 3. 3 3 Absolute Maximum Ratings2 Symbol VDD VCCSYN VDDH VIN TJ TSTG Value –0.2 to 1.7 –0.2 to 1.7 –0.2 to 3.6 (GND – 0.2) to 3.6 –40 to 120 –55 to +150 Unit V V V V °C °C 3 4. Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. See Section 4.2, Electrical Design Considerations, on page 4-1 for more information. Section 4.1, Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature (TJ). MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-1 Physical and Electrical Specifications 2.2 Recommended Operating Conditions Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Rating SC140 core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range Recommended Operating Conditions Symbol VDD VCCSYN VDDH VIN TJ Value 275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 3.135 to 3.465 –0.2 to VDDH + 0.2 275 MHz: –40 to 105 300 MHz: –40 to 75 Unit V V V V V V °C °C 2.3 Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8103. Table 2-3. Thermal Characteristics Lidded FC-PBGA 17 × 17 mm Natural Convection Junction-to-ambient, single-layer board1, 2 Junction-to-ambient, four-layer board Junction-to-board3 Junction-to-case4 Notes: 1. 1, 3 Characteristic Symbol Unit 200 ft/min (1 m/s) airflow 37 18 °C/W °C/W °C/W °C/W RθJA or θJA RθJA or θJA RθJB or θJB RθJC or θJC 50 22 15 0.8 2. 3. 4. 5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board (JESD51-9) horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface without thermal grease. TBD = to be determined. If a thin (less than 50 micron) thermal grease interface is established to a heat sink from the lid, the junction to sink thermal resistance is about 0.7 °C/W. See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics. MSC8103 Network Digital Signal Processor, Rev. 12 2-2 Freescale Semiconductor DC Electrical Characteristics 2.4 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume the following system conditions: • • • • TJ = 0 – 100 °C VDD = 1.6 V ± 5% VDC VDDH = 3.3 V ± 5% VDC GND = 0 VDC Note: The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by ± 5 percent). Table 2-4. Characteristic Input high voltage , all inputs except CLKIN Input low voltage1 CLKIN input high voltage CLKIN input low voltage2 Input leakage current, VIN = VDDH Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current3, VIL = 0.8 V Signal high input current3, VIH = 2.0 V Output high voltage, IOH = –2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Notes: 1. 2. 3. 1 DC Electrical Characteristics Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH VOL Min 2.0 GND 2.5 GND — — — — 2.4 — Max 3.465 0.8 3.465 0.8 10 10 –4.0 4.0 — 0.4 Unit V V V V µA µA mA mA V V See Figure 2-1 for undershoot and overshoot voltages. The optimum CLKIN duty cycle is obtained when: VILC = VDDH – VIHC. Not tested. Guaranteed by design. VIH VDDH + 20% VDDH + 10% VDDH VIL GND GND – 0.3 V GND – 0.7 V Must not exceed 10% of clock period Figure 2-1. Overshoot/Undershoot Voltage for VIH and VIL Typical Power Dissipation Symbol PCORE PCPM PSIU PLCO PLCP PLSI Table 2-5. Characteristic Core power dissipation at 300 MHz CPM power dissipation at 200 MHz SIU power dissipation at 100 MHz Core leakage power CPM leakage power SIU leakage power Typical 450 320 80 3 6 2 Unit mW mW mW mW mW mW MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-3 Physical and Electrical Specifications 2.5 Clock Configuration The following sections provide a general description of clock configuration. 2.5.1 Valid Clock Modes Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The user must ensure that maximum frequency values are not exceeded. Table 2-6. Characteristic Core Frequency CPM Frequency (CPMCLK) Bus Frequency (BCLK) Serial Communication Controller Clock Frequency (SCLK) Baud Rate Generator Clock Frequency (BRGCLK) External Clock Output Frequency (CLKOUT) Maximum Frequencies Maximum Frequency in MHz 275 183.33 91.67 91.67 91.67 91.67 300 200 100 100 100 100 Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option determines the CLKIN, SC140, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from three dedicated input pins (MODCK[1–3]) and three bits from the hard reset configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140, SCC clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration changes only when the internal PORESET signal is deasserted. The following factors are configured: • SPLL pre-division factor (SPLL PDF) • SPLL multiplication factor (SPLL MF) • Bus post-division factor (Bus DF) • CPM division factor (CPM DF) • Core division factor (Core DF) • CPLL pre-division factor (CPLL PDF) • CPLL multiplication factor (CPLL MF) The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256. Note: Refer to Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M (AN2306) for details on clock configuration. 2.5.2 Clocks Programming Model This section describes the clock registers in detail. The registers discussed are as follows: • System Clock Control Register (SCCR) • System Clock Mode Register (SCMR) MSC8103 Network Digital Signal Processor, Rev. 12 2-4 Freescale Semiconductor Clock Configuration 2.5.2.1 System Clock Control Register Bit Type Reset 0 1 2 3 4 5 6 7 — 8 9 10 11 12 13 14 15 Reserved — Bit Type Reset 16 17 18 19 20 21 — Reserved — 22 23 24 25 26 27 CLKODIS R/W 0 28 — 29 30 R/W 0 31 DFBRG 1 Reserved — Figure 2-2. System Clock Control Register (SCCR)—0x10C80 SCCR is memory-mapped into the SIU register map of the MSC8103. Table 2-7. Name Bit No. — 0–26 CLKODIS 27 SCCR Bit Descriptions Description Settings Defaults PORESET — 0 Hard Reset — Unaffected Reserved. Write to 0 fro future compatibility. CLKOUT Disable Disables the CLKOUT signal. The value of CLKOUT when disabled is indeterminate (can be 1 or 0). Reserved. Write to 0 fro future compatibility. Division Factor for the BRG Clock Defines the BRGCLK frequency. Changing this value does not result in a loss of lock condition. 00 01 10 11 Divide by 4 Divide by 16 (default value) Divide by 64 Divide by 256 0 1 CLKOUT enabled (default) CLKOUT disabled — 28–29 DFBRG 30–31 — 01 — Unaffected 2.5.2.2 System Clock Mode Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COREPDF Type Reset COREMF R — BUSDF CPMDF Bit 16 17 18 19 20 21 22 23 24 — R — 25 DLLDIS 26 — 27 28 29 30 31 SPLLPDF Type Reset SPLLMF COREDF Figure 2-3. System Clock Mode Register (SCMR)—0x10C88 SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For details of the available setting options, see AN2306/D. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-5 Physical and Electrical Specifications Table 2-8. Name Bit No. COREPDF 0–3 SCMR Field Descriptions Description Settings 0000 CPLL PDF = 1 0001 CPLL PDF = 2 0010 CPLL PDF = 3 0011 CPLL PDF = 4 All other combinations not used. 0101 CPLL MF = 10 0110 CPLL MF = 12 0111 CPLL MF = 14 All other combinations not used. 0001 Bus DF = 2 0010 Bus DF = 3 0011 Bus DF = 4 0100 Bus DF = 5 0101 Bus DF = 6 All other combinations not used. 0000 CPM DF = 1 0001 CPM DF = 2 0010 CPM DF = 3 All other combinations not used. 0000 SPLL PDF = 1 0001 SPLL PDF = 2 0010 SPLL PDF = 3 0011 SPLL PDF = 4 0100 SPLL PDF = 5 0101 SPLL PDF = 6 All other combinations not used 0101 SPLL MF = 10 0110 SPLL MF = 12 0111 SPLL MF = 14 1000 SPLL MF = 16 1001 SPLL MF = 18 1010 SPLL MF = 20 1011 SPLL MF = 22 1100 SPLL MF = 24 1101 SPLL MF = 26 1110 SPLL MF = 28 1111 SPLL MF = 30 All other combinations not used Defaults PORESET Configuration Pins Hard Reset Unaffected Core PLL Pre-Division Factor COREMF 4–7 Configuration Pins Unaffected Core Multiplication Factor BUSDF 8–11 Configuration Pins Unaffected 60x-compatible Bus Division Factor CPMDF 12–15 Configuration Pins Unaffected CPM Division Factor SPLLPDF 16–19 Configuration Pins Unaffected SPLL Pre-Division Factor SPLLMF 20–23 Configuration Pins Unaffected SPLL Multiplication Factor — 24 DLLDIS 25 — 26–27 COREDF 28–31 — Configuration Pins — Configuration Pins — Unaffected — Unaffected Reserved DLL Disable Reserved Core Division Factor 0000 CORE DF = 1 0001 CORE DF = 2 0010 CORE DF = 3 0011 CORE DF = 4 0100 CORE DF = 5 0101 CORE DF = 6 All other combinations not used. 0 1 DLL operation is enabled DLL is disabled MSC8103 Network Digital Signal Processor, Rev. 12 2-6 Freescale Semiconductor AC Timings 2.6 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line. 2.6.1 Output Buffer Impedances Table 2-9. Output Buffers Output Buffer Impedances Typical Impedance (Ω) 35 35 55 System Bus Memory Controller Parallel I/O Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature. 2.6.2 Start-Up Timing Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.3 describes the clocking characteristics. Section 2.6.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8103 device: • • • PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-14 for timing. If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDDH levels and then the VDD levels (see Figure 2-5 and Figure 2-6). CLKIN can start toggling after VDDH reaches its nominal level, but it must toggle before VDD reaches 0.5 V to guarantee correct device operation (see Figure 2-4 and Figure 2-6). The following figures show acceptable start-up sequence examples. Figure 2-4 shows a sequence in which VDD and VDDH are raised together. Figure 2-5 shows a sequence in which CLKIN starts toggling after VDDH reaches its nominal level and before VDD is applied. Figure 2-6 shows a sequence in which VDD is raised after VDDH and CLKIN begins to toggle shortly before VDD reaches the 0.5 V level. VDDH = Nominal Value VDD = Nominal Value 1 3.3 V VDDH Nominal Level Voltage 2.2 V 1.6 V VDD Nominal Level o.5 V Time PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted VDD/VDDH Applied Figure 2-4. Start-Up Sequence with VDD and VDDH Raised Together MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-7 Physical and Electrical Specifications VDDH = Nominal VDD = Nominal 1 3.3 V VDDH Nominal Voltage 1.6 V 1.06 V VDD Nominal Time PORESET/TRST asserted VDDH applied VDD applied CLKIN starts toggling PORESET/TRST Deasserted Figure 2-5. Start-Up Sequence with CLKIN Started After VDDH and Before VDD VDDH = Nominal VDD = Nominal 1 3.3 V VDDH Nominal Voltage 1.6 V 1.06 V o.5 V VDD Nominal Time PORESET/TRST asserted VDDH applied VDD applied PORESET/TRST deasserted CLKIN starts toggling Figure 2-6. Start-Up Sequence with VDDH Raised Before VDD with CLKIN Started Before VDD = 0.5 V 2.6.3 Clocking and Timing Characteristics Table 2-10. Characteristic System Clock Parameters Minimum — 18 — — — — Maximum 0.5 100 5 2 (0.01/CLKOUT) + CLKIN jitter 5 Unit ns MHz ns ns ns ns Phase Jitter between BCLK and DLLIN CLKIN frequency CLKIN slope DLLIN slope CLKOUT frequency jitter Delay between CLKOUT and DLLIN Notes: 1. 2. 1,2 Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the predivider (SPLLMFCLK) higher than 18 MHz. CLKIN should have a 50% ± 5% duty cycle. MSC8103 Network Digital Signal Processor, Rev. 12 2-8 Freescale Semiconductor AC Timings Table 2-11. Clock Ranges Maximum Rated Core Frequency Clock Symbol All Min Max. Values for SC140 Clock Rating of: 275 MHz 91.67 MHz 34.38 MHz 91.67 MHz 91.67 MHz 183.3 MHz 275 MHz 91.67 MHz 22.91 MHz 5.73 MHz 1.43 MHz 300 MHz 100 MHz 37.5 MHz 100 MHz 100 MHz 200 MHz 300 MHz 100 MHz 25 MHz 6.25 MHz 1.56 MHz Input Clock SPLL MF Clock Bus/Output Serial Communications Controller Communications Processor Module SC140 Core Baud Rate Generator • For BRG DF = 4 • For BRG DF = 16 (default) • For BRG DF = 64 • For BRG DF = 256 CLKIN SPLLMFCLK BCLK CLKOUT SCLK CPMCLK DSPCLK BRGCLK 18 MHz 18 MHz 18 MHz 35 MHz 70 MHz 72 MHz 36 MHz 9 MHz 2.25 MHz 562.5 KHz 2.6.4 Reset Timing The MSC8103 has several inputs to the reset logic: • Power-on reset (PORESET) • External hard reset (HRESET) • External soft reset (SRESET) Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET. When the external PORESET signal is deasserted, the MSC8103 samples several configuration pins: • RSTCONF—determines whether the MSC8103 is a master (0) or slave (1) device • DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1) • HPE—disable (0) or enable (1) the host port (HDI16) • BTM[0–1]—boot from external memory (00) or the HDI16 (01) All these reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes. Table 2-12. Name Power-on reset (PORESET) Hard reset (HRESET) Soft reset (SRESET) Reset Causes Description Direction Input Input/Output PORESET initiates the power-on reset flow that resets all the MSC8103s and configures various attributes of the MSC8103, including its clock mode. The MSC8103 can detect an external assertion of HRESET only if it occurs while the MSC8103 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an opendrain pin. The MSC8103 can detect an external assertion of SRESET only if it occurs while the MSC8103 is not asserting reset. SRESET is an open-drain pin. Input/Output MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-9 Physical and Electrical Specifications 2.6.4.1 Reset Operation The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and reduced reset configuration. 2.6.4.2 Power-On Reset Flow Asserting the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 VCC. As Table 2-13 shows, the MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the rising edge of PORESET. In addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the MSC8103. The signals on these pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies. Table 2-13. Pin RSTCONF External Configuration Signals Settings 0 1 0 1 0 1 Reset Configuration Master. Reset Configuration Slave. SC140 starts the normal processing mode after reset. SC140 enters Debug mode immediately after reset. Host port disabled (hardware reset configuration enabled). Host port enabled. Description Reset Configuration Input line sampled by the MSC8103 at the rising edge of PORESET. EONCE Event Bit 0 Input line sampled after SC140 core PLL locks. Holding EE0 high when PORESET is deasserted puts the SC140 into Debug mode. Host Port Enable Input line sampled at the rising edge of PORESET. If asserted, the Host port is enabled, the system data bus is 32-bit wide, and the Host must program the reset configuration word. Boot Mode Input lines sampled at the rising edge of PORESET, which determine the MSC8103 Boot mode. DBREQ/ EE0 HPE/EE1 BTM[0–1]/ EE[4–5] 00 01 10 11 MSC8103 boots from external memory. MSC8103 boots from HDI16. Reserved. Reserved. Table 2-14. No. 1 Reset Timing Expression 16 / CLKIN 888.8 213.3 1024 / CLKIN 56.89 13.65 800 / SPLLMFCLK 44.4 32.0 μs μs μs μs — — ns ns Characteristics Required external PORESET duration minimum • CLKIN = 18 MHz • CLKIN = 75 MHz Delay from deassertion of external PORESET to deassertion of internal PORESET • CLKIN = 18 MHz • CLKIN = 75 MHz Delay from deassertion of internal PORESET to SPLL lock • SPLLMFCLK = 18 MHz • SPLLMFCLK = 25 MHz Min Max Unit 2 3 MSC8103 Network Digital Signal Processor, Rev. 12 2-10 Freescale Semiconductor AC Timings Table 2-14. No. 4 Reset Timing (Continued) Expression 3073 / BLCK 170.72 40.97 0.0 Characteristics Delay from SPLL lock to DLL lock • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled Delay from SPLL lock to HRESET deassertion • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled — BCLK = 18 MHz — BCLK = 75 MHz Delay from SPLL lock to SRESET deassertion • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled — BCLK = 18 MHz — BCLK = 75 MHz Min Max Unit — 3585 / BLCK μs μs ns 5 199.17 47.5 512 / BLCK 28.4 6.83 3588 / BLCK 199.33 47.84 515 / BLCK 28.61 6.87 μs μs μs μs 6 μs μs μs μs Note: Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence. 2.6.4.3 Host Reset Configuration Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the signals described in Table 2-13 one the rising edge of PORESET when the signal is deasserted. If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device extends the internal PORESET until the host programs the reset configuration word register. The host must write four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word, which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the MSC8103 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is then released. The SRESET is released three bus clocks later (see Figure 2-7). MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-11 Physical and Electrical Specifications 1 PORESET Input PORESET Internal RSTCONF, HPE HRM, BTM pins are sampled asserted for min 16 CLKIN. Any time HRESET Output (I/O) Host programs Reset Configuration Word MODCK[1–3] pins are sampled. MODCK_H bits are ready for PLL. PLL locked DLL locked SRESET Output (I/O) 2 3 4 5 6 PLL locks after 800 SPLLMFCLKs and DLL locks 3073 BUS clocks after PLL is locked. When DLL is disabled, reset period is shortened by DLL lock time. HRESET/SRESET are extended for 512/515 BUS clocks, respectively, from PLL and DLL lock Figure 2-7. Host Reset Configuration Timing MSC8103 Network Digital Signal Processor, Rev. 12 2-12 Freescale Semiconductor AC Timings 2.6.4.4 Hardware Reset Configuration Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on RSTCONF while PORESET changes from assertion to deassertion determines the MSC8103 configuration. If RSTCONF is deasserted (driven high) while PORESET changes, the MSC8103 acts as a configuration slave. If RSTCONF is asserted (driven low) while PORESET changes, the MSC8103 acts as a configuration master. Section 2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master” and “configuration slave.” Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts HRESET and SRESET throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the MSC8103’s working mode. Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to MODCK[1–3], which are sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled. If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is locked. During PLL and DLL locking, HRESET and SRESET are asserted. HRESET remains asserted for another 512 BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time. Figure 2-8 shows the power-on reset flow. 1 PORESET Input PORESET Internal asserted for min 16 CLKIN. RSTCONF is sampled for master/slave determination HRESET Output (I/O) MODCK[1–3] are sampled. MODCK_H bits are ready for PLL. SRESET Output (I/O) 2 In reset configuration mode: reset configuration sequence occurs in this period. PLL locked 3 DLL locked 4 5 6 HRESET/SRESET are extended for 512/515 bus clocks, respectively, from PLL and DLL Lock time. PLL locks after 800 SPLLMFCLKs. DLL locks 3073 bus clocks after PLL is locked. When DLL is disabled, reset period is shortened by 3073 bus clocks. Figure 2-8. Hardware Reset Configuration Timing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-13 Physical and Electrical Specifications 2.6.5 System Bus Access Timing 2.6.5.1 Core Data Transfers Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is DLLIN. Memory controller signals, however, trigger on four points within a DLLIN cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of DLLIN (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows. Table 2-15. Tick Spacing for Memory Controller Signals Tick Spacing (T1 Occurs at the Rising Edge of DLLIN) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1/4 DLLIN 3/10 DLLIN 4/14 DLLIN T3 1/2 DLLIN 1/2 DLLIN 1/2 DLLIN T4 3/4 DLLIN 8/10 DLLIN 11/14 DLLIN Figure 2-9 is a graphical representation of Table 2-15. DLLIN T1 DLLIN T1 DLLIN T1 T2 T3 T4 T2 T3 T4 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6 for 1:2.5 for 1:3.5 Figure 2-9. Internal Tick Spacing for Memory Controller Signals Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs change only on the DLLIN rising edge. MSC8103 Network Digital Signal Processor, Rev. 12 2-14 Freescale Semiconductor AC Timings Table 2-16. No. 10 11a 11b 11c 11d AC Timing for SIU Inputs Value2 0.5 3.5 5.0 4.0 3.5 4.0 4.0 3.0 3.5 3.5 5.0 4.5 2.5 5.0 Characteristic Hold time for all signals after the 50% level of the DLLIN rising edge ABB/AACK set-up time before the 50% level of the DLLIN rising edge DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge ARTRY set-up time before the 50% level of the DLLIN rising edge TA set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode TEA set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode PSDVAL set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode TS set-up time before the 50% level of the DLLIN rising edge BG set-up time before the 50% level of the DLLIN rising edge Data bus set-up time before the 50% level of the DLLIN rising edge in Normal • Pipeline mode • Non-pipeline mode Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes • Pipeline mode • Non-pipeline mode DP set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode Address bus set-up time before the 50% level of the DLLIN rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • Non-extra cycle mode (SIUBCR[EXDD] = 1) Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • Non-extra cycle mode (SIUBCR[EXDD] = 1) PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge 1. 2. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11e 11f 11g 11h 12 13 2.5 8.0 4.0 9.0 5.0 8.0 ns ns ns ns ns ns 14 15a 15b 5.0 5.5 3.0 ns ns ns 161 Notes: The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation. Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are measured at the pin. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-15 Physical and Electrical Specifications Table 2-17. No. 31a AC Timing for SIU Outputs Maximum2 Min. 30 pF 50 pF 6.5 5.5 4.5 5.0 5.5 5.0 7.8 7.0 7.0 5.0 6.5 7.5 5.5 8.0 7.0 5.5 6.0 5.5 5.0 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Characteristic TA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode TEA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode PSDVAL delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode Address bus delay from the 50% level of the DLLIN rising edge • Multi master mode (SIUBCR[EBM] = 1) • Single master mode (SIUBCR[EBM] = 0) Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge BADDR delay from the 50% level of the DLLIN rising edge Data bus delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode DP delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge DBG/BR/DBB delay from the 50% level of the DLLIN rising edge AACK/ABB/CS delay from the 50% level of the DLLIN rising edge BG delay from the 50% level of the DLLIN rising edge TS delay from the 50% level of the DLLIN rising edge Delay from the 50% level of the DLLIN rising edge for all other signals 1. Units 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 4.0 3.0 3.5 4.0 3.5 6.3 5.5 5.5 3.5 5.0 6.0 4.0 6.5 5.5 4.0 4.5 4.0 3.5 4.5 31b 31c 32a 32b 32c 33a 33b 34 35a 35b 35c 35d 36 Notes: 2. The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. • Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus frequencies. • In single-master mode, the frequency depends on the timing of the devices connected to the MSC8103. Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are measured at the pin. MSC8103 Network Digital Signal Processor, Rev. 12 2-16 Freescale Semiconductor AC Timings DLLIN 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs 11 10 12 Data bus inputs—normal mode 10 Data bus inputs—ECC and parity modes DP inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs PUPMWAIT/IRQn input 13 14 15 16 10 31 PSDVAL/TEA/TA outputs 32 Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs Data bus outputs DP outputs 33a 33b Memory controller/ALE signals 34 35 AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals 36 All other normal mode outputs Figure 2-10. Bus Signal Timing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-17 Physical and Electrical Specifications 2.6.5.2 DMA Data Transfers Table 2-18 describes the DMA signal timing. Table 2-18. Number 72 73 74 75 76 DMA Signals Minimum 6 0.5 9 0.5 0.5 Characteristic DREQ set-up time before DLLIN falling edge DREQ hold time after DLLIN falling edge DONE set-up time before DLLIN rising edge DONE hold time after DLLIN rising edge DACK/DRACK/DONE delay after DLLIN rising edge Maximum — — — — 9 Units ns ns ns ns ns The DREQ signal is synchronized with the falling edge of DLLIN. DONE timing is relative to the rising edge of DLLIN. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-18. Figure 2-11 shows synchronous peripheral interaction. DLLIN 73 72 DREQ 75 74 DONE Input 76 DACK /DONE/DRACK Outputs Figure 2-11. DMA Signals 2.6.6 Number 44a 44b 44c HDI16 Signals Table 2-19. Host Interface (HDI16) Timing1, 2 Expression (1.5 × TC) + 5.0 TC + 5.0 (2.5 × TC) + 5.0 Characteristics3 Read data strobe minimum assertion width HACK read minimum assertion width 4 Value Note 11 Note 11 Note 11 Unit ns ns ns Read data strobe minimum deassertion width4 HACK read minimum deassertion width Read data strobe minimum deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK minimum deassertion width after “Last Data Register” reads5,6 Write data strobe minimum assertion width8 HACK write minimum assertion width Write data strobe minimum deassertion width8 HACK write minimum deassertion width after ICR, CVR and Data Register writes5 Host data input minimum set-up time before write data strobe deassertion8 Host data input minimum set-up time before HACK write deassertion 45 46 (1.5 × TC) + 5.0 Note 11 ns (2.5 × TC) + 5.0 — Note 11 5.0 ns ns 47 MSC8103 Network Digital Signal Processor, Rev. 12 2-18 Freescale Semiconductor AC Timings Table 2-19. Number 48 49 Host Interface (HDI16) Timing1, 2 (Continued) Expression 8 Characteristics3 Host data input minimum hold time after write data strobe deassertion Host data input minimum hold time after HACK write deassertion Value 5.0 Unit ns — Read data strobe minimum assertion to output data active from high impedance4 HACK read minimum assertion to output data active from high impedance Read data strobe maximum assertion to output data HACK read maximum assertion to output data valid valid4 — (2.0 × TC) + 5.0 5.0 Note 11 ns ns 50 51 52 53 54 55 56 57 Read data strobe maximum deassertion to output data high impedance4 HACK read maximum deassertion to output data high impedance Output data minimum hold time after read data strobe deassertion4 Output data minimum hold time after HACK read deassertion HCS[1–2] minimum assertion to read data strobe assertion4 HCS[1–2] minimum assertion to write data strobe assertion8 HCS[1–2] maximum assertion to output data valid HCS[1–2] minimum hold time after data strobe deassertion9 HA[0–3], HRW minimum set-up time before data strobe assertion9 • Read • Write HA[0–3], HRW minimum hold time after data strobe deassertion9 Maximum delay from read data strobe deassertion to host request deassertion for “Last Data Register” read4, 5, 10 Maximum delay from write data strobe deassertion to host request deassertion for “Last Data Register” write5,8,10 Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion 1. 2. 3. 4. 5. — — — — TC + 5.0 — — 5.0 5.0 5.0 5.0 Note 11 0.0 0 5.0 ns ns ns ns ns ns ns ns ns ns ns ns ns 58 61 62 63 64 Notes: — (3.5 × TC) + 5.0 (3.0 × TC) + 5 (5.0 × TC) + 5.0 (3.5 × TC) + 5.0 5.0 Note 11 Note 11 Note 11 Note 11 TC = 1/ DSPCLK. At 300 MHz, TC = 3.3 ns In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode. In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe (HDS/HDS) in the single data strobe mode. 10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request). 11. Compute the value using the expression. Figure 2-12 and Figure 2-13 show HDI16 read signal timing. Figure 2-14 and Figure 2-15 show HDI16 write signal timing. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-19 Physical and Electrical Specifications HA[0–3] 57 53 HCS[1–2] 57 58 58 56 HRW 44a HDS 44b 51 55 50 49 HD[0–15] 61 HREQ (single host request) HRRQ (double host request) 52 44c Figure 2-12. Read Timing Diagram, Single Data Strobe HA[0–3] 57 53 HCS[1–2] 44a HRD 44b 51 55 50 49 HD[0–15] 61 HREQ (single host request) HRRQ (double host request) 52 44a 58 56 Figure 2-13. Read Timing Diagram, Double Data Strobe MSC8103 Network Digital Signal Processor, Rev. 12 2-20 Freescale Semiconductor AC Timings HA[0–3] 57 54 HCS[1–2] 57 58 58 56 HRW 45 HDS 46 47 48 HD[0–15] HREQ (single host request) HTRQ (double host request) 62 Figure 2-14. Write Timing Diagram, Single Data Strobe HA[0–3] 57 54 HCS[1–2] 45 HWR 46 58 56 47 48 HD[0–15] 62 HREQ (single host request) HTRQ (double host request) Figure 2-15. Write Timing Diagram, Double Data Strobe MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-21 Physical and Electrical Specifications Figure 2-16 shows Host DMA read timing. HREQ (Output) 64 44a HACK RX[0–3] Read 63 44b 50 49 HD[0–15] (Output) Data Valid 51 52 Figure 2-16. Host DMA Read Timing Diagram, HPCR[OAD] = 0 Figure 2-17 shows Host DMA write timing. HREQ (Output) 64 45 HACK TX[0–3] Write 63 46 47 48 HD[0–15] (Output) Data Valid Figure 2-17. Host DMA Write Timing Diagram, HPCR[OAD] = 0 MSC8103 Network Digital Signal Processor, Rev. 12 2-22 Freescale Semiconductor AC Timings 2.6.7 No. 39 CPM Timings Table 2-20. CPM Input Characteristics Typical 10 5 0 3 20 5 0 5 5 5 10 3 Characteristic FCC input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) SCC/SMC/SPI/I2C input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) TDM input set-up time before low-to-high serial clock transition TDM input hold time after low-to-high serial transition PIO/TIMER/DMA input set-up time before low-to-high serial clock transition PIO/TIMER/DMA input hold time after low-to-high serial clock transition FCC, SCC, SMC, SPI, I2C are non-multiplexed serial interface signals. Unit ns ns ns ns ns ns ns ns ns ns ns ns 17 18 19 20 21 22 23 Note: Table 2-21. No. 41 CPM Output Characteristics Min 0 2 0 0 5 1 Characteristic FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) SCC/SMC/SPI/I2C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) TDM output delay after low-to-high serial clock transition PIO/TIMER/DMA output delay after low-to-high serial clock transition FCC, SCC, SMC, SPI, I C are Non-Multiplexed Serial Interface signals. 2 Max 6 18 20 30 15 14 Unit ns ns ns ns ns ns 38 40 42 Note: BRGxO 17a 29a FCC inputs 41a FCC outputs Figure 2-18. FCC Internal Clock Diagram MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-23 Physical and Electrical Specifications Serial input clock 17b 39b FCC inputs 41b FCC outputs Figure 2-19. FCC External Clock Diagram BRGxO 19a 18a SCC/SMC/SPI/I2C inputs 38a SCC/SMC/SPI/I2C outputs Figure 2-20. SCC/SMC/SPI/I2C Internal Clock Diagram Serial input clock 19b 18b SCC/SMC/SPI/I2C inputs 38b SCC/SMCSPI/I2C outputs Figure 2-21. SCC/SMC/SPI/I2C External Clock Diagram Serial input clock 20 TDM inputs 21 40 TDM outputs Figure 2-22. TDM Signal Diagram MSC8103 Network Digital Signal Processor, Rev. 12 2-24 Freescale Semiconductor AC Timings DLLIN 23 22 PIO/TIMER/DMA inputs 42 PIO/TIMER/DMA outputs Figure 2-23. PIO, Timer, and DMA Signal Diagram Note: The timing values refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the referenced internal controllers and supported communication protocols. For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of signals; the direction (input or output) of some of the shared signal names depends on the selected mode. 2.6.8 JTAG Signals Table 2-22. JTAG Timing All frequencies Unit Min Max 40.0 — — 3.0 — — 15.0 20.0 — — MHz ns ns ns ns ns ns ns ns ns 0.0 25.0 12.5 0.0 6.0 3.0 0.0 0.0 100.0 40.0 No. 500 501 502 503 508 509 510 511 512 513 TCK frequency of operation TCK cycle time Characteristics TCK clock pulse width measured at 1.6 V TCK rise and fall times TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low 501 502 TCK (Input) VIH 503 VM VIL 503 502 VM Figure 2-24. Test Clock Input Timing Diagram MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-25 Physical and Electrical Specifications TCK (Input) TDI TMS (Input) VIH VIL 508 Input Data Valid 510 509 TDO (Output) 511 TDO (Output) 510 TDO (Output) Output Data Valid Output Data Valid Figure 2-25. Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 Figure 2-26. TRST Timing Diagram MSC8103 Network Digital Signal Processor, Rev. 12 2-26 Freescale Semiconductor Packaging 3 This chapter provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded flip chip-plastic ball grid array (FC-PBGA). 3.1 FC-PBGA Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8103 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). Note: The package description in this chapter applies to packages with lead-bearing and lead-free spheres. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-1 Packaging Top View 1 A 2 IRQ5 3 D1 4 D4 5 D7 6 D11 7 D17 8 D22 9 D27 10 D32 11 D37 12 D42 13 D46 14 D51 15 D55 16 D60 17 D62 18 D63 19 A B IRQ1 IRQ3 D0 D3 D6 D10 D16 D21 D26 D31 D36 D41 D45 D50 D54 D59 PWE6 DBG BADDR 28 B C THERM 1 DP0 IRQ4 D2 D5 D9 D15 D20 D25 D30 D35 D40 D44 D49 D53 D58 D61 DBB BADDR 29 C D EE1 EE0 THERM 2 IRQ2 IRQ6 D8 D14 D19 D24 D29 D34 D39 D43 D48 D52 D57 PWE5 GBL BADDR D 27 PSD CAS E EE4 EE3 EE2 VDDH VDD VDDH D13 VDDH VDD VDDH VDDH VDD VDDH D47 VDDH D56 PSDA 10 MOD CK1 E F TDO EED EE5 VDD GND IRQ7 GND D18 GND D28 GND D38 GND PSD WE GND VDD PWE7 MOD CK2 BCTL0 F G PA31 TMS TRST TCK VDDH GND D12 GND D23 GND D33 GND PSD VAL GND VDDH VDDH TEA MOD CK3 POE G H PB30 PD31 PC31 PB31 GND TDI GND BADDR BADDR 31 30 GND VDD BR ALE PWE4 H M J PA29 PD30 PC30 VDD GND GND PA30 TA GND VDDH VDDH PSDA MUX PGTA PWE3 J SC 81 K PA28 PD29 PC29 PB29 VDDH GND GND GND PWE2 GND VDDH PWE1 PWE0 CS2 K 03 L PA27 PB28 PC28 VDD GND GND PC27 CS6 GND GND VDD CS1 CS3 BCTL1 L M PB27 PC26 PB26 VDDH GND PA26 PA16 A21 A26 GND CS0 CS5 CS7 CS4 M N PC25 PA25 PB25 VDD PC23 GND PD17 CLKIN GND PC6 TSIZ3 TT1 TT0 A1 VDDH VDDH A28 A30 A31 N P PC24 PA24 PB24 PA23 PB20 GND GND DLL_IN GND PC4 GND GND GND GND GND VDD A23 A27 A29 P R PC22 SPARE 1 PA22 PB18 PA19 VDDH VDDH VDD VDDH VDDH VDD VDDH VDD VDDH VDDH A15 A19 A24 A25 R T PB21 PB22 PA20 PA17 PC13 PC14 VCC SYN1 CLK OUT PA12 PC7 PA6 AACK TS A3 VDDH A12 A16 A20 A22 T U PA21 PB19 PD18 PD16 NMI RST CONF GND SYN1 GND SYN PA13 PA10 PA8 SPARE ARTRY 5 ABB BG TBST TT2 A4 A8 A11 A17 A18 U V PB23 PD19 PC15 PC12 NMI_ HRESET OUT PA11 PD7 PA7 TSIZ0 TT3 A2 A6 A9 A13 A14 V W 1 PA18 2 PA15 3 PO SRESET RESET 4 5 TEST VCC SYN 7 PA14 PA9 PC5 INT _OUT 11 TSIZ2 TSIZ1 13 TT4 A0 A5 16 A7 A10 W 6 8 9 10 12 14 15 17 18 19 Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-1. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View MSC8103 Network Digital Signal Processor, Rev. 12 3-2 Freescale Semiconductor FC-PBGA Package Description Bottom View 19 A 18 D63 17 D62 16 D60 15 D55 14 D51 13 D46 12 D42 11 D37 10 D32 9 D27 8 D22 7 D17 6 D11 5 D7 4 D4 3 D1 2 IRQ5 1 A B BADDR 28 DBG PWE6 D59 D54 D50 D45 D41 D36 D31 D26 D21 D16 D10 D6 D3 D0 IRQ3 IRQ1 B C BADDR 29 DBB D61 D58 D53 D49 D44 D40 D35 D30 D25 D20 D15 D9 D5 D2 IRQ4 DP0 THERM C 1 D BADDR 27 PSD CAS GBL PWE5 D57 D52 D48 D43 D39 D34 D29 D24 D19 D14 D8 IRQ6 IRQ2 THERM 2 EE0 EE1 D E MOD CK1 PSDA 10 D56 VDDH D47 VDDH VDD VDDH VDDH VDD VDDH D13 VDDH VDD VDDH EE2 EE3 EE4 E F BCTL0 MOD CK2 PWE7 VDD GND PSD WE GND D38 GND D28 GND D18 GND IRQ7 GND VDD EE5 EED TDO F G POE MOD CK3 TEA VDDH VDDH GND PSD VAL GND D33 GND D23 GND D12 GND VDDH TCK TRST TMS PA31 G H PWE4 ALE BR VDD GND BADDR BADDR 30 31 GND TDI GND PB31 PC31 PD31 PB30 H 81 03 J PWE3 PGTA PSDA MUX VDDH VDDH GND TA PA30 GND GND VDD PC30 PD30 PA29 J K CS2 PWE0 PWE1 VDDH GND PWE2 GND GND GND VDDH PB29 PC29 PD29 PA28 K L BCTL1 M CS4 CS7 CS5 CS0 GND A26 A21 M CS3 CS1 VDD GND GND CS6 SC PC27 GND GND VDD PC28 PB28 PA27 L PA16 PA26 GND VDDH PB26 PC26 PB27 M N A31 A30 A28 VDDH VDDH A1 TT0 TT1 TSIZ3 PC6 GND CLKIN PD17 GND PC23 VDD PB25 PA25 PC25 N P A29 A27 A23 VDD GND GND GND GND GND PC4 GND DLL_IN GND GND PB20 PA23 PB24 PA24 PC24 P R A25 A24 A19 A15 VDDH VDDH VDD VDDH VDD VDDH VDDH VDD VDDH VDDH PA19 PB18 PA22 SPARE 1 PC22 R T A22 A20 A16 A12 VDDH A3 TS AACK PA6 PC7 PA12 CLK OUT VCC SYN1 PC14 PC13 PA17 PA20 PB22 PB21 T U A18 A17 A11 A8 A4 TT2 TBST ARTRY SPARE 5 ABB PA8 PA10 PA13 GND SYN1 GND SYN RST CONF NMI PD16 PD18 PB19 PA21 U V A14 A13 A9 A6 A2 TT3 TSIZ0 BG PA7 PD7 PA11 HRESET NMI_ OUT PO RESET 5 PC12 PC15 PD19 PB23 V W A10 19 18 A7 17 A5 16 A0 15 TT4 14 TSIZ1 13 TSIZ2 12 INT _OUT 11 PC5 10 PA9 9 PA14 8 VCC SYN 7 TEST 6 SRESET PA15 3 PA18 2 1 W 4 Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-2. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-3 Packaging Table 3-1. MSC8103 Signal Listing By Name Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK ABB Number W15 N14 V15 T14 U15 W16 V16 W17 U16 V17 W18 U17 T16 V18 V19 R16 T17 U18 U19 R17 T18 M13 T19 P17 R18 R19 M14 P18 N17 P19 N18 N19 T12 V11 MSC8103 Network Digital Signal Processor, Rev. 12 3-4 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O BRG5O BRG6O BRG7O BRG8O BTM0 BTM1 CD for FCC1 CD for FCC2 CD/RENA for SCC1 CD/RENA for SCC2 CLK1 CLK2 CLK3 CLK4 Number H18 U12 D19 B19 C19 H14 H13 F19 L19 V12 E18 F18 G18 H17 H3 V2 J3 N7 K3 L3 L7 M2 N1 P1 E1 F3 N10 P10 T6 V4 H3 J3 K3 L3 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-5 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CTS for FCC1 CTS for FCC2 CTS/CLSN for SCC1 CTS/CLSN for SCC1 CTS/CLSN for SCC2 CTS/CLSN for SCC2 D0 D1 D2 D3 D4 D5 D6 D7 Number L7 M2 N1 P1 N5 R1 N8 T8 G1 M1 J7 M3 M16 L17 K19 L18 M19 M17 L13 M18 T10 W10 K3 V3 L3 T5 B3 A3 C4 B4 A4 C5 B5 A5 MSC8103 Network Digital Signal Processor, Rev. 12 3-6 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 Number D6 C6 B6 A6 G7 E7 D7 C7 B7 A7 F8 D8 C8 B8 A8 G9 D9 C9 B9 A9 F10 D10 C10 B10 A10 G11 D11 C11 B11 A11 F12 D12 C12 B12 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-7 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK2 DACK3 DACK4 DBB DBG DBREQ DLLIN DP0 DP1 DP2 DP3 Number A12 D13 C13 B13 A13 E14 D14 C14 B14 A14 D15 C15 B15 A15 E16 D16 C16 B16 A16 C17 A17 A18 N5 N1 D5 F6 C18 B18 D2 P8 C2 B1 D4 B2 MSC8103 Network Digital Signal Processor, Rev. 12 3-8 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name DP4 DP5 DP6 DP7 DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EE0 EE1 EE2 EE3 EE4 EE5 EED EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 EXT1 EXT2 GBL GND GND GND GND GND GND GND GND Number C3 A2 D5 F6 H2 J2 R1 P1 C3 A2 D2 D1 E3 E2 E1 F3 F2 B1 C3 C2 B2 D4 A2 H3 N5 D18 F11 F13 F15 F5 F7 F9 G10 G12 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-9 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDSYN GNDSYN1 H8BIT HA0 HA1 Number G14 G6 G8 H15 H5 H7 J14 J5 J6 K13 K15 K6 K7 L14 L15 L5 L6 M15 M5 N6 N9 P11 P12 P13 P14 P15 P6 P7 P9 V7 U7 B16 D14 C14 MSC8103 Network Digital Signal Processor, Rev. 12 3-10 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name HA2 HA3 HACK/HACK HCS1/HCS1 HCS2/HCS2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HDDS HDS/HDS HDSP HPE HRD/HRD HREQ/HREQ HRESET HRRQ/HRRQ HRW HTRQ/HTRQ HWR/HWR INT_OUT IRQ1 Number B14 A14 E16 D15 A16 A10 G11 D11 C11 B11 A11 F12 D12 C12 B12 A12 D13 C13 B13 A13 E14 C16 B15 D16 D1 C15 A15 V6 E16 C15 A15 B15 W11 B1 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-11 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 L1RSYNC for SI2 TDMB2 L1RSYNC for SI2 TDMC2 L1RSYNC for SI2 TDMD2 L1RXD for SI1 TDMA1 Serial L1RXD for SI2 TDMB2 L1RXD for SI2 TDMC2 L1RXD for SI2 TDMD2 L1RXD0 for SI1 TDMA1 Nibble L1RXD1 for SI1 TDMA1 Nibble L1RXD2 for SI1 TDMA1 Nibble L1RXD3 for SI1 TDMA1 Nibble L1TSYNC for SI1 TDMA1 L1TSYNC for SI2 TDMB2 L1TSYNC for SI2 TDMC2 L1TSYNC for SI2 TDMD2 L1TXD for SI1 TDMA1 Serial L1TXD for SI2 TDMB2 L1TXD for SI2 TDMC2 L1TXD for SI2 TDMD2 L1TXD0 for SI1 TDMA1 Nibble Number D18 C19 D4 V11 B2 C18 H14 C3 A2 H13 D5 F6 W11 T11 K4 P3 P5 U10 H1 M3 T2 U10 T2 V1 P3 V10 L2 N3 T1 W9 H4 M1 V1 W9 MSC8103 Network Digital Signal Processor, Rev. 12 3-12 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name L1TXD1 for SI1 TDMA1 Nibble L1TXD2 for SI1 TDMA1 Nibble L1TXD3 for SI1 TDMA1 Nibble LIST1 for SI1 LIST1 for SI2 LIST2 for SI1 LIST2 for SI2 LIST3 for SI1 LIST3 for SI2 LIST4 for SI1 LIST4 for SI2 MODCK1 MODCK2 MODCK3 MSNUM0 MSNUM1 MSNUM2 MSNUM3 MSNUM4 MSNUM5 NMI NMI_OUT PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 Number P5 T1 N3 R1 T10 T6 N10 V4 W10 T5 P10 E18 F18 G18 N2 P2 U8 T9 V8 U9 U5 V5 T11 V10 U10 W9 U9 V8 T9 U8 W8 W3 M7 T4 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-13 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 Number W2 R5 T3 U1 R3 P4 P2 N2 M6 L1 K1 J1 J7 G1 R4 U2 P5 T1 T2 V1 P3 N3 M3 M1 L2 K4 H1 H4 K18 K17 K14 J19 H19 D17 MSC8103 Network Digital Signal Processor, Rev. 12 3-14 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD7 PD16 PD17 PD18 PD19 PD29 PD30 PD31 PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 Number B17 F17 P10 W10 N10 T10 V4 T5 T6 V3 R1 N5 P1 N1 M2 L7 L3 K3 J3 H3 V9 U4 N7 U3 V2 K2 J2 H2 E17 F14 G19 E19 J18 J17 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-15 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PUPMWAIT PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Number J18 G19 W5 J18 E17 J17 E19 K18 K17 K14 J19 H19 D17 B17 F17 G19 G13 F14 J18 K18 K17 K14 J19 H19 D17 B17 F17 A17 A18 C2 C17 C19 H14 H13 MSC8103 Network Digital Signal Processor, Rev. 12 3-16 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 RX_DV for FCC2 RX_ER for FCC1 RX_ER for FCC2 RXADDR0 for FCC1 UTOPIA 8 RXADDR1 for FCC1 UTOPIA 8 RXADDR2 for FCC1 UTOPIA 8 Number U6 J7 L2 K2 L2 L1 H1 M6 L2 T6 V4 N10 N10 K2 U3 M6 M6 K2 V4 T4 T1 H2 H4 T4 U9 T1 M7 V8 P5 W3 T9 U2 W8 U8 RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 RXADDR3 for FCC1 UTOPIA 8 RXADDR4 for FCC1 UTOPIA 8 RXCLAV for FCC1 UTOPIA 8 RXCLAV0 for FCC1 UTOPIA 8 RXCLAV2 for FCC1 UTOPIA 8 RXCLAV3 for FCC1 UTOPIA 8 RXD for FCC1 transparent/HDLC serial RXD for FCC2 transparent/HDLC serial RXD for SCC1 RXD for SCC2 RXD0 for FCC1 MII/HDLC nibble RXD0 for FCC1 UTOPIA 8 RXD0 for FCC2 MII/HDLC nibble RXD1 for FCC1 MII/HDLC nibble RXD1 for FCC1 UTOPIA 8 RXD1 for FCC2 MII/HDLC nibble RXD2 for FCC1 MII/HDLC nibble RXD2 for FCC1 UTOPIA 8 RXD2 for FCC2 MII/HDLC nibble RXD3 for FCC1 MII/HDLC nibble RXD3 for FCC1 UTOPIA 8 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-17 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name RXD3 for FCC2 MII/HDLC nibble RXD4 for FCC1 UTOPIA 8 RXD5 for FCC1 UTOPIA 8 RXD6 for FCC1 UTOPIA 8 RXD7 for FCC1 UTOPIA 8 RXENB for FCC1 RXPRTY for FCC1 UTOPIA 8 RXSOC for FCC1 SCL SDA SMRXD for SMC1 SMRXD for SMC2 SMSYN for SMC1 SMSYN for SMC2 SMTXD for SMC1 SMTXD for SMC2 SMTXD for SMC2 SPARE1 SPARE5 SPICLK SPIMISO SPIMOSI SPISEL SRESET TA TBST TC0 TC1 TC2 TCK TDI TDO TEA TEST Number R4 W8 W3 M7 T4 K1 N7 L1 R4 U2 P10 U10 V9 V10 W10 W9 V3 R2 U11 U3 U4 N7 V2 W4 J13 U13 E18 F18 G18 G4 H6 F1 G17 W6 MSC8103 Network Digital Signal Processor, Rev. 12 3-18 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TMS TOUT1 TOUT3 TRST TS TSIZ0 TSIZ1 TSIZ2 TSIZ3 TT0 TT1 TT2 TT3 TT4 TX_EN for FCC1 MII TX_EN for FCC2 MII TX_ER for FCC1 MII TX_ER for FCC2 MII TXADDR0 for FCC1 UTOPIA 8 TXADDR1 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR2 for FCC1 UTOPIA 8 TXADDR3 for FCC1 UTOPIA 8 TXADDR4 for FCC1 UTOPIA 8 TXCLAV for FCC1 UTOPIA 8 Number H3 L7 C1 D3 L3 K3 P1 N1 M2 G2 J3 M2 G3 T13 V13 W13 W12 N11 N13 N12 U14 V14 W14 K1 K4 J1 H4 V3 T5 T10 T10 V9 V2 J7 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-19 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name TXCLAV0 for FCC1 UTOPIA 8 TXCLAV1 for FCC1 UTOPIA 8 TXCLAV2 for FCC1 UTOPIA 8 TXCLAV3 for FCC1 UTOPIA 8 Number J7 T10 V9 V2 W2 T2 J2 H1 W2 N2 T2 R5 P2 V1 T3 P4 P3 U1 R3 N3 U1 T3 R5 W2 G1 U4 J1 W7 T7 E12 E5 E9 F16 F4 TXD for FCC1 transparent/HDLC serial TXD for FCC2 transparent/HDLC serial TXD for SCC1 TXD for SCC2 TXD0 for FCC1 MII/HDLC nibble TXD0 for FCC1 UTOPIA 8 TXD0 for FCC2 MII/HDLC nibble TXD1 for FCC1 MII/HDLC nibble TXD1 for FCC1 UTOPIA 8 TXD1 for FCC2 MII/HDLC nibble TXD2 for FCC1 MII/HDLC nibble TXD2 for FCC1 UTOPIA 8 TXD2 for FCC2 MII/HDLC nibble TXD3 for FCC1 MII/HDLC nibble TXD3 for FCC1 UTOPIA 8 TXD3 for FCC2 MII/HDLC nibble TXD4 for FCC1 UTOPIA 8 TXD5 for FCC1 UTOPIA 8 TXD6 for FCC1 UTOPIA 8 TXD7 for FCC1 UTOPIA 8 TXENB for FCC1 TXPRTY for FCC1 UTOPIA 8 TXSOC for FCC1 VCCSYN VCCSYN1 VDD VDD VDD VDD VDD MSC8103 Network Digital Signal Processor, Rev. 12 3-20 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH Number H16 J4 L16 L4 N4 P16 R11 R13 R8 E10 E11 E13 E15 E4 E6 E8 G15 G16 G5 J15 J16 K16 K5 M4 N15 N16 R10 R12 R14 R15 R6 R7 R9 T15 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-21 Packaging Table 3-2. Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 MSC8103 Signal Listing by Pin Designator Signal Name IRQ5 / DP5 / DREQ4 / EXT_DBG3 D1 D4 D7 D11 D17 D22 D27 D32 / HD0 D37 / HD5 D42 / HD10 D46 / HD14 D51 / HA3 D55 / HREQ / HTRQ D60 / HCS2 D62 / Reserved D63 / Reserved IRQ1 / DP1 / EXT_BG2 IRQ3 / DP3 / EXT_BR3 D0 D3 D6 D10 D16 D21 D26 D31 D36 / HD4 D41 / HD9 D45 / HD13 D50 / HA2 D54 / HDS / HWR D59 / H8BIT PWE6 / PSDDQM6 / PBS6 DBG BADDR28 THERM1 Reserved / DP0 / EXT_BR2 IRQ4 / DP4 / DREQ3 / EXT_BG3 MSC8103 Network Digital Signal Processor, Rev. 12 3-22 Freescale Semiconductor FC-PBGA Package Description Table 3-2. Number C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name D2 D5 D9 D15 D20 D25 D30 D35 / HD3 D40 / HD8 D44 / HD12 D49 / HA1 D53 / HRW / HRD D58 / HDDS D61 DBB / IRQ3 BADDR29 / IRQ2 HPE / EE1 DBREQ / EE0 THERM2 IRQ2 / DP2 / EXT_DBG2 IRQ6 / DP6 / DACK3 D8 D14 D19 D24 D29 D34 / HD2 D39 / HD7 D43 / HD11 D48 / HA0 D52 / HCS1 D57 / HDSP PWE5 / PSDDQM5 / PBS5 IRQ1 / GBL BADDR27 BTM0 / EE4 EE3 EE2 VDDH MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-23 Packaging Table 3-2. Number E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name VDD VDDH D13 VDDH VDD VDDH VDDH VDD VDDH D47 / HD15 VDDH D56 / HACK / HRRQ PSDA10 / PGPL0 MODCK1 / TC0 / BNKSEL0 PSDCAS / PGPL3 TDO EED BTM1 / EE5 VDD GND IRQ7 / DP7 / DACK4 GND D18 GND D28 GND D38 / HD6 GND PSDWE / PGPL1 GND VDD PWE7 / PSDDQM7 / PBS7 MODCK2 / TC1 / BNKSEL1 BCTL0 PA31 / FCC1:UTOPIA8:TXENB / FCC1:MII:COL TMS TRST TCK VDDH MSC8103 Network Digital Signal Processor, Rev. 12 3-24 Freescale Semiconductor FC-PBGA Package Description Table 3-2. Number G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H6 H7 H13 H14 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J6 J7 J13 J14 J15 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name GND D12 GND D23 GND D33 / HD1 GND PSDVAL GND VDDH VDDH TEA MODCK3 / TC2 / BNKSEL2 POE / PSDRAS / PGPL2 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD PD31 / SCC1:RXD / DRACK1 / DONE1 PC31 / BRG1O / CLK1 / TGATE1 PB31 / FCC2:MII:TX_ER / SCC2:RXD / TDMB2:L1TXD GND TDI GND Reserved / BADDR31 / IRQ5 Reserved / BADDR30 / IRQ3 GND VDD BR ALE PWE4 / PSDDQM4 / PBS4 PA29 / FCC1:UTOPIA8:TXSOC / FCC1:MII:TX_ER PD30 / SCC1:TXD / DMA:DRACK2/DONE2 PC30 / EXT1 / BRG2O / CLK2 / TOUT1 VDD GND GND PA30 / FCC1:UTOPIA8:TXCLAV / FCC1:UTOPIA8:TXCLAV0 / FCC1:MII:CRS / FCC1:HDLC and transparent:RTS TA GND VDDH MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-25 Packaging Table 3-2. Number J16 J17 J18 J19 K1 K2 K3 K4 K5 K6 K7 K13 K14 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L6 L7 L13 L14 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M6 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name VDDH PSDAMUX / PGPL5 PGTA / PUPMWAIT / PPBS / PGPL4 PWE3 / PSDDQM3 / PBS3 PA28 / FCC1:UTOPIA8:RXENB / FCC1:MII:TX_EN PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 / SCC1:RTS/TENA PC29 / SCC1:CTS / SCC1:CLSN / BRG3O / CLK3 / TIN2 PB29 / FCC2:MII:TX_EN / TDMB2:L1RSYNC VDDH GND GND GND PWE2 / PSDDQM2 / PBS2 GND VDDH PWE1 / PSDDQM1 / PBS1 PWE0 / PSDDQM0 / PBS0 CS2 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC PC28 / SCC2:CTS/CLSN / BRG4O / CLK4 / TIN1/TOUT2 VDD GND GND PC27 / CLK5 / BRG5O / TGATE2 CS6 GND GND VDD CS1 CS3 BCTL1 PB27 / FCC2:MII:COL / TDMC2:L1TXD PC26 / TMCLK / BRG6O / CLK6 / TOUT3 PB26 / FCC2:MII:CRS / TDMC2:L1RXD VDDH GND PA26 / FCC1:UTOPIA8:RXCLAV / FCC1:UTOPIA8:RXCLAV0 / FCC1:MII:RX_ER MSC8103 Network Digital Signal Processor, Rev. 12 3-26 Freescale Semiconductor FC-PBGA Package Description Table 3-2. Number M7 M13 M14 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P6 P7 P8 P9 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1 A21 A26 GND CS0 CS5 CS7 CS4 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 PB25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 / TDMC2:L1TSYNC VDD PC23 / EXT2 / DMA:DACK1 / CLK9 GND PD17 / FCC1:UTOPIA8:RXPRTY / SPI:SPIMOSI / BRG2O CLKIN GND PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 / FCC1:CD / SI2:LIST2 TSIZ3 TT1 TT0 A1 VDDH VDDH A28 A30 A31 PC24 / DMA:DREQ2 / BRG8O / CLK8 / TIN3/TOUT4 PA24 / FCC1:UTOPIA8:TXD1 / SDMA:MSNUM1 PB24 / FCC2:MII and HDLC nibble:TXD2 / TDMA1:nibble:L1RXD3 / TDMC2:L1RSYNC PA23 / FCC1:UTOPIA8:TXD2 PB20 / FCC2:MII and HDLC nibble:RXD1 / TDMA1:nibble:L1TXD1 / TDMD2:L1RSYNC GND GND DLLIN GND MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-27 Packaging Table 3-2. Number P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name PC4 / FCC2:CD / SMC1:SMRXD / SI2:LIST4 GND GND GND GND GND VDD A23 A27 A29 PC22 / SI1:LIST1 / DREQ1 / CLK10 SPARE1 PA22 / FCC1:UTOPIA8:TXD3 PB18 / FCC2:MII and HDLC nibble:RXD3 / I2C:SCL PA19 / FCC1:UTOPIA8:TXD6 / FCC1:MII and HDLC nibble:TXD1 VDDH VDDH VDD VDDH VDDH VDD VDDH VDD VDDH VDDH A15 A19 A24 A25 PB21 / FCC2:MII and HDLC nibble:RXD0 / FCC2:transparent and HDLC serial:RXD /TDMA1:nibble:L1TXD2 / TDMD2:L1TSYNC PB22 / FCC2:MII and HDLC nibble TXD0 / FCC2:transparent and HDLC serial TXD /TDMA1:nibble L1RXD1 / TDMD2:L1RXD PA20 / FCC1:UTOPIA8 TXD5 / FCC1:MII and HDLC nibble TXD2 PA17 / FCC1:UTOPIA8 RXD7 / FCC1:MII and HDLC nibble RXD0 / FCC1:transparent and HDLC serial RXD PC13 / FCC1:UTOPIA8:TXADDR1 / SCC2:CTS/CLSN / SI1:LIST4 PC14 / FCC1:UTOPIA8:RXADDR0 / SCC1:CD/RENA / SI1:LIST2 VCCSYN1 T2 T3 T4 T5 T6 T7 MSC8103 Network Digital Signal Processor, Rev. 12 3-28 Freescale Semiconductor FC-PBGA Package Description Table 3-2. Number T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name CLKOUT PA12 / FCC1:UTOPIA8:RXD2 / SDMA:MSNUM3 PC7 / FCC1:UTOPIA8:TXADDR2 / FCC1:UTOPIA8:TXADDR2/TXCLAV1 / FCC1:CTS / SI1:LIST1 PA6 / TDMA1:L1RSYNC AACK TS A3 VDDH A12 A16 A20 A22 PA21 / FCC1:TXD4 / FCC1:MII and HDLC nibble TXD3 PB19 / FCC2:MII and HDLC nibble RXD2 / I2C:SDA PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK PD16 / FCC1:UTOPIA8:TXPRTY / SPI:SPIMISO NMI RSTCONF GNDSYN1 PA13 / FCC1:UTOPIA8:RXD3 / SDMA:MSNUM2 PA10 / FCC1:UTOPIA8:RXD0 / SDMA:MSNUM5 PA8 / SMC2:SMRXD / TDMA1:serial L1RXD / TDMA1:nibble L1RXD0 SPARE5 ARTRY TBST TT2 A4 A8 A11 A17 A18 PB23 / FCC2:MII and HDLC nibble:TXD1 / TDMA1:nibble:L1RXD2 / TDMD2:L1TXD PD19 / FCC1:UTOPIA8:TXADDR4 / FCC1:UTOPIA:TXCLAV3 / SPI:SPISEL / BRG1O PC15 / FCC1:UTOPIA8:TXADDR0 / SCC1:CTS/CLSN / SMC2:SMTXD PC12 / FCC1:UTOPIA8:RXADDR1 / SCC2:CD/RENA / SI1:LIST3 NMI_OUT HRESET MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-29 Packaging Table 3-2. Number V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 MSC8103 Signal Listing by Pin Designator (Continued) Signal Name GNDSYN PA11 / FCC1:UTOPIA8:RXD1 / SDMA:MSNUM4 PD7 / FCC1:UTOPIA8:TXADDR3 / FCC1:UTOPIA8:TXCLAV2 / SMC1:SMSYN PA7 / SMC2:SMSYN / TDMA1:L1TSYNC ABB / IRQ2 BG TSIZ0 TT3 A2 A6 A9 A13 A14 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / FCC1:transparent and HDLC serial:TXD PA15 / FCC1:UTOPIA8:RXD5 / FCC1:MII and HDLC nibble:RXD2 SRESET PORESET TEST VCCSYN PA14 / FCC1:UTOPIA8 RXD4 / FCC1:MII and HDLC nibble:RXD3 PA9 / SMC2:SMTXD / TDMA1:serial:L1TXD /TDMA1:nibble:L1TXD0 PC5 / FCC2:CTS / SMC1:SMTXD / SI2:LIST3 IRQ7 / INT_OUT TSIZ2 TSIZ1 TT4 A0 A5 A7 A10 MSC8103 Network Digital Signal Processor, Rev. 12 3-30 Freescale Semiconductor Lidded FC-PBGA Package Mechanical Drawing 3.2 Lidded FC-PBGA Package Mechanical Drawing . Notes: 1. Dimensioning and tolerancing per ASME Y14.5M–1994. 2. Dimensions in millimeters. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Primary Datum A and the seating plane are defined by the spherical crowns of the solder balls. CASE 1473-01 Figure 3-3. Case 1473-01 Mechanical Information, 332-pin Lidded FC-PBGA Package MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-31 Packaging MSC8103 Network Digital Signal Processor, Rev. 12 3-32 Freescale Semiconductor Design Considerations This chapter includes design and layout guidelines for manufacturing boards using the MSC8103. 4 4.1 Thermal Design Considerations The average chip-junction temperature, TJ, in °C can be obtained from the following: T J = T A + (PD • θJA) Equation 1 where TA = ambient temperature °C θJA = package thermal resistance, junction to ambient, °C/W PD = PINT + PI/O in W PINT = IDD × VDD in W—chip internal power PI/O = power dissipation on output pins in W—user determined The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too high, the user should either lower the ambient temperature or the power dissipation of the chip. 4.2 Electrical Design Considerations The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use “bootstrap” diodes between the power rails, as shown in Figure 4-1. I/O Power MUR420 MUR420 MUR420 3.3 V (VDDH) Core/PLL Supply MUR420 1.6 V (VDD/VCCSYN) Figure 4-1. Bootstrap Diodes for Power-Up Sequencing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-1 Design Considerations Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The VF should be effective at the current levels required by the processor. Do not use diodes with a nominal VF that drops too low at high current. 4.3 Power Considerations The internal power dissipation consists of three components: PINT = PCORE + PSIU + PCPM Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides typical power values at the specified operating frequencies. To determine the typical power dissipation for a given set of frequencies, use the following equations: PCORE (f) = ((PCORE – PLCO)/fCORE) × fCOREA + PLCO PCPM (f) = ((PCPM – PLCP)/fCPM) × fCPMA + PLCP PSIU (f) = ((PSIU – PLSI)/fSIU) × fSIUA + PLSI Where: • fCORE is the core frequency, fSIU is the SIU frequency, and fCPM is the CPM frequency specified in Table 2-5 in MHz • fCOREA is the actual core frequency, FSIUA is the actual SIU frequency, and FCPMA is the actual CPM frequency in MHz • PLCO, PLSI, and PLCP are the leakage power values specified in Table 2-5 • All power numbers are in mW • Power consumption is assumed to be linear with frequency. The first part of each equation computes a mw/MHz value that is then scaled based on the actual frequency used. To determine a total power dissipation in a specific application, you must add the power values derived from the above set of equations to the value derived for I/O power consumption using the following equation for each output pin: P = C × VDDH2 × f × 10–3 Equation 2 Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz. For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every second cycle with 10% of address pins switching. • External data memory writes occurs once every eight cycles with 50% of data pins switching. • Each address and data pin has a 30 pF total load at the pin. • The application operates at VDDH = 3.3 V. MSC8103 Network Digital Signal Processor, Rev. 12 4-2 Freescale Semiconductor Layout Practices Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus frequency (that is, 25 MHz). For the same reason the data pins frequency is 3.125 MHz. Table 4-1. Pins Address Data, HRD, HRW CLKOUT Total PI/O Power Dissipation × VDDH2 × 3.32 × 3.32 × 3.32 Number of Pins Switching 4 34 1 ×C × 30 × 30 × 30 × f × 10–3 × 12.5 × 10–3 × 3. 125 × 10–3 × 50 × 10–3 Power in mW 16.25 34.75 16 67 Calculating internal power (from Table 2-5 values): PCORE (200) = ((PCORE – PLCO)/300) × 200 + PLCO =((450 – 3) / 300 × 200 + 3 = 301 PCPM (100) = ((PCPM – PLCP) / 200) × 100 + PLCP = ((320 – 6) / 200) × 100 + 6 = 163 PSIU (50) = ((PSIU – PLSI) / 100) × 50 + PLSI = ((80 – 2) / 100) × 50 + 2 = 41 PINT = PCORE(200) + PCPM(100) + PSIU(50) = 301 + 163 + 41 = 505 PD = PINT + PI/O = 505 + 67 = 572 Maximum allowed ambient temperature is: TA = TJ – (PD × θJA) 4.4 Layout Practices Each VCC and VDD pin on the MSC8103 should be provided with a low-impedance path to the board’s power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There are 2 pairs of PLL supply pins: VCCSYN-GNDSYN and VCCSYN1-GNDSYN1. Each pair supplies one PLL. To ensure internal clock stability, filter the power to the VCCSYN and VCCSYN1 inputs with a circuit similar to the one in Figure 4-2. To filter as much noise as possible, place the circuit as close as possible to VCCSYN and VCCSYN1. The 0.01-µF capacitor should be closest to VCCSYN and VCCSYN1, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be kept short and direct. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-3 Design Considerations GNDSYN and GNDSYN1 should be provided with an extremely low impedance path to ground and should be bypassed to VCCSYN and VCCSYN1, respectively, by a 0.01-µF capacitor located as close as possible to the chip package. The user should also bypass GNDSYN and GNDSYN1 to VCCSYN and VCCSYN1 with a 0.01-µF capacitor as closely as possible to the chip package VDD 10 Ω 10nH 10 µF VCCSYN 0.01 µF Figure 4-2. VCCSYN and VCCSYN1 Bypass MSC8103 Network Digital Signal Processor, Rev. 12 4-4 Freescale Semiconductor Ordering Information For product availability, consult a Freescale Semiconductor sales office or authorized distributor. Supply Voltage 1.6 V core 3.3 V I/O Pin Count 332 Mask Set 2K87M Core Frequency (MHz) 275 275 300 300 Part MSC8103 Package Type Lidded Flip Chip Plastic Ball Grid Array (FC-PBGA) Sphere Type Pb-bearing Pb-free Pb-bearing Pb-free Order Number MSC8103M1100F MSC8103VT1100F MSC8103M1200F MSC8103VT1200F How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com MSC8103 Rev. 12 8/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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