MSC8122

Freescale Semiconductor Technical Data MSC8122 Rev. 13, 10/2006 MSC8122 Quad Core 16-Bit Digital Signal Processor The raw processing power of this highly integrated systemon- a-chip device will enable developers to create nextgeneration networking products that offer tremendous channel densities, while maintaining system flexibility, scalability, and upgradeability. The MSC8122 is offered in three core speed levels: 300, 400, and 500 MHz. What’s New? Rev. 13 includes the following: MII/RMII/SMII • Chapter 2 updates Table 2-13 to add timings 17 and 18 for IRQs. SC140 Extended Core MQBus SC140 Extended Core 128 SQBus SC140 Extended Core SC140 Extended Core 128 64 IP Master 32 Timers Local Bus Boot ROM M2 RAM Memory Controller UART 4 TDMs RS-232 PLL/Clock PLL IPBus 32 GPIO GIC 8 Hardware Semaphores Ethernet GPIO Pins Interrupts JTAG Port JTAG 64 System Interface Internal Local Bus SIU Registers 64 DMA Bridge Direct Slave Interface (DSI) Memory Controller DSI Port 32/64 System Bus 32/64 Internal System Bus Figure 1. MSC8122 Block Diagram The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz. Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers enhanced performance while maintaining low power dissipation and greatly reducing system cost. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. Table of Contents Table of Contents Features...............................................................................................................................................................iv Product Documentation ......................................................................................................................................ix Chapter 1 Signals/Connections 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Power Signals ...................................................................................................................................................1-3 Clock Signals ....................................................................................................................................................1-3 Reset and Configuration Signals.......................................................................................................................1-3 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4 Memory Controller Signals ............................................................................................................................1-14 GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16 Dedicated Ethernet Signals.............................................................................................................................1-23 EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24 Reserved Signals.............................................................................................................................................1-24 Maximum Ratings.............................................................................................................................................2-1 Recommended Operating Conditions...............................................................................................................2-2 Thermal Characteristics ....................................................................................................................................2-3 DC Electrical Characteristics............................................................................................................................2-3 AC Timings.......................................................................................................................................................2-4 Package Description .........................................................................................................................................3-1 MSC8122 Package Mechanical Drawing .......................................................................................................3-20 Chapter 2 Specifications 2.1 2.2 2.3 2.4 2.5 Chapter 3 Packaging 3.1 3.2 Chapter 4 Design Considerations 4.1 4.2 4.3 4.4 4.5 Start-up Sequencing Recommendations ...........................................................................................................4-1 Power Supply Design Considerations...............................................................................................................4-1 Connectivity Guidelines ...................................................................................................................................4-3 External SDRAM Selection..............................................................................................................................4-4 Thermal Considerations....................................................................................................................................4-5 Data Sheet Conventions OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MSC8122 Technical Data, Rev. 13 ii Freescale Semiconductor Data Sheet Conventions Program Sequencer SC140 Core JTAG Power Management Address Register File Address ALU EOnCE Data ALU Register File Data ALU SC140 Core Xa Xb P 64 64 128 M1 RAM Instruction Cache QBus 128 PIC IRQs LIC QBus Bank 1 QBus Bank 3 QBC QBus Interface IRQs MQBus SQBus Local Bus 128 128 64 Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. SC140 Extended Core Block Diagram MSC8122 Technical Data, Rev. 13 Freescale Semiconductor iii Features Features Feature Description Four SC140 cores: • Up to 8000 MMACS using 16 ALUs running at up to 500 MHz. • A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2 memory). Each SC140 core provides the following: • Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate command with the associated data move and pointer update. • 4 ALUs per SC140 core. • 16 data registers, 40 bits each. • 27 address registers, 32 bits each. • Hardware support for fractional and integer data types. • Very rich 16-bit wide orthogonal instruction set. • Up to six instructions executed in a single clock cycle. • Variable-length execution set (VLES) that can be optimized for code density and performance. • IEEE Std 1149.1™ JTAG port. • Enhanced on-device emulation (EOnCE) with real-time debugging capabilities. Each SC140 core is embedded within an extended core that provides the following: • 224 KB M1 memory that is accessed by the SC140 core with zero wait states. • Support for atomic accesses to the M1 memory. • 16 KB instruction cache, 16 ways. • A four-entry write buffer that frees the SC140 core from waiting for a write access to finish. • External cache support by asserting the global signal (GBL) when predefined memory banks are accessed. • Programmable interrupt controller (PIC). • Local interrupt controller (LIC). • 476 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and accessible from all four SC140 cores using the MQBus. • 4 KB bootstrap ROM. • • • • • A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory. Data bus access of up to 128-bit read and up to 64-bit write. Operation at the SC140 core frequency. A central efficient round-robin arbiter controlling SC140 core access on the MQBus. Atomic operation control of access to M2 memory by the four SC140 cores and the local bus. SC140 Cores Extended Core Multi-Core Shared Memories M2-Accessible MultiCore Bus (MQBus) Internal PLL • Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system buses and other modules. • PLL values are determined at reset based on configuration signal values. • • • • • 64/32-bit data and 32-bit address 60x bus. Support for multiple-master designs. Four-beat burst transfers (eight-beat in 32-bit wide mode). Port size of 64, 32, 16, and 8 controlled by the internal memory controller. Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to access internal resources. • Slave support, direct access by an external host to internal resources including the M1 and M2 memories. • On-device arbitration between up to four master devices. A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host processor. • 21–25 bit address, 32/64-bit data. • Direct access by an external host to internal and external resources, including the M1 and the M2 memories as well as external devices on the system bus. • Synchronous and asynchronous accesses, with burst capability in the synchronous mode. • Dual or Single strobe modes. • Write and read buffers improve host bandwidth. • Byte enable signals enables 1, 2, 4, and 8 byte write access granularity. • Sliding window mode enables access with reduced number of address pins. • Chip ID decoding enables using one CS signal for multiple DSPs. • Broadcast CS signal enables parallel write to multiple DSPs. • Big-endian, little-endian, and munged little-endian support. • 64-bit DSI, 32-bit system bus. • 32-bit DSI, 64-bit system bus. • 32-bit DSI, 32-bit system bus. 60x-Compatible System Bus Direct Slave Interface (DSI) 3-Mode Signal Multiplexing MSC8122 Technical Data, Rev. 13 iv Freescale Semiconductor Features Feature Description Flexible eight-bank memory controller: • Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode SDRAM machine. • Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable peripherals. • Byte enables for either 64-bit or 32-bit bus width mode. • Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus peripherals and internal memories. Each bank has the following features: — 32-bit address decoding with programmable mask. — Variable block sizes (32 KB to 4 GB). — Selectable memory controller machine. — Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even parity for single accesses. — Write-protection capability. — Control signal generation machine selection on a per-bank basis. — Support for internal or external masters on the system bus. — Data buffer controls activated on a per-bank basis. — Atomic operation. — RMW data parity check (on system bus only). — Extensive external memory-controller/bus-slave support. — Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus only). — Data pipeline to reduce data set-up time for synchronous devices. • • • • Multi-Channel DMA Controller 16 time-multiplexed unidirectional channels. Services up to four external peripherals. Supports DONE or DRACK protocol on two external peripherals. Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates: — A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination. — A hungry request to indicate that the FIFO can accept more data. Priority-based time-multiplexing between channels using 16 internal priority levels. Round-robin time-multiplexing between channels. A flexible channel configuration: — All channels support all features. — All channels connect to the system bus or local bus. Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO. Memory Controller • • • • Time-Division Multiplexing (TDM) Up to four independent TDM modules, each with the following features: • Optional operating configurations: — Totally independent receive and transmit channels, each having one data line, one clock line, and one frame sync line. — Four data lines with one clock and one frame sync shared among the transmit and receive lines. • Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS. • Hardware A-law/μ -law conversion. • Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used, 15.63 MHz if four data lines are used). • Up to 256 channels. • Up to 16 MB per channel buffer (granularity 8 bytes), where A/μ law buffer size is double (granularity 16 byte). • Receive buffers share one global write offset pointer that is written to the same offset relative to their start address. • Transmit buffers share one global read offset pointer that is read from the same offset relative to their start address. • All channels share the same word size. • Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering. • Each channel can be programmed to be active or inactive. • 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively. • The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output. • Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock. • Frame sync can be programmed as active low or active high. • Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame. • MSB or LSB first support. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor v Features Feature Description • Designed to comply with IEEE® Std 802® including Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™. • Three Ethernet physical interfaces: — 10/100 Mbps MII. — 10/100 Mbps RMII. — 10/100 Mbps SMII. • Full and half-duplex support. • Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation and recognition). • Out-of-sequence transmit queue for initiating flow-control. • Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN) tags and priority. • Retransmission from transmit FIFO following a collision. • CRC generation and verification of inbound/outbound packets. • Address recognition: — Each exact match can be programmed to be accepted or rejected. — Broadcast address (accept/reject). — Exact match 48-bit individual (unicast) address. — Hash (256-bit hash) check of individual (unicast) addresses. — Hash (256-bit hash) check of group (multicast) addresses. — Promiscuous mode. • Pattern matching: — Up to 16 unique 4-byte patterns. — Pattern match on bit-basis. — Matching range up to 256 bytes deep into the frame. — Offsets to a maximum of 252 bytes. — Programmable pattern size in 4-byte increments up to 64 bytes. — Accept or reject frames if a match is detected. — Up to eight unicast addresses for exact matches. — Pattern matching accepts/rejects IP addresses. • Filing of receive frames based on pattern match; prioritization of frames. • Insertion with expansion or replacement for transmit frames; VLAN tag insertion. • RMON statistics. • Master DMA on the local bus for fetching descriptors and accessing the buffers. • Ethernet PHY can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when the DSI and the system bus are both 32 bits. • MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode. • MII Bridge (MIIGSK): — Programmable selection of the 50 MHz RMII reference clock source (external or internal). — Independent 2 bit wide transmit and receive data paths. — Six operating modes. — Four general-purpose control signals. — Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain. • SMII features: — Multiplexed only with GPIO signals — Convey complete MII information between the PHY and MAC. — Allow direct MAC-to-MAC communication in SMII mode. — Can generate an interrupt request line while receiving inter-frame segments. Ethernet Controller MSC8122 Technical Data, Rev. 13 vi Freescale Semiconductor Features Feature • • • • • • • • • • Description Two signals for transmit data and receive data. No clock, asynchronous mode. Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI. Full-duplex operation. Standard mark/space non-return-to-zero (NRZ) format. 13-bit baud rate selection. Programmable 8-bit or 9-bit data format. Separately enabled transmitter and receiver. Programmable transmitter output polarity. Two receiver wake-up methods: — Idle line wake-up. — Address mark wake-up. Separate receiver and transmitter interrupt requests. Nine flags, the first five can generate interrupt request: — Transmitter empty. — Transmission complete. — Receiver full. — Idle receiver input. — Receiver overrun. — Receiver active. — Noise error. — Framing error. — Parity error. Receiver framing error detection. Hardware parity checking. 1/16 bit-time noise detection. Maximum bit rate 6.25 Mbps. Single-wire and loop operations. UART • • • • • • • General-Purpose I/O (GPIO) Port I2C Software Module • 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports. • Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode. • Booting from a serial EEPROM. • Uses GPIO timing. Two modules of 16 timers each. • Cyclic or one-shot. • Input clock polarity control. • Interrupt request when counting reaches a programmed threshold. • Pulse or level interrupts. • Dynamically updated programmed threshold. • Read counter any time. Watchdog mode for the timers that connect to the device. Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism. • Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT, NMI_OUT, and to the cores. • Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access. • Generation of virtual NMI (one to each SC140 core) by a simple write access. • • • • Low power CMOS design. Separate power supply for internal logic (1.2 V or 1.1 V) and I/O (3.3 V). Low-power standby modes. Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent). Timers Hardware Semaphores Global Interrupt Controller (GIC) Reduced Power Dissipation Packaging • 0.8 mm pitch flip-chip plastic ball-grid array (FC-PBGA) with lead-free or lead-bearing spheres. • 431-connection (ball). • 20 mm × 20 mm. The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache, timers, DMA controller, interrupts, peripherals), as follows: • High-performance and deterministic, delivering predictive response time. • Optimized to provide low interrupt latency with high data throughput. • Preemptive and priority-based multitasking. • Fully interrupt/event driven. • Small memory footprint. • Comprehensive set of APIs. Real-Time Operating System (RTOS) MSC8122 Technical Data, Rev. 13 Freescale Semiconductor vii Features Feature Multi-Core Support Description • One instance of kernel code in all four SC140 cores. • Dynamic and static memory allocation from local memory (M1) and shared memory (M2). Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks running in on-board devices or remote network devices: • Messaging mechanism between tasks using mailboxes and semaphores. • Networking support; data transfer between tasks running inside and outside the device using networking protocols. • Includes integrated device drivers for such peripherals as TDM, UART, and external buses. • Task debugging utilities integrated with compilers and vendors. • Board support package (BSP) for the application development system (ADS). • Integrated development environment (IDE): — C/C++ compiler with in-line assembly so developers can generate highly optimized DSP code. Translates C/C++ code into parallel fetch sets and maintains high code density. — Librarian. User can create libraries for modularity. — A collection of C/C++ functions for developer use. — Highly efficient linker to produce executables from object code. — Seamlessly integrated real-time, non-intrusive multi-mode debugger for debugging highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode. — Device simulation models enable design and simulation before hardware availability. — Profiler using a patented binary code instrumentation (BCI) technique helps developers identify program design inefficiencies. — Version control. Metrowerks® CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and CVS. • • • • • External memory. External host. UART. TDM. I2C Distributed System Support Software Support Boot Options MSC8122ADS • Host debug through single JTAG connector supports both processors. • MSC8103 as the MSC8122 host with both devices on the board. The MSC8103 system bus connects to the MSC8122 DSI. • Flash memory for stand-alone applications. • Communications ports: — 10/100Base-T. — 155 Mbit ATM over Optical. — T1/E1 TDM interface. — H.110. — Voice codec. — RS-232. — High-density (MICTOR) logic analyzer connectors to monitor MSC8122 signals — 6U CompactPCI form factor. • Emulates MSC8122 DSP farm by connecting to three other ADS boards. MSC8122 Technical Data, Rev. 13 viii Freescale Semiconductor Product Documentation Product Documentation The documents listed in Table 1 are required for a complete description of the MSC8122 and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back of this document. Table 1. MSC8122 Documentation Name MSC8122 Technical Data MSC8122 User’s Guide MSC8122 Reference Manual StarCore™ SC140 DSP Core Reference Manual Application Notes Description MSC8122 features list and physical, electrical, timing, and package specifications User information includes system functionality, getting started, and programming topics Order Number MSC8122 Availability TBD Detailed functional description of the MSC8122 memory and peripheral configuration, MSC8122RM operation, and register programming Detailed description of the SC140 family processor core and instruction set Documents describing specific applications or optimized device operation including code examples MNSC140CORE Refer to the MSC8122 product page. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor ix MSC8122 Technical Data, Rev. 13 x Freescale Semiconductor Signals/Connections 1 The MSC8122 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1. Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8122 external signals organized by function. Table 1-1. Functional Group Power (VDD, VCC, and GND) Clock Reset and configuration DSI, system bus, Ethernet, and interrupts Memory controller General-purpose input/output (GPIO), time-division multiplexed (TDM) interface, universal asynchronous receiver/ transmitter (UART), Ethernet, and timers Dedicated Ethernet signals EOnCE and JTAG test access port Reserved (denotes connections that are always reserved) MSC8122 Functional Signal Groupings Number of Signal Connections 155 3 4 210 16 32 3 7 1 Description Table 1-2 on page 1-3 Table 1-3 on page 1-3 Table 1-4 on page 1-3 Table 1-5 on page 1-4 Table 1-6 on page 1-14 Table 1-7 on page 1-16 Table 1-8 on page 1-23 Table 1-9 on page 1-24 Table 1-10 on page 1-24 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-1 Signals/Connections HD0/SWTE HD1/DSISYNC HD2/DSI64 HD3/MODCK1 HD4/MODCK2 HD5/CNFGS HD[6–31] HD[32-39]/D[32-39]/reserved HD40/D40/ETHRXD0 HD41/D41/ETHRXD1 HD42/D42/ETHRXD2/reserved HD43/D43/ETHRXD3/reserved HD[44-45]/D[44-45]/reserved HD46/D46/ETHTXD0 HD47/D47/ETHTXD1 HD48/D48/ETHTXD2/reserved HD49/D49/ETHTXD3/reserved HD[50-53]/D[50-53]/reserved HD54/D54/ETHTX_EN HD55/D55/ETHTX_ER/reserved HD56/D56/ETHRX_DV/ETHCRS_DV HD57/D57/ETHRX_ER HD58/D58/ETHMDC HD59/D59/ETHMDIO HD60/D60/ETHCOL/reserved HD[61–63]/D[61-63]/reserved HCID[0–2] HCID3/HA8 HA[11–29] HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/ PWE[4–7]/PSDDQM[4–7]/PBS[4–7] HRDS/HRW/HRDE HBRST HDST[0–1]/HA[9–10] HCS HBCS HTA HCLKIN GPIO0/CHIP_ID0/IRQ4/ETHTXD0 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 GPIO2/TIMER1/CHIP_ID2/IRQ6 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 GPIO4/TDM3TCLK/IRQ2/ETHTX_ER GPIO5/TDM3TDAT/IRQ3/ETHRXD3 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 GPIO8/TDM3RDAT/IRQ6/ETHCOL GPIO9/TDM2TSYN/IRQ7/ETHMDIO GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC GPIO13/TDM2RCLK/IRQ11/ETHMDC GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC GPIO15/TDM1TSYN/DREQ1 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO17/TDM1TDAT/DACK1 GPIO18/TDM1RSYN/DREQ2 GPIO19/TDM1RCLK/DACK2 GPIO20/TDM1RDAT GPIO21/TDM0TSYN GPIO22/TDM0TCLK/DONE2/DRACK2 GPIO23/TDM0TDAT/IRQ13 GPIO24/TDM0RSYN/IRQ14 GPIO25/TDM0RCLK/IRQ15 GPIO26/TDM0RDAT GPIO27/URXD/DREQ1 GPIO28/UTXD/DREQ2 GPIO29/CHIP_ID3/ETHTX_EN GPIO30/TIMER2/TMCLK/SDA GPIO31/TIMER3/SCL ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ → → → → ↔ → → → → → ← → ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ 1 1 1 1 1 1 26 8 1 1 1 1 2 1 1 1 1 4 1 1 1 1 1 1 1 3 3 1 19 4 4 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 1 1 3 5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↔ ↔ ↔ ↔ → ↔ ↔ ↔ ↔ ↔ ↔ → → ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ← → ↔ ↔ → → ↔ → → → → → → ↔ → ← → → ← ← ← ↔ ↔ ← ← ← ← ← → A[0–31] TT0/HA7 TT1 TT[2–4]/CS[5–7] CS[0–4] TSZ[0–3] TBST IRQ1/GBL IRQ3/BADDR31 IRQ2/BADDR30 IRQ5/BADDR29 BADDR28 BADDR27 BR BG DBG ABB/IRQ4 DBB/IRQ5 TS AACK ARTRY D[0–31] reserved/DP0/DREQ1/EXT_BR2 IRQ1/DP1/DACK1/EXT_BG2 IRQ2/DP2/DACK2/EXT_DBG2 IRQ3/DP3/DREQ2/EXT_BR3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ5/DP5/DACK4/EXT_BG3 IRQ6/DP6/DREQ3 IRQ7/DP7/DREQ4 TA TEA NMI NMI_OUT PSDVAL IRQ7/INT_OUT BCTL0 BCTL1/CS5 D S I / S Y S. B U S / E T H E R N E T S Y S T E M B U S M E M C D S I M E M C S Y S G P I O / T D M / E T H E R N E T / T I M E R S / I 2 C BM[0–2]/TC[0–2]/BNKSEL[0–2] ALE PWE[0–3]/PSDDQM[0–3]/PBS[0–3] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 EE0 EE1 CLKOUT Reserved CLKIN PORESET HRESET SRESET De bug C L K R E S E T J T A G RSTCONF TMS TDI TCK TRST TDO Ded. 1 Eth. 1 Net 1 ← ETHRX_CLK/ETHSYNC_IN ← ETHTX_CLK/ETHREF_CLK/ETHCLOCK ← ETHCRS/ETHRXD Power signals are: VDD, VDDH, VCCSYN, GND, GNDH, and GNDSYN. Reserved signals can be left unconnected. NC signals must not be connected. Figure 1-1. MSC8122 External Signals MSC8122 Technical Data, Rev. 13 1-2 Freescale Semiconductor Power Signals 1.1 Power Signals Table 1-2. Signal Name VDD Power and Ground Signal Inputs Description Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. System Ground An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors. System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground. VDDH VCCSYN GND GNDSYN 1.2 Clock Signals Table 1-3. Signal Name CLKIN CLKOUT Reserved Clock Signals Signal Description Type Input Output Input Clock In Primary clock input to the MSC8122 PLL. Clock Out The bus clock. Reserved. Pull down to ground. 1.3 Reset and Configuration Signals Table 1-4. Signal Name PORESET RSTCONF Reset and Configuration Signals Signal Description Type Input Input Power-On Reset When asserted, this line causes the MSC8122 to enter power-on reset state. Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the MSC8122 Reference Manual. This signal is sampled upon deassertion of PORESET. Note: When PORESET is deasserted, the MSC8122 also samples the following signals: • BM[0–2]—Selects the boot mode. • MODCK[1–2]—Selects the clock configuration. • SWTE—Enables the software watchdog timer. • DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI. Refer to Table 1-5 for details on these signals. HRESET Input/Output Hard Reset When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device enters a hard reset state, it drives the signal as an open-drain output. Input/Output Soft Reset When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device enters a soft reset state, it drives the signal as an open-drain output. SRESET MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-3 Signals/Connections 1.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals The direct slave interface (DSI) is combined with the system bus because they share some common signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5 describes the signals in this group. Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration enables only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines. Table 1-5. Signal Name HD0 DSI, System Bus, Ethernet, and Interrupt Signals Description Type Input/ Output Host Data Bus 0 Bit 0 of the DSI data bus. Input SWTE HD1 Software Watchdog Timer Disable. It is sampled on the rising edge of PORESET signal. Input/ Output Host Data Bus 1 Bit 1 of the DSI data bus. Input DSI Synchronous Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising edge of PORESET signal. DSISYNC HD2 Input/ Output Host Data Bus 2 Bit 2 of the DSI data bus. Input DSI 64 Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET signal. DSI64 HD3 Input/ Output Host Data Bus 3 Bit 3 of the DSI data bus. Input Clock Mode 1 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal. MODCK1 HD4 Input/ Output Host Data Bus 4 Bit 4 of the DSI data bus. Input Clock Mode 2 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal. MODCK2 HD5 Input/ Output Host Data Bus 5 Bit 5 of the DSI data bus. Input Configuration Source One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of PORESET signal. CNFGS HD[6–31] Input/ Output Host Data Bus 6–31 Bits 6–31 of the DSI data bus. MSC8122 Technical Data, Rev. 13 1-4 Freescale Semiconductor Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals Table 1-5. Signal Name HD[32–39] DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input/ Output Host Data Bus 32–39 Bits 32–39 of the DSI data bus. D[32–39] Input/ Output System Bus Data 32–39 For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives valid data on this bus. Input If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected. Reserved HD40 Input/ Output Host Data Bus 40 Bit 40 of the DSI data bus. Input/ Output System Bus Data 40 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data 0 In MII and RMII modes, bit 0 of the Ethernet receive data. D40 ETHRXD0 HD41 Input/ Output Host Data Bus 41 Bit 41 of the DSI data bus. Input/ Output System Bus Data 41 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data 1 In MII and RMII modes, bit 1 of the Ethernet receive data. D41 ETHRXD1 HD42 Input/ Output Host Data Bus 42 Bit 42 of the DSI data bus. Input/ Output System Bus Data 42 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data 2 In MII mode only, bit 2 of the Ethernet receive data. In RMII mode, this pin is reserved and can be left unconnected. D42 ETHRXD2 Reserved HD43 Input Input/ Output Host Data Bus 43 Bit 43 of the DSI data bus. Input/ Output System Bus Data 43 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data 3 In MII mode only, bit 3 of the Ethernet receive data. In RMII mode, this pin is reserved and can be left unconnected. D43 ETHRXD3 Reserved HD[44–45] Input Input/ Output Host Data Bus 44–45 Bits 44–45 of the DSI data bus. Input/ Output System Bus Data 44–45 For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives valid data on this bus. Input If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected. D[44–56] Reserved MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-5 Signals/Connections Table 1-5. Signal Name HD46 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input/ Output Host Data Bus 46 Bit 46 of the DSI data bus. D46 Input/ Output System Bus Data 46 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data 0 In MII and RMII modes, bit 0 of the Ethernet transmit data. ETHTXD0 HD47 Input/ Output Host Data Bus 47 Bit 47 of the DSI data bus. Input/ Output System Bus Data 47 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data 1 In MII and RMII modes, bit 1 of the Ethernet transmit data. D47 ETHTXD1 HD48 Input/ Output Host Data Bus 48 Bit 48 of the DSI data bus. Input/ Output System Bus Data 48 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data 2 In MII mode only, bit 2 of the Ethernet transmit data. In RMII mode, this pin is reserved and can be left unconnected. D48 ETHTXD2 Reserved HD49 Input Input/ Output Host Data Bus 49 Bit 49 of the DSI data bus. Input/ Output System Bus Data 49 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data 3 In MII mode only, bit 3 of the Ethernet transmit data. In RMII mode, this pin is reserved and can be left unconnected. D49 ETHTXD3 Reserved HD[50–53] Input Input/ Output Host Data Bus 50–53 Bits 50–53 of the DSI data bus. Input/ Output System Bus Data 50–53 For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives valid data on this bus. Input If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected. D[50–53] Reserved HD54 Input/ Output Host Data Bus 54 Bit 54 of the DSI data bus. Input/ Output System Bus Data 54 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data Enable In MII and RMII modes, indicates that the transmit data is valid. D54 ETHTX_EN MSC8122 Technical Data, Rev. 13 1-6 Freescale Semiconductor Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals Table 1-5. Signal Name HD55 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input/ Output Host Data Bus 55 Bit 55 of the DSI data bus. D55 Input/ Output System Bus Data 55 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Transmit Data Error In MII mode only, indicates a transmit data error. In RMII mode, this pin is reserved and can be left unconnected. ETHTX_ER Reserved HD56 Input Input/ Output Host Data Bus 56 Bit 56 of the DSI data bus. Input/ Output System Bus Data 56 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data Valid Indicates that the receive data is valid. Ethernet Carrier Sense/Receive Data Valid In RMII mode, indicates that a carrier is detected and after the connection is established that the receive data is valid. D56 ETHRX_DV ETHCRS_DV Input HD57 Input/ Output Host Data Bus 57 Bit 57 of the DSI data bus. Input/ Output System Bus Data 57 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input Ethernet Receive Data Error In MII and RMII modes, indicates a receive data error. D57 ETHRX_ER HD58 Input/ Output Host Data Bus 58 Bit 58 of the DSI data bus. Input/ Output System Bus Data 58 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Output Ethernet Management Clock In MII and RMII modes, used for the MDIO reference clock. D58 ETHMDC HD59 Input/ Output Host Data Bus 59 Bit 59 of the DSI data bus. Input/ Output System Bus Data 59 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input/ Output Ethernet Management Data In MII and RMII modes, used for station management data input/output. D59 ETHMDIO MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-7 Signals/Connections Table 1-5. Signal Name HD60 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input/ Output Host Data Bus 60 Bit 60 of the DSI data bus. D60 Input/ Output System Bus Data 60 For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives valid data on this bus. Input/ Output Ethernet Collision In MII mode only, indicates that a collision was detected. Input In RMII mode, this pin is reserved and can be left unconnected. ETHCOL Reserved HD[61–63] Input/ Output Host Data Bus 61–63 Bits 61–63 of the DSI data bus. Input/ Output System Bus Data 61–63 For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives valid data on this bus. Input Input If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected. Host Chip ID 0–2 With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID, or if HBCS is asserted. Host Chip ID 3 With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID, or if HBCS is asserted. Host Bus Address 8 Used by an external host to access the internal address space. Host Bus Address 11–29 Used by external host to access the internal address space. Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host read or write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host write accesses D[61–63] Reserved HCID[0–2] HCID3 Input HA8 HA[11–29] HWBS[0–3] Input Input Input HDBS[0–3] Input HWBE[0–3] Input HDBE[0–3] Input MSC8122 Technical Data, Rev. 13 1-8 Freescale Semiconductor Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals Table 1-5. Signal Name HWBS[4–7] DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host read or write accesses System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. Host Read Data Strobe (In Asynchronous dual mode) Used as a strobe for host read accesses. Host Read/Write Select (in Asynchronous/Synchronous single mode) Host read/write select. Host Read Data Enable (In Synchronous dual mode) Indicates valid data for host read accesses. Host Burst The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode only. Host Data Structure 0–1 Defines the data structure of the host access in DSI little-endian mode. Host Bus Address 9–10 Used by an external host to access the internal address space. HDBS[4–7] Input HWBE[4–7] Input HDBE[4–7] Input PWE[4–7] Output PSDDQM[4–7] Output PBS[4–7] Output HRDS Input HRW Input HRDE HBRST Input Input HDST[0–1] Input HA[9–10] HCS HBCS Input Input Host Chip Select DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID. Host Broadcast Chip Select DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for broadcast write accesses. Host Transfer Acknowledge Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access, indicates to the host that the data on the data bus was written to the DSI write buffer. Host Clock Input Host clock signal for DSI synchronous mode. HTA Output HCLKIN A[0–31] Input Input/ Output Address Bus When the MSC8122 is in external master bus mode, these pins function as the system address bus. The MSC8122 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8122 memory controller. Input/ Output Bus Transfer Type 0 The bus master drives this pins during the address tenure to specify the type of the transaction. Host Bus Address 7 Used by an external host to access the internal address space. TT0 HA7 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-9 Signals/Connections Table 1-5. Signal Name TT1 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input/ Output Bus Transfer Type 1 The bus master drives this pins during the address tenure to specify the type of the transaction. Some applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101 and vice versa. In these applications, TT1 functions as read/write signal. Input/ Output Bus Transfer Type 2–4 The bus master drives these pins during the address tenure to specify the type of the transaction. Output Output Chip Select 5–7 Enables specific memory devices or peripherals connected to the system bus. Chip Select 0–4 Enables specific memory devices or peripherals connected to the system bus. TT[2–4] CS[5–7] CS[0–4] TSZ[0–3] Input/ Output Transfer Size 0–3 The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. Input/ Output Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers eight words). Input Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Global1 When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin indicates that the transfer is global and should be snooped by caches in the system. Interrupt Request 31 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 311 Five burst address output pins are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8122 memory controller. Interrupt Request 21 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 301 Five burst address output pins are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8122 memory controller. Interrupt Request 51 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Burst Address 291 Five burst address output pins are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8122 memory controller. Burst Address 28 Five burst address output pins are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8122 memory controller. Burst Address 27 Five burst address output pins are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8122 memory controller. TBST IRQ1 GBL Output IRQ3 Input BADDR31 Output IRQ2 Input BADDR30 Output IRQ5 Input BADDR29 Output BADDR28 Output BADDR27 Output MSC8122 Technical Data, Rev. 13 1-10 Freescale Semiconductor Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals Table 1-5. Signal Name BR DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Request2 Type Input/ Output Bus When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an input to request bus ownership. Input/ Output Bus Grant2 When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership to the MSC8122. Input/ Output Data Bus Grant2 When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data bus ownership to the MSC8122. Input/ Output Address Bus Busy1 The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses this pin is asserted as an input by an external bus master. Input Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. BG DBG ABB IRQ4 DBB Input/ Output Data Bus Busy1 The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is asserted as an input by an external bus master. Input Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. IRQ5 TS Input/ Output Bus Transfer Start Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8122 resources, memory controller support). Input/ Output Address Acknowledge A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal terminates the address tenure. Input/ Output Address Retry Assertion of this signal indicates that the bus master should retry the bus transaction. An external master asserts this signal to enforce data coherency with its caches and to prevent deadlock situations. Input/ Output Data Bus Bits 0–31 In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus. Input The primary configuration selection (default after reset) is reserved. AACK ARTRY D[0–31] Reserved DP0 Input/ Output System Bus Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0–7]. Input DMA Request 1 Used by an external peripheral to request DMA service. External Bus Request 2 An external master asserts this pin to request bus ownership from the internal arbiter. DREQ1 EXT_BR2 Input MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-11 Signals/Connections Table 1-5. Signal Name IRQ1 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP1 Input/ Output System Bus Data Parity 1 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8–15]. Output DMA Acknowledge 1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 22 The MSC8122 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DACK1 EXT_BG2 IRQ2 Output Input DP2 Input/ Output System Bus Data Parity 2 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16–23]. Output DMA Acknowledge 2 The DMA controller drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 22 The MSC8122 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DACK2 EXT_DBG2 IRQ3 Output Input DP3 Input/ Output System Bus Data Parity 3 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24–31]. Input DMA Request 2 Used by an external peripheral to request DMA service. External Bus Request 32 An external master should assert this pin to request bus ownership from the internal arbiter. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DREQ2 EXT_BR3 IRQ4 Input Input DP4 Input/ Output System Bus Data Parity 4 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32–39]. Output DMA Acknowledge 3 The DMA controller drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 32 The MSC8122 asserts this pin to grant data bus ownership to an external bus master. DACK3 EXT_DBG3 Output MSC8122 Technical Data, Rev. 13 1-12 Freescale Semiconductor Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals Table 1-5. Signal Name IRQ5 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP5 Input/ Output System Bus Data Parity 5 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40–47]. Output DMA Acknowledge 4 The DMA controller drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 32 The MSC8122 asserts this pin to grant bus ownership to an external bus. Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DACK4 EXT_BG3 IRQ6 Output Input DP6 Input/ Output System Bus Data Parity 6 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48–55]. Input Input DMA Request 3 Used by an external peripheral to request DMA service. Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DREQ3 IRQ7 DP7 Input/ Output System Bus Data Parity 7 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56–63]. Input DMA Request 4 Used by an external peripheral to request DMA service. DREQ4 TA Input/ Output Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight data beats, with the last assertion indicating the termination of the burst transfer. Input/ Output Transfer Error Acknowledge Indicates a failure of the data tenure transaction.The masters within the MSC8122 monitor the state of this pin. The MSC8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not complete. Input Non-Maskable Interrupt When an external device asserts this line, it generates an non-maskable interrupt in the MSC8122, which is processed internally (default) or is directed to an external host for processing (see NMI_OUT). Non-Maskable Interrupt Output An open-drain pin driven from the MSC8122 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in the MSC8122 internal interrupt controller, waiting to be handled by an external host. TEA NMI NMI_OUT Output PSDVAL Input/ Output Port Size Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA controller initiates a double word (2 × 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times without TA and, finally, both pins are asserted to terminate the transfer. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-13 Signals/Connections Table 1-5. Signal Name IRQ7 DSI, System Bus, Ethernet, and Interrupt Signals (Continued) Description Type Input Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Interrupt Output Assertion of this output indicates that an unmasked interrupt is pending in the MSC8122 internal interrupt controller. INT_OUT Output Notes: 1. 2. See the System Interface Unit (SIU) chapter in the MSC8122 Reference Manual for details on how to configure these pins. When used as the bus control arbiter, the MSC8122 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8122 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in the MSC8122 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8122 is not the bus arbiter, it uses these signals (BR/BG/DBG) to obtain master control of the bus. 1.5 Memory Controller Signals Refer to the Memory Controller chapter in the MSC8122 Reference Manual for details on configuring these signals. Table 1-6. Signal Name BCTL0 Memory Controller Signals Description Type Output System Bus Buffer Control 0 Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System Bus Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System and Local Bus Chip Select 5 Enables specific memory devices or peripherals connected to MSC8122 buses. Boot Mode 0–2 Defines the boot mode of the MSC8122. This signal is sampled on PORESET deassertion. BCTL1 Output CS5 BM[0–2] Output Input TC[0–2] Input/ Output Transfer Code 0–2 The bus master drives these pins during the address tenure to specify the type of the code. Output Output Output Bank Select 0–2 Selects the SDRAM bank when the MSC8122 is in 60x-compatible bus mode. Address Latch Enable Controls the external address latch used in an external master bus. System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. BNKSEL[0–2] ALE PWE[0–3] PSDDQM[0–3] Output PBS[0–3] Output MSC8122 Technical Data, Rev. 13 1-14 Freescale Semiconductor Memory Controller Signals Table 1-6. Signal Name PSDA10 Memory Controller Signals (Continued) Description Type Output System Bus SDRAM A10 From the bus SDRAM controller. The precharge command defines which bank is precharged. When the row address is driven, it is a part of the row address. When column address is driven, it is a part of column address. System Bus UPM General-Purpose Line 0 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM Write Enable From the bus SDRAM controller. Should connect to SDRAM WE input. System Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus Output Enable From the bus GPCM. Controls the output buffer of memory devices during read operations. System Bus SDRAM RAS From the bus SDRAM controller. Should connect to SDRAM RAS input. System Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM CAS From the bus SDRAM controller. Should connect to SDRAM CAS input. System Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System GPCM TA Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper operation. System Bus UPM Wait An external device holds this pin low to force the UPM to wait until the device is ready to continue the operation. System Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus Parity Byte Select In systems that store data parity in a separate chip, this output is used as the byte-select for that chip. System Bus SDRAM Address Multiplexer Controls the system bus SDRAM address multiplexer when the MSC8122 is in external master mode. System Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PGPL0 Output PSDWE Output PGPL1 Output POE Output PSDRAS Output PGPL2 Output PSDCAS Output PGPL3 Output PGTA Input PUPMWAIT Input PGPL4 Output PPBS PSDAMUX Output Output PGPL5 Output MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-15 Signals/Connections 1.6 GPIO, TDM, UART, and Timer Signals The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7 describes the signals in this group. Table 1-7. Signal Name GPIO0 GPIO, TDM, UART, Ethernet, and Timer Signals Description Type Input/ Output General-Purpose Input Output 0 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Input Chip ID 0 Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Transmit Data 0 For MII or RMII mode, bit 0 of the Ethernet transmit data. CHIP_ID0 IRQ4 Input ETHTXD0 GPIO1 Output Input/ Output General-Purpose Input Output 1 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Input/ Output Timer 0 Each signal is configured as either input to or output from the counter. See the MSC8122 Reference Manual for configuration details. Input Chip ID 1 Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal. Interrupt Request 5 One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Transmit Data 1 For MII or RMII mode, bit 1 of the Ethernet transmit data. TIMER0 CHIP_ID1 IRQ5 Input ETHTXD1 GPIO2 Output Input/ Output General-Purpose Input Output 2 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual. Input/ Output Timer 1 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8122 Reference Manual. Input Chip ID 2 Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal. Interrupt Request 6 One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TIMER1 CHIP_ID2 IRQ6 Input MSC8122 Technical Data, Rev. 13 1-16 Freescale Semiconductor GPIO, TDM, UART, and Timer Signals Table 1-7. Signal Name GPIO3 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 3 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM3 Transmit Frame Sync Transmit frame sync for TDM 3. Input Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Transmit Data 2 For MII mode only, bit 2 of the Ethernet transmit data. TDM3TSYN IRQ1 ETHTXD2 GPIO4 Output Input/ Output General-Purpose Input Output 4 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input TDM3 Transmit Clock Transmit Clock for TDM 3 Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Transmit Data Error For MII mode only, indicates whether a transmit data error occurred. TDM3TCLK IRQ2 Input ETHTX_ER GPIO5 Output Input/ Output General-Purpose Input/Output 5 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM3 Serial Transmitter Data The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data 3 For MII mode only, bit 3 of the Ethernet receive data. TDM3TDAT IRQ3 ETHRXD3 GPIO6 Input Input/ Output General-Purpose Input Output 6 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM3 Receive Frame Sync The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data 2 For MII mode only, bit 2 of the Ethernet receive data. TDM3RSYN IRQ4 ETHRXD2 Input MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-17 Signals/Connections Table 1-7. Signal Name GPIO7 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 7 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM3 Receive Clock The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Transmit Data 3 For MII mode only, bit 3 of the Ethernet transmit data. TDM3RCLK IRQ5 ETHTXD3 GPIO8 Output Input/ Output General-Purpose Input Output 8 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM3 Serial Receiver Data The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Collision For MII mode only, indicates whether a collision was detected. TDM3RDAT IRQ6 ETHCOL GPIO9 Input Input/ Output General-Purpose Input Output 9 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM2 Transmit frame Sync Transmit Frame Sync for TDM 2. Input Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TDM2TSYN IRQ7 ETHMDIO GPIO10 Input/ Output Ethernet Management Data Station management data input/output line in MII, RMII, and SMII modes. Input/ Output General-Purpose Input Output 10 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input TDM 2 Transmit Clock Transmit Clock for TDM 2. Interrupt Request 8 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data Valid In MII mode, this signal indicates that the receive data is valid. Ethernet Carrier Sense/Receive Data Valid In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid. Not Connected For SMII mode, this signal must be left unconnected. TDM2TCLK IRQ8 Input ETHRX_DV Input ETHCRS_DV Input NC Input MSC8122 Technical Data, Rev. 13 1-18 Freescale Semiconductor GPIO, TDM, UART, and Timer Signals Table 1-7. Signal Name GPIO11 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 11 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM2 Serial Transmitter Data The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 9 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data Error In MII and RMII modes, indicates a receive data error. Ethernet Transmit Data In SMII, used as the Ethernet transmit data line. TDM2TDAT IRQ9 ETHRX_ER Input ETHTXD GPIO12 Output Input/ Output General-Purpose Input Output 12 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM2 Receive Frame Sync The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 10 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data 1 Bit 1 of the Ethernet receive data (MII and RMII mode). Ethernet Sync Signal In SMII mode, this is the Ethernet sync signal input. TDM2RSYN IRQ10 ETHRXD1 Input ETHSYNC GPIO13 Output Input/ Output General-Purpose Input Output 13 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM2 Receive Clock The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Management Clock Used for the MDIO reference clock for MII, RMII, and SMII modes. TDM2RCLK IRQ11 ETHMDC Output MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-19 Signals/Connections Table 1-7. Signal Name GPIO14 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 14 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM2 Serial Receiver Data Input The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 12 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Ethernet Receive Data 0 Bit 0 of the Ethernet receive data (MII and RMII). Not Connected For SMII mode, this signal must be left unconnected. TDM2RDAT IRQ12 ETHRXD0 Input NC GPIO15 Input Input/ Output General-Purpose Input Output 15 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM1 Transmit frame Sync Transmit Frame Sync for TDM 1. Input DMA Request 1 Used by an external peripheral to request DMA service. TDM1TSYN DREQ1 GPIO16 Input/ Output General-Purpose Input Output 16 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input TDM1 Transmit Clock Transmit Clock for TDM 1. TDM1TCLK DONE1 Input/ Output DMA Done 1 Signifies that the channel must be terminated. If the DMA controller generates DONE, the channel handling this peripheral is inactive. As an input to the DMA controller, DONE closes the channel much like a normal channel closing. See the MSC8122 Reference Manual chapters on DMA controller and GPIO for information on configuring the DRACK or DONE mode and pin direction. DRACK1 GPIO17 Output DMA Data Request Acknowledge 1 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. Input/ Output General-Purpose Input Output 17 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM1 Serial Transmitter Data The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Output DMA Acknowledge 1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. TDM1TDAT DACK1 MSC8122 Technical Data, Rev. 13 1-20 Freescale Semiconductor GPIO, TDM, UART, and Timer Signals Table 1-7. Signal Name GPIO18 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 18 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM1 Receive Frame Sync The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For configuration details, refer to the MSC8122 Reference Manual. Input DMA Request 1 Used by an external peripheral to request DMA service. TDM1RSYN DREQ2 GPIO19 Input/ Output General-Purpose Input Output 19 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM1 Receive Clock The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Output DMA Acknowledge 2 The DMA controller drives this output to acknowledge the DMA transaction on the bus. TDM1RCLK DACK2 GPIO20 Input/ Output General-Purpose Input Output 20 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM1 Serial Receiver Data The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For configuration details, refer to the MSC8122 Reference Manual. Input/ Output General-Purpose Input Output 21 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM0 Transmit frame Sync Transmit Frame Sync for TDM 0. Input/ Output General-Purpose Input Output 22 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8122 Reference Manual GPIO programming model. Input TDM 0 Transmit Clock Transmit Clock for TDM 0. TDM1RDAT GPIO21 TDM0TSYN GPIO22 TDM0TCLK DONE2 Input/ Output DMA Done 2 Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel closing. Note: See the MSC8122 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction. DRACK2 Output DMA Data Request Acknowledge 2 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-21 Signals/Connections Table 1-7. Signal Name GPIO23 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 23 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM0 Serial Transmitter Data The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 13 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TDM0TDAT IRQ13 GPIO24 Input/ Output General-Purpose Input Output 24 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM0 Receive Frame Sync The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 14 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TDM0RSYN IRQ14 GPIO25 Input/ Output General-Purpose Input Output 25 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM0 Receive Clock The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input Interrupt Request 15 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TDM0RCLK IRQ15 GPIO26 Input/ Output General-Purpose Input Output 26 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output TDM0 Serial Receiver Data The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For configuration details, refer to the MSC8122 Reference Manual chapter describing TDM operation. Input/ Output General-Purpose Input Output 27 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input DMA Request 1 Used by an external peripheral to request DMA service. UART Receive Data TDM0RDAT GPIO27 DREQ1 URXD GPIO28 Input Input/ Output General-Purpose Input Output 28 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input DMA Request 2 Used by an external peripheral to request DMA service. UART Transmit Data DREQ2 UTXD Output MSC8122 Technical Data, Rev. 13 1-22 Freescale Semiconductor Dedicated Ethernet Signals Table 1-7. Signal Name GPIO29 GPIO, TDM, UART, Ethernet, and Timer Signals (Continued) Description Type Input/ Output General-Purpose Input Output 29 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input Chip ID 3 Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal. Ethernet Transmit Enable Used to enable the Ethernet transmit controller for MII and RMII modes. CHIP_ID3 ETHTX_EN GPIO30 Output Input/ Output General-Purpose Input Output 30 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output Timer 2 Each signal is configured as either input to the counter or output from the counter. For the configuration of the pin direction, refer to the MSC8122 Reference Manual. Input External TIMER Clock An external timer can connect directly to the SIU as the SIU clock. TIMER2 TMCLK SDA GPIO31 Input/ Output I2C-Bus Data Line This is the data line for the I2C bus. Input/ Output General-Purpose Input Output 31 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8122 Reference Manual GPIO programming model. Input/ Output Timer 3 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8122 Reference Manual. Input/ Output I2C-Bus Clock Line This the clock line for the I2C bus. TIMER3 SCL 1.7 Dedicated Ethernet Signals Most Ethernet signals are multiplexed with the DSI/system bus and the GPIO ports. In addition to the multiplexed signals, there are three dedicated Ethernet signals that are described in Table 1-8. Table 1-8. Signal Name ETHRX_CLK Dedicated Ethernet Signals Signal Description Type Input Receive Clock In MII mode, provides the timing reference for the receive signals. Sync Input In SMII mode, is the sync signal input line. Transmit Clock In MII mode, provides the timing reference for transmit signals. Reference Clock In RMII mode, provides the timing reference. Ethernet Clock In SMII mode, provides the Ethernet clock signal. ETHSYNC_IN ETHTX_CLK Input Input ETHREF_CLK Input ETHCLOCK Input MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 1-23 Signals/Connections Table 1-8. Signal Name ETHCRS Dedicated Ethernet Signals Signal Description Type Input Carrier Sense In MII mode, indicates that either the transmit or receive medium is non-idle. Ethernet Receive Data In SMII mode, used for the Ethernet receive data. ETHRXD Input 1.8 EOnCE Event and JTAG Test Access Port Signals The MSC8122 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the same two signals EE0 and EE1. The MSC8122 supports the standard set of test access port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-9. Table 1-9. Signal Name EE0 EE1 TCK TDI TDO JTAG TAP Signals Signal Description Type Input Output Input Input Output EOnCE Event Bit 0 Puts the internal SC140 cores into Debug mode. EOnCE Event Bit 1 Indicates that at least one on-device SC140 core is in Debug mode. Test Clock—Synchronizes JTAG test logic. Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. Test Mode Select—Sequences the test controller state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. Test Reset—Asynchronously initializes the test controller; must be asserted during power up. TMS TRST Input Input 1.9 Reserved Signals Table 1-10. Signal Name TEST Reserved Signals Signal Description Type Input Test For manufacturing testing. You must connect this pin to GND. MSC8122 Technical Data, Rev. 13 1-24 Freescale Semiconductor Specifications 2 This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8122 User’s Guide and MSC8122 Reference Manual. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-1 Specifications Table 2-1 describes the maximum electrical ratings for the MSC8122. Table 2-1. Rating Core and PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature: • Standard range • Extended range Minimum operating temperature • Standard range • Extended range Storage temperature range Notes: 1. 2. 3. Absolute Maximum Ratings Symbol VDD VDDH VIN TJ 90 105 TJ 0 –40 TSTG –55 to +150 °C °C °C °C °C Value –0.2 to 1.6 –0.2 to 4.0 –0.2 to 4.0 Unit V V V Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 4.5, Thermal Considerations includes a formula for computing the chip junction temperature (TJ). 2.2 Recommended Operating Conditions Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Rating Core and PLL supply voltage: • Standard — 400 MHz — 500 MHz • Reduced (300 and 400 MHz) I/O supply voltage Input voltage Operating temperature range: • Standard • Extended Recommended Operating Conditions Symbol VDD VCCSYN 1.14 to 1.26 1.16 to 1.24 1.07 to 1.13 VDDH VIN TJ TJ 3.135 to 3.465 –0.2 to VDDH+0.2 0 to 90 –40 to 105 V V V V V °C °C Value Unit MSC8122 Technical Data, Rev. 13 2-2 Freescale Semiconductor Thermal Characteristics 2.3 Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8122 for the FC-PBGA packages. Table 2-3. Thermal Characteristics for the MSC8122 FC-PBGA 20 × 20 mm5 Natural Convection Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)4 Junction-to-case 5 1, 3 Characteristic Symbol Unit 200 ft/min (1 m/s) airflow 21 15 °C/W °C/W °C/W °C/W °C/W RθJA RθJA RθJB RθJC Ψ JT 26 19 9 0.9 1 Junction-to-package-top6 Notes: 1. 2. 3. 4. 5. 6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics. 2.4 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8122. The measurements in Table 2-4 assume the following system conditions: • • TA = 25 °C VDD = — 300/400 MHz 1.1 V nominal = 1.07–1.13 VDC — 400 MHz 1.2 V nominal = 1.14–1.26 VDC — 500 MHz 1.2 V nominal = 1.16–1.24 VDC • • = 3.3 V ± 5% VDC GND = 0 VDC VDDH Note: The leakage current is measured for nominal VDDH and VDD. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-3 Specifications Table 2-4. Characteristic Input high voltage , all inputs except CLKIN Input low voltage1 CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH 1 DC Electrical Characteristics Symbol VIH VIL VIHC VILC IIN IOZ IL IH VOH VOL IDDW IDDS P Min 2.0 GND 2.4 GND –1.0 –1.0 –1.0 –1.0 2.0 — — — — Typical — 0 3.0 0 0.09 0.09 0.09 0.09 3.0 0 3753 2903 1.15 Max 3.465 0.4 3.465 0.4 1 1 1 1 — 0.4 — — — Unit V V V V µA µA µA µA V V mA mA W Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current, VIL = 0.4 V Output high voltage, IOH = –2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Internal supply current: • Wait mode • Stop mode Typical power 400 MHz at 1.2 V4 Notes: 1. 2. 3. 4. 2 Signal high input current, VIH = 2.0 V2 See Figure 2-1 for undershoot and overshoot voltages. Not tested. Guaranteed by design. Measured for 1.2 V core at 25°C junction temperature. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and all four cores. It was created using CodeWarrior® 2.5. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 of this document and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601). VIH VDDH + 17% VDDH + 8% VDDH VIL GND GND – 0.3 V GND – 0.7 V Must not exceed 10% of clock period Figure 2-1. Overshoot/Undershoot Voltage for VIH and VIL 2.5 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay. When calculating overall loading, also consider additional RC delay. MSC8122 Technical Data, Rev. 13 2-4 Freescale Semiconductor AC Timings 2.5.1 Output Buffer Impedances Table 2-5. Output Buffers Output Buffer Impedances Typical Impedance (Ω) 50 50 50 System bus Memory controller Parallel I/O Note: These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature. 2.5.2 Start-Up Timing Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8122 device: • • • • PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-10 for timing. If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD levels and then the VDDH levels (see Figure 2-3). CLKIN should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET deassertion to guarantee correct device operation (see Figure 2-2 and Figure 2-3). CLKIN must not be pulled high during VDDH power-up. CLKIN can toggle during this period. The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which VDD and VDDH are raised together. Figure 2-3 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises. VDDH = Nominal Value VDD = Nominal Value 1 3.3 V VDDH Nominal Level Voltage 2.2 V 1.2 V o.5 V VDD Nominal Level Time PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted VDD/VDDH Applied Figure 2-2. Start-Up Sequence with VDD and VDDH Raised Together MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-5 Specifications VDDH = Nominal VDD = Nominal 1 3.3 V VDDH Nominal Voltage 1.2 V o.5 V VDD Nominal Time PORESET/TRST asserted VDD applied CLKIN starts toggling VDDH applied PORESET/TRST deasserted Figure 2-3. Start-Up Sequence with VDD Raised Before VDDH with CLKIN Started with VDDH 2.5.3 Clock and Timing Signals The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded. Table 2-6. Characteristic Core frequency Reference frequency (REFCLK) Internal bus frequency (BLCK) DSI clock frequency (HCLKIN) • Core frequency = 300 MHz • Core frequency = 400/500 MHz External clock frequency (CLKIN or CLKOUT) Maximum Frequencies Maximum in MHz 300/400/500 100/133/166 100/133/166 HCLKIN ≤ (min{70 MHz, CLKOUT}) HCLKIN ≤ (min{100 MHz, CLKOUT}) 100/133/166 Table 2-7. Characteristics CLKIN frequency BCLK frequency Reference clock (REFCLK) frequency Output clock (CLKOUT) frequency SC140 core clock frequency Note: Clock Frequencies 300 MHz Device 400 MHz Device Min 20 40 40 40 200 500 MHz Device Min 20 40 40 40 200 Symbol Min FCLKIN FBCLK FREFCLK FCLKOUT FCORE 20 40 40 40 200 Max 100 100 100 100 300 Max 133.3 133.3 133.3 133.3 400 Max 166.7 166.7 166.7 166.7 500 The rise and fall time of external clocks should be 3 ns maximum Table 2-8. Characteristic Phase jitter between BCLK and CLKIN CLKIN frequency CLKIN slope PLL input clock (after predivider) System Clock Parameters Min — 20 — 20 Max 0.3 see Table 2-7 3 100 Unit ns MHz ns MHz MSC8122 Technical Data, Rev. 13 2-6 Freescale Semiconductor AC Timings Table 2-8. Characteristic PLL output frequency (VCO output) • 300 MHz core • 400 MHz core • 500 MHz core CLKOUT frequency jitter1 CLKOUT phase jitter1 with CLKIN phase jitter of ±100 ps. Notes: 1. 2. Peak-to-peak. Not tested. Guaranteed by design. System Clock Parameters Min 800 1200 1600 2000 — — 200 500 Max Unit MHz MHz MHz MHz ps ps 2.5.4 • • • • • • Reset Timing Power-on reset (PORESET) External hard reset (HRESET) External soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through JTAG The MSC8122 has several inputs to the reset logic: All MSC8122 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset sources. Table 2-9. Name Power-on reset (PORESET) Reset Sources Description Direction Input Initiates the power-on reset flow that resets the MSC8122 and configures various attributes of the MSC8122. On PORESET, the entire MSC8122 device is reset. SPLL states is reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System Bus 64 bits port are configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC8122. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are reconfigured. These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word section of the Reset chapter in the MSC8122 Reference Manual. Initiates the soft reset flow. The MSC8122 detects an external assertion of SRESET only if it occurs while the MSC8122 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained. When the MSC8122 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the MSC8122 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated. External hard reset (HRESET) Input/ Output External soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through the TAP Input/ Output Internal Internal Internal Table 2-10 summarizes the reset actions that occur as a result of the different reset sources. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-7 Specifications Table 2-10. Reset Actions for Each Reset Source Hard Reset (HRESET) External or Internal (Software Watchdog or Bus Monitor) No No No Yes Yes Yes Yes Power-On Reset (PORESET) Reset Action/Reset Source External only Configuration pins sampled (Refer to Section 2.5.4.1 for details). SPLL state reset System reset configuration write through the DSI System reset configuration write though the system bus HRESET driven SIU registers reset IPBus modules reset (TDM, UART, Timers, DSI, IPBus master, GIC, HS, and GPIO) SRESET driven SC140 extended cores reset MQBS reset Yes Yes Yes Yes Yes Yes Yes Soft Reset (SRESET) JTAG Command: EXTEST, CLAMP, or HIGHZ No No No No No No Yes External No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Depends on command Yes Yes 2.5.4.1 Power-On Reset (PORESET) Pin Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after VDD and VDDH are both at their nominal levels. 2.5.4.2 Reset Configuration The MSC8122 has two mechanisms for writing the reset configuration: • • Through the direct slave interface (DSI) Through the system bus. When the reset configuration is written through the system bus, the MSC8122 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. Fourteen signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the Reset Configuration Mode and boot and operating conditions: • • • • • • • • RSTCONF CNFGS DSISYNC DSI64 CHIP_ID[0–3] BM[0–2] SWTE MODCK[1–2] MSC8122 Technical Data, Rev. 13 2-8 Freescale Semiconductor AC Timings 2.5.4.3 Reset Timing Tables Table 2-11 and Figure 2-4 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus. Table 2-11. No. 1 Timing for a Reset Configuration Write through the DSI or System Bus Characteristics Expression 16/CLKIN 800 160 120 96 1024/CLKIN 6.17 6400/(CLKIN/RDF) (PLL reference clockdivision factor) 320 64 96 77 3.08 3.10 3 51.2 320 64 96 77 12.8 12.88 — µs µs µs µs µs µs µs ns — — — — ns ns ns ns Min Max Unit Required external PORESET duration minimum • CLKIN = 20 MHz • CLKIN = 100 MHz (300 MHz core) • CLKIN = 133 MHz (400 MHz core) • CLKIN = 166 MHz (500 MHz core) Delay from deassertion of external PORESET to deassertion of internal PORESET • CLKIN = 20 MHz to 166 MHz Delay from de-assertion of internal PORESET to SPLL lock • CLKIN = 20 MHz (RDF = 1) • CLKIN = 100 MHz (RDF = 1) (300 MHz core) • CLKIN = 133 MHz (RDF = 2) (400 MHz core) • CLKIN = 166 MHz (RDF = 2) (500 MHz core) Delay from SPLL to HRESET deassertion • REFCLK = 40 MHz to 166 MHz Delay from SPLL lock to SRESET deassertion • REFCLK = 40 MHz to 166 MHz Setup time from assertion of RSTCONF, CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] before deassertion of PORESET Hold time from deassertion of PORESET to deassertion of RSTCONF, CNFGS, DSISYNC, DSI64, CHIP_ID[0–3], BM[0–2], SWTE, and MODCK[1–2] Timings are not tested, but are guaranteed by design. 2 3 5 6 7 512/REFCLK 515/REFCLK 8 5 — ns Note: 1 RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled Host programs Reset Configuration Word SPLL is locked (no external indication) PORESET Input PORESET Internal 1+2 MODCK[3–5] HRESET Output (I/O) 2 3 SRESET Output (I/O) Reset configuration write sequence during this period. SPLL locking period 5 6 Figure 2-4. Timing Diagram for a Reset Configuration Write MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-9 Specifications 2.5.5 System Bus Access Timing 2.5.5.1 Core Data Transfers Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-12 shows. Table 2-12. Tick Spacing for Memory Controller Signals Tick Spacing (T1 Occurs at the Rising Edge of REFCLK) BCLK/SC140 clock T2 1:4, 1:6, 1:8, 1:10 1:3 1:5 1/4 REFCLK 1/6 REFCLK 2/10 REFCLK T3 1/2 REFCLK 1/2 REFCLK 1/2 REFCLK T4 3/4 REFCLK 4/6 REFCLK 7/10 REFCLK Figure 2-5 is a graphical representation of Table 2-12. REFCLK T1 REFCLK T1 T2 T3 T4 T2 T3 T4 for 1:3 for 1:4, 1:6, 1:8, 1:10 REFCLK T1 T2 T3 T4 for 1:5 Figure 2-5. Internal Tick Spacing for Memory Controller Signals MSC8122 Technical Data, Rev. 13 2-10 Freescale Semiconductor AC Timings The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge. Table 2-13. AC Timing for SIU Inputs Value for Bus Speed in MHz Ref = CLKIN No. Characteristic 1.1 V 100/ 133 10 11a 11b 11c 11d Hold time for all signals after the 50% level of the REFCLK rising edge ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge AACK set-up time before the 50% level of the REFCLK rising edge TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode Data bus set-up time before REFCLK rising edge in Normal mode • Data-pipeline mode • Non-pipeline mode Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes • Data-pipeline mode • Non-pipeline mode DP set-up time before the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode TS and Address bus set-up time before the 50% level of the REFCLK rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • No extra cycle mode (SIUBCR[EXDD] = 1) Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the REFCLK rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • No extra cycle mode (SIUBCR[EXDD] = 1) PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge IRQx setup time before the 50% level; of the REFCLK rising edge3 IRQx minimum pulse width3 1. 2. 3. 0.5 3.1 3.6 3.0 Ref = CLKOUT 1.2 V 133 0.5 3.0 3.3 2.9 ns ns ns ns 1.2 V 133 0.5 3.0 3.3 2.9 1.2 V 166 0.5 3.0 3.3 2.9 Units 3.5 4.4 1.9 4.2 3.4 4.0 1.8 4.0 3.4 4.0 1.7 4.0 3.4 4.0 1.8 4.0 ns ns ns ns 12 131 2.0 8.2 2.0 7.9 2.0 7.3 2.0 6.1 2.0 7.3 2.0 6.1 2.0 7.3 2.0 6.1 ns ns ns ns 141 15a 4.2 5.5 3.8 5.0 3.8 5.0 3.8 5.0 ns ns 15b 3.7 4.8 3.7 4.0 6.0 + 3.5 4.4 3.7 4.0 6.0 + 3.5 4.4 3.7 4.0 6.0 + 3.5 4.4 3.7 4.0 6.0 + TREFCLK ns ns ns ns ns 16 17 18 Notes: TREFCLK TREFCLK TREFCLK Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. Guaranteed by design. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-11 Specifications Table 2-14. AC Timing for SIU Outputs Value for Bus Speed in MHz3 Ref = CLKIN Ref = CLKOUT 1.2 V 100/133 1.0 5.8 ns ns No. Characteristic 1.1 V 100/ 133 1.2 V 133 0.8 4.9 1.2 V 166 0.8 4.9 Units 302 31 32a Minimum delay from the 50% level of the REFCLK for all signals PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge Address bus max delay from the 50% level of the REFCLK rising edge • Multi-master mode (SIUBCR[EBM] = 1) • Single-master mode (SIUBCR[EBM] = 0) Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level of the REFCLK rising edge Address attributes: TT[2–4]/TC max delay from the 50% level of the REFCLK rising edge BADDR max delay from the 50% level of the REFCLK rising edge Data bus max delay from the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode DP max delay from the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode Memory controller signals/ALE/CS[0–4] max delay from the 50% level of the REFCLK rising edge DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK rising edge 1. 2. 3. 0.9 6.0 6.4 5.3 6.4 6.9 5.2 4.8 7.1 6.0 7.5 5.1 6.0 5.5 5.5 4.2 5.1 5.7 4.2 3.9 6.1 5.3 6.5 4.2 4.7 4.5 5.5 3.9 5.1 5.7 4.2 3.7 6.1 5.3 6.5 3.9 4.7 4.5 6.4 5.1 6.0 6.6 5.1 4.8 7.0 6.2 7.4 5.1 5.6 5.4 ns ns ns ns ns ns ns ns ns ns ns ns 32b 32c 32d 33a 33b 34 35a 35b Notes: Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except where otherwise specified. The load for specification 30 is 10 pF. The load for the other specifications in this table is 20 pF. For a 15 pF load, subtract 0.3 ns from the listed value. The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8122 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. • In single-master mode, the frequency depends on the timing of the devices connected to the MSC8122. • To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details. MSC8122 Technical Data, Rev. 13 2-12 Freescale Semiconductor AC Timings REFCLK 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB inputs 11 10 12 Data bus inputs—normal mode 10 Data bus inputs—ECC and parity modes DP inputs Address bus/TS /TT[0–4]/TC[0–2]/ TBST/TSZ[0–3]/GBL inputs PUPMWAIT input 13 14 15 16 17 IRQx inputs 30 Min delay for all output pins 31 PSDVAL/TEA/TA outputs Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs 32a/b 18 10 BADDR outputs 32c Data bus outputs DP outputs 33a 33b Memory controller/ALE outputs 34 35 AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-13 Specifications 2.5.5.2 CLKIN to CLKOUT Skew Table 2-16 describes the CLKOUT-to-CLKIN skew timing. Table 2-15. No. 20 Rise-to-rise skew • VDD = 1.1 V • VDD = 1.2 V Fall-to-fall skew • VDD = 1.1 V • VDD = 1.2 V CLKOUT phase (1.2 V, 133 MHz) • Phase high • Phase low CLKOUT phase (1.1 V, 133 MHz) • Phase high • Phase low CLKOUT phase (1.1 V, 100 MHz) • Phase high • Phase low 1. 2. 3. 4. CLKOUT Skew Min1 0.0 0.0 –1.5 –0.8 2.8 2.8 2.2 2.2 3.3 3.3 Characteristic Max1 0.95 0.85 1.0 1.0 — — — — — — Units ns ns ns ns ns ns ns ns ns ns 21 22 23 24 Notes: A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN. Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes. CLKOUT skews are measured using a load of 10 pF. CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode. For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 2-15 to adjust the riseto-fall timing values specified for CLKIN synchronization. Figure 2-6 shows the relationship between the CLKOUT and CLKIN timings. CLKIN CLKOUT 20 21 Figure 2-6. CLKOUT and CLKIN Signals. MSC8122 Technical Data, Rev. 13 2-14 Freescale Semiconductor AC Timings 2.5.5.3 DMA Data Transfers Table 2-16 describes the DMA signal timing. Table 2-16. No. 37 38 39 40 41 DMA Signals Ref = CLKIN Ref = CLKOUT (1.2 V only) Min 5.0 0.5 5.0 0.5 0.5 Characteristic Min DREQ set-up time before the 50% level of the falling edge of REFCLK DREQ hold time after the 50% level of the falling edge of REFCLK DONE set-up time before the 50% level of the rising edge of REFCLK DONE hold time after the 50% level of the rising edge of REFCLK DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge 5.0 0.5 5.0 0.5 0.5 Units ns ns ns ns ns Max — — — — 7.5 Max — — — — 8.4 The DREQ signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-16. Figure 2-7 shows synchronous peripheral interaction. REFCLK 38 37 DREQ 40 39 DONE 41 DACK/DONE/DRACK Figure 2-7. DMA Signals MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-15 Specifications 2.5.6 DSI Timing The timings in the following sections are based on a 20 pF capacitive load. 2.5.6.1 DSI Asynchronous Mode Table 2-17. No. 100 101 102 1 DSI Asynchronous Mode Timing Min 1.5 1.3 Characteristics Attributes set-up time before strobe (HWBS[n]) assertion Attributes1 hold time after data strobe deassertion Read/Write data strobe deassertion width: • DCR[HTAAD] = 1 — Consecutive access to the same DSI — Different device with DCR[HTADT] = 01 — Different device with DCR[HTADT] = 10 — Different device with DCR[HTADT] = 11 • DCR[HTAAD] = 0 Read data strobe deassertion to output data high impedance Read data strobe assertion to output data active from high impedance Output data hold time after read data strobe deassertion Read/Write data strobe assertion to HTA active from high impedance Output data valid to HTA assertion Read/Write data strobe assertion to HTA valid2 • 1.1 V core • 1.2 V core Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 0, HTA at end of access released at logic 0) Read/Write data strobe deassertion to output HTA deassertion. (DCR[HTAAD] = 1, HTA at end of access released at logic 1) Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 1, HTA at end of access released at logic 1 • DCR[HTADT] = 01 • DCR[HTADT] = 10 • DCR[HTADT] = 11 Read/Write data strobe assertion width Host data input set-up time before write data strobe deassertion Host data input hold time after write data strobe deassertion • 1.1 V core • 1.2 V core 1. 2. 3. Max — — — Unit ns ns 1.8 + TREFCLK 5 + TREFCLK 5 + (1.5 × TREFCLK) 5 + (2.5 × TREFCLK) 1.8 + TREFCLK — 2.0 2.2 2.2 3.2 — — — — — 5 + TREFCLK 5 + (1.5 × TREFCLK) 5 + (2.5 × TREFCLK) 1.8 + TREFCLK 1.0 1.7 1.5 — — — — 8.5 — — — — 7.4 6.7 6.5 6.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 103 104 105 106 107 108 109 110 111 ns ns ns ns ns ns ns 112 201 202 Notes: Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design. All values listed in this table are tested or guaranteed by design. MSC8122 Technical Data, Rev. 13 2-16 Freescale Semiconductor AC Timings Figure 2-8 shows DSI asynchronous read signals timing. HCS HA[11–29] HCID[0–4] HDST HRW1 HWBSn2 100 101 112 HDBSn1 HRDS2 102 103 107 104 HD[0–63] 106 105 109 HTA3 108 110 HTA4 111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pulldown implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation. Figure 2-8. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-17 Specifications Figure 2-9 shows DSI asynchronous write signals timing. HCS HA[11–29] HCID[0–4] HDST HRW1 HRDS2 100 101 112 HDBSn1 HWBSn2 201 202 HD[0–63] 109 102 106 HTA3 108 110 HTA4 111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation. Figure 2-9. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram Figure 2-10 shows DSI asynchronous broadcast write signals timing. HCS HA[11–29] HCID[0–4] HDST HRW1 HRDS2 100 112 101 HDBSn1 HWBSn2 201 202 HD[0–63] 102 Notes: 1. 2. Used for single-strobe mode access. Used for dual-strobe mode access. Figure 2-10. Asynchronous Broadcast Write Timing Diagram MSC8122 Technical Data, Rev. 13 2-18 Freescale Semiconductor AC Timings 2.5.6.2 DSI Synchronous Mode Table 2-18. No. 120 121 122 123 124 125 126 127 Notes: DSI Inputs in Synchronous Mode 1.1 V Core 1.2 V Core Units Min Max 55.6 33.3 33.3 — — — — — Characteristic HCLKIN cycle time1,2 HCLKIN high pulse width HCLKIN low pulse width HA[11–29] inputs set-up time HD[0–63] inputs set-up time HCID[0–4] inputs set-up time All other inputs set-up time All inputs hold time 1. 2. Values are based on a frequency range of 18–100 MHz. Refer to Table 2-6 for HCLKIN frequency limits. Expression Min 10.0 4.0 4.0 1.2 0.4 1.3 1.2 1.5 Max 55.6 33.3 33.3 — — — — — ns ns ns ns ns ns ns ns HTC (0.5 ± 0.1) × HTC (0.5 ± 0.1) × HTC — — — — — 10.0 4.0 4.0 1.2 0.6 1.3 1.2 1.5 Table 2-19. No. 128 129 130 131 132 133 134 135 DSI Outputs in Synchronous Mode 1.1 V Core 1.2 V Core Units Min Max — 7.6 — 8.3 — 7.4 — 7.5 Characteristic Min 2.0 — 1.7 — 2.0 — 1.7 — Max — 6.3 — 7.6 — 5.9 — 6.3 ns ns ns ns ns ns ns ns HCLKIN high to HD[0–63] output active HCLKIN high to HD[0–63] output valid HD[0–63] output hold time HCLKIN high to HD[0–63] output high impedance HCLKIN high to HTA output active HCLKIN high to HTA output valid HTA output hold time HCLKIN high to HTA high impedance 2.0 — 1.7 — 2.2 — 1.7 — 120 122 HCLKIN 123 HA[11–29] input signals 124 HD[0–63] input signals 125 HCID[0–4] input signals 126 All other input signals 129 121 127 127 127 127 131 130 HD[0–63] output signals ~~ ~~ 128 133 132 135 134 Figure 2-11. DSI Synchronous Mode Signals Timing Diagram MSC8122 Technical Data, Rev. 13 Freescale Semiconductor ~ ~ HTA output signal 2-19 Specifications 2.5.7 No. 300 301 302 303 304 305 306 307 308 309 310 Notes: TDM Timing Table 2-20. Characteristic TDMxRCLK/TDMxTCLK TDMxRCLK/TDMxTCLK high pulse width TDMxRCLK/TDMxTCLK low pulse width TDM receive all input set-up time TDM receive all input hold time TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3 TDMxTCLK high to TDMxTDAT/TDMxRCLK output All output hold time4 TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance2,3 TDMxTCLK high to TDMXTSYN output valid2 TDMxTSYN output hold time4 1. 2. 3. 4. TDM Timing 1.1 V Core Expression Min TC1 (0.5 ± 0.1) × TC (0.5 ± 0.1) × TC 16 7 7 1.3 1.0 2.8 — 2.5 — — 2.5 1.2 V Core Units Min 16 7 7 1.3 1.0 2.8 — 2.5 — — 2.5 Max — — — — — — 10.0 — 10.7 9.7 — Max — — — — — — 8.8 — 10.5 8.5 — ns ns ns ns ns ns ns ns ns ns ns Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz. Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz. Values are based on 20 pF capacitive load. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8122 Reference Manual for details. Values are based on 10 pF capacitive load. 300 301 TDMxRCLK 304 303 TDMxRDAT 304 302 303 TDMxRSYN Figure 2-12. TDM Inputs Signals 300 301 TDMxTCLK 306 302 308 ~~ ~~ 305 TDMxTDAT TDMxRCLK 309 TDMxTSYN 307 310 Figure 2-13. TDM Output Signals MSC8122 Technical Data, Rev. 13 2-20 Freescale Semiconductor AC Timings 2.5.8 No. 400 401 402 UART Timing Table 2-21. Characteristics URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time UART Timing Expression 16 × TREFCLK Min 160.0 Max — 10 10 Un it ns ns ns 401 401 UTXD, URXD inputs 400 400 Figure 2-14. UART Input Timing 402 402 UTXD output Figure 2-15. UART Output Timing MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-21 Specifications 2.5.9 No. 500 501 502 503 Timer Timing Table 2-22. Characteristics Min TIMERx frequency TIMERx Input high period TIMERx Output low period TIMERx Propagations delay from its clock input • 1.1 V core • 1.2 V core 10.0 4.0 4.0 3.1 2.8 Timer Timing Ref = CLKIN Unit Max — — — 9.5 8.1 ns ns ns ns ns 500 501 502 TIMERx (Input) 503 TIMERx (Output) Figure 2-16. Timer Timing 2.5.10 Ethernet Timing 2.5.10.1 Management Interface Timing Table 2-23. No. 801 802 Ethernet Controller Management Interface Timing Characteristics Min 10 10 Max — — Unit ns ns ETHMDIO to ETHMDC rising edge set-up time ETHMDC rising edge to ETHMDIO hold time ETHMDC 801 802 ETHMDIO Valid Figure 2-17. MDIO Timing Relationship to MDC MSC8122 Technical Data, Rev. 13 2-22 Freescale Semiconductor AC Timings 2.5.10.2 MII Mode Timing Table 2-24. No. 803 804 805 MII Mode Signal Timing Min 3.5 3.5 1 1 Characteristics ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay • 1.1 V core • 1.2 V core Max — — 14.6 12.6 Unit ns ns ns ns ETHRX_CLK 803 ETHRX_DV ETHRXD[0–3] ETHRX_ER Valid 804 ETHTX_CLK 805 ETHTX_EN ETHTXD[0–3] ETHTX_ER Valid Valid Figure 2-18. MII Mode Signal Timing 2.5.10.3 RMII Mode Table 2-25. No. 806 807 811 RMII Mode Signal Timing 1.1 V Core 1.2 V Core Unit Min Max — — 12.5 Characteristics Min 2 1.6 3 Max — — 11 ns ns ns ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising edge set-up time ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold time ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. 1.6 1.6 3 ETHREF_CLK 806 ETHCRS_DV ETHRXD[0–1] ETHRX_ER 807 Valid 811 ETHTX_EN ETHTXD[0–1] Valid Valid Figure 2-19. RMII Mode Signal Timing MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-23 Specifications 2.5.10.4 SMII Mode Table 2-26. No. 808 809 810 SMII Mode Signal Timing Min 1.0 1.0 1.51 1.51 Characteristics ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay • 1.1 V core. • 1.2 V core. 1. 2. Measured using a 5 pF load. Measured using a 15 pF load. Max — — 6.02 5.02 Unit ns ns ns ns Notes: ETHCLOCK 808 ETHSYNC_IN ETHRXD 809 Valid 810 ETHSYNC ETHTXD Valid Valid Figure 2-20. SMII Mode Signal Timing 2.5.11 GPIO Timing Table 2-27. No. 601 602 603 604 605 GPIO Timing Ref = CLKIN Ref = CLKOUT (1.2 V only) Min — 1.3 — 3.7 0.5 Characteristics Min REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid (GPIO out hold time) REFCLK edge to high impedance on GPIO out GPIO in valid to REFCLK edge (GPIO in set-up time) REFCLK edge to GPIO in not valid (GPIO in hold time) — 1.1 — 3.5 0.5 Unit ns ns ns ns ns Max 6.1 — 5.4 — — Max 6.9 — 6.2 — — MSC8122 Technical Data, Rev. 13 2-24 Freescale Semiconductor AC Timings REFCLK 601 603 GPIO (Output) High Impedance 602 604 GPIO (Input) 605 Valid Figure 2-21. GPIO Timing 2.5.12 EE Signals Table 2-28. Number 65 66 Notes: 1. 2. EE Pin Timing Type Asynchronous Synchronous to Core clock Characteristics EE0 (input) EE1 (output) Min 4 core clock periods 1 core clock period The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Refer to Table 1-4 on page 1-6 for details on EE pin functionality. Figure 2-22 shows the signal behavior of the EE pins. 65 EE0 in 66 EE1 out Figure 2-22. EE Pin Timing 2.5.13 JTAG Signals Table 2-29. No. 700 701 702 JTAG Timing All frequencies Min Max 25 — — — 3.0 MHz ns ns ns ns Characteristics TCK frequency of operation (1/(TC × 4); maximum 25 MHz) TCK cycle time TCK clock pulse width measured at VM = 1.6 V • High • Low TCK rise and fall times Unit 0.0 40.0 20.0 16.0 0.0 703 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-25 Specifications Table 2-29. No. 704 705 706 707 708 709 710 711 712 713 Note: Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low JTAG Timing (Continued) All frequencies Min 5.0 20.0 0.0 0.0 5.0 20.0 0.0 0.0 100.0 30.0 Characteristics Unit ns ns ns ns ns ns ns ns ns ns Max — — 30.0 30.0 — — 20.0 20.0 — — All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. 701 702 TCK (Input) VIH 703 VM VIL 703 VM Figure 2-23. Test Clock Input Timing Diagram TCK (Input) VIH VIL 704 705 Data Inputs 706 Data Outputs 707 Data Outputs Input Data Valid Output Data Valid Figure 2-24. Boundary Scan (JTAG) Timing Diagram MSC8122 Technical Data, Rev. 13 2-26 Freescale Semiconductor AC Timings TCK (Input) TDI TMS (Input) VIH VIL 708 Input Data Valid 710 709 TDO (Output) 711 TDO (Output) Output Data Valid Figure 2-25. TCK (Input) 713 TRST (Input) 712 Test Access Port Timing Diagram Figure 2-26. TRST Timing Diagram MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-27 Specifications MSC8122 Technical Data, Rev. 13 2-28 Freescale Semiconductor Packaging 3 This section provides information on the MSC8122 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8122 is available in a 431-pin flip chipplastic ball grid array (FC-PBGA). 3.1 Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the package, including pinouts. To conform to JEDEC requirements, the package is based on a 23 × 23 position (20 × 20 mm) layout with the outside perimeter depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, and CHIP_ID[0–3]) are not shown in these figures if there is another signal assigned to the pin after reset. Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second functions (BADDR[29–31], DP[1–7], and INT_OUT) are used. Table 3-1 lists the MSC8122 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). Note: For Ethernet signals multiplexed with the DSI/system Bus (MII and RMII modes only), signals not used by the RMII mode are reserved when the Ethernet controller is multiplexed with the DSI/system bus and RMII mode is selected. These reserved signals can be left unconnected. These RMII reserved signals are not included in Table 3-1, but are indicated in Table 3-2. Note: For Ethernet signals multiplexed with the GPIO/TDM signals, signals not used by the RMII or SMII mode can be assigned to their alternate GPIO or dedicated function, except for GPIO10 and GPIO14. If the Ethernet controller is enabled and multiplexed with the GPIO signals and SMII mode is selected, GPIO10 and GPIO14 (E21 and F21, respectively) must be left unconnected. These signals are designated as NC (no connect) in Table 3-1 and Table 3-2. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-1 Packaging Top View 2 B 3 VDD 4 GND 5 GND 6 NMI_ OUT 7 GND 8 VDD 9 GND 10 VDD 11 GND 12 VDD 13 GND 14 VDD 15 GND 16 VDD 17 GND 18 VDD 19 GPIO0 20 VDD 21 VDD 22 GND C GND VDD TDO S GPIO28 HCID1 RESET GND VDD GND VDD GND VDD GND GND GPIO30 GPIO2 GPIO1 GPIO7 GPIO3 GPIO5 GPIO6 D TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31 GPIO29 VDDH GPIO4 VDDH GND GPIO8 E TCK TRST TMS HRESET GPIO27 HCID0 GND VDD GND VDD GND VDD GND GND VDD GND GND GPIO9 GPIO13 GPIO10 GPIO12 F PO RESET RST CONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_ ETHTX_ GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19 CLK CLK ETHCR S G HA24 HA27 HA25 HA23 HA17 PWE0 VDD VDD BADDR 31 BM0 ABB VDD INT_ OUT VDD CS1 BCTL0 GPIO15 GND GPIO17 GPIO22 H HA20 HA28 VDD HA19 TEST PSD CAS PGTA VDD BM1 ARTRY AACK DBB HTA VDD TT4 CS4 GPIO24 GPIO21 VDD VDDH A31 J HA18 HA26 VDD HA13 GND PSDA BADDR MUX 27 BADDR 30 VDD CLKIN BM2 DBG VDD GND VDD TT3 PSDA10 BCTL1 GPIO23 GND GPIO25 A30 K HA15 HA21 HA16 PWE3 PWE1 POE Res. GND GND GND GND CLKOUT VDD TT2 ALE CS2 GND A26 A29 A28 L HA12 HA14 HA11 VDDH VDDH BADDR BADDR 28 29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 M 81 SC HB RST M HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH VDDH VDDH GND VDDH A24 A21 22 N HD26 HD30 HD29 HD24 PWE2 VDDH HWBS 0 HBCS GND GND HRDS BG HCS CS0 PSDWE GPIO26 A23 A20 P HD20 HD27 HD25 HD23 HWBS 3 HWBS 6 HWBS 7 HWBS 2 HWBS 4 HWBS 5 HWBS HCLKIN 1 GND GNDSYN VCCSYN GND GND TA BR TEA PSD VAL DP0 VDDH GND A19 R HD18 VDDH GND HD22 TSZ1 TSZ3 GBL VDD VDD VDD TT0 DP7 DP6 DP3 TS DP2 A17 A18 A16 T HD17 HD21 HD1 HD0 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 DP5 DP4 DP1 D30 GND A15 A14 U HD16 HD19 HD2 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13 V HD3 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 W HD6 HD5 HD4 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40 VDDH HD33 VDDH HD32 GND GND A7 A6 Y HD7 HD15 VDDH HD9 VDD HD60 HD58 GND VDDH HD51 GND VDDH HD43 GND VDDH GND HD37 HD34 VDDH A4 A5 AA VDD HD14 HD12 HD10 HD63 HD59 GND VDDH HD54 HD52 VDDH GND VDDH HD46 GND HD42 HD38 HD35 A0 A2 A3 AB GND HD13 HD11 HD8 HD62 HD61 HD57 HD56 HD55 HD53 HD50 HD49 HD48 HD47 HD45 HD44 HD41 HD39 HD36 A1 VDD Figure 3-1. MSC8122 Package, Top View MSC8122 Technical Data, Rev. 13 3-2 Freescale Semiconductor Package Description Bottom View 22 B GND 21 VDD 20 VDD 19 GPIO0 18 VDD 17 GND 16 VDD 15 GND 14 VDD 13 GND 12 VDD 11 GND 10 VDD 9 GND 8 VDD 7 GND 6 NMI_ OUT 5 GND 4 GND 3 VDD 2 C GPIO6 GPIO5 GPIO3 GPIO7 GPIO1 GPIO2 GPIO30 GND GND VDD GND VDD GND VDD GND HCID1 GPIO28 S RESET TDO VDD GND D GPIO8 GND VDDH GPIO4 VDDH GPIO29 GPIO31 VDD VDD GND VDD GND VDD GND HCID3 HCID2 VDDH GND EE1 EE0 TDI E GPIO12 GPIO10 GPIO13 GPIO9 GND GND VDD GND GND VDD GND VDD GND VDD GND HCID0 GPIO27 HRESET TMS TRST TCK F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20 ETHTX_ ETHRX_ CLK CLK ETHCR S VDD GND VDD GND VDD VDD VDD GND HA22 HA29 NMI RST CONF PO RESET G GPIO22 GPIO17 GND GPIO15 BCTL0 CS1 VDD INT_ OUT VDD ABB BM0 BADDR 31 VDD VDD PWE0 HA17 HA23 HA25 HA27 HA24 H A31 VDDH VDD GPIO21 GPIO24 CS4 TT4 VDD HTA DBB AACK ARTRY BM1 VDD PGTA PSD CAS TEST HA19 VDD HA28 HA20 J A30 GPIO25 GND GPIO23 BCTL1 PSDA10 TT3 VDD GND VDD DBG BM2 CLKIN VDD BADDR PSDA 27 MUX BADDR 30 GND HA13 VDD HA26 HA18 K A28 A29 A26 GND CS2 ALE TT2 VDD CLKOUT GND GND GND GND Res. POE PWE1 PWE3 HA16 HA21 HA15 L A22 A25 A27 VDDH CS3 GND GND VDDH GND GND GND BADDR BADDR 29 28 VDDH VDDH HA11 HA14 HA12 M A21 A24 VDDH GND VDDH VDDH HB RST SC 81 22 VDDH GND GND VDDH VDD GND GND GND VDDH HD31 HD28 M N A20 A23 GPIO26 PSDWE CS0 HCS BG HRDS GND GND HBCS HWBS 0 HWBS 1 VDDH PWE2 HD24 HD29 HD30 HD26 P A19 GND VDDH DP0 PSD VAL TEA BR TA GND GND VCCSYN GNDSYN GND HCLKIN HWBS 2 HWBS 4 HWBS 5 HWBS 3 HWBS 6 HWBS 7 HD23 HD25 HD27 HD20 R A16 A18 A17 DP2 TS DP3 DP6 DP7 TT0 VDD VDD VDD GBL TSZ3 TSZ1 HD22 GND VDDH HD18 T A14 A15 GND D30 DP1 DP4 DP5 D23 D21 TT1 D16 VDD TBST TSZ2 TSZ0 HD0 HD1 HD21 HD17 U A13 A12 VDDH D31 D28 D26 D25 D22 D19 D17 D15 D14 D11 D9 D8 D6 D3 D2 HD2 HD19 HD16 V A11 A10 A9 A8 D29 D27 D24 GND D20 D18 D13 D12 D10 D7 D5 D4 D1 D0 GND VDDH HD3 W A6 A7 GND GND HD32 VDDH HD33 VDDH HD40 GND VDDH HDST0 HDST1 GND VDDH VDDH GND GND HD4 HD5 HD6 Y A5 A4 VDDH HD34 HD37 GND VDDH GND HD43 VDDH GND HD51 VDDH GND HD58 HD60 VDD HD9 VDDH HD15 HD7 AA A3 A2 A0 HD35 HD38 HD42 GND HD46 VDDH GND VDDH HD52 HD54 VDDH GND HD59 HD63 HD10 HD12 HD14 VDD AB VDD A1 HD36 HD39 HD41 HD44 HD45 HD47 HD48 HD49 HD50 HD53 HD55 HD56 HD57 HD61 HD62 HD8 HD11 HD13 GND Figure 3-2. MSC8122 Package, Bottom View MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-3 Packaging Table 3-1. Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK ABB ALE ARTRY MSC8122 Signal Listing By Name Location Designator AA20 AB21 AA21 AA22 Y21 Y22 W22 W21 V19 V20 V21 V22 U21 U22 T22 T21 R22 R20 R21 P22 N22 M22 L22 N21 M21 L21 K20 L20 K22 K21 J22 H22 H12 G12 K17 H11 Signal Name BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BM0 BM1 BM2 BR CHIP_ID0 CHIP_ID1 CHIP_ID2 CHIP_ID3 CLKIN CLKOUT CNFGS CS0 CS1 CS2 CS3 CS4 CS5 CS5 CS6 CS7 D0 D1 D2 D3 D4 Location Designator J8 L7 L8 K8 G10 G18 J18 N16 G11 H10 J11 G11 H10 J11 P16 B19 C18 C17 D17 J10 K14 W3 N18 G17 K18 L18 H17 K16 J18 J16 H16 V5 V6 U5 U6 V7 MSC8122 Technical Data, Rev. 13 3-4 Freescale Semiconductor Package Description Table 3-1. Signal Name D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 MSC8122 Signal Listing By Name (Continued) Location Designator V8 U7 V9 U8 U9 V10 U10 V11 V12 U11 U12 T12 U13 V13 U14 V14 T14 U15 T15 V16 U16 U17 V17 U18 V18 T19 U19 W18 W16 Y19 AA19 AB20 Y18 AA18 AB19 W14 Signal Name D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK1 DACK2 DACK2 DACK3 DACK4 DBB DBG DONE1 DONE2 DP0 DP1 DP2 Location Designator AB18 AA17 Y14 AB17 AB16 AA15 AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10 AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 G21 T18 F22 R19 T17 T16 H13 J12 F19 G22 P19 T18 R19 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-5 Packaging Table 3-1. Signal Name DP3 DP4 DP5 DP6 DP7 DRACK1 DRACK2 DREQ1 DREQ1 DREQ1 DREQ2 DREQ2 DREQ2 DREQ3 DREQ4 DSI64 DSISYNC EE0 EE1 ETHCLOCK ETHCOL ETHCOL ETHCRS ETHCRS_DV ETHCRS_DV ETHMDC ETHMDC ETHMDIO ETHMDIO ETHREF_CLK ETHRX_CLK ETHRX_DV ETHRX_DV ETHRX_ER ETHRX_ER ETHRXD MSC8122 Signal Listing By Name (Continued) Location Designator R17 T17 T16 R16 R15 F19 G22 E6 G19 P19 C6 F18 R17 R16 R15 U4 T4 D3 D4 F16 D22 Y7 G15 E21 AB9 E20 Y8 E19 AA7 F16 F15 E21 AB9 F20 AB8 G15 Signal Name ETHRXD0 ETHRXD0 ETHRXD1 ETHRXD1 ETHRXD2 ETHRXD2 ETHRXD3 ETHRXD3 ETHSYNC ETHSYNC_IN ETHTX_CLK ETHTX_EN ETHTX_EN ETHTX_ER ETHTX_ER ETHTXD ETHTXD0 ETHTXD0 ETHTXD1 ETHTXD1 ETHTXD2 ETHTXD2 ETHTXD3 ETHTXD3 EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 GBL GND GND GND GND GND Location Designator F21 W14 E22 AB18 C22 AA17 C21 Y14 E22 F15 F16 D17 AA10 D19 AB10 F20 B19 AA15 C18 AB15 C20 AB14 C19 AB13 T18 T16 P19 R17 R19 T17 R10 B4 B5 B7 B9 B11 MSC8122 Technical Data, Rev. 13 3-6 Freescale Semiconductor Package Description Table 3-1. Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MSC8122 Signal Listing By Name (Continued) Location Designator B13 B15 B17 B22 C2 C8 C10 C12 C14 C15 D5 D9 D11 D13 D21 E8 E10 E12 E14 E15 E17 E18 F7 F11 F13 G20 J6 J14 J20 K10 K11 K12 K13 K19 L9 L10 Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDSYN GPIO0 GPIO1 Location Designator L14 L16 L17 M5 M6 M7 M10 M14 M19 N10 N14 P10 P13 P14 P21 R4 T20 V4 V15 W5 W6 W9 W13 W19 W20 Y9 Y12 Y15 Y17 AA8 AA13 AA16 AB2 P11 B19 C18 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-7 Packaging Table 3-1. Signal Name GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 HA7 HA8 HA9 HA10 HA11 HA12 MSC8122 Signal Listing By Name (Continued) Location Designator C17 C20 D19 C21 C22 C19 D22 E19 E21 F20 E22 E20 F21 G19 F19 G21 F18 F22 F17 H19 G22 J19 H18 J21 N20 E6 C6 D17 C16 D16 R14 D8 W11 W10 L4 L2 Signal Name HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HBCS HBRST HCID0 HCID1 HCID2 HCID3 HCLKIN HCS HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 Location Designator J5 L3 K2 K4 G6 J2 H5 H2 K3 F6 G5 G2 G4 J3 G3 H3 F5 N9 M16 E7 C7 D7 D8 P9 N17 T5 T4 U4 V2 W4 W3 W2 Y2 AB5 Y5 AA5 MSC8122 Technical Data, Rev. 13 3-8 Freescale Semiconductor Package Description Table 3-1. Signal Name HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 MSC8122 Signal Listing By Name (Continued) Location Designator AB4 AA4 AB3 AA3 Y3 U2 T2 R2 U3 P2 T3 R5 P5 N5 P4 N2 P3 M2 N4 N3 M3 W18 W16 Y19 AA19 AB20 Y18 AA18 AB19 W14 AB18 AA17 Y14 AB17 AB16 AA15 Signal Name HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 HDBE0 HDBE1 HDBE2 HDBE3 HDBE4 HDBE5 HDBE6 HDBE7 HDBS0 HDBS1 HDBS2 HDBS3 HDBS4 HDBS5 HDBS6 HDBS7 HDST0 HDST1 HRDE Location Designator AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10 AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 N8 P8 P7 P6 R7 T7 R6 T6 N8 P8 P7 P6 R7 T7 R6 T6 W11 W10 N15 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-9 Packaging Table 3-1. Signal Name HRDS HRESET HRW HTA HWBE0 HWBE1 HWBE2 HWBE3 HWBE4 HWBE5 HWBE6 HWBE7 HWBS0 HWBS1 HWBS2 HWBS3 HWBS4 HWBS5 HWBS6 HWBS7 INT_OUT IRQ1 IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ4 IRQ4 IRQ4 IRQ5 IRQ5 MSC8122 Signal Listing By Name (Continued) Location Designator N15 E5 N15 H14 N8 P8 P7 P6 R7 T7 R6 T6 N8 P8 P7 P6 R7 T7 R6 T6 G14 C20 R10 T18 D19 K8 R19 C21 G10 R17 B19 C22 G12 T17 C18 C19 Signal Name IRQ5 IRQ5 IRQ5 IRQ6 IRQ6 IRQ6 IRQ7 IRQ7 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 MODCK1 MODCK2 NC NC NMI NMI_OUT PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 Location Designator H13 L8 T16 C17 D22 R16 E19 G14 R15 E21 F20 E22 E20 F21 J19 H18 J21 V2 W4 E21 F21 F4 B6 G7 K6 N6 K5 R7 T7 R6 T6 J17 N19 K7 H7 H8 MSC8122 Technical Data, Rev. 13 3-10 Freescale Semiconductor Package Description Table 3-1. Signal Name PGPL5 PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 PUPMWAIT Reserved RSTCONF SCL SDA SRESET SWTE TA TBST MSC8122 Signal Listing By Name (Continued) Location Designator J7 H8 K7 F2 H8 J17 J7 H7 G7 K6 N6 K5 R7 T7 R6 T6 K7 P18 N19 G7 K6 N6 K5 R7 T7 R6 T6 H8 K9 F3 D16 C16 C5 T5 P15 T10 Signal Name TC0 TC1 TC2 TCK TDI TDM0RCLK TDM0RDAT TDM0RSYN TDM0TCLK TDM0TDAT TDM0TSYN TDM1RCLK TDM1RDAT TDM1RSYN TDM1TCLK TDM1TDAT TDM1TSYN TDM2RCLK TDM2RDAT TDM2RSYN TDM2TCLK TDM2TDAT TDM2TSYN TDM3RCLK TDM3RDAT TDM3RSYN TDM3TCLK TDM3TDAT TDM3TSYN TDO TEA TEST TIMER0 TIMER1 TIMER2 TIMER3 Location Designator G11 H10 J11 E2 D2 J21 N20 H18 G22 J19 H19 F22 F17 F18 F19 G21 G19 E20 F21 E22 E21 F20 E19 C19 D22 C22 D19 C21 C20 C4 P17 H6 C18 C17 C16 D16 MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-11 Packaging Table 3-1. Signal Name TMCLK TMS TRST TS TSZ0 TSZ1 TSZ2 TSZ3 TT0 TT1 TT2 TT3 TT4 URXD UTXD VCCSYN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD MSC8122 Signal Listing By Name (Continued) Location Designator C16 E4 E3 R18 T8 R8 T9 R9 R14 T13 K16 J16 H16 E6 C6 P12 B8 B10 B12 B14 B16 B18 B20 B21 C3 C9 C11 C13 D10 D12 D14 D15 E9 E11 E13 E16 Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH Location Designator F8 F9 F10 F12 F14 G8 G9 G13 G16 H4 H9 H15 H20 J4 J9 J13 J15 K15 M8 R11 R12 R13 T11 Y6 AA2 B3 AB22 D6 D18 D20 H21 L5 L6 L15 L19 M4 MSC8122 Technical Data, Rev. 13 3-12 Freescale Semiconductor Package Description Table 3-1. Signal Name VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH MSC8122 Signal Listing By Name (Continued) Location Designator M9 M15 M17 M18 M20 N7 P20 R3 U20 V3 W7 W8 Signal Name VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH Location Designator W12 W15 W17 Y4 Y10 Y13 Y16 Y20 AA9 AA12 AA14 Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed several times. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-13 Packaging Table 3-2. Des. B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 MSC8122 Signal Listing by Ball Designator Des. C18 C19 C20 C21 C22 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 Signal Name VDD GND GND NMI_OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0/CHIP_ID0/IRQ4/ETHTXD0 VDD VDD GND GND VDD TDO SRESET GPIO28/UTXD/DREQ2 HCID1 GND VDD GND VDD GND VDD GND GND GPIO30/TIMER2/TMCLK/SDA GPIO2/TIMER1/CHIP_ID2/IRQ6 Signal Name GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 TDI EE0 EE1 GND VDDH HCID2 HCID3/HA8 GND VDD GND VDD GND VDD VDD GPIO31/TIMER3/SCL GPIO29/CHIP_ID3/ETHTX_EN VDDH GPIO4/TDM3TCLK/IRQ2/ETHTX_ER VDDH GND GPIO8/TDM3RDAT/IRQ6/ETHCOL TCK TRST TMS HRESET GPIO27/URXD/DREQ1 HCID0 GND VDD GND VDD MSC8122 Technical Data, Rev. 13 3-14 Freescale Semiconductor Package Description Table 3-2. Des. E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G2 G3 G4 G5 MSC8122 Signal Listing by Ball Designator (Continued) Des. G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 Signal Name GND VDD GND GND VDD GND GND GPIO9/TDM2TSYN/IRQ7/ETHMDIO GPIO13/TDM2RCLK/IRQ11/ETHMDC GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC PORESET RSTCONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD ETHRX_CLK/ETHSYNC_IN ETHTX_CLK/ETHREF_CLK/ETHCLOCK GPIO20/TDM1RDAT GPIO18/TDM1RSYN/DREQ2 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC GPIO19/TDM1RCLK/DACK2 HA24 HA27 HA25 HA23 Signal Name HA17 PWE0/PSDDQM0/PBS0 VDD VDD IRQ3/BADDR31 BM0/TC0/BNKSEL0 ABB/IRQ4 VDD IRQ7/INT_OUT ETHCRS/ETHRXD VDD CS1 BCTL0 GPIO15/TDM1TSYN/DREQ1 GND GPIO17/TDM1TDAT/DACK1 GPIO22/TDM0TCLK/DONE2/DRACK2 HA20 HA28 VDD HA19 TEST PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS VDD BM1/TC1/BNKSEL1 ARTRY AACK DBB/IRQ5 HTA VDD TT4/CS7 CS4 GPIO24/TDM0RSYN/IRQ14 GPIO21/TDM0TSYN VDD MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-15 Packaging Table 3-2. Des. H21 H22 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 MSC8122 Signal Listing by Ball Designator (Continued) Des. K15 K16 K17 K18 K19 K20 K21 K22 L2 L3 L4 L5 L6 L7 L8 L9 L10 L14 L15 L16 L17 L18 L19 L20 L21 L22 M2 M3 M4 M5 M6 M7 M8 M9 M10 M14 Signal Name VDDH A31 HA18 HA26 VDD HA13 GND PSDAMUX/PGPL5 BADDR27 VDD CLKIN BM2/TC2/BNKSEL2 DBG VDD GND VDD TT3/CS6 PSDA10/PGPL0 BCTL1/CS5 GPIO23/TDM0TDAT/IRQ13 GND GPIO25/TDM0RCLK/IRQ15 A30 HA15 HA21 HA16 PWE3/PSDDQM3/PBS3 PWE1/PSDDQM1/PBS1 POE/PSDRAS/PGPL2 IRQ2/BADDR30 Reserved GND GND GND GND CLKOUT Signal Name VDD TT2/CS5 ALE CS2 GND A26 A29 A28 HA12 HA14 HA11 VDDH VDDH BADDR28 IRQ5/BADDR29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 HD28 HD31 VDDH GND GND GND VDD VDDH GND GND MSC8122 Technical Data, Rev. 13 3-16 Freescale Semiconductor Package Description Table 3-2. Des. M15 M16 M17 M18 M19 M20 M21 M22 N2 N3 N4 N5 N6 N7 N8 N9 N10 N14 N15 N16 N17 N18 N19 N20 N21 N22 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 MSC8122 Signal Listing by Ball Designator (Continued) Des. P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T2 T3 T4 T5 Signal Name VDDH HBRST VDDH VDDH GND VDDH A24 A21 HD26 HD30 HD29 HD24 PWE2/PSDDQM2/PBS2 VDDH HWBS0/HDBS0/HWBE0/HDBE0 HBCS GND GND HRDS/HRW/HRDE BG HCS CS0 PSDWE/PGPL1 GPIO26/TDM0RDAT A23 A20 HD20 HD27 HD25 HD23 HWBS3/HDBS3/HWBE3/HDBE3 HWBS2/HDBS2/HWBE2/HDBE2 HWBS1/HDBS1/HWBE1/HDBE1 HCLKIN GND GNDSYN Signal Name VCCSYN GND GND TA BR TEA PSDVAL DP0/DREQ1/EXT_BR2 VDDH GND A19 HD18 VDDH GND HD22 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4 TSZ1 TSZ3 IRQ1/GBL VDD VDD VDD TT0/HA7 IRQ7/DP7/DREQ4 IRQ6/DP6/DREQ3 IRQ3/DP3/DREQ2/EXT_BR3 TS IRQ2/DP2/DACK2/EXT_DBG2 A17 A18 A16 HD17 HD21 HD1/DSISYNC HD0/SWTE MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-17 Packaging Table 3-2. Des. T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 MSC8122 Signal Listing by Ball Designator (Continued) Des. U21 U22 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Signal Name HWBS7/HDBS7/HWBE7/HDBE7/PWE7/PSDDQM7/PBS7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/PSDDQM5/PBS5 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23 IRQ5/DP5/DACK4/EXT_BG3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ1/DP1/DACK1/EXT_BG2 D30 GND A15 A14 HD16 HD19 HD2/DSI64 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH Signal Name A12 A13 HD3/MODCK1 VDDH GND D0 D1 D4 D5 D7 D10 D12 D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 HD6 HD5/CNFGS HD4/MODCK2 GND GND VDDH VDDH GND HDST1/HA10 HDST0/HA9 VDDH GND HD40/D40/ETHRXD0 MSC8122 Technical Data, Rev. 13 3-18 Freescale Semiconductor Package Description Table 3-2. Des. W15 W16 W17 W18 W19 W20 W21 W22 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA2 AA3 AA4 AA5 AA6 AA7 AA8 MSC8122 Signal Listing by Ball Designator (Continued) Des. AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Signal Name VDDH HD33/D33/reserved VDDH HD32/D32/reserved GND GND A7 A6 HD7 HD15 VDDH HD9 VDD HD60/D60/ETHCOL/reserved HD58/D58/ETHMDC GND VDDH HD51/D51 GND VDDH HD43/D43/ETHRXD3/reserved GND VDDH GND HD37/D37/reserved HD34/D34/reserved VDDH A4 A5 VDD HD14 HD12 HD10 HD63/D63 HD59/D59/ETHMDIO GND Signal Name VDDH HD54/D54/ETHTX_EN HD52/D52 VDDH GND VDDH HD46/D46/ETHTXT0 GND HD42/D42/ETHRXD2/reserved HD38/D38/reserved HD35/D35/reserved A0 A2 A3 GND HD13 HD11 HD8 HD62/D62 HD61/D61 HD57/D57/ETHRX_ER HD56/D56/ETHRX_DV/ETHCRS_DV HD55/D55/ETHTX_ER/reserved HD53/D53 HD50/D50 HD49/D49/ETHTXD3/reserved HD48/D48/ETHTXD2/reserved HD47/D47/ETHTXD1 HD45/D45 HD44/D44 HD41/D41/ETHRXD1 HD39/D39/reserved HD36/D36/reserved A1 VDD MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 3-19 Packaging 3.2 MSC8122 Package Mechanical Drawing Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Features are symmetrical about the package center lines unless dimensioned otherwise. 4. Maximum solder ball diameter measured parallel to Datum A. 5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 6. Parallelism measurement shall exclude any effect of mark on top surface of package. 7. Capacitors may not be present on all devices. 8. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 9. FC CBGA (Ceramic) package code: 5238. FC PBGA (Plastic) package code: 5263. 10.Pin 1 indicator can be in the form of number 1 marking or an “L” shape marking. Figure 3-3. MSC8122 Mechanical Information, 431-pin FC-PBGA Package MSC8122 Technical Data, Rev. 13 3-20 Freescale Semiconductor Design Considerations The following sections discuss areas to consider when the MSC8122 device is designed into a system. 4 4.1 Start-up Sequencing Recommendations Use the following guidelines for start-up and power-down sequences: • • Assert PORESET and TRST before applying power and keep the signals driven low until the power reaches the required minimum power levels. This can be implemented via weak pull-down resistors. CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels. • If possible, bring up VDD/VCCSYN and VDDH together. If it is not possible, raise VDD/VCCSYN first and then bring up VDDH. VDDH should not exceed VDD/VCCSYN until VDD/VCCSYN reaches its nominal voltage level. Similarly, bring both voltage levels down together. If that is not possible reverse the power-up sequence, with VDDH going down first and then VDD/VCCSYN. Note: This recommended power sequencing for the MSC8122 is different from the MSC8102. External voltage applied to any input line must not exceed the I/O supply VDDH by more than 0.8 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule. However, each such input can draw up to 80 mA per input pin per device in the system during start-up. After power-up, VDDH must not exceed VDD/VCCSYN by more than 2.6 V. 4.2 Power Supply Design Considerations When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122 Design Checklist (AN2787) for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information. Figure 4-1 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved by using the following guidelines: • For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 4-1 Design Considerations • Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-1 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount at least one of the capacitors directly below the MSC8122 device. Maximum IR drop of 15 mV at 1 A 1.2 V Power supply or Voltage Regulator Lmax = 2 cm One 0.01 µF capacitor for every 3 core supply pads. MSC8122 (Imin = 3 A) + - Bulk/Tantalum capacitors with low ESR and ESL Note: Use at least three capacitors. Each capacitor must be at least 150 μ F. High frequency capacitors (very low ESR and ESL) Figure 4-1. Core Power Supply Decoupling Each VCC and VDD pin on the MSC8122 device should have a low-impedance path to the board power supply. Similarly, each GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be minimized to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in Figure 4-2. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8122 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13. VDD 10 Ω 10nH 10 µF 0.01 µF VCCSYN Figure 4-2. VCCSYN Bypass MSC8122 Technical Data, Rev. 13 4-2 Freescale Semiconductor Connectivity Guidelines 4.3 Connectivity Guidelines Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to VDDH or GND, except for the following: • • • • • • • • If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be disconnected. When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down, depending on design requirements. HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the DCR[DSRFA] bit is set. When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/ HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7]. When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up. When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up. The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK. In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0): — BG, DBG, and TS can be left unconnected. — EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus functionality. For any other functionality, connect the signal lines based on the multiplexed functionality. — BR must be pulled up. — EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality. • If there is an external bus master (BCR[EBM] = 1): — BR, BG, DBG, and TS must be pulled up. — EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus functionality. • In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up. Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set). • • If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the available clock modes. In the CLKIN synchronization mode, use the following connections: — Connect the oscillator output through a buffer to CLKIN. — Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay path between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100 ps). — Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31. MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 4-3 Design Considerations • In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the following connections: — Connect the oscillator output through a buffer to CLKIN. — Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following guidelines: • • • The maximum delay between the slave and CLKOUT must not exceed 0.7 ns. The maximum load on CLKOUT must not exceed 10 pF. Use a zero-delay buffer with a jitter less than 0.3 ns. — All clock modes are valid in this clock scheme. Note: See the Clock chapter in the MSC8122 Reference Manual for details. • • If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected. Otherwise, it should be pulled up. The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal. When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive) signals must be pulled up. When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be connected externally to any signal line. • • Note: For details on configuration, see the MSC8122 User’s Guide and MSC8122 Reference Manual. For additional information, refer to the MSC8122 Design Checklist (AN2787). 4.4 External SDRAM Selection The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by the SDRAM manufacturer. MSC8122 Technical Data, Rev. 13 4-4 Freescale Semiconductor Thermal Considerations 4.5 Thermal Considerations An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following: TJ = TA + (RθJA × PD) where Equation 1 TA = ambient temperature near the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD × VDD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8122 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8122 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ: TJ = TT + (θJA × PD) Equation 2 where TT = thermocouple (or infrared) temperature on top of the package (°C) θJA = thermal characterization parameter (°C/W) PD = power dissipation in the package (W) Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601/D). MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 4-5 Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Core Voltage 1.1 V 1.2 V Part MSC8122 Package Type Flip Chip Plastic Ball Grid Array (FC-PBGA) Operating Temperature –40° to 105°C –40° to 105°C 0° to 90°C Core Frequency (MHz) 300 400 400 500 Order Number Lead-Free MSC8122TVT4800V MSC8122TVT6400V MSC8122TVT6400 MSC8122VT8000 Lead-Bearing MSC8122TMP4800V MSC8122TMP6400V MSC8122TMP6400 MSC8122MP8000 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GMBH Technical Information Center Schatzbogen 7 81829 München, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MSC8122 Rev. 13 10/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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