MSC8254

Freescale Semiconductor Data Sheet: Product Preview Document Number: MSC8254 Rev. 2, 12/2010 MSC8254 Quad-Core Digital Signal Processor • Four StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. • Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. • 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. • 96 Kbyte boot ROM. • Three input clocks (one global and two differential). • Five PLLs (three global and two Serial RapidIO PLLs). • Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. • DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. FC-PBGA–783 29 mm × 29 mm • High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to 3.125 Gbaud with a single messaging unit and two DMA units. The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. • QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI. • I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT, NMI_OUT, and the cores. • UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. • Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT). • Eight programmable hardware semaphores. • Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. • I2C interface. • Up to 32 GPIO ports, sixteen of which can be configured as external interrupts. • Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI. • Supports standard JTAG interface • Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry. • 45 nm SOI CMOS technology. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2008, 2010 Freescale Semiconductor, Inc. Table of Contents 1 2 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagram. . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .24 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 CLKIN Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .26 2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .37 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .53 3.1 Power Supply Ramp-Up Sequence . . . . . . . . . . . . . . .53 3.2 PLL Power Supply Design Considerations . . . . . . . . . .56 3.3 Clock and Timing Signal Board Layout Considerations 57 3.4 SGMII AC-Coupled Serial Link Connection Example . .58 3.5 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .58 3.6 Guide to Selecting Connections for Remote Power Supply Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Figure 10.SGMII Transmitter DC Measurement Circuit . . . . . . . . . 34 Figure 11.DDR2 and DDR3 SDRAM Interface Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 12.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 40 Figure 14.DDR2 and DDR3 Controller Bus AC Test Load. . . . . . . 40 Figure 15.DDR2 and DDR3 SDRAM Differential Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 16.Differential Measurement Points for Rise and Fall Time 42 Figure 17.Single-Ended Measurement Points for Rise and Fall Time Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 18.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 44 Figure 19.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 45 Figure 20.TDM Receive Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21.TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22.TDM AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 23.Timer AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 48 Figure 25.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 49 Figure 26.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 27.SPI AC Timing in Slave Mode (External Clock). . . . . . . 50 Figure 28.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 50 Figure 29.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 30.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 52 Figure 31.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 32.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 33.Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO . . . . . . . . . . . . . 53 Figure 34.Supply Ramp-Up Sequence . . . . . . . . . . . . . . . . . . . . . 54 Figure 35.Reset Connection in Functional Application . . . . . . . . . 56 Figure 36.Reset Connection in Debugger Application. . . . . . . . . . 56 Figure 37.PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 38.SerDes PLL Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 42.4-Wire AC-Coupled SGMII Serial Link Connection Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 40.MSC8254 Mechanical Information, 783-ball FC-PBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3 4 5 6 7 List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. MSC8254 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 StarCore SC3850 DSP Subsystem Block Diagram . . . . 3 MSC8254 FC-PBGA Package, Top View . . . . . . . . . . . . 4 Differential Voltage Definitions for Transmitter or Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 30 SerDes Transmitter and Receiver Reference Circuits . 31 Differential Reference Clock Input DC Requirements (External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 31 Differential Reference Clock Input DC Requirements (External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32 Single-Ended Reference Clock Input DC Requirements 32 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 2 Freescale Semiconductor DDR Interface 64/32-bit JTAG DDR Controller DDR Interface 64/32-bit DDR Controller M3 Memory 1056 Kbyte I/O-Interrupt Concentrator UART Clocks CLASS High-Speed Serial Interface SC3850 DSP Core 32 Kbyte 32 Kbyte L1 L1 ICache DCache 512 Kbyte L2 Cache / M2 Memory Timers Reset DMA RMU SGMII SPI Ethernet Ethernet QUICCEngine Subsystem Dual RISC Processors DMA Semaphores Virtual Interrupts Boot ROM I2C Other Modules 4 TDMs Serial Serial PCI RapidIO RapidIO Expr Four DSP Cores at 1 GHz or 800 MHz Four TDMs 256-Channels each SPI RGMII RGMII Note: The arrow direction indicates master or slave. 128 bits master bus to CLASS 512 Kbyte L2 Cache / M2 Memory IQBus TWB DMA x2 SerDes 1 SerDes 2 4x 3.125 Gbaud PCI-EX 1x/2x/4x Two SGMII 4x 3.125 Gbaud Two SGMII Figure 1. MSC8254 Block Diagram 128 bits slave bus from CLASS Interrupts EPIC Timer DQBus Task Protection Debug Support OCE30 DPU 32 Kbyte Instruction Cache WriteThrough Buffer (WTB) 32 Kbyte Data Cache WriteBack Buffer Address Translation MMU (WBB) SC3850 Core P-bus 128 bit Xa-bus 64 bit Xb-bus 64-bit Figure 2. StarCore SC3850 DSP Subsystem Block Diagram MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 3 Pin Assignment 1 Pin Assignment This section includes diagrams of the MSC8254 package ball grid array layouts and tables showing how the pinouts are allocated for the package. 1.1 FC-PBGA Ball Layout Diagram The top view of the FC-PBGA package is shown in Figure 3 with the ball location index numbers. Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MSC8254 Figure 3. MSC8254 FC-PBGA Package, Top View MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 4 Freescale Semiconductor 1.2 Signal List By Ball Location Table 1 presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the related signal functions are used (active) Note: The information in Table 1 and Table 2 distinguishes among three concepts. First, the power pins are the balls of the device package used to supply specific power levels for different device subsystems (as opposed to signals). Second, the power rails are the electrical lines on the board that transfer power from the voltage regulators to the device. They are indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as N/A with regard to the power rails. Third, symbols used in these tables are the names for the voltage levels (absolute, recommended, and so on) and not the power supplies themselves. Table 1. Signal List by Ball Number Ball Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 B1 B2 B3 B4 B5 B6 B7 B8 M2DQS3 M2DQS3 M2ECC0 M2DQS8 M2DQS8 M2A5 M2CK1 M2CK1 M2CS0 M2BA0 M2CAS M2DQ34 M2DQS4 M2DQS4 M2DQ50 M2DQS6 M2DQS6 M2DQ48 M2DQ49 VSS Reserved SXPVDD1 SXPVSS1 Reserved Reserved SXCVDD1 SXCVSS1 M2DQ24 GVDD2 M2DQ25 VSS GVDD2 M2ECC1 VSS GVDD2 Signal Name1,2 Pin Type10 I/O I/O I/O I/O I/O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Ground NC Power Ground NC NC Power Ground I/O Power I/O Ground Power I/O Ground Power Power Rail Name GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 N/A — N/A N/A — — N/A N/A GVDD2 N/A GVDD2 N/A N/A GVDD2 N/A N/A MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 5 Table 1. Signal List by Ball Number (continued) Ball Number B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 M2A13 VSS GVDD2 M2CS1 VSS GVDD2 M2DQ35 VSS GVDD2 M2DQ51 VSS GVDD2 Reserved Reserved SR1_TXD0 SR1_TXD0 SXCVDD1 SXCVSS1 SR1_RXD0 SR1_RXD0 M2DQ28 M2DM3 M2DQ26 M2ECC4 M2DM8 M2ECC2 M2CKE1 M2CK0 M2CK0 M2BA1 M2A1 M2WE M2DQ37 M2DM4 M2DQ36 M2DQ32 M2DQ55 M2DM6 M2DQ53 M2DQ52 Reserved SR1_IMP_CAL_RX SXPVSS1 SXPVDD1 SR1_REF_CLK SR1_REF_CLK Signal Name1,2 Pin Type10 O Ground Power O Ground Power I/O Ground Power I/O Ground Power NC NC O O Power Ground I I I/O O I/O I/O O I/O O O O O O O I/O O I/O I/O I/O O I/O I/O NC I Ground Power I I Power Rail Name GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A — — SXPVDD1 SXPVDD1 N/A N/A SXCVDD1 SXCVDD1 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 — SXCVDD1 N/A N/A SXCVDD1 SXCVDD1 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 6 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number C27 C28 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 Reserved Reserved GVDD2 VSS M2DQ29 GVDD2 VSS M2ECC5 GVDD2 VSS M2A8 GVDD2 VSS M2A0 GVDD2 VSS M2DQ39 GVDD2 VSS M2DQ54 GVDD2 VSS SXPVSS1 SXPVDD1 SR1_TXD1 SR1_TXD1 SXCVSS1 SXCVDD1 SR1_RXD1 SR1_RXD1 M2DQ31 M2DQ30 M2DQ27 M2ECC7 M2ECC6 M2ECC3 M2A9 M2A6 M2A3 M2A10 M2RAS M2A2 M2DQ38 M2DQS5 M2DQS5 M2DQ33 Signal Name1,2 Pin Type10 NC NC Power Ground I/O Power Ground I/O Power Ground O Power Ground O Power Ground I/O Power Ground I/O Power Ground Ground Power O O Ground Power I I I/O I/O I/O I/O I/O I/O O O O O O O I/O I/O I/O I/O Power Rail Name — — N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A N/A N/A SXPVDD1 SXPVDD1 N/A N/A SXCVDD1 SXCVDD1 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 7 Table 1. Signal List by Ball Number (continued) Ball Number E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 G1 G2 G3 G4 G5 G6 M2DQ56 M2DQ57 M2DQS7 Reserved Reserved Reserved SXPVDD1 SXPVSS1 SR1_PLL_AGND9 SR1_PLL_AVDD9 SXCVSS1 SXCVDD1 VSS GVDD2 M2DQ16 VSS GVDD2 M2DQ17 VSS GVDD2 M2BA2 VSS GVDD2 M2A4 VSS GVDD2 M2DQ42 VSS GVDD2 M2DQ58 M2DQS7 GVDD2 SXPVDD1 SXPVSS1 SR1_TXD2/SG1_TX SXCVDD1 SXCVSS1 SR1_RXD2/SG1_RX4 SR1_RXD2/SG1_RX4 M2DQS2 M2DQS2 M2DQ19 M2DM2 M2DQ21 M2DQ22 4 Signal Name1,2 Pin Type10 I/O I/O I/O NC NC NC Power Ground Ground Power Ground Power Ground Power I/O Ground Power I/O Ground Power O Ground Power O Ground Power I/O Ground Power I/O I/O Power Power Ground O O Ground Power I I I/O I/O I/O O I/O I/O Power Rail Name GVDD2 GVDD2 GVDD2 — — — N/A N/A SXCVSS1 SXCVDD1 N/A N/A N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 GVDD2 N/A N/A N/A SXPVDD1 SXPVDD1 N/A N/A SXCVDD1 SXCVDD1 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 SR1_TXD2/SG1_TX4 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 8 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 M2CKE0 M2A11 M2A7 M2CK2 M2APAR_OUT M2ODT1 M2APAR_IN M2DQ43 M2DM5 M2DQ44 M2DQ40 M2DQ59 M2DM7 M2DQ60 Reserved Reserved SXPVSS1 SXPVDD1 SR1_IMP_CAL_TX SXCVSS1 Reserved Reserved GVDD2 VSS M2DQ18 GVDD2 VSS M2DQ20 GVDD2 VSS M2A15 M2CK2 M2MDIC0 M2VREF M2MDIC1 M2DQ46 M2DQ47 M2DQ45 M2DQ41 M2DQ62 M2DQ63 M2DQ61 Reserved Reserved SR1_TXD3/SG2_TX4 SR1_TXD3/SG2_TX4 Signal Name1,2 Pin Type10 O O O O O O I I/O O I/O I/O I/O O I/O NC NC Ground Power I Ground NC NC Power Ground I/O Power Ground I/O Power Ground O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O NC NC O O Power Rail Name GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 — — N/A N/A SXCVDD1 N/A — — N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 — — SXPVDD1 SXPVDD1 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 9 Table 1. Signal List by Ball Number (continued) Ball Number H25 H26 H27 H28 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 SXCVSS1 SXCVDD1 SR1_RXD3/SG2_RX4 SR1_RXD3/SG2_RX4 M2DQS1 M2DQS1 M2DQ10 M2DQ11 M2DQ14 M2DQ23 M2ODT0 M2A12 M2A14 VSS GVDD2 VSS GVDD2 VSS GVDD2 VSS GVDD2 VSS GVDD2 Reserved Reserved Reserved SXPVDD1 SXPVSS1 SXCVDD1 SXCVSS1 SXCVDD1 SXCVSS1 VSS GVDD2 M2DM1 VSS GVDD2 M2DQ0 VSS GVDD2 M2DQ5 VSS VDD VSS VDD VSS Signal Name1,2 Pin Type10 Ground Power I I I/O I/O I/O I/O I/O I/O O O O Ground Power Ground Power Ground Power Ground Power Ground Power NC NC NC Power Ground Power Ground Power Ground Ground Power O Ground Power I/O Ground Power I/O Ground Power Ground Power Ground Power Rail Name N/A N/A SXCVDD1 SXCVDD1 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — N/A N/A N/A N/A N/A N/A N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A N/A N/A N/A MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 10 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 M1 M2 M3 M4 VDD VSS VSS VSS VDD Reserved Reserved Reserved SXPVDD2 SXPVSS2 SXCVDD2 SXCVSS2 SXCVDD2 SXCVSS2 M2DQ9 M2DQ12 M2DQ13 M2DQS0 M2DQS0 M2DM0 M2DQ3 M2DQ2 M2DQ4 VDD VSS M3VDD VSS VSS VSS VSS VSS VDD VSS Reserved Reserved Reserved SR2_TXD3/PE_TXD3/SG2_TX4 SR2_TXD3/PE_TXD3/SG2_TX4 SXCVSS2 SXCVDD2 SR2_RXD3/PE_RXD3/SG2_RX4 SR2_RXD3/PE_RXD3/SG2_RX4 M2DQ8 VSS GVDD2 M2DQ15 Signal Name1,2 Pin Type10 Power Ground Ground Ground Power NC NC NC Power Ground Power Ground Power Ground I/O I/O I/O I/O I/O O I/O I/O I/O Power Ground Power Ground Ground Ground Ground Ground Power Ground NC NC NC O O Ground Power I I I/O Ground Power I/O Power Rail Name N/A N/A N/A N/A N/A — — — N/A N/A N/A N/A N/A N/A GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — SXPVDD2 SXPVDD2 N/A N/A SXCVDD2 SXCVDD2 GVDD2 N/A N/A GVDD2 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 11 Table 1. Signal List by Ball Number (continued) Ball Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 M2DQ1 VSS GVDD2 M2DQ7 M2DQ6 VSS VDD VSS VDD VSS VSS VSS VSS VSS VDD Reserved Reserved Reserved SXPVSS2 SXPVDD2 SR2_IMP_CAL_TX SXCVSS2 Reserved Reserved VSS TRST7 PORESET VSS TMS7 CLKOUT VSS VSS VSS VDD VSS M3VDD VSS VSS VSS VDD VSS VDD VSS Reserved SXPVDD2 SXPVSS2 7 Signal Name1,2 Pin Type10 I/O Ground Power I/O I/O Ground Power Ground Power Ground Ground Ground Ground Ground Power NC NC NC Ground Power I Ground NC NC Ground I I Ground I O Ground Ground Ground Power Ground Power Ground Ground Ground Power Ground Power Ground NC Power Ground Power Rail Name GVDD2 N/.A N/A GVDD2 GVDD2 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — N/A N/A SXCVDD2 N/A — — N/A QVDD QVDD N/A QVDD QVDD N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — N/A N/A MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 12 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number N23 N24 N25 N26 N27 N28 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Signal Name1,2 SR2_TXD2/PE_TXD2/SG1_TX4 SR2_TXD2/PE_TXD2/SG1_TX4 SXCVDD2 SXCVSS2 SR2_RXD2/PE_RXD2/SG1_RX4 SR2_RXD2/PE_RXD2/SG1_RX4 CLKIN EE0 QVDD VSS STOP_BS QVDD VSS PLL0_AVDD9 PLL2_AVDD9 VSS VDD VSS VDD VSS VSS VSS VSS VSS VDD Reserved Reserved Reserved SXPVDD2 SXPVSS2 SR2_PLL_AGND9 SR2_PLL_AVDD9 SXCVSS2 SXCVDD2 VSS NMI NMI_OUT6 HRESET EE1 VSS PLL1_AVDD9 VSS VDD VSS VDD 6,7 Pin Type10 O O Power Ground I I I I Power Ground I Power Ground Power Power Ground Power Ground Power Ground Ground Ground Ground Ground Power NC NC NC Power Ground Ground Power Ground Power Ground I O I/O O O Ground Power Ground Power Non-user Power Power Rail Name SXPVDD2 SXPVDD2 N/A N/A SXCVDD2 SXCVDD2 QVDD QVDD N/A N/A QVDD N/A N/A VDD VDD N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — N/A N/A SXCVSS2 SXCVDD2 N/A N/A N/A QVDD QVDD QVDD QVDD QVDD N/A VDD N/A N/A N/A N/A INT_OUT6 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 13 Table 1. Signal List by Ball Number (continued) Ball Number R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 U1 U2 VSS VDD VSS VSS VSS VDD VSS VSS SXPVSS2 SXPVDD2 SR2_TXD1/PE_TXD1 SXCVSS2 SXCVDD2 SR2_RXD1/PE_RXD14 SR2_RXD1/PE_RXD14 VSS TCK SRESET6,7 TDI VSS TDO VSS VSS QVDD VSS VDD VSS M3VDD VSS VDD VSS VSS VSS VDD VSS VSS SR2_IMP_CAL_RX SXPVSS2 SXPVDD2 SR2_REF_CLK SR2_REF_CLK Reserved Reserved M1DQ8 VSS 4 Signal Name1,2 Pin Type10 Ground Power Ground Ground Ground Power Ground Non-user Ground Power O O Ground Power I I Ground I I/O I Ground Power Ground Ground Power Ground Power Ground Power Ground Power Ground Ground Ground Power Ground Non-user I Ground Power I I NC NC I/O Ground Power Rail Name N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SXPVDD2 SXPVDD2 N/A N/A SXCVDD2 SXCVDD2 N/A QVDD QVDD QVDD N/A QVDD N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SXCVDD2 N/A N/A SXCVDD2 SXCVDD2 — — GVDD1 N/A SR2_TXD1/PE_TXD14 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 14 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 GVDD1 M1DQ15 M1DQ1 VSS GVDD1 M1DQ7 M1DQ6 VDD VSS M3VDD VSS VDD VSS VDD VSS VDD VSS VSS VSS VSS SR2_TXD0/PE_TXD04 SR2_TXD0/PE_TXD04 SXCVDD2 SXCVSS2 SR2_RXD0/PE_RXD04 SR2_RXD0/PE_RXD04 M1DQ9 M1DQ12 M1DQ13 M1DQS0 M1DQS0 M1DM0 M1DQ3 M1DQ2 M1DQ4 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NVDD Signal Name1,2 Pin Type10 Power I/O I/O Ground Power I/O I/O Power Ground Power Ground Power Ground Power Ground Power Ground Ground Ground Non-user O O Power Ground I I I/O I/O I/O I/O I/O O I/O I/O I/O Ground Power Ground Power Ground Power Ground Power Ground Power Power Power Rail Name N/A GVDD1 GVDD1 N/A N/A GVDD1 GVDD1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SXPVDD2 SXPVDD2 N/A N/A SXCVDD2 SXCVDD2 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 15 Table 1. Signal List by Ball Number (continued) Ball Number V21 V22 V23 V24 V25 V26 V27 V28 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 RCW_LSEL_3/RC20 RCW_LSEL_2/RC19 SXPVDD2 SXPVSS2 RCW_LSEL_1/RC18 RC21 SXCVDD2 SXCVSS2 VSS GVDD1 M1DM1 VSS GVDD1 M1DQ0 VSS GVDD1 M1DQ5 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VSS RCW_LSEL0/RC17 GPIO19/SPI_MISO5,8 VSS NVDD GPIO11/IRQ11/RC115,8 GPIO3/DRQ1/IRQ3/RC35,8 GPIO7/IRQ7/RC7 M1DQS1 M1DQS1 M1DQ10 M1DQ11 M1DQ14 M1DQ23 M1ODT0 M1A12 M1A14 VSS 5,8 Signal Name1,2 Pin Type10 I/O I/O Power Ground I/O I Power Ground Ground Power O Ground Power I/O Ground Power I/O Power Ground Power Ground Power Ground Power Ground Power Ground Ground I/O I/O Ground Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O Ground Power Rail Name NVDD NVDD N/A N/A NVDD NVDD N/A N/A N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A NVDD NVDD N/A N/A NVDD NVDD NVDD NVDD GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 N/A GPIO2/IRQ2/RC25,8 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 16 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 GVDD1 VSS GVDD1 VSS GVDD1 VSS GVDD1 VSS GVDD1 VSS NVDD GPIO20/SPI_SL5,8 GPIO17/SPI_SCK5,8 GPIO14/DRQ0/IRQ14/RC145,8 GPIO12/IRQ12/RC125,8 GPIO8/IRQ8/RC85,8 NVDD VSS GVDD1 VSS M1DQ18 GVDD1 VSS M1DQ20 GVDD1 VSS M1A15 M1CK2 M1MDIC0 M1VREF M1MDIC1 M1DQ46 M1DQ47 M1DQ45 M1DQ41 M1DQ62 M1DQ63 M1DQ61 VSS GPIO21 5,8 Signal Name1,2 Pin Type10 Power Ground Power Ground Power Ground Power Ground Power Ground Power I/O I/O I/O I/O I/O Power Ground Power Ground I/O Power Ground I/O Power Ground O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O Ground I/O I/O I/O Power Rail Name N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A NVDD NVDD NVDD NVDD NVDD N/A N/A N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 N/A NVDD NVDD NVDD NVDD NVDD NVDD NVDD GPIO18/SPI_MOSI5,8 GPIO16/RC165,8 GPIO4/DDN1/IRQ4/RC4 GPIO9/IRQ9/RC95,8 GPIO6/IRQ6/RC65,8 GPIO1/IRQ1/RC1 5,8 5,8 I/O I/O I/O I/O MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 17 Table 1. Signal List by Ball Number (continued) Ball Number AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 M1DQS2 M1DQS2 M1DQ19 M1DM2 M1DQ21 M1DQ22 M1CKE0 M1A11 M1A7 M1CK2 M1APAR_OUT M1ODT1 M1APAR_IN M1DQ43 M1DM5 M1DQ44 M1DQ40 M1DQ59 M1DM7 M1DQ60 VSS GPIO31/I2C_SDA5,8 GPIO27/TMR4/RCW_SRC05,8 GPIO25/TMR2/RCW_SRC15,8 GPIO24/TMR1/RCW_SRC25,8 GPIO10/IRQ10/RC105,8 GPIO5/IRQ5/RC5 VSS GVDD1 M1DQ16 VSS GVDD1 M1DQ17 VSS GVDD1 M1BA2 VSS GVDD1 M1A4 VSS GVDD1 M1DQ42 VSS GVDD1 M1DQ58 5,8 Signal Name1,2 Pin Type10 I/O I/O I/O O I/O I/O O O O O O O I I/O O I/O I/O I/O O I/O Ground I/O I/O I/O I/O I/O I/O I/O Ground Power I/O Ground Power I/O Ground Power O Ground Power O Ground Power I/O Ground Power I/O Power Rail Name GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 N/A NVDD NVDD NVDD NVDD NVDD NVDD NVDD N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 GPIO0/IRQ0/RC05,8 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 18 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 VSS GVDD1 VSS NVDD GPIO30/I2C_SCL5,8 GPIO26/TMR35,8 VSS NVDD GPIO23/TMR05,8 GPIO225,8 M1DQ31 M1DQ30 M1DQ27 M1ECC7 M1ECC6 M1ECC3 M1A9 M1A6 M1A3 M1A10 M1RAS M1A2 M1DQ38 M1DQS5 M1DQS5 M1DQ33 M1DQ56 M1DQ57 M1DQS7 M1DQS7 VSS GE2_TX_CTL GPIO15/DDN0/IRQ15/RC155,8 GPIO13/IRQ13/RC135,8 GE_MDC GE_MDIO TDM2TCK/GE1_TD33 TDM2RCK/GE1_TD0 GVDD1 VSS M1DQ29 GVDD1 VSS M1ECC5 GVDD1 VSS 3 Signal Name1,2 Pin Type10 Ground Power Ground Power I/O I/O Ground Power I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Ground O I/O I/O O I/O I/O I/O Power Ground I/O Power Ground I/O Power Ground Power Rail Name N/A N/A N/A N/A NVDD NVDD N/A N/A NVDD NVDD GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 N/A NVDD NVDD NVDD NVDD NVDD NVDD NVDD N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 19 Table 1. Signal List by Ball Number (continued) Ball Number AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 M1A8 GVDD1 VSS M1A0 GVDD1 VSS M1DQ39 GVDD1 VSS M1DQ54 GVDD1 VSS GPIO29/UART_TXD5,8 TDM1TCK/GE2_RX_CLK3 TDM1RSN/GE2_RX_CTL3 VSS TDM3RCK/GE1_GTX_CLK3 TDM3TSN/GE1_RX_CLK3 TDM2RSN/GE1_TD2 M1DQ28 M1DM3 M1DQ26 M1ECC4 M1DM8 M1ECC2 M1CKE1 M1CK0 M1CK0 M1BA1 M1A1 M1WE M1DQ37 M1DM4 M1DQ36 M1DQ32 M1DQ55 M1DM6 M1DQ53 M1DQ52 GPIO28/UART_RXD5,8 TDM0RSN/GE2_TD23 TDM0TDT/GE2_TD3 NVDD TDM2TSN/GE1_TX_CTL3 GE1_RX_CTL 3 3 Signal Name1,2 Pin Type10 O Power Ground O Power Ground I/O Power Ground I/O Power Ground I/O I I/O Ground I/O I/O I/O I/O I/O O I/O I/O O I/O O O O O O O I/O O I/O I/O I/O O I/O I/O I/O I/O I/O Power I/O I Power Rail Name GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A NVDD NVDD NVDD N/A NVDD NVDD NVDD NVDD GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 NVDD NVDD NVDD N/A NVDD NVDD TDM2RDT/GE1_TD13 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 20 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number AF27 AF28 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 TDM2TDT/GE1_TX_CLK3 TDM3RSN/GE1_RD13 M1DQ24 GVDD1 M1DQ25 VSS GVDD1 M1ECC1 VSS GVDD1 M1A13 VSS GVDD1 M1CS1 VSS GVDD1 M1DQ35 VSS GVDD1 M1DQ51 VSS GVDD1 NVDD TDM1TSN/GE2_TD13 TDM1RDT/GE2_TX_CLK3 TDM0TCK/GE2_GTX_CLK3 TDM1TDT/GE2_TD0 VSS NVDD TDM3RDT/GE1_RD03 Reserved. M1DQS3 M1DQS3 M1ECC0 M1DQS8 M1DQS8 M1A5 M1CK1 M1CK1 M1CS0 M1BA0 M1CAS M1DQ34 M1DQS4 M1DQS4 M1DQ50 3 Signal Name1,2 Pin Type10 I/O I/O I/O Power I/O Ground Power I/O Ground Power O Ground Power O Ground Power I/O Ground Power I/O Ground Power Power I/O I/O I/O I/O Ground Power I/O NC I/O I/O I/O I/O I/O O O O O O O I/O I/O I/O I/O Power Rail Name NVDD NVDD GVDD1 N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A GVDD1 N/A N/A N/A NVDD NVDD NVDD NVDD N/A N/A NVDD — GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 GVDD1 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 21 Table 1. Signal List by Ball Number (continued) Ball Number AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 Notes: 1. M1DQS6 M1DQS6 M1DQ48 M1DQ49 VSS TDM0RCK/GE2_RD23 TDM0RDT/GE2_RD33 TDM0TSN/GE2_RD03 TDM1RCK/GE2_RD13 TDM3TDT/GE1_RD33 TDM3TCK/GE1_RD2 VSS 3 Signal Name1,2 Pin Type10 I/O I/O I/O I/O Ground I/O I/O I/O I/O I/O I Ground Power Rail Name GVDD1 GVDD1 GVDD1 GVDD1 N/A NVDD NVDD NVDD NVDD NVDD NVDD N/A Reserved signals should be disconnected for compatibility with future revisions of the device. Non-user signals are reserved for manufacturing and test purposes only. The assigned signal name is used to indicate whether the signal must be unconnected (Reserved), pulled down (VSS), or pulled up (VDD). 2. Signal function during power-on reset is determined by the RCW source type. 3. Selection of TDM versus RGMII functionality is determined by the RCW bit values. 4. Selection of RapidIO, SGMII, and PCI Express functionality is determined by the RCW bit values. 5. Selection of the GPIO function and other functions is done by GPIO register setup. For configuration details, see the GPIO chapter in the MSC8254 Reference Manual. 6. Open-drain signal. 7. Internal 20 KΩ pull-up resistor. 8. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register programming. See the GPIO chapter of the MSC8254 Reference Manual for configuration details. 9. Connect to power supply via external filter. See Section 3.2, PLL Power Supply Design Considerations for details. 10. Pin types are: Ground = all VSS connections; Power = all VDD connections; I = Input; O = Output; I/O = Input/Output; NC = not connected. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 22 Freescale Semiconductor Electrical Characteristics 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8254 Reference Manual. 2.1 Maximum Ratings In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8254. Table 2. Absolute Maximum Ratings Rating Core supply voltage • Cores 0–3 PLL supply voltage3 Power Rail Name VDD Symbol VDD VDDPLL0 VDDPLL1 VDDPLL2 Value –0.3 to 1.1 –0.3 to 1.1 –0.3 to 1.1 –0.3 to 1.1 –0.3 to 1.1 –0.3 to 1.98 –0.3 to 1.65 Unit V V V V V V V V M3 memory supply voltage DDR memory supply voltage • DDR2 mode • DDR3 mode DDR reference voltage M3VDD GVDD1, GVDD2 VDDM3 VDDDDR MVREF MVREF –0.3 to 0.51 × VDDDDR Input DDR voltage I/O voltage excluding DDR and RapidIO lines Input I/O voltage RapidIO pad voltage Rapid I/O core voltage SXPVDD1, SXPVDD2 SXCVDD1, SXCVDD2 NVDD, QVDD VINDDR VDDIO VINIO VDDSXP VDDSXC –0.3 to VDDDDR + 0.3 –0.3 to 2.625 –0.3 to VDDIO + 0.3 –0.3 to 1.26 –0.3 to 1.21 V V V V V Rapid I/O PLL voltage3 Input RapidIO I/O voltage Operating temperature Storage temperature range Notes: 1. 2. 3. VDDRIOPLL VINRIO TJ TSTG –0.3 to 1.21 –0.3 to VDDSXC + 0.3 –40 to 105 –55 to +150 V V °C °C Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. PLL supply voltage is specified at input of the filter and not at pin of the MSC8254 (see Figure 37 and Figure 38) MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 23 Electrical Characteristics 2.2 Recommended Operating Conditions Table 3. Recommended Operating Conditions Rating Symbol VDD VDDM3 VDDDDR 1.7 1.425 0.49 × VDDDDR 2.375 0.97 0.97 0 0 –40 — — — 4.77 4.4 1.8 1.5 0.5 × VDDDDR 2.5 1.0 1.0 1.9 1.575 0.51 × VDDDDR 2.625 1.05 1.05 90 105 — 105 — — V V V V V V °C °C °C Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Min 0.97 0.97 Nominal 1.0 1.0 Max 1.05 1.05 Unit V V Core supply voltage M3 memory supply voltage DDR memory supply voltage • DDR2 mode • DDR3 mode DDR reference voltage I/O voltage excluding DDR and RapidIO lines Rapid I/O pad voltage Rapid I/O core voltage Operating temperature range: • Standard • Higher • Extended Typical power: • 1 GHz at 1.0 V1 • 800 MHz at 1.0 V2 Notes: 1. MVREF VDDIO VDDSXP VDDSXC TJ TJ TA TJ P W W 2. The typical power values are derived for a device running under the following conditions. • Four cores running at 1 GHz, Core voltage at 1V, 75% utilization (50% control/50% DSP). • A single 64 bit DDR3 running at 800 MHz, 50% utilization (50% reads/50% writes). • M3 Memory 50% utilized, PCI Express controller disabled, TDM enabled 20% loading, Serial RapidIO controller disabled, 1 RGMII at 1 Gbps 50% loading. • A junction temperature of 60°C. The typical power values are derived for a device running under the following conditions. • Four cores running at 800 MHz, Core voltage at 1V, 75% utilization (50% control/50% DSP). • A single 64 bit DDR3 running at 800 MHz, 50% utilization (50% reads/50% writes). • M3 Memory 50% utilized, PCI Express controller disabled, TDM enabled 20% loading, Serial RapidIO controller disabled, 1 RGMII at 1 Gbps 50% loading. • A junction temperature of 60°C. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 24 Freescale Semiconductor Electrical Characteristics 2.3 Thermal Characteristics Table 4. Thermal Characteristics for the MSC8254 FC-PBGA 29 × 29 mm2 Natural Convection 200 ft/min (1 m/s) airflow 12 9 °C/W °C/W °C/W °C/W Table 4 describes thermal characteristics of the MSC8254 for the FC-PBGA packages. Characteristic Symbol Unit Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)3 Junction-to-case4 Notes: 1. 1, 2 RθJA RθJA RθJB RθJC 18 13 5 0.6 2. 3. 4. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESDC51-6. Thermal test board meets JEDEC specification for the specified package. Junction-to-board thermal resistance determined per JEDEC JESD 51-8. Thermal test board meets JEDEC specification for the specified package. Junction-to-case at the top of the package determined using MIL- STD-883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer 2.4 CLKIN Requirements Table 5. CLKIN Requirements Parameter/Condition1 Symbol — — — — ΔVAC CIN Table 5 summarizes the required characteristics for the CLKIN signal. Min 40 1 — — 1.5 — Typ — — — — — — Max 60 4 ±150 500 — 15 Unit % V/ns ps KHz V pf Notes 2 3 — 4 — — CLKIN duty cycle CLKIN slew rate CLKIN peak period jitter CLKIN jitter phase noise at –56 dBc AC input swing limits Input capacitance Notes: 1. 2. 3. 4. For clock frequencies, see the Clock chapter in the MSC8254 Reference Manual. Measured at the rising edge and/or the falling edge at VDDIO/2. Slew rate as measured from ±20% to 80% of voltage swing at clock input. Phase noise is calculated as FFT of TIE jitter. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 25 Electrical Characteristics 2.5 2.5.1 Note: DC Electrical Characteristics DDR SDRAM DC Electrical Characteristics DDR2 SDRAM uses VDDDDR(typ) = 1.8 V and DDR3 SDRAM uses VDDDDR(typ) = 1.5 V. This section describes the DC electrical characteristics for the MSC8254. This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8254. 2.5.1.1 Note: DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 6 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR2 SDRAM. At recommended operating conditions (see Table 3) with VDDDDR = 1.8 V. Table 6. DDR2 SDRAM Interface DC Electrical Characteristics Parameter/Condition I/O reference voltage Input high voltage Input low voltage I/O leakage current Output high current (VOUT (VOH) = 1.37 V) Output low current (VOUT (VOL) = 0.33 V) Notes: 1. 2. 3. Symbol MVREF VIH VIL IOZ IOH IOL Min 0.49 × VDDDDR MVREF + 0.125 –0.3 –50 –13.4 13.4 Max 0.51 × VDDDDR VDDDDR + 0.3 Unit V V V μA mA mA Notes 2, 3, 4 5 5 6 7 7 MVREF – 0.125 50 — — 4. 5. 6. 7. VDDDDR is expected to be within 50 mV of the DRAM VDD supply voltage at all times. The DRAM and memory controller can use the same or different sources. MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations in the DC-level of MVREF. The voltage regulator for MVREF must be able to supply up to 300 μA. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR. Refer to the IBIS model for the complete output IV curve characteristics. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 26 Freescale Semiconductor Electrical Characteristics 2.5.1.2 Note: DDR3 (1.5V) SDRAM DC Electrical Characteristics Table 7 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. At recommended operating conditions (see Table 3) with VDDDDR = 1.5 V. Table 7. DDR3 SDRAM Interface DC Electrical Characteristics Parameter/Condition I/O reference voltage Input high voltage Input low voltage I/O leakage current Notes: 1. 2. 3. Symbol MVREF VIH VIL IOZ Min 0.49 × VDDDDR MVREF + 0.100 GND –50 Max 0.51 × VDDDDR VDDDDR MVREF – 0.100 50 Unit V V V μA Notes 2,3,4 5 5 6 4. 5. 6. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. The DRAM and memory controller can use the same or different sources. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±1% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations in the DC-level of MVREF. The voltage regulator for MVREF must be able to supply up to 250 μA. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR. 2.5.1.3 Note: DDR2/DDR3 SDRAM Capacitance Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory. At recommended operating conditions (see Table 3) with VDDDDR = 1.8 V for DDR2 memory or VDDDDR = 1.5 V for DDR3 memory. Table 8. DDR2/DDR3 SDRAM Capacitance Parameter I/O capacitance: DQ, DQS, DQS Delta I/O capacitance: DQ, DQS, DQS Notes: 1. 2. Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1, 2 1, 2 This parameter is sampled. VDDDDR = 1.8 V ± 0.1 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V. This parameter is sampled. VDDDDR = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.175 V. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 27 Electrical Characteristics 2.5.1.4 Note: DDR Reference Current Draw Table 9 lists the current draw characteristics for MVREF. Values when used at recommended operating conditions (see Table 3). Table 9. Current Draw Characteristics for MVREF Parameter / Condition Current draw for MVREFn • DDR2 SDRAM • DDR3 SDRAM Symbol IMVREFn Min — Max 300 250 Unit μA μA 2.5.2 High-Speed Serial Interface (HSSI) DC Electrical Characteristics The MSC8254 features an HSSI that includes two 4-channel SerDes ports used for high-speed serial interface applications (PCI Express, Serial RapidIO interfaces, and SGMII). This section and its subsections describe the common portion of the SerDes DC, including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter (Tx) and receiver (Rx) reference circuits. The data lane circuit specifications are specific for each supported interface, and they have individual subsections by protocol. The selection of individual data channel functionality is done via the Reset Configuration Word High Register (RCWHR) SerDes Protocol selection fields (S1P and S2P). Specific AC electrical characteristics are defined in Section 2.6.2, “HSSI AC Timing Specifications.” 2.5.2.1 Signal Term Definitions The SerDes interface uses differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 4 shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. Figure 4 shows the waveform for either a transmitter output (SR[1–2]_TX and SR[1–2]_TX) or a receiver input (SR[1–2]_RX and SR[1–2]_RX). Each signal swings between A volts and B volts where A > B. A Volts SR[1–2]_TX or SR[1–2]_RX Vcm = (A + B)/2 SR[1–2]_TX or SR[1–2]_RX B Volts Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown) Figure 4. Differential Voltage Definitions for Transmitter or Receiver MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 28 Freescale Semiconductor Electrical Characteristics Using this waveform, the definitions are listed in Table 10. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. Table 10. Differential Signal Definitions Term Single-Ended Swing Definition The transmitter output signals and the receiver input signals SR[1–2]_TX, SR[1–2]_TX, SR[1–2]_RX and SR[1–2]_RX each have a peak-to-peak swing of A – B volts. This is also referred to as each signal wire’s single-ended swing. The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSR[1–2]_TX – VSR[1–2]_TX. The VOD value can be either positive or negative. The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complimentary input voltages: VSR[1–2]_RX – VSR[1–2]_RX. The VID value can be either positive or negative. The peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, VDIFFp = |A – B| volts. Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 × |VOD|. The differential waveform is constructed by subtracting the inverting signal (SR[1–2]_TX, for example) from the non-inverting signal (SR[1–2]_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 16 as an example for differential waveform. The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSR[1–2]_TX + VSR[1–2]_TX) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. Differential Output Voltage, VOD (or Differential Output Swing): Differential Input Voltage, VID (or Differential Input Swing) Differential Peak Voltage, VDIFFp Differential Peak-to-Peak, VDIFFp-p Differential Waveform Common Mode Voltage, Vcm To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (VOD) has the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 29 Electrical Characteristics 2.5.2.2 SerDes Reference Clock Receiver Characteristics The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clock inputs are SR1_REF_CLK/SR1_REF_CLK or SR2_REF_CLK/SR2_REF_CLK. Figure 5 shows a receiver reference diagram of the SerDes reference clocks. 50 Ω SR[1–2]_REF_CLK Input Amp SR[1–2]_REF_CLK 50 Ω Figure 5. Receiver of SerDes Reference Clocks The characteristics of the clock signals are as follows: • • The supply voltage requirements for VDDSXC are as specified in Table 3. The SerDes reference clock receiver reference circuit structure is as follows: — The SR[1–2]_REF_CLK and SR[1–2]_REF_CLK are internally AC-coupled differential inputs as shown in Figure 5. Each differential clock input (SR[1–2]_REF_CLK or SR[1–2]_REF_CLK) has on-chip 50-Ω termination to GNDSXC followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and single-ended mode descriptions below for detailed requirements. The maximum average current requirement also determines the common mode voltage range. — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA) while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. — If the device driving the SR[1–2]_REF_CLK and SR[1–2]_REF_CLK inputs cannot drive 50 Ω to GNDSXC DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled externally. The input amplitude requirement is described in detail in the following sections. • • MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 30 Freescale Semiconductor Electrical Characteristics 2.5.2.3 SerDes Transmitter and Receiver Reference Circuits Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver. 50 Ω SR[1–2]_TXm SR[1–2]_RXm 50 Ω Transmitter 50 Ω SR[1–2]_TXm SR[1–2]_RXm 50 Ω Receiver Note: The [1–2] indicates the specific SerDes Interface (1 or 2) and the m indicates the specific channel within that interface (0,1,2,3). Actual signals are assigned by the HRCW assignments at reset (see Chapter 5, Reset in the reference manual for details) Figure 6. SerDes Transmitter and Receiver Reference Circuits 2.5.3 DC-Level Requirements for SerDes Interfaces The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the Serial RapidIO data lines, and the SGMII data lines. 2.5.3.1 DC-Level Requirements for SerDes Reference Clocks The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below: • Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For an external DC-coupled connection, the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 7 shows the SerDes reference clock input requirement for DC-coupled connection scheme. 200 mV < Input Amplitude or Differential Peak < 800 mV Vmax < 800 mV SR[1–2]_REF_CLK 100 mV < Vcm < 400 mV SR[1–2]_REF_CLK Vmin > 0 V Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled) MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 31 Electrical Characteristics — For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input requirement for AC-coupled connection scheme. 200 mV < Input Amplitude or Differential Peak < 800 mV SR[1–2]_REF_CLK Vmax < Vcm + 400 mV Vcm SR[1–2]_REF_CLK Vmin > Vcm – 400 mV Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled) • Single-Ended Mode — The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left unconnected or tied to ground. — The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use. 400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV SR[1–2]_REF_CLK 0V SR[1–2]_REF_CLK Figure 9. Single-Ended Reference Clock Input DC Requirements 2.5.3.2 DC-Level Requirements for PCI Express Configurations The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8254 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 32 Freescale Semiconductor Electrical Characteristics Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications Parameter Symbol VTX-DIFFp-p VTX-DE-RATIO ZTX-DIFF-DC ZTX-DC Min 800 3.0 80 40 Typical 1000 3.5 100 50 Max 1200 4.0 120 60 Units mV dB Ω Ω Notes 1 2 3 4 Differential peak-to-peak output voltage De-emphasized differential output voltage (ratio) DC differential Tx impedance Transmitter DC impedance Notes: 1. 2. 3. 4. VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin. Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. Measured at the package pins with a test load of 50 Ω to GND on each pin. Tx DC differential mode low impedance Required Tx D+ as well as D– DC Impedance during all states Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications Parameter Differential input peak-to-peak voltage DC differential Input Impedance DC input impedance Powered down DC input impedance Electrical idle detect threshold Notes: 1. 2. Symbol VRX-DIFFp-p ZRX-DIFF-DC ZRX-DC ZRX-HIGH-IMP-DC VRX-IDLE-DET-DIFFp-p Min 120 80 40 50 65 Typical 1000 100 50 — — Max 1200 120 60 — 175 Units mV Ω Ω ΚΩ mV Notes 1 2 3 4 5 3. 4. 5. VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin. Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of a port. Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of a port. Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx ground. VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. Measured at the package pins of the receiver 2.5.3.3 Note: DC-Level Requirements for Serial RapidIO Configurations This sections provided various DC-level requirements for Serial RapidIO Configurations. Specifications are valid at the recommended operating conditions listed in Table 3. Table 13. Serial RapidIO Transmitter DC Specifications Parameter Output voltage Long run differential output voltage Short run differential output voltage Note: Symbol VO VDIFFPP VDIFFPP Min –0.40 800 500 Typical Max 2.30 1600 1000 Units V mVp-p mVp-p Notes 1 — — — — — Voltage relative to COMMON of either signal comprising a differential pair. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 33 Electrical Characteristics Table 14. Serial RapidIO Receiver DC Specifications Parameter Differential input voltage Notes: 1. Measured at receiver. Symbol VIN Min 200 Typical — Max 1600 Units mVp-p Notes 1 2.5.3.4 Note: DC-Level Requirements for SGMII Configurations Specifications are valid at the recommended operating conditions listed in Table 3 Table 15 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) as shown in Figure 10. Table 15. SGMII DC Transmitter Electrical Characteristics5 Parameter DC Input voltage range Input differential voltage LSTS = 0 LSTS = 1 Loss of signal threshold LSTS = 0 LSTS = 1 Receiver differential input impedance Notes: 1. 2. 3. ZRX_DIFF VLOS Symbol — VRX_DIFFp-p Min Typ N/A Max Unit — Notes 1 2, 4 100 175 30 65 80 — — — — — 1200 mV 100 175 120 mV 3, 4 W — 4. 5. Input must be externally AC-coupled. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface. Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document. for details. The LSTS shown in the table refers to the LSTSAB or LSTSEF bit fields of the SerDes Control Register. The supply voltage is 1.0 V. SGMII SerDes Interface 50 Ω SR[1–2]_TXn Transmitter 50 Ω SR[1–2]_TXn 50 Ω Vos 50 Ω VOD Figure 10. SGMII Transmitter DC Measurement Circuit MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 34 Freescale Semiconductor Electrical Characteristics Table 16 describes the SGMII SerDes receiver AC-coupled DC electrical characteristics. Table 16. SGMII DC Receiver Electrical Characteristics5 Parameter DC Input voltage range Input differential voltage SRDSnCR4[EICE{12:10}] = 0b001 for SGMII1 SRDSnCR4[EICF{4:2}] = 0b001 for SGMII2 SRDSnCR4[EICE{12:10}] = 0b100 for SGMII1 SRDSnCR4[EICF{4:2}] = 0b100 for SGMII2 SRDSnCR4[EICE{12:10}] = 0b001 for SGMII1 SRDSnCR4[EICF{4:2}] = 0b001 for SGMII2 SRDSnCR4[EICE{12:10}] = 0b100 for SGMII1 SRDSnCR4[EICF{4:2}] = 0b100 for SGMII2 ZRX_DIFF VLOS Symbol — VRX_DIFFp-p Min Typ N/A Max Unit — Notes 1 2, 4 100 175 30 65 80 — — — — — 1200 mV Loss of signal threshold 100 175 120 mV 3, 4 Receiver differential input impedance Notes: 1. 2. 3. W — 4. 5. Input must be externally AC-coupled. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface. Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document. for details. The values for SGMII1 and SGMII2 are selected in the SRDS control registers. The supply voltage is 1.0 V. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 35 Electrical Characteristics 2.5.4 • • • • • • • • • • • • RGMII and Other Interface DC Electrical Characteristics RGMII Ethernet SPI TDM GPIO UART TIMER EE I 2C Interrupts (IRQn, NMI_OUT, INT_OUT) Clock and resets (CLKIN, PORESET, HRESET, SRESET) DMA External Request JTAG signals Table 17. 2.5 V I/O DC Electrical Characteristics Characteristic Symbol VIH VIL IIN IIL VOH VOL Table 17 describes the DC electrical characteristics for the following interfaces: Min 1.7 — — –15 2.0 GND – 0.3 Max — 0.7 10 — VDDIO + 0.3 0.40 Unit V V μA μA V V Notes 1 1 2 2 1 1 Input high voltage Input low voltage Input high current (VIN = VDDIO) Output low current (VIN = GND) Output high voltage (VDDIO = min, IOH = –1.0 mA Output low voltage (VDDIO = min, IOL= 1.0 mA) Notes: 1. 2. The min VIL and max VIH values are based on the respective min and max VIN values listed in Table 3. The symbol VIN represents the input voltage of the supply. It is referenced in Table 3. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 36 Freescale Semiconductor Electrical Characteristics 2.6 2.6.1 AC Timing Characteristics DDR SDRAM AC Timing Specifications This section describes the AC timing characteristics for the MSC8254. This section describes the AC electrical characteristics for the DDR SDRAM interface. 2.6.1.1 DDR SDRAM Input AC Timing Specifications Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface Parameter Symbol VIL VIH Min — MVREF + 0.20 Max MVREF – 0.20 — Unit V V Table 18 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.8 V. AC input low voltage AC input high voltage Note: At recommended operating conditions with VDDDDR of 1.8 ± 5%. Table 19 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.5 V. Table 19. DDR3 SDRAM Input AC Timing Specifications for 1.5 V Interface Parameter AC input low voltage AC input high voltage Note: At recommended operating conditions with VDDDDR of 1.5 ± 5%. Symbol VIL VIH Min — MVREF + 0.175 Max MVREF – 0.175 — Unit V V Table 20 provides the input AC timing specifications for the DDR SDRAM interface. Table 20. DDR SDRAM Input AC Timing Specifications Parameter Controller Skew for MDQS—MDQ/MECC/MDM • 800 MHz data rate • 667 MHz data rate Tolerated Skew for MDQS—MDQ/MECC/MDM • 800 MHz data rate • 667 MHz data rate Notes: 1. 2. 3. Symbol tCISKEW –200 –240 tDISKEW –425 –510 425 510 ps ps 200 240 ps ps 2, 3 Min Max Unit Notes 1, 2 tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. Subtract this value from the total timing budget. At recommended operating conditions with VDDDDR (1.8 V or 1.5 V) ± 5% The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 37 Electrical Characteristics Figure 11 shows the DDR2 and DDR3 SDRAM interface input timing diagram. MCK[n] MCK[n] tMCK MDQS[n] tDISKEW MDQ[n] tDISKEW D0 D1 tDISKEW Figure 11. DDR2 and DDR3 SDRAM Interface Input Timing Diagram 2.6.1.2 DDR SDRAM Output AC Timing Specifications Table 21. DDR SDRAM Output AC Timing Specifications Parameter Symbol 1 tMCK tDDKHAS 0.917 1.10 tDDKHAX 0.767 1.02 tDDKHCS 0.917 1.10 tDDKHCX 0.767 1.02 tDDKHMH –0.4 –0.6 tDDKHDS, tDDKLDS tDDKHDX, tDDKLDX tDDKHMP tDDKHME 300 375 300 375 –0.9 × tMCK –0.4 × tMCK 0.375 0.6 5 — — — — — –0.6 × tMCK ps ps 5 ps ps ns ns — — — — ns ns ns 4 — — ns ns 3 — — ns ns 3 — — ns ns 3 Min 2.5 Max 5 Unit ns Notes 2 3 Table 21 provides the output AC timing specifications for the DDR SDRAM interface. MCK[n] cycle time ADDR/CMD output setup with respect to MCK • 800 MHz data rate • 667 MHz data rate ADDR/CMD output hold with respect to MCK • 800 MHz data rate • 667 MHz data rate MCSn output setup with respect to MCK • 800 MHz data rate • 667 MHz data rate MCSn output hold with respect to MCK • 800 MHz data rate • 667 MHz data rate MCK to MDQS Skew • 800 MHz data rate • 667 MHz data rate MDQ/MECC/MDM output setup with respect to MDQS • 800 MHz • 667 MHz MDQ/MECC/MDM output hold with respect to MDQS • 800 MHz • 667 MHz MDQS preamble MDQS postamble MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 38 Freescale Semiconductor Electrical Characteristics Table 21. DDR SDRAM Output AC Timing Specifications (continued) Parameter Notes: 1. Symbol 1 Min Max Unit Notes 2. 3. 4. 5. 6. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. All MCK/MCK referenced measurements are made from the crossing of the two signals. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the MSC8254 Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8254. At recommended operating conditions with VDDDDR (1.5 V or 1,8 V) ± 5%. Note: For the ADDR/CMD setup and hold specifications in Table 21, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. Figure 12 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns or 0.375 ns MDQS tDDKHMH(min) = –0.6 ns or –0.375 ns MDQS Figure 12. MCK to MDQS Timing MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 39 Electrical Characteristics Figure 13 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS, tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 13. DDR SDRAM Output Timing Figure 14 provides the AC test load for the DDR2 and DDR3 controller bus. Output Z0 = 5 0 Ω VDDDDR/2 RL = 50 Ω Figure 14. DDR2 and DDR3 Controller Bus AC Test Load 2.6.1.3 DDR2 and DDR3 SDRAM Differential Timing Specifications This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM controller interface. Figure 15 shows the differential timing specification. GVDD VTR GVDD/2 VCP GND VOX or VIX Figure 15. DDR2 and DDR3 SDRAM Differential Timing Specifications Note: VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as MCK or MDQS). MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 40 Freescale Semiconductor Electrical Characteristics Table 22 provides the DDR2 differential specifications for the differential signals MDQS/MDQS and MCK/MCK. Table 22. DDR2 SDRAM Differential Electrical Characteristics Parameter Input AC differential cross-point voltage Output AC differential cross-point voltage Symbol VIXAC VOXAC Min 0.5 × GVDD – 0.175 0.5 × GVDD – 0.125 Max 0.5 × GVDD + 0.175 0.5 × GVDD + 0.125 Unit V V Table 23 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK. Table 23. DDR3 SDRAM Differential Electrical Characteristics Parameter Input AC differential cross-point voltage Output AC differential cross-point voltage Symbol VIXAC VOXAC Min 0.5 × GVDD – 0.150 0.5 × GVDD – 0.115 Max 0.5 × GVDD + 0.150 0.5 × GVDD + 0.115 Unit V V 2.6.2 HSSI AC Timing Specifications The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the Serial RapidIO data lines, and the SGMII data lines. 2.6.2.1 Note: AC Requirements for SerDes Reference Clock Table 24 lists AC requirements for the SerDes reference clocks. Specifications are valid at the recommended operating conditions listed in Table 3. Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements Parameter SR[1–2]_REF_CLK/SR[1–2]_REF_CLK frequency range SR[1–2]_REF_CLK/SR[1–2]_REF_CLK clock frequency tolerance SR[1–2]_REF_CLK/SR[1–2]_REF_CLK reference clock duty cycle (measured at 1.6 V) SR[1–2]_REF_CLK/SR[1–2]_REF_CLK max deterministic peak-peak jitter at 10-6 BER SR[1–2]_REF_CLK/SR[1–2]_REF_CLK total reference clock jitter at 10-6 BER (peak-to-peak jitter at ref_clk input) SR[1–2]_REF_CLK/SR[1–2]_REF_CLK rising/falling edge rate Differential input high voltage Differential input low voltage Rising edge rate (SR[1–2]_REF_CLK) to falling edge rate (SR[1–2]_REF_CLK) matching Symbol tCLK_REF tCLK_TOL tCLK_DUTY tCLK_DJ tCLK_TJ Min — –350 40 — — Typical 100/125 — 50 — — Max — 350 60 42 86 Units MHz ppm % ps ps Notes 1 — — — 2 tCLKRR/tCLKFR VIH VIL Rise-Fall Matching 1 200 — — — — — — 4 — –200 20 V/ns mV mV % 3 4 4 5, 6 MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 41 Electrical Characteristics Table 24. SR[1–2]_REF_CLK and SR[1–2]_REF_CLK Input Clock Requirements (continued) Parameter Notes: 1. 2. 3. Symbol Min Typical Max Units Notes 4. 5. 6. Caution: Only 100 and 125 have been tested. Other values will not work correctly with the rest of the system. Limits from PCI Express CEM Rev 1.0a Measured from –200 mV to +200 mV on the differential waveform (derived from SR[1–2]_REF_CLK minus SR[1–2]_REF_CLK). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 16. Measurement taken from differential waveform Measurement taken from single-ended waveform Matching applies to rising edge for SR[1–2]_REF_CLK and falling edge rate for SR[1–2]_R EF_CLK. It is measured using a 200 mV window centered on the median cross point where SR[1–2]_REF_CLK rising meets SR[1–2]_REF_CLK falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SR[1–2]_REF_CLK should be compared to the fall edge rate of SR[1–2]_REF_CLK; the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 17. Rise Edge Rate Fall Edge Rate VIH = +200 mV 0.0 V VIL = –200 mV SR[1–2]_REF_CLK – SR[1–2]_REF_CLK Figure 16. Differential Measurement Points for Rise and Fall Time Figure 17. Single-Ended Measurement Points for Rise and Fall Time Matching MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 42 Freescale Semiconductor Electrical Characteristics 2.6.2.2 PCI Express AC Physical Layer Specifications The AC requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8254 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The transmitter specifications are defined in Table 25 and the receiver specifications are defined in Table 26. The parameters are specified at the component pins. the AC timing specifications do not include REF_CLK jitter. Note: Specifications are valid at the recommended operating conditions listed in Table 3. Table 25. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications Parameter Unit interval Minimum Tx eye width Maximum time between the jitter median and maximum deviation from the median. AC coupling capacitor Notes: 1. 2. 3. Symbol UI TTX-EYE TTX-EYE-MEDIANto-MAX-JITTER Min 399.88 0.70 — 75 Typical 400.00 — — — Max 400.12 — 0.15 200 Units ps UI UI nF Notes 1 2, 3 3, 4 5 CTX 4. 5. Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. No test load is necessarily associated with this value. The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 – TTX-EYE = 0.3 UI. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 8 and measured over any 250 consecutive Tx UIs. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered Tx UI. A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI. All transmitters shall be AC-coupled. The AC coupling is required either within the media or within the transmitting component itself. The SerDes transmitter does not have built-in Tx capacitance. An external AC coupling capacitor is required. Table 26. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input AC Specifications Parameter Unit Interval Minimum receiver eye width Maximum time between the jitter median and maximum deviation from the median. Notes: 1. 2. 3. Symbol UI TRX-EYE TRX-EYE-MEDIAN-to-MAX -JITTER Min 399.88 0.4 — Typical 400.00 — — Max 400.12 — 0.3 Units ps UI UI Notes 1 2, 3, 4 3, 4, 5 4. 5. Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. No test load is necessarily associated with this value. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER = 1 – TRX-EYE = 0.6 UI. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 8 should be used as the Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered Tx UI. A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx UI. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 43 Electrical Characteristics 2.6.2.3 Note: Serial RapidIO AC Timing Specifications Specifications are valid at the recommended operating conditions listed in Table 3. Table 27 defines the transmitter AC specifications for the Serial RapidIO interface. The AC timing specifications do not include REF_CLK jitter. Table 27. Serial RapidIO Transmitter AC Timing Specifications Characteristic Deterministic Jitter Total Jitter Unit Interval: 1.25 GBaud Unit Interval: 2.5 GBaud Unit Interval: 3.125 GBaud Symbol JD JT UI UI UI Min — — 800 – 100ppm 400 – 100ppm 320 – 100ppm Typical — — 800 400 320 Max 0.17 0.35 800 + 100ppm 400 + 100ppm 320 + 100ppm Unit UI p-p UI p-p ps ps ps Table 28 defines the Receiver AC specifications for the Serial RapidIO interface. The AC timing specifications do not include REF_CLK jitter. Table 28. Serial RapidIO Receiver AC Timing Specifications Characteristic Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Bit Error Rate Unit Interval: 1.25 GBaud Unit Interval: 2.5 GBaud Unit Interval: 3.125 GBaud Notes: 1. 2. Symbol JD JDR JT BER UI UI UI Min 0.37 0.55 0.65 — 800 – 100ppm 400 – 100ppm 320 – 100ppm Typical — — — — 800 400 320 Max — — — 10 –12 Unit UI p-p UI p-p UI p-p — ps ps ps Notes 1 1 1, 2 — — — — 800 + 100ppm 400 + 100ppm 320 + 100ppm Measured at receiver. Total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 18. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. 8.5 UI p-p Sinusoidal Jitter Amplitude 0.10 UI p-p 22.1 kHz Frequency 1.875 MHz 20 MHz Figure 18. Single Frequency Sinusoidal Jitter Limits MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 44 Freescale Semiconductor Electrical Characteristics 2.6.2.4 Note: SGMII AC Timing Specifications Specifications are valid at the recommended operating conditions listed in Table 3. Transmitter and receiver AC characteristics are measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) or at the receiver inputs (SR[1–2]_RX[n] and SR[1–2]_RX[n]) as depicted in Figure 19, respectively. D+ Package Pin TX Silicon + Package D– Package Pin C = CTX C = CTX R = 50 Ω R = 50 Ω Figure 19. SGMII AC Test/Measurement Load Table 29 provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include REF_CLK jitter. Table 29. SGMII Transmit AC Timing Specifications Parameter Symbol JD JT UI Min — — 799.92 Typ — — 800 Max 0.17 0.35 800.08 Unit UI p-p UI p-p ps Notes Deterministic Jitter Total Jitter Unit Interval Notes: 1. 2. — 2 1 See Figure 18 for single frequency sinusoidal jitter limits Each UI is 800 ps ± 100 ppm. Table 30 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter. Table 30. SGMII Receive AC Timing Specifications Parameter Deterministic Jitter Tolerance Combined Deterministic and Random Jitter Tolerance Total Jitter Tolerance Bit Error Ratio Unit Interval Notes: 1. 2. 3. Symbol JD JDR JT BER UI Min 0.37 0.55 0.65 — 799.92 Typ — — — — 800.00 Max — — — 10-12 800.08 Unit UI p-p UI p-p UI p-p — ps Notes 1, 2 1, 2 1,2 — 3 Measured at receiver. Refer to RapidIOTM 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. Also see Figure 18. Each UI is 800 ps ± 100 ppm. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 45 Electrical Characteristics 2.6.3 TDM Timing Table 31. TDM AC Timing Specifications for 62.5 MHz1 Parameter Symbol2 tDM tDM_HIGH tDM_LOW tDMIVKH tDMRDIXKH tDMFSIXKH tDM_OUTAC tDMTKHOV tDMTKHOX tDM_OUTHI tDMFSKHOV tDMFSKHOX Table 31 provides the input and output AC timing specifications for the TDM interface. Min 16.0 7.0 7.0 3.6 1.9 1.9 2.5 — 2.5 — — 2.0 Max — — — — — — — 9.8 — 9.8 9.25 — Unit ns ns ns ns ns ns ns ns ns ns ns ns TDMxRCK/TDMxTCK TDMxRCK/TDMxTCK high pulse width TDMxRCK/TDMxTCK low pulse width TDM all input setup time TDMxRD hold time TDMxTFS/TDMxRFS input hold time TDMxTCK High to TDMxTD output active TDMxTCK High to TDMxTD output valid TDMxTD hold time TDMxTCK High to TDMxTD output high impedance TDMxTFS/TDMxRFS output valid TDMxTFS/TDMxRFS output hold time Notes: 1. 2. 3. 4. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the output internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Output values are based on 30 pF capacitive load. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. All values are based on a maximum TDM interface frequency of 62.5 MHz. Figure 20 shows the TDM receive signal timing. tDM tDM_HIGH TDMxRCK tDM_LOW tDMIVKH TDMxRD tDMRDIXKH tDMIVKH TDMxRFS tDMFSIXKH tDMFSKHOV ~ ~ TDMxRFS (output) tDMFSKHOX Figure 20. TDM Receive Signals MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 46 Freescale Semiconductor Electrical Characteristics Figure 21 shows the TDM transmit signal timing. tDM tDM_HIGH TDMxTCK tDM_LOW tDM_OUTHI tDMTKHOV TDMxTD TDMxRCK tDMFSKHOV TDMxTFS (output) ~~ ~~ tDM_OUTAC tDMTKHOX tDMFSKHOX tDMIVKH TDMxTFS (input) tDMFSIXKH Figure 21. TDM Transmit Signals Figure 22 provides the AC test load for the TDM/SI. Output Z0 = 5 0 Ω RL = 50 Ω VDDIO/2 Figure 22. TDM AC Test Load 2.6.4 Timers AC Timing Specifications Table 32. Timers Input AC Timing Specifications Characteristics Symbol TTIWID Minimum 8 Unit ns Notes 1, 2 Table 32 lists the timer input AC timing specifications. Timers inputs—minimum pulse width Notes: 1. 2. The maximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. Note: For recommended operating conditions, see Table 3. Figure 23 shows the AC test load for the timers. Output Z0 = 5 0 Ω RL = 50 Ω VDDIO/2 Figure 23. Timer AC Test Load MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 47 Electrical Characteristics 2.6.5 Ethernet Timing This section describes the AC electrical characteristics for the Ethernet interface. There are programmable delay units (PDU) that should be programmed differently for each interface to meet timing. There is a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8254 Reference Manual. 2.6.5.1 Management Interface Timing Table 33. Ethernet Controller Management Interface Timing Characteristics Symbol tMDKHDX tMDDVKH tMDDXKH Min 10 7 0 Max 70 — — Unit ns ns ns Table 33 lists the timer input Ethernet controller management interface timing specifications shown in Table 24. GE_MDC to GE_MDIO delay2 GE_MDIO to GE_MDC rising edge setup time GE_MDC rising edge to GE_MDIO hold time Notes: 1. 2. Program the GE_MDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz to achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8254 Reference Manual for configuration details. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of 333 MHz, the delay is 58 ns. tMDC GE_MDC GE_MDIO (Input) tMDDVKH tMDDXKH GE_MDIO (Output) tMDKHDX Figure 24. MII Management Interface Timing 2.6.5.2 RGMII AC Timing Specifications Table 34. RGMII at 1 GHz2 with On-Board Delay3 AC Timing Specifications Parameter/Condition Symbol tSKEWT tSKEWR Min –-0.5 1 Typ — — Max 0.5 2.6 Unit ns ns Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock. Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 4 Notes: 1. 2. 3. 4. 4 At recommended operating conditions with VDDIO of 2.5 V ± 5%. RGMII at 100 MHz support is guaranteed by design. Program GCR4 as 0x00000000. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 48 Freescale Semiconductor Electrical Characteristics Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board. Table 35. RGMII at 1 GHz2 with No On-Board Delay3 AC Timing Specifications Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Notes: 1. 2. 3. 4. 4 4 Symbol tSKEWT tSKEWR Min –2,6 –0.5 Typ — — Max –1.0 0.5 Unit ns ns At recommended operating conditions with VDDIO of 2.5 V ± 5%. RGMII at 100 MHz support is guaranteed by design. GCR4 should be programmed as 0x000CC330. This implies that PC board design requires clocks to be routed with no additional trace delay Figure 25 shows the RGMII AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) tSKEWT TXD[3:0] txd[3:0] txd[7:4] TX_CTL RXD[3:0] rxd[3:0] rxd[8:5] RX_CTL tSKEWR RX_CLK (At Receiver) Figure 25. RGMII AC Timing and Multiplexing 2.6.6 SPI Timing Table 36. SPI AC Timing Specifications Parameter Symbol 1 Min Max Unit Note Table 36 lists the SPI input and output AC timing specifications. SPI outputs valid—Master mode (internal clock) delay SPI outputs hold—Master mode (internal clock) delay SPI outputs valid—Slave mode (external clock) delay SPI outputs hold—Slave mode (external clock) delay SPI inputs—Master mode (internal clock) input setup time tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH — 0.5 — 2 12 6 — 12 — — ns ns ns ns ns 2 2 2 2 — MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 49 Electrical Characteristics Table 36. SPI AC Timing Specifications Parameter Symbol 1 Min Max Unit Note SPI inputs—Master mode (internal clock) input hold time SPI inputs—Slave mode (external clock) input setup time SPI inputs—Slave mode (external clock) input hold time Notes: 1. tNIIXKH tNEIVKH tNEIXKH 0 4 2 — — — ns ns ns — — — The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) 2. until outputs (O) are invalid (X). Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings are measured at the pin. Figure 26 provides the AC test load for the SPI. Output Z0 = 5 0 Ω VDDIO/2 RL = 50 Ω Figure 26. SPI AC Test Load Figure 27 and Figure 28 represent the AC timings from Table 36. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 27 shows the SPI timings in slave mode (external clock). SPICLK (input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See note) Output Signals: SPIMISO (See note) tNEKHOX tNEKHOV Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0 Figure 27. SPI AC Timing in Slave Mode (External Clock) Figure 28 shows the SPI timings in master mode (internal clock). SPICLK (output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See note) Output Signals: SPIMOSI (See note) tNIKHOX tNIKHOV Note: measured with SPMODE[CI] = 0, SPMODE[CP] = 0 Figure 28. SPI AC Timing in Master Mode (Internal Clock) MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 50 Freescale Semiconductor 2.6.7 Asynchronous Signal Timing Table 37. Signal Timing Characteristics Symbol tIN tOUT Input value relevant for EE0, IRQ[15–0], and NMI only. Type Asynchronous Asynchronous Min One CLKIN cycle Application dependent Table 35 lists the asynchronous signal timing specifications. Input Output Note: The following interfaces use the specified asynchronous signals: • Note: • • • • • GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are not selected. When used as a general purpose input (GPI), the input signal should be driven until it is acknowledged by the MSC8254 device, that is, when the expected input value is read from the GPIO data register. EE port. Signals EE0, EE1. Boot function. Signal STOP_BS. I2C interface. Signals I2C_SCL and I2C_SDA. Interrupt inputs. Signals IRQ[15–0] and NMI. Interrupt outputs. Signals INT_OUT and NMI_OUT (minimum pulse width is 32 ns). 2.6.8 JTAG Signals Table 38. JTAG Timing All frequencies Characteristics Symbol Min Max — — — — 20.0 24.0 — — 10.0 12.0 — ns ns ns ns ns ns ns ns ns ns ns tTCKX tTCKH tBSVKH tBSXKH tTCKHOV tTCKHOZ tTDIVKH tTDIXKH tTDOHOV tTDOHOZ tTRST 36.0 15.0 0.0 15.0 — — 0.0 5.0 — — 100.0 Unit Table 38 lists the JTAG timing specifications shown in Figure 29 through Figure 32. TCK cycle time TCK clock high phase measured at VM = VDDIO/2 Boundary scan input data setup time Boundary scan input data hold time TCK fall to output data valid TCK fall to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK fall to TDO data valid TCK fall to TDO high impedance TRST assert time Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 29 shows the test clock input timing diagram tTCKX tTCKH TCK (Input) tTCKR VM VM tTCKR Figure 29. Test Clock Input Timing MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 51 Figure 30 shows the boundary scan (JTAG) timing diagram. TCK (Input) tBSVKH Data Inputs tTCKHOV Data Outputs tTCKHOZ Data Outputs tBSXKH Input Data Valid Output Data Valid Figure 30. Boundary Scan (JTAG) Timing Figure 31 shows the test access port timing diagram TCK (Input) TDI TMS (Input) tTDIVKH tTDIXKH Input Data Valid tTDOHOV TDO (Output) tTDOHOZ TDO (Output) Output Data Valid Figure 31. Test Access Port Timing Figure 32 shows the TRST timing diagram. TRST (Input) tTRST Figure 32. TRST Timing MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 52 Freescale Semiconductor Hardware Design Considerations 3 3.1 3.1.1 Hardware Design Considerations Power Supply Ramp-Up Sequence Clock, Reset, and Supply Coordination The following sections discuss areas to consider when the MSC8254 device is designed into a system. The following subsections describe the required device initialization sequence. Starting the device requires coordination between several inputs including: clock, reset, and power supplies. Follow this guidelines when starting up an MSC8254 device: • PORESET and TRST must be asserted externally for the duration of the supply ramp-up, using the VDDIO supply. TRST deassertion does not have to be synchronized with PORESET deassertion. However, TRST must be deasserted before normal operation begins to ensure correct functionality of the device. CLKIN should toggle at least 32 cycles before PORESET deassertion to guarantee correct device operation. The 32 cycles should only be counted from the time after VDDIO reaches its nominal value (see timing 1 in Figure 33). CLKIN should either be stable low during ramp-up of VDDIO supply (and start its swings after ramp-up) or should swing within VDDIO range during VDDIO ramp-up, so its amplitude grows as VDDIO grows during ramp-up. • • Figure 33 shows a sequence in which VDDIO ramps-up after VDD and CLKIN begins to toggle with the raise of VDDIO supply. VDDIO = Nominal VDD = Nominal Voltage 1 VDDIO Nominal VDD Nominal Time PORESET/TRST asserted VDD applied CLKIN starts toggling PORESET deasserted VDDIO applied Figure 33. Supply Ramp-Up Sequence with VDD Ramping Before VDDIO and CLKIN Starting With VDDIO Note: For details on power-on reset flow and duration, see the Reset chapter in the MSC8254 Reference Manual. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 53 Hardware Design Considerations 3.1.2 Power-On Ramp Time This section describes the AC electrical specification for the power-on ramp rate requirements for all voltage supplies (including GVDD/SXPVDD/SXCVDD/QVDD/GVDD/NVDD, all VDD supplies, MVREF, and all AVDD supplies). Controlling the power-on ramp time is required to avoid falsely triggering the ESD circuitry. Table 39 defines the power supply ramp time specification. Table 39. Power Supply Ramp Rate Parameter Required ramp rate. Required ramp time. Notes: 1. Min — 25 Max 36000 50 Unit V/s µs 2. Ramp time is specified as a linear ramp from 10% to 90% of nominal voltage of the specific voltage supply. If the ramp is non-linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical because this range might falsely trigger the ESD circuitry. Required over the full recommended operating temperature range (see Table 3). 3.1.3 • • • • • • Power Supply Guidelines Couple M3VDD with the VDD power rail using an extremely low impedance path. Couple inputs PLL1_AVDD, PLL2_AVDD and PLL3_AVDD with the VDD power rail using an RC filter (see Figure 37). There is no dependency in power-on/power-off sequence between the GVDD1, GVDD2, NVDD, and QVDD power rails. Couple inputs M1VREF and M2VREF with the GVDD1 and GVDD2 power rails, respectively. They should rise at the same time as or after their respective power rail. There is no dependency between RapidIO supplies: SXCVDD1, SXCVDD2, SXPVDD1 and SXPVDD2 and other MSC8254 supplies in the power-on/power-off sequence Couple inputs SR1_PLL_AVDD and SR2_PLL_AVDD with SXCVDD1 and SXCVDD2 power rails, respectively, using an RC filter (see Figure 38). Use the following guidelines for power-up sequencing: External voltage applied to any input line must not exceed the I/O supply voltage related to this line by more than 0.6 V at any time, including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80 mA per input pin per MSC8254 device in the system during power-up. An assertion of the inputs to the high voltage level before power-up should be with slew rate less than 4 V/ns. The device power rails should rise in the following sequence: 1. 2. VDD (and all coupled supplies) After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see Figure 34): QVDD, NVDD, GVDD1, and GVDD2. NVDD, QVDD, GVDD1, GVDD2 VDD, M3VDD 90% Figure 34. Supply Ramp-Up Sequence MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 54 Freescale Semiconductor Hardware Design Considerations Notes: 1. 2. 3. 4. 5. If the M3 memory is not used, M3VDD can be tied to GND. If the HSSI port1 is not used, SXCVDD1and SXPVDD1 must be connected to the designated power supplies. If the HSSI port2 is not used, SXCVDD2 and SXPVDD2 must be connected to the designated power supplies. If the DDR port 1 interface is not used, it is recommended that GVDD1 be left unconnected. If the DDR port 2 interface is not used, it is recommended that GVDD2 be left unconnected. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 55 Hardware Design Considerations 3.1.4 Reset Guidelines When a debugger is not used, implement the connection scheme shown in Figure 35. MSC815x On-board PORESET source (example: voltage monitor) TRST PORESET Figure 35. Reset Connection in Functional Application When a debugger is used, implement the connection scheme shown in Figure 36. VDDIO 10 ΚΩ MSC815x TRST On-board PORESET source (example: voltage monitor) PORESET On-board TRST source (example: OnCE) Figure 36. Reset Connection in Debugger Application 3.2 • • • Note: PLL Power Supply Design Considerations R = 5 Ω ± 5% C1 = 10 µ F ± 10%, 0603, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor. C2 = 1.0 µF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH, low ESL Surface Mount Capacitor. A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change. Each global PLL power supply must have an external RC filter for the PLLn_AVDD input (see Figure 37) in which the following components are defined as listed: All three PLLs can connect to a single supply voltage source (such as a voltage regulator) as long as the external RC filter is applied to each PLL separately. For optimal noise filtering, place the circuit as close as possible to its PLLn_AVDD inputs. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 56 Freescale Semiconductor Hardware Design Considerations . MSC8156E VDD Power Rail (Voltage Regulator) R PLL0_AVDD C1 VSS R C2 PLL1_AVDD C1 VSS R C2 PLL2_AVDD C1 VSS C2 Figure 37. PLL Supplies Each SerDes PLL power supply must be filtered using a circuit similar to the one shown in Figure 38, to ensure stability of the internal clock. For maximum effectiveness, the filter circuit should be placed as closely as possible to the SRn_PLL_AVDD ball to ensure it filters out as much noise as possible. The ground connection should be near the SRn_PLL_AVDD ball. The 0.003 μF capacitor is closest to the ball, followed by the two 2.2 μF capacitors, and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from SRn_PLL_AVDD to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All trances should be kept short, wide, and direct. 1Ω VDDSXC 2.2 μF 2.2 μF 0.003 μF SRn_PLL_AGND as short as possible GNDSXC SRn_PLL_AVDD Figure 38. SerDes PLL Supplies 3.3 • • Clock and Timing Signal Board Layout Considerations Keep clock and timing signal paths as short as possible and route with 50 Ω impedance. Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following equation to compute the resistor value: Rterm = Rim – Rbuf where Rim = trace characteristic impedance Rbuf = clock buffer internal impedance. When laying out the system board, use the following guidelines: MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 57 Hardware Design Considerations 3.4 SGMII AC-Coupled Serial Link Connection Example Figure 39 shows an example of a 4-wire AC-coupled serial link connection. For additional layout suggestions, see AN3556 MSC815x High Speed Serial Interface Hardware Design Considerations, available on the Freescale website or from your local sales office or representative. SR[1–2]_TX[[1–2] CTX SR[1–2]_RX[1–2] 50 Ω Transmitter 50 Ω SR[1–2]_TX[1–2] SR[1–2]_RX[1–2] 50 Ω Receiver CTX SGMII SerDes Interface 50 Ω 50 Ω SR[1–2]_TX[1–2] SR[1–2]_RX[1–2] CTX Receiver 50 Ω SR[1–2]_RX[1–2]] Transmitter 50 Ω CTX SR[1–2]_TX[1–2] 50 Ω Figure 39. 4-Wire AC-Coupled SGMII Serial Link Connection Example 3.5 Note: Connectivity Guidelines Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal connections in this discussion. First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following subsections for board design and connections. The following conventions are used in describing the connectivity requirements: 1. GND indicates using a 10 kΩ pull-down resistor (recommended) or a direct connection to the ground plane. Direct connections to the ground plane may yield DC current up to 50 mA through the I/O supply that adds to overall power consumption. VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply. Direct connections to the supply may yield DC current up to 50 mA through the I/O supply that adds to overall power consumption. Mandatory use of a pull-up or pull-down resistor is clearly indicated as “pull-up/pull-down.” For buses, each pin on the bus should have its own resistor. NC indicates “not connected” and means do not connect anything to the pin. The phrase “in use” indicates a typical pin connection for the required function. Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of subset interface connection. 2. 3. 4. 5. Note: MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 58 Freescale Semiconductor Hardware Design Considerations 3.5.1 Note: DDR Memory Related Pins The signal names in Table 40, Table 41 and Table 42 are generic names for a DDR SDRAM interface. For actual pin names refer to Table 1. This section discusses the various scenarios that can be used with either of the MSC8254 DDR ports. 3.5.1.1 DDR Interface Is Not Used Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used Signal Name Pin Connection NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC MDQ[0–63] MDQS[7–0] MDQS[7–0] MA[15–0] MCK[0–2] MCK[0–2] MCS[1–0] MDM[7–0] MBA[2–0] MCAS MCKE[1–0] MODT[1–0] MMDIC[1–0] MRAS MWE MECC[7–0] MDM8 MDQS8 MDQS8 MAPAR_OUT MAPAR_IN MVREF 3 GVDD1/GVDD23 Notes: 1. 2. 3. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used. If the DDR controller is not used, disable the internal DDR clock by setting the appropriate bit in the System Clock Control Register (SCCR) and put all DDR I/O in sleep mode by setting DRx_GCR[DDRx_DOZE] (for DDR controller x). See the Clocks and General Configuration Registers chapters in the MSC8254 Reference Manual for details. For MSC8254 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8254, connecting these pins to GND increases device power consumption. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 59 Hardware Design Considerations 3.5.1.2 DDR Interface Is Used With 32-Bit DDR Memory Only Table 41. Connectivity of DDR Related Pins When Using 32-bit DDR Memory Only Signal Name Pin Connection in use NC in use NC in use NC in use in use in use in use in use NC in use in use in use in use in use in use in use in use in use Table 41 lists unused pin connection when using 32-bit DDR memory. The 32 most significant data lines are not used. MDQ[31–0] MDQ[63–32] MDQS[3–0] MDQS[7–4] MDQS[3–0] MDQS[7–4] MA[15–0] MCK[2–0] MCK[2–0] MCS[1–0] MDM[3–0] MDM[7–4] MBA[2–0] MCAS MCKE[1–0] MODT[1–0] MMDIC[1–0] MRAS MWE MVREF GVDD1/GVDD2 Notes: 1. 2. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used. For MSC8254 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8254, connecting these pins to GND increases device power consumption. 3.5.1.3 ECC Unused Pin Connections When the error code correction mechanism is not used in any 32- or 64-bit DDR configuration, refer to Table 42 to determine the correct pin connections. Table 42. Connectivity of Unused ECC Mechanism Pins Signal Name MECC[7–0] MDM8 MDQS8 MDQS8 Notes: 1. 2. Pin connection NC NC NC NC For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used. For MSC8254 Revision 1 silicon, these pins were connected to GND (or VDD). For newer revisions of the MSC8254, connecting these pins to GND increases device power consumption. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 60 Freescale Semiconductor Hardware Design Considerations 3.5.1.4 DDR2 Unused MAPAR Pin Connections Table 43. Connectivity of MAPAR Pins for DDR2 Signal Name When the MAPAR signals are not used, refer to Table 43 to determine the correct pin connections. Pin connection NC NC MAPAR_OUT MAPAR_IN Notes: 1. 2. For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is used for DDR2. For MSC8254 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8254, connecting these pins to GND increases device power consumption. 3.5.2 3.5.2.1 HSSI-Related Pins HSSI Port Is Not Used The signal names in Table 44 and Table 45 are generic names for a RapidIO interface. For actual pin names refer to Table 1. Table 44. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used Signal Name SR_IMP_CAL_RX SR_IMP_CAL_TX SR[1–2]_REF_CLK SR[1–2]_REF_CLK SR[1–2]_RXD[3–0] SR[1–2]_RXD[3–0] SR[1–2]_TXD[3–0] SR[1–2]_TXD[3–0] SR[1–2]_PLL_AVDD SR[1–2]_PLL_AGND SXPVSS SXCVSS SXPVDD SXCVDD Note: Pin Connection NC NC SXCVSS SXCVSS SXCVSS SXCVSS NC NC In use In use In use In use In use In use All lanes in the HSSI SerDes should be powered down. Refer to the MSC8254 Reference Manual for details. 3.5.2.2 HSSI Specific Lane Is Not Used Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used Signal Name Pin Connection In use In use In use In use SR_IMP_CAL_RX SR_IMP_CAL_TX SR[1–2]_REF_CLK SR[1–2]_REF_CLK MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 61 Hardware Design Considerations Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used (continued) Signal Name SR[1–2]_RXDn SR[1–2]_RXDn SR[1–2]_TXDn SR[1–2]_TXDn SR[1–2]_PLL_AVDD SR[1–2]_PLL_AGND SXPVSS SXCVSS SXPVDD SXCVDD Note: The n indicates the lane number {0,1,2,3} for all unused lanes. Pin Connection SXCVSS SXCVSS NC NC in use in use in use in use in use in use 3.5.3 Note: RGMII Ethernet Related Pins Table 46 and Table 47 assume that the alternate function of the specified pin is not used. If the alternate function is used, connect the pin as required to support that function. Table 46. Connectivity of RGMII Related Pins When the RGMII Interface Is Not Used Signal Name Pin Connection GND NC GE1_RX_CTL GE2_TX_CTL Note: Assuming GE1 and GE2 are disabled in the reset configuration word. GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used, Table 47 lists the recommended management pin connections. Table 47. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used Signal Name GE_MDC GE_MDIO Pin Connection NC NC 3.5.4 TDM Interface Related Pins Table 48 lists the board connections of the TDM pins when an entire specific TDM is not used. For multiplexing options that select a subset of a TDM interface, use the connections described in Table 48 for those signals that are not selected. Table 48 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 48. Connectivity of TDM Related Pins When TDM Interface Is Not Used Signal Name TDMnRCLK TDMnRDAT TDMnRSYN Pin Connection GND GND GND MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 62 Freescale Semiconductor Hardware Design Considerations Table 48. Connectivity of TDM Related Pins When TDM Interface Is Not Used Signal Name TDMnTCLK TDMTnDAT TDMnTSYN VDDIO Notes: 1. 2. Pin Connection GND GND GND 2.5 V n = {0, 1, 2,3} In case of subset of TDM interface usage please make sure to disable unused TDM modules. See TDM chapter in the MSC8254 Reference Manual for details. 3.5.5 Miscellaneous Pins Table 49 lists the board connections for the pins not required by the system design. Table 49 assumes that the alternate function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function. Table 49. Connectivity of Individual Pins When They Are Not Required Signal Name CLKOUT EE0 EE1 GPIO[31–0] SCL SDA INT_OUT IRQ[15–0] NMI NMI_OUT RC[21–0] STOP_BS TCK TDI TDO TMR[4–0] TMS TRST URXD UTXD DDN[1–0] DRQ[1–0] RCW_LSEL_0 RCW_LSEL_1 RCW_LSEL_2 RCW_LSEL_3 VDDIO Pin Connection NC GND NC NC See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. NC See the GPIO connectivity guidelines in this table. VDDIO NC GND GND GND GND NC See the GPIO connectivity guidelines in this table. GND See Section 3.1 for guidelines. See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. See the GPIO connectivity guidelines in this table. GND GND GND GND 2.5 V Note: For details on configuration, see the MSC8254 Reference Manual. For additional information, refer to the MSC815x and MSC825x DSP Family Design Checklist. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 63 Ordering Information 3.6 Guide to Selecting Connections for Remote Power Supply Sensing To assure consistency of input power levels, some applications use a practice of connecting the remote sense signal input of an on-board power supply to one of power supply pins of the IC device. The advantage of using this connection is the ability to compensate for the slow components of the IR drop caused by resistive supply current path from on-board power supply to the pins layer on the package. However, because of specific device requirements, not every ball connection can be selected as the remote sense pin. Some of these pins must be connected to the appropriate power supply or ground to ensure correct device functionality. Some connections supply critical power to a specific high usage area of the IC die; using such a connection as a non-supply pin could impact necessary supply current during high current events. The following balls can be used as the board supply remote sense output without degrading the power and ground supply quality: • • • VDD: W10, T19 VSS: J18, Y10 M3VDD: None Do not use any other connections for remote sensing. Use of any other connections for this purpose can result in application and device failure. 4 Ordering Information Core Voltage 1.0 V Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Core Frequency (MHz) 1000 1000 800 800 Part MSC8254 Package Type Flip Chip Plastic Ball Grid Array (FC-PBGA) Spheres Lead-free Operating Temperature 0° C to 105°C –40° C to 105°C 0° C to 105°C –40° C to 105°C Order Number MSC8254SVT1000B MSC8254TVT1000B MSC8254SVT800B MSC8254TVT800B MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 64 Freescale Semiconductor Package Information 5 Package Information NOTES: 1. 2. 3. 4. 5. 6. 7. ALL DIMENSIONS IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. MAXIMUM SOLDER BALL DIAMETER MEASURE PARALLEL TO DATUM A. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. ALL DIMENSIONS ARE SYMMETRIC ACROSS THE PACKAGE CENTER LINES, UNLESS DIMENSIONED OTHERWISE. 29.2MM MAXIMUM PACKAGE ASSEMBLY (LID + LAMINATE) X AND Y. Figure 40. MSC8254 Mechanical Information, 783-ball FC-PBGA Package MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 65 Product Documentation 6 • • • • • • Product Documentation MSC8254 Technical Data Sheet (MSC8254). Details the signals, AC/DC characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the MSC8254 device. MSC8254 Reference Manual (MSC8254RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8254 device. QUICC Engine Block Reference Manual with Protocol Interworking (QEIWRM). Provides detailed information regarding the QUICC Engine technology including functional description, registers, and programming information. SC3850 DSP Core Reference Manual. Covers the SC3850 core architecture, control registers, clock registers, program control, and instruction set. MSC8156SC3850 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and registers. Following is a general list of supporting documentation: 7 Revision History Table 50. Document Revision History Table 50 provides a revision history for this data sheet. Rev. 0 1 2 Date Apr. 2010 May 2010 Dec 2010 • Initial public release. Description • Changed connection for pins K17, L14, L16, M15, M17, and N14 from VDD to VSS in Table 1. • Updated Section 3.1.2, Power-On Ramp Time. • Updated Table 16. • Updated Section 3.1.2, Power-On Ramp Time. • Updated Section 4, Ordering Information. MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 66 Freescale Semiconductor Revision History MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 2 Freescale Semiconductor 67 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. 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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale, the Freescale logo, CodeWarrior, and StarCore are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2008, 2010 Freescale Semiconductor, Inc. D ocument Number: MSC8254 Rev. 2 12/2010