PC35XS3400CPNA

Freescale Semiconductor Advance Information Document Number: MC35XS3400 Rev. 5.0, 10/2008 Quad High Side Switch (Quad 35mΩ) The 35XS3400 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(ON) MOSFETs (quad 35mΩ) can control four separate 28W bulbs, and/or LEDs. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew-rate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 35XS3400 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has Fail-safe mode to provide failsafe functionality of the outputs in case of MCU damaged. Features • Four protected 35mΩ high side switches (at 25°C) • Operating voltage range of 6.0V to 20V with standby current < 5.0μA, extended mode from 4.0V to 28V • 8MHz 16-bit 3.3V and 5V SPI control and status reporting with daisy chain capability • PWM module using external clock or calibratable internal oscillator with programmable outputs delay management • Smart over-current shutdown, severe short-circuit, overtemperature protections with time limited autoretry, and Fail-safe mode in case of MCU damage • Output OFF or ON open-load detection compliant to bulbs or LEDs and short to battery detection. Analog current feedback with selectable ratio and board temperature feedback. 35XS3400 HIGH SIDE SWITCH PNA SUFFIX (PB-FREE) 98ARL10596D 24-PIN PQFN ORDERING INFORMATION Device PC35XS3400CPNA Temperature Range (TA) - 40°C to 125°C Package 24 PQFN VDD VDD VPWR VDD VPWR 35XS3400 VDD I/O SCLK CS SI I/O MCU SO I/O I/O I/O I/O A/D GND WAKE FS SCLK CS SO RST SI IN0 IN1 IN2 IN3 CSNS FSI GND VPWR HS0 LOAD HS1 LOAD HS2 LOAD HS3 LOAD Figure 1. 35XS3400 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VDD VPWR IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3 VDD Failure Detection Internal Regulator VREG POR Over/Under-voltage Protections Charge Pump VPWR Voltage Clamp Selectable Slew Rate Gate Driver Selectable Over-current Detection Severe Short-circuit Detection Short to VPWR Detection Over-temperature Detection Open-load Detections HS0 Logic HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator VREG PWM Module HS1 HS2 HS2 HS3 FSI Programmable Watchdog Temperature Feedback Over-temperature Prewarning Analog MUX VDD HS3 Selectable Output Current Recopy GND CSNS Figure 2. 35XS3400 Simplified Internal Block Diagram 35XS3400 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS Transparent Top View of Package WAKE CSNS 1 24 14 GND 23 FSI GND 22 HS2 Definition This pin reports an analog value proportional to the designated HS[0:3] output current or the temperature of the GND flag (pin 14). It is used externally to generate a ground-referenced voltage for the microcontroller (MCU) . Current recopy and temperature feedback is SPI programmable. Each direct input controls the device mode. The IN[0 : 3] high side input pins are used to directly control HS0 : HS3 high side output pins. The PWM frequency can be generated from IN0 pin to PWM module in case the external clock is set. Output Input Input Input Input Input Power Fault Status (Active Low) Wake Reset Chip Select (Active Low) Serial Clock Serial Input Digital Drain Voltage This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. This input pin controls the device mode. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep mode. This input pin is connected to a chip select output of a master microcontroller (MCU). This input pin is connected to the MCU providing the required bit shift clock for SPI communication. This pin is a command data input pin connected to the SPI serial data output of the MCU or to the SO pin of the previous device of a daisy-chain of devices. This pin is an external voltage input pin used to supply power interfaces to the SPI bus. 35XS3400 SCLK VDD RST IN3 IN2 IN1 3 13 12 11 10 SO GND 16 17 9 8 7 6 5 4 HS3 18 15 VPWR 19 20 21 HS1 NC HS0 Figure 3. 35XS3400 Pin Connections Table 1. 35XS3400 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number 1 Pin Name CSNS Pin Function Output Formal Name Output Current Monitoring 2 3 5 6 7 8 9 10 11 12 13 IN0 IN1 IN2 IN3 FS WAKE RST CS SCLK SI VDD Input Direct Inputs Analog Integrated Circuit Device Data Freescale Semiconductor IN0 2 NC CS FS SI 3 PIN CONNECTIONS Table 1. 35XS3400 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 17. Pin Number 14, 17, 23 15 16 18 19 21 22 4, 20 24 Pin Name GND VPWR SO HS3 HS1 HS0 HS2 NC FSI Pin Function Ground Power Output Output Formal Name Ground Definition These pins, internally shorted, are the ground for the logic and analog circuitry of the device. These ground pins must be also shorted in the board. Positive Power Supply This pin connects to the positive power supply and is the source of operational power for the device. Serial Output High Side Outputs This output pin is connected to the SPI serial data input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. Protected 35mΩ high side power output pins to the load. N/A Input No Connect Fail-safe Input These pins may not be connected. This input enables the watchdog timeout feature. 35XS3400 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS VPWR Supply Voltage Range Load Dump at 25°C (400ms) Maximum Operating Voltage Reverse Battery at 25°C (2 min.) VDD Supply Voltage Range Input / Output Voltage WAKE Input Clamp Current CSNS Input Clamp Current HS [0:3] Voltage Positive Negative Output Current(1) Output Clamp Energy using single-pulse method(2) ESD Voltage(3) Human Body Model (HBM) for HS[0:3], VPWR and GND Human Body Model (HBM) for other pins Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature THERMAL RESISTANCE Thermal Resistance(5) Junction to Case Junction to Ambient Peak Pin Reflow Temperature During Solder Mounting (6) Symbol Value Unit VPWR(SS) 41 28 -18 VDD (4) V -0.3 to 5.5 -0.3 to VDD + 0.3 2.5 2.5 41 -16 V V mA mA V ICL(WAKE) ICL(CSNS) VHS[0:3] IHS[0:3] ECL [0:3] VESD1 VESD2 VESD3 VESD4 6 35 ± 8000 ± 2000 ± 750 ± 500 A mJ V °C TA TJ TSTG - 40 to 125 - 40 to 150 - 55 to 150 °C °C/ W RθJC RθJA TSOLDER VIH VPWR Supply Current Outputs commanded OFF, OFF Open-load Detection Disabled, IPWR(SBY) – IPWR(SLEEP) 6.0 8.0 μA VPWR(CLAMP) IPWR(ON) – 6.5 20 mA VPWR 6.0 4.0 41 – – 47 20 28 53 V mA V Symbol Min Typ Max Unit HS[0 : 3] shorted to the ground with VDD= 5.5V WAKE > VIH or RST > VIH and IN[0:3] < VIL Sleep State Supply Current VPWR = 12V, RST = WAKE = IN[0:3] < VIL, HS[0 : 3] shorted to the ground TA = 25°C TA = 85°C VDD Supply Voltage VDD Supply Current at VDD = 5.5V No SPI Communication 8.0MHz SPI Communication(9) VDD Sleep State Current at VDD = 5.5V Over-voltage Shutdown Threshold Over-voltage Shutdown Hysteresis Under-voltage Shutdown Threshold(10) VPWR and VDD Power on Reset Threshold VDD Supply Failure Threshold ( for VPWR > VPWR(UV) ) Recovery Under-voltage Threshold OUTPUTS HS0 TO HS3 Output Drain-to-Source ON Resistance (IHS = 2.0A, TA = 25°C) VPWR = 4.0V VPWR = 6.0V VPWR = 10V VPWR = 13V RDS(ON)_25 – – – – – – – – 100 55 35 35 mΩ IDD(SLEEP) VPWR(OV) VPWR(OVHYS) VPWR(UV) VSUPPLY(POR) VDD(FAIL) VPWR(UV)_UP VDD(ON) IDD(ON) – – – 28 0.2 3.3 0.5 2.2 3.4 1.6 5.0 – 32 0.8 3.9 – 2.5 4.1 2.2 – 5.0 36 1.5 4.3 0.9 2.8 4.5 μA V V V VPWR(UV) V V – – 3.0 1.0 – – 5.0 30 5.5 V mA Notes 7. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0V to 6.0V voltage range, the device is only protected with the thermal shutdown detection. 8. Measured with the outputs open. 9. Typical value guaranteed per design. 10. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the VPWR degradation level did not go below the under-voltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 35XS3400 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic OUTPUTS HS0 TO HS3 (Continued) Output Drain-to-Source ON Resistance (IHS = 2.0A, TA = 150°C) VPWR = 4.5V VPWR = 6.0V VPWR = 10V VPWR = 13V Output Source-to-Drain ON Resistance (IHS = -2.0A, VPWR = -18V T A = 2 5 °C TA = 150°C Maximum Severe Short-Circuit Impedance Detection(12) RSHORT OCHI1_0 OCHI2_0 OC1_0 OC2_0 OC3_0 OC4_0 OCLO4_0 OCLO3_0 OCLO2_0 OCLO1_0 CSR0 Current Recopy Accuracy with one calibration point (6.0V < VHS[0:3] < 20V)(14) Output Current 2.0A Current Sense Ratio (6.0V < HS[0:3] < 20V, CSNS < 5.0V)(13) CSNS_ratio bit = 0 CSNS_ratio bit = 1 Current Sense Ratio (CSR0) Accuracy (6.0V < VHS[0:3] < 20V) Output Current 6.75A 2.5A 1.5A 0.75A -12 -13 -16 -20 – – – – 12 13 16 20 CSR0_0 CSR1_0 CSR0_0_ACC – – 1/4300 1/25800 – – % CSR0_0_ACC(CAL) -5.0 – 5.0 – Output Over-current Detection Levels (6.0V < VHS[0:3] < 20V) 39.5 25.2 22 18.9 15.7 12.6 9.4 6.3 5.0 3.2 47 30 26.2 22.5 18.7 15 11.2 7.5 6.0 4.0 54.5 34.8 30.4 26.1 21.7 17.4 13.0 8.7 7.0 4.8 % )(11) RSD(ON) – – 70 – – 160 52.5 70 200 mΩ A RDS(ON)_150 – – – – – – – – 170 94 66 66 mΩ mΩ Symbol Min Typ Max Unit Notes 11. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 12. 13. 14. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design. Current sense ratio = ICSNS / IHS[0:3]. Based on statistical analysis, it is not production tested. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic OUTPUTS HS0 TO HS3 (continued) CSR0 Current Recopy Temperature Drift (6.0V < VHS[0:3] < 20V)(15) Output Current 2.0A Current Sense Ratio (CSR1) Accuracy (6.0V < VHS[0:3] < 20V) Output Current 6.25A 39.5A Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 2.0A with CSR0 ratio OFF Open-load Detection Source Current(16) OFF Open-load Fault Detection Voltage Threshold ON Open-load Fault Detection Current Threshold ON Open-load Fault Detection Current Threshold with LED VHS[0:3] = VPWR - 0.75V Output Short to VPWR Detection Voltage Threshold Output programmed OFF Output Negative Clamp Voltage 0.5A < IHS[0:3] < 5.0A, Output programmed OFF Output Over-temperature Shutdown for 4.5V < VPWR < 28V TSD VCL - 22 155 – 175 -16 195 VOSD(THRES) VPWR-1.2 VPWR-0.8 VPWR-0.4 V IOLD(OFF) VOLD(THRES) IOLD(ON) IOLD(ON_LED) 2.5 5.0 10 V VCL(CSNS) VDD+0.25 30 2.0 100 – – 3.0 300 VDD+1.0 100 4.0 600 μA V mA mA -17 -12 – – +17 +12 V CSR1_0_ACC 0.04 % Symbol Min Typ Max Unit Δ(CSR0_0)/Δ(T) %/°C °C Notes 15. Based on statistical data: delta(CSR0)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production tested. 16. Output OFF Open-load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open-load condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES) 35XS3400 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic CONTROL INTERFACE Input Logic High Voltage(17) Input Logic Low Voltage(17) Input Logic Pull-down Current (SCLK, SI)(20) Input Logic Pull-up Current (CS)(21) SO, FS Tri-state Capacitance(18) Input Logic Pull-down Resistor (RST, WAKE and IN[0:3]) Input Capacitance(18) Wake Input Clamp Voltage(19) ICL(WAKE) < 2.5mA Wake Input Forward Voltage ICL(WAKE) = -2.5mA SO High State Output Voltage IOH = 1.0mA SO and FS Low-state Output Voltage IOL = -1.0mA SO, CSNS and FS Tri-state Leakage Current CS = VIH and 0V < VSO < VDD, or FS = 5.5V, or CSNS=0.0V Symbol Min Typ Max Unit VIH VIL IDWN IUP CSO RDWN 2.0 -0.3 5.0 5.0 – 125 – 20 – – – – – 250 4.0 28 – VDD+0.3 0.8 20 20 20 500 12 35 V V μA μA pF kΩ pF V V CIN VCL(WAKE) VF(WAKE) - 2.0 VSOH VDD-0.4 VSOL – ISO(LEAK) - 2.0 RFS – 10 - 0.3 V – – 0 0 Infinite – V 0.4 μA 2.0 kΩ 1.0 – FSI External Pull-down Resistance(22) Watchdog Disabled Watchdog Enabled Notes 17. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 18. 19. 20. 21. 22. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0V. Pull-down current is with VSI > 1.0V and VSCLK > 1.0V. Pull-up current is with VCS < 2.0V. CS has an active internal pull-up to VDD. In Fail-Safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to VREG ~ 3.0V. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUT TIMING HS0 TO HS3 Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(23) VPWR = 14V Output Rising Slow Slew Rate (low speed slew rate / SR[1:0]=01)(23) VPWR = 14V Output Falling Fast Slew Rate (high speed slew rate / SR[1:0]=10)(23) VPWR = 14V Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0]=00)(23) VPWR = 14V Output Falling Slow Slew Rate (low speed slew rate / SR[1:0]=01)(23) VPWR = 14V Output Rising Fast Slew Rate (high speed slew rate / SR[1:0]=10)(23) VPWR = 14V Output Turn-ON Delay Time(24) VPWR = 14V for medium speed slew rate (SR[1:0]=00) Output Turn-OFF Delay Time(25) VPWR = 14V for medium speed slew rate (SR[1:0]=00) Driver Output Matching Slew Rate (SRR /SRF) VPWR = 14V @ 25°C and for medium speed slew rate (SR[1:0]=00) Driver Output Matching Time (t DLY(ON) - t DLY(OFF)) VPWR = 14V, f PWM = 240Hz, PWM duty cycle = 50%, @ 25°C for medium speed slew rate (SR[1:0]=00) Δ t RF -25 0 25 Δ SR 0.8 1.0 1.2 μs t DLY(ON) 35 60 60 85 μs 35 85 SRF_10 0.4 0.8 1.6 μs SRF_01 0.1 0.2 0.4 V/μs SRF_00 0.2 0.4 0.8 V/μs SRR_10 0.4 0.8 1.6 V/μs SRR_01 0.1 0.2 0.4 V/μs SRR_00 0.2 0.4 0.8 V/μs V/μs Symbol Min Typ Max Unit t DLY(OFF) Notes 23. Rise and Fall Slew Rates measured across a 5.0Ω resistive load at high side output = 30% to 70% (see Figure 4, page 14). 24. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3] and CS) that would turn the output ON to VHS[0 : 3] = VPWR / 2 with RL = 5.0Ω resistive load. 25. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3] and CS) that would turn the output OFF to VHS[0 : 3] =VPWR / 2 with RL = 5.0Ω resistive load. 35XS3400 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic POWER OUTPUT TIMING HS0 TO HS3 (CONTINUED) Fault Detection Blanking Time(26) Output Shutdown Delay Time(27) CS to CSNS Valid Time(28) Symbol Min Typ Max Unit tFAULT tDETECT – – – 217 105 3.4 1.0 1.4 2.0 3.4 8.4 31.2 1.72 0.56 0.72 1.02 1.56 4.28 15.4 6.8 2.2 2.8 4.0 6.8 17 6.24 13.7 4.5 5.9 8.1 13.7 34.2 124.9 5.0 7.0 70 310 150 5.0 1.72 2.0 3.0 5.0 12.2 44.6 2.48 0.8 1.04 1.58 2.24 6.12 22.2 9.8 3.2 4.2 5.8 9.8 24.4 89.2 19.6 6.4 8.4 11.6 19.6 48.8 178.4 20 30 100 400 195 6.6 2.0 2.6 4.0 6.74 16 48 3.22 1.04 1.36 1.92 2.92 7.96 29 12.8 4.2 5.6 7.6 12.8 31.8 116 25.5 8.3 10.9 15.1 25.5 63.4 231.9 μs μs μs ms ms ms t CNSVAL t WDTO TOLD(LED) tOC1_00 tOC2_00 tOC3_00 tOC4_00 tOC5_00 tOC6_00 tOC7_00 Watchdog Time-out(29) ON Open-load Fault Cyclic Detection Time with LED Output Over-current Time Step OC[1:0]=00 (slow by default) OC[1:0]=01 (fast) tOC1_01 tOC2_01 tOC3_01 tOC4_01 tOC5_01 tOC6_01 tOC7_01 OC[1:0]=10 (medium) tOC1_10 tOC2_10 tOC3_10 tOC4_10 tOC5_10 tOC6_10 tOC7_10 OC[1:0]=11 (very slow) tOC1_11 tOC2_11 tOC3_11 tOC4_11 tOC5_11 tOC6_11 tOC7_11 Notes 26. Time necessary to report the fault to FS pin. 27. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage = 50% of VPWR 28. 29. Time necessary for the CSNS to be with ±5% of the targeted value. For FSI open, the watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding input command. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Bulb Cooling Time Step CB[1:0]=00 or 11 (medium) tBC1_00 tBC2_00 tBC3_00 tBC4_00 tBC5_00 tBC6_00 CB[1:0]=01 (fast) tBC1_01 tBC2_01 tBC3_01 tBC4_01 tBC5_01 tBC6_01 CB[1:0]=10 (slow) tBC1_10 tBC2_10 tBC3_10 tBC4_10 tBC5_10 tBC6_10 PWM MODULE TIMING Input PWM Clock Range on IN0 Input PWM Clock Low Frequency Detection Range on IN0(30) Input PWM Clock High Frequency Detection Range on IN0(30) Output PWM Frequency Range Output PWM Frequency Accuracy using Calibrated Oscillator Default Output PWM Frequency using Internal Oscillator CS Calibration Low Minimum Time Detection Range CS Calibration Low Maximum Tine Detection Range Symbol Min 582 312 356 416 502 628 296 156 176 202 256 452 1166 624 714 834 1002 1256 Typ 834 448 510 596 718 898 418 224 254 290 360 648 1668 894 1022 1192 1434 1796 Max 1084 584 664 776 934 1168 544 292 332 378 468 884 2170 1164 1310 1552 1866 2340 Unit ms fIN0 fIN0(LOW) fIN0(HIGH) fPWM AFPWM(CAL) fPWM(0) t CSB(MIN) t CSB(MAX) RPWM_400 RPWM_200 RPWM_1k 7.68 1.0 100 – -10 84 14 140 10 5.0 6.0 175 105 – 2.0 200 – – 120 20 200 – – – 250 150 30.72 4.0 400 1.0 +10 156 26 260 98 98 94 325 195 kHz kHz kHz kHz % Hz μs μs % % % ms ms Output PWM Duty-cycle Range for fPWM = 400Hz(31) Output PWM Duty-cycle Range for fPWM = 200Hz(31) Output PWM Duty-cycle Range for fPWM = 1.0kHz for high speed slew rate(31) INPUT TIMING Direct Input Toggle Timeout AUTORETRY TIMING Autoretry Period tIN tAUTO Notes 30. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0]. 31. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle 100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming and the PWM on the output with RL = 5.0Ω resistive load. 35XS3400 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0V ≤ VPWR ≤ 20V, 3.0V ≤ VDD ≤ 5.5V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic TEMPERATURE ON THE GND FLAG Thermal Prewarning Detection(32) Analog Temperature Feedback at TA = 25°C with RCSNS=2.5kΩ Analog Temperature Feedback Derating with RCSNS=2.5kΩ(33) SPI INTERFACE CHARACTERISTICS(32) Maximum Frequency of SPI Operation Required Low State Duration for RST(34) Rising Edge of CS to Falling Edge of CS (Required Setup Time)(35) Rising Edge of RST to Falling Edge of CS (Required Setup Time)(35) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(35) Required High State Duration of SCLK (Required Setup Time)(35) Required Low State Duration of SCLK (Required Setup Time)(35) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(35) SI to Falling Edge of SCLK (Required Setup Time)(36) Falling Edge of SCLK to SI (Required Setup Time)(36) SO Rise Time CL = 80pF SO Fall Time CL = 80pF SI, CS, SCLK, Incoming Signal Rise Time(36) SI, CS, SCLK, Incoming Signal Fall Time(36) Time from Rising Edge of SCLK to SO Low Logic Level (37) Symbol Min Typ Max Unit TOTWAR TFEED DTFEED 110 1.15 -3.5 125 1.20 -3.7 140 1.25 -3.9 °C V mV/°C f SPI t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI (SU) t SI (HOLD) t RSO – 10 – – – – – – – – – – – – – – – – – – – – – – – – – 8.0 – 1.0 5.0 500 50 50 60 37 49 13 MHz μs μs μs ns ns ns ns ns ns ns ns t FSO – 13 13 13 60 60 t RSI t FSI t SO(EN) t SO(DIS) – – – – ns ns ns ns Time from Rising Edge of SCLK to SO High Logic Level(38) Notes 32. 33. 34. 35. 36. 37. 38. Parameters guaranteed by design. Value guaranteed per statistical analysis RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 35XS3400 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on CS. Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on CS. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS IN[0:3] high logic level low logic level CS high logic level low logic level VHS[0:3] VPWR RPWM 50%VPWR Time or Time Time VHS[0:3] 70% VPWR 30% VPWR t DLY(ON) t DLY(OFF) SR F Time SR R Figure 4. Output Slew Rate and Time Delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5. Over-current Shutdown Protection 35XS3400 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 tB C 1 t BC2 t BC3 t BC4 tB C5 tB C6 Previous OFF duration (toff) Figure 6. Bulb Cooling Management VIH VIH RSTB RST 10% V 0.2 VDD DD tWRST TwRSTB tENBL TCSB t CS VIL VIL TENBL 90% VDD 0.7VDD CS CSB 10% VDD 0.7VDD VIH VIH VIL VIL tTlead LEAD t WSCLKh TwSCLKh t RSI TrSI SCLK SCLK 90% VDD 0.7VDD 10% VDD 0.2VDD t LAG Tlag VIH VIH VIL VIL t TSIsu SI(SU) t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) tTfSI FSI Valid Don’t Care VIH VIH SI SI Don’t Care 90% VDD 0.7 VDD 0.2VDD 10% VDD Valid Don’t Care VIH VIL Figure 7. Input Timing Switching Characteristics 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS tRSI TrSI 90% VDD 3.5V tFSI TfSI VOH VOH 50% 1.0V 10% VDD VOL VOL SCLK SCLK t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD VOH VOH VOL VOL 0.2 VDD DD 10% V TrSO t RSO TVALID t VALID Low-to-High Low to High SO SO 90% V High to Low High-to-Low 0.7 VDD DD TfSO t FSO VVOH OH TdlyHL t SO(DIS) 0.2VDD 10% VDD VVOL OL Figure 8. SCLK Waveform and Valid SO Data Delay Time 35XS3400 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 35XS3400 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(ON) MOSFETs (quad 35 mΩ) can control four separate 28W bulbs. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slewrate improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation (PWM) control if desired. The 35XS3400 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush. The device has Fail-safe mode to provide fail-safe functionality of the outputs in case of MCU damaged. FUNCTIONAL PIN DESCRIPTION OUTPUT CURRENT MONITORING (CSNS) The Current Sense pin provides a current proportional to the designated HS0 : HS3 output or a voltage proportional to the temperature on the GND flag. That current is fed into a ground-referenced resistor (4.7kΩ typical) and its voltage is monitored by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI. DIRECT INPUTS (IN0, IN1, IN2, IN3) Each IN input wakes the device. The IN0 : IN3 high side input pins are also used to directly control HS0 : HS3 high side output pins. If the outputs are controlled by the PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels, and they have a passive internal pull-down, RDWN. the device is capable of transferring information to, and receiving information from, the MCU. The 35XS3400 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pull-up from VDD, IUP. SERIAL CLOCK (SCLK) The SCLK pin clocks the internal shift registers of the 35XS3400 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 9, page 20). SCLK input has an active internal pulldown, IDWN. FAULT STATUS (FS) This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin. WAKE The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10kΩ typ). This input has a passive internal pulldown, RDWN. SERIAL INPUT (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 35XS3400 are configured and controlled using a 5-bit addressing scheme described in Table 9, page 28. Register addressing and configuration are described in Table 10, page 28. SI input has an active internal pull-down, IDWN. RESET (RST) The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal pull-down, RDWN. DIGITAL DRAIN VOLTAGE (VDD) This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to Fail-safe mode. CHIP SELECT (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION GROUND (GND) These pins are the ground for the device. SCLK. SO reporting descriptions are provided in Table 22, page 32. POSITIVE POWER SUPPLY (VPWR) This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. HIGH SIDE OUTPUTS (HS3, HS1, HS0, HS2) Protected 35mΩ high side power outputs to the load. FAIL-SAFE INPUT (FSI) This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature. When the FSI pin is opened, the watchdog circuit is enabled. After a watchdog timeout occurs, the output states depends on IN[0:3]. When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:3] in case of VDD failure condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]). SERIAL OUTPUT (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of FUNCTIONAL INTERNAL BLOCK DESCRIPTION POWER SUPPLY MCU INTERFACE and OUTPUT CONTROL SPI INTERFACE PARALLEL CONTROL INPUTS MCU INTERFACE SELFPROTECTED HIGH SIDE SWITCHES HS0-HS3 PWM CONTROLLER POWER SUPPLY The 35XS3400 is designed to operate from 4.0V to 28V on the VPWR pin. Characteristics are provided from 6.0V to 20V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep mode. Applying VPWR and VDD to the device will place the device in the Normal mode. The device will transit to Fail-safe mode in case of failures on the SPI or/and on VDD voltage. bulbs and LED modules. 55W/65W lamps can be driven for two outputs shorted together. Those N-channel MOSFETs with 35mΩ RDS(ON) are self-protected and present extended diagnostics in order to detect bulb outage and short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line. When driving DC motor or solenoid loads demanding multiple switching, an external recirculation device must be used to maintain the device in its Safe Operating Area. MCU INTERFACE AND OUTPUT CONTROL In Normal mode, each bulb is controlled directly from the MCU through SPI. A pulse width modulation control module allows improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100Hz to 400Hz) and HIGH SIDE SWITCHES: HS0 – HS3 These pins are the high side outputs controlling automotive lamps located for the rear of vehicle, such as 28W 35XS3400 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION addressing the dimming application (day running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault conditions are: open load, short circuit to battery, short circuit to ground (over-current and severe short-circuit), thermal shutdown, and under/over- voltage. Thanks to accurate and configurable over-current detection circuitry and wire-harness optimization, the vehicle is lighter. In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL DEVICE OPERATION SPI PROTOCOL DESCRIPTION The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI / SO pins of the 35XS3400 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0V or 3.3V CMOS logic levels. CSB CS CS SCLK SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Notes 1. RST is a logic [1] state during the above operation. NOTES: 1. 2. D15isD0 relate state during therecent ordered entry of data into the device. RSTB : in a logic H to the most above operation. out of 2. 3. OD15D2, ... , and D15to the firstmostbits ofordered entry of program data into the LUX IC the device. DO, D1, : OD0 relate relate to the 16 recent ordered fault and status data device. Figure 9. Single 16-Bit Word SPI Communication 35XS3400 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES OPERATIONAL MODES The 35XS3400 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 5 and Figure 11 summarize details contained in succeeding paragraphs. The Figure 10 describes an internal signal called IN_ON[x] depending on IN[x] input. tIN Table 5. 35XS3400 Operating Modes Mode Sleep Normal wake-up 0 1 fail fault x 0 x 0 Comments Device is in Sleep mode. All outputs are OFF. Device is currently in Normal mode. Watchdog is active if enabled. Device is currently in Fail-safe mode due to watchdog timeout or VDD Failure conditions. The output states depend on the corresponding input in case FSI is open. Device is currently in Fault mode. The faulted output(s) is (are) OFF. The safe autoretry circuitry is active to turn-on again the output(s). IN[x] IN_ON[x] Fail-safe 1 1 0 Figure 10. IN_ON[x] internal signal The 35XS3400 transits to operating modes according to the following signals: • wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3], • fail = (VDD Failure and VDD_FAIL_en) or ( Watchdog time-out and FSI input not shorted to ground ), • fault = OC[0:3] or OT[0:3] or SC[0:3] or UV ( UV ) or ( OV and OV_dis ). Fault 1 X 1 x = Don’t care. (wake-up=0) (wake-up=1) and (fail=1) and (fault=0) (wake-up=0) (fail=1) and (wake-up=1) and (fault=1) Sleep (fail=0) and (wake-up=1) and (fault=0) (wake-up=1) and (fault=1) (wake-up=0) Fault (fail=0) and (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=0) Normal Fail-Safe (fail=1) and (wake-up=1) and (fault=0) (fail=0) and (wake-up=1) and (fault=0) (fail=1) and (wake-up=1) and (fault=0) Figure 11. Operating Modes SLEEP MODE The 35XS3400 is in Sleep mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 0, • fail = X, • fault = X. This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST and IN_ON[0:3] are logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0]. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES In the event of an external VPWR supply disconnect, an unexpected current consumption may sink on the VDD supply pin (In Sleep State). This current leakage is about 70mA instead of 5.0µA and it may impact the device reliability. The device recovers its normal operational mode once VPWR is reconnected. To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal Mode with RST pin set to logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0V on VDD supply pin to switch the device to Sleep State. Table 7. Output PWM Switching Delay Delay bits 000 001 010 011 100 101 110 111 Output delay no delay 16 PWM clock periods 32 PWM clock periods 48 PWM clock periods 64 PWM clock periods 80 PWM clock periods 96 PWM clock periods 112 PWM clock periods NORMAL MODE The 35XS3400 is in Normal mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = 0, • fault = 0. In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]). Programmable PWM module The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1]. The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The outputs HS[0:3] can be controlled in the range of 5% to 98% with a resolution of 7 bits of duty cycle (Table 6). The state of other IN pin is ignored. Table 6. Output PWM Resolution On bit 0 1 1 1 1 1 Duty cycle X 0000000 0000001 0000010 n 1111111 Output state OFF PWM (1/128 duty cycle) PWM (2/128 duty cycle) PWM (3/128 duty cycle) PWM ((n+1)/128 duty cycle) fully ON The clock frequency from IN0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and the CLOCK_fail bit reports [1]. Calibratable internal clock The internal clock can vary as much as +/-30 percent corresponding to typical fPWM(0) output switching period. Using the existing SPI inputs and the precision timing reference already available to the MCU, the 35XS3400 allows clock period setting within ±10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is provided by the MCU. The pulse is sent on the CS pin after the SPI word is launched. At the moment, the CS pin transitions from logic [1] to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128. CS SI CALR SI command ignored Internal clock duration In case of negative CS pulse is outside a predefined time range (from t CSB(MIN) to t CSB(MAX)), the calibration event will be ignored and the internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before. The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1]. The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of the light module (Table 7). 35XS3400 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FAIL-SAFE MODE The 35XS3400 is in Fail-safe mode when: • VPWR is within the normal voltage range, • wake-up = 1, • fail = 1, • fault = 0. Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:3] or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), the device will operate normally. Fail-safe Conditions If an internal watchdog time-out occurs before the WD bit for FSI open (Table 8) or in case of VDD failure condition (VDD< VDD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1] (see fail-safe to normal mode transition paragraph) and VDD is within the normal voltage range. Table 8. SPI Watchdog Activation Typical RFSI (Ω) 0 (shorted to ground) (open) Watchdog Disabled Enable To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-safe mode (autoretry included). FAULT MODE The 35XS3400 is in Fault mode when: • VPWR and VDD are within the normal voltage range, • wake-up = 1, • fail = X, • fault=1. This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up: •Over-temperature fault, •Over-current fault, •Severe short-circuit fault, •Output(s) shorted to VPWR fault in OFF state, •Open load fault in OFF state, •Over-voltage fault (enabled by default), •Under-voltage fault. The FS pin will automatically return to logic [1] when the fault condition is removed, except for over-current, severe short-circuit, over-temperature and under-voltage which will be reset by a new turn-on command (each fault_control signal to be toggled). Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication. The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS pin. During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value (except POR bit) and fault protections are fully operational. The Fail-safe mode can be detected by monitoring the NM bit is set to [0]. START-UP SEQUENCE The 35XS3400 enters in Normal mode after start-up if following sequence is provided: •VPWR and VDD power supplies must be above their under-voltage thresholds, •generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to Normal mode with SPI register content is reset (as defined in Table 10 and Table 22). All features of 35XS3400 will be available after 50μs typical and all SPI registers are set to default values (set to logic [0]). The UV fault is reported in the SPI status registers. And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock: •apply PWM clock on IN0 input pin after maximum 200μs (min. 50μs). If the correct start-up sequence is not provided, the PWM function is not guaranteed. NORMAL & FAIL-SAFE MODE TRANSITIONS Transition Fail-Safe to Normal mode To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included). Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0]. Transition Normal to Fail-safe Mode 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES PROTECTION AND DIAGNOSTIC FEATURES PROTECTIONS Over-temperature Fault The 35XS3400 incorporates over-temperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: •If the output command is ON: the corresponding output is latched OFF. FS will be also latched to logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. •If the output command is OFF: FS will go to logic [0] until the corresponding output temperature will be below TSD. For both cases, the fault register OT[0:3] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after a SPI read command. Over-current Fault The 35XS3400 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition. This protection is composed by eight predefined current levels (time dependent) to fit 28W bulb profiles. In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an autoretry define this event. In this case, the over-current protection will be fitted to inrush current, as shown in Figure 5. This over-current protection is programmable: OC[1:0] bits select over-current slope speed and OCHI1 current step can be removed in case the OCHI bit is set to [1]. levels are available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits. If the load current level ever reaches the over-current detection level, the corresponding output will latch the output OFF and FS will be also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. The SPI fault report (OC[0:3] bits) is removed after a read operation. In Normal mode using the internal PWM module, the 35XS3400 also incorporates a cooling bulb filament management, if the OC_mode is set to logic [1]. In this case, the 1st step of multi-step over-current protection will depend to the previous OFF duration, as illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits. Depending on toff depending to toff Over-current thresholds Cooling toff fault_control hson signal hson PWM Over-current thresholds Severe Short-Circuit Fault fault_control hson signal The 35XS3400 provides output shutdown in order to protect each output in case of severe short-circuit during of the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FS will go to logic [0] and the fault register SC[0:3] bit will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the corresponding output must be commanded OFF, and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition, if VDD = 0. hson PWM In steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC over-current 35XS3400 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES The SPI fault report (SC[0:3] bits) is removed after a read operation. Over-voltage Fault (Enabled by default) By default, the over-voltage protection is enabled. The 35XS3400 shuts down all outputs and FS will go to logic [0] during an over-voltage fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the over-voltage condition is removed (VPWR < VPWR(OV) VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read. The over-voltage protection can be disabled through SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any over-voltage condition (VPWR > VPWR(OV)). This over-voltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold. In Fail-safe mode, the over-voltage activation depends on the RST logic state; enable for RST = 1 and disable for RST = 0. The device is still protected with over-temperature protection in case the over-voltage feature is disabled. Under-voltage Fault The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the internal logic states within the device will remain (configuration and reporting). In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FS will go to logic [0], and the fault register UV bit will be set to [1]. Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP): •If the output command is OFF, FS will go to logic [1], but the UV bit will remain set to 1 until the next read operation (warning report). •If the output command is ON, FS will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0. In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the VPWR voltage does not drop any lower than 3.5V typical. All latched faults (over-temperature, over-current, severe short-circuit, over and under-voltage) are reset if: • VDD < VDD(FAIL) with VPWR in nominal voltage range, •VDD and VPWR supplies is below VSUPPLY(POR) voltage value. 35XS3400 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES (fault_control=0) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (fault_control=1 and OV=0) (OpenloadON=1) (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (SC=1) OFF if hson=0 (fault_control=0 or OV=1) ON if hson=1 Latched OFF (fault_control=0) (Retry=1) (count=16) (SC=1) (OpenloadON=1) (after Retry Period and OV=0) Autoretry OFF (OV=1) Autoretry ON if hson=1 (OpenloadOFF=1 or ShortVpwr=1 or OV=1) (fault_control=0) (Retry=1) => count=count+1 Figure 12. Auto-retry State Machine AUTO-RETRY The auto-retry circuitry is used to reactivate the output(s) automatically in case of over-current or over-temperature or under-voltage failure conditions to provide a high availability of the load. Auto-retry feature is available in Fault mode. It is activated in case of internal retry signal is set to logic [1]: retry[x] = OC[x] or OT[x] or UV. The feature retries to switch-on the output(s) after one auto-retry period (tAUTO) with a limitation in term of number of occurrence (16 for each output). The counter of retry occurrences is reset in case of Fail-safe to Normal or Normal to Fail-safe mode transitions. At each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush current. The Figure 12 describes the auto-retry state machine. status register after the internal gate voltage is pulled low enough to turn OFF the output. The OS[0:3] and OL_OFF[0:3] fault bits are set in the status register and FS pin reports in real time the fault. If the output shorted to VPWR fault is removed, the status register will be cleared after reading the register. The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:3] bit). Open-Load Faults The 35XS3400 incorporates three dedicated open-load detection circuitries on the output to detect in OFF and in ON state. Open-load Detection In Off State The OFF output open-load fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output open-load fault is latched into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:3] fault bit is set in the status register. If the open load fault is removed (FS output pin goes to high), the status register will be cleared after reading the register. The OFF output open-load protection can be disabled through SPI (OLOFF_DIS[0:3] bit). DIAGNOSTIC Output Shorted to VPWR Fault The 35XS3400 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if output voltage is higher than VOSD(THRES) and reported as a fault condition when the output is disabled (OFF). The output shorted to VPWR fault is latched into the 35XS3400 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES Open-load Detection In On State The ON output open-load current thresholds can be chosen by SPI to detect a standard bulbs or LEDs (OLLED[0:3] bit set to logic [1]). In cases where the load current drops below the defined current threshold, the OLON bit will be set to a logic [1], the output will stay ON and FS will not be disturbed. Open-load Detection In On State For Led Open load for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically each t OLLED (fully-on, D[6:0]=7F). To detect OLLED in fully-on state, the output must be ON at least t OLLED. To delatch the diagnosis, the condition should be removed and SPI read operation is needed (OL_ON[0:3] bit). The ON output open-load protection can be disabled through SPI (OLON_DIS[0:3] bit). Analog Current Recopy and Temperature Feedbacks The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits). In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The maximum current is 2mA typical. The typical value of external CSNS resistor connected to the ground is 4.7kΩ. The current recopy is not active in Fail-safe mode. Temperature Prewarning Detection In Normal mode, the 35XS3400 provides a temperature prewarning reported via SPI in case of the temperature of the GND flag is higher than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed. mode. No additional passive components are required except on VDD current path. GROUND DISCONNECT PROTECTION In the event the 35XS3400 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection (maximum VPWR=16V). A 10kΩ resistor needs to be added between the MCU and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings. LOSS OF SUPPLY LINES Loss of VDD If the external VDD supply is disconnected (or not within specification: VDD