PCIMX538DZK1C

Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53CEC Rev. 2, 5/2011 MCIMX53xD i.MX53xD Applications Processors for Consumer Products Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Case FC-PBGA PoP 12 x 12 mm Ordering Information See Table 1 on page 3 1 Introduction 1. The i.MX53xD multimedia application processor is Freescale Semiconductor’s latest addition to a growing family of multimedia-focused products offering high performance processing optimized for lowest power consumption. The i.MX53xD processor features Freescale’s advanced implementation of the ARM™ core, which operates at clock speeds as high as 1 GHz and interfaces with DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. This device is suitable for applications such as the following: • Tablets, high-end mobile internet devices (MID) • Smart mobile devices • Thin clients • Internet monitors, media phones, high-end portable media players (PMP) with HD video capability • Gaming consoles The flexibility of the i.MX53xD architecture allows for its use in a wide variety of applications. As the heart of 2. 3. 4. 5. 6. 7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17 4.2. Power Supplies Requirements and Restrictions . 25 4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4. Output Buffer Impedance Characteristics . . . . . . 35 4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 39 4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 46 4.7. External Peripheral Interfaces Parameters . . . . . . 68 4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 146 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 147 5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 147 5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 148 5.3. Power setup during Boot . . . . . . . . . . . . . . . . . . 149 Package Information and Contact Assignments . . . . . 150 6.1. 19x19 mm Package Information . . . . . . . . . . . . . 150 6.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169 6.3. PoP 12 x 12 mm Package on Package (PoP) Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Introduction the application chipset, the i.MX53xD processor provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays. Features of the i.MX53xD processor include the following: • Applications processor—The i.MX53xD processors boost the capabilities of high-tier portable applications by satisfying the ever increasing MIPS needs of operating systems and games. Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio decode. • Multilevel memory system—The multilevel memory system of the i.MX53xD is based on the L1 instruction and data caches, L2 cache, internal and external memory. The i.MX53xD supports many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND including eMMC up to rev 4.4. • Smart speed technology—The i.MX53xD device has power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product requiring levels of power far lower than industry expectations. • Multimedia powerhouse—The multimedia performance of the i.MX53xD processor ARM core is boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision floating point support) and vector floating point coprocessors. The system is further enhanced by a multistandard hardware video codec, autonomous image processing unit (IPU), SD and HD720p triple video (TV) encoder with triple video DAC, and a programmable smart DMA (SDMA) controller. • Powerful graphics acceleration—Graphics is the key to mobile game, navigation, web browsing, and other applications. The i.MX53xD processors provide two independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator (200 Mpix/s). • Interface flexibility—The i.MX53xD processor supports connection to a variety of interfaces, including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces (PATA, UART, I2C, and I2S serial audio, among others). • Advanced security—The i.MX53xD processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. For detailed information about the i.MX53xD security features contact a Freescale representative. The i.MX53xD application processor is a follow-on to the i.MX51, with improved performance, power efficiency, and multimedia capabilities. i.MX53xD Applications Processors for Consumer Products, Rev. 2 2 Freescale Semiconductor Introduction 1.1 Ordering Information Table 1. Ordering Information Case Tempera ture Range (°C) -20 to +85 -20 to +85 -20 to +85 -20 to +85 Table 1 provides ordering information. Part Number1 Mask Set Features Package2 PCIMX535DVV1C MCIMX535DVV1C PCIMX538DZK1C MCIMX538DZK1C 1 2 N78C N78C N78C N78C 1 GHz, full feature set 1 GHz, full feature set 1 GHz, full feature set 1 GHz, full feature set 19 x 19 mm, 0.8 mm pitch BGA Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch BGA Case TEPBGA-2 12 x 12 mm PoP 12 x 12 mm PoP Part numbers with a PC prefix indicate non production engineering parts. Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3. 1.2 Features The i.MX53xD multimedia applications processor (AP) is based on the ARM Platform, which has the following features: • MMU, L1 instruction and L1 data cache • Unified L2 cache • Target frequency of the core (including Neon, VFPv3 and L1 cache): 1 GHz • Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3 • TrustZone The memory system consists of the following components: • Level 1 cache: — Instruction (32 Kbyte) — Data (32 Kbyte) • Level 2 cache: — Unified instruction and data (256 Kbyte) • Level 2 (internal) memory: — Boot ROM, including HAB (64 Kbyte) — Internal multimedia/shared, fast access RAM (128 Kbyte) — Secure/non-secure RAM (16 Kbyte) i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 3 Introduction • External memory interfaces: — 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte — 32-bit LPDDR2 — 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC — 8/16-bit NOR Flash, PSRAM, and cellular RAM. — 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM. — 8-bit Asynchronous (DTACK mode) EIM interface. — All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot. — Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode) 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz. 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz. 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz. The i.MX53xD system is built around the following system on chip interfaces: • • • The i.MX53xD makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks. The i.MX53xD incorporates the following hardware accelerators: • VPU, version 3—video processing unit • GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance, 256 Kbyte RAM memory • GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance, • IPU, version 3M—image processing unit • ASRC—asynchronous sample rate converter The i.MX53xD includes the following interfaces to external devices: NOTE Not all interfaces are available simultaneously, depending on I/O multiplexer configuration. • Hard disk drives: — PATA, up to U-DMA mode 5, 100 MByte/s — SATA I, 1.5 Gbps Displays: — Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once. • i.MX53xD Applications Processors for Consumer Products, Rev. 2 4 Freescale Semiconductor Introduction • • • • — Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example, UXGA at 60 Hz). — LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA at 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60). Camera sensors: — Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency. Expansion cards: — Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4). USB — High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – High-speed host with integrated on-chip high-speed PHY – Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB Miscellaneous interfaces: — One-wire (OWIRE) port — Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer (AUDMUX) providing four external ports. — Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support 4-wire. — Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port — Three I2C ports, supporting 400 kbps — Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps — Two controller area network (FlexCAN) interfaces, 1 Mbps each — Sony Phillips Digital Interface (SPDIF), Rx and Tx — Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel — Key pad port (KPP) — Two pulse-width modulators (PWM) — GPIO with interrupt capabilities The system supports efficient and smart power control and clocking: • Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes • Power gating SRPG (State Retention Power Gating) for ARM core and Neon • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip oscillator amplifier supporting 32.768 kHz external crystal i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 5 Introduction • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) • Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features • Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches • Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine • SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator (TRNG) • Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure RAM and support for multiple keys as well as TZ/non-TZ separation • Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by e-fuses, and determines the security level operation mode as well as the TrustZone (TZ) policy • Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization NOTE The actual feature set depends on the part number as described in Table 1. Functions such as video hardware acceleration with 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. i.MX53xD Applications Processors for Consumer Products, Rev. 2 6 Freescale Semiconductor Architectural Overview 2 2.1 Architectural Overview Block Diagram The following subsections provide an architectural overview of the i.MX53xD processor system. Figure 1 shows the functional modules in the i.MX53xD processor system. Composite CVBS/ S-Video Component RGB, YCC (HD TV-Out / VGA) DDR2/DDR3/ LPDDR2 NOR/NAND Battery Ctrl Flash Device Camera Camera (2) (2) LVDS (WSXGA+) LCD LCD Display-1,2 Display (2) Digital Audio External Memory I/F (EXTMC) Application Processor Domain (AP) Internal RAM 144 KB Boot ROM 64 KB Debug DAP CTI (2) AXI and AHB Switch Fabric TPIU LDB TV-Encoder Temperature Sensor SATA / P-ATA HDD Smart DMA (SDMA) Image Processing Subsystem (IPU) ARM Cortex A8 Platform ARM Cortex A8 Neon, VFPv3 L1 I/D cache L2 cache 256 KB ETM, CTI0,1 Clock and Reset PLL (4) CCM GPC SRC XTALOSC(2) CAMP (2) AP Peripherals ECSPI CSPI UART (4) AUDMUX CAN i/f SPBA GPS Shared Peripherals eSDHCv2 (3) eSDHCv3 SSI ECSPI ESAI P-ATA SATA + Temp Mon SJC Security SAHARAv4 Lite RTICv3 SCCv2 SRTC CSU TZIC RF/IF UART SPDIF Rx/Tx ASRC Video Proc. Unit (VPU) 3D Graphics Proc. Unit (GPU3D) G-Memory 256 KB I2C (3) OWIRE PWM (2) IIM IOMUXC KPP GPIOx32 (7) SSI (2) FIRI FlexCAN (2) FEC(IEEE1588) RF / IF IC’s Audio, Power Mngmnt. Ethernet 10/100 Mbps Fuse Box Timers WDOG (2) GPT EPIT (2) 2D Graphics Proc. Unit (GPU2D) USB PHY1 USB PHY2 USB OTG + 3 HS Ports IrDA XVR Keypad Bluetooth WLAN JTAG (IEEE1149.1) MMC/SD eMMC/eSD USB OTG (dev/host) Access. Conn. Figure 1. i.MX53xD System Block Diagram NOTE The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 7 Modules List 3 Modules List Table 2. i.MX53xD Digital and Analog Blocks The i.MX53xD processor contains a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Block Mnemonic ARM Block Name ARM Platform Subsystem ARM Brief Description The ARM Cortex A8TM Platform consists of the ARM processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a 256 Kbyte L2 cache. The platform also contains an event monitor and debug modules. It also has a NEON coprocessor with SIMD media processing architecture, a register file with 32/64-bit general-purpose registers, an integer execute pipeline (ALU, Shift, MAC), dual single-precision floating point execute pipelines (FADD, FMUL), a load/store and permute pipeline and a non-pipelined vector floating point (VFP Lite) coprocessor supporting VFPv3. The asynchronous sample rate converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about –120 dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. ASRC Asynchronous Sample Rate Converter Multimedia Peripherals AUDMUX Digital Audio Multiplexer Multimedia Peripherals CAMP-1 CAMP-2 CCM GPC SRC CSPI ECSPI-1 ECSPI-2 CSU Clock Amplifier Clocks, Clock amplifier Resets, and Power Control Clocks, These modules are responsible for clock and reset distribution in the Resets, and system, as well as for system power management. Power Control The system includes four PLLs. Clock Control Module Global Power Controller System Reset Controller Configurable SPI, Enhanced CSPI Central Security Unit Connectivity Peripherals Security Full-duplex enhanced synchronous serial interface, with data rates 16-60 Mbit/s. It is configurable to support master/slave modes. In Master mode it supports four slave selects for multiple peripherals. The central security unit (CSU) is responsible for setting comprehensive security policy within the i.MX53xD platform, and for sharing security information between the various security modules. The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. i.MX53xD Applications Processors for Consumer Products, Rev. 2 8 Freescale Semiconductor Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic DEBUG Block Name Debug System Subsystem System Control Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (CTI), counters, and sequencers. debug access port (DAP) —The DAP provides real-time access for the debugger without halting the core to system memory, peripheral register, debug configuration registers and JTAG scan chains. The EXTMC is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel, slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel, internal memory (RAM, ROM) channel and graphical memory (GMEM) channel. In order to increase the bandwidth performance, the EXTMC separates the buffering and the arbitration between different channels so parallel accesses can occur. By separating the channels, slow accesses do not interfere with fast accesses. EXTMC Features: • 64-bit and 32-bit AXI ports • Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (read or write) was the last access • Flexible bank interleaving • Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2. • Support up to 2 GByte DDR memories. • Support NFC, EIM signal muxing scheme. • Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async operating modes), at slow frequency. (8-bit is not supported on D[23]-D[16]). • Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB Nand-Flash (including MLC) • Multiple chip selects (up to 4). • Enhanced DDR memory controller, supporting access latency hiding • Support watermark for security (internal and external memories) Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. The enhanced serial audio interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. The ESAI has 12 pins for data and clocking connection to external devices. EXTMC External Memory Connectivity Controller Peripherals EPIT-1 EPIT-2 Enhanced Timer Periodic Interrupt Peripherals Timer ESAI Enhanced Serial Audio Interface Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 9 Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic Block Name Subsystem Connectivity Peripherals Brief Description Ultra high-speed eMMC / SD host controller, enhanced to support eMMC 4.4 standard specification, for 832 MBps. • Port 3 is specifically enhanced to support eMMC 4.4 specification, for double data rate (832 Mbps, 8-bit port). ESDHCV3 is backward compatible to ESDHCV2 and supports all the features of ESDHCV2 as described below. Enhanced multimedia card / secure digital host controller • Ports 1, 2, and 4 are compatible with the “MMC System Specification” version 4.3, full support and supporting 1, 4 or 8-bit data. The generic features of the eSDHCv2 module, when serving as SD / MMC host, include the following: • Can be configured either as SD / MMC controller • Supports eSD and eMMC standard, for SD/MMC embedded type cards • Conforms to SD Host Controller Standard Specification, version 2.0, full support. • Compatible with the SD Memory Card Specification, version 1.1 • Compatible with the SDIO Card Specification, version 1.2 • Designed to work with SD memory, miniSD memory, SDIO, miniSDIO, SD Combo, MMC and MMC RS cards • Configurable to work in one of the following modes: - SD/SDIO 1-bit, 4-bit - MMC 1-bit, 4-bit, 8-bit • Full/high speed mode. • Host clock frequency variable between 32 kHz to 52 MHz • Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data lines • Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines Connectivity Peripherals The Ethernet media access controller (MAC) is designed to support both 10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The i.MX53xD also consists of HW assist for IEEE1588™ standard. See, TSU and CE_RTC (IEEE1588) section for more details. Fast infrared interface The controller area network (CAN) protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus. Meets the following specific requirements of this application: real-time processing, reliable operation in the EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. ESDHCV3-3 Ultra-HighSpeed eMMC / SD Host Controller ESDHCV2-1 Enhanced ESDHCV2-2 Multi-Media Card ESDHCv2-4 / Secure Digital Host Controller FEC Fast Ethernet Controller FIRI FLEXCAN-1 FLEXCAN-2 Fast Infrared Interface Flexible Controller Area Network Connectivity Peripherals Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 2 10 Freescale Semiconductor Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPIO-5 GPIO-6 GPIO-7 GPT Block Name Subsystem Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O. General Purpose System I/O Modules Control Peripherals General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. The GPU, version 3, provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. It supports color representation up to 32 bits per pixel. GPU enables high-performance mobile 3D and 2D vector graphics at rates up to 33 Mtriangles/s, 200 Mpix/s, 800 Mpix/s (z). The GPU2D version 1, provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 kbps are supported. The IC identification module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. IIM interfaces to the electrical fuse array (split to banks). Enabled to set up boot modes, security levels, security keys and many other system parameters. i.MX53xDA consists of 4 x 256-bit + 1x 128-bit fuse-banks (total 1152 bits) through IIM interface. GPU3D Graphics Processing Unit Multimedia Peripherals GPU2D Graphics Processing Unit-2D I2C Controller Multimedia Peripherals Connectivity Peripherals Security I2C-1 I2C-2 I2C-3 IIM IC Identification Module i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 11 Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic IOMUXC Block Name IOMUX Control Subsystem System Control Peripherals Multimedia Peripherals Brief Description This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. Version 3M IPU enables connectivity to displays, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces: • Legacy parallel interfaces • Single/dual channel LVDS display interface • Analog TV or VGA interfaces The processing includes: • Image enhancement—color adjustment and gamut mapping, gamma correction and contrast enhancement • Video/graphics combining • Support for display backlight reduction • Image conversion—resizing, rotation, inversion and color space conversion • Hardware de-interlacing support • Synchronization and control capabilities, allowing autonomous operation. The KPP supports an 8 × 8 external keypad matrix. The KPP features are as follows: • Open drain design • Glitch suppression circuit design • Multiple keys detection • Standby key press detection LVDS display bridge is used to connect the IPU (image processing unit) to external LVDS display interface. LDB supports two channels; each channel has following signals: • 1 clock pair • 4 data pairs On-chip differential drivers are provided for each pair. One-wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502. The PATA block is a AT attachment host interface. Its main use is to interface with hard disk drives and optical disc drives. It interfaces with the ATA-6 compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound. Internal RAM, shared with VPU. The on-chip memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. Supports secure and regular boot modes. The ROM controller supports ROM patching. IPU Image Processing Unit KPP Keypad Port Connectivity Peripherals LDB LVDS Display Bridge Connectivity Peripherals OWIRE PATA One-Wire Interface Parallel ATA Connectivity Peripherals Connectivity Peripherals PWM-1 PWM-2 Pulse Width Modulation Connectivity Peripherals INTRAM Internal RAM Internal Memory BOOTROM Boot ROM Internal Memory i.MX53xD Applications Processors for Consumer Products, Rev. 2 12 Freescale Semiconductor Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic RTIC Block Name Subsystem Brief Description Protecting read only data from modification is one of the basic elements in trusted platforms. The run-time integrity checker, version 3 (RTIC) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution. The RTIC mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The purpose of the RTIC is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement and assist with boot authentication. SAHARA (symmetric/asymmetric hashing and random accelerator), version 4, is a security coprocessor. It implements symmetric encryption algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and a hardware true random number generator. It has a slave IP Bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory. SATA HDD interface, includes the SATA controller and the PHY. It is a complete mixed-signal IP solution for SATA HDD connectivity. The security controller is a security assurance hardware module designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords and biometrics reference data. The SCCv2 monitors the system’s alert signal to determine if the data paths to and from it are secure, that is, it cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal RAM. The SCCv2 also features a key encryption module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing. The SDMA features list is as follows: • Powered by a 16-bit instruction-set micro-RISC engine • Multi-channel DMA supports up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between ARM and SDMA • Very fast context-switching with two-level priority-based preemptive multi-tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle unidirectional and bidirectional flows (copy mode) • Up to 8-word buffer for configurable burst transfers to / from the EXTMC • Support of byte swapping and CRC calculations • A library of scripts and API is available Run-Time Security Integrity Checker SAHARA SAHARA Security Accelerator Security SATA SCCv2 Serial ATA Security Controller, ver. 2 Connectivity Peripherals Security SDMA Smart Direct Memory Access System Control Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 13 Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic SECRAM SJC Block Name Subsystem Brief Description Secure / non-secure Internal RAM, controlled by SCC. JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus. The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden. In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX53xD processor incorporates a mechanism for regulating JTAG access. SJC provides four different JTAG security modes that can be selected through an e-fuse configuration. SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP bus) arbiter. A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Both transmitter and receiver functionalists are supported. The SRTC incorporates a special system state retention register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately even if all other supply rails are shut down. This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication). The SSI is a full-duplex synchronous interface used on the i.MX53xDA processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX for mapping to external ports. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously. Secure / Internal Non-secure RAM Memory Secure JTAG Interface System Control Peripherals SPBA Shared Peripheral Bus Arbiter Sony Philips Digital Interface Secure Real Time Clock System Control Peripherals Multimedia Peripherals Security SPDIF SRTC SSI-1 SSI-2 SSI-3 I2S/SSI/AC97 Interface Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 2 14 Freescale Semiconductor Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic IPTP Block Name IEEE1588 Precision Time Protocol Subsystem Connectivity Peripherals Brief Description The IEEE 1588-2002 (version 1) standard defines a precision time protocol (PTP) - which is a time-transfer protocol that enables synchronization of networks (for example, Ethernet), to a high degree of accuracy and precision. The IEEE1588 hardware assist is composed of the two blocks: time stamp unit and real time clock, which provide the timestamping protocol’s functionality, generating and reading the needed timestamps. The hardware-assisted implementation delivers more precise clock synchronization at significantly lower CPU load compared to purely software implementations. The temperature sensor is an internal module to the i.MX53xD that monitors the die temperature. The monitor is capable in generating SW interrupt, or trigger the CCM, to reduce the core operating frequency. The TV encoder, version 2.1 is implemented in conjunction with the image processing unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports composite PAL/NTSC, VGA, S-video, and component up to HD1080p analog video outputs. The TrustZone interrupt controller (TZIC) collects interrupt requests from all i.MX53xD sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported. Each of the UART blocks supports the following serial data transmit/receive protocols and configurations: • 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable bit-rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F standard. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • Option to operate as 8-pins full UART, DCE, or DTE USB supports USB2.0 480 MHz, and contains: • One high-speed OTG sub-block with integrated HS USB PHY • One high-speed host sub-block with integrated HS USB PHY • Two identical high-speed Host modules The high-speed OTG module, which is internally connected to the HS USB PHY, is equipped with transceiver-less logic to enable on-board USB connectivity without USB transceivers All the USB ports are equipped with standard digital interfaces (ULPI, HS IC-USB) and transceiver-less logic to enable onboard USB connectivity without USB transceivers. Temperature Monitor TVE (Part of SATA Block) TV Encoder System Control Peripherals Multimedia TZIC TrustZone Aware ARM/Control Interrupt Controller UART Interface Connectivity Peripherals UART-1 UART-2 UART-3 UART-4 UART-5 USB USB Controller Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 15 Modules List Table 2. i.MX53xD Digital and Analog Blocks (continued) Block Mnemonic VPU Block Name Subsystem Brief Description A high-performing video processing unit (VPU) version 3, which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring. VPU Features: • MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit rate • MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps bit rate • H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate • Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate • H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit rate • VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit rate • RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate • DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate • MJPEG decode, Baseline profile, up to 8192 x 8192 resolution, 40 Mpixel/s bit rate for 4:4:4 format • MPEG21 encode, Main-Main profile, up to D1 resolution, 15 Mbps bit rate • MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate2 • H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate2 • H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate2 • MJPEG encode, Baseline profile, up to 8192 x 8192 resolution, 80 Mpixel/s bit rate for 4:2:2 format The watch dog timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line. The TrustZone watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. Provides a crystal oscillator amplifier that supports a 24-MHz external crystal Provides a crystal oscillator amplifier that supports a 32.768-kHz external crystal. Video Processing Multimedia Unit Peripherals WDOG-1 Watch Dog Timer Peripherals WDOG-2 (TZ) Watch Dog (TrustZone) Timer Peripherals XTALOSC XTALOSC_ 32K 1 2 24 MHz Crystal Oscillator Clocking 32.768 KHz Clocking Crystal Oscillator I/F Video partially performed in hardware accelerator (70%) and partially in software. VPU can generate higher bit rate than the maximum specified by the corresponding standard. i.MX53xD Applications Processors for Consumer Products, Rev. 2 16 Freescale Semiconductor Electrical Characteristics 3.1 Special Signal Considerations The package contact assignments can be found in Section 6, “Package Information and Contact Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide. Document number is MX53UG. 4 Electrical Characteristics NOTE This electrical specification is preliminary. These specifications are not fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after thorough characterization and device qualifications have been completed. This section provides the device and module-level electrical characteristics for the i.MX53xD processor. 4.1 Chip-Level Conditions This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference to the individual tables and sections. Table 3. i.MX53xD Chip-Level Conditions For these characteristics, … Absolute Maximum Ratings TEPBGA-2 Package Thermal Resistance Data i.MX53xD Operating Ranges External Clock Sources Maximal Supply Currents USB Interface Current Consumption Topic appears … Table 4 on page 18 Table 5 on page 18 Table 7 on page 20 Table 8 on page 22 Table 9 on page 23 Table 10 on page 25 4.1.1 Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 4 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 7 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 17 Electrical Characteristics Table 4. Absolute Maximum Ratings Parameter Description Peripheral Core Supply Voltage ARM Core Supply Voltage Supply Voltage UHVIO Supply Voltage for non UHVIO USB VBUS Input voltage on USB_OTG_DP, USB_OTG_DN, USB_H1_DP, USB_H1_DN pins Input/Output Voltage Range ESD Damage Immunity: • Human Body Model (HBM) • Charge Device Model (CDM) Storage Temperature Range 1 2 Symbol VCC VDDGP Supplies denoted as I/O Supply Supplies denoted as I/O Supply VBUS USB_DP/USB_DN Vin/Vout Vesd Min –0.3 –0.3 –0.5 –0.5 — –0.3 –0.5 Max 1.35 1.35 3.6 3.3 5.25 3.631 OVDD +0.32 Unit V V V V V V V — — TSTORAGE –40 2000 500 150 V oC USB_DN and USB_DP can tolerate 5 V for up to 24 hours. The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in Table 112 on page 154. The maximum range can be superseded by the DC tables. 4.1.2 4.1.2.1 Thermal Resistance TEPBGA-2 Package Thermal Resistance Table 5. TEPBGA-2 Package Thermal Resistance Data Rating Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — — Symbol RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT Value 28 16 21 13 6 4 4 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 5 provides the TEPBGA-2 package thermal resistance data. Junction to Ambient (natural convection)1, 2 Junction to Ambient (natural convection)1, 2, 3 Junction to Ambient (at 200 ft/min)1, 3 Junction to Ambient (at 200 ft/min)1, 3 Junction to Board4 Junction to Case 5 Junction to Package Top (natural convection)6 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. i.MX53xD Applications Processors for Consumer Products, Rev. 2 18 Freescale Semiconductor Electrical Characteristics 3 4 Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.1.2.2 PoP Package Thermal Resistance Table 6. PoP Package Thermal Resistance Data1 Center Array of Pillars used for Ground 45 22 35 18 7.2