PK10X128VMJ150

Freescale Semiconductor Data Sheet: Product Preview Document Number: K10P81M100SF2 Rev. 1, 11/2010 K10 Sub-Family Data Sheet Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C K10P81M100SF2 Supports the following: MK10N512VLK100, MK10N512VMB100 • Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output • Analog modules – 16-bit SAR ADC with PGA (x64) – 12-bit DAC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference • Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timers – Two-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock • Communication interfaces – Controller Area Network (CAN) module – SPI modules – I2C modules – UART modules – Secure Digital host controller (SDHC) – I2S • Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz • Memories and memory interfaces – Up to 512 KB program flash memory on nonFlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface • Clocks – 1 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator • System peripherals – 10 low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 64 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit • Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Hardware random-number generator – 128-bit unique identification (ID) number per chip This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © 2010–2010 Freescale Semiconductor, Inc. Preliminary Pr el im in ar y Table of Contents 1 Ordering parts...........................................................................4 1.1 Determining valid orderable parts......................................4 2 Part identification......................................................................4 2.1 Description.........................................................................4 2.2 Format...............................................................................4 2.3 Fields.................................................................................4 2.4 Example............................................................................5 3 Terminology and guidelines......................................................5 3.1 Definition: Operating requirement......................................5 3.2 Definition: Operating behavior...........................................6 3.3 Definition: Attribute............................................................6 6.3.3 6.1 Core modules....................................................................19 6.1.1 6.1.2 Debug trace timing specifications.........................19 JTAG electricals....................................................20 6.2 System modules................................................................23 6.3 Clock modules...................................................................23 6.3.1 6.3.2 MCG Specifications...............................................23 Oscillator Electrical Characteristics.......................25 6.3.2.1 6.3.2.2 Oscillator DC Electrical Specifications 25 Oscillator frequency specifications......26 3.4 Definition: Rating...............................................................7 3.5 Result of exceeding a rating..............................................7 3.6 Relationship between ratings and operating requirements......................................................................7 3.7 Guidelines for ratings and operating requirements............8 3.8 Definition: Typical value.....................................................8 3.9 Typical Value Conditions...................................................9 4 Ratings......................................................................................9 4.1 Thermal handling ratings...................................................9 4.2 Moisture handling ratings..................................................10 4.3 ESD handling ratings.........................................................10 4.4 Voltage and current operating ratings...............................10 5 General.....................................................................................11 5.1 Nonswitching electrical specifications...............................11 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Voltage and Current Operating Requirements......11 LVD and POR operating requirements.................12 Voltage and current operating behaviors..............13 Power mode transition operating behaviors..........13 Power consumption operating behaviors..............14 5.1.5.1 Diagram: Typical IDD_RUN operating behavior...............................................16 5.1.6 5.1.7 5.1.8 EMC radiated emissions operating behaviors.......17 Designing with radiated emissions in mind...........18 Capacitance attributes..........................................18 6.6.2 6.6.3 5.2 Switching electrical specifications.....................................18 5.3 Thermal specifications.......................................................18 5.3.1 5.3.2 Thermal operating requirements...........................18 Thermal attributes.................................................19 6.6.4 6 Peripheral operating requirements and behaviors....................19 2 Pr el im in ar y 6.3.3.1 6.3.3.2 6.4.1 6.4.1.1 6.4.1.2 6.4.1.3 6.4.1.4 6.4.2 6.4.3 6.6.1 6.6.1.1 6.6.1.2 6.6.1.3 6.6.1.4 6.6.3.1 6.6.3.2 32kHz Oscillator Electrical Characteristics............27 32kHz Oscillator DC Electrical Specifications......................................27 32kHz Oscillator Frequency Specifications......................................27 6.4 Memories and memory interfaces.....................................28 Flash (FTFL) Electrical Characteristics.................28 Flash Timing Parameters — Program and Erase............................................28 Flash Timing Parameters — Commands..........................................28 Flash (FTFL) Current and Power Parameters..........................................29 Reliability Characteristics....................29 EzPort Switching Specifications............................29 Flexbus Switching Specifications..........................30 6.5 Security and integrity modules..........................................32 6.6 Analog...............................................................................32 ADC electrical specifications.................................32 16-bit ADC operating conditions..........33 16-bit ADC electrical characteristics....35 16-bit ADC with PGA operating conditions............................................38 16-bit ADC with PGA characteristics...39 CMP and 6-bit DAC electrical specifications.........40 12-bit DAC electrical characteristics.....................41 12-bit DAC operating requirements.....41 12-bit DAC operating behaviors..........42 Voltage Reference Electrical Specifications..........44 6.7 Timers................................................................................45 6.8 Communication interfaces.................................................45 K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. 6.8.1 DSPI Switching Specifications for Low-speed Operation..............................................................46 6.9.2 TSI Electrical Specifications..................................52 7 Dimensions...............................................................................53 7.1 Obtaining package dimensions.........................................53 8 Pinout........................................................................................54 8.1 K10 Signal Multiplexing and Pin Assignments..................54 8.2 K10 Pinouts.......................................................................57 9 Revision History........................................................................58 6.8.2 DSPI Switching Specifications (High-speed mode)....................................................................47 6.8.3 6.8.4 SDHC Specifications.............................................49 I2S Switching Specifications.................................50 6.9 Human-machine interfaces (HMI)......................................52 6.9.1 General Switching Specifications..........................52 Freescale Semiconductor, Inc. Pr el im in ar y K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 3 Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: Q K## M FFF T PP CCC N 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q K## M Qualification status Kinetis family Flash memory type Description Values • M = Fully qualified, general market flow • P = Prequalification • K10 • N = Program flash only • X = Program flash and FlexMemory Table continues on the next page... 4 Pr el im in ar y K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Terminology and guidelines Field FFF Description Program flash memory size • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB Values T PP Temperature range (°C) Package identifier • V = –40 to 105 • • • • • • • • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) FX = 64 QFN (9 mm x 9 mm) LH = 64 LQFP (10 mm x 10 mm) LK = 80 LQFP (12 mm x 12 mm) MB = 81 MAPBGA (8 mm x 8 mm) LL = 100 LQFP (14 mm x 14 mm) ML = 104 MAPBGA (8 mm x 8 mm) LQ = 144 LQFP (20 mm x 20 mm) MD = 144 MAPBGA (13 mm x 13 mm) MF = 196 MAPBGA (15 mm x 15 mm) MJ = 256 MAPBGA (17 mm x 17 mm) 50 = 50 MHz 72 = 72 MHz 100 = 100 MHz 120 = 120 MHz 150 = 150 MHz CCC Maximum CPU frequency (MHz) N Packaging type 2.4 Example This is an example part number: MK10N512VMD100 3 Terminology and guidelines 3.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Freescale Semiconductor, Inc. Pr el im in ar y • R = Tape and reel • (Blank) = Trays K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 5 Terminology and guidelines 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply volt‐ age 0.9 Min. 1.1 Max. V Unit 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol IWP Description Min. Max. Unit Digital I/O weak pullup/ 10 pulldown current 130 µA 3.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 3.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digi‐ — tal pins Min. 7 Max. pF Unit 6 Pr el im in ar y K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. This is an example of an operating rating: Symbol VDD Description 1.0 V core supply volt‐ age –0.3 Pr el im in ar y Min. Max. 1.2 V The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating rating 3.4.1 Example Unit 3.5 Result of exceeding a rating 40 Failures in time (ppm) 30 20 10 0 Measured characteristic K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 7 Terminology and guidelines 3.6 Relationship between ratings and operating requirements g tin h or an dlin g in rat g( mi n.) ing ui req in. (m nt me re ) ui req ax (m nt me re .) h or g dlin an ( ing rat x.) ma g g tin Op era Op t era era Op tin era Op Fatal range - Probable permanent failure Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Normal operating range - No permanent failure - Correct operation Limited operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range - Probable permanent failure Handling range - No permanent failure –ȡ Pr el im in ar y Description Min. 10 70 Typ. 130 Max. µA ȡ 3.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol IWP Unit Digital I/O weak pullup/pulldown current K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 8 Preliminary Freescale Semiconductor, Inc. Ratings 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 3500 IDD_STOP (μA) 3000 2500 2000 1500 1000 500 0 0.90 TJ 3.9 Typical Value Conditions Typical values assume you meet the following conditions (or other conditions as specified): Symbol TA VDD Description Value Unit Ambient temperature 3.3 V supply voltage 25 3.3 °C V 4 Ratings Freescale Semiconductor, Inc. Pr el im in ar y 105 °C 25 °C –40 °C 0.95 1.00 1.05 1.10 VDD (V) 150 °C K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 9 Ratings 4.1 Thermal handling ratings Symbol TSTG TSDR Description Storage temperature Solder temperature, lead-free Solder temperature, leaded Min. –55 — — Max. 150 260 245 Unit °C °C Notes 1 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Pr el im in ar y Min. — Max. 3 Unit — Min. Max. Unit V V -2000 -500 -100 +2000 +500 +100 mA Min. –0.3 — –0.3 –0.3 Max. 3.8 185 5.5 VDD + 0.3 Table continues on the next page... Notes 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol VHBM VCDM ILAT Description Notes 1 2 Electrostatic discharge voltage, human body model Electrostatic discharge voltage, charged-device model Latch-up current at ambient temperature of 85°C 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4.4 Voltage and current operating ratings Symbol VDD IDD VDIO VAIO Description Digital supply voltage Digital supply current Digital input voltage (except RESET, EXTAL, and XTAL) Analog, RESET, EXTAL, and XTAL input voltage Unit V mA V V K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 10 Preliminary Freescale Semiconductor, Inc. General Symbol ID VDDA IDDA VBAT VRAM VRFVBAT Description Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage Analog supply current1 RTC battery supply voltage VDD voltage required to retain RAM VBAT voltage required to retain the VBAT register file Min. –25 VDD – 0.3 TBD –0.3 1.2 TBD Max. 25 VDD + 0.3 TBD 3.8 — — Unit mA V mA V V V 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 5 General 5.1 Nonswitching electrical specifications 5.1.1 Voltage and Current Operating Requirements Symbol VDD VDDA Description Min. Pr el im in ar y Table 1. Voltage and current operating requirements Max. 3.6 3.6 0.1 0.1 1.71 1.71 –0.1 –0.1 Unit V V V V 0.7 × VDD — — V 0.75 × VDD V — — 0.06 × VDD Table continues on the next page... 0.35 × VDD 0.3 × VDD — V V V Notes Supply voltage Analog supply voltage VDD – VDDA VDD-to-VDDA differential voltage VSS – VSSA VSS-to-VSSA differential voltage VIH Input high voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VIL Input low voltage • 2.7 V ≤ VDD ≤ 3.6 V • 1.7 V ≤ VDD ≤ 2.7 V VHYS Input hysteresis K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 11 General Table 1. Voltage and current operating requirements (continued) Symbol IIC Description DC injection current — single pin • VIN > VDD • VIN < VSS DC injection current — total MCU limit, includes sum of all stressed pins • VIN > VDD • VIN < VSS 0 0 2 –0.2 mA mA 1 0 0 25 –5 mA mA Min. Max. Unit Notes 1 5.1.2 LVD and POR operating requirements Symbol VPOR VLVDH Description Min. Pr el im in ar y Table 2. LVD and POR operating requirements Typ. 1.1 TBD TBD Max. TBD TBD V V 2.56 TBD TBD TBD TBD 2.70 2.80 2.90 3.00 60 TBD TBD TBD TBD TBD TBD TBD V V V V V TBD TBD TBD TBD 1.80 1.90 2.00 2.10 TBD TBD TBD TBD V V V V Table continues on the next page... 1. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Unit Notes Falling VDD POR detect voltage Falling low-voltage detect threshold — high range (LVDV=01) Low-voltage warning thresholds — high range VLVW1 VLVW2 VLVW3 VLVW4 VHYS VLVDL • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) 1 Low-voltage inhibit reset/recover hysteresis — high range Falling low-voltage detect threshold — low range (LVDV=00) Low-voltage warning thresholds — low range mV 1 VLVW1 VLVW2 VLVW3 VLVW4 • Level 1 falling (LVWV=00) • Level 2 falling (LVWV=01) • Level 3 falling (LVWV=10) • Level 4 falling (LVWV=11) K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 12 Preliminary Freescale Semiconductor, Inc. General Table 2. LVD and POR operating requirements (continued) Symbol VHYS VBG tLPO Description Low-voltage inhibit reset/recover hysteresis — low range Bandgap voltage reference Internal low power oscillator period factory trimmed 1. Rising thresholds are falling threshold + VHYS TBD TBD Min. Typ. 40 1.00 1000 TBD TBD Max. Unit mV V μs Notes 5.1.3 Voltage and current operating behaviors Symbol VOH Description Min. Pr el im in ar y Table 3. Voltage and current operating behaviors Max. Unit VDD – 0.5 VDD – 0.5 — — V V VDD – 0.5 VDD – 0.5 — — — V V 100 mA — — 0.5 0.5 V V — — — — — 30 0.5 0.5 V V 100 1 1 50 mA μA μA kΩ Notes Output high voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA Output high voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA IOHT VOL Output high current total for all ports Output low voltage — high drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA Output low voltage — low drive strength • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA IOLT IIN IOZ RPU and RPD Output low current total for all ports Input leakage current (per pin) Hi-Z (off-state) leakage current (per pin) Internal weak pullup and pulldown resistors 1 1. Measured at VIL max and VDD min K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 13 General 5.1.4 Power mode transition operating behaviors In the table below, all specifications except tPOR, assume the following clock configuration: • CPU and system clocks = 100MHz • Bus and FlexBus clocks = 50 MHz • Flash clock = 25 MHz Table 4. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.8V to execution of the first instruction across the operating temperature range of the chip. RUN → VLLS1 → RUN • RUN → VLLS1 • VLLS1 → RUN Min. — Max. 300 Unit μs Notes 1 RUN → VLLS2 → RUN • RUN → VLLS2 • VLLS2 → RUN RUN → VLLS3 → RUN • RUN → VLLS3 • VLLS3 → RUN RUN → LLS → RUN • RUN → LLS • LLS → RUN RUN → STOP → RUN • RUN → STOP • STOP → RUN RUN → VLPS → RUN • RUN → VLPS • VLPS → RUN 1. Normal boot (FTFL_OPT[LPBOOT]=1) 14 Pr el im in ar y — — 4.1 μs μs 123.8 — — 4.1 μs μs 49.3 — — 4.1 μs μs 49.2 — — 4.1 5.9 μs μs — — 4.1 4.2 μs μs — — 4.1 5.8 μs μs K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. General 5.1.5 Power consumption operating behaviors Table 5. Power consumption operating behaviors Symbol IDD_RUN Description Run mode current — all peripheral clocks disa‐ bled, code executing from flash • @ 1.8V • @ 3.0V IDD_RUN Run mode current — all peripheral clocks ena‐ bled, code executing from flash • @ 1.8V • @ 3.0V — — 55 56 TBD TBD mA mA 3 — — 40 42 TBD TBD mA mA 2 Min. Typ. Max. Unit Notes 1 IDD_RUN_M Run mode current — all peripheral clocks ena‐ bled and peripherals active, code executing from AX flash • @ 1.8V • @ 3.0V IDD_WAIT IDD_STOP IDD_VLPR IDD_VLPR IDD_VLPW IDD_VLPS IDD_LLS IDD_VLLS3 Wait mode current at 3.0 V — all peripheral clocks disabled Stop mode current at 3.0 V Pr el im in ar y — — — — — — — — — 85 85 TBD TBD TBD TBD TBD TBD TBD TBD TBD 15 1.4 1.25 TBD 1.05 30 12 μA μA — — — — 8 TBD TBD TBD TBD μA 4 2 550 μA μA nA mA mA mA mA mA mA mA 5 6 7 4 Very-low-power run mode current at 3.0 V — all peripheral clocks disabled Very-low-power run mode current at 3.0 V — all peripheral clocks enabled Very-low-power wait mode current at 3.0 V Very-low-power stop mode current at 3.0 V Low leakage stop mode current at 3.0 V Very low-leakage stop mode 3 current at 3.0 V • 128KB RAM devices IDD_VLLS2 IDD_VLLS1 IDD_VBAT Very low-leakage stop mode 2 current at 3.0 V Very low-leakage stop mode 1 current at 3.0 V Average current when CPU is not accessing RTC registers at 3.0 V 1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, but peripherals are not in active operation. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled, and peripherals are in active operation. 4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. Code executing from flash. 6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 15 General 7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled. 5.1.5.1 • • • • • Diagram: Typical IDD_RUN operating behavior The following data was measured under these conditions: MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks disabled except FTFL LVD disabled No GPIOs toggled Code execution from flash Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled The following data was measured under these conditions: • • • • • 16 MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE) All peripheral clocks enabled but peripherals are not in active operation LVD disabled No GPIOs toggled Code execution from flash K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Pr el im in ar y General Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled 5.1.6 EMC radiated emissions operating behaviors Symbol VRE1 VRE2 VRE3 VRE4 Description Frequency band (MHz) 0.15–50 50–150 150–500 500–1000 0.15–1000 Pr el im in ar y Table 6. EMC radiated emissions operating behaviors Typ. Unit TBD TBD TBD TBD TBD — dBμV Notes 1, 2 Radiated emissions voltage, band 1 Radiated emissions voltage, band 2 Radiated emissions voltage, band 3 Radiated emissions voltage, band 4 VRE_IEC_SAE IEC and SAE level 2, 3 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/ Wideband TEM (GTEM) Cell Method. 2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 20 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 17 General 5.1.7 Designing with radiated emissions in mind 1. To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.freescale.com and perform a keyword search for “EMC design.” 5.1.8 Capacitance attributes Table 7. Capacitance attributes Symbol CIN_A CIN_D Description Pr el im in ar y Min. — — Max. 7 7 Unit pF pF Input capacitance: analog pins Input capacitance: digital pins 5.2 Switching electrical specifications Symbol Description Table 8. Device clock specifications Min. Normal run mode Max. Unit Notes fSYS fBUS FB_CLK fFLASH System and core clock Bus clock — — — — 100 50 50 25 MHz MHz MHz MHz FlexBus clock Flash clock VLPR mode fSYS fBUS FB_CLK fFLASH System and core clock Bus clock — — — — 2 2 2 1 MHz MHz MHz MHz FlexBus clock Flash clock 5.3 Thermal specifications K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 18 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 5.3.1 Thermal operating requirements Table 9. Thermal operating requirements Symbol TJ TA Description Die junction temperature Ambient temperature Min. –40 –40 Max. 125 105 Unit °C °C 5.3.2 Thermal attributes Singlelayer (1s) Four-layer (2s2p) Singlelayer (1s) Four-layer (2s2p) — — — RθJA RθJA RθJMA RθJMA RθJB RθJC ΨJT Pr el im in ar y Thermal resistance, junction to ambient (natural convection) TBD TBD °C/W Thermal resistance, junction to ambient (natural convection) TBD TBD °C/W Thermal resistance, junction to ambient (200 ft./ min. air speed) TBD TBD TBD TBD °C/W °C/W Thermal resistance, junction to ambient (200 ft./ min. air speed) Thermal resistance, junction to board Thermal resistance, junction to case TBD TBD °C/W TBD TBD °C/W Thermal characterization parameter, junction to package top outside center (natural convection) TBD TBD °C/W Board type Symbol Description 81 80 LQFP Unit MAPBGA Notes 1 1 1 1 2 3 4 6 Peripheral operating requirements and behaviors 6.1 Core modules Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions —Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 1. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 19 Peripheral operating requirements and behaviors 6.1.1 Debug trace timing specifications Table 10. Debug trace operating behaviors Symbol Tcyc Twl Twh Tr Tf Ts Th Description Clock period Low pulse width High pulse width Clock and data rise time Clock and data fall time Data setup Data hold Min. Max. Unit MHz ns ns ns ns ns ns Frequency dependent 2 2 — — 3 2 — — 3 3 — — TRACE_CLKOUT TRACE_D[3:0] 6.1.2 JTAG electricals Symbol Description Operating voltage J1 Pr el im in ar y Figure 3. TRACE_CLKOUT specifications Ts Th Ts Th Figure 4. Trace data specifications Table 11. JTAG electricals Min. 2.7 Max. 3.6 Unit V MHz 0 0 1/J1 Table continues on the next page... 25 50 — ns TCLK frequency of operation • JTAG and CJTAG • Serial Wire Debug J2 TCLK cycle period K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 20 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 11. JTAG electricals (continued) Symbol J3 Description TCLK clock pulse width • JTAG and CJTAG • Serial Wire Debug J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output high-Z 20 10 — 20 0 — — — — 3 — — 30 30 — — 4 4 ns ns ns ns ns ns ns ns ns ns ns Min. Max. Unit ns TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO high-Z TRST assert time TRST setup time (negation) to TCLK high TCLK (input) Freescale Semiconductor, Inc. Pr el im in ar y 16 1 — — 100 8 — — J2 J3 J3 J4 J4 Figure 5. Test clock input timing K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 21 Peripheral operating requirements and behaviors TCLK J5 J6 Data inputs J7 Input data valid Data outputs J8 Output data valid Data outputs Data outputs TCLK TDI/TMS TDO TDO J11 TDO 22 Pr el im in ar y J7 Output data valid Figure 6. Boundary scan (JTAG) timing J9 J10 Input data valid J11 Output data valid J12 Output data valid Figure 7. Test Access Port timing K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 8. TRST timing There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG Specifications Symbol fints_ft fints_t tirefsts Δfdco_res_t Description Pr el im in ar y Table 12. MCG specifications Min. — Typ. Max. — 32.768 — 31.25 — — 39.0625 4 TBD µs ± 0.1 ± 0.3 — ± 0.2 ± 0.5 — + 0.5 - 1.0 — ± 0.5 ± TBD ± 3.5 3.875 3 4 — 4.125 5 Table continues on the next page... 6.2 System modules Unit kHz kHz Notes Internal reference frequency (slow clock) — facto‐ ry trimmed at nominal VDD and 25°C Internal reference frequency (slow clock) — user trimmed Internal reference (slow clock) startup time Resolution of trimmed DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM %fdco Δfdco_res_t Resolution of trimmed DCO output frequency at fixed voltage and temperature — using SCTRIM only Δfdco_t Δfdco_t %fdco Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0– 70°C Internal reference frequency (fast clock) — factory trimmed at nominal VDD and 25°C Internal reference frequency (fast clock) — user trimmed %fdco %fdco fintf_ft fintf_t MHz MHz K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 23 Peripheral operating requirements and behaviors Table 12. MCG specifications (continued) Symbol tirefstf floc_low floc_high Description Internal reference startup time (fast clock) Loss of external clock minimum frequency — RANGE = 00 Loss of external clock minimum frequency — RANGE = 01, 10, or 11 FLL fdco_t DCO output fre‐ quency range — user trimmed and DMX32=0 Low range (DRS=00) 640 × fints_t Mid range (DRS=01) 1280 × fints_t 40 41.94 50 MHz 20 20.97 25 MHz 1, 2 Min. — (3/5) x fints_t (16/5) x fints_t Typ. TBD — — Max. TBD — — Unit µs kHz kHz Notes fdco_t_DMX3 DCO output fre‐ quency range — 2 reference = 32,768Hz and DMX32=1 Pr el im in ar y Mid-high range (DRS=10 192)0 × fints_t 60 62.91 75 High range (DRS=11) 2560 × fints_t 80 83.89 100 Low range (DRS=00) 732 × fints_t — 23.99 — Mid range (DRS=01) 1464 × fints_t — 47.97 — Mid-high range (DRS=10) 2197 × fints_t — 71.99 — High range (DRS=11) 2929 × fints_t — 95.98 — — — — TBD TBD — TBD TBD 1 ps ps PLL 48.0 2.0 — — ± 1.49 ± 4.47 — — — 400 TBD — — — 100 4.0 — — ± 2.98 ± 5.97 0.15 + 1075(1/ fpll_ref) ps ps % % MHz MHz MHz 3 MHz MHz MHz Jcyc_fll Jacc_fll tfll_acquire FLL period jitter 4 FLL accumulated jitter of DCO output over a 1µs time window FLL target frequency acquisition time ms 5 fvco fpll_ref Jcyc_pll Jacc_pll Dlock Dunl tpll_lock VCO operating frequency PLL reference frequency range PLL period jitter PLL accumulated jitter over 1µs window Lock entry frequency tolerance Lock exit frequency tolerance Lock detector detection time MHz MHz 6, 7 6,7 ms 8 1. The resulting system clock frequencies should not exceed their maximum specified values. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 24 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2. 3. 4. 5. This specification includes the 2% precision of the internal reference frequency (slow clock). The resulting clock frequency must not exceed the maximum specified clock frequency of the device. This specification was obtained at TBD frequency. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 6. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 7. This specification was obtained at internal frequency of TBD. 8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. This section provides the electrical characteristics of the module. 6.3.2.1 Symbol VDD33OSC IDDOSC Oscillator DC Electrical Specifications Description Min. Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH) Typ. — Max. 3.6 Unit V Notes 3.3 V supply voltage 1.71 Supply current — low-power mode • 32 kHz • 1 MHz • 4 MHz • 8 MHz Pr el im in ar y — — — — — — — 500 100 200 300 700 1.2 1.5 — — — — — — — nA μA μA μA μA — — — — — — — — — Table continues on the next page... 25 200 400 800 1.5 3 4 — — — — — — — — — — — μA μA μA μA 6.3.2 Oscillator Electrical Characteristics 1 • 16 MHz • 24 MHz • 32 MHz IDDOSC mA mA 1 Supply current — high gain mode • 32 kHz • 1 MHz • 4 MHz • 8 MHz • 16 MHz • 24 MHz • 32 MHz mA mA mA 2, 3 2,3 Cx Cy EXTAL load capacitance XTAL load capacitance K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 25 Peripheral operating requirements and behaviors Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH) (continued) Symbol RF Description Feedback resistor — low-frequency, low-power mode Feedback resistor — low-frequency, high-gain mode Feedback resistor — high-frequency, low-power mode (1 – 8 MHz, 8 – 32 MHz) Feedback resistor — high-frequency, high-gain mode (1 – 8 MHz, 8 – 32 MHz) RS Series resistor — low-frequency, low-power mode Min. — — — — — — — Typ. — 10 — 1 — Max. — — — — — — — Unit MΩ MΩ MΩ MΩ kΩ kΩ kΩ Notes 2,3 Series resistor — low-frequency, high-gain mode Series resistor — high-frequency, low-power mode Series resistor — high-frequency, high-gain mode • 1 MHz resonator • 2 MHz resonator • 4 MHz resonator • 8 MHz resonator • 16 MHz resonator • 20 MHz resonator • 32 MHz resonator Vpp Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode 1. VDD33OSC=3.3 V, Temperature =27 °C, Cx/Cy=20 pF 2. See crystal or resonator manufacturer's recommendation 3. RF and Cx,Cy are integrated in low-frequency, low-power mode and must not be attached externally 26 Pr el im in ar y 200 — — — — — — — — — 6.6 3.3 0 0 0 0 0 — — — — — — — — — — — kΩ kΩ kΩ kΩ kΩ kΩ kΩ V V V V 0.6 0.75 × VDD33OSC — VDD33OSC 0.6 0.75 × VDD33OSC VDD33OSC K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 6.3.2.2 Oscillator frequency specifications Table 14. Oscillator frequency specifications, (VDD33OSC = VDD33OSC (min) to VDD33OSC (max), TA = TL to TH) Symbol fosc_lo fosc_hi_1 fosc_hi_2 tdc_extal tcst Description Oscillator crystal or resonator frequency — low frequency mode Oscillator crystal or resonator frequency — high frequency mode (low range) Oscillator crystal or resonator frequency — high frequency mode (high range) Input clock duty cycle (external clock mode) Min. 32 1 8 40 — — — — Typ. — — — 50 Max. 40 8 32 60 — — — — Unit kHz MHz MHz % Notes Crystal start-up time — 32 kHz low-frequency, low-power mode Crystal start-up time — 32 kHz low-frequency, high-gain mode Pr el im in ar y TBD 800 4 3 ms ms ms ms Min. 1.71 — — — — Typ. — 100 2.5 15 0.6 3.6 — — — — 1, 2, 3 Crystal start-up time — 8 MHz high-frequency, low-power mode Crystal start-up time — 8 MHz high-frequency, high-gain mode 1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. 3. Crystal start up time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. 6.3.3 32kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32kHz Oscillator DC Electrical Specifications Table 15. 32kHz Oscillator Module DC Electrical Specifications (VSSOSC= 0 VDC) (TA = TL to TH) Symbol VBAT RF Cpara Cload Vpp Description Supply voltage Internal feedback resistor Parasitical capacitance of EXTAL32 and XTAL32 Internal load capacitance (programmable) Peak-to-peak amplitude of oscillation Max. Unit V MΩ pF pF V K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 27 Peripheral operating requirements and behaviors 6.3.3.2 32kHz Oscillator Frequency Specifications Table 16. 32kHz oscillator frequency specifications (VDD33OSC = VDD33OSC (min) to VDD33OSC (max), TA = TL to TH) Symbol fosc_lo tstart Description Oscillator crystal Crystal start-up time Min. — — Typ. 32 1000 Max. — — Unit kHz ms 1, 2 Notes 1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. 6.4 Memories and memory interfaces 6.4.1 Flash (FTFL) Electrical Characteristics This section describes the electrical characteristics of the FTFL module. 6.4.1.1 Flash Timing Parameters — Program and Erase The following characteristics represent the amount of time the internal charge pumps are active and do not include command overhead. Table 17. NVM program/erase timing characteristics Min. — — — Typ. 20 20 Max. TBD 100 800 Symbol thvpgm4 thversscr thversblk Description Pr el im in ar y μs ms ms 160 Unit Notes Longword Program high-voltage time Sector Erase high-voltage time Erase Block high-voltage time 1 1 1. Maximum time based on expectations at cycling end-of-life. 6.4.1.2 Symbol trd1blk trd1sec2k tpgmchk Flash Timing Parameters — Commands Table 18. Flash command timing characteristics Description Read 1s Block execution time Read 1s Section execution time (2 KB flash sec‐ tor) Program Check execution time Min. — — — Table continues on the next page... Typ. — — — Max. 1.4 40 35 Unit ms μs μs Notes K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 28 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 18. Flash command timing characteristics (continued) Symbol trdrsrc tpgm4 tersblk tersscr tpgmsec2k trd1all trdonce tpgmonce tersall tvfykey Description Read Resource execution time Program Longword execution time Erase Flash Block execution time Erase Flash Sector execution time Program Section execution time (2 KB flash sec‐ tor) Read 1s All Blocks execution time Read Once execution time Min. — — — — — — — — — — Typ. — 50 160 20 TBD — — Max. 35 TBD 800 100 TBD 2.8 35 Unit μs μs ms ms ms ms μs μs 1 2 2 Notes 1 Program Once execution time Erase All Blocks execution time Pr el im in ar y 50 TBD 320 — 1600 35 ms μs 2 1 Verify Backdoor Access Key execution time 1. Assumes 25MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 Flash (FTFL) Current and Power Parameters Description Table 19. Flash (FTFL) current and power parameters Typ. 10 Symbol IDD_PGM Unit mA Worst case programming current in program flash 6.4.1.4 Symbol Reliability Characteristics Description Table 20. NVM reliability characteristics Min. Typ.1 Program Flash 5 10 15 10 K Max. Unit Notes tnvmretp10k tnvmretp1k tnvmretp100 nnvmcycp Data retention after up to 10 K cycles Data retention after up to 1 K cycles Data retention after up to 100 cycles Cycling endurance TBD TBD TBD TBD — — — — years years years cycles 2 2 2 3 1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618. 2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application). 3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 29 Peripheral operating requirements and behaviors 6.4.2 EzPort Switching Specifications Table 21. EzPort switching specifications Num Description Operating voltage EP1 EP1a EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EZP_CK frequency of operation (all commands except READ) EZP_CK frequency of operation (READ command) EZP_CS negation to next EZP_CS assertion EZP_CS input valid to EZP_CK high (setup) EZP_CK high to EZP_CS input invalid (hold) EZP_D input valid to EZP_CK high (setup) Min. 2.7 — — 2 x tEZP_CK 5 5 2 5 Max. 3.6 fSYS/2 fSYS/8 — — — — — Unit V MHz MHz ns ns ns ns ns ns ns ns EZP_CK high to EZP_D input invalid (hold) EZP_CK low to EZP_Q output valid (setup) EZP_CK low to EZP_Q output invalid (hold) EZP_CS negation to EZP_Q tri-state EZP_CK EZP_CS EZP_Q (output) EZP_D (input) 6.4.3 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency. 30 Pr el im in ar y — 0 12 — — 12 EP3 EP4 EP2 EP9 EP7 EP8 EP5 EP6 Figure 9. EzPort Timing Diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be derived from these values. Table 22. Flexbus switching specifications Num Description Operating voltage Frequency of operation FB1 FB2 FB3 FB4 FB5 Clock period Address, data, and control output valid Address, data, and control output hold Data and FB_TA input setup Data and FB_TA input hold Min. 2.7 — 20 TBD 0 Max. 3.6 50 — 11.5 — — — Unit V Mhz ns ns ns ns ns 1 1 2 2 Notes 1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], and FB_TS. 2. Specification is valid for all FB_AD[31:0] and FB_TA. FB1 FB_CLK FB_A[Y] FB_D[X] FB_RW FB_TS FB_CSn FB_OEn FB_BE/BWEn FB4 AA=1 FB_TA FB_TSIZ[1:0] Freescale Semiconductor, Inc. Pr el im in ar y 8.5 0.5 FB5 FB3 Address FB4 FB2 Address Data AA=1 AA=0 FB5 AA=0 TSIZ Figure 10. FlexBus read timing diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 31 Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB_A[Y] FB2 Address FB_D[X] Address Data FB_RW FB_TS FB_CSn FB_OEn FB_BE/BWEn FB_TA FB_TSIZ[1:0] 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the differential pins (ADCx_DP0, ADCx_DM0, ADC, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DP3). The ADCx_DP2 and ADCx_DM2 ADC inputs are used K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 32 Pr el im in ar y AA=1 AA=0 FB4 FB5 AA=1 AA=0 TSIZ Figure 11. FlexBus write timing diagram Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors as the PGA inputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 25 and Table 26. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 Symbol VDDA ΔVDDA ΔVSSA VREFH VREFL VADIN CADIN 16-bit ADC operating conditions Table 23. 16-bit ADC operating conditions Description Supply voltage Supply voltage Ground voltage ADC reference voltage high Conditions Absolute Delta to VDD (VDDVDDA) Delta to VSS (VSSVSSA) Min. 1.71 -100 -100 1.13 Typ.1 — 0 0 Max. 3.6 +100 +100 VDDA VSSA Unit V mV mV V V V 2 2 Notes Reference volt‐ age low Input voltage Input capaci‐ tance RADIN Input resistance Freescale Semiconductor, Inc. Pr el im in ar y VDDA VSSA — 8 4 VSSA VREFL — — VREFH 10 5 • 16 bit modes • 8/10/12 bit modes pF — 2 5 kΩ Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary 33 Peripheral operating requirements and behaviors Table 23. 16-bit ADC operating conditions (continued) Symbol RAS Description Analog source resistance Conditions 16 bit modes • fADCK > 8MHz • fADCK = 4–8MHz • fADCK < 4MHz 13/12 bit modes • fADCK > 16MHz • fADCK > 8MHz • fADCK = 4–8MHz • fADCK < 4MHz — — — — — — — — 0.5 1 2 5 kΩ kΩ kΩ kΩ — — — — — — 0.5 1 2 kΩ kΩ kΩ Min. Typ.1 Max. Unit Notes External to MCU Assumes ADLSMP=0 fADCK ADC conversion clock frequency 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. 34 Pr el im in ar y 11/10 bit modes • fADCK > 8MHz — — — — — — — — — — 2 5 kΩ kΩ kΩ kΩ kΩ • fADCK = 4–8MHz • fADCK < 4MHz 10 5 9/8 bit modes • fADCK > 8MHz • fADCK < 8MHz 10 ADLPC=0, ADHSC=1 • 16 bit modes • ≤13 bit modes 1.0 1.0 — — TBD TBD MHz MHz ADLPC=0, ADHSC=0 • 16 bit modes • ≤13 bit modes 1.0 1.0 1.0 1.0 — — — — 8.0 MHz MHz MHz MHz 12.0 5.0 8.0 ADLPC=1, ADHSC=1 • 16 bit modes • ≤13 bit modes ADLPC=1, ADHSC=0 • 16 bit modes • ≤13 bit modes 1.0 1.0 — — 2.5 5.0 MHz MHz K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Z AS R AS V ADIN V AS C AS Pad leakage due to input protection R ADIN ADC SAR ENGINE 6.6.1.2 Symbol IDDA 16-bit ADC electrical characteristics Description Conditions1 Min. — — — — — Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Typ.2 215 340 470 610 Max. — — — — Supply current • ADLPC=1, ADHSC=0 • ADLPC=1, ADHSC=1 • ADLPC=0, ADHSC=0 • ADLPC=0, ADHSC=1 Pr el im in ar y INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN R ADIN C ADIN Figure 12. ADC input impedance equivalency diagram Unit μA μA μA μA μA Notes ADLSMP= 0 ADCO=1 Supply current • Stop, reset, module off • ADLPC=1, ADHSC=0 • ADLPC=1, ADHSC=1 • ADLPC=0, ADHSC=0 • ADLPC=0, ADHSC=1 0.01 2.4 4.0 5.2 6.2 0.8 fADACK ADC asynchro‐ nous clock source TBD TBD TBD TBD TBD TBD TBD TBD MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times Conversion Time See Reference Manual chapter for conversion times Table continues on the next page... K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 35 Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol TUE Description Total unadjusted error Conditions1 • 16 bit differential • 16 bit single-ended • 13 bit differential • 12 bit single-ended • 11 bit differential • 10 bit single-ended • 9 bit differential • 8 bit single-ended DNL Differential nonlinearity • 16 bit differential • 13 bit differential • 11 bit differential • 9 bit differential Min. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Typ.2 ±14.0 ±13.0 ±1.5 ±TBD ±0.8 ±TBD ±0.5 ±0.5 ±2.5 ±2.5 ±0.7 ±0.7 ±0.5 ±0.2 ±0.2 Max. ±TBD ±TBD ±TBD ±TBD ±TBD ±TBD ±1.0 ±1.0 ±TBD ±TBD ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 — — LSB3 Max hard‐ ware aver‐ aging (AVGE = %1, AVGS = %11) Unit LSB3 Notes Max hard‐ ware aver‐ aging (AVGE = %1, AVGS = %11) INL Integral non-line‐ arity Pr el im in ar y • 16 bit single-ended • 12 bit single-ended • 10 bit single-ended • 8 bit single-ended • 16 bit differential • 13 bit differential • 11 bit differential • 9 bit differential ±TBD -6 to +2.5 -2 to +12 ±1.0 ±1.0 ±0.5 ±0.5 ±0.3 ±0.3 ±4.0 ±4.0 ±0.7 ±0.7 ±0.4 ±0.4 ±0.2 ±0.2 • 16 bit single-ended • 12 bit single-ended • 10 bit single-ended • 8 bit single-ended • 16 bit differential • 13 bit differential • 12 bit single-ended • 11 bit differential • 10 bit single-ended • 9 bit differential • 8 bit single-ended ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 — — ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 • 16 bit single-ended Table continues on the next page... LSB3 Max aver‐ aging EZS Zero-scale error LSB3 VADIN = VSSA K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 36 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol EFS Description Full-scale error Conditions1 • 16 bit differential • 16 bit single-ended • 13 bit differential • 12 bit single-ended • 11 bit differential • 10 bit single-ended • 9 bit differential • 8 bit single-ended EQ Quantization er‐ ror • 16 bit modes Min. — — — — — — — — — — Typ.2 0 to +10 0 to +14 ±1.0 ±TBD ±0.4 ±0.4 ±0.2 ±0.2 -1 to 0 — Max. — — ±TBD ±TBD ±TBD ±TBD ±0.5 ±0.5 — LSB3 Unit LSB3 Notes VADIN = VDDA ENOB Effective number 16 bit differential mode of bits • Avg=32 • Avg=16 • Avg=8 • Avg=4 • Avg=1 Pr el im in ar y • ≤13 bit modes ±0.5 TBD TBD TBD TBD TBD 13.6 14.1 13.2 TBD TBD TBD TBD TBD TBD TBD 16 bit single-ended mode • Avg=32 • Avg=16 • Avg=8 • Avg=4 • Avg=1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD See ENOB 6.02 × ENOB + 1.76 dB 16 bit differential mode • Avg=32 16 bit single-ended mode • Avg=32 — TBD TBD dB — -94 TBD dB TBD TBD 95 TBD — — dB dB 16 bit single-ended mode • Avg=32 Table continues on the next page... 4 bits bits bits bits bits bits bits bits bits bits SINAD THD Signal-to-noise plus distortion Total harmonic distortion 4 SFDR Spurious free dy‐ 16 bit differential mode namic range • Avg=32 4 K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. Freescale Semiconductor, Inc. Preliminary 37 Peripheral operating requirements and behaviors Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol EIL Description Input leakage er‐ ror Conditions1 Min. Typ.2 IIn × RAS Max. Unit mV Notes IIn = leak‐ age cur‐ rent (refer to the MCU's voltage and cur‐ rent oper‐ ating rat‐ ings) VTEMP25 Temp sensor voltage 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. 1 LSB = (VREFH - VREFL)/2N 4. Input data is 1 kHz sine wave. 6.6.1.3 Symbol VDDA VREFPGA VADIN RPGA 16-bit ADC with PGA operating conditions Description Conditions Min. Typ.1 — Pr el im in ar y • 25°C to 105°C — — TBD TBD — — 25°C Temp sensor slope • –40°C to 25°C — TBD — mV/°C mV/°C mV Table 25. 16-bit ADC with PGA operating conditions Max. 3.6 Absolute 1.71 Unit V V V Notes Supply voltage PGA ref voltage Input voltage VREFOUT VREFOUT VREFOUT VSSA TBD TBD TBD TBD TBD TBD — 1.25 — VDDA TBD TBD TBD TBD TBD TBD — — 2, 3 Input impedance Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64 64 32 16 kΩ RPGAD Differntial input impedance Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64 128 64 32 100 — kΩ IN+ to IN- RAS TS Analog source resistance ADC sampling time Gain = 16, 32 Gain = 64 Ω µs 4 5 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREFOUT) 3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output of the VREF module, the VREF module must be disabled. K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010. 38 Preliminary Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 4. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency 6.6.1.4 Symbol IDDA_PGA ILKG G 16-bit ADC with PGA characteristics Table 26. 16-bit ADC with PGA characteristics Description Supply current Leakage current Gain2 PGA disabled Conditions Min. TBD — Typ.1 590