SC312XDP512J1VAA

MC9S12XDP512 Data Sheet Covers S12XD, S12XB & S12XA Families HCS12X Microcontrollers MC9S12XDP512 Rev. 2.17 July 2007 freescale.com MC9S12XDP512 Data Sheet MC9S12XDP512 Rev. 2.17 July 2007 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. Read page 29 first to understand the maskset specific chapters of this document This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to the CPU S12X Reference Manual. Revision History Date April, 2005 May, 2005 Revision Level 02.07 02.08 New Book Minor corrections Description May, 2005 02.09 removed ESD Machine Model from electrical characteristics added thermal characteristics added more details to run current measurement configurations VDDA supply voltage range 3.15V - 3.6V fot ATD Operating Characteristics I/O Chararcteristics for alll pins except EXTAL, XTAL .... corrected VREG electrical spec IDD wait max 95mA Improvements to NVM reliabity spec, added part numbers Added ROM parts to App. Single Souce S12XD Fam. Document, New Memory Map Figures, SPI electricals updated Voltage Regulator electricals updated Added Partnumbers and 1L15Y maskset Updated App. E 6SCI’s on 112 pin DT/P512 and 3 SPI’s on all D256 parts Data Sheet covers S12XD/B & A Family Included differnt pull device specification for differnt masksets Minor Corrections and Improvments Added 2M42E and 1M84E masksets Modified Appendix May 2005 July 2005 October 2005 02.10 02.11 02.12 May 2006 2.13 June 2006 July 2006 June 2007 July 2007 2.14 2.15 2.16 2.17 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC9S12XDP512 Data Sheet, Rev. 2.17 4 Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 5 MC9S12XDP512 Data Sheet, Rev. 2.17 6 Freescale Semiconductor Section Number Chapter 1 Chapter 2 Chapter 3 Title Page Device Overview MC9S12XD-Family . . . . . . . . . . . . . . . . . . . . 31 Clocks and Reset Generator (S12CRGV6) . . . . . . . . . . . . . . . . 79 Pierce Oscillator (S12XOSCLCPV1) . . . . . . . . . . . . . . . . . . . . 119 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description125 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 419 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23 Chapter 24 Analog-to-Digital Converter (S12ATD10B8CV3) . . . . . . . . . . 159 XGATE (S12XGATEV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Enhanced Capture Timer (S12ECT16B8CV2) . . . . . . . . . . . . 309 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . 363 Inter-Integrated Circuit (IICV2) Block Description. . . . . . . . . 395 Freescale’s Scalable Controller Area Network (S12MSCANV3). Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 477 Serial Peripheral Interface (S12SPIV4) . . . . . . . . . . . . . . . . . . 515 Periodic Interrupt Timer (S12PIT24B4CV1) . . . . . . . . . . . . . . 541 Voltage Regulator (S12VREG3V3V5) . . . . . . . . . . . . . . . . . . . 555 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . 569 Interrupt (S12XINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Memory Mapping Control (S12XMMCV2) . . . . . . . . . . . . . . . . 613 Memory Mapping Control (S12XMMCV3) . . . . . . . . . . . . . . . 651 Debug (S12XDBGV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 745 External Bus Interface (S12XEBIV2) . . . . . . . . . . . . . . . . . . . 787 DP512 Port Integration Module (S12XDP512PIMV2) . . . . . . . 807 DQ256 Port Integration Module (S12XDQ256PIMV2) . . . . . . 901 DG128 Port Integration Module (S12XDG128PIMV2) . . . . . . 975 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 5 Section Number Chapter 25 Chapter 26 Chapter 27 Chapter 28 Chapter 29 Chapter 30 Title Page 2 Kbyte EEPROM Module (S12XEETX2KV1) . . . . . . . . . . . . 1039 4 Kbyte EEPROM Module (S12XEETX4KV2) . . . . . . . . . . . . 1073 512 Kbyte Flash Module (S12XFTX512K4V2). . . . . . . . . . . . 1107 256 Kbyte Flash Module (S12XFTX256K2V1). . . . . . . . . . . . 1149 128 Kbyte Flash Module (S12XFTX128K1V1). . . . . . . . . . . . 1191 Security (S12X9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 Appendix C Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . 1294 Appendix D Using L15Y Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 Appendix G Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 MC9S12XDP512 Data Sheet, Rev. 2.17 6 Freescale Semiconductor Section Number Title Page Chapter 1Device Overview MC9S12XD-Family 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.1 MC9S12XD/B/A Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.1.5 Part ID Assignments & Maskset Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.5.1 User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.5.2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1.5.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.6.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.6.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ATD0 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ATD1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 2.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . . 82 2.2.2 XFC — External Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 9 2.2 2.3 2.4 Section Number 2.5 Title Page 2.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.2 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.3 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.4 Power On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.6.1 Real Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.6.3 Self Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 120 3.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 3.2.3 XCLKS — Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.2 3.3 3.4 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins 127 4.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . . . . 127 4.2.3 VRH, VRL — High Reference Voltage Pin, Low Reference Voltage Pin . . . . . . . . . . . . 127 4.2.4 VDDA, VSSA — Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 127 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.2 4.3 MC9S12XDP512 Data Sheet, Rev. 2.17 10 Freescale Semiconductor Section Number Title Page 4.4 4.5 4.6 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Chapter 5Analog-to-Digital Converter (S12ATD10B8CV3) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . 160 5.2.3 VRH and VRL — High and Low Reference Voltage Pins . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2.4 VDDA and VSSA — Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 5.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.2 5.3 5.4 5.5 5.6 Chapter 6 XGATE (S12XGATEV2) 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 11 6.2 6.3 6.4 Section Number Title Page 6.5 6.6 6.7 6.8 6.9 6.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.6.2 Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.6.3 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 6.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 6.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 6.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 311 7.2.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 311 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 7.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 7.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 MC9S12XDP512 Data Sheet, Rev. 2.17 12 Freescale Semiconductor 7.2 7.3 7.4 Section Number Title Page 7.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 8.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 8.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 8.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 8.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 8.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 8.2 8.3 8.4 8.5 8.6 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 9.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 13 9.2 9.3 9.4 Section Number 9.5 9.6 9.7 Title Page 9.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 9.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 10.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 10.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 10.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 10.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 10.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 10.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 10.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 10.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 10.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 10.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 10.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 10.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 10.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 10.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 10.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 10.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Chapter 11 Serial Communication Interface (S12SCIV5) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 MC9S12XDP512 Data Sheet, Rev. 2.17 14 Freescale Semiconductor Section Number Title Page 11.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 11.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 11.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 11.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 11.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 11.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 11.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 11.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 11.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 11.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 11.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 12.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 12.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 12.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 12.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 15 Section Number Title Page 12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 13.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 13.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 13.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 13.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 13.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 13.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 13.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 558 14.2.5 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.4.6 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 MC9S12XDP512 Data Sheet, Rev. 2.17 16 Freescale Semiconductor Section Number Title Page 14.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Chapter 15 Background Debug Module (S12XBDMV2) 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 15.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 15.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 15.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 15.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 15.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 15.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 15.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 15.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 15.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 15.4.11Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Chapter 16 Interrupt (S12XINTV1) 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 16.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 17 Section Number Title Page 16.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 16.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 16.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 16.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 16.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 Chapter 17 Memory Mapping Control (S12XMMCV2) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 17.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 17.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 17.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 17.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 17.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 17.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 17.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 17.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 17.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 17.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 Chapter 18 Memory Mapping Control (S12XMMCV3) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 18.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 18.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 MC9S12XDP512 Data Sheet, Rev. 2.17 18 Freescale Semiconductor Section Number Title Page 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 18.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 18.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 18.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 18.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 18.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 18.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 Chapter 19 Debug (S12XDBGV2) 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 19.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 19.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 19.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 19.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 19.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 19.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 19.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 19.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 19.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 19.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 Chapter 20 S12X Debug (S12XDBGV3) Module 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 19 Section Number Title Page 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 20.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 20.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 20.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 20.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 20.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 20.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 20.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 Chapter 21 External Bus Interface (S12XEBIV2) 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 21.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 21.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 21.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 21.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 21.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 21.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 21.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 21.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 21.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 22.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 MC9S12XDP512 Data Sheet, Rev. 2.17 20 Freescale Semiconductor Section Number Title Page 22.4.2 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 22.4.3 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 22.4.4 Expanded Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 22.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 22.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Chapter 23Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901 23.0.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901 23.0.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 Figure 23-1.External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.0.3 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 Table 23-1.Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 23.0.4 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 23.0.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 Table 23-66.Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 23.0.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 23.0.7 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 23.0.8 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 23.0.9 Expanded Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 23.0.10Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 23.0.10.3Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Chapter 24Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 24.0.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 24.0.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976 Figure 24-1.External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 24.0.3 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 Table 24-1.Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.0.4 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.0.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Table 24-59.Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 24.0.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 24.0.7 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 24.0.8 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 24.0.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 24.0.9.3Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 21 Section Number Title Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Page 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 25.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 25.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 25.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 25.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 25.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 25.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 25.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 25.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 25.6 EEPROM Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 25.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1070 25.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 25.7.1 EEPROM Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 25.7.2 Reset While EEPROM Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 25.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 25.8.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 26.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 26.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 26.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 MC9S12XDP512 Data Sheet, Rev. 2.17 22 Freescale Semiconductor Section Number Title Page 26.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.6 EEPROM Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1105 26.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105 26.7.1 EEPROM Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105 26.7.2 Reset While EEPROM Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105 26.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105 26.8.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107 27.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108 27.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108 27.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109 27.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 27.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 27.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113 27.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 27.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126 27.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 27.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144 27.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 27.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 27.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 27.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 27.6 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145 27.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 27.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1147 27.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 23 Section Number Title Page Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 28.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 28.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 28.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 28.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 28.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 28.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151 28.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153 28.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 28.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166 28.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169 28.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185 28.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 28.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 28.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 28.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 28.6 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186 28.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187 28.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1188 28.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 28.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 28.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 28.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188 28.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 29.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191 29.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 MC9S12XDP512 Data Sheet, Rev. 2.17 24 Freescale Semiconductor Section Number 29.5 Title Page 29.6 29.7 29.8 29.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1229 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 29.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 29.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 29.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230 Chapter 30 Security (S12X9SECV2) 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 30.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 30.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 30.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 30.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 30.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 30.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 30.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 Appendix A Electrical Characteristics A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254 A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 25 Section Number Title Page A.3 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 A.3.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264 A.4.1 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 A.4.2 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265 A.5 Reset, Oscillator, and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267 A.5.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268 A.5.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 A.7 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 A.8.1 Normal Expanded Mode (External Wait Feature Disabled). . . . . . . . . . . . . . . . . . . . . 1279 A.8.2 Normal Expanded Mode (External Wait Feature Enabled) . . . . . . . . . . . . . . . . . . . . . 1281 A.8.3 Emulation Single-Chip Mode (Without Wait States) . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 A.8.4 Emulation Expanded Mode (With Optional Access Stretching) . . . . . . . . . . . . . . . . . 1286 A.8.5 External Tag Trigger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 Appendix B Package Information B.1 144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 B.2 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 B.3 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293 Appendix C Recommended PCB Layout Appendix D Using L15Y Silicon Appendix E Derivative Differences E.1 E.2 E.3 E.4 E.5 E.6 Memory Sizes and Package Options S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Memory Sizes and Package Options S12XA & S12XB Family. . . . . . . . . . . . . . . . . . . . . . . . . 1302 MC9S12XD-Family Flash Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 MC9S12XD/A/B -Family SRAM & EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 1304 Peripheral Sets S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 Peripheral Sets S12XA & S12XB - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306 MC9S12XDP512 Data Sheet, Rev. 2.17 26 Freescale Semiconductor Section Number E.7 Title Page Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 Appendix F Ordering Information Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 27 Section Number Title Page MC9S12XDP512 Data Sheet, Rev. 2.17 28 Freescale Semiconductor NOTE This documentation covers all devices in the S12XD, S12XB and S12XA families. A full list of these devices and their features can be found in the following chapters: • E.1 Memory Sizes and Package Options S12XD - Family • E.2 Memory Sizes and Package Options S12XA & S12XB Family • E.5 Peripheral Sets S12XD - Family • E.6 Peripheral Sets S12XA & S12XB - Family • Table 1-6 Partnames, Masksets and assigned PartID’s This document includes different sections for S12XDPIM, S1XMMC, S12XDBG, S12XEETX and S12XFTX because the different masksets of the S12XD, S12XB and S12XA families include differnt configurations or versions of the modules or have different memory sizes. Table 0-1 shows the maskset specific chapters in this documentation. Table 0-1. Maskset Specific Documentation Chapters in this Documentation Chapter 21 External Bus Interface (S12XEBIV2) 787 Chapter 17 Memory Mapping Control (S12XMMCV2) 613 Chapter 18 Memory Mapping Control (S12XMMCV3) 649 Chapter 19 Debug (S12XDBGV2) 691 Chapter 20 S12X Debug (S12XDBGV3) Module 743 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 805 Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 899 Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 973 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 1037 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 1071 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 1105 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 1147 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 1189 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 157 L15Y (512k Flash) M84E (256K Flash) M42E (128K Flash) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 29 Chapter 1 Device Overview MC9S12XD-Family describes pinouts, detailed pin description , interrupts and register map of the cover part MC9S12XDP512 (maskset L15Y). For availability of the modules on other members of the S12XA, S12XB and S12XD families please refer to Appendix E Derivative Differences. For pinout explanations of the different parts refer to E.7 Pinout explanations:. For a list of available partnames /masksets refer to Table 1-6. MC9S12XDP512 Data Sheet, Rev. 2.17 30 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Chapter 1 Device Overview MC9S12XD-Family 1.1 Introduction The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family. Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12. The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA functionality, this parallel processing module offloads the CPU by providing high-speed data processing and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the RAM block. The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel, 10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to external memories The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. System power consumption can be further improved with the new “fast exit from stop mode” feature. In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt capability allowing wake-up from stop or wait mode. Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP or 80-pin QFP package without external bus interface. See Appendix E Derivative Differences for package optioÔÛÆ@» MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 31 Chapter 1 Device Overview MC9S12XD-Family 1.1.1 MC9S12XD/B/A Family Features This section lists the features which are available on MC9S12XDP512. See Appendix E Derivative Differences for availability of features and memory sizes on other family members. • • • • • • • HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’s model identical to MC9S12 – Instruction queue – Enhanced indexed addressing – Enhanced instruction set — EBI (external bus interface) — MMC (module mapping control) — INT (interrupt controller) — DBG (debug module to monitor HCS12X CPU and XGATE bus activity) — BDM (background debug mode) XGATE (peripheral coprocessor) — Parallel processing module off loads the CPU by providing high-speed data processing and transfer — Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports PIT (periodic interrupt timer) — Four timers with independent time-out periods — Time-out periods selectable between 1 and 224 bus clock cycles CRG (clock and reset generator) — Low noise/low power Pierce oscillator — PLL — COP watchdog — Real time interrupt — Clock monitor — Fast wake-up from stop mode Port H & Port J with interrupt functionality — Digital filtering — Programmable rising or falling edge trigger Memory — 512, 256 and 128-Kbyte Flash EEPROM — 4 and 2-Kbyte EEPROM — 32, 16 and 12-Kbyte RAM One 16-channel and one 8-channel ADC (analog-to-digital converter) MC9S12XDP512 Data Sheet, Rev. 2.17 32 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family • • • • • • — 10-bit resolution — External and internal conversion trigger capabilityFiveFourTwo 1M bit per second, CAN 2.0 A, B software compatible modules — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit — Four separate interrupt channels for Rx, Tx, error, and wake-up — Low-pass filter wake-up function — Loop-back for self-test operation ECT (enhanced capture timer) — 16-bit main counter with 7-bit prescaler — 8 programmable input capture or output compare channels — Four 8-bit or two 16-bit pulse accumulators 8 PWM (pulse-width modulator) channels — Programmable period and duty cycle — 8-bit 8-channel or 16-bit 4-channel — Separate control for each pulse width and duty cycle — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies — Fast emergency shutdown input Serial interfaces — SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width — ThreeTwo Synchronous Serial Peripheral Interfaces (SPI) TwoOne IIC (Inter-IC bus) Modules — Compatible with IIC bus standard — Multi-master operation — Software programmable for one of 256 different serial clock frequencies On-Chip Voltage Regulator — Two parallel, linear voltage regulators with bandgap reference — Low-voltage detect (LVD) with low-voltage interrupt (LVI) — Power-on reset (POR) circuit — 3.3-V–5.5-V operation — Low-voltage reset (LVR) — Ultra low-power wake-up timer 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages — I/O lines with 5-V input and drive capability — Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation — 5-V A/D converter inputs — Operation at 80 MHz equivalent to 40-MHz bus speed MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 33 Chapter 1 Device Overview MC9S12XD-Family • Development support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints 1.1.2 Modes of Operation Normal expanded mode, Emulation of single-chip mode and Emulation of expanded mode are ony available on family members with an external bus interface in 144-pin LQFP. See Appendix E Derivative Differences for package options. User modes: • Normal and emulation operating modes — Normal single-chip mode — Normal expanded mode — Emulation of single-chip mode — Emulation of expanded mode Special Operating Modes — Special single-chip mode with active background debug mode — Special test mode (Freescale use only) • Low-power modes: • System stop modes — Pseudo stop mode — Full stop mode • System wait mode 1.1.3 Block Diagram Figure 1-1 shows a block diagram of theMC9S12X-Family. The block diagram shows all modules available on cover part MC9S12XDP512. Availability of modules on other family members see Appendix E Derivative Differences. Figure 1-2 shows blocks integrated on maskset M42E. The 16 channel ATD Converter is routed to pins PAD00 - PAD15 on maskset M42E. See Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 123. MC9S12XDP512 Data Sheet, Rev. 2.17 34 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 512/384/256/128/64-Kbyte Flash 32/20/16/14/10/8/4-Kbyte RAM 4/2/1-Kbyte EEPROM VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PLL ATD0 VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 DDRAD0 & AD0 ATD1 VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 Voltage Regulator Single-Wire Background Debug Module Clock and Reset Generation Module CPU12X Enhanced Multilevel Interrupt Module Periodic Interrupt COP Watchdog Clock Monitor Breakpoints XGATE Peripheral Co-Processor DDRAD1 & AD1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 UDS ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 EWAIT ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 XIRQ IRQ R/W/WE LSTRB/LDS/EROMCTL ECLK MODA/RE/TAGLO MODB/TAGHI ECLKX2/XCLKS IQSTAT0 IQSTAT1 IQSTAT2 IQSTAT3 8-Bit PPAGE ACC0 Allows 4-MByte ACC1 Program space ACC2 ROMCTL/EWAIT Timer 4-Channel 16-Bit with Prescaler for Internal Timebases SCI3 RXD TXD DDRE PTE Enhanced Capture Timer SCI0 SCI1 MISO MOSI SCK SS RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXD TXD SDA SCL SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS SPI0 DDRM DDRA PTA CAN2 CAN3 CAN4 SCI2 Non-Multiplexed External Bus Interface (EBI) DDRB Digital Supply 2.5 V VDD1,2 VSS1,2 PLL Supply 2.5 V VDDPLL VSSPLL Analog Supply 3-5 V VDDA VSSA I/O Supply 3-5 V VDDX1,2 VSSX1,2 Voltage Regulator 3-5 V VDDR1,2 VSSR1,2 SCI4 SCI5 RXD TXD RXD TXD IIC1 IIC0 PWM DDRD SPI1 SPI2 KWJ0 KWJ1 KWJ2 KWJ4 KWJ5 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 PTM CAN1 Module to Port Routing CAN0 PJ0 CS3 PJ1 PJ2 CS1 PJ4 CS0 PJ5 CS2 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 DDRC PTC DDRP PTD DDRH Figure 1-1. MC9S12XD-Family Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 35 PTH PTP Signals shown in Bold-Italics are neither available on the 112-pin nor on the 80-pin oackage option Signals shown in Bold are not available on the 80-pin package DDRS DDRJ PTB DDRK PTK PTJ PTS AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD DDRT PTT Chapter 1 Device Overview MC9S12XD-Family 128-Kbyte Flash ATD1 12 Kbyte RAM 2-Kbyte EEPROM VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PLL VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 Voltage Regulator Single-Wire Background Debug Module Clock and Reset Generation Module CPU12X Enhanced Multilevel Interrupt Module Periodic Interrupt COP Watchdog Clock Monitor Breakpoints XGATE Peripheral Co-Processor XIRQ IRQ DDRE PTE Enhanced Capture Timer ECLK ECLKX2/XCLKS SCI0 DDRK SCI1 8-Bit PPAGE Allows 4-MByte Program space MISO MOSI SPI0 SCK SS RXCAN CAN0 TXCAN DDRM DDRA PTA Timer 4-Channel 16-Bit with Prescaler for Internal Timebases CAN4 Digital Supply 2.5 V VDD1,2 VSS1,2 RXCAN TXCAN DDRB PTB KWJ0 KWJ1 DDRJ PTJ PJ0 PJ1 PLL Supply 2.5 V VDDPLL VSSPLL Analog Supply 3-5 V VDDA VSSA I/O Supply 3-5 V VDDX VSSX Voltage Regulator 3-5 V VDDR VSSR IIC0 PWM SPI1 DDRH Figure 1-2. Block Diagram Maskset M42E MC9S12XDP512 Data Sheet, Rev. 2.17 36 Freescale Semiconductor PTH SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 DDRP PTP Signals shown in Bold-Italics are neither available on the 112-pin nor on the 80-pin oackage option Signals shown in Bold are not available on the 80-pin package DDRS PTK Module to Port Routing PTM PTS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD DDRAD1 DDRT PTT PTAD1 Chapter 1 Device Overview MC9S12XD-Family 1.1.4 Device Memory Map Table 1-1shows the device register memory map of the MC9S12XDP512. Available modules on other Family members please refer to Appendix E Derivative Differences Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these locations have no effect. Read access to these locations returns zero. Figure 1-1 shows the global address mapping for the parts listed in Table 1-2. Table 1-1. Device Register Memory Map Address 0x0000–0x0009 0x000A–0x000B 0x000C–0x000D 0x000E–0x000F 0x0010–0x0017 0x0018–0x0019 0x001A–0x001B 0x001C–0x001F 0x0020–0x002F 0x0030–0x0031 0x0032–0x0033 0x0034–0x003F 0x0040–0x007F 0x0080–0x00AF 0x00B0–0x00B7 0x00B8–0x00C7 0x00B8–0x00BF 0x00C0–0x00C7 0x00C8–0x00CF 0x00D0–0x00D7 0x00D8–0x00DF 0x00E0–0x00E7 0x00E8–0x00EF 0x00F0–0x00F7 0x00F8–0x013F 0x00F8–0x00FF 0x0100–0x010F Module PIM (port integration module) MMC (memory map control) PIM (port integration module) EBI (external bus interface) MMC (memory map control) Unimplemented Device ID register PIM (port integration module) DBG (debug module) MMC (memory map control) PIM (port integration module) CRG (clock and reset generator) ECT (enhanced capture timer 16-bit 8-channel)s ATD1 (analog-to-digital converter 10-bit 16-channel) IIC1 (inter IC bus) Reserved SCI2 (serial communications interface) SCI3 (serial communications interface) SCI0 (serial communications interface) SCI1 (serial communications interface) SPI0 (serial peripheral interface) IIC0 (inter IC bus) Unimplemented SPI1 (serial peripheral interface) Reserved SPI2 (serial peripheral interface) Flash control register Size (Bytes) 10 2 2 2 8 2 2 4 16 2 2 12 64 48 8 16 8 8 8 8 8 8 8 8 8 8 16 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 37 Chapter 1 Device Overview MC9S12XD-Family Table 1-1. Device Register Memory Map (continued) Address 0x0110–0x011B 0x011C–0x011F 0x0120–0x012F 0x0130–0x013F 0x0130–0x0137 0x0138–0x013F 0x0140–0x017F 0x0180–0x01BF 0x0180–0x023F 0x01C0–0x01FF 0x0200–0x023F 0x0200–0x023F 0x0240–0x027F 0x0280–0x02BF 0x02C0–0x02DF 0x02C0–0x02DF 0x02E0–0x02EF 0x02F0–0x02F7 0x02F8–0x02FF 0x0300–0x0327 0x0328–0x033F 0x0340–0x0367 0x0368–0x037F 0x0380–0x03BF 0x03C0–0x03FF 0x0400–0x07FF Module EEPROM control register MMC (memory map control) INT (interrupt module) Reserved SCI4 (serial communications interface) SCI5 (serial communications interface) CAN0 (scalable CAN) CAN1 (scalable CAN) Reserved CAN2 (scalable CAN) Reserved CAN3 (scalable CAN) PIM (port integration module) CAN4 (scalable CAN) Reserved ATD0 (analog-to-digital converter 10 bit 8-channel) Unimplemented Voltage regulator Unimplemented PWM (pulse-width modulator 8 channels) Unimplemented Periodic interrupt timer Unimplemented XGATE Unimplemented Unimplemented Size (Bytes) 12 4 16 16 8 8 64 64 192 64 64 64 64 64 32 32 16 8 8 40 24 40 24 64 64 1024 MC9S12XDP512 Data Sheet, Rev. 2.17 38 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family CPU and BDM Local Memory Map 0x00_0000 0x00_07FF Global Memory Map 2K REGISTERS Unimplemented RAM RAM_LOW RAM 2K REGISTERS 1K EEPROM window 1K EEPROM 4K RAM window 8K RAM 0x4000 0x13_FFFF Unpaged 16K FLASH 0x1F_FFFF 0x8000 External Space CS1 16K FLASH window PPAGE 0x3F_FFFF Unimplemented FLASH Unpaged 16K FLASH 0xFFFF Reset Vectors FLASH_LOW FLASH 0x7F_FFFF RPAGE EEPROM_LOW EEPROM Unimplemented EEPROM EEPROMSIZE CS2 FLASHSIZE CS0 39 CS2 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor EPAGE 0x0F_FFFF RAMSIZE 0x0000 0x0800 0x0C00 0x1000 0x2000 0xC000 Figure 1-3. S12X CPU & BDM Global Address Mapping CS3 Chapter 1 Device Overview MC9S12XD-Family Table 1-2. Device Internal Resources (see Figure 1-3) Device 9S12XDP512 9S12XDT512 9S12XA512 9S12XDG128 3S12XDG128 9S12XD128 9S12XD64 9S12XB128 9S12XA128 RAMSIZE/ RAM_LOW 32K 0x0F_8000 20K 0x0F_B000 32K 0x0F_8000 12K 0x0F_D000 12K 0x0F_D000 8K 0x0F_E000 4K 0x0F_F000 6K 0x0F_E800 12K 0x0F_D000 EEPROMSIZE/ EEPROM_LOW 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 2K 0x13_F800 2K 0x13_F800 2K 0x13_F800 1K 0x13_FC00 1K 0x13_FC00 2K 0x13_F800 FLASHSIZE/ FLASH_LOW 512K 0x78_0000 512K 0x78_0000 512K 0x78_0000 128K 7E_0000 128K 7E_0000 128K 7E_0000 64K 7F_0000 128K 7E_0000 128K 7E_0000 MC9S12XDP512 Data Sheet, Rev. 2.17 40 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family CPU and BDM Local Memory Map 0x00_0000 0x00_07FF Global Memory Map 2K REGISTERS Unimplemented RAM RAM_LOW RAM 2K REGISTERS 1K EEPROM window 1K EEPROM 4K RAM window 8K RAM 0x4000 0x13_FFFF Unpaged 16K FLASH 0x1F_FFFF 0x8000 External Space CS1 16K FLASH window PPAGE 0x3F_FFFF Unimplemented FLASH Unpaged 16K FLASH 0xFFFF Reset Vectors 0x78_0000 FLASH0 FLASHSIZE FLASH0_LOW Unimplemented FLASH FLASH1_HIGH FLASH1 0x7F_FFFF RPAGE EEPROM_LOW EEPROM Unimplemented EEPROM EEPROMSIZE CS2 CS0 41 CS0 CS2 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor EPAGE 0x0F_FFFF RAMSIZE 0x0000 0x0800 0x0C00 0x1000 0x2000 0xC000 Figure 1-4. S12X CPU & BDM Global Address Mapping CS3 Chapter 1 Device Overview MC9S12XD-Family Table 1-3. Device Internal Resources (see Figure 1-4) Device 9S12XDT384 9S12XDQ256 9S12XDT256 9S12XD256 9S12XA256 9S12XB256 RAMSIZE/ RAM_LOW 20K 0x0F_B000 16K 0x0F_C000 16K 0x0F_C000 14K 0x0F_C800 16K 0x0F_C000 10K 0x0F_D800 EEPROMSIZE/ EEPROM_LOW 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 2K 0x13_F800 128K 0x79_FFFF 128K 0x7E_0000 FLASHSIZE0/ FLASH_LOW 128K 0x79_FFFF FLASHSIZE1/ FLASH_HIGH 256K 0x7C_0000 MC9S12XDP512 Data Sheet, Rev. 2.17 42 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family XGATE Local Memory Map Figure 1-5. GATE Global Address Mapping Global Memory Map 0x00_0000 Registers 0x00_07FF 0x0000 Registers 0x0800 RAM 0x0F_FFFF XGRAMSIZE XGRAM_LOW RAMSIZE FLASHSIZE 43 FLASH RAM 0x78_0800 FLASH XGFLASH_HIGH 0xFFFF 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-4. XGATE Resources (see Figure 1-5) Device 9S12XDP512 9S12XDT512 9S12XDT384 9S12XA512 9S12XDQ256 9S12XD256 9S12XB256 9S12XA256 1 XGRANMSIZE XGRAM_LOW 32K 0x0F_8000 20K 0x0F_B000 20K 0x0F_B000 32K 0x0F_8000 16K 0x0F_C000 16K 0x0F_C000 10K 0x0F_D800 16K 0x0F_C000 XGFLASHSIZE1 XGFLASH_HIGH 30K 0x78_7FFF Available Flah Memory 30K on all listed parts MC9S12XDP512 Data Sheet, Rev. 2.17 44 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family XGATE Local Memory Map Figure 1-6. XGATE Global Address Mapping Global Memory Map 0x00_0000 Registers 0x00_07FF 0x0000 Registers 0x0800 RAM 0x0F_FFFF XGRAMSIZE XGRAM_LOW RAMSIZE 45 RAM 0xFFFF 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-5. XGATE Resources (see Figure 1-6) Device 9S12XDG128 3S12XDG128 9S12XD128 9S12XD64 9S12XB128 9S12XA128 XGRAMSIZE 12K 12K 8K 4K 6K 12K XGRAM_LOW 0x0F_D000 0x0F_D000 0x0F_E000 0x0F_F000 0x0F_E800 0x0F_D000 MC9S12XDP512 Data Sheet, Rev. 2.17 46 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.1.5 Part ID Assignments & Maskset Numbers The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and Mask Set number. Table 1-6. Part Names, Masksets and Assigned Part ID Numbers Part Names MC9S12XDP512 MC9S12XDT512 MC9S12XA512 MC9S12XDT384 MC9S12XDQ256 MC9S12XDT256 MC9S12XD256 MC9S12XB256 MC9S12XA256 Mask Set Number 0L15Y/1L15Y 0L15Y/1L15Y 0L15Y/1L15Y 0L15Y/1L15Y 0L15Y/1L15Y 0M84E/1M84E 0L15Y/1L15Y 0M84E/1M84E 0L15Y/1L15Y 0M84E/1M84E 0L15Y/1L15Y 0M84E/1M84E 0L15Y/1L15Y 0M84E/1M84E MC9S12XDG128 MC9S12XD128 MC9S12XA128 MC9S12XB128 1 Part ID1 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC100/0xC101/0xC102 0xC410/0xC411 0xC100/0xC101/0xC102 0xC410/0xC411 0xC100/0xC101/0xC102 0xC410/0xC411 0xC100/0xC101/0xC102 0L15Y/1L15Y 0M42E/1M42E/2M42E 0L15Y/1L15Y 0M42E/1M42E/2M42E 0L15Y/1L15Y 0M42E/1M42E/2M42E 0L15Y/1L15Y 0M42E/1M42E/2M42E The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor — non full — mask set revision 1.2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 1.2.1 Device Pinout The MC9S12XD family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 47 Chapter 1 Device Overview MC9S12XD-Family The S12XD, S12XA and S12XB family devices are offered in the following packages: • 144-pin LQFP package with an external bus interface (address/data bus) • 112-pin LQFP without external bus interface • 80-pin QFP without external bus interface See Appendix E Derivative Differences for package options. CAUTION Most the I/O Pins have different functionality depending on the module configuration. Not all functions are shown in the following pinouts. Please refer to Table 1-7 for a complete description. For avalability of the modules on different family members refer to Appendix E Derivative Differences. For pinout explanations of the different parts refer to E.7 Pinout explanations: MC9S12XDP512 Data Sheet, Rev. 2.17 48 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 CS1/KWJ2/PJ2 ACC2/ADDR22/PK6 IQSTAT3/ADDR19/PK3 IQSTAT2/ADDR18/PK2 IQSTAT1/ADDR17/PK1 IQSTAT0/ADDR16/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 ACC1/ADDR21/PK5 ACC0/ADDR20/PK4 TXD2/KWJ1/PJ1 CS3/RXD2/KWJ0/PJ0 MODC/BKGD VDDX2 VSSX2 DATA8/PC0 DATA9/PC1 DATA10/PC2 DATA11/PC3 UDS/ADDR0/PB0 ADDR1/PB1 ADDR2/PB2 ADDR3/PB3 ADDR4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 PAD23/AN23 PAD22/AN22 PAD21/AN21 PAD20/AN20 PAD19/AN19 PAD18/AN18 VSSA VRL MC9S12XD-Family 144-Pin LQFP Pins shown in BOLD-ITALICS are not available on the 112-Pin LQFP or the 80-Pin QFP package option Pins shown in BOLD are not available on the 80-Pin QFP package option VRH VDDA PAD17/AN17 PAD16/AN16 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 VDDR2 VSSR2 PA7/ADDR15 PA6/ADDR14 PA5/ADDR13 PA4/ADDR12 PA3/ADDR11 PA2/ADDR10 PA1/ADDR9 PA0/ADDR8 Figure 1-7. MC9S12XD Family Pin Assignment 144-Pin LQFP Package Freescale Semiconductor ADDR5/PB5 ADDR6/PB6 ADDR7/PB7 DATA12/PC4 DATA13/PC5 DATA14/PC6 DATA15/PC7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/ECLKX2/PE7 TAGHI/MODB/PE6 RE/TAGLO/MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PD0/DATA0 PD1/DATA1 PD2/DATA2 PD3/DATA3 LDS/LSTRB/PE3/EROMCTL WE/R/W/PE2 IRQ/PE1 XIRQ/PE0 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 MC9S12XDP512 Data Sheet, Rev. 2.17 49 Chapter 1 Device Overview MC9S12XD-Family PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOS PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 PK3 PK2 PK1 PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 PK5 PK4 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD PB0 PB1 PB2 PB3 PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 Figure 1-8. MC9S12XD Family Pin Assignments 112-Pin LQFP Package 50 PB5 PB6 PB7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/PE7 PE6 PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PE3 PE2 IRQ/PE1 XIRQ/PE0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MC9S12XD-Family 112-Pin LQFP Pins shown in BOLD are not available on the 80-Pin QFP package option VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 MC9S12XD-Family 80-Pin QFP VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Figure 1-9. MC9S12XD Family Pin Assignments 80-Pin QFP Package MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 51 PB5 PB6 PB7 XCLKS/PE7 PE6 PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Chapter 1 Device Overview MC9S12XD-Family 1.2.2 Signal Properties Summary Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences. Table 1-7. Signal Properties Summary (Sheet 1 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 EXTAL XTAL RESET TEST VREGEN XFC BKGD PAD[23:08] — — — — — — MODC AN[23:8] — — — — — — — — — — — — — — — — — — — — — — — — VDDPLL VDDPLL VDDR N.A. VDDX VDDPLL VDDX VDDA Internal Pull Resistor Description CTRL NA NA PULLUP RESET pin PUCR NA Always on PER0/ PER1 PER1 Up NA Up Reset State NA NA External reset Voltage regulator enable Input PLL loop filter Background debug DOWN Test input Oscillator pins Disabled Port AD I/O, Port AD inputs of ATD1 and analog inputs of ATD1 Disabled Port AD I/O, Port AD inputs of ATD0 and analog inputs of ATD0 Disabled Port A I/O Disabled Port BI/O Disabled Port A I/O, address bus, internal visibility data Disabled Port B I/O, address bus, internal visibility data Disabled Port B I/O, address bus, upper data strobe Disabled Port C I/O, data bus Disabled Port D I/O, data bus Up Port E I/O, system clock output, clock select Port E I/O, tag high, mode input Port E I/O, read enable, mode input, tag low input Port E I/O, bus clock output Port E I/O, low byte data strobe, EROMON control Port E I/O, read/write Port E Input, maskable interrupt PAD[07:00] AN[7:0] — — — VDDA PA[7:0] PB[7:0] PA[7:0] PB[7:1] PB0 PC[7:0] PD[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 — — — — — — — — — — — — VDDR VDDR VDDR VDDR VDDR PUCR PUCR PUCR PUCR PUCR PUCR PUCR PUCR ADDR[15:8] IVD[15:8] ADDR[7:1] ADDR0 DATA[15:8] DATA[7:0] ECLKX2 TAGHI RE ECLK LSTRB R/W IRQ IVD[7:0] UDS — — XCLKS MODB MODA — LDS WE — — — — — TAGLO — EROMCTL — — — — — — — — — — — VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR While RESET pin is low: down While RESET pin is low: down PUCR PUCR PUCR PUCR Up Up Up Up MC9S12XDP512 Data Sheet, Rev. 2.17 52 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-7. Signal Properties Summary (Sheet 2 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PJ7 XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 KWJ7 — SS2 SCK2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 TXCAN4 — TXD5 RXD5 TXD4 RXD4 — — — — SCL0 — — — — — — — — — TXCAN0 VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDX Internal Pull Resistor Description CTRL PUCR Reset State Up Port E input, non-maskable interrupt PERH/PPSH Disabled Port H I/O, interrupt, SS of SPI2, TXD of SCI5 PERH/ PPSH PERH/ PPSH Disabled Port H I/O, interrupt, SCK of SPI2, RXD of SCI5 Disabled Port H I/O, interrupt, MOSI of SPI2, TXD of SCI4 PERH/PPSH Disabled Port H I/O, interrupt, MISO of SPI2, RXD of SCI4 PERH/PPSH Disabled Port H I/O, interrupt, SS of SPI1 PERH/PPSH Disabled Port H I/O, interrupt, SCK of SPI1 PERH/PPSH Disabled Port H I/O, interrupt, MOSI of SPI1 PERH/PPSH Disabled Port H I/O, interrupt, MISO of SPI1 PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PERJ/ PPSJ PUCR PUCR PUCR PUCR Up Port J I/O, interrupt, TX of CAN4, SCL of IIC0, TX of CAN0 Port J I/O, interrupt, RX of CAN4, SDA of IIC0, RX of CAN0 Port J I/O, interrupt, SCL of IIC1, chip select 2 Port J I/O, interrupt, SDA of IIC1, chip select 0 Port J I/O, interrupt, chip select 1 Port J I/O, interrupt, TXD of SCI2 Port J I/O, interrupt, RXD of SCI2 Port K I/O Port K I/O Port K I/O, EWAIT input, ROM on control Port K I/O, extended addresses, access source for external access Extended address, PIPE status PJ6 KWJ6 RXCAN4 SDA0 RXCAN0 VDDX Up PJ5 PJ4 PJ2 PJ1 PJ0 PK7 PK[5:4] PK7 PK[6:4] KWJ5 KWJ4 KWJ2 KWJ1 KWJ0 — — EWAIT ADDR [22:20] ADDR19 SCL1 SDA1 CS1 TXD2 RXD2 — — ROMCTL ACC[2:0] CS2 CS0 — — CS3 — — — — — — — — — — — — — VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX Up Up Up Up Up Up Up Up Up PK3 IQSTAT3 — — VDDX PUCR Up MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 53 Chapter 1 Device Overview MC9S12XD-Family Table 1-7. Signal Properties Summary (Sheet 3 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 PK2 PK1 PK0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 PP7 ADDR18 ADDR17 ADDR16 TXCAN3 RXCAN3 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 KWP7 PWM7 IQSTAT2 IQSTAT1 IQSTAT0 TXD3 RXD3 TXCAN0 RXCAN0 TXCAN0 RXCAN0 — — — TXCAN4 RXCAN4 TXCAN4 RXCAN4 — — — — SCK2 — — — — — SCK0 MOSI0 SS0 MISO0 — — — VDDX VDDX VDDX VDDX Internal Pull Resistor Description CTRL PUCR PUCR PUCR PERM/ PPSM Reset State Up Up Up Extended address, PIPE status Extended address, PIPE status Extended address, PIPE status Disabled Port M I/O, TX of CAN3 and CAN4, TXD of SCI3 VDDX PERM/PPSM Disabled Port M I/O RX of CAN3 and CAN4, RXD of SCI3 VDDX PERM/PPSM Disabled Port M I/O CAN0, CAN2, CAN4, SCK of SPI0 VDDX PERM/PPSM Disabled Port M I/O, CAN0, CAN2, CAN4, MOSI of SPI0 VDDX PERM/PPSM Disabled Port M I/O TX of CAN1, CAN0, SS of SPI0 VDDX PERM/PPSM Disabled Port M I/O, RX of CAN1, CAN0, MISO of SPI0 VDDX PERM/PPSM Disabled Port M I/O, TX of CAN0 VDDX PERM/PPSM Disabled Port M I/O, RX of CAN0 VDDX PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERP/ PPSP PERS/ PPSS PERS/ PPSS Disabled Port P I/O, interrupt, channel 7 of PWM, SCK of SPI2 Disabled Port P I/O, interrupt, channel 6 of PWM, SS of SPI2 Disabled Port P I/O, interrupt, channel 5 of PWM, MOSI of SPI2 Disabled Port P I/O, interrupt, channel 4 of PWM, MISO2 of SPI2 Disabled Port P I/O, interrupt, channel 3 of PWM, SS of SPI1 Disabled Port P I/O, interrupt, channel 2 of PWM, SCK of SPI1 Disabled Port P I/O, interrupt, channel 1 of PWM, MOSI of SPI1 Disabled Port P I/O, interrupt, channel 0 of PWM, MISO2 of SPI1 Up Up Port S I/O, SS of SPI0 Port S I/O, SCK of SPI0 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SS0 SCK0 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 — — SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 — — — — — — — — — — — VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX VDDX MC9S12XDP512 Data Sheet, Rev. 2.17 54 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-7. Signal Properties Summary (Sheet 4 of 4) Pin Pin Pin Pin Pin Power Name Name Name Name Name Supply Function 1 Function 2 Function 3 Function 4 Function 5 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0] MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0] — — — — — — — — — — — — — — — — — — — — — VDDX VDDX VDDX VDDX VDDX VDDX VDDX Internal Pull Resistor Description CTRL PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERS/ PPSS PERT/ PPST Reset State Up Up Up Up Up Up Port S I/O, MOSI of SPI0 Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Port S I/O, RXD of SCI1 Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0 Disabled Port T I/O, timer channels NOTE For devices assembled in 80-pin and 112-pin packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-7 for affected pins. 1.2.3 Detailed Signal Descriptions NOTE This section describes all pins which are availabe on the cover part MC9S12XDP512 in 144-pin LQFP package. For modules and pinout explanations of the different family members refer to E.7 Pinout explanations: and E.5 Peripheral Sets S12XD - Family and E.6 Peripheral Sets S12XA & S12XB - Family 1.2.3.1 EXTAL, XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 1.2.3.2 RESET — External Reset Pin The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.The RESET pin has an internal pullup device. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 55 Chapter 1 Device Overview MC9S12XD-Family 1.2.3.3 TEST — Test Pin NOTE The TEST pin must be tied to VSS in all applications. This input only pin is reserved for test. This pin has a pulldown device. 1.2.3.4 VREGEN — Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device. 1.2.3.5 XFC — PLL Loop Filter Pin Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. VDDPLL CS MCU R0 CP VDDPLL XFC Figure 1-10. PLL Loop Filter Connections 1.2.3.6 BKGD / MODC — Background Debug and Mode Pin The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has a pullup device. 1.2.3.7 PAD[23:8] / AN[23:8] — Port AD Input Pins of ATD1 PAD[23:8] are general-purpose input or output pins and analog inputs AN[23:8] of the analog-to-digital converter ATD1. 1.2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins of ATD0 PAD[7:0] are general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital converter ATD0. 1.2.3.9 PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1 PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital converter ATD1. MC9S12XDP512 Data Sheet, Rev. 2.17 56 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.2.3.10 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data. 1.2.3.11 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data. 1.2.3.12 PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0 PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation, this pin is used for external address bus ADDR0 and internal visibility read data IVD0. 1.2.3.13 PB[7:0] — Port B I/O Pins PB[7:0] are general-purpose input or output pins. 1.2.3.14 PC[7:0] / DATA [15:8] — Port C I/O Pins PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes. 1.2.3.15 PD[7:0] / DATA [7:0] — Port D I/O Pins PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external data bus. The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes. 1.2.3.16 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7 PE7 is a general-purpose input or output pin. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 57 Chapter 1 Device Overview MC9S12XD-Family The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of reset. The pin can be configured to drive the internal system clock ECLKX2. EXTAL C1 MCU XTAL C2 VSSPLL Crystal or Ceramic Resonator Figure 1-11. Loop Controlled Pierce Oscillator Connections (PE7 = 1) EXTAL C1 MCU RS XTAL C2 VSSPLL RB Crystal or Ceramic Resonator Figure 1-12. Full Swing Pierce Oscillator Connections (PE7 = 0) EXTAL MCU XTAL CMOS-Compatible External Oscillator Not Connected Figure 1-13. External Clock Connections (PE7 = 0) 1.2.3.17 PE6 / MODB / TAGHI — Port E I/O Pin 6 PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a MC9S12XDP512 Data Sheet, Rev. 2.17 58 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue. The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE6 is configured to reduced levels out of reset in expanded and emulation modes. 1.2.3.18 PE5 / MODA / TAGLO / RE — Port E I/O Pin 5 PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the read enable RE output. This pin is an input with a pull-down device which is only active when RESET is low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue. The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE5 is configured to reduced levels out of reset in expanded and emulation modes. 1.2.3.19 PE4 / ECLK — Port E I/O Pin 4 PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference. 1.2.3.20 PE3 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3 PE3 is a general-purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET the state of this pin is latched to the EROMON bit. 1.2.3.21 PE2 / R/W / WE— Port E I/O Pin 2 PE2 is a general-purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal or write enable output signal for the external bus. It indicates the direction of data on the external bus 1.2.3.22 PE[6:2] — Port E I/O Pins PE[6:2] are general-purpose input or output pins. 1.2.3.23 PE1 / IRQ — Port E Input Pin 1 PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. 1.2.3.24 PE0 / XIRQ — Port E Input Pin 0 PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 59 Chapter 1 Device Overview MC9S12XD-Family 1.2.3.25 PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7 PH7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as slave select pin SS of the serial peripheral interface 2 (SPI2). It can be configured as the transmit pin TXD of serial communication interface 5 (SCI5). 1.2.3.26 PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6 PH6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as serial clock pin SCK of the serial peripheral interface 2 (SPI2). It can be configured as the receive pin (RXD) of serial communication interface 5 (SCI5). 1.2.3.27 PH5 / KWH5 / MOSI2 / TXD4 — Port H I/O Pin 5 PH5 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). It can be configured as the transmit pin TXD of serial communication interface 4 (SCI4). 1.2.3.28 PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 4 PH4 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). It can be configured as the receive pin RXD of serial communication interface 4 (SCI4). 1.2.3.29 PH3 / KWH3 / SS1 — Port H I/O Pin 3 PH3 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as slave select pin SS of the serial peripheral interface 1 (SPI1). 1.2.3.30 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 PH2 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as serial clock pin SCK of the serial peripheral interface 1 (SPI1). 1.2.3.31 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 PH1 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). MC9S12XDP512 Data Sheet, Rev. 2.17 60 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.2.3.32 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 PH0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 1 (SPI1). 1.2.3.33 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 PJ7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the transmit pin TXCAN for the scalable controller area network controller 0 or 4 (CAN0 or CAN4) or as the serial clock pin SCL of the IIC0 module. 1.2.3.34 PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 — PORT J I/O Pin 6 PJ6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the receive pin RXCAN for the scalable controller area network controller 0 or 4 (CAN0 or CAN4) or as the serial data pin SDA of the IIC0 module. 1.2.3.35 PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5 PJ5 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the serial clock pin SCL of the IIC1 module. It can be configured to provide a chip-select output. 1.2.3.36 PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4 PJ4 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the serial data pin SDA of the IIC1 module. It can be configured to provide a chip-select output. 1.2.3.37 PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2 PJ2 is a general-purpose input or output pins. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured to provide a chip-select output. 1.2.3.38 PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1 PJ1 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the transmit pin TXD of the serial communication interface 2 (SCI2). 1.2.3.39 PJ0 / KWJ0 / RXD2 / CS3 — PORT J I/O Pin 0 PJ0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the receive pin RXD of the serial communication interface 2 (SCI2).It can be configured to provide a chip-select output. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 61 Chapter 1 Device Overview MC9S12XD-Family 1.2.3.40 PK7 / EWAIT / ROMCTL — Port K I/O Pin 7 PK7 is a general-purpose input or output pin. During MCU emulation modes and normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read). The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PK7 is configured to reduced levels out of reset in expanded and emulation modes. 1.2.3.41 PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4] PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is time multiplexed with the high addresses 1.2.3.42 PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0] PK3-PK0 are general-purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information. 1.2.3.43 PK7,PK[5:0] — Port K I/O Pins 7 & [5:0] PK7 and PK[5:0] are general-purpose input or output pins. 1.2.3.44 PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7 PM7 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM7 can be configured as the transmit pin TXD3 of the serial communication interface 3 (SCI3). 1.2.3.45 PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6 PM6 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM6 can be configured as the receive pin RXD3 of the serial communication interface 3 (SCI3). 1.2.3.46 PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 — Port M I/O Pin 5 PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers 0, 2 or 4 (CAN0, CAN2, or CAN4). It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). MC9S12XDP512 Data Sheet, Rev. 2.17 62 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.2.3.47 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4 PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controllers 0, 2, or 4 (CAN0, CAN2, or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the serial peripheral interface 0 (SPI0). 1.2.3.48 PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the serial peripheral interface 0 (SPI0). 1.2.3.49 PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2 PM2 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the serial peripheral interface 0 (SPI0). 1.2.3.50 PM1 / TXCAN0 — Port M I/O Pin 1 PM1 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controller 0 (CAN0). 1.2.3.51 PM0 / RXCAN0 — Port M I/O Pin 0 PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controller 0 (CAN0). 1.2.3.52 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 PP7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 7 output. It can be configured as serial clock pin SCK of the serial peripheral interface 2 (SPI2). 1.2.3.53 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6 PP6 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 6 output. It can be configured as slave select pin SS of the serial peripheral interface 2 (SPI2). 1.2.3.54 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5 PP5 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 5 output. It can MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 63 Chapter 1 Device Overview MC9S12XD-Family be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). 1.2.3.55 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4 PP4 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 2 (SPI2). 1.2.3.56 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3 PP3 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the serial peripheral interface 1 (SPI1). 1.2.3.57 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 PP2 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the serial peripheral interface 1 (SPI1). 1.2.3.58 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1 PP1 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). 1.2.3.59 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0 PP0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 1 (SPI1). 1.2.3.60 PS7 / SS0 — Port S I/O Pin 7 PS7 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial peripheral interface 0 (SPI0). 1.2.3.61 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). MC9S12XDP512 Data Sheet, Rev. 2.17 64 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.2.3.62 PS5 / MOSI0 — Port S I/O Pin 5 PS5 is a general-purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0). 1.2.3.63 PS4 / MISO0 — Port S I/O Pin 4 PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0). 1.2.3.64 PS3 / TXD1 — Port S I/O Pin 3 PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 1 (SCI1). 1.2.3.65 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 1 (SCI1). 1.2.3.66 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial communication interface 0 (SCI0). 1.2.3.67 PS0 / RXD0 — Port S I/O Pin 0 PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial communication interface 0 (SCI0). 1.2.3.68 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] PT[7:0] are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC[7:0] of the enhanced capture timer (ECT). 1.2.4 Power Supply Pins NOTE All VSS pins must be connected together in the application. MC9S12XDP512 power and ground pins are described below. 1.2.4.1 VDDX1, VDDX2, VSSX1,VSSX2 — Power and Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 65 Chapter 1 Device Overview MC9S12XD-Family 1.2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 — Power and Ground Pins for I/O Drivers and for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. 1.2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5-V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE No load allowed except for bypass capacitors. 1.2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog-to-digital converters. 1.2.4.5 VRH, VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog-to-digital converter. 1.2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the oscillator and the phased-locked loop. This allows the supply voltage to the oscillator and PLL to be bypassed independently. This 2.5-V voltage is generated by the internal voltage regulator. NOTE No load allowed except for bypass capacitors. MC9S12XDP512 Data Sheet, Rev. 2.17 66 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-8. MC9S12XD Family Power and Ground Connection Summary Pin Number Mnemonic 144-Pin LQFP 15, 87 16, 88 53 52 139 138 26 27 82 81 107 110 112-Pin LQFP 13, 65 14, 66 41 40 107 106 N.A. N.A. N.A. N.A. 83 86 80-Pin QFP 9, 49 10, 50 29 28 77 76 N.A. N.A. N.A. N.A. 59 62 Nominal Voltage 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V Description VDD1, 2 VSS1, 2 VDDR1 VSSR1 VDDX1 VSSX1 VDDX2 VSSX2 VDDR2 VSSR2 VDDA VSSA Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator External power and ground, supply to pin drivers External power and ground, supply to pin drivers External power and ground, supply to pin drivers Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the phased-locked loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. VRL VRH VDDPLL VSSPLL 109 108 55 57 85 84 43 45 61 60 31 33 0V 5.0 V 2.5 V 0V MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 67 Chapter 1 Device Overview MC9S12XD-Family 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules. See 79Chapterf or details on clock generation. SCI Modules SPI Modules CAN Modules IIC Modules ATD Modules Bus Clock PIT EXTAL Oscillator Clock ECT CRG PIM Core Clock XTAL RAM S12X XGATE FLASH EEPROM Figure 1-14. MC9S12XD Family Clock Connections The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: • The on-chip phase locked loop (PLL) • the PLL self clocking • the oscillator The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-12, this system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The oscillator clock is used as a time base to derive the program and erase times for the NVM’s. See the Flash and EEPROM section for more details on the operation of the NVM’s. MC9S12XDP512 Data Sheet, Rev. 2.17 68 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. This allows the user to select its clock based on the required jitter performance. Consult MSCAN block description for more details on the operation and configuration of the CAN blocks. In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to generate a system reset if it is allowed to time out as a result of no oscillator clock being present. In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more accurate check of the clock. The clock quality checker counts a predetermined number of clock edges within a defined time window to insure that the clock is running. The checker can be invoked following specific events such as on wake-up or clock monitor failure. 1.4 Chip Configuration Summary CAUTION Emulation single chip mode, Normal expanded mode, Emulation expanded mode and ROMCTL/EROMCTL functionality is only available on parts with external bus interface in 144 LQFP package. see Appendix E Derivative Differences. The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL signal on rising edge of RESET, and the security state of the MCU affects the following device characteristics: • External bus interface configuration • Flash in memory map, or not • Debug features enabled or disabled The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals during reset (see Table 1-9). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA signals are latched into these bits on the rising edge of RESET. In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See Table 1-9.) For a detailed description of the ROMON and EROMON bits refer to the S12X_MMC section. The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MISC register on the rising edge of RESET. The MCU can operate in two different modes. The operating mode out of reset is determined by the state of the MODC signal during reset. The MODC bit in the MODE register shows the current operating mode and provide limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 69 Chapter 1 Device Overview MC9S12XD-Family Table 1-9. Chip Modes and Data Sources Chip Modes Normal single chip Special single chip Emulation single chip Normal expanded Emulation expanded BKGD = MODC 1 0 0 1 0 PE6 = MODB 0 0 0 0 1 PE5 = MODA 0 0 1 1 1 X X 0 1 0 1 1 Special test 1 PK7 = ROMCTL X PE3 = EROMCTL X 0 1 X X X 0 1 X X Data Source1 Internal Emulation memory Internal Flash External application Internal Flash External application Emulation memory Internal Flash External application Internal Flash 0 1 0 0 1 Internal means resources inside the MCU are read/written. Internal Flash means Flash resources inside the MCU are read/written. Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM, and register space are always considered internal). External application means resources residing outside the MCU are read/written. The configuration of the oscillator can be selected using the XCLKS signal (see Table 1-10). For a detailed description please refer to the S12CRG section. Table 1-10. Clock Selection Based on PE7 PE7 = XCLKS 0 1 Description Full swing Pierce oscillator or external clock source selected Loop controlled Pierce oscillator selected The logic level on the voltage regulator enable pin VREGEN determines whether the on-chip voltage regulator is enabled or disabled (see Table 1-11). Table 1-11. Voltage Regulator VREGEN VREGEN 1 0 Description Internal voltage regulator enabled Internal voltage regulator disabled, VDD1,2 and VDDPLL must be supplied externally MC9S12XDP512 Data Sheet, Rev. 2.17 70 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.5 1.5.1 1.5.1.1 Modes of Operation User Modes Normal Expanded Mode Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate. 1.5.1.2 Normal Single-Chip Mode There is no external bus in this mode. The processor program is executed from internal memory. Ports A, B,C,D, K, and most pins of port E are available as general-purpose I/O. 1.5.1.3 Special Single-Chip Mode This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external bus after reset in this mode. 1.5.1.4 Emulation of Expanded Mode Developers use this mode for emulation systems in which the users target application is normal expanded mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. 1.5.1.5 Emulation of Single-Chip Mode Developers use this mode for emulation systems in which the user’s target application is normal single-chip mode. Code is executed from external memory or from internal memory depending on the state of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface. 1.5.1.6 Special Test Mode Freescale internal use only. 1.5.2 Low-Power Modes The microcontroller features two main low-power modes. Consult the respective sections for information on the module behavior in system stop, system pseudo stop, and system wait mode. An important source of information about the clock system is the Clock and Reset Generator S12CRG section. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 71 Chapter 1 Device Overview MC9S12XD-Family 1.5.2.1 System Stop Modes The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to CRG section. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes. 1.5.2.2 Pseudo Stop Mode In this mode the clocks are stopped but the oscillator is still running and the real time interrupt (RTI) or watchdog (COP) submodule can stay active. Other peripherals are turned off. This mode consumes more current than the system stop mode, but the wake up time from this mode is significantly shorter. 1.5.2.3 Full Stop Mode The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen. 1.5.2.4 System Wait Mode This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in system wait mode. For further power consumption the peripherals can individually turn off their local clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that has not been masked ends system wait mode. 1.5.3 Freeze Mode The enhanced capture timer, pulse width modulator, analog-to-digital converters, the periodic interrupt timer and the XGATE module provide a software programmable option to freeze the module status during the background debug module is active. This is useful when debugging application software. For detailed description of the behavior of the ATD0, ATD1, ECT, PWM, XGATE and PIT when the background debug module is active consult the corresponding sections.. 1.6 Resets and Interrupts Consult the S12XCPU Block Guide for information on exception processing. 1.6.1 Vectors Table 1-12 lists all interrupt sources and vectors in the default order of priority. The interrupt module (S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. MC9S12XDP512 Data Sheet, Rev. 2.17 72 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-12. Interrupt Vector Locations (Sheet 1 of 3) Vector Address1 $FFFE $FFFC $FFFA Vector base + $F8 Vector base+ $F6 Vector base+ $F4 Vector base+ $F2 Vector base+ $F0 Vector base+ $EE Vector base + $EC Vector base+ $EA Vector base+ $E8 Vector base+ $E6 Vector base+ $E4 Vector base + $E2 Vector base+ $E0 Vector base+ $DE Vector base+ $DC Vector base + $DA Vector base + $D8 Vector base+ $D6 Vector base + $D4 Vector base + $D2 Vector base + $D2 Vector base + $D0 Vector base + $CE Vector base + $CC Vector base + $CA Vector base + $C8 Vector base + $C6 Vector base + $C4 Vector base + $C2 Vector base + $C0 $60 IIC0 bus $68 $67 $66 $65 $64 $63 $62 ATD1 Port J Port H Modulus down counter underflow Pulse accumulator B overflow CRG PLL lock CRG self-clock mode Reserved I bit IBCR0 (IBIE) XGATE Channel ID2 — — — — — — — $78 $77 $76 $75 $74 $73 $72 $71 $70 $6F $6E $6D $6C $6B $6A $69 Interrupt Source System reset or illegal access reset Clock monitor reset COP watchdog reset Unimplemented instruction trap SWI XIRQ IRQ Real time interrupt Enhanced capture timer channel 0 Enhanced capture timer channel 1 Enhanced capture timer channel 2 Enhanced capture timer channel 3 Enhanced capture timer channel 4 Enhanced capture timer channel 5 Enhanced capture timer channel 6 Enhanced capture timer channel 7 Enhanced capture timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 Reserved I bit I bit I bit I bit I bit I bit I bit ATD1CTL2 (ASCIE) PIEJ (PIEJ7-PIEJ0) PIEH (PIEH7-PIEH0) MCCTL(MCZI) PBCTL(PBOVI) CRGINT(LOCKIE) CRGINT (SCMIE) CCR Mask None None None None None X Bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Local Enable None PLLCTL (CME, SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOF) PACTL (PAOVI) PACTL (PAI) SPI0CR1 (SPIE, SPTIE) SCI0CR2 (TIE, TCIE, RIE, ILIE) SCI1CR2 (TIE, TCIE, RIE, ILIE) ATD0CTL2 (ASCIE) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 73 Chapter 1 Device Overview MC9S12XD-Family Table 1-12. Interrupt Vector Locations (Sheet 2 of 3) Vector Address1 Vector base + $BE Vector base + $BC Vector base + $BC Vector base + $BA Vector base + $B8 Vector base + $B6 Vector base + $B4 Vector base + $B2 Vector base + $B0 Vector base + $AE Vector base + $AC Vector base + $AA Vector base + $A8 Vector base + $A6 Vector base + $A4 Vector base + $A2 Vector base + $A0 Vector base + $9E Vector base+ $9C Vector base+ $9A Vector base + $98 Vector base + $AE to Vector base + 98 Vector base + $9E to Vector base + 98 Vector base + $96 Vector base + $94 Vector base + $92 Vector base + $90 Vector base + $8E Vector base+ $8C Vector base + $8A $4B $4A $49 $48 $47 $46 $45 CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit Port P Interrupt PWM emergency shutdown SCI2 $5D $5C $5B $5A $59 $58 $57 $56 $55 $54 $53 $52 $51 $50 $4F $4E $4D $4C EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CAN1 transmit CAN2 wake-up CAN2 errors CAN2 receive CAN2 transmit CAN3 wake-up CAN3 errors CAN3 receive CAN3 transmit Reserved XGATE Channel ID2 $5F $5E Interrupt Source SPI1 SPI2 RESERVED I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit ECNFG (CCIE, CBEIE) FCNFG (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE[2:0]) CAN1RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) CAN1TIER (TXEIE[2:0]) CAN2RIER (WUPIE) CAN2RIER (CSCIE, OVRIE) CAN2RIER (RXFIE) CAN2TIER (TXEIE[2:0]) CAN3RIER (WUPIE) CAN3RIER (CSCIE, OVRIE) CAN3RIER (RXFIE) CAN3TIER (TXEIE[2:0]) CCR Mask I bit I bit Local Enable SPI1CR1 (SPIE, SPTIE) SPI2CR1 (SPIE, SPTIE) Reserved I bit I bit I bit I bit I bit I bit I bit CAN4RIER (WUPIE) CAN4RIER (CSCIE, OVRIE) CAN4RIER (RXFIE) CAN4TIER (TXEIE[2:0]) PIEP (PIEP7-PIEP0) PWMSDN (PWMIE) SCI2CR2 (TIE, TCIE, RIE, ILIE) MC9S12XDP512 Data Sheet, Rev. 2.17 74 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family Table 1-12. Interrupt Vector Locations (Sheet 3 of 3) Vector Address1 Vector base + $88 Vector base + $8A to Vector base + $88 Vector base + $86 Vector base + $84 Vector base + $86 to Vector base + $84 Vector base + $82 Vector base + $82 Vector base + $80 Vector base + $7E Vector base + $7C Vector base + $7A Vector base + $78 Vector base + $76 Vector base + $74 Vector base + $72 Vector base + $70 Vector base + $6E Vector base + $6C Vector base + $6A Vector base + $68 Vector base + $66 Vector base + $64 Vector base + $62 Vector base + $60 Vector base+ $12 to Vector base + $5E Vector base + $10 1 2 XGATE Channel ID2 $44 Interrupt Source SCI3 CCR Mask I bit Local Enable SCI3CR2 (TIE, TCIE, RIE, ILIE) Reserved $43 $42 SCI4 SCI5 I bit I bit SCI4CR2 (TIE, TCIE, RIE, ILIE) SCI5CR2 (TIE, TCIE, RIE, ILIE) Reserved $41 IIC1 Bus Reserved $40 $3F Low-voltage interrupt (LVI) Autonomous periodical interrupt (API) Reserved $3D $3C $3B $3A $39 $38 $37 $36 $35 $34 $33 $32 — — Periodic interrupt timer channel 0 Periodic interrupt timer channel 1 Periodic interrupt timer channel 2 Periodic interrupt timer channel 3 XGATE software trigger 0 XGATE software trigger 1 XGATE software trigger 2 XGATE software trigger 3 XGATE software trigger 4 XGATE software trigger 5 XGATE software trigger 6 XGATE software trigger 7 XGATE software error interrupt S12XCPU RAM access violation Reserved I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit PITINTE (PINTE0) PITINTE (PINTE1) PITINTE (PINTE2) PITINTE (PINTE3) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) XGMCTL (XGIE) RAMWPC (AVIE) I bit I bit VREGCTRL (LVIE) VREGAPICTRL (APIE) I bit IBCR (IBIE) — Spurious interrupt — None 16 bits vector address based For detailed description of XGATE channel ID refer to XGATE Block Guide MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 75 Chapter 1 Device Overview MC9S12XD-Family 1.6.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states. 1.6.2.1 I/O Pins Refer to the PIM Block Guide for reset configurations of all peripheral module ports. 1.6.2.2 Memory The RAM array is not initialized out of reset. 1.7 COP Configuration The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See Table 1-13 and Table 1-14 for coding. The FCTL register is loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence NOTE If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset. Table 1-13. Initial COP Rate Configuration NV[2:0] in FCTL Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000 Table 1-14. Initial WCOP Configuration NV[3] in FCTL Register 1 0 WCOP in COPCTL Register 0 1 MC9S12XDP512 Data Sheet, Rev. 2.17 76 Freescale Semiconductor Chapter 1 Device Overview MC9S12XD-Family 1.8 ATD0 External Trigger Input Connection The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the external trigger inputs on MC9S12XDP512. Table 1-15. ATD0 External Trigger Sources External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connected to . . Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger0 PITTRIG[0]. Periodic interrupt timer hardware trigger1 PITTRIG[1]. See Section Chapter 5, “Analog-to-Digital Converter (S12ATD10B8CV3) for information about the analog-to-digital converter module. When this section refers to freeze mode this is equivalent to active BDM mode. 1.9 ATD1 External Trigger Input Connection The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events. Table 1-16 shows the connection of the external trigger inputs on MC9S12XDP512. Table 1-16. ATD1 External Trigger Sources External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connected to . . Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger0 PITTRIG[0]. Periodic interrupt timer hardware trigger1 PITTRIG[1]. See Section Chapter 4, “Analog-to-Digital Converter (ATD10B16CV4) Block Description for information about the analog-to-digital converter module. When this section refers to freeze mode this is equivalent to active BDM mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 77 Chapter 1 Device Overview MC9S12XD-Family MC9S12XDP512 Data Sheet, Rev. 2.17 78 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1 Introduction This specification describes the function of the clocks and reset generator (CRG). 2.1.1 Features The main features of this block are: • Phase locked loop (PLL) frequency multiplier — Reference divider — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Interrupt request on entry or exit from locked condition — Self clock mode in absence of reference clock • System clock generator — Clock quality check — User selectable fast wake-up from Stop in self-clock mode for power saving and immediate program execution — Clock switch for either oscillator or PLL based system clocks • Computer operating properly (COP) watchdog timer with time-out clear window • System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 79 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. • Wait mode In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL register. • Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo stop mode (PSTP = 1). — Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. — Pseudo stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set, the COP and RTI will continue to run, or else they remain frozen. • Self clock mode Self clock mode will be entered if the clock monitor enable bit (CME) and the self clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self clock mode is entered, the CRG starts to perform a clock quality check. Self clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. MC9S12XDP512 Data Sheet, Rev. 2.17 80 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1.3 Block Diagram Figure 2-1 shows a block diagram of the CRG. Illegal Address Reset Power on Reset Low Voltage Reset S12X_MMC Voltage Regulator CRG RESET Clock Monitor CM fail COP Timeout Reset Generator Clock Quality Checker COP RTI System Reset XCLKS EXTAL XTAL OSCCLK Oscillator Bus Clock Core Clock Oscillator Clock Registers XFC VDDPLL VSSPLL PLLCLK PLL Clock and Reset Control Real Time Interrupt PLL Lock Interrupt Self Clock Mode Interrupt Figure 2-1. CRG Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 81 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.2 External Signal Description This section lists and describes the signals that connect off chip. 2.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL and VSSPLL must be connected to properly. 2.2.2 XFC — External Loop Filter Pin A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter that eliminates the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device specification for calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied to VDDPLL. VDDPLL CS MCU RS XFC CP Figure 2-2. PLL Loop Filter Connections 2.2.3 RESET — Reset Pin RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has been triggered. 2.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the CRG. MC9S12XDP512 Data Sheet, Rev. 2.17 82 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.1 Module Memory Map Table 2-1. CRG Memory Map Address Offset 0x_00 0x_01 0x_02 0x_03 0x_04 0x_05 0x_06 0x_07 0x_08 0x_09 0x_0A 0x_0B 1 2 Table 2-1 gives an overview on all CRG registers. Use CRG Synthesizer Register (SYNR) CRG Reference Divider Register (REFDV) CRG Test Flags Register (CTFLG) CRG Flags Register (CRGFLG) CRG Interrupt Enable Register (CRGINT) CRG Clock Select Register (CLKSEL) CRG PLL Control Register (PLLCTL) CRG RTI Control Register (RTICTL) CRG COP Control Register (COPCTL) CRG Force and Bypass Test Register CRG Test Control Register (FORBYP)2 1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (CTCTL)3 CRG COP Arm/Timer Reset (ARMCOP) CTFLG is intended for factory test purposes only. FORBYP is intended for factory test purposes only. 3 CTCTL is intended for factory test purposes only. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 83 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2 Register Descriptions This section describes in address order all the CRG registers and their individual bits. Register Name SYNR R W REFDV R W CTFLG R W CRGFLG R W CRGINT R W CLKSEL R W PLLCTL R W RTICTL R W COPCTL R W FORBYP R W CTCTL R W ARMCOP R W 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 1 0 0 0 0 0 0 0 RTIF PORF LVRF 0 LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 Bit 7 0 6 0 5 SYN5 4 SYN4 3 SYN3 2 SYN2 1 SYN1 Bit 0 SYN0 REFDV5 0 REFDV4 0 REFDV3 0 REFDV2 0 REFDV1 0 REFDV0 0 RTIE ILAF LOCKIE 0 0 0 SCMIE 0 PLLSEL PSTP 0 PLLWAI 0 RTIWAI COPWAI CME PLLON AUTO ACQ FSTWKP PRE PCE SCME RTDEC RTR6 RTR5 0 WRTMASK 0 RTR4 0 RTR3 0 RTR2 RTR1 RTR0 WCOP 0 RSBCK 0 CR2 0 CR1 0 CR0 0 0 0 = Unimplemented or Reserved Figure 2-3. S12CRGV6 Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 84 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (fSCM). ( SYNR + 1 ) PLLCLK = 2xOSCCLKx ----------------------------------( REFDV + 1 ) NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 SYN5 0 SYN4 0 SYN3 0 SYN2 0 SYN1 0 SYN0 0 = Unimplemented or Reserved Figure 2-4. CRG Synthesizer Register (SYNR) Read: Anytime Write: Anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit. 2.3.2.2 CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 REFDV5 0 REFDV4 0 REFDV3 0 REFDV2 0 REFDV1 0 REFDV0 0 = Unimplemented or Reserved Figure 2-5. CRG Reference Divider Register (REFDV) Read: Anytime Write: Anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 85 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.3 Reserved Register (CTFLG) This register is reserved for factory testing of the CRG module and is not available in normal modes. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-6. Reserved Register (CTFLG) Read: Always reads 0x_00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG fucntionality. 2.3.2.4 CRG Flags Register (CRGFLG) This register provides CRG status bits and flags. 7 6 5 4 3 2 1 0 R W Reset RTIF 0 PORF 1 LVRF 2 LOCKIF 0 LOCK 0 TRACK 0 SCMIF 0 SCM 0 1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved Figure 2-7. CRG Flags Register (CRGFLG) Read: Anytime Write: Refer to each bit for individual write conditions Table 2-2. CRGFLG Field Descriptions Field 7 RTIF Description Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred. 6 PORF MC9S12XDP512 Data Sheet, Rev. 2.17 86 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-2. CRGFLG Field Descriptions (continued) Field 5 LVRF Description Low Voltage Reset Flag — If low voltage reset feature is not available (see device specification) LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. Lock Status Bit — LOCK reflects the current state of PLL lock condition. This bit is cleared in self clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self clock mode. Writes have no effect. 0 Acquisition mode status. 1Tracking mode status. Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM. 4 LOCKIF 3 LOCK 2 TRACK 1 SCMIF 0 SCM MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 87 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. 7 6 5 4 3 2 1 0 R W Reset RTIE 0 ILAF 1 0 0 LOCKIE 0 0 0 0 0 SCMIE 0 0 0 1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 2-8. CRG Interrupt Enable Register (CRGINT) Read: Anytime Write: Anytime Table 2-3. CRGINT Field Descriptions Field 7 RTIE 6 ILAF Description Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address reset has not occurred. 1 Illegal address reset has occurred. Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self ClockMmode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. 4 LOCKIE 1 SCMIE MC9S12XDP512 Data Sheet, Rev. 2.17 88 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 2-17 for more details on the effect of each bit. 7 6 5 4 3 2 1 0 R W Reset PLLSEL 0 PSTP 0 0 0 0 0 PLLWAI 0 0 0 RTIWAI 0 COPWAI 0 = Unimplemented or Reserved Figure 2-9. CRG Clock Select Register (CLKSEL) Read: Anytime Write: Refer to each bit for individual write conditions Table 2-4. CLKSEL Field Descriptions Field 7 PLLSEL Description PLL Select Bit — Write anytime. Writing a1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self clock mode, Stop mode or wait mode with PLLWAI bit set. 0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2). 1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2). Pseudo Stop Bit Write: Anytime This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo stop). Note: Pseudo stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. PLL Stops in Wait Mode Bit Write: Anytime If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode, but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set, the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. RTI Stops in Wait Mode Bit Write: Anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COP Stops in Wait Mode Bit Normal modes: Write once Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP counter whenever the part goes into wait mode. 6 PSTP 3 PLLWAI 1 RTIWAI 0 COPWAI MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 89 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.7 CRG PLL Control Register (PLLCTL) This register controls the PLL functionality. 7 6 5 4 3 2 1 0 R W Reset CME 1 PLLON 1 AUTO 1 ACQ 1 FSTWKP 0 PRE 0 PCE 0 SCME 1 Figure 2-10. CRG PLL Control Register (PLLCTL) Read: Anytime Write: Refer to each bit for individual write conditions Table 2-5. PLLCTL Field Descriptions Field 7 CME Description Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality, this could cause unpredictable operation of the MCU! Note: In stop mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor is disabled independently of the CME bit setting and any loss of external clock will not be detected. Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI = 1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. Acquisition Bit Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If self-clock mode is disabled (SCME = 0) this bit has no effect. 0 Fast wake-up from full stop mode is disabled. 1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately resume operation i self-clock mode (see Section 2.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with oscillator and clock monitor disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to OSCCLK. The SCMIF flag will be set. See application examples in Figure 2-23 and Figure 2-24. 6 PLLON 5 AUTO 4 ACQ 3 FSTWKP MC9S12XDP512 Data Sheet, Rev. 2.17 90 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-5. PLLCTL Field Descriptions (continued) Field 2 PRE Description RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime. 0 RTI stops running during pseudo stop mode. 1 RTI continues running during pseudo stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. COP Enable during Pseudo Stop Bit — PCE enables the COP during pseudo stop mode. Write anytime. 0 COP stops running during pseudo stop mode 1 COP continues running during pseudo stop mode Note: If the PCE bit is cleared, the COP dividers will go static while pseudo stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. Self Clock Mode Enable Bit Normal modes: Write once Special modes: Write anytime SCME can not be cleared while operating in self clock mode (SCM = 1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 2.5.2, “Clock Monitor Reset”). 1 Detection of crystal clock failure forces the MCU in self clock mode (see Section 2.4.2.2, “Self Clock Mode”). 1 PCE 0 SCME 2.3.2.8 CRG RTI Control Register (RTICTL) This register selects the timeout period for the real time interrupt. 7 6 5 4 3 2 1 0 R W Reset RTDEC 0 RTR6 0 RTR5 0 RTR4 0 RTR3 0 RTR2 0 RTR1 0 RTR0 0 Figure 2-11. CRG RTI Control Register (RTICTL) Read: Anytime Write: Anytime NOTE A write to this register initializes the RTI counter. Table 2-6. RTICTL Field Descriptions Field 7 RTDEC 6–4 RTR[6:4] 3–0 RTR[3:0] Description Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 2-7 1 Decimal based divider value. See Table 2-8 Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 2-7 and Table 2-8. Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 2-7 and Table 2-8 show all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 91 Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-7. RTI Frequency Divide Rates for RTDEC = 0 RTR[6:4] = RTR[3:0] 000 (OFF) OFF* OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216 0000 (÷1) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 1001 (÷10) 1010 (÷11) 1011 (÷12) 1100 (÷13) 1101 (÷14) 1110 (÷15) 1111 (÷16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. MC9S12XDP512 Data Sheet, Rev. 2.17 92 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-8. RTI Frequency Divide Rates for RTDEC = 1 RTR[6:4] = RTR[3:0] 000 (1x103) 1x103 2x103 3x103 4x103 5x103 6x103 7x103 8x103 9x103 10 x103 11 x103 12x103 13x103 14x103 15x103 16x103 001 (2x103) 2x103 4x103 6x103 8x103 10x103 12x103 14x103 16x103 18x103 20x103 22x103 24x103 26x103 28x103 30x103 32x103 010 (5x103) 5x103 10x103 15x103 20x103 25x103 30x103 35x103 40x103 45x103 50x103 55x103 60x103 65x103 70x103 75x103 80x103 011 (10x103) 10x103 20x103 30x103 40x103 50x103 60x103 70x103 80x103 90x103 100x103 110x103 120x103 130x103 140x103 150x103 160x103 100 (20x103) 20x103 40x103 60x103 80x103 100x103 120x103 140x103 160x103 180x103 200x103 220x103 240x103 260x103 280x103 300x103 320x103 101 (50x103) 50x103 100x103 150x103 200x103 250x103 300x103 350x103 400x103 450x103 500x103 550x103 600x103 650x103 700x103 750x103 800x103 110 (100x103) 100x103 200x103 300x103 400x103 500x103 600x103 700x103 800x103 900x103 1x106 1.1x106 1.2x106 1.3x106 1.4x106 1.5x106 1.6x106 111 (200x103) 200x103 400x103 600x103 800x103 1x106 1.2x106 1.4x106 1.6x106 1.8x106 2x106 2.2x106 2.4x106 2.6x106 2.8x106 3x106 3.2x106 0000 (÷1) 0001 (÷2) 0010 (÷3) 0011 (÷4) 0100 (÷5) 0101 (÷6) 0110 (÷7) 0111 (÷8) 1000 (÷9) 1001 (÷10) 1010 (÷11) 1011 (÷12) 1100 (÷13) 1101 (÷14) 1110 (÷15) 1111 (÷16) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 93 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. 7 6 5 4 3 2 1 0 R W Reset1 WCOP RSBCK 0 0 WRTMASK 0 0 0 0 0 CR2 CR1 CR0 1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0. = Unimplemented or Reserved Figure 2-12. CRG COP Control Register (COPCTL) Read: Anytime Write: 1. RSBCK: Anytime in special modes; write to “1” but not to “0” in all other modes 2. WCOP, CR2, CR1, CR0: — Anytime in special modes — Write once in all other modes Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. Writing WCOP to “0” has no effect, but counts for the “write once” condition. The COP time-out period is restarted if one these two conditions is true: 1. Writing a nonzero value to CR[2:0] (anytime in special modes, once in all other modes) with WRTMASK = 0. or 2. Changing RSBCK bit from “0” to “1”. Table 2-9. COPCTL Field Descriptions Field 7 WCOP Description Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x_55 can be written as often as desired. Once 0x_AA is written after the 0x_55, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP. Table 2-10 shows the duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode. 6 RSBCK MC9S12XDP512 Data Sheet, Rev. 2.17 94 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-9. COPCTL Field Descriptions (continued) Field 5 WRTMASK Description Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR[2:0]. 0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL 1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.) COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 2-10). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register. While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in emulation or special modes 2–0 CR[1:0] Table 2-10. COP Watchdog Rates1 CR2 0 0 0 0 1 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 OSCCLK Cycles to Time-out COP disabled 214 216 218 220 222 223 224 OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x_55/0x_AA to the ARMCOP register) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 95 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-13. Reserved Register (FORBYP) Read: Always read 0x_00 except in special modes Write: Only in special modes 2.3.2.11 Reserved Register (CTCTL) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG’s functionality. 7 6 5 4 3 2 1 0 R W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 2-14. Reserved Register (CTCTL) Read: always read 0x_80 except in special modes Write: only in special modes MC9S12XDP512 Data Sheet, Rev. 2.17 96 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. 7 6 5 4 3 2 1 0 R W Reset 0 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0 Bit 0 0 Figure 2-15. ARMCOP Register Diagram Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 97 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4 2.4.1 2.4.1.1 Functional Description Functional Blocks Phase Locked Loop (PLL) The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register. [ SYNR + 1 ] PLLCLK = 2 × OSCCLK × ----------------------------------[ REFDV + 1 ] CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually. The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency fSCM. REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV FEEDBACK LOCK DETECTOR LOCK REFERENCE PROGRAMMABLE DIVIDER VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO CRYSTAL MONITOR LOOP PROGRAMMABLE DIVIDER SYN VDDPLL LOOP FILTER XFC PIN PLLCLK supplied by: VDDPLL/VSSPLL VDD/VSS Figure 2-16. PLL Functional Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 98 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.1.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 2-16. The phase detector then compares the FEEDBACK clock, with the REFERENCE clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL. The minimum VCO frequency is reached with the XFC pin forced to VDDPLL. This is the self clock mode frequency. 2.4.1.1.2 Acquisition and Tracking Modes The lock detector compares the frequencies of the FEEDBACK clock, and the REFERENCE clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. The PLL filter can be manually or automatically configured into one of two possible operating modes: • Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. • Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 99 Chapter 2 Clocks and Reset Generator (S12CRGV6) The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): • The TRACK bit is a read-only indicator of the mode of the filter. • The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt. • The LOCK bit is a read-only indicator of the locked state of the PLL. • The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared when the VCO frequency is out of a certain tolerance, ∆unl. • Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. • After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before entering tracking mode (ACQ = 0). • After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1). 2.4.1.2 System Clocks Generator PLLSEL or SCM PHASE LOCK LOOP PLLCLK 1 0 STOP SYSCLK CORE CLOCK SCM ÷2 EXTAL OSCILLATOR OSCCLK 1 0 WAIT(RTIWAI), STOP(PSTP,PRE), RTI ENABLE CLOCK PHASE GENERATOR BUS CLOCK RTI XTAL WAIT(COPWAI), STOP(PSTP,PCE), COP ENABLE COP CLOCK MONITOR GATING CONDITION = CLOCK GATE STOP OSCILLATOR CLOCK Figure 2-17. System Clocks Generator MC9S12XDP512 Data Sheet, Rev. 2.17 100 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) The clock generator creates the clocks used in the MCU (see Figure 2-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self clock mode (see Section 2.4.2.2, “Self Clock Mode”) oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 2-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL registerr. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases. CORE CLOCK BUS CLOCK / ECLK Figure 2-18. Core Clock and Bus Clock Relationship 2.4.1.3 Clock Monitor (CM) If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRG then asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit. 2.4.1.4 Clock Quality Checker The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events: • Power on reset (POR) • Low voltage reset (LVR) • Wake-up from full stop mode (exit full stop) • Clock monitor fail indication (CM fail) A time window of 50,000 VCO clock cycles1 is called check window. 1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 101 Chapter 2 Clocks and Reset Generator (S12CRGV6) A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 2-19 as an example. check window 1 VCO Clock 1 OSCCLK 4095 osc ok 2 3 4 5 4096 2 3 49999 50000 Figure 2-19. Check Window Example The sequence for clock quality check is shown in Figure 2-20. Clock OK CM fail exit full stop POR LVR SCME = 1 & FSTWKP = 1 ? no Clock Monitor Reset yes num = 0 Enter SCM no FSTWKP = 0 ? yes num = 50 Enter SCM yes no SCM active? num = 0 check window num=num–1 yes yes no SCME=1 ? no osc ok ? yes SCM active? no no num > 0 ? yes Switch to OSCCLK Exit SCM Figure 2-20. Sequence for Clock Quality Check MC9S12XDP512 Data Sheet, Rev. 2.17 102 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) NOTE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo stop mode or wait mode. 2.4.1.5 Computer Operating Properly Watchdog (COP) The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 2.4.1.5, “Computer Operating Properly Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register allow selection of seven COP time-out periods. When COP is enabled, the program must write 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than 0x_55 or 0x_AA is written, the part is immediately reset. Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. If PCE bit is set, the COP will continue to run in pseudo stop mode. 2.4.1.6 Real Time Interrupt (RTI) The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE = 1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK. At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. If the PRE bit is set, the RTI will continue to run in pseudo stop mode. 2.4.2 2.4.2.1 Operating Modes Normal Mode The CRG block behaves as described within this specification in all normal modes. 1. A Clock Monitor Reset will always set the SCME bit to logical 1. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 103 Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.2.2 Self Clock Mode The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO running at minimum operating frequency; this mode of operation is called self clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. Section 2.4.1.4, “Clock Quality Checker” for more information on entering and leaving self clock mode. NOTE In order to detect a potential clock loss the CME bit should be always enabled (CME = 1)! If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO’s minimum frequency fSCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency. If the MCU is running on external clock any loss of clock will cause the system to go static. 2.4.3 Low Power Options This section summarizes the low power options available in the CRG. 2.4.3.1 Run Mode The RTI can be stopped by setting the associated rate select bits to 0. The COP can be stopped by setting the associated rate select bits to 0. 2.4.3.2 Wait Mode The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed. This provides enhanced granularity in reducing the level of power consumption during wait mode. Table 2-11 lists the individual configuration bits and the parts of the MCU that are affected in wait mode . Table 2-11. MCU Configuration During Wait Mode PLLWAI PLL RTI COP Stopped — — RTIWAI — Stopped — COPWAI — — Stopped After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG then checks whether the PLLWAI bit is asserted (Figure 2-21). Depending on the configuration, the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the PLL. As soon as all clocks are switched off wait mode is active. MC9S12XDP512 Data Sheet, Rev. 2.17 104 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) CPU Req’s Wait Mode. PLLWAI=1 ? Yes No Clear PLLSEL, Disable PLL No Enter Wait Mode Wait Mode left due to external reset CME=1 ? Yes No INT ? Yes Exit Wait w. ext.RESET CM Fail ? Yes No Exit Wait w. CMRESET No SCME=1 ? Yes Exit Wait Mode SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait) Yes Exit Wait Mode No SCM=1 ? Yes No Enter SCM Enter SCM Continue w. Normal OP Figure 2-21. Wait Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 105 Chapter 2 Clocks and Reset Generator (S12CRGV6) There are four different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Any interrupt If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. Wait mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 2.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation.If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake-up from wait-mode. If any other interrupt source (e.g., RTI) triggers exit from wait mode, the MCU immediately continues with normal operation. If the PLL has been powered-down during wait mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. If wait mode is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 2-12 summarizes the outcome of a clock loss while in wait mode. 2.4.3.3 System Stop Mode All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE, and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g., voltage-regulator) to enter their individual power saving modes (if available). This is the main difference between pseudo stop mode and wait mode. If the PLLSEL bit is still set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo stop mode (PSTP = 1) is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode, an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is left again. Wake-up from stop mode also depends on the setting of the PSTP bit. MC9S12XDP512 Data Sheet, Rev. 2.17 106 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-12. Outcome of Clock Loss in Wait Mode CME 0 1 SCME X 0 SCMIE X X Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock failure --> Scenario 1: OSCCLK recovers prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled depending on PLLWAI, – VREG remains enabled (never gets disabled in wait mode). – MCU remains in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit wait mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in wait mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLKis o.k.again. Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit wait mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. CRG Actions 1 1 0 1 1 1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 107 Chapter 2 Clocks and Reset Generator (S12CRGV6) Core req’s Stop Mode. Clear PLLSEL, Disable PLL Stop Mode left due to external reset Exit Stop w. ext.RESET Enter Stop Mode No INT ? Yes No PSTP=1 ? Yes CME=1 ? Yes No No INT ? Yes SCME=1 & FSTWKP=1 ? No Yes CM fail ? Yes No No Clock OK ? Yes Exit Stop Mode Exit Stop w. CMRESET no SCME=1 ? Yes Exit Stop Mode Exit Stop w. CMRESET No SCME=1 ? Yes SCMIE=1 ? Yes Exit Stop Mode No Exit Stop Mode Exit Stop Mode Generate SCM Interrupt (Wakeup from Stop) No SCM=1 ? Yes Enter SCM Enter SCM SCMIF not set! Enter SCM Enter SCM Continue w. normal OP Figure 2-22. Stop Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev. 2.17 108 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.3.3.1 Wake-up from Pseudo Stop Mode (PSTP=1) Wake-up from pseudo stop mode is the same as wake-up from wait mode. There are also four different scenarios for the CRG to restart the MCU from pseudo stop mode: • External reset • Clock monitor fail • COP reset • Wake-up interrupt If the MCU gets an external reset or COP reset during pseudo stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector. pseudo stop mode is left and the MCU is in run mode again. If the clock monitor is enabled (CME = 1), the MCU is able to leave pseudo stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG’s behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE = 1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (Section 2.4.1.4, “Clock Quality Checker”). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE=0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo stop mode. If any other interrupt source (e.g., RTI) triggers exit from pseudo stop mode, the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode, the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 2-13 summarizes the outcome of a clock loss while in pseudo stop mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 109 Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-13. Outcome of Clock Loss in Pseudo Stop Mode CME 0 1 SCME X 0 SCMIE X X Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers. – CM no longer indicates a failure, – 4096 OSCCLK cycles later clock quality check indicates clock o.k., – SCM deactivated, – PLL disabled, – VREG disabled. – MCU remains in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode using OSCCLK as system clock (SYSCLK), – Continue normal operation. or an External Reset is applied. – Exit pseudo stop mode using OSCCLK as system clock, – Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag, – Keep performing clock quality checks (could continue infinitely) while in pseudo stop mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock – Continue to perform additional clock quality checks until OSCCLK is o.k. again. or an External RESET is applied. – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock – Start reset sequence, – Continue to perform additional clock quality checks until OSCCLK is o.k.again. Clock failure --> – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit pseudo stop mode in SCM using PLL clock (fSCM) as system clock, – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. CRG Actions 1 1 0 1 1 1 MC9S12XDP512 Data Sheet, Rev. 2.17 110 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.3.3.2 Wake-up from Full Stop (PSTP = 0) The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 2.4.1.4, “Clock Quality Checker”). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop-mode is left and the MCU is in run mode again. If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see Section 2.4.1.4, “Clock Quality Checker”). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will immediately resume operation in self-clock mode (see Section 2.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to oscillator clock. The SCMIF flag will be set. See application examples in Figure 2-23 and Figure 2-24. Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 111 Chapter 2 Clocks and Reset Generator (S12CRGV6) CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service STOP Interrupt IRQ Service STOP Interrupt IRQ Service Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 2-23. Fast Wake-up from Full Stop Mode: Example 1 . CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service FSTWKP=0 IRQ Interrupt SCMIE=1 Freq. Uncritical Instructions Freq. Critical Instr. Possible SCM Interrupt Clock Quality Check Oscillator Disabled OSC Startup Oscillator Clock PLL Clock Self-Clock Mode Core Clock Figure 2-24. Fast Wake-up from Full Stop Mode: Example 2 MC9S12XDP512 Data Sheet, Rev. 2.17 112 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.5 Resets This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 2.3, “Memory Map and Register Definition”. All reset sources are listed in Table 2-14. Refer to MCU specification for related vector addresses and priorities. Table 2-14. Reset Summary Reset Source Power on Reset Low Voltage Reset External Reset Illegal Address Reset Clock Monitor Reset COP Watchdog Reset Local Enable None None None None PLLCTL (CME = 1, SCME = 0) COPCTL (CR[2:0] nonzero) 2.5.1 Description of Reset Operation The reset sequence is initiated by any of the following events: • Low level is detected at the RESET pin (external reset) • Power on is detected • Low voltage is detected • Illegal Address Reset is detected (see S12XMMC Block Guide for details) • COP watchdog times out • Clock monitor failure is detected and self-clock mode was disabled (SCME=0) Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 2-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128 + n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 2-15 shows which vector will be fetched. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 113 Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-15. Reset Vector Selection Sampled RESET Pin (64 cycles after release) 1 1 1 0 Clock Monitor Reset Pending 0 1 0 X COP Reset Pending 0 X 1 X Vector Fetch POR / LVR / Illegal Address Reset / External Reset Clock Monitor Reset COP Reset POR / LVR / Illegal Address Reset / External Reset with rise of RESET pin NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too. RESET )( )( RESET pin released CRG drives RESET pin low SYSCLK ) ( 128 + n cycles Possibly SYSCLK not running With n being min 3 / max 6 cycles depending on internal synchronization delay ) ( 64 cycles ) ( Possibly RESET driven low externally Figure 2-25. RESET Timing MC9S12XDP512 Data Sheet, Rev. 2.17 114 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.5.2 Clock Monitor Reset The CRG generates a clock monitor reset in case all of the following conditions are true: • Clock monitor is enabled (CME = 1) • Loss of clock is detected • Self-clock mode is disabled (SCME = 0). The reset event asynchronously forces the configuration registers to their default settings (see Section 2.3, “Memory Map and Register Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG immediately enters self clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self clock mode. Since the clock quality checker is running in parallel to the reset generator, the CRG may leave self clock mode while still completing the internal reset sequence. When the reset sequence is finished, the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated, processing begins by fetching the clock monitor reset vector. 2.5.3 Computer Operating Properly Watchdog (COP) Reset When COP is enabled, the CRG expects sequential write of 0x_55 and 0x_AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x_55 or 0x_AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled writes (0x_55 or 0x_AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector. 2.5.4 Power On Reset, Low Voltage Reset The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal, the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode. Figure 2-26 and Figure 2-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 115 Chapter 2 Clocks and Reset Generator (S12CRGV6) RESET Clock Quality Check (no Self-Clock Mode) )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 2-26. RESET Pin Tied to VDD (by a pull-up resistor) RESET Clock Quality Check (no Self Clock Mode) )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 2-27. RESET Pin Held Low Externally 2.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 2-16. Refer to MCU specification for related vector addresses and priorities. Table 2-16. CRG Interrupt Vectors Interrupt Source Real time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE) 2.6.1 Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real time interrupt flag (RTIF) is set to1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo stop if the RTI interrupt is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 116 Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.6.2 PLL Lock Interrupt The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. 2.6.3 Self Clock Mode Interrupt The CRG generates a self clock mode interrupt when the SCM condition of the system has changed, either entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 2.4.1.4, “Clock Quality Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 117 Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.17 118 Freescale Semiconductor Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.1 Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (2.5 V nominal) and require the minimum number of external components. It is designed for optimal start-up margin with typical crystal oscillators. 3.1.1 Features The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity. • High noise immunity due to input hysteresis • Low RF emissions with peak-to-peak swing limited dynamically • Transconductance (gm) sized for optimum start-up margin for typical oscillators • Dynamic gain control eliminates the need for external current limiting resistor • Integrated resistor eliminates the need for external bias resistor • Low power consumption: — Operates from 2.5 V (nominal) supply — Amplitude control limits power • Clock monitor 3.1.2 Modes of Operation Two modes of operation exist: 1. Loop controlled Pierce oscillator 2. External square wave mode featuring also full swing Pierce without internal feedback resistor MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 119 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.1.3 Block Diagram Figure 3-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Detector Gain Control VDDPLL = 2.5 V Rf EXTAL XTAL Figure 3-1. XOSC Block Diagram 3.2 External Signal Description This section lists and describes the signals that connect off chip 3.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This allows the supply voltage to the XOSC to be independently bypassed. 3.2.2 EXTAL and XTAL — Input and Output Pins These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the MC9S12XDP512 Data Sheet, Rev. 2.17 120 Freescale Semiconductor Chapter 3 Pierce Oscillator (S12XOSCLCPV1) EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. EXTAL C1 MCU XTAL C2 VSSPLL Crystal or Ceramic Resonator Figure 3-2. Loop Controlled Pierce Oscillator Connections (XCLKS = 1) NOTE Full swing Pierce circuit is not suited for overtone resonators and crystals without a careful component selection. EXTAL C1 MCU RS* XTAL C2 VSSPLL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. RB Crystal or Ceramic Resonator Figure 3-3. Full Swing Pierce Oscillator Connections (XCLKS = 0) EXTAL MCU XTAL CMOS Compatible External Oscillator (VDDPLL Level) Not Connected Figure 3-4. External Clock Connections (XCLKS = 0) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 121 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.2.3 XCLKS — Input Signal The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS pin. Table 3-1 lists the state coding of the sampled XCLKS signal. . Table 3-1. Clock Selection Based on XCLKS XCLKS 1 0 Description Loop controlled Pierce oscillator selected Full swing Pierce oscillator/external clock selected 3.3 Memory Map and Register Definition The CRG contains the registers and associated bits for controlling and monitoring the oscillator module. 3.4 Functional Description The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins. 3.4.1 Gain Control A closed loop control system will be utilized whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are provided in the Electrical Characteristics appendix. 3.4.2 Clock Monitor The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter. MC9S12XDP512 Data Sheet, Rev. 2.17 122 Freescale Semiconductor Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.4.3 Wait Mode Operation During wait mode, XOSC is not impacted. 3.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 123 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev. 2.17 124 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.1 Introduction The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy. 4.1.1 • • • • • • • • • • • • • Features 8-/10-bit resolution 7 µs, 10-bit single conversion time Sample buffer amplifier Programmable sample time Left/right justified, signed/unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for 16 analog input channels Analog/digital input pin multiplexing 1 to 16 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity Configurable location for channel wrap around (when converting multiple channels in a sequence) • 4.1.2 Modes of Operation There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 4.1.3 Block Diagram Refer to Figure 4-1 for a block diagram of the ATD0B16C block. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 125 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Bus Clock Clock Prescaler Trigger Mux ATD clock ATD10B16C ETRIG0 ETRIG1 ETRIG2 ETRIG3 (see Device Overview chapter for availability and connectivity) ATDCTL1 Mode and Timing Control Sequence Complete Interrupt ATDDIEN VDDA VSSA VRH VRL AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 Analog MUX PORTAD Successive Approximation Register (SAR) and DAC Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 + Sample & Hold 1 1 Comparator AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Figure 4-1. ATD10B16C Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 126 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.2 External Signal Description This section lists all inputs to the ATD10B16C block. 4.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion. 4.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the Device Overview chapter for availability and connectivity of these inputs. 4.2.3 VRH, VRL — High Reference Voltage Pin, Low Reference Voltage Pin VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion. 4.2.4 VDDA, VSSA — Analog Circuitry Power Supply Pins These pins are the power supplies for the analog circuitry of the ATD10B16CV4 block. 4.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ATD10B16C. 4.3.1 Module Memory Map Table 4-1 gives an overview of all ATD10B16C registers MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 127 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description . Table 4-1. ATD10B16CV4 Memory Map Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010, 0x0011 0x0012, 0x0013 0x0014, 0x0015 0x0016, 0x0017 0x0018, 0x0019 0x001A, 0x001B 0x001C, 0x001D 0x001E, 0x001F 0x0020, 0x0021 0x0022, 0x0023 0x0024, 0x0025 0x0026, 0x0027 0x0028, 0x0029 0x002A, 0x002B 0x002C, 0x002D 0x002E, 0x002F 1 Use ATD Control Register 0 (ATDCTL0) ATD Control Register 1 (ATDCTL1) ATD Control Register 2 (ATDCTL2) ATD Control Register 3 (ATDCTL3) ATD Control Register 4 (ATDCTL4) ATD Control Register 5 (ATDCTL5) ATD Status Register 0 (ATDSTAT0) Unimplemented ATD Test Register 0 (ATDTEST0)1 ATD Test Register 1 (ATDTEST1) ATD Status Register 2 (ATDSTAT2) ATD Status Register 1 (ATDSTAT1) ATD Input Enable Register 0 (ATDDIEN0) ATD Input Enable Register 1 (ATDDIEN1) Port Data Register 0 (PORTAD0) Port Data Register 1 (PORTAD1) ATD Result Register 0 (ATDDR0H, ATDDR0L) ATD Result Register 1 (ATDDR1H, ATDDR1L) ATD Result Register 2 (ATDDR2H, ATDDR2L) ATD Result Register 3 (ATDDR3H, ATDDR3L) ATD Result Register 4 (ATDDR4H, ATDDR4L) ATD Result Register 5 (ATDDR5H, ATDDR5L) ATD Result Register 6 (ATDDR6H, ATDDR6L) ATD Result Register 7 (ATDDR7H, ATDDR7L) ATD Result Register 8 (ATDDR8H, ATDDR8L) ATD Result Register 9 (ATDDR9H, ATDDR9L) ATD Result Register 10 (ATDDR10H, ATDDR10L) ATD Result Register 11 (ATDDR11H, ATDDR11L) ATD Result Register 12 (ATDDR12H, ATDDR12L) ATD Result Register 13 (ATDDR13H, ATDDR13L) ATD Result Register 14 (ATDDR14H, ATDDR14L) ATD Result Register 15 (ATDDR15H, ATDDR15L) Access R/W R/W R/W R/W R/W R/W R/W R R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ATDTEST0 is intended for factory test purposes only. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. MC9S12XDP512 Data Sheet, Rev. 2.17 128 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits. Register Name 0x0000 ATDCTL0 R W R W R W R W R W R W R W R W R W R W R W R W R W IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 Unimplemented SC CCF8 Unimplemented SRES8 0 0 0 Bit 7 0 6 0 5 0 4 0 3 2 1 Bit 0 WRAP3 WRAP2 WRAP1 WRAP0 0x0001 ATDCTL1 0x0002 ATDCTL2 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDTEST0 0x0009 ATDTEST1 0x000A ATDSTAT2 0x000B ATDSTAT1 0x000C ATDDIEN0 ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ASCIF ADPU 0 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 DJM DSGN 0 SCAN MULT CD CC3 CC CC2 CB CC1 CA CC0 SCF ETORF FIFOR = Unimplemented or Reserved u = Unaffected Figure 4-2. ATD Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 129 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Register Name 0x000D ATDDIEN1 0x000E PORTAD0 0x000F PORTAD1 R W R W R W Bit 7 IEN7 PTAD15 6 IEN6 PTAD14 5 IEN5 PTAD13 4 IEN4 PTAD12 3 IEN3 PTAD11 2 IEN2 PTAD10 1 IEN1 PTAD9 Bit 0 IEN0 PTAD8 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 R BIT 9 MSB BIT 7 MSB 0x0010–0x002F W ATDDRxH– ATDDRxL R W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved u = Unaffected Figure 4-2. ATD Register Summary (continued) 4.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 WRAP3 WRAP2 1 WRAP1 1 WRAP0 1 0 0 0 0 1 = Unimplemented or Reserved Figure 4-3. ATD Control Register 0 (ATDCTL0) Read: Anytime Write: Anytime Table 4-2. ATDCTL0 Field Descriptions Field 3:0 WRAP[3:0] Description Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 4-3. MC9S12XDP512 Data Sheet, Rev. 2.17 130 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-3. Multi-Channel Wrap Around Coding WRAP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WRAP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WRAP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WRAP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 4.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R ETRIGSEL W Reset 0 0 0 0 ETRIGCH3 ETRIGCH2 1 ETRIGCH1 1 ETRIGCH0 1 0 0 0 1 = Unimplemented or Reserved Figure 4-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 4-4. ATDCTL1 Field Descriptions Field 7 ETRIGSEL Description External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG[3:0] inputs. See device specification for availability and connectivity of ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external trigger. The coding is summarized in Table 4-5. 3:0 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG[3:0] inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 4-5. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 131 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-5. External Trigger Channel Select Coding ETRIGSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 ETRIGCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 ETRIGCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 X ETRIGCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X ETRIGCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X External Trigger Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG01 ETRIG11 ETRIG21 ETRIG31 Reserved Reserved Only if ETRIG[3:0] input option is available (see device specification), else ETRISEL is ignored, that means external trigger source remains on one of the AD channels selected by ETRIGCH[3:0] 4.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. MC9S12XDP512 Data Sheet, Rev. 2.17 132 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 7 6 5 4 3 2 1 0 R ADPU W Reset 0 0 0 0 0 0 0 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF 0 = Unimplemented or Reserved Figure 4-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 4-6. ATDCTL2 Field Descriptions Field 7 ADPU Description ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during Wait mode After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 4-7 for details. External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 4-7 for details. External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the ETRIG[3:0] inputs as described in Table 4-5. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. 0 Disable external trigger 1 Enable external trigger ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 4.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending 6 AFFC 5 AWAI 4 ETRIGLE 3 ETRIGP 2 ETRIGE 1 ASCIE 0 ASCIF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 133 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-7. External Trigger Configurations ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling Edge Ring Edge Low Level High Level MC9S12XDP512 Data Sheet, Rev. 2.17 134 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset 0 S8C 0 0 S4C 1 S2C 0 S1C 0 FIFO 0 FRZ1 0 FRZ0 0 = Unimplemented or Reserved Figure 4-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 4-8. ATDCTL3 Field Descriptions Field 6 S8C 5 S4C 4 S2C 3 S1C Description Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 4-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 135 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-8. ATDCTL3 Field Descriptions (continued) Field 2 FIFO Description Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 4-10. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. 1:0 FRZ[1:0] Table 4-9. Conversion Sequence Length Coding S8C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S4C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1C 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Number of Conversions per Sequence 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MC9S12XDP512 Data Sheet, Rev. 2.17 136 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 137 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R SRES8 W Reset 0 0 0 0 0 1 0 1 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Figure 4-7. ATD Control Register 4 (ATDCTL4) Read: Anytime Write: Anytime Table 4-11. ATDCTL4 Field Descriptions Field 7 SRES8 Description A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution Sample Time Select —These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 4-12 lists the lengths available for the second sample phase. ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDclock = ------------------------------- × 0.5 [ PRS + 1 ] Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 4-13 illustrates the divide-by operation and the appropriate range of the bus clock. 6:5 SMP[1:0] 4:0 PRS[4:0] Table 4-12. Sample Time Select SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods MC9S12XDP512 Data Sheet, Rev. 2.17 138 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-13. Clock Prescaler Values Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 Total Divisor Value Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64 Max. Bus Clock1 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz Min. Bus Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 139 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase. 7 6 5 4 3 2 1 0 R DJM W Reset 0 0 0 0 0 0 0 0 DSGN SCAN MULT CD CC CB CA Figure 4-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime Table 4-14. ATDCTL5 Field Descriptions Field 7 DJM Description Result Register Data Justification — This bit controls justification of conversion data in the result registers. See Section 4.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details. 0 Left justified data in the result registers. 1 Right justified data in the result registers. Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed data is not available in right justification. See 4.3.2.16 ATD Conversion Result Registers (ATDDRx) for details. 0 Unsigned data representation in the result registers. 1 Signed data representation in the result registers. Table 4-15 summarizes the result data formats available and how they are set up using the control bits. Table 4-16 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means each trigger event starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0. 0 Sample only one channel 1 Sample across several channels 6 DSGN 5 SCAN 4 MULT MC9S12XDP512 Data Sheet, Rev. 2.17 140 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-14. ATDCTL5 Field Descriptions (continued) Field 3:0 C[D:A} Description Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 4-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined. In the case of multiple channel conversions (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one defined by WRAP[3:0] the first wrap around will be AN15 to AN0. Table 4-15. Available Result Data Formats. SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned — bits 15:8 8-bit / left justified / signed — bits 15:8 8-bit / right justified / unsigned — bits 7:0 10-bit / left justified / unsigned — bits 15:6 10-bit / left justified / signed -— bits 15:6 10-bit / right justified / unsigned — bits 9:0 Table 4-16. Left Justified, Signed and Unsigned ATD Output Codes. Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 141 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-17. Analog Input Channel Select Coding CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 MC9S12XDP512 Data Sheet, Rev. 2.17 142 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. 7 6 5 4 3 2 1 0 R SCF W Reset 0 0 ETORF 0 0 FIFOR 0 CC3 CC2 CC1 CC0 0 0 0 0 = Unimplemented or Reserved Figure 4-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on CC[3:0]) Table 4-18. ATDSTAT0 Field Descriptions Field 7 SCF Description Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: • Write “1” to SCF • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag —While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: • Write “1” to ETORF • Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted) • Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred 5 ETORF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 143 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-18. ATDSTAT0 Field Descriptions (continued) Field 4 FIFOR Description FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag is cleared when one of the following occurs: • Write “1” to FIFOR • Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag remained set) Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0, CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. 3:0 CC[3:0} MC9S12XDP512 Data Sheet, Rev. 2.17 144 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.8 Reserved Register 0 (ATDTEST0) 7 6 5 4 3 2 1 0 R W Reset u u u u u u u u 1 0 0 0 0 0 0 0 = Unimplemented or Reserved u = Unaffected Figure 4-10. Reserved Register 0 (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 4.3.2.9 ATD Test Register 1 (ATDTEST1) This register contains the SC bit used to enable special channel conversions. 7 6 5 4 3 2 1 0 R W Reset u u u u u u u SC 0 0 0 0 0 0 0 0 = Unimplemented or Reserved u = Unaffected Figure 4-11. Reserved Register 1 (ATDTEST1) Read: Anytime, returns unpredictable values for bit 7 and bit 6 Write: Anytime NOTE Writing to this register when in special modes can alter functionality. Table 4-19. ATDTEST1 Field Descriptions Field 0 SC Description Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5. Table 4-20 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 145 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-20. Special Channel Select Coding SC 1 1 1 1 1 1 CD 0 0 0 0 0 1 CC 0 1 1 1 1 X CB X 0 0 1 1 X CA X 0 1 0 1 X Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved Reserved 4.3.2.10 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8. 7 6 5 4 3 2 1 0 R W Reset CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-12. ATD Status Register 2 (ATDSTAT2) Read: Anytime Write: Anytime, no effect Table 4-21. ATDSTAT2 Field Descriptions Field 7:0 CCF[15:8] Description Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs: • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx • If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx MC9S12XDP512 Data Sheet, Rev. 2.17 146 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 7 6 5 4 3 2 1 0 R W Reset CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-13. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 4-22. ATDSTAT1 Field Descriptions Field 7:0 CCF[7:0] Description Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A CCF flag is cleared when one of the following occurs: • Write to ATDCTL5 (a new conversion sequence is started) • If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx • If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 147 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) 7 6 5 4 3 2 1 0 R IEN15 W Reset 0 0 0 0 0 0 0 0 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 Figure 4-14. ATD Input Enable Register 0 (ATDDIEN0) Read: Anytime Write: anytime Table 4-23. ATDDIEN0 Field Descriptions Field 7:0 IEN[15:8] Description ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 4.3.2.13 ATD Input Enable Register 1 (ATDDIEN1) 7 6 5 4 3 2 1 0 R IEN7 W Reset 0 0 0 0 0 0 0 0 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Figure 4-15. ATD Input Enable Register 1 (ATDDIEN1) Read: Anytime Write: Anytime Table 4-24. ATDDIEN1 Field Descriptions Field 7:0 IEN[7:0] Description ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. MC9S12XDP512 Data Sheet, Rev. 2.17 148 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.14 Port Data Register 0 (PORTAD0) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. 7 6 5 4 3 2 1 0 R W Reset Pin Function PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 1 AN15 1 AN14 1 AN13 1 AN12 1 AN11 1 AN10 1 AN9 1 AN8 = Unimplemented or Reserved Figure 4-16. Port Data Register 0 (PORTAD0) Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input. Table 4-25. PORTAD0 Field Descriptions Field 7:0 PTAD[15:8] Description A/D Channel x (ANx) Digital Input Bits— If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD0 bits to “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 149 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.15 Port Data Register 1 (PORTAD1) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. 7 6 5 4 3 2 1 0 R W Reset Pin Function PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 AN 7 1 AN6 1 AN5 1 AN4 1 AN3 1 AN2 1 AN1 1 AN0 = Unimplemented or Reserved Figure 4-17. Port Data Register 1 (PORTAD1) Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input. Table 4-26. PORTAD1 Field Descriptions Field 7:0 PTAD[7:8] Description A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD1 bits to “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 150 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 4.3.2.16.1 Left Justified Result Data 7 6 5 4 3 2 1 0 R (10-BIT) BIT 9 MSB R (8-BIT) BIT 7 MSB W Reset 0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH) 7 6 5 4 3 2 1 0 R (10-BIT) R (8-BIT) W Reset BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u = Unaffected 0 0 = Unimplemented or Reserved Figure 4-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 151 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.16.2 Right Justified Result Data 7 6 5 4 3 2 1 0 R (10-BIT) R (8-BIT) W Reset 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH) 7 6 5 4 3 2 1 0 R (10-BIT) BIT 7 R (8-BIT) BIT 7 MSB W Reset 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 4-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL) 4.4 Functional Description The ATD10B16C is structured in an analog and a digital sub-block. 4.4.1 Analog Sub-block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 4.4.1.1 Sample and Hold Machine The sample and hold (S/H) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. MC9S12XDP512 Data Sheet, Rev. 2.17 152 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 4.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 4.4.1.4 Analog-to-Digital (A/D) Machine The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics continue drawing quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes. 4.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See register descriptions for all details. 4.4.2.1 External Trigger Input The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 4-27 gives a brief description of the different combinations of control bits and their effect on the external trigger function. Table 4-27. External Trigger Control Bits ETRIGLE X X 0 0 1 1 ETRIGP X X 0 1 0 1 ETRIGE 0 0 1 1 1 1 SCAN 0 1 X X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active. During a conversion, if additional active edges are detected the overrun error flag ETORF is set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 153 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger remains asserted in level mode while a sequence is completing, another sequence will be triggered immediately. 4.4.2.2 General-Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input. 4.4.3 Operation in Low Power Modes The ATD10B16C can be configured for lower MCU power consumption in three different ways: • Stop Mode Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due to the recovery time the result of this conversion should be ignored. Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This halts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence. • Wait Mode Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AWAIT bit. • Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. NOTE The reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state. MC9S12XDP512 Data Sheet, Rev. 2.17 154 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.5 Resets At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 4.3, “Memory Map and Register Definition,” which details the registers and their bit fields. 4.6 Interrupts The interrupt requested by the ATD10B16C is listed in Table 4-28. Refer to MCU specification for related vector address and priority. Table 4-28. ATD Interrupt Vectors Interrupt Source Sequence Complete Interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2 See Section 4.3.2, “Register Descriptions,” for further details. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 155 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 156 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 157 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 158 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.1 Introduction The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 5.1.1 • • • • • • • • • • • • • Features 8/10-bit resolution 7 µsec, 10-bit single conversion time Sample buffer amplifier Programmable sample time Left/right justified, signed/unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for 8 analog input channels Analog/digital input pin multiplexing 1-to-8 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional external trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to the device overview chapter for availability and connectivity. Configurable location for channel wrap around (when converting multiple channels in a sequence). • 5.1.2 5.1.2.1 Modes of Operation Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 159 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.1.2.2 • MCU Operating Modes • • Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence. Wait mode Entering wait mode the ATD conversion either continues or aborts for low power depending on the logical value of the AWAIT bit. Freeze mode In freeze mode the ATD will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. 5.1.3 Block Diagram Figure 5-1 shows a block diagram of the ATD. 5.2 External Signal Description This section lists all inputs to the ATD block. 5.2.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Pin This pin serves as the analog input channel x. It can also be configured as general purpose digital port pin and/or external trigger for the ATD conversion. 5.2.2 ETRIG3, ETRIG2, ETRIG1, and ETRIG0 — External Trigger Pins These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the device overview chapter for availability and connectivity of these inputs. 5.2.3 VRH and VRL — High and Low Reference Voltage Pins VRH is the high reference voltage and VRL is the low reference voltage for ATD conversion. 5.2.4 VDDA and VSSA — Power Supply Pins These pins are the power supplies for the analog circuitry of the ATD block. MC9S12XDP512 Data Sheet, Rev. 2.17 160 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Bus Clock Clock Prescaler Trigger Mux ATD clock ATD10B8C ETRIG0 ETRIG1 ETRIG2 ETRIG3 (See Device Overview chapter for availability and connectivity) Mode and Timing Control Sequence Complete Interrupt ATDCTL1 ATDDIEN PORTAD VDDA VSSA VRH VRL Successive Approximation Register (SAR) and DAC Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 AN7 AN6 AN5 AN4 AN3 Analog AN2 AN1 AN0 MUX 1 1 Sample & Hold – Comparator + Figure 5-1. ATD Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 161 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ATD. 5.3.1 Module Memory Map NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Figure 5-2 gives an overview of all ATD registers. 5.3.2 Register Descriptions This section describes in address order all the ATD registers and their individual bits. Register Name ATDCTL0 R W Bit 7 0 6 0 5 0 4 0 3 0 2 WRAP2 1 WRAP1 Bit 0 WRAP0 ATDCTL1 R ETRIGSEL W R W R W R W R W R W R W R W R W U ADPU 0 0 0 0 0 ETRIGCH2 ETRIGCH1 ETRIGCH0 ASCIF ATDCTL2 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ATDCTL3 S8C S4C S2C S1C FIFO FRZ1 FRZ0 ATDCTL4 SRES8 SMP1 SMP0 PRS4 PRS3 0 PRS2 PRS1 PRS0 ATDCTL5 DJM DSGN 0 SCAN MULT CC CC2 CB CC1 CA CC0 ATDSTAT0 SCF ETORF FIFOR 0 Unimplemente d ATDTEST0 U U U U U U U ATDTEST1 U U 0 0 0 0 0 SC = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 1 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 162 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Register Name Unimplemente d ATDSTAT1 R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Unimplemente d ATDDIEN IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Unimplemente d PORTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 Left Justified Result Data Note: The read portion of the left justified result data registers has been divided to show the bit position when reading 10-bit and 8-bit conversion data. For more detailed information refer to Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx)”. ATDDR0H 10-BIT BIT 9 MSB BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8-BIT BIT 7 MSB W ATDDR0L 10-BIT 8-BIT W BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDDR1H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDDR1L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDDR2H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDDR2L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDDR3H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 2 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 163 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Register Name ATDDR3L 10-BIT 8-BIT W Bit 7 BIT 1 U 6 BIT 0 U 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 ATDDR4H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDDR4L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDD45H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDD45L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDD46H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDDR6L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDD47H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W 10-BIT 8-BIT W BIT 1 U BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDD47L BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 Right Justified Result Data Note: The read portion of the right justified result data registers has been divided to show the bit position when reading 10-bit and 8-bit conversion data. For more detailed information refer to Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx)”. ATDDR0H 10-BIT 0 0 0 0 0 0 BIT 9 MSB BIT 8 0 0 0 0 0 0 0 0 8-BIT W ATDDR0L 10-BIT BIT 7 8-BIT BIT 7 MSB W BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 3 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 164 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Register Name ATDDR1H 10-BIT 8-BIT W Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 BIT 9 MSB 0 Bit 0 BIT 8 0 ATDDR1L 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 ATDDR2H 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDDR2L 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 ATDDR3H 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDDR3L 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 ATDDR4H 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDDR4L 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 ATDD45H 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDD45L 10-BIT BIT 7 8-BIT BIT 7 MSB W 10-BIT 8-BIT W 0 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 ATDD46H 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDDR6L 10-BIT BIT 7 8-BIT BIT 7 MSB W BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 4 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 165 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Register Name ATDD47H 10-BIT 8-BIT W 10-BIT 8-BIT Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 BIT 9 MSB 0 Bit 0 BIT 8 0 ATDD47L BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 5 of 5) 5.3.2.1 ATD Control Register 0 (ATDCTL0) Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 WRAP2 1 WRAP1 1 WRAP0 1 = Unimplemented or Reserved Figure 5-3. ATD Control Register 0 (ATDCTL0) Read: Anytime Write: Anytime Table 5-1. ATDCTL0 Field Descriptions Field 2–0 WRAP[2:0] Description Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 5-2. Table 5-2. Multi-Channel Wrap Around Coding WRAP2 0 0 0 0 1 1 1 1 WRAP1 0 0 1 1 0 0 1 1 WRAP0 0 1 0 1 0 1 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 MC9S12XDP512 Data Sheet, Rev. 2.17 166 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset ETRIGSEL 0 0 0 0 0 0 0 0 0 ETRIGCH2 1 ETRIGCH1 1 ETRIGCH0 1 = Unimplemented or Reserved Figure 5-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 5-3. ATDCTL1 Field Descriptions Field 7 ETRIGSEL Description External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3–0 inputs. See the device overview chapter for availability and connectivity of ETRIG3–0 inputs. If ETRIG3–0 input option is not available, writing a 1 to ETRISEL only sets the bit but has not effect, that means still one of the AD channels (selected by ETRIGCH2–0) is the source for external trigger. The coding is summarized in Table 5-4. 2–0 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3–0 inputs ETRIGCH[2:0] as source for the external trigger. The coding is summarized in Table 5-4. Table 5-4. External Trigger Channel Select Coding ETRIGSEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 ETRIGCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 ETRIGCH1 0 0 1 1 0 0 1 1 0 0 1 1 X ETRIGCH0 0 1 0 1 0 1 0 1 0 1 0 1 X External trigger source is AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ETRIG01 ETRIG11 ETRIG21 ETRIG31 Reserved Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH2–0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 167 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset ADPU 0 AFFC 0 AWAI 0 ETRIGLE 0 ETRIGP 0 ETRIGE 0 ASCIE 0 ASCIF 0 = Unimplemented or Reserved Figure 5-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 5-5. ATDCTL2 Field Descriptions Field 7 ADPU Description ATD Power Up — This bit provides on/off control over the ATD block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode — When entering wait mode this bit provides on/off control over the ATD block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during wait mode After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 5-6 for details. External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 5-6 for details. External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the ETRIG3–0 inputs as described in Table 5-4. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions processes with external events. 0 Disable external trigger 1 Enable external trigger Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel have no meaning while external trigger mode is enabled. 6 AFFC 5 AWAI 4 ETRIGLE 3 ETRIGP 2 ETRIGE MC9S12XDP512 Data Sheet, Rev. 2.17 168 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Table 5-5. ATDCTL2 Field Descriptions (continued) Field 1 ASCIE 0 ASCIF Description ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 5.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending Table 5-6. External Trigger Configurations ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling edge Rising edge Low level High level 5.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in freeze mode. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset 0 0 S8C 0 S4C 0 S2C 0 S1C 0 FIFO 0 FRZ1 0 FRZ0 0 = Unimplemented or Reserved Figure 5-6. ATD Control Register 3 (ATDCTL3) Read: Anytime Write: Anytime Table 5-7. ATDCTL3 Field Descriptions Field 6–3 S8C, S4C, S2C, S1C Description Conversion Sequence Length — These bits control the number of conversions per sequence. Table 5-8 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 169 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Table 5-7. ATDCTL3 Field Descriptions (continued) Field 2 FIFO Description Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC2-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 5-9. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. 1–0 FRZ[1:0] Table 5-8. Conversion Sequence Length Coding S8C 0 0 0 0 0 0 0 0 1 S4C 0 0 0 0 1 1 1 1 X S2C 0 0 1 1 0 0 1 1 X S1C 0 1 0 1 0 1 0 1 X Number of Conversions per Sequence 8 1 2 3 4 5 6 7 8 Table 5-9. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.17 170 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 R W Reset SRES8 0 SMP1 0 SMP0 0 PRS4 0 PRS3 0 PRS2 1 PRS1 0 PRS0 1 Figure 5-7. ATD Control Register 4 (ATDCTL4) Read: Anytime Write: Anytime Table 5-10. ATDCTL4 Field Descriptions Field 7 SRES8 Description A/D Resolution Select — This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits; however, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10-bit resolution 8-bit resolution Sample Time Select — These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4–0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine’s storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 5-11 lists the lengths available for the second sample phase. ATD Clock Prescaler — These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDclock = -------------------------------- × 0.5 [ PRS + 1 ] 6–5 SMP[1:0] 4–0 PRS[4:0] Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 5-12 illustrates the divide-by operation and the appropriate range of the bus clock. Table 5-11. Sample Time Select SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 171 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Table 5-12. Clock Prescaler Values Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1 Total Divisor Value Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64 Max. Bus Clock1 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz Min. Bus Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. MC9S12XDP512 Data Sheet, Rev. 2.17 172 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. 7 6 5 4 3 2 1 0 R W Reset DJM 0 DSGN 0 SCAN 0 MULT 0 0 0 CC 0 CB 0 CA 0 = Unimplemented or Reserved Figure 5-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime Table 5-13. ATDCTL5 Field Descriptions Field 7 DJM Description Result Register Data Justification — This bit controls justification of conversion data in the result registers. See Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx),” for details. 0 Left justified data in the result registers 1 Right justified data in the result registers Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed data is not available in right justification. See Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx),” for details. 0 Unsigned data representation in the result registers 1 Signed data representation in the result registers Table 5-14 summarizes the result data formats available and how they are set up using the control bits. Table 5-15 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code. 0 Sample only one channel 1 Sample across several channels Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 5-16 lists the coding used to select the various analog input channels. In the case of single channel scans (MULT = 0), this selection code specified the channel examined. In the case of multi-channel scans (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value. 6 DSGN 5 SCAN 4 MULT 2–0 CC, CB, CA MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 173 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) Table 5-14. Available Result Data Formats SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed — bits 8–15 8-bit / right justified / unsigned — bits 0–7 10-bit / left justified / unsigned — bits 6–15 10-bit / left justified / signed — bits 6–15 10-bit / right justified / unsigned — bits 0–9 Table 5-15. Left Justified, Signed, and Unsigned ATD Output Codes Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000 Table 5-16. Analog Input Channel Select Coding CC 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 MC9S12XDP512 Data Sheet, Rev. 2.17 174 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter. 7 6 5 4 3 2 1 0 R W Reset SCF 0 0 0 ETORF 0 FIFOR 0 0 0 CC2 0 CC1 0 CC0 0 = Unimplemented or Reserved Figure 5-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC2, CC1, CC0)) Table 5-17. ATDSTAT0 Field Descriptions Field 7 SCF Description Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL2, ATDCTL3 or ATDCTL4 (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 An over run condition exists Conversion Counter — These 3 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD result register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. 5 ETORF 4 FIFOR 2–0 CC[2:0] MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 175 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.8 R W Reset Reserved Register (ATDTEST0) 7 6 5 4 3 2 1 0 U 1 U 0 U 0 U 0 U 0 U 0 U 0 U 0 = Unimplemented or Reserved Figure 5-10. Reserved Register (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 5.3.2.9 ATD Test Register 1 (ATDTEST1) This register contains the SC bit used to enable special channel conversions. 7 6 5 4 3 2 1 0 R W Reset U 0 U 0 0 0 0 0 0 0 0 0 0 0 SC 0 = Unimplemented or Reserved Figure 5-11. ATD Test Register 1 (ATDTEST1) Read: Anytime, returns unpredictable values for Bit7 and Bit6 Write: Anytime Table 5-18. ATDTEST1 Field Descriptions Field 0 SC Description Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CC, CB and CA of ATDCTL5. Table 5-19 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled Note: Always write remaining bits of ATDTEST1 (Bit7 to Bit1) zero when writing SC bit. Not doing so might result in unpredictable ATD behavior. Table 5-19. Special Channel Select Coding SC 1 1 1 1 1 CC 0 1 1 1 1 CB X 0 0 1 1 CA X 0 1 0 1 Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 176 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.10 ATD Status Register 1 (ATDSTAT1) This read-only register contains the conversion complete flags. 7 6 5 4 3 2 1 0 R W Reset CCF7 0 CCF6 0 CCF5 0 CCF4 0 CCF3 0 CCF2 0 CCF1 0 CCF0 0 = Unimplemented or Reserved Figure 5-12. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 5-20. ATDSTAT1 Field Descriptions Field 7–0 CCF[7:0] Description Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx C) If AFFC=1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 177 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.11 R W Reset ATD Input Enable Register (ATDDIEN) 7 6 5 4 3 2 1 0 IEN7 0 IEN6 0 IEN5 0 IEN4 0 IEN3 0 IEN2 0 IEN1 0 IEN0 0 Figure 5-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 5-21. ATDDIEN Field Descriptions Field 7–0 IEN[7:0] Description ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region. 5.3.2.12 Port Data Register (PORTAD) The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified in the device overview. The port pins are shared with the analog A/D inputs AN7–0. 7 6 5 4 3 2 1 0 R W Reset Pin Function PTAD7 1 AN7 PTAD6 1 AN6 PTAD5 1 AN5 PTAD4 1 AN4 PTAD3 1 AN3 PTAD2 1 AN2 PTAD1 1 AN1 PTAD0 1 AN0 = Unimplemented or Reserved Figure 5-14. Port Data Register (PORTAD) Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general purpose digital input. Table 5-22. PORTAD Field Descriptions Field 7–0 PTAD[7:0] Description A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD0 bits to “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 178 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.3.2.13 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 5.3.2.13.1 7 Left Justified Result Data 6 5 4 3 2 1 0 R BIT 9 MSB R BIT 7 MSB W Reset 0 BIT 8 BIT 6 0 BIT 7 BIT 5 0 BIT 6 BIT 4 0 BIT 5 BIT 3 0 BIT 4 BIT 2 0 BIT 3 BIT 1 0 BIT 2 BIT 0 0 10-bit data 8-bit data = Unimplemented or Reserved Figure 5-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH) 7 6 5 4 3 2 1 0 R R W Reset BIT 1 U 0 BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) 5.3.2.13.2 7 Right Justified Result Data 6 5 4 3 2 1 0 R R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 0 BIT 8 0 0 10-bit data 8-bit data = Unimplemented or Reserved Figure 5-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH) 7 6 5 4 3 2 1 0 R BIT 7 R BIT 7 MSB W Reset 0 BIT 6 BIT 6 0 BIT 5 BIT 5 0 BIT 4 BIT 4 0 BIT 3 BIT 3 0 BIT 2 BIT 2 0 BIT 1 BIT 1 0 BIT 0 BIT 0 0 10-bit data 8-bit data = Unimplemented or Reserved Figure 5-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 179 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.4 Functional Description The ATD is structured in an analog and a digital sub-block. 5.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 5.4.1.1 Sample and Hold Machine The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA. 5.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine. 5.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 5.4.1.4 Analog-to-Digital (A/D) Machine The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes. MC9S12XDP512 Data Sheet, Rev. 2.17 180 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See register descriptions for all details. 5.4.2.1 External Trigger Input The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 5-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. Table 5-23. External Trigger Control Bits ETRIGLE X X 0 0 1 ETRIGP X X 0 1 0 ETRIGE 0 0 1 1 1 SCAN 0 1 X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active. 1 1 1 X During a conversion, if additional active edges are detected the overrun error flag ETORF is set. In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled. Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 181 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 5.4.2.2 General Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port register PORTAD (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input. 5.4.2.3 Low Power Modes The ATD can be configured for lower MCU power consumption in 3 different ways: 1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. 3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state. 5.5 Resets At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 5.3, “Memory Map and Register Definition”), which details the registers and their bit-field. 5.6 Interrupts The interrupt requested by the ATD is listed in Table 5-24. Refer to the device overview chapter for related vector address and priority. Table 5-24. ATD Interrupt Vectors Interrupt Source Sequence complete interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2 See register descriptions for further details. MC9S12XDP512 Data Sheet, Rev. 2.17 182 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.1 Introduction The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 6-1 gives an overview on the XGATE architecture. This document describes the functionality of the XGATE module, including: • XGATE registers (Section 6.3, “Memory Map and Register Definition”) • XGATE RISC core (Section 6.4.1, “XGATE RISC Core”) • Hardware semaphores (Section 6.4.4, “Semaphores”) • Interrupt handling (Section 6.5, “Interrupts”) • Debug features (Section 6.6, “Debug Mode”) • Security (Section 6.7, “Security”) • Instruction set (Section 6.8, “Instruction Set”) 6.1.1 Glossary of Terms XGATE Request A service request from a peripheral module which is directed to the XGATE by the S12X_INT module (see Figure 6-1). XGATE Channel The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request Vector, Interrupt Flag) which are associated with a particular XGATE Request. XGATE Channel ID A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range from $78 to $09. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 183 Chapter 6 XGATE (S12XGATEV2) Special XGATE channel that is not associated with any peripheral service request. A Software Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module. XGATE Semaphore A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE. (see 6.4.4/6-204) XGATE Thread A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request. XGATE Debug Mode A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables the XGATE’s debug features (see 6.6/6-206). XGATE Software Error The XGATE is able to detect a number of error conditions caused by erratic software (see 6.4.5/6-205). These error conditions will cause the XGATE to seize program execution and flag an Interrupt to the S12X_CPU. Word A 16 bit entity. Byte An 8 bit entity. 6.1.2 Features The XGATE module includes these features: • Data movement between various targets (i.e Flash, RAM, and peripheral modules) • Data manipulation through built in RISC core • Provides up to 112 XGATE channels — 104 hardware triggered channels — 8 software triggered channels • Hardware semaphores which are shared between the S12X_CPU and the XGATE module • Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer • Software error detection to catch erratic application code 6.1.3 Modes of Operation There are four run modes on S12X devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active) MC9S12XDP512 Data Sheet, Rev. 2.17 184 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 6.3.1.1, “XGATE Control Register (XGMCTL)”). 6.1.4 Block Diagram Figure Figure 6-1 shows a block diagram of the XGATE. Peripheral Interrupts S12X_INT XGATE INTERRUPTS XGATE REQUESTS XGATE Interrupt Flags Semaphores Software Triggers RISC Core Software Triggers Data/Code S12X_DBG Peripherals S12X_MMC Figure 6-1. XGATE Block Diagram 6.2 External Signal Description The XGATE module has no external pins. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 185 Chapter 6 XGATE (S12XGATEV2) 6.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Figure 6-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved registers have no effect. 6.3.1 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name XGMCTL R W XGMCHID R W Reserved R W Reserved R W Reserved R W XGVBR R W = Unimplemented or Reserved XGVBR[15:1] 0 15 0 XGEM 14 0 13 0 12 0 11 0 10 0 9 0 XG SWEIFM 8 0 XGIEM 7 6 5 4 3 XG FACT 2 0 1 0 XG XG XG XGSSM FRZM DBGM FACTM XGE XGFRZ XGDBG XGSS XG XGIE SWEIF 0 XGCHID[6:0] Figure 6-2. XGATE Register Summary (Sheet 1 of 3) MC9S12XDP512 Data Sheet, Rev. 2.17 186 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 127 XGIF R W 111 XGIF R W 0 126 0 125 0 124 0 123 0 122 0 121 0 120 119 118 117 116 115 114 113 112 XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 95 XGIF R W 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 79 XGIF R W Register Name XGIF R W 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 47 XGIF R W 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 31 XGIF R W 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 15 XGIF R W 14 13 12 11 10 9 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 = Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet 2 of 3) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 187 Chapter 6 XGATE (S12XGATEV2) 15 XGSWTM R W XGSEMM R W Reserved R W XGCCR R W XGPC R W Reserved R W Reserved R W XGR1 R W XGR2 R W XGR3 R W XGR4 R W XGR5 R W XGR6 R W XGR7 R W 0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 2 1 0 XGSWTM[7:0] 0 0 0 0 0 0 0 XGSWT[7:0] XGSEMM[7:0] XGSEM[7:0] 0 0 0 0 XGN XGZ XGV XGC XGPC XGR1 XGR2 XGR3 XGR4 XGR5 XGR6 XGR7 = Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet 3 of 3) MC9S12XDP512 Data Sheet, Rev. 2.17 188 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.1 XGATE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 6-3. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 XGEM 0 0 0 0 XG SSM 0 0 XG FACTM 0 0 0 0 XGE 0 XGFRZ XGDBG XGSS XGFACT 0 0 0 0 0 XG XG FRZM DBGM 0 0 XG XGIEM SWEIFM 0 0 0 XG SWEIF 0 XGIE 0 0 = Unimplemented or Reserved Figure 6-3. XGATE Control Register (XGMCTL) Read: Anytime Write: Anytime Table 6-1. XGMCTL Field Descriptions (Sheet 1 of 3) Field 15 XGEM Description XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is written to the XGEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGE in the same bus cycle 1 Enable write access to the XGE in the same bus cycle XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared if a "1" is written to the XGFRZM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFRZ in the same bus cycle 1 Enable write access to the XGFRZ in the same bus cycle XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared if a "1" is written to the XGDBGM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGDBG in the same bus cycle 1 Enable write access to the XGDBG in the same bus cycle XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a "1" is written to the XGSSM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSS in the same bus cycle 1 Enable write access to the XGSS in the same bus cycle 14 XGFRZM 13 XGDBGM 12 XGSSM MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 189 Chapter 6 XGATE (S12XGATEV2) Table 6-1. XGMCTL Field Descriptions (Sheet 2 of 3) Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFACT in the same bus cycle 1 Enable write access to the XGFACT in the same bus cycle XGSWEIF Mask — This bit controls the write access to the XGSWEIF bit. The XGSWEIF bit can only be cleared 9 XGSWEIFM if a "1" is written to the XGSWEIFM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSWEIF in the same bus cycle 1 Enable write access to the XGSWEIF in the same bus cycle 8 XGIEM XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1" is written to the XGIEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGIE in the same bus cycle 1 Enable write access to the XGIE in the same bus cycle XGATE Module Enable — This bit enables the XGATE module. If the XGATE module is disabled, pending XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will continue to run. Read: 0 XGATE module is disabled 1 XGATE module is enabled Write: 0 Disable XGATE module 1 Enable XGATE module Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active). Read: 0 RISC core operates normally in Freeze (BDM active) 1 RISC core stops in Freeze Mode (BDM active) Write: 0 Don’t stop RISC core in Freeze Mode (BDM active) 1 Stop RISC core in Freeze Mode (BDM active) XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see Section 6.6, “Debug Mode”). Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see S12X_DBG Section), or by writing a "1" to this bit. Read: 0 RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit. 7 XGE 6 XGFRZ 5 XGDBG MC9S12XDP512 Data Sheet, Rev. 2.17 190 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) Table 6-1. XGMCTL Field Descriptions (Sheet 3 of 3) Field 4 XGSS Description XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed. Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE idle periods Read: 0 XGATE will only flag activity if it is not idle or in debug mode. 1 XGATE will always signal activity to the MCU. Write: 0 Only flag activity if not idle or in debug mode. 1 Always signal XGATE activity. XGATE Software Error Interrupt Flag — This bit signals a pending Software Error Interrupt. It is set if the RISC core detects an error condition (see Section 6.4.5, “Software Error Detection”). The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle. Read: 0 Software Error Interrupt is not pending 1 Software Error Interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the XGSWEIF bit XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module Read: 0 All XGATE interrupts disabled 1 All XGATE interrupts enabled Write: 0 Disable all XGATE interrupts 1 Enable all XGATE interrupts 3 XGFACT 1 XGSWEIF 0 XGIE MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 191 Chapter 6 XGATE (S12XGATEV2) 6.3.1.2 XGATE Channel ID Register (XGCHID) The XGATE channel ID register (Figure 6-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads (see Section 6.6.1, “Debug Features”). 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 XGCHID[6:0] 0 0 0 0 = Unimplemented or Reserved Figure 6-4. XGATE Channel ID Register (XGCHID) Read: Anytime Write: In Debug Mode Table 6-2. XGCHID Field Descriptions Field Description 6–0 Request Identifier — ID of the currently active channel XGCHID[6:0] 6.3.1.3 XGATE Vector Base Address Register (XGVBR) The vector base address register (Figure 6-5 and Figure 6-6) determines the location of the XGATE vector block. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 XGVBR[15:1] 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 6-5. XGATE Vector Base Address Register (XGVBR) Read: Anytime Write: Only if the module is disabled (XGE = 0) and idle (XGCHID = $00)) Table 6-3. XGVBR Field Descriptions Field Description 15–1 Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE XBVBR[15:1] memory map. MC9S12XDP512 Data Sheet, Rev. 2.17 192 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.4 XGATE Channel Interrupt Flag Vector (XGIF) The interrupt flag vector (Figure 6-6) provides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location. 127 126 125 124 123 122 121 120 XGIF_78 119 XGF_77 118 117 116 115 114 113 112 R W Reset 0 0 111 0 0 110 0 0 109 0 0 108 0 0 107 0 0 106 0 0 105 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70 0 104 0 103 XGF_67 0 102 0 101 0 100 0 99 0 98 0 97 0 96 R W Reset XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 0 95 0 94 0 93 0 92 0 91 0 90 0 89 0 88 0 87 XGF_57 0 86 0 85 0 84 0 83 0 82 0 81 0 80 R W Reset XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 0 79 0 78 0 77 0 76 0 75 0 74 0 73 0 72 0 71 0 70 0 69 0 68 0 67 0 66 0 65 0 64 R W Reset XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 0 63 0 62 0 61 0 60 0 59 0 58 0 57 0 56 0 55 0 54 0 53 0 52 0 51 0 50 0 49 0 48 R W Reset XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 0 47 0 46 0 45 0 44 0 43 0 42 0 41 0 40 0 39 0 38 0 37 0 36 0 35 0 34 0 33 0 32 R W Reset XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20 0 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 R W Reset XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 R W Reset XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 6-6. XGATE Channel Interrupt Flag Vector (XGIF) Read: Anytime Write: Anytime MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 193 Chapter 6 XGATE (S12XGATEV2) Table 6-4. XGIV Field Descriptions Field 127–9 XGIF[78:9] Description Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core. Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Refer to Section “Interrupts” of the SoC Guide for a list of implemented Interrupts. Read: 0 Channel interrupt is not pending 1 Channel interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the interrupt flag NOTE Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0]) MC9S12XDP512 Data Sheet, Rev. 2.17 194 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.5 XGATE Software Trigger Register (XGSWT) The eight software triggers of the XGATE module can be set and cleared through the XGATE software trigger register (Figure 6-7). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XGSWTM[7:0] XGSWT[7:0] 0 0 0 0 0 Figure 6-7. XGATE Software Trigger Register (XGSWT) Read: Anytime Write: Anytime Table 6-5. XGSWT Field Descriptions Field Description 15–8 Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access. Read: These bits will always read "0". Write: 0 Disable write access to the XGSWT in the same bus cycle 1 Enable write access to the corresponding XGSWT bit in the same bus cycle 7–0 XGSWT[7:0] Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels. They can only be set and cleared by software. Read: 0 No software trigger pending 1 Software trigger pending if the XGIE bit is set Write: 0 Clear Software Trigger 1 Set Software Trigger NOTE The XGATE channel IDs that are associated with the eight software triggers are determined on chip integration level. (see Section “Interrupts” of the Soc Guide) XGATE software triggers work like any peripheral interrupt. They can be used as XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 195 Chapter 6 XGATE (S12XGATEV2) 6.3.1.6 XGATE Semaphore Register (XGSEM) The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register (Figure 6-8). Refer to section Section 6.4.4, “Semaphores” for details. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XGSEMM[7:0] XGSEM[7:0] 0 0 0 0 0 Figure 6-8. XGATE Semaphore Register (XGSEM) Read: Anytime Write: Anytime (see Section 6.4.4, “Semaphores”) Table 6-6. XGSEM Field Descriptions Field Description 15–8 Semaphore Mask — These bits control the write access to the XGSEM bits. XGSEMM[7:0] Read: These bits will always read "0". Write: 0 Disable write access to the XGSEM in the same bus cycle 1 Enable write access to the XGSEM in the same bus cycle 7–0 XGSEM[7:0] Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access. Read: 0 Semaphore is unlocked or locked by the RISC core 1 Semaphore is locked by the S12X_CPU Write: 0 Clear semaphore if it was locked by the S12X_CPU 1 Attempt to lock semaphore by the S12X_CPU MC9S12XDP512 Data Sheet, Rev. 2.17 196 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.7 XGATE Condition Code Register (XGCCR) The XGCCR register (Figure 6-9) provides access to the RISC core’s condition code register. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGN 0 XGZ 0 XGV 0 XGC 0 = Unimplemented or Reserved Figure 6-9. XGATE Condition Code Register (XGCCR) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-7. XGCCR Field Descriptions Field 3 XGN 2 XGZ 1 XGV 0 XGC Sign Flag — The RISC core’s Sign flag Zero Flag — The RISC core’s Zero flag Overflow Flag — The RISC core’s Overflow flag Carry Flag — The RISC core’s Carry flag Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 197 Chapter 6 XGATE (S12XGATEV2) 6.3.1.8 XGATE Program Counter Register (XGPC) The XGPC register (Figure 6-10) provides access to the RISC core’s program counter. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 XGPC 0 0 0 0 0 0 0 0 0 Figure 6-10. XGATE Program Counter Register (XGPC) Figure 6-11. Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-8. XGPC Field Descriptions Field 15–0 XGPC[15:0] Description Program Counter — The RISC core’s program counter 6.3.1.9 XGATE Register 1 (XGR1) The XGR1 register (Figure 6-12) provides access to the RISC core’s register 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR1 0 0 0 0 0 0 0 0 Figure 6-12. XGATE Register 1 (XGR1) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-9. XGR1 Field Descriptions Field 15–0 XGR1[15:0] Description XGATE Register 1 — The RISC core’s register 1 MC9S12XDP512 Data Sheet, Rev. 2.17 198 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.10 XGATE Register 2 (XGR2) The XGR2 register (Figure 6-13) provides access to the RISC core’s register 2. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR2 0 0 0 0 0 0 0 0 Figure 6-13. XGATE Register 2 (XGR2) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-10. XGR2 Field Descriptions Field 15–0 XGR2[15:0] Description XGATE Register 2 — The RISC core’s register 2 6.3.1.11 XGATE Register 3 (XGR3) The XGR3 register (Figure 6-14) provides access to the RISC core’s register 3. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR3 0 0 0 0 0 0 0 0 Figure 6-14. XGATE Register 3 (XGR3) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-11. XGR3 Field Descriptions Field 15–0 XGR3[15:0] Description XGATE Register 3 — The RISC core’s register 3 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 199 Chapter 6 XGATE (S12XGATEV2) 6.3.1.12 XGATE Register 4 (XGR4) The XGR4 register (Figure 6-15) provides access to the RISC core’s register 4. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR4 0 0 0 0 0 0 0 0 Figure 6-15. XGATE Register 4 (XGR4) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-12. XGR4 Field Descriptions Field 15–0 XGR4[15:0] Description XGATE Register 4 — The RISC core’s register 4 6.3.1.13 XGATE Register 5 (XGR5) The XGR5 register (Figure 6-16) provides access to the RISC core’s register 5. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR5 0 0 0 0 0 0 0 0 Figure 6-16. XGATE Register 5 (XGR5) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-13. XGR5 Field Descriptions Field 15–0 XGR5[15:0] Description XGATE Register 5 — The RISC core’s register 5 MC9S12XDP512 Data Sheet, Rev. 2.17 200 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.3.1.14 XGATE Register 6 (XGR6) The XGR6 register (Figure 6-17) provides access to the RISC core’s register 6. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR6 0 0 0 0 0 0 0 0 Figure 6-17. XGATE Register 6 (XGR6) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-14. XGR6 Field Descriptions Field 15–0 XGR6[15:0] Description XGATE Register 6 — The RISC core’s register 6 6.3.1.15 XGATE Register 7 (XGR7) The XGR7 register (Figure 6-18) provides access to the RISC core’s register 7. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 XGR7 0 0 0 0 0 0 0 0 Figure 6-18. XGATE Register 7 (XGR7) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-15. XGR7 Field Descriptions Field 15–0 XGR7[15:0] Description XGATE Register 7 — The RISC core’s register 7 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 201 Chapter 6 XGATE (S12XGATEV2) 6.4 Functional Description The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 6-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible. A new XGATE request can only be serviced when the previous sequence is finished and the RISC core becomes idle. The XGATE module also provides a set of hardware semaphores which are necessary to ensure data consistency whenever RAM locations or peripherals are shared with the S12X_CPU. The following sections describe the components of the XGATE module in further detail. 6.4.1 XGATE RISC Core The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit manipulations, and simple arithmetic operations (see Section 6.8, “Instruction Set”). It is able to access the MCU’s internal memories and peripherals without blocking these resources from the S12X_CPU1. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core will be stalled until the resource becomes available again1. The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC core can perform up to two RAM accesses per S12X_CPU bus cycle. Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU cycle can not be exceeded. The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral modules or by software. 6.4.2 Programmer’s Model Register Block 15 15 15 15 15 15 15 15 Program Counter 0 0 0 0 0 0 0 0 15 R7 R6 R5 R4 R3 R2 PC 0 Condition Code Register NZVC 3210 R1(Variable Pointer) R0 = 0 Figure 6-19. Programmer’s Model 1. With the exception of PRR registers (see Section “S12X_MMC”). MC9S12XDP512 Data Sheet, Rev. 2.17 202 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) The programmer’s model of the XGATE RISC core is shown in Figure 6-19. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded with the initial variable pointer of the channel’s service request vector (see Figure 6-20). The initial content of the remaining general purpose registers is undefined. The 16 bit program counter allows the addressing of a 64 kbyte address space. The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and the carry bit (C). The initial content of the condition code register is undefined. 6.4.3 Memory Map The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed information. The XGATE vector block assigns a start address and a variable pointer to each XGATE channel. Its position in the XGATE memory map can be adjusted through the XGVBR register (see Section 6.3.1.3, “XGATE Vector Base Address Register (XGVBR)”). Figure 6-20 shows the layout of the vector block. Each vector consists of two 16 bit words. The first contains the start address of the service routine. This value will be loaded into the program counter before a service routine is executed. The second word is a pointer to the service routine’s variable space. This value will be loaded into register R1 before a service routine is executed. XGVBR +$0000 unused Code +$0024 Channel $09 Initial Program Counter Channel $09 Initial Variable Pointer +$0028 Channel $0A Initial Program Counter Channel $0A Initial Variable Pointer +$002C Channel $0B Initial Program Counter Channel $0B Initial Variable Pointer +$0030 Channel $0C Initial Program Counter Channel $0C Initial Variable Pointer Variables Code +$01E0 Channel $78 Initial Program Counter Channel $78 Initial Variable Pointer Variables Figure 6-20. XGATE Vector Block MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 203 Chapter 6 XGATE (S12XGATEV2) 6.4.4 Semaphores The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the S12X_CPU and one running on the XGATE RISC core. Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore register (XGSEM, see Section 6.3.1.6, “XGATE Semaphore Register (XGSEM)”). The RISC core does this through its SSEM and CSEM instructions. Figure 6-21 illustrates the valid state transitions. %1 ⇒ XGSEM SSEM Instruction CSEM Instruction %1 ⇒ XGSEM %0 ⇒ XGSEM SSEM Instruction LOCKED BY S12X_CPU LOCKED BY XGATE M SE XG M ⇒ SE 0 . % EM str XG r ⇒ o GS In XM 1 % ⇒E 1 SS % nd a UNLOCKED %0 ⇒ XGSEM CSEM Instruction Figure 6-21. Semaphore State Transitions MC9S12XDP512 Data Sheet, Rev. 2.17 204 Freescale Semiconductor In CS st E ru M ct In SS io st E n ru M ct io n Chapter 6 XGATE (S12XGATEV2) Figure 6-22 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown. S12X_CPU ......... %1 ⇒ XGSEMx XGSEM ≡ %1? XGATE ......... SSEM BCC? critical code sequence critical code sequence XGSEM ⇒ %0 ......... CSEM ......... Figure 6-22. Algorithm for Locking and Releasing Semaphores 6.4.5 Software Error Detection The XGATE module will immediately terminate program execution after detecting an error condition caused by erratic application code. There are three error conditions: • Execution of an illegal opcode • Illegal vector or opcode fetches • Illegal load or store accesses All opcodes which are not listed in section Section 6.8, “Instruction Set” are illegal opcodes. Illegal vector and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the S12X_MMC Section for a detailed information. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 205 Chapter 6 XGATE (S12XGATEV2) 6.5 6.5.1 Interrupts Incoming Interrupt Requests XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide. 6.5.2 Outgoing Interrupt Requests There are three types of interrupt requests which can be triggered by the XGATE module: 4. Channel interrupts For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector (XGIF, see Section 6.3.1.4, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to the S12X_CPU when the XGATE has completed one of its tasks. 5. Software triggers Software triggers are interrupt flags, which can be set and cleared by software (see Section 6.3.1.5, “XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software. 6. Software error interrupt The software error interrupt signals to the S12X_CPU the detection of an error condition in the XGATE application code (see Section 6.4.5, “Software Error Detection”). All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL, see Section 6.3.1.1, “XGATE Control Register (XGMCTL)”). 6.6 Debug Mode The XGATE debug mode is a feature to allow debugging of application code. 6.6.1 Debug Features In debug mode the RISC core will be halted and the following debug features will be enabled: • Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)1 All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values. 1. Only possible if MCU is unsecured MC9S12XDP512 Data Sheet, Rev. 2.17 206 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) • • Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly. Write accesses to the XGCHID register Three operations can be performed by writing to the XGCHID register: – Change of channel ID If a non-zero value is written to the XGCHID while a thread is active (XGCHID ≠ $00), then the current channel ID will be changed without any influence on the program counter or the other RISC core registers. – Start of a thread If a non-zero value is written to the XGCHID while the XGATE is idle (XGCHID = $00), then the thread that is associated with the new channel ID will be executed upon leaving debug mode. – Termination of a thread If zero is written to the XGCHID while a thread is active (XGCHID ≠ $00), then the current thread will be terminated and the XGATE will become idle. 6.6.2 Entering Debug Mode Debug mode can be entered in four ways: 1. Setting XGDBG to "1" Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter debug mode upon completion of the current instruction. NOTE After writing to the XGDBG bit the XGATE will not immediately enter debug mode. Depending on the instruction that is executed at this time there may be a delay of several clock cycles. The XGDBG will read "0" until debug mode is entered. 2. Software breakpoints XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A software breakpoint is set by replacing an instruction of the program code with the "BRK" instruction. As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode. Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the "BRK" instruction. The other RISC core registers will hold the result of the previous instruction. To resume program execution, the "BRK" instruction must be replaced by the original instruction before leaving debug mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 207 Chapter 6 XGATE (S12XGATEV2) 3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion of the current instruction. 6.6.3 Leaving Debug Mode Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been cleared in debug mode), program execution will resume at the value of XGPC. 6.7 Security In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug features have been made. These are: • Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device • Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device • Single stepping is not possible on a secured device 6.8 6.8.1 Instruction Set Addressing Modes For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all operations must have one of the eight general purpose registers R0 … R7 as their source as well their destination. All word accesses must work with a word aligned address, that is A[0] = 0! MC9S12XDP512 Data Sheet, Rev. 2.17 208 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.8.1.1 Naming Conventions Destination register, allowed range is R0–R7 Low byte of the destination register, bits [7:0] High byte of the destination register, bits [15:8] Source register, allowed range is R0–R7 Low byte of the source register, bits [7:0] High byte of the source register, bits[15:8] Base register for indexed addressing modes, allowed range is R0–R7 Offset register for indexed addressing modes with register offset, allowed range is R0–R7 Offset register for indexed addressing modes with register offset and post-increment, Allowed range is R0–R7 (R0+ is equivalent to R0) Offset register for indexed addressing modes with register offset and pre-decrement, Allowed range is R0–R7 (–R0 is equivalent to R0) RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.H RB RI RI+ –RI NOTE Even though register R1 is intended to be used as a pointer to the variable segment, it may be used as a general purpose data register as well. Selecting R0 as destination register will discard the result of the instruction. Only the condition code register will be updated 6.8.1.2 Inherent Addressing Mode (INH) Instructions that use this addressing mode either have no operands or all operands are in internal XGATE registers:. Examples BRK RTS 6.8.1.3 Immediate 3-Bit Wide (IMM3) Operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an immediate addressing mode operand. This address mode is used for semaphore instructions. Examples: CSEM SSEM #1 #3 ; Unlock semaphore 1 ; Lock Semaphore 3 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 209 Chapter 6 XGATE (S12XGATEV2) 6.8.1.4 Immediate 4 Bit Wide (IMM4) The 4 bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples: LSL LSR R4,#1 R4,#3 ; R4 = R4 > 3; shift register R4 by 3 bits to the right 6.8.1.5 Immediate 8 Bit Wide (IMM8) The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples: ADDL SUBL LDH CMPL R1,#1 R2,#2 R3,#3 R4,#4 ; ; ; ; adds an 8 bit value to register R1 subtracts an 8 bit value from register R2 loads an 8 bit immediate into the high byte of Register R3 compares the low byte of register R4 with an immediate value 6.8.1.6 Immediate 16 Bit Wide (IMM16) The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode. RD = RD ∗ imm16 Examples: LDW ADD R4,#$1234 R4,#$5678 ; translated to LDL R4,#$34; LDH R4,#$12 ; translated to ADDL R4,#$78; ADDH R4,#$56 6.8.1.7 Monadic Addressing (MON) In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)), the target (RD = f()), or both source and target of the operation (RD = f(RD)). Examples: JAL SIF R1 R2 ; PC = R1, R1 = PC+2 ; Trigger IRQ associated with the channel number in R2.L MC9S12XDP512 Data Sheet, Rev. 2.17 210 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.8.1.8 Dyadic Addressing (DYA) In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated. This addressing mode is used only for shift operations with a variable shift value Examples: LSL LSR R4,R5 R4,R5 ; R4 = R4 > R5 6.8.1.9 Triadic Addressing (TRI) In this mode the result of an operation between two or three registers is stored into a third one. RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code flags are updated. This addressing mode is used for all arithmetic and logical operations. Examples: ADC SUB R5,R6,R7 R5,R6,R7 ; R5 = R6 + R7 + Carry ; R5 = R6 - R7 6.8.1.10 Relative Addressing 9-Bit Wide (REL9) A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for conditional branch instructions. Examples: BCC BEQ REL9 REL9 ; PC = PC + 2 + (REL9 R2;arithmetic shift register R4 right by the amount ; of bits contained in R2[3:0]. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 213 Chapter 6 XGATE (S12XGATEV2) 6.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word. 15 W4 O4 5 2 W4=3, O4=2 RS2 0 RS1 Bit Field Extract Bit Field Insert 15 3 0 RD Figure 6-23. Bit Field Addressing BFEXT R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3 6.8.2.6 Special Instructions for DMA Usage The XGATE offers a number of additional instructions for flag manipulation, program flow control and debugging: 1. SIF: Set a channel interrupt flag 2. SSEM: Test and set a hardware semaphore 3. CSEM: Clear a hardware semaphore 4. BRK: Software breakpoint 5. NOP: No Operation 6. RTS: Terminate the current thread MC9S12XDP512 Data Sheet, Rev. 2.17 214 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) 6.8.3 Cycle Notation Table 6-16 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle. Table 6-16. Access Detail Notation V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle r — 8 bit data read: lasts for at least one RISC core cycle R — 16 bit data read: lasts for at least one RISC core cycle w — 8 bit data write: lasts for at least one RISC core cycle W — 16 bit data write: lasts for at least one RISC core cycle A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles f — Free cycle: no read or write, lasts for one RISC core cycles Special Cases PP/P — Branch: PP if branch taken, P if not 6.8.4 Thread Execution When the RISC core is triggered by an interrupt request (see Figure 6-1) it first executes a vector fetch sequence which performs three bus accesses: 1. A V-cycle to fetch the initial content of the program counter. 2. A V-cycle to fetch the initial content of the data segment pointer (R1). 3. A P-cycle to load the initial opcode. Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If further interrupt requests are pending after a thread has been terminated, a new vector fetch will be performed. Otherwise the RISC core will idle until a new interrupt request is received. A thread can not be interrupted by an interrupt request. 6.8.5 Instruction Glossary This section describes the XGATE instruction set in alphabetical order. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 215 Chapter 6 XGATE (S12XGATEV2) ADC Operation RS1 + RS2 + C ⇒ RD Add with Carry ADC Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions. Example: ADC ADC BCC R6,R2,R2 R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2 ; conditional branch on 32 bit addition CCR Effects N ∆ N: Z: V: C: Z ∆ V ∆ C ∆ Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000 and Z was set before this operation; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Code and CPU Cycles Source Form ADC RD, RS1, RS2 Address Mode TRI 0 0 0 1 1 Machine Code RD RS1 RS2 1 1 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 216 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) ADD Operation Add without Carry ADD RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16 bit addition and stores the result in the destination register RD. CCR Effects N ∆ N: Z: V: Z ∆ V ∆ C ∆ C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. Code and CPU Cycles Source Form ADD RD, RS1, RS2 ADD RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 1 0 Cycles P P P MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 217 Chapter 6 XGATE (S12XGATEV2) ADDH Operation RD + IMM8:$00 ⇒ RD Add Immediate 8 bit Constant (High Byte) ADDH Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition. Example: ADDL ADDH R2,#LOWBYTE R2,#HIGHBYTE ; R2 = R2 + 16 bit immediate CCR Effects N ∆ N: Z: V: C: Z ∆ V ∆ C ∆ Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new Code and CPU Cycles Source Form ADDH RD, #IMM8 Address Mode IMM8 1 1 1 0 1 Machine Code RD IMM8 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 218 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) ADDL Operation RD + $00:IMM8 ⇒ RD Add Immediate 8 bit Constant (Low Byte) ADDL Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects N ∆ N: Z: V: C: Z ∆ V ∆ C ∆ Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RD[15]old & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & RD[15]new Code and CPU Cycles Source Form ADDL RD, #IMM8 Address Mode IMM8 1 1 1 0 0 Machine Code RD IMM8 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 219 Chapter 6 XGATE (S12XGATEV2) AND Operation Logical AND AND RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD. Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result. CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C — Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Refer to ANDH instruction for #IMM16 operations. 0; cleared. Not affected. Code and CPU Cycles Source Form AND RD, RS1, RS2 AND RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 0 0 Cycles P P P MC9S12XDP512 Data Sheet, Rev. 2.17 220 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) ANDH Operation RD.H & IMM8 ⇒ RD.H Logical AND Immediate 8 bit Constant (High Byte) ANDH Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C — Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form ANDH RD, #IMM8 Address Mode IMM8 1 0 0 0 1 Machine Code RD IMM8 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 221 Chapter 6 XGATE (S12XGATEV2) ANDL Operation RD.L & IMM8 ⇒ RD.L Logical AND Immediate 8 bit Constant (Low Byte) ANDL Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C — Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form ANDL RD, #IMM8 Address Mode IMM8 1 0 0 0 0 Machine Code RD IMM8 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 222 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) ASR Operation b15 Arithmetic Shift Right ASR C n RD n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0. In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS is greater than 15. CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C ∆ Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected. Code and CPU Cycles Source Form ASR RD, #IMM4 ASR RD, RS Address Mode IMM4 DYA 0 0 0 0 0 0 0 0 1 1 Machine Code RD RD IMM4 RS 1 1 0 0 0 0 0 1 1 Cycles P P MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 223 Chapter 6 XGATE (S12XGATEV2) BCC Operation Branch if Carry Cleared (Same as BHS) BCC If C = 0, then PC + $0002 + (REL9 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits. 15 7 W4 15 3 4 3 O4 0 RS1 Inverted Bit Field Insert 15 5 2 0 RD 0 RS2 W4=3, O4=2 CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C — Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form BFINSI RD, RS1, RS2 Address Mode TRI 0 1 1 1 0 Machine Code RD RS1 RS2 1 1 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 230 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) BFINSX Operation Bit Field Insert and XNOR BFINSX !(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back io RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits. 15 7 W4 15 3 4 3 O4 0 RS1 Bit Field Insert XNOR 15 5 2 0 RD 0 RS2 W4=3, O4=2 CCR Effects N ∆ N: Z: V: C: Z ∆ V 0 C — Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form BFINSX RD, RS1, RS2 Address Mode TRI 0 1 1 1 1 Machine Code RD RS1 RS2 1 1 Cycles P MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 231 Chapter 6 XGATE (S12XGATEV2) BGE Operation Branch if RS1 ≥ RS2: SUB BGE Branch if Greater than or Equal to Zero BGE If N ^ V = 0, then PC + $0002 + (REL9 RS2: SUB BGE R0,RS1,RS2 REL9 Branch if Greater than Zero BGT If Z | (N ^ V) = 0, then PC + $0002 + (REL9 RS2: SUB BHI R0,RS1,RS2 REL9 Branch if Higher BHI If C | Z = 0, then PC + $0002 + (REL9 1) $C000 INIT_SCI INIT_INT MC9S12XDP512 Data Sheet, Rev. 2.17 292 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) INIT_XGATE INIT_XGATE_BUSY_LOOP ;########################################### ;# INITIALIZE XGATE # ;########################################### MOVW #XGMCTL_CLEAR , XGMCTL;clear all XGMCTL bits TST BNE LDX LDD STD STD STD STD STD STD STD STD XGCHID ;wait until current thread is finished INIT_XGATE_BUSY_LOOP #XGIF #$FFFF 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ ;clear all channel interrupt flags MOVW #XGATE_VECTORS_XG, XGVBR;set vector base register MOVW #$FF00, XGSWT ;clear all software triggers INIT_XGATE_VECTAB_LOOP ;########################################### ;# INITIALIZE XGATE VECTOR TABLE # ;########################################### LDAA #128 ;build XGATE vector table LDY #XGATE_VECTORS MOVW #XGATE_DUMMY_ISR_XG, 4,Y+ DBNE A, INIT_XGATE_VECTAB_LOOP MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC) MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2 ;########################################### ;# COPY XGATE CODE # ;########################################### LDX #XGATE_DATA_FLASH MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ MOVW 2,X+, 2,Y+ CPX #XGATE_CODE_FLASH_END BLS COPY_XGATE_CODE_LOOP ;########################################### ;# START XGATE # ;########################################### MOVW #XGMCTL_ENABLE, XGMCTL;enable XGATE BRA * ;########################################### ;# DUMMY INTERRUPT SERVICE ROUTINE # ;########################################### RTI CPU XGATE COPY_XGATE_CODE COPY_XGATE_CODE_LOOP START_XGATE DUMMY_ISR MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 293 Chapter 6 XGATE (S12XGATEV2) XGATE_DATA_FLASH XGATE_DATA_SCI XGATE_DATA_IDX XGATE_DATA_MSG ;########################################### ;# XGATE DATA # ;########################################### ALIGN 1 EQU * EQU *-XGATE_DATA_FLASH DW SCI_REGS ;pointer to SCI register space EQU *-XGATE_DATA_FLASH DB XGATE_DATA_MSG ;string pointer EQU *-XGATE_DATA_FLASH FCC "Hello World! ;ASCII string DB $0D ;CR ;########################################### ;# XGATE CODE # ;########################################### ALIGN 1 LDW R2,(R1,#XGATE_DATA_SCI);SCI -> R2 LDB R3,(R1,#XGATE_DATA_IDX);msg -> R3 LDB R4,(R1,R3+) ;curr. char -> R4 STB R3,(R1,#XGATE_DATA_IDX);R3 -> idx LDB R0,(R2,#(SCISR1-SCI_REGS));initiate SCI transmit STB R4,(R2,#(SCIDRL-SCI_REGS));initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS LDL R4,#$00 ;disable SCI interrupts STB R4,(R2,#(SCICR2-SCI_REGS)) LDL R3,#XGATE_DATA_MSG;reset R3 STB R3,(R1,#XGATE_DATA_IDX) RTS EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG XGATE_CODE_FLASH XGATE_CODE_DONE XGATE_CODE_FLASH_END XGATE_DUMMY_ISR_XG MC9S12XDP512 Data Sheet, Rev. 2.17 294 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 295 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 296 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 297 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 298 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 299 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 300 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 301 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 302 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 303 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 304 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 305 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 306 Freescale Semiconductor Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 307 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 308 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.1 Introduction The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. A full access for the counter registers or the input capture/output compare registers will take place in one clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same result as accessing them in one word. 7.1.1 • • • • Features 16-bit buffer register for four input capture (IC) channels. Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-bit pulse accumulators. 16-bit modulus down-counter with 8-bit prescaler. Four user-selectable delay counters for input noise immunity increase. 7.1.2 • • • • Modes of Operation Stop — Timer and modulus counter are off since clocks are stopped. Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register is set to one. Wait — Counters keep on running, unless the TSWAI bit in the TSCR1 register is set to one. Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register or the MCEN bit in the MCCTL register are cleared. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 309 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.1.3 Block Diagram Bus Clock Prescaler 16-bit Counter Channel 0 Input Capture Output Compare Channel 1 Input Capture IOC0 Modulus Counter Interrupt Timer Overflow Interrupt Timer Channel 0 Interrupt 16-Bit Modulus Counter Output Compare Channel 2 Input Capture Output Compare Channel 3 Input Capture Output Compare IOC1 IOC2 IOC3 Registers Channel 4 Input Capture Output Compare Channel 5 Input Capture Output Compare IOC4 IOC5 Timer Channel 7 Interrupt PA Overflow Interrupt PA Input Interrupt PB Overflow Interrupt 16-Bit Pulse Accumulator A 16-Bit Pulse Accumulator B Channel 6 Input Capture Output Compare Channel 7 Input Capture Output Compare IOC6 IOC7 Figure 7-1. ECT Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 310 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.2 External Signal Description The ECT module has a total of eight external pins. 7.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7. 7.2.2 IOC6 — Input Capture and Output Compare Channel 6 This pin serves as input capture or output compare for channel 6. 7.2.3 IOC5 — Input Capture and Output Compare Channel 5 This pin serves as input capture or output compare for channel 5. 7.2.4 IOC4 — Input Capture and Output Compare Channel 4 This pin serves as input capture or output compare for channel 4. 7.2.5 IOC3 — Input Capture and Output Compare Channel 3 This pin serves as input capture or output compare for channel 3. 7.2.6 IOC2 — Input Capture and Output Compare Channel 2 This pin serves as input capture or output compare for channel 2. 7.2.7 IOC1 — Input Capture and Output Compare Channel 1 This pin serves as input capture or output compare for channel 1. 7.2.8 IOC0 — Input Capture and Output Compare Channel 0 NOTE For the description of interrupts see Section 7.4.3, “Interrupts”. This pin serves as input capture or output compare for channel 0. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 311 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 7.3.1 Module Memory Map The memory map for the ECT module is given below in Table 7-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register. Table 7-1. ECT Memory Map Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D Register Timer Input Capture/Output Compare Select (TIOS) Timer Compare Force Register (CFORC) Output Compare 7 Mask Register (OC7M) Output Compare 7 Data Register (OC7D) Timer Count Register High (TCNT) Timer Count Register Low (TCNT) Timer System Control Register 1 (TSCR1) Timer Toggle Overflow Register (TTOV) Timer Control Register 1 (TCTL1) Timer Control Register 2 (TCTL2) Timer Control Register 3 (TCTL3) Timer Control Register 4 (TCTL4) Timer Interrupt Enable Register (TIE) Timer System Control Register 2 (TSCR2) Main Timer Interrupt Flag 1 (TFLG1) Main Timer Interrupt Flag 2 (TFLG2) Timer Input Capture/Output Compare Register 0 High (TC0) Timer Input Capture/Output Compare Register 0 Low (TC0) Timer Input Capture/Output Compare Register 1 High (TC1) Timer Input Capture/Output Compare Register 1 Low (TC1) Timer Input Capture/Output Compare Register 2 High (TC2) Timer Input Capture/Output Compare Register 2 Low (TC2) Timer Input Capture/Output Compare Register 3 High (TC3) Timer Input Capture/Output Compare Register 3 Low (TC3) Timer Input Capture/Output Compare Register 4 High (TC4) Timer Input Capture/Output Compare Register 4 Low (TC4) Timer Input Capture/Output Compare Register 5 High (TC5) Timer Input Capture/Output Compare Register 5 Low (TC5) Timer Input Capture/Output Compare Register 6 High (TC6) Timer Input Capture/Output Compare Register 6 Low (TC6) Access R/W R/W1 R/W R/W R/W2 R/W2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 MC9S12XDP512 Data Sheet, Rev. 2.17 312 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-1. ECT Memory Map (continued) Address Offset 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F 1 2 Register Timer Input Capture/Output Compare Register 7 High (TC7) Timer Input Capture/Output Compare Register 7 Low (TC7) 16-Bit Pulse Accumulator A Control Register (PACTL) Pulse Accumulator A Flag Register (PAFLG) Pulse Accumulator Count Register 3 (PACN3) Pulse Accumulator Count Register 2 (PACN2) Pulse Accumulator Count Register 1 (PACN1) Pulse Accumulator Count Register 0 (PACN0) 16-Bit Modulus Down Counter Register (MCCTL) 16-Bit Modulus Down Counter Flag Register (MCFLG) Input Control Pulse Accumulator Register (ICPAR) Delay Counter Control Register (DLYCT) Input Control Overwrite Register (ICOVW) Input Control System Control Register (ICSYS) Reserved Timer Test Register (TIMTST) Precision Timer Prescaler Select Register (PTPSR) Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) 16-Bit Pulse Accumulator B Control Register (PBCTL) 16-Bit Pulse Accumulator B Flag Register (PBFLG) 8-Bit Pulse Accumulator Holding Register 3 (PA3H) 8-Bit Pulse Accumulator Holding Register 2 (PA2H) 8-Bit Pulse Accumulator Holding Register 1 (PA1H) 8-Bit Pulse Accumulator Holding Register 0 (PA0H) Modulus Down-Counter Count Register High (MCCNT) Modulus Down-Counter Count Register Low (MCCNT) Timer Input Capture Holding Register 0 High (TC0H) Timer Input Capture Holding Register 0 Low (TC0H) Timer Input Capture Holding Register 1 High(TC1H) Timer Input Capture Holding Register 1 Low (TC1H) Timer Input Capture Holding Register 2 High (TC2H) Timer Input Capture Holding Register 2 Low (TC2H) Timer Input Capture Holding Register 3 High (TC3H) Timer Input Capture Holding Register 3 Low (TC3H) Access R/W3 R/W3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W4 -R/W2 R/W R/W R/W R/W R/W5 R/W5 R/W5 R/W5 R/W R/W R/W5 R/W5 R/W5 R/W5 R/W5 R/W5 R/W5 R/W5 Always read 0x0000. Only writable in special modes (test_mode = 1). 3 Writes to these registers have no meaning or effect during input capture. 4 May be written once when not in test00mode but writes are always permitted when test00mode is enabled. 5 Writes have no effect. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 313 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name TIOS R W CFORC R W OC7M R W OC7D R W TCNT (High) R W TCNT (Low) R W TSCR1 R W TTOF R W TCTL1 R W TCTL2 R W TCTL3 R W TCTL4 R W TIE R W Bit 7 IOS7 0 FOC7 OC7M7 6 IOS6 0 FOC6 OC7M6 5 IOS5 0 FOC5 OC7M5 4 IOS4 0 FOC4 OC7M4 3 IOS3 0 FOC3 OC7M3 2 IOS2 0 FOC2 OC7M2 1 IOS1 0 FOC1 OC7M1 Bit 0 IOS0 0 FOC0 OC7M0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 0 TCNT1 0 TCNT0 0 TEN TSWAI TSFRZ TFFCA PRNT TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A C7I C6I C5I C4I C3I C2I C1I C0I = Unimplemented or Reserved Figure 7-2. ECT Register Summary (Sheet 1 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 314 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TSCR2 R W TFLG1 R W TFLG2 R W TC0 (High) R W TC0 (Low) R W TC1 (High) R W TC1 (Low) R W TC2 (High) R W TC2 (Low) R W TC3 (High) R W TC3 (Low) R W TC4 (High) R W TC4 (Low) R W TC5 (High) R W TC5 (Low) R W Bit 7 TOI 6 0 5 0 4 0 3 TCRE 2 PR2 1 PR1 Bit 0 PR0 C7F C6F 0 C5F 0 C4F 0 C3F 0 C2F 0 C1F 0 C0F 0 TOF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = Unimplemented or Reserved Figure 7-2. ECT Register Summary (Sheet 2 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 315 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TC6 (High) R W TC6 (Low) R W TC7 (High) R W TC7 (Low) R W PACTL R W PAFLG R W PACN3 R W PACN2 R W PACN1 R W PACN0 R W MCCTL R W MCFLG R W ICPAR R W DLYCT R W ICOVW R W Bit 7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEN 0 PAMOD 0 PEDGE 0 CLK1 0 CLK0 0 PA0VI PAI 0 PA0VF PAIF PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8) PACNT7 PACNT6 PACNT5 PACNT4 0 ICLAT 0 PACNT3 0 FLMC POLF3 PACNT2 PACNT1 PACNT0 MCZI MODMC 0 RDMCL 0 MCEN POLF2 MCPR1 POLF1 MCPR0 POLF0 MCZF 0 0 0 0 PA3EN PA2EN PA1EN PA0EN DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 = Unimplemented or Reserved Figure 7-2. ECT Register Summary (Sheet 3 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 316 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name ICSYS R W Reserved R W TIMTST R W PTPSR R W PTMCPSR R W PBCTL R W PBFLG R W PA3H R W PA2H R W PA1H R W PA0H R W MCCNT (High) MCCNT (Low) R W R W Bit 7 SH37 6 SH26 5 SH15 4 SH04 3 TFMOD 2 PACMX 1 BUFEN Bit 0 LATQ Reserved Timer Test Register PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTMPS7 0 PTMPS6 PTMPS5 0 PTMPS4 0 PTMPS3 0 PTMPS2 0 PTMPS1 PTMPS0 0 PBEN 0 PBOVI 0 0 0 0 0 PBOVF PA3H1 0 PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H0 PA2H7 PA2H6 PA2H5 PA2H4 PA2H3 PA2H2 PA2H1 PA2H0 PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1H0 PA0H7 PA0H6 PA0H5 PA0H4 PA0H3 PA0H2 PA0H1 PA0H0 MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10 MCCNT9 MCCNT8 MCCNT7 TC15 MCCNT6 TC14 MCCNT5 TC13 MCCNT4 TC12 MCCNT3 TC11 MCCNT2 TC10 MCCNT1 TC9 MCCNT9 TC8 TC0H (High) R W TC0H (Low) R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 = Unimplemented or Reserved Figure 7-2. ECT Register Summary (Sheet 4 of 5) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 317 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TC1H (High) R W TC1H (Low) R W TC2H (High) R W TC2H (Low) R W TC3H (High) R W TC3H (Low) R W Bit 7 TC15 6 TC14 5 TC13 4 TC12 3 TC11 2 TC10 1 TC9 Bit 0 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 = Unimplemented or Reserved Figure 7-2. ECT Register Summary (Sheet 5 of 5) 7.3.2.1 R W Reset Timer Input Capture/Output Compare Select Register (TIOS) 7 6 5 4 3 2 1 0 IOS7 0 IOS6 0 IOS5 0 IOS4 0 IOS3 0 IOS2 0 IOS1 0 IOS0 0 Figure 7-3. Timer Input Capture/Output Compare Register (TIOS) Read or write: Anytime All bits reset to zero. Table 7-2. TIOS Field Descriptions Field 7:0 IOS[7:0] Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare. MC9S12XDP512 Data Sheet, Rev. 2.17 318 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.2 R W Reset Timer Compare Force Register (CFORC) 7 6 5 4 3 2 1 0 0 FOC7 0 0 FOC6 0 0 FOC5 0 0 FOC4 0 0 FOC3 0 0 FOC2 0 0 FOC1 0 0 FOC0 0 Figure 7-4. Timer Compare Force Register (CFORC) Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero. Table 7-3. CFORC Field Descriptions Field 7:0 FOC[7:0] Description Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. Note: A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the same time as the successful output compare, then the forced output compare action will take precedence and the interrupt flag will not get set. 7.3.2.3 R W Reset Output Compare 7 Mask Register (OC7M) 7 6 5 4 3 2 1 0 OC7M7 0 OC7M6 0 OC7M5 0 OC7M4 0 OC7M3 0 OC7M2 0 OC7M1 0 OC7M0 0 Figure 7-5. Output Compare 7 Mask Register (OC7M) Read or write: Anytime All bits reset to zero. Table 7-4. OC7M Field Descriptions Field 7:0 OC7M[7:0] Description Output Compare Mask Action for Channel 7:0 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on a successful channel 7 output compare, even if the corresponding pin is setup for output compare. 1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a successful channel 7 output compare. Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred from the output compare 7 data register to the timer port. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 319 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.4 R W Reset Output Compare 7 Data Register (OC7D) 7 6 5 4 3 2 1 0 OC7D7 0 OC7D6 0 OC7D5 0 OC7D4 0 OC7D3 0 OC7D2 0 OC7D1 0 OC7D0 0 Figure 7-6. Output Compare 7 Data Register (OC7D) Read or write: Anytime All bits reset to zero. Table 7-5. OC7D Field Descriptions Field 7:0 OC7D[7:0] Description Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register. MC9S12XDP512 Data Sheet, Rev. 2.17 320 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.5 R W Reset Timer Count Register (TCNT) 15 14 13 12 11 10 9 8 TCNT15 0 TCNT14 0 TCNT13 0 TCNT12 0 TCNT11 0 TCNT10 0 TCNT9 0 TCNT8 0 Figure 7-7. Timer Count Register High (TCNT) 7 6 5 4 3 2 1 0 R W Reset TCNT7 0 TCNT6 0 TCNT5 0 TCNT4 0 TCNT3 0 TCNT2 0 TCNT1 0 TCNT0 0 Figure 7-8. Timer Count Register Low (TCNT) Read: Anytime Write: Has no meaning or effect All bits reset to zero. Table 7-6. TCNT Field Descriptions Field Description 15:0 Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value TCNT[15:0] of the counter. Access to the counter register will take place in one clock cycle. Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing them as a word. The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 321 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.6 R W Reset Timer System Control Register 1 (TSCR1) 7 6 5 4 3 2 1 0 TEN 0 TSWAI 0 TSFRZ 0 TFFCA 0 PRNT 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-9. Timer System Control Register 1 (TSCR1) Read or write: Anytime except PRNT bit is write once All bits reset to zero. Table 7-7. TSCR1 Field Descriptions Field 7 TEN Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode. Timer interrupts cannot be used to get the MCU out of wait. Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode. 1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation. The pulse accumulators do not stop in freeze mode. Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 A read from an input capture or a write to the output compare channel registers causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses. Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when TFFCA = 1. Precision Timer 0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection. 1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the prescaler Precision Timer Modulus Counter Prescaler selection. 6 TSWAI 5 TSFRZ 4 TFFCA 3 PRNT MC9S12XDP512 Data Sheet, Rev. 2.17 322 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.7 R W Reset Timer Toggle On Overflow Register 1 (TTOV) 7 6 5 4 3 2 1 0 TOV7 0 TOV6 0 TOV5 0 TOV4 0 TOV3 0 TOV2 0 TOV1 0 TOV0 0 Figure 7-10. Timer Toggle On Overflow Register 1 (TTOV) Read or write: Anytime All bits reset to zero. Table 7-8. TTOV Field Descriptions Field 7:0 TOV[7:0] Description Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 323 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.8 R W Reset Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) 7 6 5 4 3 2 1 0 OM7 0 OL7 0 OM6 0 OL6 0 OM5 0 OL5 0 OM4 0 OL4 0 Figure 7-11. Timer Control Register 1 (TCTL1) 7 6 5 4 3 2 1 0 R W Reset OM3 0 OL3 0 OM2 0 OL2 0 OM1 0 OL1 0 OM0 0 OL0 0 Figure 7-12. Timer Control Register 2 (TCTL2) Read or write: Anytime All bits reset to zero. Table 7-9. TCTL1/TCTL2 Field Descriptions Field OM[7:0] 7, 5, 3, 1 OL[7:0] 6, 4, 2, 0 Description OMx — Output Mode OLx — Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx. See Table 7-10. Table 7-10. Compare Result Output Action OMx 0 0 1 1 OLx 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to zero Set OCx output line to one NOTE To enable output action by OMx and OLx bits on timer port, the corresponding bit in OC7M should be cleared. MC9S12XDP512 Data Sheet, Rev. 2.17 324 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.9 R W Reset Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4) 7 6 5 4 3 2 1 0 EDG7B 0 EDG7A 0 EDG6B 0 EDG6A 0 EDG5B 0 EDG5A 0 EDG4B 0 EDG4A 0 Figure 7-13. Timer Control Register 3 (TCTL3) 7 6 5 4 3 2 1 0 R W Reset EDG3B 0 EDG3A 0 EDG2B 0 EDG2A 0 EDG1B 0 EDG1A 0 EDG0B 0 EDG0A 0 Figure 7-14. Timer Control Register 4 (TCTL4) Read or write: Anytime All bits reset to zero. Table 7-11. TCTL3/TCTL4 Field Descriptions Field EDG[7:0]B 7, 5, 3, 1 EDG[7:0]A 6, 4, 2, 0 Description Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the active edge for the 16-bit pulse accumulator PACB. See Table 7-12. Table 7-12. Edge Detector Circuit Configuration EDGxB 0 0 1 1 EDGxA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 325 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.10 R W Reset Timer Interrupt Enable Register (TIE) 7 6 5 4 3 2 1 0 C7I 0 C6I 0 C5I 0 C4I 0 C3I 0 C2I 0 C1I 0 C0I 0 Figure 7-15. Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register. Table 7-13. TIE Field Descriptions Field 7:0 C[7:0]I Description Input Capture/Output Compare “x” Interrupt Enable 0 The corresponding flag is disabled from causing a hardware interrupt. 1 The corresponding flag is enabled to cause an interrupt. MC9S12XDP512 Data Sheet, Rev. 2.17 326 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.11 R W Reset Timer System Control Register 2 (TSCR2) 7 6 5 4 3 2 1 0 TOI 0 0 0 0 0 0 0 TCRE 0 PR2 0 PR1 0 PR0 0 = Unimplemented or Reserved Figure 7-16. Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. Table 7-14. TSCR2 Field Descriptions Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set. Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output compare. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset disabled and counter free runs. 1 Counter reset by a successful output compare on channel 7. Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000. Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. See Table 7-15. 2:0 PR[2:0] Table 7-15. Prescaler Selection PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 327 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.12 R W Reset Main Timer Interrupt Flag 1 (TFLG1) 7 6 5 4 3 2 1 0 C7F 0 C6F 0 C5F 0 C4F 0 C3F 0 C2F 0 C1F 0 C0F 0 Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers, instead of generating an interrupt for every capture. Table 7-16. TFLG1 Field Descriptions Field 7:0 C[7:0]F Description Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be set by 8-bit pulse accumulators PAC3–PAC0. If the delay counter is enabled, the CxF flag will not be set until after the delay. MC9S12XDP512 Data Sheet, Rev. 2.17 328 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.13 R W Reset Main Timer Interrupt Flag 2 (TFLG2) 7 6 5 4 3 2 1 0 TOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-18. Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). Table 7-17. TFLG2 Field Descriptions Field 7 TOF Description Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 329 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.14 R W Reset Timer Input Capture/Output Compare Registers 0–7 15 14 13 12 11 10 9 8 Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-19. Timer Input Capture/Output Compare Register 0 High (TC0) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-20. Timer Input Capture/Output Compare Register 0 Low (TC0) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-21. Timer Input Capture/Output Compare Register 1 High (TC1) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-22. Timer Input Capture/Output Compare Register 1 Low (TC1) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-23. Timer Input Capture/Output Compare Register 2 High (TC2) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-24. Timer Input Capture/Output Compare Register 2 Low (TC2) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-25. Timer Input Capture/Output Compare Register 3 High (TC3) MC9S12XDP512 Data Sheet, Rev. 2.17 330 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-26. Timer Input Capture/Output Compare Register 3 Low (TC3) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-27. Timer Input Capture/Output Compare Register 4 High (TC4) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-28. Timer Input Capture/Output Compare Register 4 Low (TC4) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-29. Timer Input Capture/Output Compare Register 5 High (TC5) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-30. Timer Input Capture/Output Compare Register 5 Low (TC5) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-31. Timer Input Capture/Output Compare Register 6 High (TC6) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-32. Timer Input Capture/Output Compare Register 6 Low (TC6) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 331 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 15 14 13 12 11 10 9 8 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 7-33. Timer Input Capture/Output Compare Register 7 High (TC7) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 7-34. Timer Input Capture/Output Compare Register 7 Low (TC7) Read: Anytime Write anytime for output compare function. Writes to these registers have no meaning or effect during input capture. All bits reset to zero. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. 7.3.2.15 R W Reset 16-Bit Pulse Accumulator A Control Register (PACTL) 7 6 5 4 3 2 1 0 0 0 PAEN 0 PAMOD 0 PEDGE 0 CLK1 0 CLK0 0 PAOVI 0 PAI 0 = Unimplemented or Reserved Figure 7-35. 16-Bit Pulse Accumulator Control Register (PACTL) Read: Anytime Write: Anytime All bits reset to zero. Table 7-18. PACTL Field Descriptions Field 6 PAEN Description Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7. MC9S12XDP512 Data Sheet, Rev. 2.17 332 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-18. PACTL Field Descriptions (continued) Field 5 PAMOD 4 PEDGE Description Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 0 Event counter mode 1 Gated time accumulation mode Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Refer to Table 7-19. For PAMOD bit = 0 (event counter mode). 0 Falling edges on PT7 pin cause the count to be incremented 1 Rising edges on PT7 pin cause the count to be incremented For PAMOD bit = 1 (gated time accumulation mode). 0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag. 1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag. If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the timer prescaler. 3:2 CLK[1:0] Clock Select Bits — For the description of PACLK please refer to Figure 7-70. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. Refer to Table 7-20. Pulse Accumulator A Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAOVF is set Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PAIF is set 2 PAOVI 0 PAI . Table 7-19. Pin Action PAMOD 0 0 1 1 PEDGE 0 1 0 1 Falling edge Rising edge Divide by 64 clock enabled with pin high level Divide by 64 clock enabled with pin low level Pin Action Table 7-20. Clock Selection CLK1 0 0 1 1 CLK0 0 1 0 1 Clock Source Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 333 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.16 R W Reset Pulse Accumulator A Flag Register (PAFLG) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PAOVF 0 PAIF 0 = Unimplemented or Reserved Figure 7-36. Pulse Accumulator A Flag Register (PAFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). Table 7-21. PAFLG Field Descriptions Field 1 PAOVF Description Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000. When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by an active edge on PT3. 0 PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. 7.3.2.17 R W Reset Pulse Accumulators Count Registers (PACN3 and PACN2) 7 6 5 4 3 2 1 0 PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) 0 0 0 0 0 0 PACNT1(9) 0 PACNT0(8) 0 Figure 7-37. Pulse Accumulators Count Register 3 (PACN3) MC9S12XDP512 Data Sheet, Rev. 2.17 334 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7 6 5 4 3 2 1 0 R W Reset PACNT7 0 PACNT6 0 PACNT5 0 PACNT4 0 PACNT3 0 PACNT2 0 PACNT1 0 PACNT0 0 Figure 7-38. Pulse Accumulators Count Register 2 (PACN2) Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents are respectively the high and low byte of the PACA. When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word. When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. 7.3.2.18 R W Reset Pulse Accumulators Count Registers (PACN1 and PACN0) 7 6 5 4 3 2 1 0 PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) 0 0 0 0 0 0 PACNT1(9) 0 PACNT0(8) 0 Figure 7-39. Pulse Accumulators Count Register 1 (PACN1) 7 6 5 4 3 2 1 0 R W Reset PACNT7 0 PACNT6 0 PACNT5 0 PACNT4 0 PACNT3 0 PACNT2 0 PACNT1 0 PACNT0 0 Figure 7-40. Pulse Accumulators Count Register 0 (PACN0) Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 335 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word. When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. MC9S12XDP512 Data Sheet, Rev. 2.17 336 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.19 R W Reset 16-Bit Modulus Down-Counter Control Register (MCCTL) 7 6 5 4 3 2 1 0 MCZI 0 MODMC 0 RDMCL 0 0 ICLAT 0 0 FLMC 0 MCEN 0 MCPR1 0 MCPR0 0 Figure 7-41. 16-Bit Modulus Down-Counter Control Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero. Table 7-22. MCCTL Field Descriptions Field 7 MCZI 6 MODMC Modulus Counter Underflow Interrupt Enable 0 Modulus counter interrupt is disabled. 1 Modulus counter interrupt is enabled. Modulus Mode Enable 0 The modulus counter counts down from the value written to it and will stop at 0x0000. 1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest value written to the modulus count register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. Read Modulus Down-Counter Load 0 Reads of the modulus count register (MCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MCCNT) will return the contents of the load register. Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse accumulators will be automatically cleared when the latch action occurs. Writing zero to this bit has no effect. Read of this bit will always return zero. 3 FLMC Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus down-counter is enabled (MCEN = 1). A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets the modulus counter prescaler. Write zero to this bit has no effect. Read of this bit will return always zero. 2 MCEN Modulus Down-Counter Enable 0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 1 Modulus counter is enabled. Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Description 5 RDMCL 4 ICLAT 1:0 MCPR[1:0] MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 337 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-23. Modulus Counter Prescaler Select MCPR1 0 0 1 1 MCPR0 0 1 0 1 Prescaler Division 1 4 8 16 7.3.2.20 R W Reset 16-Bit Modulus Down-Counter FLAG Register (MCFLG) 7 6 5 4 3 2 1 0 MCZF 0 0 0 0 0 0 0 POLF3 0 POLF2 0 POLF1 0 POLF0 0 = Unimplemented or Reserved Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG) Read: Anytime Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. Table 7-24. MCFLG Field Descriptions Field 7 MCZF Description Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000. The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect. Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Each POLFx corresponds to a timer PORTx input. 0 The first input capture has been caused by a falling edge. 1 The first input capture has been caused by a rising edge. 3:0 POLF[3:0] MC9S12XDP512 Data Sheet, Rev. 2.17 338 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.21 R W Reset ICPAR — Input Control Pulse Accumulators Register (ICPAR) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PA3EN 0 PA2EN 0 PA1EN 0 PA0EN 0 = Unimplemented or Reserved Figure 7-43. Input Control Pulse Accumulators Register (ICPAR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN is set, PA1EN and PA0EN have no effect. Table 7-25. ICPAR Field Descriptions Field 3:0 PA[3:0]EN 8-Bit Pulse Accumulator ‘x’ Enable 0 8-Bit Pulse Accumulator is disabled. 1 8-Bit Pulse Accumulator is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 339 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.22 R W Reset Delay Counter Control Register (DLYCT) 7 6 5 4 3 2 1 0 DLY7 0 DLY6 0 DLY5 0 DLY4 0 DLY3 0 DLY2 0 DLY1 0 DLY0 0 Figure 7-44. Delay Counter Control Register (DLYCT) Read: Anytime Write: Anytime All bits reset to zero. Table 7-26. DLYCT Field Descriptions Field 7:0 DLY[7:0] Description Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to calculate the delay.Table 7-27 shows the delay settings in this case. When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay. Table 7-28 shows the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to narrow input pulses. Delay between two active edges of the input signal period should be longer than the selected counter delay. Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register TSCR1. Table 7-27. Delay Counter Select when PRNT = 0 DLY1 0 0 1 1 DLY0 0 1 0 1 Delay Disabled 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles Table 7-28. Delay Counter Select Examples when PRNT = 1 DLY7 0 0 0 0 0 0 0 0 0 0 0 0 1 DLY6 0 0 0 0 0 0 0 0 0 0 0 1 1 DLY5 0 0 0 0 0 0 0 0 0 0 1 1 1 DLY4 0 0 0 0 0 0 0 0 0 1 1 1 1 DLY3 0 0 0 0 0 0 0 0 1 1 1 1 1 DLY2 0 0 0 0 1 1 1 1 1 1 1 1 1 DLY1 0 0 1 1 0 0 1 1 1 1 1 1 1 DLY0 0 1 0 1 0 1 0 1 1 1 1 1 1 Delay Disabled (bypassed) 8 bus clock cycles 12 bus clock cycles 16 bus clock cycles 20 bus clock cycles 24 bus clock cycles 28 bus clock cycles 32 bus clock cycles 64 bus clock cycles 128 bus clock cycles 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles MC9S12XDP512 Data Sheet, Rev. 2.17 340 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.23 R W Reset Input Control Overwrite Register (ICOVW) 7 6 5 4 3 2 1 0 NOVW7 0 NOVW6 0 NOVW5 0 NOVW4 0 NOVW3 0 NOVW2 0 NOVW1 0 NOVW0 0 Figure 7-45. Input Control Overwrite Register (ICOVW) Read: Anytime Write: Anytime All bits reset to zero. Table 7-29. ICOVW Field Descriptions Field 7:0 NOVW[7:0] Description No Input Capture Overwrite 0 The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 The related capture register or holding register cannot be written by an event unless they are empty (see Section 7.4.1.1, “IC Channels”). This will prevent the captured value being overwritten until it is read or latched in the holding register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 341 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.24 R W Reset Input Control System Control Register (ICSYS) 7 6 5 4 3 2 1 0 SH37 0 SH26 0 SH15 0 SH04 0 TFMOD 0 PACMX 0 BUFEN 0 LATQ 0 Figure 7-46. Input Control System Register (ICSYS) Read: Anytime Write: Once in normal modes All bits reset to zero. Table 7-30. ICSYS Field Descriptions Field 7:4 SHxy Description Share Input action of Input Capture Channels x and y 0 Normal operation 1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge detector is used to be active on the channel ‘y’. Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture. By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers are emptied, an input capture event will first update the related input capture register with the main timer contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on PTx. 0 The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin occurs. 1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 are set only when a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are set the same way as for TFMOD = 0. 8-Bit Pulse Accumulators Maximum Count 0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge, it will be incremented to 0x0000. 1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value 0x00FF indicates a count of 255 or more. IC Buffer Enable 0 Input capture and pulse accumulator holding registers are disabled. 1 Input capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ control bit. 3 TFMOD 2 PACMX 1 BUFFEN MC9S12XDP512 Data Sheet, Rev. 2.17 342 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-30. ICSYS Field Descriptions (continued) Field 0 LATQ Description Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers. 0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. 1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is written into the count register MCCNT (see Section 7.4.1.1.2, “Buffered IC Channels”). With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared. 7.3.2.25 R W Reset Precision Timer Prescaler Select Register (PTPSR) 7 6 5 4 3 2 1 0 PTPS7 0 PTPS6 0 PTPS5 0 PTPS4 0 PTPS3 0 PTPS2 0 PTPS1 0 PTPS0 0 Figure 7-47. Precision Timer Prescaler Select Register (PTPSR) Read: Anytime Write: Anytime All bits reset to zero. Table 7-31. PTPSR Field Descriptions Field 7:0 PTPS[7:0] Description Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 7-32 shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. Table 7-32. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 0 0 0 0 0 0 0 PTPS6 0 0 0 0 0 0 0 PTPS5 0 0 0 0 0 0 0 PTPS4 0 0 0 0 0 0 0 PTPS3 0 0 0 0 0 0 0 PTPS2 0 0 0 0 1 1 1 PTPS1 0 0 1 1 0 0 1 PTPS0 0 1 0 1 0 1 0 Prescale Factor 1 2 3 4 5 6 7 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 343 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-32. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 0 0 0 0 0 1 PTPS6 0 0 0 0 1 1 PTPS5 0 0 0 1 1 1 PTPS4 0 0 1 1 1 1 PTPS3 0 1 1 1 1 1 PTPS2 1 1 1 1 1 1 PTPS1 1 1 1 1 1 1 PTPS0 1 1 1 1 1 1 Prescale Factor 8 16 32 64 128 256 7.3.2.26 R W Reset Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) 7 6 5 4 3 2 1 0 PTMPS7 0 PTMPS6 0 PTMPS5 0 PTMPS4 0 PTMPS3 0 PTMPS2 0 PTMPS1 0 PTMPS0 0 Figure 7-48. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR) Read: Anytime Write: Anytime All bits reset to zero. Table 7-33. PTMCPSR Field Descriptions Field Description 7:0 Precision Timer Modulus Counter Prescaler Select Bits — These eight bits specify the division rate of the PTMPS[7:0] modulus counter prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 7-34 shows some possible division rates. The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs. Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 PTMPS7 0 0 0 0 0 0 0 PTMPS6 0 0 0 0 0 0 0 PTMPS5 0 0 0 0 0 0 0 PTMPS4 0 0 0 0 0 0 0 PTMPS3 0 0 0 0 0 0 0 PTMPS2 0 0 0 0 1 1 1 PTMPS1 0 0 1 1 0 0 1 PTMPS0 0 1 0 1 0 1 0 Prescaler Division Rate 1 2 3 4 5 6 7 MC9S12XDP512 Data Sheet, Rev. 2.17 344 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued) PTMPS7 0 0 0 0 0 1 PTMPS6 0 0 0 0 1 1 PTMPS5 0 0 0 1 1 1 PTMPS4 0 0 1 1 1 1 PTMPS3 0 1 1 1 1 1 PTMPS2 1 1 1 1 1 1 PTMPS1 1 1 1 1 1 1 PTMPS0 1 1 1 1 1 1 Prescaler Division Rate 8 16 32 64 128 256 7.3.2.27 R W Reset 16-Bit Pulse Accumulator B Control Register (PBCTL) 7 6 5 4 3 2 1 0 0 0 PBEN 0 0 0 0 0 0 0 0 0 PBOVI 0 0 0 = Unimplemented or Reserved Figure 7-49. 16-Bit Pulse Accumulator B Control Register (PBCTL) Read: Anytime Write: Anytime All bits reset to zero. Table 7-35. PBCTL Field Descriptions Field 6 PBEN Description Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless pulse accumulator is disabled. 0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set. 1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. PA1EN and PA0EN control bits in ICPAR have no effect. The PACB shares the input pin with IC0. Pulse Accumulator B Overflow Interrupt Enable 0 Interrupt inhibited 1 Interrupt requested if PBOVF is set 1 PBOVI MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 345 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.28 R W Reset Pulse Accumulator B Flag Register (PBFLG) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PBOVF 0 0 0 = Unimplemented or Reserved Figure 7-50. Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit. NOTE When TFFCA = 1, the flag cannot be cleared via the normal flag clearing mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”. All bits reset to zero. PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”). Table 7-36. PBFLG Field Descriptions Field 1 PBOVF Description Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from 0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000. When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active edge follows on PT1. MC9S12XDP512 Data Sheet, Rev. 2.17 346 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.29 R W Reset 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) 7 6 5 4 3 2 1 0 PA3H7 0 PA3H6 0 PA3H5 0 PA3H4 0 PA3H3 0 PA3H2 0 PA3H1 0 PA3H0 0 = Unimplemented or Reserved Figure 7-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H) 7 6 5 4 3 2 1 0 R W Reset PA2H7 0 PA2H6 0 PA2H5 0 PA2H4 0 PA2H3 0 PA2H2 0 PA2H1 0 PA2H0 0 = Unimplemented or Reserved Figure 7-52. 8-Bit Pulse Accumulators Holding Register 2 (PA2H) 7 6 5 4 3 2 1 0 R W Reset PA1H7 0 PA1H6 0 PA1H5 0 PA1H4 0 PA1H3 0 PA1H2 0 PA1H1 0 PA1H0 0 = Unimplemented or Reserved Figure 7-53. 8-Bit Pulse Accumulators Holding Register 1 (PA1H) 7 6 5 4 3 2 1 0 R W Reset PA0H7 0 PA0H6 0 PA0H5 0 PA0H4 0 PA0H3 0 PA0H2 0 PA0H1 0 PA0H0 0 = Unimplemented or Reserved Figure 7-54. 8-Bit Pulse Accumulators Holding Register 0 (PA0H) Read: Anytime. Write: Has no effect. All bits reset to zero. These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR are enabled (see Section 7.4.1.3, “Pulse Accumulators”). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 347 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.30 R W Reset Modulus Down-Counter Count Register (MCCNT) 15 14 13 12 11 10 9 8 MCCNT15 1 MCCNT14 1 MCCNT13 1 MCCNT12 1 MCCNT11 1 MCCNT10 1 MCCNT9 1 MCCNT8 1 Figure 7-55. Modulus Down-Counter Count Register High (MCCNT) 7 6 5 4 3 2 1 0 R W Reset MCCNT7 1 MCCNT6 1 MCCNT5 1 MCCNT4 1 MCCNT3 1 MCCNT2 1 MCCNT1 1 MCCNT9 1 Figure 7-56. Modulus Down-Counter Count Register Low (MCCNT) Read: Anytime Write: Anytime. All bits reset to one. A full access for the counter register will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give different results than accessing them as a word. If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load register. If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture and pulse accumulator registers will be latched. With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register. If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write to MCCNT will update the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and will immediately update the counter register with the value written to it and down-counts to 0x0000 and stops. The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an immediate load is desired. MC9S12XDP512 Data Sheet, Rev. 2.17 348 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.31 R W Reset Timer Input Capture Holding Registers 0–3 (TCxH) 15 14 13 12 11 10 9 8 TC15 0 TC14 0 TC13 0 TC12 0 TC11 0 TC10 0 TC9 0 TC8 0 = Unimplemented or Reserved Figure 7-57. Timer Input Capture Holding Register 0 High (TC0H) 7 6 5 4 3 2 1 0 R W Reset TC7 0 TC6 0 TC5 0 TC4 0 TC3 0 TC2 0 TC1 0 TC0 0 = Unimplemented or Reserved Figure 7-58. Timer Input Capture Holding Register 0 Low (TC0H) 15 14 13 12 11 10 9 8 R W Reset TC15 0 TC14 0 TC13 0 TC12 0 TC11 0 TC10 0 TC9 0 TC8 0 = Unimplemented or Reserved Figure 7-59. Timer Input Capture Holding Register 1 High (TC1H) 7 6 5 4 3 2 1 0 R W Reset TC7 0 TC6 0 TC5 0 TC4 0 TC3 0 TC2 0 TC1 0 TC0 0 = Unimplemented or Reserved Figure 7-60. Timer Input Capture Holding Register 1 Low (TC1H) 15 14 13 12 11 10 9 8 R W Reset TC15 0 TC14 0 TC13 0 TC12 0 TC11 0 TC10 0 TC9 0 TC8 0 = Unimplemented or Reserved Figure 7-61. Timer Input Capture Holding Register 2 High (TC2H) 7 6 5 4 3 2 1 0 R W Reset TC7 0 TC6 0 TC5 0 TC4 0 TC3 0 TC2 0 TC1 0 TC0 0 = Unimplemented or Reserved Figure 7-62. Timer Input Capture Holding Register 2 Low (TC2H) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 349 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 15 14 13 12 11 10 9 8 R W Reset TC15 0 TC14 0 TC13 0 TC12 0 TC11 0 TC10 0 TC9 0 TC8 0 = Unimplemented or Reserved Figure 7-63. Timer Input Capture Holding Register 3 High (TC3H) 7 6 5 4 3 2 1 0 R W Reset TC7 0 TC6 0 TC5 0 TC4 0 TC3 0 TC2 0 TC1 0 TC0 0 = Unimplemented or Reserved Figure 7-64. Timer Input Capture Holding Register 3 Low (TC3H) Read: Anytime Write: Has no effect. All bits reset to zero. These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding IOSx bits in TIOS should be cleared (see Section 7.4.1.1, “IC Channels”). 7.4 Functional Description This section provides a complete functional description of the ECT block, detailing the operation of the design from the end user perspective in a number of subsections. MC9S12XDP512 Data Sheet, Rev. 2.17 350 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) ÷ 1, 2, ..., 128 Bus Clock Timer Prescaler 16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock ÷ 1, 4, 8, 16 Modulus Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET Underflow RESET RESET RESET LATCH P0 Pin Logic Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. 0 P2 Pin Logic Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PA2H Hold Reg. 0 P3 Pin Logic PAC3 TC3H Hold Reg. PA3H Hold Reg. P4 Pin Logic Comparator EDG4 EDG0 SH04 Comparator EDG5 EDG1 SH15 Comparator EDG6 EDG2 SH26 Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. MUX TC6 Capture/Compare Reg. MUX TC5 Capture/Compare Reg. Write 0x0000 to Modulus Counter MUX TC4 Capture/Compare Reg. ICLAT, LATQ, BUFEN (Force Latch) P5 Pin Logic P6 Pin Logic LATQ (MDC Latch Enable) P7 Pin Logic Figure 7-65. Detailed Timer Block Diagram in Latch Mode when PRNT = 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 351 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) ÷ 1, 2,3, ..., 256 Bus Clock Timer Prescaler 16-Bit Free-Running 16 BITMain Timer MAIN TIMER Bus Clock ÷ 1, 2,3, ..., 256 Modulus Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET Underflow RESET RESET RESET LATCH P0 Pin Logic Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 8, 12, 16, ..., 1024 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 8, 12, 16, ..., 1024 TC1H Hold Reg. PA1H Hold Reg. 0 P2 Pin Logic Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 8, 12, 16, ..., 1024 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PAC3 PA2H Hold Reg. 0 P3 Pin Logic 8, 12, 16, ..., 1024 TC3H Hold Reg. PA3H Hold Reg. P4 Pin Logic Comparator EDG4 EDG0 SH04 Comparator EDG5 EDG1 SH15 Comparator EDG6 EDG2 SH26 Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. MUX TC6 Capture/Compare Reg. MUX TC5 Capture/Compare Reg. Write 0x0000 to Modulus Counter MUX TC4 Capture/Compare Reg. ICLAT, LATQ, BUFEN (Force Latch) P5 Pin Logic P6 Pin Logic LATQ (MDC Latch Enable) P7 Pin Logic Figure 7-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 1 MC9S12XDP512 Data Sheet, Rev. 2.17 352 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Bus Clock ÷1, 2, ..., 128 Timer Prescaler 16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock ÷ 1, 4, 8, 16 Modulus Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter 0 RESET P0 Pin Logic Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 LATCH0 LATCH3 LATCH2 LATCH1 TC0H Hold Reg. Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PA0H Hold Reg. 0 RESET P1 Pin Logic PAC1 TC1H Hold Reg. Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PA1H Hold Reg. 0 RESET P2 Pin Logic PAC2 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PA2H Hold Reg. 0 RESET P3 Pin Logic PAC3 TC3H Hold Reg. Comparator EDG4 EDG0 MUX SH04 P5 Pin Logic Comparator EDG5 EDG1 MUX SH15 P6 Pin Logic Comparator EDG6 EDG2 MUX SH26 P7 Pin Logic Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. TC6 Capture/Compare Reg. TC5 Capture/Compare Reg. TC4 Capture/Compare Reg. PA3H Hold Reg. P4 Pin Logic LATQ, BUFEN (Queue Mode) Read TC3H Hold Reg. Read TC2H Hold Reg. Read TC1H Hold Reg. Read TC0H Hold Reg. Figure 7-67. Detailed Timer Block Diagram in Queue Mode when PRNT = 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 353 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) ÷1, 2, 3, ... 256 Bus Clock Timer Prescaler 16-Bit Free-Running 16 BIT MAIN TIMER Main Timer Bus Clock ÷ 1, 2, 3, ... 256 Modulus Prescaler 0 P0 Pin Logic Comparator Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 LATCH0 LATCH3 LATCH2 LATCH1 16-Bit Load Register 16-Bit Modulus Down Counter RESET 8, 12, 16, ... 1024 TC0H Hold Reg. Comparator Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 PA0H Hold Reg. 0 P1 Pin Logic RESET 8, 12, 16, ... 1024 TC1H Hold Reg. Comparator Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 PA1H Hold Reg. 0 P2 Pin Logic RESET 8, 12, 16, ... 1024 TC2H Hold Reg. Comparator Delay Counter EDG3 TC3 Capture/Compare Reg. PAC3 PA2H Hold Reg. 0 P3 Pin Logic RESET 8, 12, 16, ... 1024 TC3H Hold Reg. Comparator EDG4 EDG0 MUX SH04 P5 Pin Logic Comparator EDG5 EDG1 MUX SH15 P6 Pin Logic Comparator EDG6 EDG2 MUX SH26 P7 Pin Logic Comparator EDG7 EDG3 SH37 MUX TC7 Capture/Compare Reg. Read TC0H Hold Reg. TC6 Capture/Compare Reg. Read TC1H Hold Reg. Read TC2H Hold Reg. TC5 Capture/Compare Reg. TC4 Capture/Compare Reg. PA3H Hold Reg. P4 Pin Logic LATQ, BUFEN (Queue Mode) Read TC3H Hold Reg. Figure 7-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 1 MC9S12XDP512 Data Sheet, Rev. 2.17 354 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Load Holding Register and Reset Pulse Accumulator 0 EDG0 P0 Edge Detector Delay Counter 8-Bit PAC0 (PACN0) 8, 12,16, ..., 1024 PA0H Holding Register Interrupt 8, 12,16, ..., 1024 EDG1 P1 Edge Detector Delay Counter 0 8-Bit PAC1 (PACN1) PA1H Holding Register 8, 12,16, ..., 1024 EDG2 P2 Edge Detector Delay Counter 0 8-Bit PAC2 (PACN2) PA2H Holding Register Interrupt 8, 12,16, ..., 1024 P3 Edge Detector Delay Counter 0 EDG3 8-Bit PAC3 (PACN3) PA3H Holding Register Figure 7-69. 8-Bit Pulse Accumulators Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 355 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) TIMCLK (Timer Clock) CLK1 CLK0 4:1 MUX PACLK / 65536 PACLK / 256 Prescaled Clock (PCLK) Clock Select (PAMOD) PACLK Edge Detector P7 Interrupt 8-Bit PAC3 (PACN3) PACA 8-Bit PAC2 (PACN2) MUX Divide by 64 Bus Clock Interrupt 8-Bit PAC1 (PACN1) PACB 8-Bit PAC0 (PACN0) Delay Counter Edge Detector P0 Figure 7-70. 16-Bit Pulse Accumulators Block Diagram 16-Bit Main Timer Px Edge Detector Delay Counter TCx Input Capture Register Set CxF Interrupt TCxH I.C. Holding Register BUFEN • LATQ • TFMOD Figure 7-71. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A MC9S12XDP512 Data Sheet, Rev. 2.17 356 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called input capture (IC) channels. Four IC channels (channels 7–4) are the same as on the standard timer with one capture register each that memorizes the timer value captured by an action on the associated input pin. Four other IC channels (channels 3–0), in addition to the capture register, also have one buffer each called a holding register. This allows two different timer values to be saved without generating any interrupts. Four 8-bit pulse accumulators are associated with the four buffered IC channels (channels 3–0). Each pulse accumulator has a holding register to memorize their value by an action on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator. The 16-bit modulus down-counter can control the transfer of the IC registers and the pulse accumulators contents to the respective holding registers for a given period, every time the count reaches zero. The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability. 7.4.1.1 IC Channels The IC channels are composed of four standard IC registers and four buffered IC channels. • An IC register is empty when it has been read or latched into the holding register. • A holding register is empty when it has been read. 7.4.1.1.1 Non-Buffered IC Channels The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty. This will prevent the captured value from being overwritten until it is read. 7.4.1.1.2 Buffered IC Channels There are two modes of operations for the buffered IC channels: 1. IC latch mode (LATQ = 1) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 7-65 and Figure 7-66). The value of the buffered IC register is latched to its holding register by the modulus counter for a given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write to ICLAT in the MCCTL register. If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. In case of latching, the contents of its holding register are overwritten. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 357 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 7.4.1.1, “IC Channels”). This will prevent the captured value from being overwritten until it is read or latched in the holding register. 2. IC Queue Mode (LATQ = 0) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 7-67 and Figure 7-68). If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 7.4.1.1, “IC Channels”). In queue mode, reads of the holding register will latch the corresponding pulse accumulator value to its holding register. 7.4.1.1.3 Delayed IC Channels There are four delay counters in this module associated with IC channels 0–3. The use of this feature is explained in the diagram and notes below. BUS CLOCK DLY_CNT INPUT ON CH0–3 INPUT ON CH0–3 INPUT ON CH0–3 INPUT ON CH0–3 0 1 2 3 253 254 255 256 Rejected 255 Cycles Rejected 255.5 Cycles 255.5 Cycles Accepted 256 Cycles Accepted Figure 7-72. Channel Input Validity with Delay Counter Feature In Figure 7-72 a delay counter value of 256 bus cycles is considered. 1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected. 2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or accepted, depending on their relative alignment with the sample points. 4. Input pulses with a duration of DLY_CNT or longer are accepted. MC9S12XDP512 Data Sheet, Rev. 2.17 358 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1.2 OC Channel Initialization Internal register whose output drives OCx when TIOS is set, can be force loaded with a desired data by writing to CFORC register before OCx is configured for output compare action. This allows a glitch free switch over of port from general purpose I/O to timer output once the output compare is enabled. 7.4.1.3 Pulse Accumulators There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels 3–0. A pulse accumulator counts the number of active edges at the input of its channel. The minimum pulse width for the PAI input is greater than two bus clocks.The maximum input frequency on the pulse accumulator channel is one half the bus frequency or Eclk. The user can prevent the 8-bit pulse accumulators from counting further than 0x00FF by utilizing the PACMX control bit in the ICSYS register. In this case, a value of 0x00FF means that 255 counts or more have occurred. Each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see Figure 7-70). To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output compare 7 and 0 respectively, the user must set the corresponding bits: IOSx = 1, OMx = 0, and OLx = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared. There are two modes of operation for the pulse accumulators: • Pulse accumulator latch mode The value of the pulse accumulator is transferred to its holding register when the modulus down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control bit ICLAT is written. At the same time the pulse accumulator is cleared. • Pulse accumulator queue mode When queue mode is enabled, reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its holding register. At the same time the pulse accumulator is cleared. 7.4.1.4 Modulus Down-Counter The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers. The action of latching can be programmed to be periodic or only once. 7.4.1.5 Precision Timer By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter and enhance delay counter settings compared to the settings in the present ECT timer. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 359 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1.6 Flag Clearing Mechanisms The flags in the ECT can be cleared one of two ways: 1. Normal flag clearing mechanism (TFFCA = 0) Any of the ECT flags can be cleared by writing a one to the flag. 2. Fast flag clearing mechanism (TFFCA = 1) With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing the various registers associated with the ECT modes of operation as described below. The flags cannot be cleared via the normal flag clearing mechanism. This fast flag clearing mechanism has the advantage of eliminating the software overhead required by a separate clear sequence. Extra care must be taken to avoid accidental flag clearing due to unintended accesses. — Input capture A read from an input capture channel register causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. — Output compare A write to the output compare channel register causes the corresponding channel flag, CxF, to be cleared in the TFLG1 register. — Timer counter Any access to the TCNT register clears the TOF flag in the TFLG2 register. — Pulse accumulator A Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the PAFLG register. — Pulse accumulator B Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register. — Modulus down counter Any access to the MCCNT register clears the MCZF flag in the MCFLG register. 7.4.2 Reset The reset state of each individual bit is listed within the register description section (Section 7.3, “Memory Map and Register Definition”) which details the registers and their bit-fields. MC9S12XDP512 Data Sheet, Rev. 2.17 360 Freescale Semiconductor Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. Table 7-37 lists the interrupts generated by the ECT to communicate with the MCU. Table 7-37. ECT Interrupts Interrupt Source Timer channel 7–0 Modulus counter underflow Pulse accumulator B overflow Pulse accumulator A input Pulse accumulator A overflow Timer overflow Description Active high timer channel interrupts 7–0 Active high modulus counter interrupt Active high pulse accumulator B interrupt Active high pulse accumulator A input interrupt Pulse accumulator overflow interrupt Timer 0verflow interrupt The ECT only originates interrupt requests. The following is a description of how the module makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. 7.4.3.1 Channel [7:0] Interrupt This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be serviced by the system controller. 7.4.3.2 Modulus Counter Interrupt This active high output will be asserted by the module to request a modulus counter underflow interrupt to be serviced by the system controller. 7.4.3.3 Pulse Accumulator B Overflow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller. 7.4.3.4 Pulse Accumulator A Input Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A input interrupt to be serviced by the system controller. 7.4.3.5 Pulse Accumulator A Overflow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller. 7.4.3.6 Timer Overflow Interrupt This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 361 Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 362 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1 Introduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel. Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs. 8.1.1 Features The PWM block includes these distinctive features: • Eight independent PWM channels with programmable period and duty cycle • Dedicated counter for each PWM channel • Programmable PWM enable/disable for each channel • Software selection of PWM duty pulse polarity for each channel • Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled. • Programmable center or left aligned outputs on individual channels • Eight 8-bit channel or four 16-bit channel PWM resolution • Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies • Programmable clock select logic • Emergency shutdown 8.1.2 Modes of Operation There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 363 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1.3 Block Diagram Figure 8-1 shows the block diagram for the 8-bit 8-channel PWM block. PWM8B8C PWM Channels Channel 7 Period and Duty Channel 6 Counter PWM7 PWM6 Counter Bus Clock Clock Select PWM Clock Period and Duty Channel 5 Period and Duty Control Channel 4 Period and Duty Counter Counter PWM5 PWM4 Channel 3 Enable Period and Duty Counter PWM3 Polarity Channel 2 Period and Duty Counter PWM2 Alignment Channel 1 Period and Duty Channel 0 Period and Duty Counter Counter PWM1 PWM0 Figure 8-1. PWM Block Diagram 8.2 External Signal Description The PWM module has a total of 8 external pins. 8.2.1 PWM7 — PWM Channel 7 This pin serves as waveform output of PWM channel 7 and as an input for the emergency shutdown feature. 8.2.2 PWM6 — PWM Channel 6 This pin serves as waveform output of PWM channel 6. MC9S12XDP512 Data Sheet, Rev. 2.17 364 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.2.3 PWM5 — PWM Channel 5 This pin serves as waveform output of PWM channel 5. 8.2.4 PWM4 — PWM Channel 4 This pin serves as waveform output of PWM channel 4. 8.2.5 PWM3 — PWM Channel 3 This pin serves as waveform output of PWM channel 3. 8.2.6 PWM3 — PWM Channel 2 This pin serves as waveform output of PWM channel 2. 8.2.7 PWM3 — PWM Channel 1 This pin serves as waveform output of PWM channel 1. 8.2.8 PWM3 — PWM Channel 0 This pin serves as waveform output of PWM channel 0. 8.3 Memory Map and Register Definition This section describes in detail all the registers and register bits in the PWM module. The special-purpose registers and register bit functions that are not normally available to device end users, such as factory test control registers and reserved registers, are clearly identified by means of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions. 8.3.1 Module Memory Map This section describes the content of the registers in the PWM module. The base address of the PWM module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The figure below shows the registers associated with the PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. . MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 365 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 8.3.2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module. Register Name PWME R W PWMPOL R W PWMCLK R W PWMPRCLK R W PWMCAE R W PWMCTL R W PWMTST1 R W PWMPRSC1 R W PWMSCLA R W PWMSCLB R W PWMSCNTA R 1 Bit 7 PWME7 6 PWME6 5 PWME5 4 PWME4 3 PWME3 2 PWME2 1 PWME1 Bit 0 PWME0 PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 PCLK7 0 PCLKL6 PCLK5 PCLK4 PCLK3 0 PCLK2 PCLK1 PCLK0 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 0 CAE0 0 CON67 0 CON45 0 CON23 0 CON01 0 PSWAI 0 PFRZ 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 W 0 0 0 0 0 0 0 0 PWMSCNTB R 1 W = Unimplemented or Reserved Figure 8-2. PWM Register Summary (Sheet 1 of 3) MC9S12XDP512 Data Sheet, Rev. 2.17 366 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Register Name PWMCNT0 R W PWMCNT1 R W PWMCNT2 R W PWMCNT3 R W PWMCNT4 R W PWMCNT5 R W PWMCNT6 R W PWMCNT7 R W PWMPER0 R W PWMPER1 R W PWMPER2 R W PWMPER3 R W PWMPER4 R W PWMPER5 R W PWMPER6 R W Bit 7 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 6 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 5 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 4 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 3 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 2 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 8-2. PWM Register Summary (Sheet 2 of 3) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 367 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Register Name PWMPER7 R W PWMDTY0 R W PWMDTY1 R W PWMDTY2 R W PWMDTY3 R W PWMDTY4 R W PWMDTY5 R W PWMDTY6 R W PWMDTY7 R W PWMSDN R W Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 0 PWMRSTRT 4 3 0 2 PWM7IN 1 Bit 0 PWMIF PWMIE PWMLVL PWM7INL PWM7ENA = Unimplemented or Reserved Figure 8-2. PWM Register Summary (Sheet 3 of 3) 1 Intended for factory test purposes only. 8.3.2.1 PWM Enable Register (PWME) Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the MC9S12XDP512 Data Sheet, Rev. 2.17 368 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts off for power savings. 7 6 5 4 3 2 1 0 R W Reset PWME7 0 PWME6 0 PWME5 0 PWME4 0 PWME3 0 PWME2 0 PWME1 0 PWME0 0 Figure 8-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime Table 8-1. PWME Field Descriptions Field 7 PWME7 Description Pulse Width Channel 7 Enable 0 Pulse width channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle. Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled. 1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled. Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled. 1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle. Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled. 1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled. Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled. Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled. 6 PWME6 5 PWME5 4 PWME4 3 PWME3 2 PWME2 1 PWME1 0 PWME0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 369 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.3.2.2 PWM Polarity Register (PWMPOL) The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. 7 6 5 4 3 2 1 0 R W Reset PPOL7 0 PPOL6 0 PPOL5 0 PPOL4 0 PPOL3 0 PPOL2 0 PPOL1 0 PPOL0 0 Figure 8-4. PWM Polarity Register (PWMPOL) Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition Table 8-2. PWMPOL Field Descriptions Field 7–0 PPOL[7:0] Description Pulse Width Channel 7–0 Polarity Bits 0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is reached. 1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is reached. 8.3.2.3 PWM Clock Select Register (PWMCLK) Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. 7 6 5 4 3 2 1 0 R W Reset PCLK7 0 PCLKL6 0 PCLK5 0 PCLK4 0 PCLK3 0 PCLK2 0 PCLK1 0 PCLK0 0 Figure 8-5. PWM Clock Select Register (PWMCLK) Read: Anytime Write: Anytime MC9S12XDP512 Data Sheet, Rev. 2.17 370 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 8-3. PWMCLK Field Descriptions Field 7 PCLK7 6 PCLK6 5 PCLK5 4 PCLK4 3 PCLK3 2 PCLK2 1 PCLK1 0 PCLK0 Description Pulse Width Channel 7 Clock Select 0 Clock B is the clock source for PWM channel 7. 1 Clock SB is the clock source for PWM channel 7. Pulse Width Channel 6 Clock Select 0 Clock B is the clock source for PWM channel 6. 1 Clock SB is the clock source for PWM channel 6. Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3. 1 Clock SB is the clock source for PWM channel 3. Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0. 8.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK) This register selects the prescale clock source for clocks A and B independently. 7 6 5 4 3 2 1 0 R W Reset 0 0 PCKB2 0 PCKB1 0 PCKB0 0 0 0 PCKA2 0 PCKA1 0 PCKA0 0 = Unimplemented or Reserved Figure 8-6. PWM Prescale Clock Select Register (PWMPRCLK) Read: Anytime Write: Anytime MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 371 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 8-4. PWMPRCLK Field Descriptions Field 6–4 PCKB[2:0] 2–0 PCKA[2:0] s Description Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in Table 8-5. Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or 5. These three bits determine the rate of clock A, as shown in Table 8-6. Table 8-5. Clock B Prescaler Selects PCKB2 0 0 0 0 1 1 1 1 PCKB1 0 0 1 1 0 0 1 1 PCKB0 0 1 0 1 0 1 0 1 Value of Clock B Bus clock Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 Bus clock / 128 Table 8-6. Clock A Prescaler Selects PCKA2 0 0 0 0 1 1 1 1 PCKA1 0 0 1 1 0 0 1 1 PCKA0 0 1 0 1 0 1 0 1 Value of Clock A Bus clock Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16 Bus clock / 32 Bus clock / 64 Bus clock / 128 8.3.2.5 PWM Center Align Enable Register (PWMCAE) The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See Section 8.4.2.5, “Left Aligned Outputs” and Section 8.4.2.6, “Center Aligned Outputs” for a more detailed description of the PWM output modes. 7 6 5 4 3 2 1 0 R W Reset CAE7 0 CAE6 0 CAE5 0 CAE4 0 CAE3 0 CAE2 0 CAE1 0 CAE0 0 Figure 8-7. PWM Center Align Enable Register (PWMCAE) MC9S12XDP512 Data Sheet, Rev. 2.17 372 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. Table 8-7. PWMCAE Field Descriptions Field 7–0 CAE[7:0] Description Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode. 8.3.2.6 PWM Control Register (PWMCTL) The PWMCTL register provides for various control of the PWM module. 7 6 5 4 3 2 1 0 R W Reset CON67 0 CON45 0 CON23 0 CON01 0 PSWAI 0 PFRZ 0 0 0 0 0 = Unimplemented or Reserved Figure 8-8. PWM Control Register (PWMCTL) Read: Anytime Write: Anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 8.4.2.7, “PWM 16-Bit Functions” for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 373 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Table 8-8. PWMCTL Field Descriptions Field 7 CON67 Description Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode, the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program flow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation. 6 CON45 5 CON23 4 CON01 3 PSWAI 2 PFREZ 8.3.2.7 Reserved Register (PWMTST) This register is reserved for factory testing of the PWM module and is not available in normal modes. MC9S12XDP512 Data Sheet, Rev. 2.17 374 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-9. Reserved Register (PWMTST) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. 8.3.2.8 Reserved Register (PWMPRSC) This register is reserved for factory testing of the PWM module and is not available in normal modes. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-10. Reserved Register (PWMPRSC) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. 8.3.2.9 PWM Scale A Register (PWMSCLA) PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 375 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 8-11. PWM Scale A Register (PWMSCLA) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value) 8.3.2.10 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 Figure 8-12. PWM Scale B Register (PWMSCLB) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value). 8.3.2.11 Reserved Registers (PWMSCNTx) The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 8-13. Reserved Registers (PWMSCNTx) Read: Always read $00 in normal modes Write: Unimplemented in normal modes MC9S12XDP512 Data Sheet, Rev. 2.17 376 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Writing to these registers when in special modes can alter the PWM functionality. 8.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see Section 8.4.2.5, “Left Aligned Outputs” and Section 8.4.2.6, “Center Aligned Outputs” for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, see Section 8.4.2.4, “PWM Timer Counters”. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. 7 6 5 4 3 2 1 0 R W Reset Bit 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0 Figure 8-14. PWM Channel Counter Registers (PWMCNTx) Read: Anytime Write: Anytime (any value written causes PWM counter to be reset to $00). 8.3.2.13 PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) • The channel is disabled MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 377 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. See Section 8.4.2.3, “PWM Period and Duty” for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: • • Left aligned output (CAEx = 0) PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For boundary case programming values, please refer to Section 8.4.2.8, “PWM Boundary Cases”. 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 8-15. PWM Channel Period Registers (PWMPERx) Read: Anytime Write: Anytime 8.3.2.14 PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) • The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. MC9S12XDP512 Data Sheet, Rev. 2.17 378 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 8.4.2.3, “PWM Period and Duty” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel: • Polarity = 0 (PPOL x =0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% • Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% For boundary case programming values, please refer to Section 8.4.2.8, “PWM Boundary Cases”. 7 6 5 4 3 2 1 0 R W Reset Bit 7 1 6 1 5 1 4 1 3 1 2 1 1 1 Bit 0 1 Figure 8-16. PWM Channel Duty Registers (PWMDTYx) Read: Anytime Write: Anytime 8.3.2.15 PWM Shutdown Register (PWMSDN) The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks. 7 6 5 4 3 2 1 0 R W Reset PWMIF 0 PWMIE 0 0 PWMRSTRT 0 PWMLVL 0 0 0 PWM7IN 0 PWM7INL 0 PWM7ENA 0 = Unimplemented or Reserved Figure 8-17. PWM Shutdown Register (PWMSDN) Read: Anytime Write: Anytime MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 379 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Table 8-9. PWMSDN Field Descriptions Field 7 PWMIF Description PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM7IN input. 1 Change on PWM7IN input PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted. 0 PWM interrupt is disabled. 1 PWM interrupt is enabled. 6 PWMIE 5 PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic PWMRSTRT 1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as “0”. 4 PWMLVL PWM Shutdown Output Level If active level as defined by the PWM7IN input, gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL. 0 PWM outputs are forced to 0 1 Outputs are forced to 1. PWM Channel 7 Input Status — This reflects the current status of the PWM7 pin. PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled (PWM7ENA = 1), this bit determines the active level of the PWM7channel. 0 Active level is low 1 Active level is high PWM Emergency Shutdown Enable — If this bit is logic 1, the pin associated with channel 7 is forced to input and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if PWM7ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled. 2 PWM7IN 1 PWM7INL 0 PWM7ENA 8.4 8.4.1 Functional Description PWM Clock Select There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 8-18 shows the four different clocks and how the scaled clocks are created. MC9S12XDP512 Data Sheet, Rev. 2.17 380 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.4.1.1 Prescale The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register. 8.4.1.2 Clock Scale The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 381 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock A Clock A/2, A/4, A/6,....A/512 M U X PCLK0 M U X Clock to PWM Ch 0 PCKA2 PCKA1 PCKA0 8-Bit Down Counter Count = 1 Load PWMSCLA M U X 2 4 8 16 32 64 128 DIV 2 Clock SA Clock to PWM Ch 1 PCLK1 M U X PCLK2 M U X PCLK3 Clock to PWM Ch 3 Clock to PWM Ch 2 Divide by Prescaler Taps: Clock B Clock B/2, B/4, B/6,....B/512 M U X PCLK4 Clock to PWM Ch 4 M U X 8-Bit Down Counter Count = 1 Load PWMSCLB DIV 2 Clock SB M U X PCLK5 M U X PCLK6 M U X PCLK7 Clock to PWM Ch 5 Clock to PWM Ch 6 Bus Clock PFRZ Freeze Mode Signal PWME7-0 PCKB2 PCKB1 PCKB0 Clock to PWM Ch 7 Prescale Scale Clock Select Figure 8-18. PWM Clock Select Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 382 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs. 8.4.1.3 Clock Select Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2, 3, 6, and 7 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 383 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown below in Figure 8-19 is the block diagram for the PWM timer. Clock Source 8-Bit Counter Gate (Clock Edge Sync) Up/Down Reset 8-bit Compare = T PWMDTYx R 8-bit Compare = PWMPERx PPOLx Q Q M U X M U X To Pin Driver PWMCNTx From Port PWMP Data Register Q Q T R CAEx PWMEx Figure 8-19. PWM Timer Channel Block Diagram 8.4.2.1 PWM Enable Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 8.4.2.7, “PWM 16-Bit Functions” for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. MC9S12XDP512 Data Sheet, Rev. 2.17 384 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 8.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. 8.4.2.3 PWM Period and Duty Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: • The effective period ends • The counter is written (counter resets to $00) • The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. 8.4.2.4 PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 8.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 8-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 8-19 and described in Section 8.4.2.5, “Left Aligned Outputs” and Section 8.4.2.6, “Center Aligned Outputs”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 385 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new “clean” PWM waveform without any “history” from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (see Section 8.4.2.5, “Left Aligned Outputs” and Section 8.4.2.6, “Center Aligned Outputs” for more details). Table 8-10. PWM Timer Counter Conditions Counter Clears ($00) When PWMCNTx register written to any value Effective period ends Counter Counts When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. Counter Stops When PWM channel is disabled (PWMEx = 0) 8.4.2.5 Left Aligned Outputs The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 8-19. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop, as shown in Figure 8-19, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 8.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. MC9S12XDP512 Data Sheet, Rev. 2.17 386 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 8-20. PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel. • PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx • PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) • Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 8-21. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 387 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 8-21. PWM Left Aligned Output Example Waveform 8.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 8-19. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described in Section 8.4.2.3, “PWM Period and Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx PWMPERx Period = PWMPERx*2 PWMDTYx PWMPERx Figure 8-22. PWM Center Aligned Output Waveform MC9S12XDP512 Data Sheet, Rev. 2.17 388 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. • PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx) • PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 389 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 8-23 is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 8-23. PWM Center Aligned Output Example Waveform 8.4.2.7 PWM 16-Bit Functions The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 8-24. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 8-24. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. MC9S12XDP512 Data Sheet, Rev. 2.17 390 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High PWMCNT6 Low PWCNT7 Period/Duty Compare PWM7 Clock Source 5 High PWMCNT4 Low PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High PWMCNT2 Low PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High PWMCNT0 Low PWCNT1 Period/Duty Compare PWM1 Figure 8-24. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 391 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 8-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 8-11. 16-bit Concatenation Mode Summary CONxx CON67 CON45 CON23 CON01 PWMEx PWME7 PWME5 PWME3 PWME1 PPOLx PPOL7 PPOL5 PPOL3 PPOL1 PCLKx PCLK7 PCLK5 PCLK3 PCLK1 CAEx CAE7 CAE5 CAE3 CAE1 PWMx Output PWM7 PWM5 PWM3 PWM1 8.4.2.8 PWM Boundary Cases Table 8-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation). Table 8-12. PWM Boundary Cases PWMDTYx $00 (indicates no duty) $00 (indicates no duty) XX XX >= PWMPERx >= PWMPERx 1 PWMPERx >$00 >$00 $001 (indicates no period) $001 (indicates no period) XX XX PPOLx 1 0 1 0 1 0 PWMx Output Always low Always high Always high Always low Always high Always low Counter = $00 and does not count. 8.5 Resets The reset state of each individual bit is listed within the Section 8.3.2, “Register Descriptions” which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. • The 8-bit up/down counter is configured as an up counter out of reset. • All the channels are disabled and all the counters do not count. MC9S12XDP512 Data Sheet, Rev. 2.17 392 Freescale Semiconductor Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active. In stop mode or wait mode (with the PSWAI bit set), the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set. A description of the registers involved and affected due to this interrupt is explained in Section 8.3.2.15, “PWM Shutdown Register (PWMSDN)”. The PWM block only generates the interrupt and does not service it. The interrupt signal name is PWM interrupt signal. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 393 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev. 2.17 394 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 9.1.1 Features The IIC module has the following key features: • Compatible with I2C bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 395 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 9.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 9-1. IIC Start Stop Arbitration Control Registers Interrupt Clock Control In/Out Data Shift Register SCL bus_clock SDA Address Compare Figure 9-1. IIC Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 396 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.2 External Signal Description The IICV2 module has two external pins. 9.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 9.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 9.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers for the IIC module. 9.3.1 Module Memory Map The memory map for the IIC module is given below in Table 1-1. The address listed for each register is the address offset.The total address for each register is the sum of the base address for the IIC module and the address offset for each register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 397 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. Register Name IBAD R W IBFD R W IBCR R W IBSR R W IBDR R W D7 D6 D5 Bit 7 ADR7 6 ADR6 5 ADR5 4 ADR4 3 ADR3 2 ADR2 1 ADR1 Bit 0 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 0 IBC1 0 IBC0 IBEN TCF IBIE IAAS MS/SL IBB Tx/Rx TXAK 0 RSTA SRW IBIF IBSWAI RXAK IBAL D4 D3 D2 D1 D0 = Unimplemented or Reserved Figure 9-2. IIC Register Summary 9.3.2.1 IIC Address Register (IBAD) 7 6 5 4 3 2 1 0 R ADR7 W Reset 0 0 0 0 0 0 0 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 0 = Unimplemented or Reserved Figure 9-3. IIC Bus Address Register (IBAD) Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. Table 9-1. IBAD Field Descriptions Field 7:1 ADR[7:1] 0 Reserved Description Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0. MC9S12XDP512 Data Sheet, Rev. 2.17 398 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.3.2.2 IIC Frequency Divider Register (IBFD) 7 6 5 4 3 2 1 0 R IBC7 W Reset 0 0 0 0 0 0 0 0 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 = Unimplemented or Reserved Figure 9-4. IIC Bus Frequency Divider Register (IBFD) Read and write anytime Table 9-2. IBFD Field Descriptions Field 7:0 IBC[7:0] Description I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 9-3. Table 9-3. I-Bus Tap and Prescale Values IBC2-0 (bin) 000 001 010 011 100 101 110 111 IBC5-3 (bin) 000 001 010 011 100 101 110 111 scl2start (clocks) 2 2 2 6 14 30 62 126 SCL Tap (clocks) 5 6 7 8 9 10 12 15 scl2stop (clocks) 7 7 9 9 17 33 65 129 SDA Tap (clocks) 1 1 2 2 3 3 4 4 scl2tap (clocks) 4 4 6 6 14 30 62 126 tap2tap (clocks) 1 2 4 8 16 32 64 128 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 399 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-4. Multiplier Factor IBC7-6 00 01 10 11 MUL 01 02 04 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 9-3, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 9-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 9-4. SCL Divider SCL SDA SDA Hold SDA SCL Hold(start) SCL Hold(stop) SCL START condition STOP condition Figure 9-5. SCL Divider and SDA Hold The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)} MC9S12XDP512 Data Sheet, Rev. 2.17 400 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 9-5. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap] Table 9-5. IIC Divider and Hold Values (Sheet 1 of 5) IBC[7:0] (hex) SCL Divider (clocks) 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 SDA Hold (clocks) 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 SCL Hold (start) 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 SCL Hold (stop) 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113 MUL=1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 401 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5. IIC Divider and Hold Values (Sheet 2 of 5) IBC[7:0] (hex) 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider (clocks) 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 SDA Hold (clocks) 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 SCL Hold (start) 126 142 158 190 238 158 190 222 254 286 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 SCL Hold (stop) 129 145 161 193 241 161 193 225 257 289 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58 MUL=2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E MC9S12XDP512 Data Sheet, Rev. 2.17 402 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5. IIC Divider and Hold Values (Sheet 3 of 5) IBC[7:0] (hex) 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B SCL Divider (clocks) 136 96 112 128 144 160 176 208 256 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 SDA Hold (clocks) 26 18 18 26 26 34 34 42 42 18 18 34 34 50 50 66 66 34 34 66 66 98 98 130 130 66 66 130 130 194 194 258 258 130 130 258 258 386 386 514 514 258 258 514 514 SCL Hold (start) 60 36 44 52 60 68 76 92 116 76 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 SCL Hold (stop) 70 50 58 66 74 82 90 106 130 82 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 403 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5. IIC Divider and Hold Values (Sheet 4 of 5) IBC[7:0] (hex) 7C 7D 7E 7F SCL Divider (clocks) 4608 5120 6144 7680 80 88 96 104 112 120 136 160 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 SDA Hold (clocks) 770 770 1026 1026 28 28 32 32 36 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 SCL Hold (start) 2300 2556 3068 3836 24 28 32 36 40 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 SCL Hold (stop) 2306 2562 3074 3842 44 48 52 56 60 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964 MUL=4 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MC9S12XDP512 Data Sheet, Rev. 2.17 404 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5. IIC Divider and Hold Values (Sheet 5 of 5) IBC[7:0] (hex) A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF SCL Divider (clocks) 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 SDA Hold (clocks) 132 132 260 260 388 388 516 516 260 260 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 SCL Hold (start) 632 760 888 1016 1144 1272 1528 1912 1272 1528 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 SCL Hold (stop) 644 772 900 1028 1156 1284 1540 1924 1284 1540 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684 9.3.2.3 IIC Control Register (IBCR) 7 6 5 4 3 2 1 0 R IBEN W Reset 0 0 0 0 0 IBIE MS/SL Tx/Rx TXAK 0 0 IBSWAI RSTA 0 0 0 = Unimplemented or Reserved Figure 9-6. IIC Bus Control Register (IBCR) Read and write anytime MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 405 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-6. IBCR Field Descriptions Field 7 IBEN Description I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set. Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 0 Slave Mode 1 Master Mode Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive 1 Transmit Transmit Acknowledge Enable — This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter. 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle 6 IBIE 5 MS/SL 4 Tx/Rx 3 TXAK 2 RSTA 1 Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. RESERVED 0 IBSWAI I Bus Interface Stop in Wait Mode 0 IIC bus module clock operates normally 1 Halt IIC bus module clock generation in wait mode Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume MC9S12XDP512 Data Sheet, Rev. 2.17 406 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively. 9.3.2.4 IIC Status Register (IBSR) 7 6 5 4 3 2 1 0 R W Reset TCF IAAS IBB IBAL 0 SRW IBIF RXAK 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-7. IIC Bus Status Register (IBSR) This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable. Table 9-7. IBSR Field Descriptions Field 7 TCF Description Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module. 0 Transfer in progress 1 Transfer complete Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy Bit 0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1. SDA sampled low when the master drives a high during an address or data transmit cycle. 2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. A start cycle is attempted when the bus is busy. 4. A repeated start cycle is requested in slave mode. 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit. 6 IAAS 5 IBB 4 IBAL 3 Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 407 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-7. IBSR Field Descriptions (continued) Field 2 SRW Description Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs: — Arbitration lost (IBAL bit set) — Byte transfer complete (TCF bit set) — Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received 1 IBIF 0 RXAK 9.3.2.5 IIC Data I/O Register (IBDR) 7 6 5 4 3 2 1 0 R D7 W Reset 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 Figure 9-8. IIC Bus Data I/O Register (IBDR) In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0). MC9S12XDP512 Data Sheet, Rev. 2.17 408 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.4 Functional Description This section provides a complete functional description of the IICV2. 9.4.1 I-Bus Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 9-9. MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0 Start Signal Calling Address Read/ Write Ack Bit Data Byte No Stop Ack Signal Bit LSB MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 8 9 SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W Start Signal Calling Address Read/ Write Ack Bit Repeated Start Signal New Calling Address Read/ Write No Stop Ack Signal Bit Figure 9-9. IIC-Bus Transmission Signals 9.4.1.1 START Signal When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown in Figure 9-9, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 409 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description SDA SCL START Condition STOP Condition Figure 9-10. Start and Stop Conditions 9.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 9-9). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master. 9.4.1.3 Data Transfer As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 9-9. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. MC9S12XDP512 Data Sheet, Rev. 2.17 410 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal. 9.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 9-9). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus. 9.4.1.5 Repeated START Signal As shown in Figure 9-9, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 9.4.1.6 Arbitration Procedure The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration. 9.4.1.7 Clock Synchronization Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 9-10). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 411 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Start Counting High Period WAIT SCL1 SCL2 SCL Internal Counter Reset Figure 9-11. IIC-Bus Clock Synchronization 9.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 9.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched. 9.4.2 Operation in Run Mode This is the basic mode of operation. 9.4.3 Operation in Wait Mode IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry. 9.4.4 Operation in Stop Mode The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states. MC9S12XDP512 Data Sheet, Rev. 2.17 412 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.5 Resets The reset state of each individual bit is listed in Section 9.3, “Memory Map and Register Definition,” which details the registers and their bit-fields. 9.6 Interrupts Table 9-8. Interrupt Summary Interrupt IIC Interrupt Offset — Vector — Priority — Source Description IICV2 uses only one interrupt vector. IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine. 9.7 9.7.1 9.7.1.1 Initialization/Application Information IIC Programming Examples Initialization Sequence Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the IIC bus address register (IBAD) to define its slave address. 3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 413 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.7.1.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below: CHFLAG TXSTART IBFREE BRSET BSET MOVB BRCLR IBSR,#$20,* IBCR,#$30 CALLING,IBDR IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION ;TRANSMIT THE CALLING ADDRESS, D0=R/W ;WAIT FOR IBB FLAG TO SET 9.7.1.3 Post-Transfer Software Response Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine. ISR BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA TRANSMIT MC9S12XDP512 Data Sheet, Rev. 2.17 414 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.7.1.4 Generation of STOP A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. MASTX TST BEQ BRSET MOVB DEC BRA BCLR RTI TXCNT END IBSR,#$01,END DATABUF,IBDR TXCNT EMASTX IBCR,#$20 ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA ;END IF NO ACK ;TRANSMIT NEXT BYTE OF DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT END EMASTX If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver. MASR DEC BEQ MOVB DEC BNE BSET BRA BCLR MOVB RTI RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 NXMAR IBCR,#$20 IBDR,RXBUF ;DECREASE THE RXCNT ;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE ;TO BE READ ;NOT LAST OR SECOND LAST ;SECOND LAST, DISABLE ACK ;TRANSMITTING ;LAST ONE, GENERATE ‘STOP’ SIGNAL ;READ DATA AND STORE LAMAR ENMASR NXMAR 9.7.1.5 Generation of Repeated START At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown. RESTART BSET MOVB IBCR,#$04 CALLING,IBDR ;ANOTHER START (RESTART) ;TRANSMIT THE CALLING ADDRESS;D0=R/W 9.7.1.6 Slave Mode In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 415 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. 9.7.1.7 Arbitration Lost If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MC9S12XDP512 Data Sheet, Rev. 2.17 416 Freescale Semiconductor Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Clear IBIF Y Master Mode ? N TX Tx/Rx ? RX Y Arbitration Lost ? N Last Byte Transmitted ? N Y Clear IBAL RXAK=0 ? Y End Of Addr Cycle (Master Rx) ? N N Last Byte To Be Read ? N Y N IAAS=1 ? Y Y IAAS=1 ? N Address Transfer Y 2nd Last Y Byte To Be Read ? N Y (Read) SRW=1 ? N (Write) Y Data Transfer TX/RX ? TX ACK From Receiver ? N Read Data From IBDR And Store RX Write Next Byte To IBDR Set TXAK =1 Generate Stop Signal Set TX Mode Write Data To IBDR Tx Next Byte Switch To Rx Mode Set RX Mode Switch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Dummy Read From IBDR Dummy Read From IBDR RTI Figure 9-12. Flow-Chart of Typical IIC Interrupt Routine MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 417 Chapter 9 Inter-Integrated Circuit (IICV2) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 418 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.1 Introduction Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software. 10.1.1 Glossary ACK: Acknowledge of CAN message CAN: Controller Area Network CRC: Cyclic Redundancy Code EOF: End of Frame FIFO: First-In-First-Out Memory IFS: Inter-Frame Sequence SOF: Start of Frame CPU bus: CPU related read/write data bus CAN bus: CAN protocol related serial bus oscillator clock: Direct clock from external oscillator bus clock: CPU bus realated clock CAN clock: CAN protocol related clock MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 419 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.1.2 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req. Control and Status Message Filtering and Buffering Configuration Registers Wake-Up Low Pass Filter Figure 10-1. MSCAN Block Diagram 10.1.3 Features The basic features of the MSCAN are as follows: • Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps1 — Support for remote frames • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization using a “local priority” concept • Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters • Programmable wakeup functionality with integrated low-pass filter • Programmable loopback mode supports self-test operation • Programmable listen-only mode for monitoring of CAN bus • Programmable bus-off recovery functionality • Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) • Programmable MSCAN clock source either bus clock or oscillator clock 1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12XDP512 Data Sheet, Rev. 2.17 420 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Internal timer for time-stamping of received and transmitted messages Three low-power modes: sleep, power down, and MSCAN enable Global initialization of configuration registers 10.1.4 Modes of Operation The following modes of operation are specific to the MSCAN. See Section 10.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode 10.2 External Signal Description The MSCAN uses two external pins: 10.2.1 RXCAN — CAN Receiver Input Pin RXCAN is the MSCAN receiver input pin. 10.2.2 TXCAN — CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state 10.2.3 CAN System A typical CAN system with MSCAN is shown in Figure 10-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 421 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN node 1 MCU CAN Controller (MSCAN) CAN node 2 CAN node n TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 10-2. CAN System 10.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 10.3.1 Module Memory Map Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The detailed register descriptions follow in the order they appear in the register map. Register Name 0x0000 CANCTL0 0x0001 CANCTL1 R W R W Bit 7 6 RXACT 5 4 SYNCH 3 2 1 Bit 0 RXFRM CSWAI TIME WUPE SLPRQ SLPAK INITRQ INITAK CANE CLKSRC LOOPB LISTEN BORM WUPM = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 422 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x0002 CANBTR0 0x0003 CANBTR1 0x0004 CANRFLG 0x0005 CANRIER 0x0006 CANTFLG 0x0007 CANTIER 0x0008 CANTARQ 0x0009 CANTAAK 0x000A CANTBSEL 0x000B CANIDAC 0x000C Reserved 0x000D CANMISC 0x000E CANRXERR 0x000F CANTXERR 0x0010–0x0013 CANIDAR0–3 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 SJW1 6 SJW0 5 BRP5 4 BRP4 3 BRP3 2 BRP2 1 BRP1 Bit 0 BRP0 SAMP TSEG22 TSEG21 RSTAT1 TSEG20 RSTAT0 TSEG13 TSTAT1 TSEG12 TSTAT0 TSEG11 TSEG10 WUPIF CSCIF OVRIF RXF WUPIE 0 CSCIE 0 RSTATE1 0 RSTATE0 0 TSTATE1 0 TSTATE0 OVRIE RXFIE TXE2 TXE1 TXE0 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 0 0 ABTRQ2 ABTAK2 ABTRQ1 ABTAK1 ABTRQ0 ABTAK0 0 0 0 0 0 0 0 0 0 0 TX2 IDHIT2 TX1 IDHIT1 TX0 IDHIT0 0 0 IDAM1 0 IDAM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOHOLD RXERR0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary (continued) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 423 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x0014–0x0017 CANIDMRx 0x0018–0x001B CANIDAR4–7 0x001C–0x001F CANIDMR4–7 0x0020–0x002F CANRXFG 0x0030–0x003F CANTXFG R W R W R W R W R W Bit 7 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 See Section 10.3.3, “Programmer’s Model of Message Storage” See Section 10.3.3, “Programmer’s Model of Message Storage” = Unimplemented or Reserved u = Unaffected Figure 10-3. MSCAN Register Summary (continued) 10.3.2 Register Descriptions This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. 10.3.2.1 MSCAN Control Register 0 (CANCTL0) The CANCTL0 register provides various control bits of the MSCAN module as described below. 7 6 5 4 3 2 1 0 R RXFRM W Reset: 0 RXACT CSWAI 0 = Unimplemented 0 SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1 Figure 10-4. MSCAN Control Register 0 (CANCTL0) NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime MC9S12XDP512 Data Sheet, Rev. 2.17 424 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode). Table 10-1. CANCTL0 Register Field Descriptions Field 7 RXFRM1 Description Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 10.3.3, “Programmer’s Model of Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is detected (see Section 10.4.5.4, “MSCAN Sleep Mode”). This bit must be configured before sleep mode entry for the selected function to take effect. 0 Wake-up disabled — The MSCAN ignores traffic on CAN 1 Wake-up enabled — The MSCAN is able to restart 6 RXACT 5 CSWAI3 4 SYNCH 3 TIME 2 WUPE4 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 425 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-1. CANCTL0 Register Field Descriptions (continued) Field 1 SLPRQ5 Description Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannot be set while the WUPIF flag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running — The MSCAN functions normally 1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 10.4.5.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode 0 INITRQ6,7 1 2 The MSCAN must be in normal mode for this bit to become set. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. 3 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 10.4.5.2, “Operation in Wait Mode” and Section 10.4.5.3, “Operation in Stop Mode”). 4 The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 7 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 8 Not including WUPE, INITRQ, and SLPRQ. 9 TSTAT1 and TSTAT0 are not affected by initialization mode. 10 RSTAT1 and RSTAT0 are not affected by initialization mode. 10.3.2.2 MSCAN Control Register 1 (CANCTL1) The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. MC9S12XDP512 Data Sheet, Rev. 2.17 426 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 R CANE W Reset: 0 0 = Unimplemented 0 1 0 0 CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK 0 1 Figure 10-5. MSCAN Control Register 1 (CANCTL1) Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). Table 10-2. CANCTL1 Register Field Descriptions Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source — This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 10.4.3.2, “Clock System,” and Section Figure 10-43., “MSCAN Clocking Scheme,”). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode — When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode — This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 10.4.4.4, “Listen-Only Mode”). In addition, the error counters are frozen. Listen only mode supports applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Bus-Off Recovery Mode — This bits configures the bus-off state recovery mode of the MSCAN. Refer to Section 10.5.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification) 1 Bus-off recovery upon user request Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 10.4.5.4, “MSCAN Sleep Mode”). 0 MSCAN wakes up on any dominant level on the CAN bus 1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of Twup Description 5 LOOPB 4 LISTEN 3 BORM 2 WUPM MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 427 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-2. CANCTL1 Register Field Descriptions (continued) Field 1 SLPAK Description Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running — The MSCAN operates normally 1 Sleep mode active — The MSCAN has entered sleep mode Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode (see Section 10.4.5.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running — The MSCAN operates normally 1 Initialization mode active — The MSCAN has entered initialization mode 0 INITAK 10.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0) The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module. 7 6 5 4 3 2 1 0 R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-3. CANBTR0 Register Field Descriptions Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 10-4). Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 10-5). Table 10-4. Synchronization Jump Width SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles MC9S12XDP512 Data Sheet, Rev. 2.17 428 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-5. Baud Rate Prescaler BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64 10.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module. 7 6 5 4 3 2 1 0 R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Figure 10-7. MSCAN Bus Timing Register 1 (CANBTR1) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-6. CANBTR1 Register Field Descriptions Field 7 SAMP Description Sampling — This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0). 6:4 Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 10-44). Time segment 2 (TSEG2) values are programmable as shown in Table 10-7. 3:0 Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 10-44). Time segment 1 (TSEG1) values are programmable as shown in Table 10-8. 1 In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 429 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-7. Time Segment 2 Values TSEG22 0 0 : 1 1 1 TSEG21 0 0 : 1 1 TSEG20 0 1 : 0 1 Time Segment 2 1 Tq clock cycle1 2 Tq clock cycles : 7 Tq clock cycles 8 Tq clock cycles This setting is not valid. Please refer to Table 10-35 for valid settings. Table 10-8. Time Segment 1 Values TSEG13 0 0 0 0 : 1 1 1 TSEG12 0 0 0 0 : 1 1 TSEG11 0 0 1 1 : 1 1 TSEG10 0 1 0 1 : 0 1 Time segment 1 1 Tq clock cycle1 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 16 Tq clock cycles This setting is not valid. Please refer to Table 10-35 for valid settings. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 10-7 and Table 10-8). Eqn. 10-1 ( Prescaler value ) Bit Time = ----------------------------------------------------- • ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK 10.3.2.5 MSCAN Receiver Flag Register (CANRFLG) A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register. 7 6 5 4 3 2 1 0 R WUPIF W Reset: 0 0 CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF 0 0 0 0 0 0 = Unimplemented Figure 10-8. MSCAN Receiver Flag Register (CANRFLG) MC9S12XDP512 Data Sheet, Rev. 2.17 430 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored. Table 10-9. CANRFLG Register Field Descriptions Field 7 WUPIF Description Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 ≤ receive error counter ≤ 96 01 RxWRN: 96 < receive error counter ≤ 127 10 RxERR: 127 < receive error counter 11 Bus-off1: transmit error counter > 255 Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 ≤ transmit error counter ≤ 96 01 TxWRN: 96 < transmit error counter ≤ 127 10 TxERR: 127 < transmit error counter ≤ 255 11 Bus-Off: transmit error counter > 255 6 CSCIF 5:4 RSTAT[1:0] 3:2 TSTAT[1:0] 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 431 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-9. CANRFLG Register Field Descriptions (continued) Field 1 OVRIF Description Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG 0 RXF2 1 Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition. 10.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER) This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register. 7 6 5 4 3 2 1 0 R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE Figure 10-9. MSCAN Receiver Interrupt Enable Register (CANRIER) NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode MC9S12XDP512 Data Sheet, Rev. 2.17 432 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-10. CANRIER Register Field Descriptions Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request. 5:4 Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 1 OVRIE 0 RXFIE 1 Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request. WUPIE and WUPE (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 10.3.2.7 MSCAN Transmitter Flag Register (CANTFLG) The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 433 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TXE2 TXE1 1 TXE0 1 0 0 0 0 0 1 = Unimplemented Figure 10-10. MSCAN Transmitter Flag Register (CANTFLG) NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored Table 10-11. CANTFLG Register Field Descriptions Field 2:0 TXE[2:0] Description Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 10.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). When listen-mode is active (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled) 10.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the transmit buffer empty interrupt flags. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TXEIE2 TXEIE1 0 TXEIE0 0 0 0 0 0 0 0 = Unimplemented Figure 10-11. MSCAN Transmitter Interrupt Enable Register (CANTIER) MC9S12XDP512 Data Sheet, Rev. 2.17 434 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 10-12. CANTIER Register Field Descriptions Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. 10.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ) The CANTARQ register allows abort request of queued messages as described below. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 ABTRQ2 ABTRQ1 0 ABTRQ0 0 0 0 0 0 0 0 = Unimplemented Figure 10-12. MSCAN Transmitter Message Abort Request Register (CANTARQ) NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 10-13. CANTARQ Register Field Descriptions Field Description 2:0 Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge flags (ABTAK, see Section 10.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 435 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags Table 10-14. CANTAAK Register Field Descriptions Field Description 2:0 Abort Acknowledge — This flag acknowledges that a message was aborted due to a pending abort request ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted. 10.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 TX2 TX1 0 TX0 0 0 0 0 0 0 0 = Unimplemented Figure 10-14. MSCAN Transmit Buffer Selection Register (CANTBSEL) MC9S12XDP512 Data Sheet, Rev. 2.17 436 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode Table 10-15. CANTBSEL Register Field Descriptions Field 2:0 TX[2:0] Description Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. • LDD CANTFLG; value read is 0b0000_0110 • STD CANTBSEL; value written is 0b0000_0110 • LDD CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers. 10.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC) The CANIDAC register is used for identifier acceptance control as described below. 7 6 5 4 3 2 1 0 R W Reset: 0 0 IDAM1 IDAM0 0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 0 0 0 = Unimplemented Figure 10-15. MSCAN Identifier Acceptance Control Register (CANIDAC) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 437 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only Table 10-16. CANIDAC Register Field Descriptions Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-17 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-18 summarizes the different settings. Table 10-17. Identifier Acceptance Mode Settings IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters Filter closed Table 10-18. Identifier Acceptance Hit Indication IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well. 10.3.2.13 MSCAN Reserved Register This register is reserved for factory testing of the MSCAN module and is not available in normal system operation modes. MC9S12XDP512 Data Sheet, Rev. 2.17 438 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-16. MSCAN Reserved Register Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.14 MSCAN Miscellaneous Register (CANMISC) This register provides additional features. 7 6 5 4 3 2 1 0 R W Reset: 0 0 0 0 0 0 0 BOHOLD 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-17. MSCAN Miscellaneous Register (CANMISC) Read: Anytime Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored Table 10-19. CANMISC Register Field Descriptions Field 0 BOHOLD Description Bus-off State Hold Until User Request — If BORM is set in Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 10.5.2, “Bus-Off Recovery,” for details. 0 Module is not bus-off or recovery has been requested by user in bus-off state 1 Module is bus-off and holds this state until user request 10.3.2.15 MSCAN Receive Error Counter (CANRXERR) This register reflects the status of the MSCAN receive error counter. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 439 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 R W Reset: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-18. MSCAN Receive Error Counter (CANRXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.16 MSCAN Transmit Error Counter (CANTXERR) This register reflects the status of the MSCAN transmit error counter. 7 6 5 4 3 2 1 0 R W Reset: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 = Unimplemented Figure 10-19. MSCAN Transmit Error Counter (CANTXERR) Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. MC9S12XDP512 Data Sheet, Rev. 2.17 440 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 10.3.3.1, “Identifier Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 10.4.3, “Identifier Acceptance Filter”). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied. Module Base + 0x0010 (CANIDAR0) 0x0011 (CANIDAR1) 0x0012 (CANIDAR2) 0x0013 (CANIDAR3) 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 10-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 441 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-20. CANIDAR0–CANIDAR3 Register Field Descriptions Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7) 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 7 6 5 4 3 2 1 0 R AC7 W Reset 0 0 0 0 0 0 0 0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 10-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12XDP512 Data Sheet, Rev. 2.17 442 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-21. CANIDAR4–CANIDAR7 Register Field Descriptions Field 7:0 AC[7:0] Description Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. 10.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3) 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Figure 10-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 443 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-22. CANIDMR0–CANIDMR3 Register Field Descriptions Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7) 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 7 6 5 4 3 2 1 0 R AM7 W Reset 0 0 0 0 0 0 0 0 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Figure 10-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7 Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) MC9S12XDP512 Data Sheet, Rev. 2.17 444 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-23. CANIDMR4–CANIDMR7 Register Field Descriptions Field 7:0 AM[7:0] Description Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit 10.3.3 Programmer’s Model of Message Storage The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. Table 10-24. Message Buffer Organization Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register1 Time Stamp Register (High Byte)2 Time Stamp Register (Low Byte)3 Register Access MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 445 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 2 Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU Figure 10-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 10-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. 1. Exception: The transmit priority registers are 0 out of reset. MC9S12XDP512 Data Sheet, Rev. 2.17 446 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 447 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 10-24. Receive/Transmit Message Buffer — Extended Identifier Mapping Register Name R IDR0 W ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 Bit 7 6 5 4 3 2 1 Bit0 MC9S12XDP512 Data Sheet, Rev. 2.17 448 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 10-24. Receive/Transmit Message Buffer — Extended Identifier Mapping Register Name R IDR1 W R IDR2 ID14 W R IDR3 ID6 W R DSR0 DB7 W R DSR1 DB7 W R DSR2 DB7 W R DSR3 DB7 W R DSR4 DB7 W R DSR5 DB7 W R DSR6 DB7 W R DSR7 DB7 W R DLR DLC3 W DLC2 DLC1 DLC0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ID5 ID4 ID3 ID2 ID1 ID0 RTR ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 Bit 7 6 5 4 3 2 1 Bit0 = Unused, always read ‘x’ MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 449 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF flag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Write: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation Figure 10-25. Receive/Transmit Message Buffer — Standard Identifier Mapping Register Name R IDR0 W R IDR1 W R IDR2 W R IDR3 W ID2 ID1 ID0 RTR IDE (=0) ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Bit 7 6 5 4 3 2 1 Bit 0 = Unused, always read ‘x’ 10.3.3.1 Identifier Registers (IDR0–IDR3) The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. 10.3.3.1.1 IDR0–IDR3 for Extended Identifier Mapping 7 6 5 4 3 2 1 0 R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21 Figure 10-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping MC9S12XDP512 Data Sheet, Rev. 2.17 450 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-25. IDR0 Register Field Descriptions — Extended Field 7:0 ID[28:21] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 7 6 5 4 3 2 1 0 R ID20 W Reset: x x x x x x x x ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 Figure 10-27. Identifier Register 1 (IDR1) — Extended Identifier Mapping Table 10-26. IDR1 Register Field Descriptions — Extended Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. 2:0 ID[17:15] 7 6 5 4 3 2 1 0 R ID14 W Reset: x x x x x x x x ID13 ID12 ID11 ID10 ID9 ID8 ID7 Figure 10-28. Identifier Register 2 (IDR2) — Extended Identifier Mapping Table 10-27. IDR2 Register Field Descriptions — Extended Field 7:0 ID[14:7] Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 451 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR Figure 10-29. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 10-28. IDR3 Register Field Descriptions — Extended Field 7:1 ID[6:0] 0 RTR Description Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame 10.3.3.1.2 IDR0–IDR3 for Standard Identifier Mapping 7 6 5 4 3 2 1 0 R ID10 W Reset: x x x x x x x x ID9 ID8 ID7 ID6 ID5 ID4 ID3 Figure 10-30. Identifier Register 0 — Standard Mapping Table 10-29. IDR0 Register Field Descriptions — Standard Field 7:0 ID[10:3] Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 10-30. 7 6 5 4 3 2 1 0 R ID2 W Reset: x x x x x x x x ID1 ID0 RTR IDE (=0) = Unused; always read ‘x’ Figure 10-31. Identifier Register 1 — Standard Mapping MC9S12XDP512 Data Sheet, Rev. 2.17 452 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-30. IDR1 Register Field Descriptions Field 7:5 ID[2:0] 4 RTR Description Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 10-29. Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) 3 IDE 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure 10-32. Identifier Register 2 — Standard Mapping 7 6 5 4 3 2 1 0 R W Reset: x x x x x x x x = Unused; always read ‘x’ Figure 10-33. Identifier Register 3 — Standard Mapping 10.3.3.2 Data Segment Registers (DSR0-7) The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 453 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7) 7 6 5 4 3 2 1 0 R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0 Figure 10-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 10-31. DSR0–DSR7 Register Field Descriptions Field 7:0 DB[7:0] Data bits 7:0 Description 10.3.3.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. 7 6 5 4 3 2 1 0 R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0 = Unused; always read “x” Figure 10-35. Data Length Register (DLR) — Extended Identifier Mapping Table 10-32. DLR Register Field Descriptions Field 3:0 DLC[3:0] Description Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 10-33 shows the effect of setting the DLC bits. MC9S12XDP512 Data Sheet, Rev. 2.17 454 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-33. Data Length Codes Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8 10.3.3.4 Transmit Buffer Priority Register (TBPR) This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: • All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. • The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. 7 6 5 4 3 2 1 0 R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Figure 10-36. Transmit Buffer Priority Register (TBPR) Read: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). 10.3.3.5 Time Stamp Register (TSRH–TSRL) If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (see Section 10.3.2.1, MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 455 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers. 7 6 5 4 3 2 1 0 R W Reset: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 x x x x x x x x Figure 10-37. Time Stamp Register — High Byte (TSRH) 7 6 5 4 3 2 1 0 R W Reset: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 x x x x x x x x Figure 10-38. Time Stamp Register — Low Byte (TSRL) Read: Anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Write: Unimplemented 10.4 10.4.1 Functional Description General This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction. MC9S12XDP512 Data Sheet, Rev. 2.17 456 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 Rx1 Rx2 Rx3 Rx4 RXF RxBG MSCAN Receiver Tx0 RxFG CPU bus TXE0 TxBG Tx1 PRIO TXE1 TxFG MSCAN CPU bus PRIO Tx2 TXE2 Transmitter TxBG PRIO Figure 10-39. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 457 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. • The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the “local priority” concept described in Section 10.4.2.2, “Transmit Structures.” 10.4.2.2 Transmit Structures The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 10-39. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 10.3.3, “Programmer’s Model of Message Storage”). An additional Section 10.3.3.4, “Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 10.3.3.4, “Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required (see Section 10.3.3.5, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 10.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag. MC9S12XDP512 Data Sheet, Rev. 2.17 458 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 10.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 10.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0). 10.4.2.3 Receive Structures The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 10-39). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 10-39). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 10.3.3, “Programmer’s Model of Message Storage”). The receiver full flag (RXF) (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 10.4.3, “Identifier Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (see Section 10.4.7.3, “Receive Interrupt”) to the CPU3. The user’s receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF flag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 459 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 10.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted. 10.4.3 Identifier Acceptance Filter The MSCAN identifier acceptance registers (see Section 10.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”) define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identifier mask registers (see Section 10.3.2.18, “MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)”). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 10.3.2.12, “MSCAN Identifier Acceptance Control Register (CANIDAC)”). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): • Two identifier acceptance filters, each to be applied to: — The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identifier extension (IDE) – Substitute remote request (SRR) — The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 10-40 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a filter 1 hit. 1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC9S12XDP512 Data Sheet, Rev. 2.17 460 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 10-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits. Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 10-42 shows how the first 32-bit filter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to 7 hits. Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set. IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 0 Hit) Figure 10-40. 32-bit Maskable Identifier Acceptance Filter MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 461 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier ID28 ID10 IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 10-41. 16-bit Maskable Identifier Acceptance Filters MC9S12XDP512 Data Sheet, Rev. 2.17 462 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10 IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID Accepted (Filter 0 Hit) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID Accepted (Filter 1 Hit) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID Accepted (Filter 2 Hit) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID Accepted (Filter 3 Hit) Figure 10-42. 8-bit Maskable Identifier Acceptance Filters MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 463 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identifier acceptance control register (CANIDAC) — MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identifier mask registers (CANIDMR0–CANIDMR7) • The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 10.4.5.6, “MSCAN Power Down Mode,” and Section 10.4.5.5, “MSCAN Initialization Mode”). • The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN. 10.4.3.2 Clock System Figure 10-43 shows the structure of the MSCAN clock generation circuitry. MSCAN Bus Clock CANCLK CLKSRC Prescaler (1 .. 64) Time quanta clock (Tq) CLKSRC Oscillator Clock Figure 10-43. MSCAN Clocking Scheme The clock source bit (CLKSRC) in the CANCTL1 register (10.3.2.2/10-426) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. MC9S12XDP512 Data Sheet, Rev. 2.17 464 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn. 10-2 f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure 10-44): • SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. • Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Eqn. 10-3 f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta ) NRZ Signal SYNC_SEG Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time Time Segment 2 (PHASE_SEG2) 2 ... 8 1 Transmit Point Sample Point (single or triple sampling) Figure 10-44. Segments within the Bit Time MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 465 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-34. Time Segment Syntax Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Sample Point The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 10.3.2.3, “MSCAN Bus Timing Register 0 (CANBTR0)” and Section 10.3.2.4, “MSCAN Bus Timing Register 1 (CANBTR1)”). Table 10-35 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. Table 10-35. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3 10.4.4 10.4.4.1 Modes of Operation Normal Modes The MSCAN module behaves as described within this specification in all normal system operation modes. 10.4.4.2 Special Modes The MSCAN module behaves as described within this specification in all special system operation modes. MC9S12XDP512 Data Sheet, Rev. 2.17 466 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 10.4.4.4 Listen-Only Mode In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus may remain in recessive state externally. 10.4.4.5 Security Modes The MSCAN module has no security features. 10.4.5 Low-Power Options If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 10-36 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 467 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-36. CPU vs. MSCAN Operating Modes MSCAN Mode CPU Mode Normal Sleep CSWAI = X1 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X RUN WAIT STOP 1 ‘X’ means don’t care. 10.4.5.1 Operation in Run Mode As shown in Table 10-36, only MSCAN sleep mode is available as low power option when the CPU is in run mode. 10.4.5.2 Operation in Wait Mode The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 10-36. 10.4.5.3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits (Table 10-36). 10.4.5.4 MSCAN Sleep Mode The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity: MC9S12XDP512 Data Sheet, Rev. 2.17 468 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. Bus Clock Domain CAN Clock Domain SLPRQ Flag SLPRQ CPU Sleep Request SYNC sync. SLPRQ SLPAK Flag sync. SLPAK SYNC SLPAK MSCAN in Sleep Mode Figure 10-45. Sleep Request / Acknowledge Cycle NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 10-45). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 10-46). WUPE must be set before entering sleep mode to take effect. The MSCAN is able to leave sleep mode (wake up) only when: • CAN bus activity occurs and WUPE = 1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 469 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • or the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. CAN Activity StartUp Wait for Idle CAN Activity SLPRQ (CAN Activity & WUPE) | SLPRQ CAN Activity & SLPRQ Idle Sleep (CAN Activity & WUPE) | CAN Activity & SLPRQ CAN Activity CAN Activity Tx/Rx Message Active CAN Activity Figure 10-46. Simplified State Transitions for Entering/Leaving Sleep Mode 10.4.5.5 MSCAN Initialization Mode In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. MC9S12XDP512 Data Sheet, Rev. 2.17 470 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode. Bus Clock Domain CAN Clock Domain INIT Flag INITRQ CPU Init Request SYNC sync. INITRQ INITAK Flag sync. INITAK SYNC INITAK Figure 10-47. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 10-47., “Initialization Request/Acknowledge Cycle”). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active. 10.4.5.6 MSCAN Power Down Mode The MSCAN is in power down mode (Table 10-36) when • CPU is in stop mode MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 471 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • or CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again. 10.4.5.7 Programmable Wake-Up Function The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from—for example—electromagnetic interference within noisy environments. 10.4.6 Reset Initialization The reset state of each individual bit is listed in Section 10.3.2, “Register Descriptions,” which details all the registers and their bit-fields. 10.4.7 Interrupts This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately. 10.4.7.1 Description of Interrupt Operation The MSCAN supports four interrupt vectors (see Table 10-37), any of which can be individually masked (for details see sections from Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER),” to Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). MC9S12XDP512 Data Sheet, Rev. 2.17 472 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 10-37. Interrupt Vectors Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) 10.4.7.2 Transmit Interrupt At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set. 10.4.7.3 Receive Interrupt A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer. 10.4.7.4 Wake-Up Interrupt A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode. WUPE (see Section 10.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must be enabled. 10.4.7.5 Error Interrupt An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: • Overrun — An overrun condition of the receiver FIFO as described in Section 10.4.2.3, “Receive Structures,” occurred. • CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” and Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). 10.4.7.6 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)” or the Section 10.3.2.7, “MSCAN Transmitter Flag Register MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 473 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine. 10.4.7.7 Recovery from Stop or Wait The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1). 10.5 10.5.1 Initialization/Application Information MSCAN initialization The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode 10.5.2 Bus-Off Recovery The bus-off recovery is user configurable. The bus-off state can either be left automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (See the Bosch CAN specification for details). MC9S12XDP512 Data Sheet, Rev. 2.17 474 Freescale Semiconductor Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the MSCAN is configured for user request (BORM set in Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”), the recovery from bus-off starts after both independent events have become true: • 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in Section 10.3.2.14, “MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 475 Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.17 476 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.1 Introduction This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 11.1.1 Glossary IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Significant Bit MSB: Most Significant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin 11.1.2 Features The SCI includes these distinctive features: • Full-duplex or single-wire operation • Standard mark/space non-return-to-zero (NRZ) format • Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths • 13-bit baud rate selection • Programmable 8-bit or 9-bit data format • Separately enabled transmitter and receiver • Programmable polarity for transmitter and receiver MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 477 Chapter 11 Serial Communication Interface (S12SCIV5) • • • • • • Programmable transmitter output parity Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection 11.1.3 Modes of Operation The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes. • Run mode • Wait mode • Stop mode 11.1.4 Block Diagram Figure 11-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. MC9S12XDP512 Data Sheet, Rev. 2.17 478 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) SCI Data Register RXD Data In Infrared Decoder Receive Shift Register IDLE Receive & Wakeup Control Receive RDRF/OR Interrupt Generation BRKD RXEDG BERR Transmit TDRE Interrupt Generation TC SCI Interrupt Request Bus Clock Baud Rate Generator Data Format Control 1/16 Transmit Control Transmit Shift Register Infrared Encoder Data Out TXD SCI Data Register Figure 11-1. SCI Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 479 Chapter 11 Serial Communication Interface (S12SCIV5) 11.2 External Signal Description The SCI module has a total of two external pins. 11.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 11.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage. 11.3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers. 11.3.1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Figure 11-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register. MC9S12XDP512 Data Sheet, Rev. 2.17 480 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order. Register Name SCIBDH1 R W SCIBDL1 R W SCICR11 R W SCIASR12 R W SCIACR12 R W SCIACR22 R W SCICR2 R W SCISR1 R W SCISR2 R W SCIDRH R W SCIDRL R W R7 T7 AMAP R8 0 0 TXPOL 0 RXPOL 0 BRK13 0 TXDIR 0 RAF TIE TDRE TCIE TC RIE RDRF ILIE IDLE TE OR Bit 7 IREN 6 TNP1 5 TNP0 4 SBR12 3 SBR11 2 SBR10 1 SBR9 Bit 0 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 LOOPS SCISWAI 0 RSRC 0 M 0 WAKE 0 ILT PE PT RXEDGIF BERRV 0 BERRIF BKDIF RXEDGIE 0 0 0 0 0 BERRIE BKDIE 0 0 0 0 BERRM1 BERRM0 BKDFE RE NF RWU FE SBK PF T8 R6 T6 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. = Unimplemented or Reserved Figure 11-2. SCI Register Summary 1 2 Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero Those registers are accessible if the AMAP bit in the SCISR2 register is set to one MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 481 Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.1 R W Reset SCI Baud Rate Registers (SCIBDH, SCIBDL) 7 6 5 4 3 2 1 0 IREN 0 TNP1 0 TNP0 0 SBR12 0 SBR11 0 SBR10 0 SBR9 0 SBR8 0 Figure 11-3. SCI Baud Rate Register (SCIBDH) 7 6 5 4 3 2 1 0 R W Reset SBR7 0 SBR6 0 SBR5 0 SBR4 0 SBR3 0 SBR2 0 SBR1 0 SBR0 0 Figure 11-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. Table 11-1. SCIBDH and SCIBDL Field Descriptions Field 7 IREN 6:5 TNP[1:0] 4:0 7:0 SBR[12:0] Description Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule. 0 IR disabled 1 IR enabled Transmitter Narrow Pulse Bits — These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 11-2. SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (32 x SBR[12:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and IREN = 1). Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. MC9S12XDP512 Data Sheet, Rev. 2.17 482 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-2. IRSCI Transmit Pulse Width TNP[1:0] 11 10 01 00 Narrow Pulse Width 1/4 1/32 1/16 3/16 11.3.2.2 R W Reset SCI Control Register 1 (SCICR1) 7 6 5 4 3 2 1 0 LOOPS 0 SCISWAI 0 RSRC 0 M 0 WAKE 0 ILT 0 PE 0 PT 0 Figure 11-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 11-3. SCICR1 Field Descriptions Field 7 LOOPS Description Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit. SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 11-4. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin. 0 Idle line wakeup 1 Address mark wakeup 6 SCISWAI 5 RSRC 4 M 3 WAKE MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 483 Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-3. SCICR1 Field Descriptions (continued) Field 2 ILT Description Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 1 Even parity 1 Odd parity 1 PE 0 PT Table 11-4. Loop Functions LOOPS 0 1 1 RSRC x 0 1 Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input Function MC9S12XDP512 Data Sheet, Rev. 2.17 484 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.3 R W Reset SCI Alternative Status Register 1 (SCIASR1) 7 6 5 4 3 2 1 0 RXEDGIF 0 0 0 0 0 0 0 0 0 BERRV 0 BERRIF 0 BKDIF 0 = Unimplemented or Reserved Figure 11-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-5. SCIASR1 Field Descriptions Field 7 RXEDGIF Description Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it. 0 No active receive on the receive input has occurred 1 An active edge on the receive input has occurred Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1. 0 A low input was sampled, when a high was expected 1 A high input reassembled, when a low was expected Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it. 0 No mismatch detected 1 A mismatch has occurred Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it. 0 No break signal was received 1 A break signal was received 2 BERRV 1 BERRIF 0 BKDIF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 485 Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.4 R W Reset SCI Alternative Control Register 1 (SCIACR1) 7 6 5 4 3 2 1 0 RXEDGIE 0 0 0 0 0 0 0 0 0 0 0 BERRIE 0 BKDIE 0 = Unimplemented or Reserved Figure 11-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-6. SCIACR1 Field Descriptions Field 7 RSEDGIE Description Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag, RXEDGIF, to generate interrupt requests. 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt requests. 0 BERRIF interrupt requests disabled 1 BERRIF interrupt requests enabled Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt requests. 0 BKDIF interrupt requests disabled 1 BKDIF interrupt requests enabled 1 BERRIE 0 BKDIE MC9S12XDP512 Data Sheet, Rev. 2.17 486 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.5 R W Reset SCI Alternative Control Register 2 (SCIACR2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 BERRM1 0 BERRM0 0 BKDFE 0 = Unimplemented or Reserved Figure 11-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-7. SCIACR2 Field Descriptions Field Description 2:1 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 11-8. BERRM[1:0] 0 BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry. 0 Break detect circuit disabled 1 Break detect circuit enabled Table 11-8. Bit Error Mode Coding BERRM1 0 0 1 1 BERRM0 0 1 0 1 Bit error detect circuit is disabled Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 11-19) Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 11-19) Reserved Function MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 487 Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.6 R W Reset SCI Control Register 2 (SCICR2) 7 6 5 4 3 2 1 0 TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 Figure 11-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 11-9. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit — RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters 6 TCIE 5 RIE 4 ILIE 3 TE 2 RE 1 RWU 0 SBK MC9S12XDP512 Data Sheet, Rev. 2.17 488 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for flag clearing. 7 6 5 4 3 2 1 0 R W Reset TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PF 0 = Unimplemented or Reserved Figure 11-10. SCI Status Register 1 (SCISR1) Read: Anytime Write: Has no meaning or effect Table 11-10. SCISR1 Field Descriptions Field 7 TDRE Description Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty Transmit Complete Flag — TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. 6 TC 5 RDRF 4 IDLE MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 489 Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-10. SCISR1 Field Descriptions (continued) Field 3 OR Description Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Note: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received. Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error 2 NF 1 FE 0 PF MC9S12XDP512 Data Sheet, Rev. 2.17 490 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.8 R W Reset SCI Status Register 2 (SCISR2) 7 6 5 4 3 2 1 0 AMAP 0 0 0 0 0 TXPOL 0 RXPOL 0 BRK13 0 TXDIR 0 RAF 0 = Unimplemented or Reserved Figure 11-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 11-11. SCISR2 Field Descriptions Field 7 AMAP Description Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1. 0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible 1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. 0 Normal polarity 1 Inverted polarity Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break character is 10 or 11 bit long 1 Break character is 13 or 14 bit long Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation. 0 TXD pin to be used as an input in single-wire mode 1 TXD pin to be used as an output in single-wire mode Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress 4 TXPOL 3 RXPOL 2 BRK13 1 TXDIR 0 RAF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 491 Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.9 R W Reset SCI Data Registers (SCIDRH, SCIDRL) 7 6 5 4 3 2 1 0 R8 0 T8 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-12. SCI Data Registers (SCIDRH) 7 6 5 4 3 2 1 0 R W Reset R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 Figure 11-13. SCI Data Registers (SCIDRL) Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect Table 11-12. SCIDRH and SCIDRL Field Descriptions Field SCIDRH 7 R8 SCIDRH 6 T8 SCIDRL 7:0 R[7:0] T[7:0] Description Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1). R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. MC9S12XDP512 Data Sheet, Rev. 2.17 492 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 11-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. IREN SCI Data Register RXD Infrared Receive Decoder Ir_RXD SCRXD Receive Shift Register RE R16XCLK Receive and Wakeup Control RWU LOOPS RSRC M Baud Rate Generator WAKE Data Format Control ILT PE SBR12:SBR0 PT TCIE TE ÷16 Transmit Control LOOPS SBK RSRC T8 Transmit Shift Register SCI Data Register RXEDGIE Active Edge Detect Break Detect BKDIE TC TDRE TC TDRE SCI Interrupt Request R8 NF FE PF RAF IDLE RDRF OR RIE TIE RDRF/OR RXEDGIF BKDIF RXD BERRIE Infrared Transmit Encoder R32XCLK TNP[1:0] IREN BERRM[1:0] Ir_TXD TXD ILIE IDLE Bus Clock BKDFE SCTXD R16XCLK LIN Transmit BERRIF Collision Detect Figure 11-14. Detailed SCI Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 493 Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock. 11.4.1.1 Infrared Transmit Encoder The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set. 11.4.1.2 Infrared Receive Decoder The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification. 11.4.2 LIN Support This module provides some basic support for the LIN protocol. At first this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions. MC9S12XDP512 Data Sheet, Rev. 2.17 494 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 11-15 below. 8-Bit Data Format (Bit M in SCICR1 Clear) Start Bit Possible Parity Bit Bit 6 Bit 7 STOP Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Next Start Bit Standard SCI Data Infrared SCI Data 9-Bit Data Format (Bit M in SCICR1 Set) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 POSSIBLE PARITY Bit Bit 8 STOP Bit NEXT START Bit Standard SCI Data Infrared SCI Data Figure 11-15. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. Table 11-13. Example of 8-Bit Data Formats Start Bit 1 1 1 1 Data Bits 8 7 7 Address Bits 0 0 1 1 Parity Bits 0 1 0 Stop Bit 1 1 1 The address bit identifies the frame as an address character. See Section 11.4.6.6, “Receiver Wakeup”. When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 11-14. Example of 9-Bit Data Formats Start Bit 1 1 1 Data Bits 9 8 8 Address Bits 0 0 1 1 Parity Bits 0 1 0 Stop Bit 1 1 1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 495 Chapter 11 Serial Communication Interface (S12SCIV5) 1 The address bit identifies the frame as an address character. See Section 11.4.6.6, “Receiver Wakeup”. 11.4.4 Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: • Integer division of the bus clock may not give the exact target frequency. Table 11-15 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (16 * SCIBR[12:0]) Table 11-15. Baud Rates (Example: Bus Clock = 25 MHz) Bits SBR[12:0] 41 81 163 326 651 1302 2604 5208 Receiver Clock (Hz) 609,756.1 308,642.0 153,374.2 76,687.1 38,402.5 19,201.2 9600.6 4800.0 Transmitter Clock (Hz) 38,109.8 19,290.1 9585.9 4792.9 2400.2 1200.1 600.0 300.0 Target Baud Rate 38,400 19,200 9,600 4,800 2,400 1,200 600 300 Error (%) .76 .47 .16 .15 .01 .01 .00 .00 MC9S12XDP512 Data Sheet, Rev. 2.17 496 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.5 Transmitter Internal Bus Bus Clock Baud Divider ÷ 16 SCI Data Registers SBR12:SBR0 Start Stop 11-Bit Transmit Register 8 MSB 7 6 5 4 3 2 1 0 TXPOL SCTXD M H L T8 Load from SCIDR Preamble (All 1s) Break (All 0s) LOOP CONTROL To Receiver PT TDRE IRQ Parity Generation TIE TDRE Shift Enable PE LOOPS RSRC Transmitter Control TC IRQ TC TCIE TE SBK BERRM[1:0] BERRIF BER IRQ TCIE Transmit Collision Detect SCTXD SCRXD (From Receiver) Figure 11-16. Transmitter Block Diagram 11.4.5.1 Transmitter Character Length The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 11.4.5.2 Character Transmission To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 497 Chapter 11 Serial Communication Interface (S12SCIV5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS,RSRC,M,WAKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. MC9S12XDP512 Data Sheet, Rev. 2.17 498 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L. 11.4.5.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0): • Sets the framing error flag, FE • Sets the receive data register full flag, RDRF • Clears the SCI data registers (SCIDRH/L) • May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios1 The break is detected right from a start bit or is detected during a byte reception. • Sets the break detect interrupt flag, BLDIF • Does not change the data register full flag, RDRF or overrun flag OR • Does not change the framing error flag FE, parity error flag PE. • Does not clear the SCI data registers (SCIDRH/L) • May set noise flag NF, or receiver active flag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 499 Chapter 11 Serial Communication Interface (S12SCIV5) Figure 11-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF flag will be set. Start Bit Position Stop Bit Position BRKDIF = 1 RXD_1 Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 . . . FE = 1 RXD_2 BRKDIF = 1 Zero Bit Counter 1 2 3 4 5 6 7 8 9 10 ... Figure 11-17. Break Detection if BRKDFE = 1 (M = 0) 11.4.5.4 Idle Characters An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin MC9S12XDP512 Data Sheet, Rev. 2.17 500 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.5.5 LIN Transmit Collision Detection LIN Physical Interface This module allows to check for collisions on the LIN bus. Synchronizer Stage Receive Shift Register Compare Bit Error Bus Clock RXD Pin LIN Bus Sample Point Transmit Shift Register TXD Pin Figure 11-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and flag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens: • The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1) • The transmission is aborted and the byte in transmit buffer is discarded. • the transmit data register empty and the transmission complete flag will be set • The bit error interrupt flag, BERRIF, will be set. • No further transmissions will take place until the BERRIF is cleared. 0 1 2 3 4 5 6 7 8 Sampling Begin 9 Sampling End 10 11 12 Sampling Begin 13 Sampling End 14 15 0 Output Transmit Shift Register Input Receive Shift Register BERRM[1:0] = 0:1 BERRM[1:0] = 1:1 Compare Sample Points Figure 11-19. Timing Diagram Bit Error Detection If the bit error detect feature is disabled, the bit error interrupt flag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt flag may be set incorrectly. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 501 Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6 Receiver Internal Bus SBR12:SBR0 SCI Data Register 11-Bit Receive Shift Register 8 7 6 All 1s 5 4 3 2 1 0 RXPOL SCRXD From TXD Pin or Transmitter Loop Control Data Recovery H RE RAF MSB LOOPS RSRC FE M WAKE ILT PE PT Wakeup Logic NF PE RWU Parity Checking R8 IDLE ILIE Idle IRQ Start L RDRF/OR IRQ BRKDFE Stop Bus Clock Baud Divider RDRF OR RIE Break IRQ Break Detect Logic BRKDIF BRKDIE Active Edge Detect Logic RXEDGIF RXEDGIE RX Active Edge IRQ Figure 11-20. SCI Receiver Block Diagram 11.4.6.1 Receiver Character Length The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8). 11.4.6.2 Character Reception During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set, MC9S12XDP512 Data Sheet, Rev. 2.17 502 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 11.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 11-21) is re-synchronized: • After every start bit • After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Start Bit RXD Samples 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB Start Bit Qualification Start Bit Verification Data Sampling RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT10 RT11 RT12 RT13 RT14 RT15 RT CLock Count Reset RT Clock RT16 RT4 Figure 11-21. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 11-16 summarizes the results of the start bit verification samples. Table 11-16. Start Bit Verification RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 503 Chapter 11 Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-17 summarizes the results of the data bit samples. Table 11-17. Data Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-18 summarizes the results of the stop bit samples. Table 11-18. Stop Bit Recovery RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 MC9S12XDP512 Data Sheet, Rev. 2.17 504 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. Start Bit RXD Samples 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 LSB RT6 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock RT16 RT3 RT7 Figure 11-22. Start Bit Search Example 1 In Figure 11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit RXD Samples 1 1 1 1 1 0 1 0 0 0 0 0 RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT Clock Count Reset RT Clock RT5 Figure 11-23. Start Bit Search Example 2 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 505 Chapter 11 Serial Communication Interface (S12SCIV5) In Figure 11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Perceived Start Bit Actual Start Bit RXD Samples 1 1 1 0 0 1 0 0 0 0 LSB RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 LSB RT2 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock RT16 RT9 RT3 Figure 11-24. Start Bit Search Example 3 Figure 11-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. Perceived and Actual Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 1 0 RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock Figure 11-25. Start Bit Search Example 4 MC9S12XDP512 Data Sheet, Rev. 2.17 506 Freescale Semiconductor RT16 RT1 Chapter 11 Serial Communication Interface (S12SCIV5) Figure 11-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 0 1 1 0 No Start Bit Found 0 0 0 0 0 0 0 LSB RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 LSB RT2 RT Clock Count Reset RT Clock RT1 RT3 Figure 11-26. Start Bit Search Example 5 In Figure 11-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. Start Bit RXD Samples 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT Clock Count Reset RT Clock RT16 RT1 Figure 11-27. Start Bit Search Example 6 11.4.6.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 507 Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 11.4.6.5.1 Slow Data Tolerance Figure 11-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB Stop Receiver RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 Data Samples Figure 11-28. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 11-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 – 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 11-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 – 160) / 167) X 100 = 4.19% MC9S12XDP512 Data Sheet, Rev. 2.17 508 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.5.2 Fast Data Tolerance Figure 11-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame Receiver RT Clock RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 Data Samples Figure 11-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 11-29, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 – 154) / 160) x 100 = 3.75% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 11-29, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 – 170) /176) x 100 = 3.40% 11.4.6.6 Receiver Wakeup To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 509 Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 11.4.6.6.2 Address Mark Wakeup (WAKE = 1) In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately. 11.4.7 Single-Wire Operation Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. Transmitter TXD Receiver RXD Figure 11-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) MC9S12XDP512 Data Sheet, Rev. 2.17 510 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set. 11.4.8 Loop Operation In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Transmitter TXD Receiver RXD Figure 11-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same. 11.5 11.5.1 Initialization/Application Information Reset Initialization See Section 11.3.2, “Register Descriptions”. 11.5.2 11.5.2.1 Modes of Operation Run Mode Normal mode of operation. To initialize a SCI transmission, see Section 11.4.5.2, “Character Transmission”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 511 Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. 11.5.2.3 Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode. 11.5.3 Interrupt Operation This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 11-19 lists the eight interrupt sources of the SCI. Table 11-19. SCI Interrupt Sources Interrupt TDRE TC RDRF OR IDLE Source SCISR1[7] SCISR1[6] SCISR1[5] SCISR1[3] SCISR1[4] ILIE RXEDGIE BERRIE BRKDIE Local Enable TIE TCIE RIE Description Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. Active high level. Indicates that a transmit is complete. Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. Active high level. This interrupt indicates that an overrun condition has occurred. Active high level. Indicates that receiver input has become idle. Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. Active high level. Indicates that a break character has been received. RXEDGIF SCIASR1[7] BERRIF BKDIF SCIASR1[1] SCIASR1[0] MC9S12XDP512 Data Sheet, Rev. 2.17 512 Freescale Semiconductor Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 11.5.3.1.1 TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL). 11.5.3.1.2 TC Description The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC flag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent. 11.5.3.1.3 RDRF Description The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 11.5.3.1.4 OR Description The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL). 11.5.3.1.5 IDLE Description The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 513 Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 11.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if the bit error detect feature is disabled. 11.5.3.1.8 BKDIF Description The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled. 11.5.4 Recovery from Wait Mode The SCI interrupt request can be used to bring the CPU out of wait mode. 11.5.5 Recovery from Stop Mode An active edge on the receive input can be used to bring the CPU out of stop mode. MC9S12XDP512 Data Sheet, Rev. 2.17 514 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 12.1.1 Glossary of Terms SPI SS SCK MOSI MISO MOMI SISO Serial Peripheral Interface Slave Select Serial Clock Master Output, Slave Input Master Input, Slave Output Master Output, Master Input Slave Input, Slave Output 12.1.2 Features The SPI includes these distinctive features: • Master mode and slave mode • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode 12.1.3 Modes of Operation The SPI functions in three modes: run, wait, and stop. • Run mode This is the basic mode of operation. • Wait mode MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 515 Chapter 12 Serial Peripheral Interface (S12SPIV4) • SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 12.4.7, “Low Power Mode Options”. 12.1.4 Block Diagram Figure 12-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic. MC9S12XDP512 Data Sheet, Rev. 2.17 516 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register SPIF MODF SPTEF Interrupt Control SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler Clock Select SPPR 3 SPR 3 Shifter SPI Baud Rate Register LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB LSBFE=0 LSBFE=1 LSBFE=0 LSB LSBFE=1 Data Out Data In Baud Rate Shift Clock Sample Clock Slave Control CPOL CPHA MOSI Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Master Control Port Control Logic SCK SS Figure 12-1. SPI Block Diagram 12.2 External Signal Description This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins. 12.2.1 MOSI — Master Out/Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave. 12.2.2 MISO — Master In/Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 517 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 12.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 12.3 12.3.1 Memory Map and Register Definition Module Memory Map This section provides a detailed description of address space and registers used by the SPI. The memory map for the SPI is given in Figure 12-2. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. Register Name SPICR1 R W R W R W R W R W R W R W R W Bit 7 SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR 3 CPOL 2 CPHA 0 1 SSOE Bit 0 LSBFE SPICR2 MODFEN BIDIROE 0 SPISWAI SPC0 SPIBR 0 SPPR2 0 SPPR1 SPTEF SPPR0 MODF SPR2 0 SPR1 0 SPR0 0 SPISR SPIF 0 Reserved SPIDR Bit 7 6 5 4 3 2 1 Bit 0 Reserved Reserved = Unimplemented or Reserved Figure 12-2. SPI Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 518 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 519 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.1 R W Reset SPI Control Register 1 (SPICR1) 7 6 5 4 3 2 1 0 SPIE 0 SPE 0 SPTIE 0 MSTR 0 CPOL 0 CPHA 1 SSOE 0 LSBFE 0 Figure 12-3. SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Table 12-1. SPICR1 Field Descriptions Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock. Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 12-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first. 5 SPTIE 4 MSTR 3 CPOL 2 CPHA 1 SSOE 0 LSBFE MC9S12XDP512 Data Sheet, Rev. 2.17 520 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-2. SS Input / Output Selection MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS is slave select output Slave Mode SS input SS input SS input SS input 12.3.2.2 R W Reset SPI Control Register 2 (SPICR2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 MODFEN 0 BIDIROE 0 0 0 SPISWAI 0 SPC0 0 = Unimplemented or Reserved Figure 12-4. SPI Control Register 2 (SPICR2) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 12-3. SPICR2 Field Descriptions Field 4 MODFEN Description Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to Table 12-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI. 1 SS port pin with MODF feature. Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 12-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 3 BIDIROE 1 SPISWAI 0 SPC0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 521 Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-4. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Out Slave In Slave I/O Slave In MOSI not used by SPI Master In MISO not used by SPI Master Out Master In Master I/O 12.3.2.3 R W Reset SPI Baud Rate Register (SPIBR) 7 6 5 4 3 2 1 0 0 0 SPPR2 0 SPPR1 0 SPPR0 0 0 0 SPR2 0 SPR1 0 SPR0 0 = Unimplemented or Reserved Figure 12-5. SPI Baud Rate Register (SPIBR) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 12-5. SPIBR Field Descriptions Field 6–4 SPPR[2:0] 2–0 SPR[2:0] Description SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 12-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in Table 12-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 12-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 12-2 NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. MC9S12XDP512 Data Sheet, Rev. 2.17 522 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Baud Rate Divisor 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 Baud Rate 12.5 MHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 4.16667 MHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 523 Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Baud Rate Divisor 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 19.53 kHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 16.28 kHz 1.78571 MHz 892.86 kHz 446.43 kHz 223.21 kHz 111.61 kHz 55.80 kHz 27.90 kHz 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 12.21 kHz MC9S12XDP512 Data Sheet, Rev. 2.17 524 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.4 R W Reset SPI Status Register (SPISR) 7 6 5 4 3 2 1 0 SPIF 0 0 0 SPTEF 1 MODF 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-6. SPI Status Register (SPISR) Read: Anytime Write: Has no effect Table 12-7. SPISR Field Descriptions Field 7 SPIF Description SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI data register. 0 Transfer not yet complete. 1 New data copied to SPIDR. SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR must be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI data register without reading SPTEF = 1, is effectively ignored. 0 SPI data register not empty. 1 SPI data register empty. Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 12.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. 5 SPTEF 4 MODF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 525 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.5 R W Reset SPI Data Register (SPIDR) 7 6 5 4 3 2 1 0 Bit 7 0 6 0 5 0 4 0 3 0 2 0 2 0 Bit 0 0 Figure 12-7. SPI Data Register (SPIDR) Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and a byte has been received, the received byte is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second byte has been received, the second received byte is kept as valid byte in the receive shift register until the start of another transmission. The byte in the SPIDR does not change. If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 12-8). If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of a third transmission, the byte in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 12-9). MC9S12XDP512 Data Sheet, Rev. 2.17 526 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data A Data B Data C SPIF SPI Data Register Data A Data B Data C = Unspecified = Reception in progress Figure 12-8. Reception with SPIF Serviced in Time Data A Received Data B Received Data C Received Data B Lost SPIF Serviced Receive Shift Register Data A Data B Data C SPIF SPI Data Register Data A Data C = Unspecified = Reception in progress Figure 12-9. Reception with SPIF Serviced too Late MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 527 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as: • Slave select (SS) • Serial clock (SCK) • Master out/slave in (MOSI) • Master in/slave out (MISO) The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 12.4.3, “Transmission Formats”). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided. MC9S12XDP512 Data Sheet, Rev. 2.17 528 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. • Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. • MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. • SS pin If MODFEN and SSOE are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 12.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 529 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • Serial clock In slave mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. • SS pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the first bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF flag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided. MC9S12XDP512 Data Sheet, Rev. 2.17 530 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI SHIFT REGISTER SHIFT REGISTER VDD Figure 12-10. Master/Slave Transfer Block Diagram 12.4.3.1 Clock Phase and Polarity Controls Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. 12.4.3.2 CPHA = 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 531 Chapter 12 Serial Peripheral Interface (S12SPIV4) Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master. • The SPIF flag in the SPI status register is set, indicating that the transfer is complete. Figure 12-11 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT Bit 1 Bit 6 tI tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. LSB Minimum 1/2 SCK for tT, tl, tL MSB Figure 12-11. SPI Clock Format 0 (CPHA = 0) MC9S12XDP512 Data Sheet, Rev. 2.17 532 Freescale Semiconductor If next transfer begins here SAMPLE I MOSI/MISO Chapter 12 Serial Peripheral Interface (S12SPIV4) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time. 12.4.3.3 CPHA = 1 Transfer Format Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th SCK edge: • Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. • The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 12-12 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 533 Chapter 12 Serial Peripheral Interface (S12SPIV4) End of Idle State SCK Edge Number SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3 Begin 4 5 6 7 Transfer 8 9 10 11 12 End 13 14 15 16 Begin of Idle State CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL tT tI tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Minimum leading time before the first SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers Figure 12-12. SPI Clock Format 1 (CPHA = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. • Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI data register, this byte is sent out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge. MC9S12XDP512 Data Sheet, Rev. 2.17 534 Freescale Semiconductor If next transfer begins here SAMPLE I MOSI/MISO Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 12-3. BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 12-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 12-6 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Specification in the Electricals chapter of this data sheet. 12.4.5 12.4.5.1 Special Features SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 12-2. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 535 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 12-8). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI. Table 12-8. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 Serial Out MOSI Serial In SPI MOSI Normal Mode SPC0 = 0 SPI Serial In MISO Serial Out MISO Serial Out MOMI BIDIROE Serial In BIDIROE SPI Serial Out SISO Bidirectional Mode SPC0 = 1 SPI Serial In The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. • The SCK is output for the master mode and input for the slave mode. • The SS is the input or output for the master mode, and it is always the input for the slave mode. • The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose. MC9S12XDP512 Data Sheet, Rev. 2.17 536 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.6 Error Conditions The SPI has one error condition: • Mode fault error 12.4.6.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost. 12.4.7 12.4.7.1 Low Power Mode Options SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 537 Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.7.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF flag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur. – 12.4.7.3 SPI in Stop Mode Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit. MC9S12XDP512 Data Sheet, Rev. 2.17 538 Freescale Semiconductor Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.7.4 Reset The reset values of registers and signals are described in Section 12.3, “Memory Map and Register Definition”, which details the registers and their bit fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. 12.4.7.5 Interrupts The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request. 12.4.7.5.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 12-2). After MODF is set, the current transfer is aborted and the following bit is changed: • MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”. 12.4.7.5.2 SPIF SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”. 12.4.7.5.3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described in Section 12.3.2.4, “SPI Status Register (SPISR)”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 539 Chapter 12 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev. 2.17 540 Freescale Semiconductor Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.1 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 13-1 for a simplified block diagram. 13.1.1 Glossary Acronyms and Abbreviations PIT ISR CCR SoC Periodic Interrupt Timer Interrupt Service Routine Condition Code Register System on Chip clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit modulus down-counters. micro time bases 13.1.2 Features The PIT includes these features: • Four timers implemented as modulus down-counters with independent time-out periods. • Time-out periods selectable between 1 and 224 bus clock cycles. Time-out equals m*n bus clock cycles with 1 IPL[2:0]). 3. The I bit in the condition code register (CCR) of the CPU must be cleared. 4. There is no SWI, TRAP, or XIRQ request pending. NOTE All non I bit maskable interrupt requests always have higher priority than I bit maskable interrupt requests. If an I bit maskable interrupt request is interrupted by a non I bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 607 Chapter 16 Interrupt (S12XINTV1) 16.4.2.1 Interrupt Priority Stack The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction. 16.4.3 XGATE Requests The XINT module processes all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below. 16.4.3.1 XGATE Request Prioritization An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the associated configuration register is set to 1 (please refer to Section 16.3.1.4, “Interrupt Request Configuration Data Registers (INT_CFDATA0–7)”). The priority level setting (PRIOLVL) for this channel becomes the DMA priority which will be used to determine the highest priority DMA request to be serviced next by the XGATE module. Additionally, DMA interrupts may be raised by the XGATE module by setting one or more of the XGATE channel interrupt flags (using the SIF instruction). This will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST bits are set. The shared interrupt priority for the DMA interrupt requests is taken from the XGATE interrupt priority configuration register (please refer to Section 16.3.1.2, “XGATE Interrupt Priority Configuration Register (INT_XGPRIO)”). If more than one DMA interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization. 16.4.4 Priority Decoders The XINT module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. There are two priority decoders, one for each interrupt request target (CPU, XGATE module). The function of both priority decoders is basically the same with one exception: the priority decoder for the XGATE module does not take the current interrupt processing level into account because XGATE requests cannot be nested. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request. MC9S12XDP512 Data Sheet, Rev. 2.17 608 Freescale Semiconductor Chapter 16 Interrupt (S12XINTV1) If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)). 16.4.5 Reset Exception Requests The XINT supports three system reset exception request types (please refer to CRG for details): 1. Pin reset, power-on reset, low-voltage reset, or illegal address reset 2. Clock monitor reset request 3. COP watchdog reset request 16.4.6 Exception Priority The priority (from highest to lowest) and address of all exception vectors issued by the XINT upon request by the CPU is shown in Table 16-8. Table 16-8. Exception Vector Map and Priority Vector Address1 0xFFFE 0xFFFC 0xFFFA (Vector base + 0x00F8) (Vector base + 0x00F6) (Vector base + 0x00F4) (Vector base + 0x00F2) Source Pin reset, power-on reset, low-voltage reset, illegal address reset Clock monitor reset COP watchdog reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ interrupt request IRQ interrupt request (Vector base + 0x00F0–0x0012) Device specific I bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order) (Vector base + 0x0010) 1 Spurious interrupt 16 bits vector address based MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 609 Chapter 16 Interrupt (S12XINTV1) 16.5 16.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests. • If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and configure the XGATE module (please refer the XGATE Block Guide for details). • Enable I maskable interrupts by clearing the I bit in the CCR. • Enable the X maskable interrupt by clearing the X bit in the CCR (if required). 16.5.2 Interrupt Nesting The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I bit maskable interrupt requests handled by the CPU. • I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 16-14 for an example using up to three nested interrupt requests). I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can interrupt the current ISR. An ISR of an interruptible I bit maskable interrupt request could basically look like this: • Service interrupt, e.g., clear interrupt flags, copy data, etc. • Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI MC9S12XDP512 Data Sheet, Rev. 2.17 610 Freescale Semiconductor Chapter 16 Interrupt (S12XINTV1) 0 Stacked IPL 0 4 0 0 0 IPL in CCR 7 6 5 4 Processing Levels 3 2 1 0 0 4 7 4 3 1 0 L7 RTI RTI L3 (Pending) L4 L1 (Pending) Reset RTI RTI Figure 16-14. Interrupt Processing Example 16.5.3 16.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode: • If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU. • An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the current IPL in CCR. • I bit maskable interrupt requests which are configured to be handled by the XGATE are not capable of waking up the CPU. An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set. 16.5.3.2 XGATE Wake Up from Stop or Wait Mode Interrupt request channels which are configured to be handled by the XGATE are capable of waking up the XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 611 Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.17 612 Freescale Semiconductor Chapter 17 Memory Mapping Control (S12XMMCV2) 17.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 1-1. The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses including internal memories and peripherals are controlled in this module. The local address space for each master is translated to a global memory space. 17.1.1 Features The main features of this block are: • Paging capability to support a global 8 Mbytes memory address space • Bus arbitration between the masters CPU, BDM, and XGATE • Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 1-1) • Resolution of target bus access collision • Access restriction control from masters to some targets (e.g., RAM write access protection for user specified areas) • MCU operation mode control • MCU security control • Separate memory map schemes for each master CPU, BDM, and XGATE • ROM control bits to enable the on-chip FLASH or ROM selection • Port replacement registers access control • Generation of system reset when CPU accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes 17.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the MMC. 17.1.2.1 • Power Saving Modes Run mode MMC is functional during normal run mode. 1. Resources are also called targets. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 613 Chapter 17 Memory Mapping Control (S12XMMCV2) • • Wait mode MMC is functional during wait mode. Stop mode MMC is inactive during stop mode. 17.1.2.2 • • Functional Modes • Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus. Emulation modes External bus is active to emulate via an external tool the normal expanded or the normal single chip mode. 17.1.3 Block Diagram Figure 1-1 shows a block diagram of the MMC. BDM CPU XGATE EBI MMC Address Decoder & Priority DBG EEPROM Target Bus Controller FLASH RAM Peripherals Figure 17-1. MMC Block Diagram 17.2 External Signal Description The user is advised to refer to the SoC Guide for port configuration and location of external bus signals. Some pins may not be bonded out in all implementations. MC9S12XDP512 Data Sheet, Rev. 2.17 614 Freescale Semiconductor Chapter 17 Memory Mapping Control (S12XMMCV2) Table 1-2 and Table 1-3 outline the pin names and functions. It also provides a brief description of their operation. Table 17-1. External Input Signals Associated with the MMC Signal MODC MODB MODA EROMCTL ROMCTL I/O I I I I I Description Mode input Mode input Mode input EROM control input ROM control input Availability Latched after RESET (active low) Table 17-2. External Output Signals Associated with the MMC Available in Modes Signal CS0 CS1 CS2 CS3 I/O O O O O Description NS Chip select line 0 Chip select line 1 Chip select line 2 Chip select line 3 SS NX ES EX ST (see Table 1-4) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 615 Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3 17.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 1-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address 0x000A Register Name MMCCTL0 R W 0x000B MODE R W 0x0010 GPAGE R W 0x0011 DIRECT R W 0x0012 Reserved R W 0x0013 MMCCTL1 R W 0x0014 Reserved R W 0x0015 Reserved R W 0x0016 RPAGE R W 0x0017 EPAGE R W 0x0030 PPAGE R W 0x0031 Reserved R W = Unimplemented or Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 0 6 0 5 0 4 0 3 CS3E 0 2 CS2E 0 1 CS1E 0 Bit 0 CS0E 0 MODC 0 MODB MODA GP6 GP5 GP4 GP3 GP2 GP1 GP0 DP15 0 DP14 0 DP13 0 DP12 0 DP11 0 DP10 0 DP9 0 DP8 0 EROMON 0 ROMHM 0 ROMON 0 RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 PIX7 0 PIX6 0 PIX5 0 PIX4 0 PIX3 0 PIX2 0 PIX1 0 PIX0 0 Figure 17-2. MMC Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 616 Freescale Semiconductor Chapter 17 Memory Mapping Control (S12XMMCV2) Address 0x011C Register Name RAMWPC R W Bit 7 RPWE 1 6 0 5 0 4 0 3 0 2 0 1 AVIE Bit 0 AVIF 0x011D RAMXGU R W XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 0x011E RAMSHL R W 1 SHL6 SHL5 SHL4 SHL3 SHL2 SHL1 SHL0 0x011F RAMSHU R W 1 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 = Unimplemented or Reserved Figure 17-2. MMC Register Summary 17.3.2 17.3.2.1 Register Descriptions MMC Control Register (MMCCTL0) Address: 0x000A PRR 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 CS3E 0 CS2E 0 CS1E 0 CS0E ROMON1 1. ROMON is bit[0] of the register MMCTL1 (see Figure 1-10) = Unimplemented or Reserved Figure 17-3. MMC Control Register (MMCCTL0) Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other modes the data is read from this register. Write: Anytime. In emulation modes write operations will also be directed to the external bus. Table 17-3. Chip Selects Function Activity Chip Modes Register Bit NS CS3E, CS2E, CS1E, CS0E 1 2 SS Disabled NX Enabled 2 ES Disabled EX Enabled ST Enabled Disabled1 Disabled: feature always inactive. Enabled: activity is controlled by the appropriate register bit value. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 617 Chapter 17 Memory Mapping Control (S12XMMCV2) The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Table 17-4. MMCCTL0 Field Descriptions Field 3–0 CS[3:0]E Description Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0 outputs which are asserted during accesses to specific external addresses. The associated global address ranges are shown in Table 1-6 and Table 1-21 and Figure 1-23. Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test mode. The function disabled in all other operating modes. 0 Chip select is disabled 1 Chip select is enabled Table 17-5. Chip Select Signals Global Address Range 0x00_0800–0x0F_FFFF 0x10_0000–0x1F_FFFF 0x20_0000–0x3F_FFFF 0x40_0000–0x7F_FFFF 1 Asserted Signal CS3 CS2 CS1 CS01 When the internal NVM is enabled (see ROMON in Section 1.3.2.5, “MMC Control Register (MMCCTL1)”) the CS0 is not asserted in the space occupied by this on-chip memory block. MC9S12XDP512 Data Sheet, Rev. 2.17 618 Freescale Semiconductor Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.2 Mode Register (MODE) Address: 0x000B PRR 7 6 5 4 3 2 1 0 R W Reset MODC MODC1 MODB MODB1 MODA MODA1 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 1-2). = Unimplemented or Reserved Figure 17-4. Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register. Write: Only if a transition is allowed (see Figure 1-5). In emulation modes write operations will be also directed to the external bus. The MODE bits of the MODE register are used to establish the MCU operating mode. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Table 17-6. MODE Field Descriptions Field 7–5 MODC, MODB, MODA Description Mode Select Bits — These bits control the current operating mode during RESET high (inactive). The external mode pins MODC, MODB, and MODA determine the operating mode during RESET low (active). The state of the pins is latched into the respective register bits after the RESET signal goes inactive (see Figure 1-5). Write restrictions exist to disallow transitions between certain modes. Figure 1-5 illustrates all allowed mode changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to these register bits except in special modes. Both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to emulation expanded mode are only executed by writing a value of 0b101 (write once). Writing any other value will not change the MODE bits, but will block further writes to these register bits. Changes of operating modes are not allowed when the device is secured, but it will block further writes to these register bits except in special modes. In emulation modes reading this address returns data from the external bus which has to be driven by the emulator. It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value corresponding to normal single chip mode while the device is in emulation single-chip mode or a value corresponding to normal expanded mode while the device is in emulation expanded mode). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 619 Chapter 17 Memory Mapping Control (S12XMMCV2) RESET 010 Special Test (ST) 010 10 10 0 1 1 01 00 1 Normal Expanded (NX) 101 010 000 RESET 100 110 111 Normal Single-Chip (NS) 100 101 101 RESET 001 RESET 10 1 Emulation Single-Chip (ES) 001 101 Emulation Expanded (EX) 011 011 RESET 10 0 Special Single-Chip (SS) 000 000 RESET Transition done by external pins (MODC, MODB, MODA) RESET Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, MODA) pin values. Do not use. (Reserved for future use). Figure 17-5. Mode Transition Diagram when MCU is Unsecured MC9S12XDP512 Data Sheet, Rev. 2.17 620 Freescale Semiconductor 01 00 1 1 Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.3 Global Page Index Register (GPAGE) Address: 0x0010 7 6 5 4 3 2 1 0 R W Reset 0 0 GP6 0 GP5 0 GP4 0 GP3 0 GP2 0 GP1 0 GP0 0 = Unimplemented or Reserved Figure 17-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used only when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see Figure 1-7). CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Global Address [22:0] Bit22 Bit16 Bit15 Bit 0 GPAGE Register [6:0] CPU Address [15:0] Figure 17-7. GPAGE Address Mapping Table 17-7. GPAGE Field Descriptions Field 6–0 GP[6:0] Description Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is to be accessed. Example 17-1. This example demonstrates usage of the GPAGE register LDAADR MOVB GLDAA EQU $5000 #$14, GPAGE >LDAADR ;Initialize LDADDR to the value of $5000 ;Initialize GPAGE register with the value of $14 ;Load Accu A from the global address $14_5000 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 621 Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.4 Direct Page Register (DIRECT) Address: 0x0011 7 6 5 4 3 2 1 0 R W Reset DP15 0 DP14 0 DP13 0 DP12 0 DP11 0 DP10 0 DP9 0 DP8 0 Figure 17-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the direct page within the memory map. Table 17-8. DIRECT Field Descriptions Field 7–0 DP[15:8] Description Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. The bits from this register form bits [15:8] of the address (see Figure 1-9). CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Global Address [22:0] Bit22 Bit16 Bit15 Bit8 Bit7 Bit0 DP [15:8] CPU Address [15:0] Figure 17-9. DIRECT Address Mapping Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global instruction in direct addressing mode or by the appropriate local address to the global address expansion (refer to Expansion of the CPU Local Address Map). Example 17-2. This example demonstrates usage of the Direct Addressing Mode by a global instruction LDAADR MOVB MOVB GLDAA EQU $0000 #$80,DIRECT #$14,GPAGE CompBD_Addr) In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. In forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to 0x7FFFFF or lower range limit to 0x000000 respectively. When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR register and hence vector address can be modified. 19.4.3 Trigger Modes Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections. 19.4.3.1 Trigger On Comparator Match If a comparator match occurs, a trigger occurs to initiate a transition to another state sequencer state and the corresponding flags in DBGSR are set. For a comparator match to trigger firstly the comparator must be enabled by setting the COMPE bit in the corresponding comparator control register. Secondly the state control register for the current state must enable the match for that state. The state control registers allow for different matches to be enabled in each of the states 1 to 3. 19.4.3.2 Trigger On Comparator Related Taghit If either a CPU or XGATE taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the DBG must first generate tags based on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU/XGATE. 19.4.3.3 External Tag Trigger In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device emulation modes. MC9S12XDP512 Data Sheet, Rev. 2.17 718 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) 19.4.3.4 Trigger On XGATE S/W Breakpoint Request The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU immediately independent of DBG settings. If the debug module is armed triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun using begintrigger, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1 determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the XGATE requested breakpoint causes the system to enter BDM mode or initiate a software interrupt (SWI). 19.4.3.5 Immediate Trigger At any time independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. This triggers the state sequencer into the final state and issues a forced breakpoint request to both CPU and XGATE. 19.4.3.6 Trigger Priorities In case of simultaneous triggers, the priority is resolved according to Table 19-38. The lower priority trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. The trigger priorities described in Table 19-38 dictate that in the case of simultaneous matches, the match on the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When configured for range modes a simultaneous match of comparators A and C generates an active match0 while match2 is suppressed. Table 19-38. Trigger Priorities Priority Highest Source XGATE TRIG External TAGHI/TAGLO Match0 (force or tag hit) Match1 (force or tag hit) Match2 (force or tag hit) Lowest Match3 (force or tag hit) Action Immediate forced breakpoint......(Tracing terminated immediately). Enter final state Enter State0 Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 719 Chapter 19 Debug (S12XDBGV2) 19.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session complete (disarm) Final State ARM=0 State3 State2 Figure 19-23. State Sequencer Diagram The state sequence control allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then State1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. From final state the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, the final state is entered and tracing starts immediately if the TSOURCE bits are configured for tracing. A tag hit through TAGHI/TAGLO causes a breakpoint, if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits TALIGN[1:0]. Furthermore, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers independent of the state sequencer state. Thus it is possible to generate an immediate breakpoint on selected channels, while a state sequencer transition can be initiated by a match on other channels. An XGATE S/W breakpoint request, if enabled causes a transition to the final state and generates a breakpoint request to the CPU immediately. If neither tracing nor breakpoints are enabled then, when a forced match triggers to final state, it can only be returned to the disarmed state0 by clearing the ARM bit by software. This also applies to the case that BDM breakpoints are enabled, but the BDM is disabled. Furthermore if neither tracing nor breakpoints are enabled, forced triggers on channels with BRK set cause a transition to the state determined by the state sequencer as if the BRK bit were not being used. If neither tracing nor breakpoints are enabled then when a tagged match triggers to final state, the state sequencer returns to the disarmed state0. MC9S12XDP512 Data Sheet, Rev. 2.17 720 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) 19.4.4.1 Final State On entering final state a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 19.3.1.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. 19.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 64-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The CPU accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace buffer line is read via the CPU, an internal pointer into the RAM is incremented so that the next read will receive fresh information. Data is stored in the format shown in Table 19-39. After each store the counter register bits DBGCNT[6:0] are incremented. Tracing of CPU activity is disabled when the BDM is active but tracing of XGATE activity is still possible. Reading the trace buffer while the BDM is active returns invalid data and the trace buffer pointer is not incremented. 19.4.5.1 Trace Trigger Alignment Using the TALIGN bits (see Section 19.3.1.3, “Debug Trace Control Register (DBGTCR)”) it is possible to align the trigger with the end, the middle or the beginning of a tracing session. If end or mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to final state if end is selected signals the end of the tracing session. The transition to final state if mid is selected signals that another 32 lines will be traced before ending the tracing session. Tracing with begin-trigger starts at the opcode of the trigger. 19.4.5.1.1 Storing with Begin-Trigger Storing with begin-trigger, data is not stored in the trace buffer until the final state is entered. Once the trigger condition is met the DBG module will remain armed until 64 lines are stored in the trace buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger will be stored in the trace buffer. Using begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 19.4.5.1.2 Storing with Mid-Trigger Storing with mid-trigger, data is stored in the trace buffer as soon as the DBG module is armed. When the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the DBG module is disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction the trigger event is not stored in the trace buffer. Using mid-trigger with tagging, if the tagged instruction is about to be executed then the trace MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 721 Chapter 19 Debug (S12XDBGV2) is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 19.4.5.1.3 Storing with End-Trigger Storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the DBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the trace buffer. 19.4.5.2 Trace Modes The DBG module can operate in three trace modes. The mode is selected using the TRCMOD bits in the DBGTCR register. In each mode tracing of XGATE or CPU information is possible. The source for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 19-39. 19.4.5.2.1 Normal Mode In normal mode, change of flow (COF) addresses will be stored. COF addresses are defined as follows for the CPU: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR and CALL instruction. • Destination address of RTI, RTS and RTC instructions • Vector address of interrupts, except for SWI and BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. COF addresses are defined as follows for the XGATE: • Source address of taken conditional branches • Destination address of indexed JAL instructions. • First XGATE code address, determined by the vector contained in the XGATE XGVBR register Change-of-flow addresses stored include the full 23-bit address bus in the case of CPU, the 16-bit address bus for the XGATE module and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. 19.4.5.2.2 Loop1 Mode Loop1 mode, similarly to normal mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the trace buffer resulting from repeated branches. MC9S12XDP512 Data Sheet, Rev. 2.17 722 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below: LOOP INX BRCLR CMPTMP,#$0c,LOOP ;1-byte instruction fetched by 1st P-cycle of BRCLR ;the BRCLR instruction also will be fetched by 1st P-cycle ;of BRCLR ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE LOOP2 BRN* NOP DBNE A,LOOP2 19.4.5.2.3 Detail Mode In detail mode, address and data for all memory and register accesses is stored in the trace buffer. In the case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information byte storage to the trace buffer, for each address byte storage. The information byte indicates the size of access (word or byte), the type of access (read or write). When tracing CPU activity in detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the time of the trace buffer entry. When tracing CPU activity alone in detail mode, the address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses comparators C and D to define an address range inside which CPU activity should be traced (see Table 19-10). Thus, the traced CPU activity can be restricted to register range accesses. When tracing XGATE activity in detail mode, all cycles apart from opcode fetch and free cycles are stored to the trace buffer. Additionally the CPU program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of CPU activity. 19.4.5.3 Trace Buffer Organization The buffer can be used to trace either from CPU, from XGATE or from both sources. An “X” prefix denotes information from the XGATE module, a “C” prefix denotes information from the CPU. ADRH,ADRM,ADRL denote address high, middle and low byte respectively. INF bytes contain control MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 723 Chapter 19 Debug (S12XDBGV2) information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the DBGCNT[0] is incremented after each separate entry. In all other modes, DBGCNT[0] remains cleared while the other DBGCNT bits are incremented on each trace buffer entry. XGATE and S12X_CPU COFs occur independently of each other and the profile of COFs for the 2 sources is totally different. When both sources are being traced in Normal or Loop1 mode, for each single entry from one source, there may be many entries from the other source and vice versa, depending on user code. COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously. If a COF occurs in one source only in a particular cycle, then the trace buffer bytes that are mapped to the other source are redundant. Info byte bit CDV/XDV indicates that no useful information is stored in these bytes. This is the typical case. Only in the rare event that both XGATE and S12X_CPU COF cycles coincide is a valid trace buffer entry for both made, corresponding to the first line for mode "Both Normal/Loop1" in Table 19-39. Single byte data accesses in detail mode are always stored to the low byte of the trace buffer (CDATAL or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2 Table 19-39. Trace Buffer Organization 8-Byte Wide Word Buffer Mode 7 XGATE DETAIL CXINF1 CXINF2 CPU DETAIL Both NORMAL / LOOP1 CXINF1 CXINF2 XINF0 1XINF1 2XINF2 6 CADRH1 CADRH2 CADRH1 CADRH2 5 CADRM1 CADRM2 CADRM1 CADRM2 XADRM0 4 CADRL1 CADRL2 CADRL1 CADRL2 XADRL0 3 XDATAH1 XDATAH2 CDATAH1 CDATAH2 CINF0 CINF1 2 XDATAL1 XDATAL2 CDATAL1 CDATAL2 CADRH0 CADRH1 1 XADRM1 XADRM2 XADRM1 XADRM2 CADRM0 CADRM1 0 XADRL1 XADRL2 XADRL1 XADRL2 CADRL0 CADRL1 XADRM2 XADRM1 XADRM3 CADRH1 CADRH3 CADRM1 CADRM3 XADRL2 XADRL1 XADRL3 CADRL1 CADRL3 CINF2 XINF0 XINF2 CINF0 CINF2 CADRH0 CADRH2 XADRM0 XADRM2 CADRM0 CADRM2 XADRL0 XADRL2 CADRL0 CADRL2 XGATE NORMAL / LOOP1 CPU NORMAL / LOOP1 1 2 XINF1 XINF3 CINF1 CINF3 COF in CPU only. XGATE trace buffer entries in this tracing step are invalid COF in XGATE only. CPU trace buffer entries in this tracing step are invalid MC9S12XDP512 Data Sheet, Rev. 2.17 724 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) 19.4.5.3.1 Information Byte Organization The format of the control information byte for both CPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In normal mode or loop1 mode, tracing of XGATE activity XINF is used to store control information. In normal mode or loop1 mode, tracing of CPU activity CINF is used to store control information. In detail mode, CXINF contains the control information. Bit 7 XSD Bit 6 0 Bit 5 0 Bit 4 XDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 19-24. XGATE Information Byte XINF Table 19-40. XINF Field Descriptions Field 7 XSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in normal and loop1 mode tracing. 0 Source Address 1 Destination Address Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in normal and loop1 mode, to indicate that the XGATE trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid 4 XDV Bit 7 CSD Bit 6 0 Bit 5 0 Bit 4 CDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 19-25. CPU Information Byte CINF Table 19-41. CINF Field Descriptions Field 7 CSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in normal and loop1 mode tracing. 0 Source Address 1 Destination Address Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in normal and loop1 mode, to indicate that the CPU trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid 4 CDV MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 725 Chapter 19 Debug (S12XDBGV2) Bit 7 CFREE Bit 6 CSZ Bit 5 CRW Bit 4 COCF Bit 3 XACK Bit 2 XSZ Bit 1 XRW Bit 0 XOCF Figure 19-26. Information Byte CXINF This describes the format of the information byte used only when tracing from CPU or XGATE in detail mode. When tracing from the CPU in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made by the CPU, while the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The CPU entry stored on the same line is a snapshot of the CPU program counter. In this case the XSZ and XRW bits indicate the type of access being made by the XGATE, while the CFREE and COCF bits indicate if the simultaneous CPU cycle is a free cycle or opcode fetch cycle. Table 19-42. CXINF Field Descriptions Field 7 CREE Description CPU Free Cycle Indicator — This bit indicates if the stored CPU address corresponds to a free cycle. This bit only contains valid information when tracing the XGATE accesses in detail mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing CPU activity in detail mode. 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing CPU activity in detail mode. 0 Write Access 1 Read Access CPU Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle. This bit only contains valid information when tracing the XGATE accesses in detail mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit only contains valid information when tracing the CPU accesses in detail mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains valid information when tracing XGATE activity in detail mode. 0 Word Access 1 Byte Access 6 CSZ 5 CRW 4 COCF 3 XACK 2 XSZ MC9S12XDP512 Data Sheet, Rev. 2.17 726 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) Table 19-42. CXINF Field Descriptions (continued) Field 1 XRW Description Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in detail mode. 0 Read/Write Access 1 Access XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.This bit only contains valid information when tracing the CPU accesses in detail mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle 0 XOCF 19.4.5.3.2 Reading Data from Trace Buffer The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is not armed, is configured for tracing (at least one TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. Multiple writes to the DBGTB are not allowed since they increment the pointer. The trace buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid 64-bit lines can be determined. DBGCNT will not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 19-39. The bytes containing invalid information (shaded in Table 19-39) are also read out. Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the RAM pointer will occur. Reading the trace buffer is not possible if both TSOURCE bits are cleared. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 727 Chapter 19 Debug (S12XDBGV2) 19.4.5.3.3 Trace Buffer Reset State The trace buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. Generally debugging occurrences of system resets is best handled using mid or end-trigger alignment since the reset may occur before the trace trigger, which in the begin-trigger alignment case means no information would be stored in the trace buffer. 19.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. Both CPU and XGATE opcodes can be tagged with the comparator register TAG bits. Using a begin-aligned trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the final state, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Similarly using a mid-aligned trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated. Using an end-aligned trigger, when the tagged instruction is about to be executed and the next transition is to final state then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagged triggering is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. CPU tagging is disabled when the BDM becomes active. Conversely, BDM firmware commands are not processed while tagging is active. XGATE tagging is possible when the BDM is active. MC9S12XDP512 Data Sheet, Rev. 2.17 728 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) 19.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into State0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other. External tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge of the external clock (ECLK) performs the function indicated in the Table 19-43. It is possible to tag both bytes of an instruction word. If a taghit comes from the low or high byte, a breakpoint generated according to the DBGBRK and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag is replaced by a new one Table 19-43. Tag Pin Function TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes 19.4.7 Breakpoints It is possible to select breakpoints to the XGATE and let the CPU continue operation, setting DBGBRK[0], or breakpoints to the CPU and let the XGATE continue operation setting, DBGBRK[1], or a breakpoint to both CPU and XGATE, setting both bits DBGBRK[1:0]. There are several ways to generate breakpoints to the XGATE and CPU modules. • Through XGATE software breakpoint requests. • From comparator channel triggers to final state. • Using software to write to the TRIG bit in the DBGC1 register. • From taghits generated using the external TAGHI and TAGLO pins. 19.4.7.1 XGATE Software Breakpoints The XGATE software breakpoint instruction BRK can request an CPU breakpoint, via the DBG module. In this case, if the XGSBPE bit is set, the DBG module immediately generates a forced breakpoint request to the CPU, the state sequencer is returned to state0 and tracing, if active, is terminated. If configured for begin-trigger and tracing has not yet been triggered from another source, the trace buffer contains no new information. Breakpoint requests from the XGATE module do not depend upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the CPU program flow, but it is necessary to set XGSBPE. Furthermore if a breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an CPU breakpoint, the XGATE program flow stops by default, independent of the DBG module. The user can thus determine if an XGATE breakpoint has occurred by reading out the XGATE program counter over the BDM interface. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 729 Chapter 19 Debug (S12XDBGV2) 19.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If an end aligned trigger is selected or no tracing is enabled, breakpoints can be generated immediately, depending on the state of the DBGBRK[n] bits. If a begin or mid aligned tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus the breakpoint is requested only on completion of the subsequent trace (see Table 19-44). If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment. Table 19-44. Setup for Both XGATE and CPU Breakpoints BRK 0 0 0 0 0 TALIGN 00 00 01 01 10 DBGBRK[n] 0 1 0 1 0 Type of Debug Session Fill trace buffer until trigger (no breakpoints — keep running) Fill trace buffer until trigger, then a breakpoint request occurs Start trace buffer at trigger (no breakpoints — keep running) Start trace buffer at trigger A breakpoint request occurs when trace buffer is full Start trace buffer at trigger End tracing 32 line entries after trigger (no breakpoints — keep running) Start trace buffer at trigger End tracing 32 line entries after trigger Request breakpoint after the 32 further trace buffer entries Terminate tracing immediately on trigger without breakpoint Terminate tracing and generate breakpoint immediately on trigger Reserved 0 10 1 1 1 x 00,01,10 00,01,10 11 0 1 x 19.4.7.3 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the final state is entered. Tracing trigger alignment is defined by the TALIGN bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace. If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the DBG module is disarmed. TRIG bit breakpoints are enabled by setting DBGBRK[n]. 19.4.7.4 Breakpoints via TAGHI Or TAGLO Pin Taghits Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is always end aligned, independent of internal channel trigger alignment configuration. External tag breakpoints are always mapped to the CPU, are only possible in emulation modes and can be enabled by setting DBGBRK[1]. MC9S12XDP512 Data Sheet, Rev. 2.17 730 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) 19.4.7.5 DBG Breakpoint Priorities XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG triggers occur after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a comparator channel whose BRK=0, it has no effect, since tracing has already started. If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer enters State0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of the tracing trigger alignment bits TALIGN[1:0]. 19.4.7.5.1 DBG Breakpoint priorities, mapping and BDM interfacing Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM firmware and S12X breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. Table 19-45. Breakpoint Mapping Summary DBGBRK[1] BDM bit (DBGC1[3])1 (DBGC1[4]) 0 1 1 1 1 1 1 2 BDM enabled X 0 1 0 1 1 BDM active X 0 X 0 0 1 Type of Debug Session No Breakpoint Breakpoint to SWI Illegal Configuration. Do Not Use.2 Illegal Configuration. Do Not Use. 3 Breakpoint to BDM No Breakpoint X 0 0 1 1 1 All sources except XGATE software BKP, which are independent of this bit. The DBGC1[4] bit (BDM) must be set if using the BDM interface together with the DBG module. Failure to set this bit could result in XGATE generated breakpoints to SWI during BDM firmware execution corrupting the S12X PC return address, should the user have entered BDM via the BACKGROUND command or BGND instruction. 3 End aligned tagged Breakpoint to SWI. Begin, Mid aligned and Forced Breakpoints disabled If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in the user’s code. On returning from BDM, the SWI from user code gets executed. BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code and DBG breakpoint could occur simultaneously. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re-triggering a breakpoint. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 731 Chapter 19 Debug (S12XDBGV2) When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. Thus care must be taken to avoid re triggering a breakpoint at the same location. This can be done by reconfiguring the DBG module in the SWI routine, (SWI configuration), or by executing a TRACE command before the GO (BDM configuration) to increment the program flow past the tagged instruction. Comparators should not be configured for the vector address range while tagging, since these addresses are not opcode addresses MC9S12XDP512 Data Sheet, Rev. 2.17 732 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 733 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 734 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 735 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 736 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 737 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 738 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 739 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 740 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 741 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 742 Freescale Semiconductor Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 743 Chapter 19 Debug (S12XDBGV2) MC9S12XDP512 Data Sheet, Rev. 2.17 744 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.1 Introduction The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12XDBG module is optimized for the HCS12X 16-bit architecture and allows debugging of both S12XCPU and XGATE module operations. Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user configures the S12XDBG module for a debugging session over the BDM interface. Once configured the S12XDBG module is armed and the device leaves BDM Mode returning control to the user program, which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured over a serial interface using SWI routines. 20.1.1 Glossary Of Terms COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt. BDM : Background Debug Mode DUG: Device User Guide, describing the features of the device into which the DBG is integrated. WORD: 16 bit data entity Data Line : 64 bit data entity XGATE : S12X family programmable Direct Memory Access Module CPU : S12X_CPU module Tag : Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs. 20.1.2 Overview The comparators monitor the bus activity of the S12XCPU and XGATE modules. When a match occurs the control logic can trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered by the external TAGHI and TAGLO signals, by an XGATE module S/W breakpoint request or an immediate trigger, instigated by writing to the TRIG control bit. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 745 Chapter 20 S12X Debug (S12XDBGV3) Module The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured. 20.1.3 • Features • • • • • • Four comparators (A, B, C, and D) — Comparators A and C compare the full address bus and full 16-bit data bus — Comparators A and C feature a data bus mask register — Comparators B and D compare the full address bus only — Each comparator can be configured to monitor either S12XCPU or XGATE buses — Each comparator features control of R/W and byte/word access cycles — Comparisons can be used as triggers for the state sequencer Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin ≤ Address ≤ Addmax — Outside address range match mode, Address < Addmin or Address > Addmax Two types of triggers — Tagged — This triggers just before a specific instruction begins execution — Force — This triggers on the first instruction boundary after a match occurs. Three types of breakpoints — S12XCPU breakpoint entering BDM on breakpoint (BDM) — S12XCPU breakpoint executing SWI on breakpoint (SWI) — XGATE breakpoint Three trigger modes independent of comparators — External instruction tagging (associated with S12XCPU instructions only) — XGATE S/W breakpoint request — TRIG Immediate software trigger Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 20.4.5.2.1) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored. 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin, End, and Mid alignment of tracing to trigger 20.1.4 Modes of Operation The S12XDBG module can be used in all MCU functional modes. MC9S12XDP512 Data Sheet, Rev. 2.17 746 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled. Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed. The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be generated if the MCU is secure. Table 20-1. Mode Dependent Restriction Summary BDM Enable x 0 0 1 1 BDM Active x 0 1 0 1 MCU Secure 1 0 0 0 0 Yes XGATE only Comparator Matches Enabled Yes Yes Breakpoints Possible Yes Only SWI Yes XGATE only Tagging Possible Yes Yes Yes XGATE only Tracing Possible No Yes Yes XGATE only Active BDM not possible when not enabled 20.1.5 Block Diagram TAGS BREAKPOINT REQUESTS S12XCPU & XGATE TAGHITS EXTERNAL TAGHI / TAGLO XGATE S/W BREAKPOINT REQUEST SECURE COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL MATCH1 MATCH2 MATCH3 TAG & TRIGGER CONTROL LOGIC TRIGGER STATE STATE SEQUENCER STATE S12XCPU BUS XGATE BUS BUS INTERFACE TRACE CONTROL TRIGGER TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 20-1. Debug Module Block Diagram 20.2 External Signal Description The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation modes only. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 747 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-2. External System Pins Associated With S12XDBG Pin Name TAGHI (See DUG) TAGLO (See DUG) TAGLO (See DUG) Pin Functions TAGHI TAGLO Unconditional Tagging Enable Description When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the end of reset enables the Unconditional Tagging function. 20.3 20.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the S12XDBG sub-block is shown in Table 20-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address 0x0020 Name DBGC1 R W R W R W R W R W R W R W R W R W Bit 7 ARM TBF 6 0 TRIG EXTF 5 XGSBPE 0 4 BDM 0 0 3 DBGBRK SSF2 2 1 Bit 0 COMRV SSF1 SSF0 0x0021 DBGSR 0x0022 DBGTCR TSOURCE 0 0 0 TRANGE 0 TRCMOD TALIGN 0x0023 DBGC2 CDCM Bit 11 Bit 10 Bit 9 ABCM Bit 8 0x0024 DBGTBH Bit 15 Bit 14 Bit 13 Bit 12 0x0025 DBGTBL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0026 DBGCNT 0 CNT 0x0027 0x0027 0x00281 0x00282 DBGSCRX DBGMFR 0 0 0 0 0 0 0 0 SC3 MC3 SC2 MC2 SC1 MC1 SC0 MC0 DBGXCTL R (COMPA/C) W DBGXCTL R (COMPB/D) W DBGXAH R W 0 NDB SZ TAG TAG BRK BRK RW RW RWE RWE SRC SRC COMPE COMPE SZE 0 0x0029 Bit 22 21 20 19 18 17 Bit 16 Figure 20-2. Quick Reference to S12XDBG Registers MC9S12XDP512 Data Sheet, Rev. 2.17 748 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module Address 0x002A Name DBGXAM R W R W R W R W R W Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8 0x002B DBGXAL Bit 7 6 5 4 3 2 1 Bit 0 0x002C DBGXDH Bit 15 14 13 12 11 10 9 Bit 8 0x002D DBGXDL Bit 7 6 5 4 3 2 1 Bit 0 0x002E DBGXDHM Bit 15 14 13 12 11 10 9 Bit 8 R Bit 7 6 5 4 3 2 W 1 This represents the contents if the Comparator A or C control register is blended into this address. 2 This represents the contents if the Comparator B or D control register is blended into this address 0x002F DBGXDLM 1 Bit 0 Figure 20-2. Quick Reference to S12XDBG Registers 20.3.2 Register Descriptions This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0] 20.3.2.1 Debug Control Register 1 (DBGC1) Address: 0x0020 7 6 5 4 3 2 1 0 R W Reset ARM 0 0 TRIG 0 XGSBPE 0 BDM 0 0 DBGBRK 0 0 COMRV 0 Figure 20-3. Debug Control Register (DBGC1) Read: Anytime Write: Bits 7, 1, 0 anytime, bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime S12XDBG is not armed. NOTE When disarming the S12XDBG by clearing ARM with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 749 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-3. DBGC1 Field Descriptions Field 7 ARM Description Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the S12XDBG module registers that can be written are ARM and TRIG. 0 Debugger disarmed 1 Debugger armed Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If both TSOURCE bits are clear no tracing is carried out. If tracing has already commenced using BEGINor MID trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit settings, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect. 0 Do not trigger until the state sequencer enters the Final State. 1 Enter Final State immediately and issue forced breakpoint request when trace buffer is full. XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is passed to the S12XCPU. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can request an S12XCPU breakpoint depending on the state of this bit. 0 XGATE S/W breakpoint request is disabled 1 XGATE S/W breakpoint request is enabled Background Debug Mode Enable — This bit determines if a S12X breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). It has no affect on S12XDBG functionality. If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint to either S12XCPU or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 20.4.7 for further details. XGATE software breakpoints are independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the S12XCPU independent of the DBGBRK bit field configuration. See Table 20-4. Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 20-5. 6 TRIG 5 XGSBPE 4 BDM 3–2 DBGBRK 1–0 COMRV Table 20-4. DBGBRK Encoding DBGBRK 00 01 10 11 Resource Halted by Breakpoint No breakpoint generated XGATE breakpoint generated S12XCPU breakpoint generated Breakpoints generated for S12XCPU and XGATE Table 20-5. COMRV Encoding COMRV 00 01 Visible Comparator Comparator A Comparator B Visible Register at 0x0027 DBGSCR1 DBGSCR2 MC9S12XDP512 Data Sheet, Rev. 2.17 750 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-5. COMRV Encoding COMRV 10 11 Visible Comparator Comparator C Comparator D Visible Register at 0x0027 DBGSCR3 DBGMFR MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 751 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.2 Debug Status Register (DBGSR) Address: 0x0021 7 6 5 4 3 2 1 0 R W Reset POR TBF — 0 EXTF 0 0 0 0 0 0 0 0 0 0 0 SSF2 0 0 SSF1 0 0 SSF0 0 0 = Unimplemented or Reserved Figure 20-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 20-6. DBGSR Field Descriptions Field 7 TBF Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0]. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was met since arming. This bit is cleared when ARM in DBGC1 is written to a one. 0 External tag hit has not occurred 1 External tag hit has occurred State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 20-7. 6 EXTF 2–0 SSF[2:0] Table 20-7. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] 000 001 010 011 100 101,110,111 Current State State0 (disarmed) State1 State2 State3 Final State Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 752 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.3 Debug Trace Control Register (DBGTCR) Address: 0x0022 7 6 5 4 3 2 1 0 R W Reset 0 TSOURCE 0 0 TRANGE 0 0 TRCMOD 0 0 TALIGN 0 Figure 20-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Table 20-8. DBGTCR Field Descriptions Field 7–6 TSOURCE 5–4 TRANGE Description Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU system is secured, these bits cannot be set and tracing is inhibited. See Table 20-9. Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when tracing from the S12XCPU in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To use a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state sequence triggers. If the corresponding SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect on the valid address range, memory accesses within the whole memory map are traced. See Table 20-10. Trace Mode Bits — See Section 20.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See Table 20-11. Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. See Table 20-12. 3–2 TRCMOD 1–0 TALIGN Table 20-9. TSOURCE — Trace Source Bit Encoding TSOURCE 00 01 101 11 1 2 1,2 Tracing Source No tracing requested S12XCPU XGATE Both S12XCPU and XGATE No range limitations are allowed. Thus tracing operates as if TRANGE = 00. No Detail Mode tracing supported. If TRCMOD = 10, no information is stored. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 753 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-10. TRANGE Trace Range Encoding TRANGE 00 01 10 11 Tracing Range Trace from all addresses (No filter) Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $7FFFFF Trace only in range from Comparator C to Comparator D Table 20-11. TRCMOD Trace Mode Bit Encoding TRCMOD 00 01 10 11 Description Normal Loop1 Detail Pure PC Table 20-12. TALIGN Trace Alignment Encoding TALIGN 00 01 10 11 Description Trigger at end of stored data Trigger before storing data Trace buffer entries before and after trigger Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 754 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.4 Debug Control Register2 (DBGC2) Address: 0x0023 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 CDCM 0 0 ABCM 0 = Unimplemented or Reserved Figure 20-6. Debug Control Register2 (DBGC2) Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 20-13. DBGC2 Field Descriptions Field 3–2 CDCM[1:0] 1–0 ABCM[1:0] Description C and D Comparator Match Control — These bits determine the C and D comparator match mapping as described in Table 20-14. A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 20-15. Table 20-14. CDCM Encoding CDCM 00 01 10 11 Description Match2 mapped to comparator C match....... Match3 mapped to comparator D match. Match2 mapped to comparator C/D inside range....... Match3 disabled. Match2 mapped to comparator C/D outside range....... Match3 disabled. Reserved Table 20-15. ABCM Encoding ABCM 00 01 10 11 Description Match0 mapped to comparator A match....... Match1 mapped to comparator B match. Match 0 mapped to comparator A/B inside range....... Match1 disabled. Match 0 mapped to comparator A/B outside range....... Match1 disabled. Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 755 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 X X X X X X X Bit 8 X Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 X Bit 0 X Figure 20-7. Debug Trace Buffer Register (DBGTB) Read: Anytime when unlocked and not secured and not armed. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. Table 20-16. DBGTB Field Descriptions Field 15–0 Bit[15:0] Description Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. System resets do not affect the trace buffer contents. The POR state is undefined. MC9S12XDP512 Data Sheet, Rev. 2.17 756 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 7 6 5 4 3 2 1 0 R W Reset POR 0 0 0 — 0 — 0 — 0 CNT — 0 — 0 — 0 — 0 = Unimplemented or Reserved Figure 20-8. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 20-17. DBGCNT Field Descriptions Field 6–0 CNT[6:0] Description Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer. Table 20-18 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. Table 20-18. CNT Decoding Table TBF (DBGSR) 0 0 0 CNT[6:0] 0000000 0000001 0000010 0000100 0000110 .. 1111100 1111110 0000000 0000010 .. .. 1111110 Description No data valid 32 bits of one line valid1 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 63 lines valid 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 64 lines valid, oldest data has been overwritten by most recent data 0 1 1 1 This applies to Normal/Loop1 Modes when tracing from either S12XCPU or XGATE only. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 757 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 20-19. State Control Register Access Encoding COMRV 00 01 10 11 Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR MC9S12XDP512 Data Sheet, Rev. 2.17 758 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.1 Address: 0x0027 7 Debug State Control Register 1 (DBGSCR1) 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 SC3 0 SC2 0 SC1 0 SC0 0 = Unimplemented or Reserved Figure 20-9. Debug State Control Register 1 (DBGSCR1) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 20-1 and described in Section 20.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 20-20. DBGSCR1 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State1, based upon the match event. Table 20-21. State1 Sequencer Next State Selection SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state2 Any match triggers to state3 Any match triggers to Final State Match2 triggers to State2....... Other matches have no effect Match2 triggers to State3....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2 Reserved Reserved Reserved The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 759 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.2 Address: 0x0027 7 Debug State Control Register 2 (DBGSCR2) 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 SC3 0 SC2 0 SC1 0 SC0 0 = Unimplemented or Reserved Figure 20-10. Debug State Control Register 2 (DBGSCR2) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 20-1 and described in Section 20.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 20-22. DBGSCR2 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State2, based upon the match event. Table 20-23. State2 —Sequencer Next State Selection SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state3 Any match triggers to Final State Match3 triggers to State1....... Other matches have no effect Match3 triggers to State3....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect Match2 triggers to State1..... Match3 trigger to Final State Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State Reserved Reserved The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches. MC9S12XDP512 Data Sheet, Rev. 2.17 760 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.3 Address: 0x0027 7 Debug State Control Register 3 (DBGSCR3) 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 SC3 0 SC2 0 SC1 0 SC0 0 = Unimplemented or Reserved Figure 20-11. Debug State Control Register 3 (DBGSCR3) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 20-1 and described in Section 20.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 20-24. DBGSCR3 Field Descriptions Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State3, based upon the match event. Table 20-25. State3 — Sequencer Next State Selection SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state2 Any match triggers to Final State Match0 triggers to State1....... Other matches have no effect Match0 triggers to State2....... Other matches have no effect Match0 triggers to Final State.......Match1 triggers to State1 Match1 triggers to State1....... Other matches have no effect Match1 triggers to State2....... Other matches have no effect Match1 triggers to Final State....... Other matches have no effect Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Reserved Reserved The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 761 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.4 Address: 0x0027 7 Debug Match Flag Register (DBGMFR) 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 MC3 0 MC2 0 MC1 0 MC0 0 = Unimplemented or Reserved Figure 20-12. Debug Match Flag Register (DBGMFR) Read: Anytime Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further triggers on the same channel have no affect. 20.3.2.8 Comparator Register Descriptions Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparators B and D consist of four register bytes (three address bus compare registers and a control register). Each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for comparators B and D differ from those of comparators A and C. Table 20-26. Comparator Register Layout 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F CONTROL ADDRESS HIGH ADDRESS MEDIUM ADDRESS LOW DATA HIGH COMPARATOR DATA LOW COMPARATOR DATA HIGH MASK DATA LOW MASK Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write — — — — Comparator A and C only Comparator A and C only Comparator A and C only Comparator A and C only MC9S12XDP512 Data Sheet, Rev. 2.17 762 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.1 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Address: 0x0028 7 6 5 4 3 2 1 0 R W Reset 0 0 NDB 0 TAG 0 BRK 0 RW 0 RWE 0 SRC 0 COMPE 0 = Unimplemented or Reserved Figure 20-13. Debug Comparator Control Register (Comparators A and C) Address: 0x0028 7 6 5 4 3 2 1 0 R W Reset SZE 0 SZ 0 TAG 0 BRK 0 RW 0 RWE 0 SRC 0 COMPE 0 Figure 20-14. Debug Comparator Control Register (Comparators B and D) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-27. DBGXCTL Field Descriptions Field 7 SZE (Comparators B nd D) 6 NDB (Comparators A and C Description Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 Word/Byte access size is not used in comparison 1 Word/Byte access size is used in comparison Not Data Bus Compare — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. Furthermore data bus bits can be individually masked using the comparator data mask registers. This bit is only available for comparators A and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for comparators B and D. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. This bit position has NDB functionality for comparators A and C 0 Word access size will be compared 1 Byte access size will be compared Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 Trigger immediately on match 1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated 6 SZ (Comparators B and D) 5 TAG MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 763 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-27. DBGXCTL Field Descriptions (continued) Field 4 BRK Description Break — This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bits DBGBRK[1:0]. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Determines mapping of comparator to S12XCPU or XGATE 0 The comparator is mapped to S12XCPU buses 1 The comparator is mapped to XGATE address and data buses Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation 3 RW 2 RWE 1 SRC 0 COMPE Table 20-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Thus these bits are ignored if tagged triggering is selected. Table 20-28. Read or Write Comparison Logic Table RWE Bit 0 0 1 1 1 1 RW Bit x x 0 0 1 1 RW Signal 0 1 0 1 0 1 Comment RW not used in comparison RW not used in comparison Write data bus No match No match Read data bus MC9S12XDP512 Data Sheet, Rev. 2.17 764 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.2 Address: 0x0029 7 Debug Comparator Address High Register (DBGXAH) 6 5 4 3 2 1 0 R W Reset 0 0 Bit 22 0 Bit 21 0 Bit 20 0 Bit 19 0 Bit 18 0 Bit 17 0 Bit 16 0 = Unimplemented or Reserved Figure 20-15. Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-29. DBGXAH Field Descriptions Field 6–0 Bit[22:16] Description Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is ignored for XGATE compares. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 20.3.2.8.3 Address: 0x002A 7 Debug Comparator Address Mid Register (DBGXAM) 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 20-16. Debug Comparator Address Mid Register (DBGXAM) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-30. DBGXAM Field Descriptions Field 7–0 Bit[15:8] Description Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 765 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.4 Address: 0x002B 7 Debug Comparator Address Low Register (DBGXAL) 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 20-17. Debug Comparator Address Low Register (DBGXAL) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-31. DBGXAL Field Descriptions Field 7–0 Bits[7:0] Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one 20.3.2.8.5 Address: 0x002C 7 Debug Comparator Data High Register (DBGXDH) 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 20-18. Debug Comparator Data High Register (DBGXDH) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-32. DBGXAH Field Descriptions Field 7–0 Bits[15:8] Description Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one MC9S12XDP512 Data Sheet, Rev. 2.17 766 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.6 Address: 0x002D 7 Debug Comparator Data Low Register (DBGXDL) 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 20-19. Debug Comparator Data Low Register (DBGXDL) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-33. DBGXDL Field Descriptions Field 7–0 Bits[7:0] Description Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one 20.3.2.8.7 Address: 0x002E 7 Debug Comparator Data High Mask Register (DBGXDHM) 6 5 4 3 2 1 0 R W Reset Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8 0 Figure 20-20. Debug Comparator Data High Mask Register (DBGXDHM) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-34. DBGXDHM Field Descriptions Field 7–0 Bits[15:8] Description Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 767 Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.8 Address: 0x002F 7 Debug Comparator Data Low Mask Register (DBGXDLM) 6 5 4 3 2 1 0 R W Reset Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 20-21. Debug Comparator Data Low Mask Register (DBGXDLM) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-35. DBGXDLM Field Descriptions Field 7–0 Bits[7:0] Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit 20.4 Functional Description This section provides a complete functional description of the S12XDBG module. If the part is in secure mode, the S12XDBG module can generate breakpoints but tracing is not possible. 20.4.1 S12XDBG Operation Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the S12XCPU or the XGATE module. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the S12XCPU and XGATE modules. Comparators can be configured to monitor address and databus. Comparators can also be configured to mask out individual data bus bits during a compare and to use R/W and word/byte access qualification in the comparison. When a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see Figure 20-23). Either forced or tagged triggers are possible. Using a forced trigger, the trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. Tracing of both S12XCPU and/or XGATE bus activity is possible. Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals, by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register. MC9S12XDP512 Data Sheet, Rev. 2.17 768 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. TAGHITS EXTERNAL TAGHI / TAGLO XGATE S/W BREAKPOINT REQUEST SECURE COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL MATCH1 MATCH2 MATCH3 TRACE CONTROL TRIGGER TAG & TRIGGER CONTROL LOGIC TAGS BREAKPOINT REQUESTS S12XCPU & XGATE TRIGGER STATE STATE SEQUENCER STATE S12XCPU BUS XGATE BUS BUS INTERFACE TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS) Figure 20-22. S12XDBG Overview 20.4.2 Comparator Modes The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor either S12XCPU or XGATE buses using the SRC bit in the corresponding comparator control register. Each comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C also compare the data buses to the data stored in DBGXDH, DBGXDL and allow masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (see Figure 20-22) configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. On a match a trigger can initiate a transition to another state sequencer state (see Section 20.4.3”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare. Only comparators B and D feature SZE and SZ. The TAG bit in each comparator control register is used to determine the triggering condition. By setting TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 769 Chapter 20 S12X Debug (S12XDBGV3) Module before the tagged instruction executes (tagged-type trigger). Whilst tagging the RW, RWE, SZE, and SZ bits are ignored and the comparator register must be loaded with the exact opcode address. If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. Comparators C and D can also be used to select an address range to trace from. This is determined by the TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 20-10. If the TRANGE bits select a range definition using comparator D, then comparator D is configured for trace range definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range definition using comparator C, then comparator C is configured for trace range definition and cannot be used for address bus comparisons. Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see Section 20.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 20.4.3.6”). 20.4.2.1 Exact Address Comparator Match (Comparators A and C) With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible. Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact address is compared, thus with the comparator address register loaded with address (n) a misaligned word access of address (n–1) also accesses (n) but does not cause a match. Table 20-37 lists access considerations without data bus compare. Table 20-36 lists access considerations with data bus comparison. To compare byte accesses DBGXDH must be loaded with the data byte. The low byte must be masked out using the DBGXDLM mask register. On word accesses the data byte of the lower address is mapped to DBGXDH. Table 20-36. Comparator A and C Data Bus Considerations Access Word Byte Word Word Address ADDR[n] ADDR[n] ADDR[n] ADDR[n] DBGxDH Data[n] Data[n] Data[n] x DBGxDL Data[n+1] x x Data[n+1] DBGxDHM $FF $FF $FF $00 DBGxDLM $FF $00 $00 $FF Example Valid Match MOVW #$WORD ADDR[n] MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] MOVW #$WORD ADDR[n] MC9S12XDP512 Data Sheet, Rev. 2.17 770 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents. 20.4.2.2 Exact Address Comparator Match (Comparators B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match. Table 20-37. Comparator Access Size Considerations Comparator Comparators A and C Comparators B and D Comparators B and D Comparators B and D 1 Address ADDR[n] SZE — SZ8 — Condition For Valid Match Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word accesses of ADDR[n]1 MOVW #$WORD ADDR[n] Byte accesses of ADDR[n] MOVB #$BYTE ADDR[n] ADDR[n] 0 X ADDR[n] ADDR[n] 1 1 0 1 A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address used in the code. 20.4.2.3 Range Comparisons When using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator C data and data mask registers. Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both COMPEC and COMPED must be set. If a range mode is selected SRCA and SRCC select the source (S12X or XGATE), SRCB and SRCD are ignored. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 20.4.2.3.1 Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr) In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. This configuration depends upon the control register (DBGC2). The MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 771 Chapter 20 S12X Debug (S12XDBGV3) Module match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 20.4.2.3.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr) In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. In forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $7FFFFF or lower range limit to $000000 respectively. When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR register and hence vector address can be modified. 20.4.3 Trigger Modes Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections. 20.4.3.1 Forced Trigger On Comparator Match If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state for each trigger. Forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. For this reason a forced trigger of an opcode address precedes a tagged trigger at the same address by several cycles. 20.4.3.2 Trigger On Comparator Related Taghit If either a S12XCPU or XGATE taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first generate tags based on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the S12XCPU/XGATE. The state control register for the current state determines the next state for each trigger. 20.4.3.3 External Tagging Trigger In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the MC9S12XDP512 Data Sheet, Rev. 2.17 772 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device emulation modes. 20.4.3.4 Trigger On XGATE S/W Breakpoint Request The XGATE S/W breakpoint request issues a forced breakpoint request to the S12XCPU immediately independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1 determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI). 20.4.3.5 Immediate Trigger Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. This triggers the state sequencer into the Final State and issues a forced breakpoint request to both S12XCPU and XGATE. 20.4.3.6 Trigger Priorities In case of simultaneous triggers, the priority is resolved according to Table 20-38. The lower priority trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When configured for range modes a simultaneous match of comparators A and C generates an active match0 whilst match2 is suppressed. Table 20-38. Trigger Priorities Priority Highest Source XGATE TRIG External TAGHI/TAGLO Match0 (force or tag hit) Match1 (force or tag hit) Match2 (force or tag hit) Lowest Match3 (force or tag hit) Action Immediate forced breakpoint......(Tracing terminated immediately). Enter Final State Enter State0 Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 773 Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2 Figure 20-23. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, the Final State is entered and tracing starts immediately if the TSOURCE bits are configured for tracing. A tag hit through TAGHI/TAGLO brings the state sequencer immediately into state0, causes a breakpoint, if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits TALIGN[1:0]. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint request to the S12XCPU immediately. 20.4.4.1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 20.3.2.3”). If the TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM MC9S12XDP512 Data Sheet, Rev. 2.17 774 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 20.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace information in the RAM array in a circular buffer format. The S12XCPU accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace buffer line is read via the S12XCPU, an internal pointer into the RAM is incremented so that the next read will receive fresh information. Data is stored in the format shown in Table 20-39. After each store the counter register bits DBGCNT[6:0] are incremented. Tracing of S12XCPU activity is disabled when the BDM is active but tracing of XGATE activity is still possible. Reading the trace buffer whilst the BDM is active returns invalid data and the trace buffer pointer is not incremented. 20.4.5.1 Trace Trigger Alignment Using the TALIGN bits (see Section 20.3.2.3”) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to Final State if End is selected signals the end of the tracing session. The transition to Final State if Mid is selected signals that another 32 lines will be traced before ending the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using End or Mid-Trigger or when the tracing is initiated by writing to the TRIG bit whilst configured for Begin-Trigger, tracing starts at the second opcode after writing to DBGC1 if written in the CPU thread, . 20.4.5.1.1 Storing with Begin-Trigger Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 20.4.5.1.2 Storing with Mid-Trigger Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed. When the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is disarmed and no more data is stored. If the trigger is at the address of a change of flow instruction the trigger event is not stored in the Trace Buffer. Using Mid-trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 775 Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.1.3 Storing with End-Trigger Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer. 20.4.5.2 Trace Modes The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in the DBGTCR register. In each mode tracing of XGATE or S12XCPU information is possible. The source for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 20-39. 20.4.5.2.1 Normal Mode In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored. COF addresses are defined as follows for the S12XCPU: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction. • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for SWI and BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. COF addresses are defined as follows for the XGATE: • Source address of taken conditional branches • Destination address of indexed JAL instructions. • First XGATE code address in a thread Change-of-flow addresses stored include the full 23-bit address bus in the case of S12XCPU, the 16-bit address bus for the XGATE module and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. 20.4.5.2.2 Loop1 Mode Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the S12XDBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. MC9S12XDP512 Data Sheet, Rev. 2.17 776 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the S12XDBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below: LOOP INX BRCLR CMPTMP,#$0c, LOOP ; 1-byte instruction fetched by 1st P-cycle of BRCLR ; the BRCLR instruction also will be fetched by 1st ; P-cycle of BRCLR ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE LOOP2 BRN NOP DBNE * A,LOOP2 20.4.5.2.3 Detail Mode In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. In the case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information byte storage to the trace buffer, for each address byte storage. The information byte indicates the size of access (word or byte), the type of access (read or write). When tracing S12XCPU activity in Detail Mode, all cycles are traced except those when the S12XCPU is either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the time of the trace buffer entry. When tracing S12XCPU activity alone in Detail Mode, the address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses comparators C and D to define an address range inside which S12XCPU activity should be traced (see Table 20-39). Thus the traced S12XCPU activity can be restricted to register range accesses. When tracing XGATE activity in Detail Mode, all load and store cycles are traced. Additionally the S12XCPU program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of S12XCPU activity. 20.4.5.2.4 Pure PC Mode In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes are stored with the exception of WAI and STOP instructions. In Pure PC Mode, tracing from the XGATE the PC addresses of all executed opcodes are stored. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 777 Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.3 Trace Buffer Organization The buffer can be used to trace either from S12XCPU, from XGATE or from both sources. An X prefix denotes information from the XGATE module, a C prefix denotes information from the S12XCPU. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for Loop1 Mode is the same as that of Normal Mode. Whilst tracing from XGATE or S12XCPU only, in Normal or Loop1 modes each array line contains data from entries made at two separate times, thus in this case the DBGCNT[0] is incremented after each separate entry. In all other modes DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry. XGATE and S12XCPU COFs occur independently of each other and the profile of COFs for the two sources is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one source, there may be many COFs from the other source, depending on user code. COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF, but is simply a snapshot of the PC contents at the time of the COF from the other source. Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2 Table 20-39. Trace Buffer Organization Mode 8-Byte Wide Word Buffer 7 CXINF1 CXINF2 CXINF1 CXINF2 XINF0 XINF1 XINF1 XINF3 CINF1 CINF3 CPCH1 CPCH3 6 CADRH1 CADRH2 CADRH1 CADRH2 5 CADRM1 CADRM2 CADRM1 CADRM2 XPCM0 XPCM1 XPCM1 XPCM3 CPCM1 CPCM3 4 CADRL1 CADRL2 CADRL1 CADRL2 XPCL0 XPCL1 XPCL1 XPCL3 CPCL1 CPCL3 3 XDATAH1 XDATAH2 CDATAH1 CDATAH2 CINF0 CINF1 XINF0 XINF2 CINF0 CINF2 CPCH0 CPCH2 2 XDATAL1 XDATAL2 CDATAL1 CDATAL2 CPCH0 CPCH1 1 XADRM1 XADRM2 XADRM1 XADRM2 CPCM0 CPCM1 XPCM0 XPCM2 CPCM0 CPCM2 0 XADRL1 XADRL2 XADRL1 XADRL2 CPCL0 CPCL1 XPCL0 XPCL2 CPCL0 CPCL2 XGATE Detail S12XCPU Detail Both Other Modes XGATE Other Modes S12XCPU Other Modes MC9S12XDP512 Data Sheet, Rev. 2.17 778 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.3.1 Information Byte Organization The format of the control information byte for both S12XCPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes tracing of S12XCPU activity, CINF is used to store control information. In Detail Mode, CXINF contains the control information XGATE Information Byte Bit 7 XSD Bit 6 XSOT Bit 5 XCOT Bit 4 XDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 20-24. XGATE Information Byte XINF Table 20-40. XINF Field Descriptions Field 7 XSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source Address 1 Destination Address or Start of Thread or Continuation of Thread Source Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread address. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a start of thread 1 Stored address from a start of thread Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a continuation of thread 1 Stored address from a continuation of thread Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid 6 XSOT 5 XCOT 4 XDV X12X_CPU Information Byte Bit 7 CSD Bit 6 CVA Bit 5 0 Bit 4 CDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Figure 20-25. S12XCPU Information Byte CINF MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 779 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-41. CINF Field Descriptions Field 7 CSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source Address 1 Destination Address Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. This is only used in Normal and Loop1 mode tracing. 0 Source Address 1 Destination Address Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the S12XCPU trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid 6 CVA 4 CDV CXINF Information Byte Bit 7 CFREE Bit 6 CSZ Bit 5 CRW Bit 4 COCF Bit 3 XACK Bit 2 XSZ Bit 1 XRW Bit 0 XOCF Figure 20-26. Information Byte CXINF This describes the format of the information byte used only when tracing from S12XCPU or XGATE in Detail Mode. When tracing from the S12XCPU in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made by the S12XCPU, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The S12XCPU entry stored on the same line is a snapshot of the S12XCPU program counter. In this case the XSZ and XRW bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF bits indicate if the simultaneous S12XCPU cycle is a free cycle or opcode fetch cycle. Table 20-42. CXINF Field Descriptions Field 7 CFREE Description S12XCPU Free Cycle Indicator — This bit indicates if the stored S12XCPU address corresponds to a free cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing S12XCPU activity in Detail Mode. 0 Word Access 1 Byte Access 6 CSZ MC9S12XDP512 Data Sheet, Rev. 2.17 780 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-42. CXINF Field Descriptions (continued) Field 5 CRW Description Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing S12XCPU activity in Detail Mode. 0 Write Access 1 Read Access S12XCPU Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit only contains valid information when tracing the S12XCPU accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Write Access 1 Read Access XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.This bit only contains valid information when tracing the S12XCPU accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle 4 COCF 3 XACK 2 XSZ 1 XRW 0 XOCF 20.4.5.4 Reading Data from Trace Buffer The data stored in the Trace Buffer can be read using either the background debug module (BDM) module or the S12XCPU provided the S12XDBG module is not armed, is configured for tracing (at least one TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. Multiple writes to the DBGTB are not allowed since they increment the pointer. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid 64-bit lines can be determined. DBGCNT will not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 781 Chapter 20 S12X Debug (S12XDBGV3) Module The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 20-39. The bytes containing invalid information (shaded in Table 20-39) are also read out. Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur. Reading the trace buffer is not possible if both TSOURCE bits are cleared. 20.4.5.5 Trace Buffer Reset State The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. 20.4.6 Tagging A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. Both S12XCPU and XGATE opcodes can be tagged with the comparator register TAG bits. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagged triggering is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. S12X tagging is disabled when the BDM becomes active. Conversely BDM firmware commands are not processed while tagging is active. XGATE tagging is possible when the BDM is active. MC9S12XDP512 Data Sheet, Rev. 2.17 782 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag S12XCPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other. External tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge of the external clock (ECLK) performs the function indicated in the Table 20-43. It is possible to tag both bytes of an instruction word. If a taghit occurs, a breakpoint can be generated as defined by the DBGBRK and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag is replaced by a new one. Table 20-43. Tag Pin Function TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes 20.4.6.2 Unconditional Tagging Function In emulation modes a low assertion of PE5/TAGLO/MODA in the 7th or 8th bus cycle after reset enables the unconditional tagging function, allowing immediate tagging via TAGHI/TAGLO with breakpoint to BDM independent of the ARM, BDM and DBGBRK bits. Conversely these bits are not affected by unconditional tagging. The unconditional tagging function remains enabled until the next reset. This function allows an immediate entry to BDM in emulation modes before user code execution. The TAGLO assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior RESET pin assertion lasts the full 192 bus cycles. 20.4.7 Breakpoints There are several ways to generate breakpoints to the XGATE and S12XCPU modules • Through XGATE software breakpoint requests. • From comparator channel triggers to final state. • Using software to write to the TRIG bit in the DBGC1 register. • From taghits generated using the external TAGHI and TAGLO pins. • Through the auxilliary forced breakpoint input. 20.4.7.1 XGATE Software Breakpoints The XGATE software breakpoint instruction BRK can request an S12XCPU breakpoint, via the S12XDBG module. In this case, if the XGSBPE bit is set, the S12XDBG module immediately generates a forced breakpoint request to the S12XCPU, the state sequencer is returned to state0 and tracing, if active, is terminated. If configured for BEGIN trigger and tracing has not yet been triggered from another source, the trace buffer contains no information. Breakpoint requests from the XGATE module do not depend MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 783 Chapter 20 S12X Debug (S12XDBGV3) Module upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the S12XCPU program flow, but it is necessary to set XGSBPE. Furthermore, if a breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an S12XCPU breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module. 20.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 20-44). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment. Table 20-44. Breakpoint Setup For Both XGATE and S12XCPU Breakpoints BRK 0 0 0 0 0 0 1 1 x TALIGN 00 00 01 01 10 10 00,01,10 00,01,10 11 DBGBRK[n] 0 1 0 1 0 1 1 0 x Breakpoint Alignment Fill Trace Buffer until trigger (no breakpoints — keep running) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints — keep running) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Store a further 32 Trace Buffer line entries after trigger (no breakpoints — keep running) Store a further 32 Trace Buffer line entries after trigger Request breakpoint after the 32 further Trace Buffer entries Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger Reserved 20.4.7.3 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered. Tracing trigger alignment is defined by the TALIGN bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 20-44). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the S12XDBG module is disarmed. MC9S12XDP512 Data Sheet, Rev. 2.17 784 Freescale Semiconductor Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.7.4 Breakpoints Via TAGHI Or TAGLO Pin Taghits Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is always end aligned, independent of internal channel trigger alignment configuration. 20.4.7.5 Auxilliary Breakpoint Input When this signal asserts tracing is terminated and an immediate forced breakpoints are generated, depending on the configuration of DBGBRK bits. 20.4.7.6 S12XDBG Breakpoint Priorities XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a comparator channel whose BRK = 0, it has no effect, since tracing has already started. If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of the tracing trigger alignment bits TALIGN[1:0]. If a forced and tagged breakpoint coincide, the forced breakpoint occurs too late to prevent the tagged instruction being loaded into the execution unit. Conversely the taghit is too late to prevent the breakpoint request in the DBG module. Thus the S12XCPU suppresses the taghit although the tagged instruction is executed. Considering the code example below the forced breakpoint is requested when the location COUNTER is accessed. This is signalled to the S12XCPU when the next (tagged) instruction (NOP) is already in the execution stage, thus the tagged instruction is carried out but the tagged breakpoint is suppressed. Reading the PC with BDM READ_PC returns $C008 c000 c003 c004 c007 00 [BDM c008 cf ff 00 a7 72 70 08 a7 START LDS NOP INC NOP BGND BRA #$FF00 COUNTER ; Forced breakpoint location = COUNTER ; Tagged opcode location = MARK MARK firmware commands] 20 01 END ; 1st instruction on return from BDM 20.4.7.6.1 S12XDBG Breakpoint Priorities And BDM Interfacing Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is active, the S12XCPU is executing out of BDM firmware and S12X breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in the user’s code. On returning from BDM, the SWI from user code gets executed. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 785 Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-45. Breakpoint Mapping Summary DBGBRK[1] (DBGC1[3]) 0 1 1 1 1 1 BDM Bit (DBGC1[4]) X 0 0 1 1 1 BDM Enabled X X X 0 1 1 BDM Active X 0 1 X 0 1 S12X Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint Breakpoint to SWI Breakpoint to BDM No Breakpoint BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the S12XCPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal S12XCPU flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code and DBG breakpoint could occur simultaneously. The S12XCPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re triggering a breakpoint. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. To avoid re triggering a breakpoint at the same location reconfigure the S12XDBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. An XGATE software breakpoint is forced immediately, the tracing session terminated and the XGATE module execution stops. The user can thus determine if an XGATE breakpoint has occurred by reading out the XGATE program counter over the BDM interface. MC9S12XDP512 Data Sheet, Rev. 2.17 786 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.1 Introduction This document describes the functionality of the XEBI block controlling the external bus interface. The XEBI controls the functionality of a non-multiplexed external bus (a.k.a. ‘expansion bus’) in relationship with the chip operation modes. Dependent on the mode, the external bus can be used for data exchange with external memory, peripherals or PRU, and provide visibility to the internal bus externally in combination with an emulator. 21.1.1 Features The XEBI includes the following features: • Output of up to 23-bit address bus and control signals to be used with a non-muxed external bus • Bidirectional 16-bit external data bus with option to disable upper half • Visibility of internal bus activity 21.1.2 • • Modes of Operation • Single-chip modes The external bus interface is not available in these modes. Expanded modes Address, data, and control signals are activated on the external bus in normal expanded mode and special test mode. Emulation modes The external bus is activated to interface to an external tool for emulation of normal expanded mode or normal single-chip mode applications. Refer to the S12X_MMC section for a detailed description of the MCU operating modes. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 787 Chapter 21 External Bus Interface (S12XEBIV2) 21.1.3 Block Diagram Figure 21-1 is a block diagram of the XEBI with all related I/O signals. ADDR[22:0] DATA[15:0] IVD[15:0] LSTRB R/W EWAIT XEBI UDS LDS RE WE ACC[2:0] IQSTAT[3:0] Figure 21-1. XEBI Block Diagram 21.2 External Signal Description NOTE The following external bus related signals are described in other sections: CS2, CS1, CS0 (chip selects) — S12X_MMC section ECLK, ECLKX2 (free-running clocks) — PIM section TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section The user is advised to refer to the SoC section for port configuration and location of external bus signals. Table 21-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section and PIM section for reset states of these pins and associated pull-ups or pull-downs. MC9S12XDP512 Data Sheet, Rev. 2.17 788 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) Table 21-1. External System Signals Associated with XEBI EBI Signal Multiplex (T)ime2 (F)unction3 — T — — — T — — T — — T F Available in Modes Description NS Read Enable, indicates external read access External address Access source External address Instruction Queue Status External address Internal visibility read data (IVIS = 1) External address Internal visibility read data (IVIS = 1) — — — — — — — — — — — F F Upper Data Select, indicates external access to the high byte DATA[15:8] Low Strobe, indicates valid data on DATA[7:0] Lower Data Select, indicates external access to the low byte DATA[7:0] Read/Write, indicates the direction of internal data transfers Write Enable, indicates external write access Bidirectional data (even address) Bidirectional data (odd address) External control for external bus access stretches (adding wait states) No No No No No No No No No No No No No No No No No SS No No No No No No No No No No No No No No No No No NX Yes Yes No Yes No Yes No No No Yes No Yes No Yes Yes Yes Yes ES No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes No EX No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes Yes ST No Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes Yes No Signal I /O 1 RE ADDR[22:20] ACC[2:0] ADDR[19:16] IQSTAT[3:0] ADDR[15:1] IVD[15:1] ADDR0 IVD0 UDS LSTRB LDS R/W WE DATA[15:8] DATA[7:0] EWAIT 1 2 O O O O O O O O O O O O O O I/O I/O I All inputs are capable of reducing input threshold level Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated time slot (in modes where applicable). 3 Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin depending on configuration and reset state. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 789 Chapter 21 External Bus Interface (S12XEBIV2) 21.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XEBI. 21.3.1 Module Memory Map The registers associated with the XEBI block are shown in Figure 21-2. Register Name EBICTL0 R W EBICTL1 R W Bit 7 ITHRS 6 0 5 HDBE 0 4 ASIZ4 0 3 ASIZ3 0 2 ASIZ2 1 ASIZ1 Bit 0 ASIZ0 EWAITE 0 EXSTR2 EXSTR1 EXSTR0 = Unimplemented or Reserved Figure 21-2. XEBI Register Summary 21.3.2 Register Descriptions The following sub-sections provide a detailed description of each register and the individual register bits. All control bits can be written anytime, but this may have no effect on the related function in certain operating modes. This allows specific configurations to be set up before changing into the target operating mode. NOTE Depending on the operating mode an available function may be enabled, disabled or depend on the control register bit. Reading the register bits will reflect the status of related function only if the current operating mode allows user control. Please refer the individual bit descriptions. MC9S12XDP512 Data Sheet, Rev. 2.17 790 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.3.2.1 R W Reset External Bus Interface Control Register 0 (EBICTL0) 7 6 5 4 3 2 1 0 ITHRS 0 0 0 HDBE 1 ASIZ4 1 ASIZ3 1 ASIZ2 1 ASIZ1 1 ASIZ0 1 = Unimplemented or Reserved Figure 21-3. External Bus Interface Control Register 0 (EBICTL0) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes, the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register controls input pin threshold level and determines the external address and data bus sizes in normal expanded mode. If not in use with the external bus interface, the related pins can be used for alternative functions. External bus is available as programmed in normal expanded mode and always full-sized in emulation modes and special test mode; function not available in single-chip modes. Table 21-2. EBICTL0 Field Descriptions Field 7 ITHRS Description Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific control input signals which are in use with the external bus interface in order to adapt to external devices with a 3.3 V, 5 V tolerant I/O. The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable signals of the EBI pin function as summarized in Table 21-3. 0 Input threshold is at standard level on all pins 1 Reduced input threshold level enabled on pins in use with the external bus interface High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-bit data bus can be used with the external bus interface. In this case the unused data pins and the data select signals (UDS and LDS) are free to be used for alternative functions. 0 DATA[15:8], UDS, and LDS disabled 1 DATA[15:8], UDS, and LDS enabled External Address Bus Size — These bits allow scalability of the external address bus. The programmed value corresponds to the number of available low-aligned address lines (refer to Table 21-4). All address lines ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when using alternative functions on relevant pins in applications which utilize a reduced external address bus. 5 HDBE 4–0 ASIZ[4:0] MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 791 Chapter 21 External Bus Interface (S12XEBIV2) Table 21-3. Input Threshold Levels on External Signals ITHRS External Signal DATA[15:8] TAGHI, TAGLO 0 DATA[7:0] EWAIT DATA[15:8] TAGHI, TAGLO 1 DATA[7:0] EWAIT Standard Standard Reduced if HDBE = 1 Reduced Reduced if EWAITE = 1 Standard Reduced if EWAITE = 1 Standard Standard Standard Standard NS SS NX ES Reduced Standard Reduced EX Reduced Standard Reduced Reduced ST Standard Table 21-4. External Address Bus Size ASIZ[4:0] 00000 00001 00010 00011 : 10110 10111 : 11111 Available External Address Lines None UDS ADDR1, UDS ADDR[2:1], UDS : ADDR[21:1], UDS ADDR[22:1], UDS MC9S12XDP512 Data Sheet, Rev. 2.17 792 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.3.2.2 R W Reset External Bus Interface Control Register 1 (EBICTL1) 7 6 5 4 3 2 1 0 EWAITE 0 0 0 0 0 0 0 0 0 EXSTR2 1 EXSTR1 1 EXSTR0 1 = Unimplemented or Reserved Figure 21-4. External Bus Interface Control Register 1 (EBICTL1) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register is used to configure the external access stretch (wait) function. Table 21-5. EBICTL1 Field Descriptions Field 7 EWAITE Description External Wait Enable — This bit enables the external access stretch function using the external EWAIT input pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to Table 21-6). External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function not available in all other operating modes. 0 External wait is disabled 1 External wait is enabled External Access Stretch Bits 2, 1, 0 — This three bit field determines the amount of additional clock stretch cycles on every access to the external address space as shown in Table 21-6. The minimum number of stretch cycles depends on the EWAITE setting. Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function not available in all other operating modes. 2–0 EXSTR[2:0] Table 21-6. External Access Stretch Bit Definition Number of Stretch Cycles EXSTR[2:0] EWAITE = 0 000 001 010 011 100 101 110 111 1 cycle 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles EWAITE = 1 >= 2 cycles >= 2 cycles >= 3 cycles >= 4 cycles >= 5 cycles >= 6 cycles >= 7 cycles >= 8 cycles MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 793 Chapter 21 External Bus Interface (S12XEBIV2) 21.4 Functional Description This section describes the functions of the external bus interface. The availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in separate sub-sections. 21.4.1 Operating Modes and External Bus Properties Table 21-7. Summary of Functions Single-Chip Modes Expanded Modes Normal Expanded Emulation Single-Chip Emulation Expanded Special Test A summary of the external bus interface functions for each operating mode is shown in Table 21-7. Properties (if Enabled) Normal Single-Chip Special Single-Chip Timing Properties PRR access 1 2 cycles read internal write internal — — 2 cycles read internal write internal — — 2 cycles read internal write internal — Max. of 2 to 9 programmed cycles or n cycles of ext. wait3 — 2 cycles read external write int & ext 1 cycle 1 cycle 2 cycles read external write int & ext 1 cycle Max. of 2 to 9 programmed cycles or n cycles of ext. wait3 1 cycle 2 cycles read internal write internal 1 cycle 1 cycle Internal access visible externally External address access and unimplemented area access2 Flash area address access4 — — 1 cycle 1 cycle Signal Properties Bus signals — — ADDR[22:1] DATA[15:0] ADDR[22:20]/A ADDR[22:20]/A CC[2:0] CC[2:0] ADDR[19:16]/ ADDR[19:16]/ IQSTAT[3:0] IQSTAT[3:0] ADDR[15:0]/ ADDR[15:0]/ IVD[15:0] IVD[15:0] DATA[15:0] DATA[15:0] ADDR0 LSTRB R/W — DATA[15:0] EWAIT ADDR0 LSTRB R/W EWAIT DATA[15:0] EWAIT ADDR[22:0] DATA[15:0] Data select signals (if 16-bit data bus) Data direction signals External wait feature Reduced input threshold enabled on 1 2 — — — — — — — — UDS LDS RE WE EWAIT Refer to Table 21-3 ADDR0 LSTRB R/W — Refer to Table 21-3 Incl. S12X_EBI registers Refer to S12X_MMC section. 3 If EWAITE = 1, the minimum number of external bus cycles is 3. 4 Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section). MC9S12XDP512 Data Sheet, Rev. 2.17 794 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2 Internal Visibility Internal visibility allows the observation of the internal MCU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface. Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal CPU and BDM accesses are made visible on the external bus interface, except those to BDM firmware and BDM registers. Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 21-9 to Table 21-11), internal writes on ADDRx and DATAx (see Table 21-12 to Table 21-14). R/W and LSTRB show the type of access. External read data are also visible on IVDx. 21.4.2.1 Access Source and Instruction Queue Status Signals The access source (bus master) can be determined from the external bus control signals ACC[2:0] as shown in Table 21-8. Table 21-8. Determining Access Source from Control Signals ACC[2:0] 000 001 010 011 100 101, 110, 111 1 2 Access Description Repetition of previous access cycle CPU access BDM access XGATE PRR access1 No access2 Reserved Invalid IVD brought out in read cycles Denotes also accesses to BDM firmware and BDM registers (IQSTATx are ‘XXXX’ and R/W = 1 in these cases) The CPU instruction queue status (execution-start and data-movement information) is brought out as IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section. 21.4.2.2 Emulation Modes Timing A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases. Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and (for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL (0x0000) from the third until one cycle after the access to indicate continuation. The resulting timing pattern of the external bus signals is outlined in the following tables for read, write and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus cycles. Non-shaded bold entries denote all values related to Access #0. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 795 Chapter 21 External Bus Interface (S12XEBIV2) The following terminology is used: ‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins ‘x’ — Undefined output pin values ‘z’ — Tristate pins ‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’ 21.4.2.2.1 Read Access Timing Table 21-9. Read Access (1 Cycle) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) R/W ... ... ... addr 0 ? ? 1 ... ... ... ... high Access #1 2 3 low acc 1 iqstat 0 ivd 0 z z 1 high addr 2 z data 1 1 low acc 2 iqstat 1 ivd 1 z z 1 ... ... ... ... ... ... ... ... 1 low acc 0 iqstat -1 ? z z 1 z data 0 1 addr 1 high ADDR[19:16] / IQSTAT[3:0] ... Table 21-10. Read Access (2 Cycles) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) R/W ... ... ... addr 0 ? ? 1 ... ... ... ... high Access #1 2 3 low 000 iqstat 0 x z z 1 high addr 1 z data 0 1 low acc 1 0000 ivd 0 z z 1 ... ... ... ... ... ... ... ... 1 low acc 0 iqstat-1 ? z z 1 z z 1 addr 0 high ADDR[19:16] / IQSTAT[3:0] ... Table 21-11. Read Access (n–1 Cycles) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) R/W ... ... ... addr 0 ? ? 1 ... ... ... ... high Access #1 3 ... low 000 addr 0 z z 1 0000 x z z 1 ... ... ... ... ... ... ... z data 0 1 addr 1 high 1 low acc 0 iqstat-1 ? z z 1 z z 1 addr 0 high 2 low 000 iqstat 0 x z z 1 high n low acc 1 0000 ivd 0 z z 1 ... ... ... ... ... ... ... ... ADDR[19:16] / IQSTAT[3:0] ... MC9S12XDP512 Data Sheet, Rev. 2.17 796 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2.2.2 Write Access Timing Table 21-12. Write Access (1 Cycle) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) R/W ... ... ... addr 0 ? 0 0 ... ... ... high Access #1 2 high addr 1 low acc 1 iqstat 0 x data 0 1 1 data 1 Access #2 3 high addr 2 low acc 2 iqstat 1 x data 2 1 1 ... ... ... ... ... ... ... 1 low acc 0 iqstat -1 ? ADDR[19:16] / IQSTAT[3:0] ... Table 21-13. Write Access (2 Cycles) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) R/W ... ... ... addr 0 ? 0 0 0 ... ... ... high Access #1 2 3 low 000 iqstat 0 x data 0 0 1 high addr 1 low acc 1 0000 x x 1 ... ... ... ... ... ... ... 1 low acc 0 iqstat-1 ? addr 0 high ADDR[19:16] / IQSTAT[3:0] ... Table 21-14. Write Access (n–1 Cycles) Access #0 Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) R/W ... ... ... addr 0 ? 0 0 0 0 ... ... ... high Access #1 3 ... low 000 addr 0 0000 x data 0 0 0 ... 1 ... ... ... ... addr 1 high 1 low acc 0 iqstat-1 ? addr 0 high 2 low 000 iqstat 0 x high n low acc 1 0000 x x 1 ... ... ... ... ... ... ... ADDR[19:16] / IQSTAT[3:0] ... MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 797 Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2.2.3 Read-Write-Read Access Timing Table 21-15. Interleaved Read-Write-Read Accesses (1 Cycle) Access #0 Access #1 2 low acc 0 addr 0 ? ? 1 iqstat -1 ? z z 1 z data 0 0 addr 1 high low acc 1 iqstat 0 ivd 0 (write) data 1 (write) data 1 0 1 addr 2 high Access #2 3 low acc 2 iqstat 1 x z z 1 ... ... ... ... ... ... ... ... Bus cycle -> ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (internal read) DATA[15:0] (external read) R/W ... ... ... ... ... ... ... high 1 ADDR[19:16] / IQSTAT[3:0] ... 21.4.2.3 Internal Visibility Data Depending on the access size and alignment, either a word of read data is made visible on the address lines or only the related data byte will be presented in the ECLK low phase. For details refer to Table 21-16. Table 21-16. IVD Read Data Output Access Word read of data at an even and even+1 address Word read of data at an odd and odd+1 internal RAM address (misaligned) Byte read of data at an even address Byte read of data at an odd address IVD[15:8] ivd(even) ivd(odd+1) ivd(even) addr[15:8] (rep.) IVD[7:0] ivd(even+1) ivd(odd) addr[7:0] (rep.) ivd(odd) 21.4.3 Accesses to Port Replacement Registers All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode. If writing to these addresses in emulation modes, the access is directed to both, the internal register and the external resource while reads will be treated external. The XEBI control registers also belong to this category. 21.4.4 Stretched External Bus Accesses In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI supports stretched external bus accesses (wait states). This feature is available in normal expanded mode and emulation expanded mode for accesses to all external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2 cycles, respectively. MC9S12XDP512 Data Sheet, Rev. 2.17 798 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fixed amount of stretch cycles 2. Activation of the external wait feature by EWAITE in EBICTL1 register 3. Assertion of the external EWAIT signal when EWAITE = 1 The EXSTR[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An arbitrary amount of stretch cycles can be added using the EWAIT input. EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional cycles will cause the external bus access to be stretched accordingly. Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed and controlled by external wait after the data have been driven out on the external bus. This results in an extension of time the bus signals and the related control signals are valid externally. Read data are not captured by the system in normal expanded mode until the specified setup time before the RE rising edge. Read data are not captured in emulation expanded mode until the specified setup time before the falling edge of ECLK. In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched as programmed and controlled by external wait. 21.4.5 Data Select and Data Direction Signals The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses. The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this module exclusively supports these kind of accesses in a single cycle. With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to odd addresses. In expanded modes the data access type is externally determined by a set of control signals, i.e., data select and data direction signals, as described below. The data select signals are not available if using the external bus interface with an 8-bit data bus. 21.4.5.1 Normal Expanded Mode In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write), data size and alignment of an external bus access (Table 21-17). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 799 Chapter 21 External Bus Interface (S12XEBIV2) Table 21-17. Access in Normal Expanded Mode DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Indicates No Access Unimplemented RE WE UDS LDS I/O data(addr) I/O data(addr) 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 Out data(even) Out In In In In In In In x data(even) x data(even) x x x Out In In In In In In In Out data(even) data(odd) data(odd) x data(odd) data(odd) x x x x DATA[7:0] 21.4.5.2 Emulation Modes and Special Test Mode In emulation modes and special test mode, the external signals LSTRB, R/W, and ADDR0 indicate the access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 21-18. Table 21-18. Access in Emulation Modes and Special Test Mode DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word write at an odd and odd+1 internal RAM address (misaligned — only in emulation modes) Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Word read at an odd and odd+1 internal RAM address (misaligned - only in emulation modes) R/W LSTRB ADDR0 I/O 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Out In Out data(addr) data(even) x data(odd) I/O Out Out In data(addr) data(odd) data(odd) x data(odd) data(even+1) data(odd) x data(odd) DATA[7:0] Out data(odd+1) Out In In In In data(even) x data(even) data(odd+1) In In In In MC9S12XDP512 Data Sheet, Rev. 2.17 800 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.4.6 Low-Power Options The XEBI does not support any user-controlled options for reducing power consumption. 21.4.6.1 Run Mode The XEBI does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface. Operation in expanded modes results in a higher power consumption, however any unnecessary toggling of external bus signals is reduced to the lowest indispensable activity by holding the previous states between external accesses. 21.4.6.2 Wait Mode The XEBI does not support any options for reducing power in wait mode. 21.4.6.3 Stop Mode The XEBI will cease to function in stop mode. 21.5 Initialization/Application Information This section describes the external bus interface usage and timing. Typical customer operating modes are normal expanded mode and emulation modes, specifically to be used in emulator applications. Taking the availability of the external wait feature into account the use cases are divided into four scenarios: • Normal expanded mode — External wait feature disabled – External wait feature enabled • Emulation modes – Emulation single-chip mode (without wait states) – Emulation expanded mode (with optional access stretching) Normal single-chip mode and special single-chip mode do not have an external bus. Special test mode is used for factory test only. Therefore, these modes are omitted here. All timing diagrams referred to throughout this section are available in the Electrical Characteristics appendix of the SoC section. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 801 Chapter 21 External Bus Interface (S12XEBIV2) 21.5.1 Normal Expanded Mode This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access. 21.5.1.1 Example 1a: External Wait Feature Disabled The first example of bus timing of an external read and write access with the external wait feature disabled is shown in • Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’ The associated supply voltage dependent timing are numbers given in • • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 0)’ Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAITE = 0)’ Systems designed this way rely on the internal programmable access stretching. These systems have predictable external memory access times. The additional stretch time can be programmed up to 8 cycles to provide longer access times. 21.5.1.2 Example 1b: External Wait Feature Enabled The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles over the programmed number in EXSTR[2:0]. The feature must be enabled by writing EWAITE = 1. If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If EWAIT is asserted within the predefined time window during the access it will be strobed active and another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is finished. EWAIT can be held asserted as long as desired to stretch the access. An access with 1 cycle stretch by EWAIT assertion is shown in • Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’ • Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’ The associated timing numbers for both operations are given in • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 1)’ • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAITE = 1)’ It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize the EWAIT input signal. MC9S12XDP512 Data Sheet, Rev. 2.17 802 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2 Emulation Modes In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are directed to the external bus in emulation modes which are substituted by PRR as part of the PRU. Accesses to these registers take a constant time of 2 cycles. Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait state operation (stretching) of the external bus access is done in emulation modes when accessing internal memory or emulation memory addresses. In both modes observation of the internal operation is supported through the external bus (internal visibility). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 803 Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 21-5 shows the PRU connection with the available external bus signals in an emulator application. S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator PRU PRR Ports LSTRB R/W ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] ECLK ECLKX2 Figure 21-5. Application in Emulation Single-Chip Mode The timing diagram for this operation is shown in: • Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’ The associated timing numbers are given in: • Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAITE = 0)’ Timing considerations: • Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing. • LSTRB has the same timing as R/W. • ECLKX2 rising edges have the same timing as ECLK edges. • The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing for an external non-PRR access with 1 cycle of stretch as shown in example 2b. MC9S12XDP512 Data Sheet, Rev. 2.17 804 Freescale Semiconductor Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals UDS, LDS, RE, and WE from the ADDR0, LSTRB, and R/W signals. Figure 21-6 shows the PRU connection with the available external bus signals in an emulator application. S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator PRU PRR Ports LSTRB R/W UDS LDS RE WE ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] EWAIT ECLK ECLKX2 CS[2:0] Figure 21-6. Application in Emulation Expanded Mode The timings of accesses with 1 stretch cycle are shown in • Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’ • Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’ The associated timing numbers are given in • Table ‘Example 2b: Emulation Expanded Mode Timing VDD5 = 5.0 V (EWAITE = 0)’ (this also includes examples for alternative settings of 2 and 3 additional stretch cycles) Timing considerations: • If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 805 Chapter 21 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev. 2.17 806 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.1 Introduction The S12XD family port integration module (below referred to as PIM) establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This document covers the description of: • Port A, B used as address output of the S12X_EBI • Port C, D used as data I/O of the S12X_EBI • Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs • Port K associated with address output and control signals of the S12X_EBI • Port T connected to the Enhanced Capture Timer (ECT) module • Port S associated with 2 SCI and 1 SPI modules • Port M associated with 4 MSCAN modules and 1 SCI module • Port P connected to the PWM and 2 SPI modules — inputs can be used as an external interrupt source • Port H associated with 2 SCI modules — inputs can be used as an external interrupt source • Port J associated with 1 MSCAN, 1 SCI, and 2 IIC modules — inputs can be used as an external interrupt source • Port AD0 and AD1 associated with one 8-channel and one 16-channel ATD module Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and select pull-up or pull-down devices. Interrupts can be enabled on specific pins resulting in status flags. The I/O’s of 2 MSCAN and all 3 SPI modules can be routed from their default location to alternative port pins. NOTE The implementation of the PIM is device dependent. Therefore some functions are not available on certain derivatives or 112-pin and 80-pin package options. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 807 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.1.1 Features A full-featured PIM module includes these distinctive registers: • Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, and AD1 when used as general-purpose I/O • Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P, H, and J on per-pin basis • Control registers to enable/disable pull-up devices on Ports AD0, and AD1 on per-pin basis • Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis and on BKGD pin • Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, and AD1 on per-pin basis • Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on per-port basis • Control registers to enable/disable open-drain (wired-OR) mode on Ports S and M • Control registers to enable/disable pin interrupts on Ports P, H, and J • Interrupt flag register for pin interrupts on Ports P, H, and J • Control register to configure IRQ pin operation • Free-running clock outputs A standard port pin has the following minimum features: • Input/output selection • 5V output drive with two selectable drive strengths • 5V digital and analog input • Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt inputs with glitch filtering • Reduced input threshold to support low voltage applications 22.1.2 Block Diagram Figure 22-1 is a block diagram of the PIM. • Signals shown in Bold are not available in 80-pin packages. • Signals shown in Bold-Italics are neither available in 112-pin nor in 80-pin packages. • Shaded labels denote alternative module routing ports. MC9S12XDP512 Data Sheet, Rev. 2.17 808 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Port Integration Module PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PJ7 PJ6 PJ5 PJ4 PJ2 PJ1 PJ0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 TXCAN CAN4 RXCAN SCL IIC0 SDA SCL IIC1 SDA TXD RXD SCI2 ECT TXD SCI3 RXD AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 Port AD0 ATD0 Port AD1 ATD1 TXD SCI5 RXD TXD SCI4 RXD AN15,14 AN13,12 AN11,10 AN9,8 AN7,6 AN5,4 AN3,2 AN1,0 PAD22 PAD20 PAD18 PAD16 PAD14 PAD12 PAD10 PAD08 PAD07 PAD06 PAD05 PAD04 PAD03 PAD02 PAD01 PAD00 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 BKGD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 PAD23 PAD21 PAD19 PAD17 PAD15 PAD13 PAD11 PAD09 Interrupt Logic Interrupt Logic SPI2 SPI1 CAN0 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0/UDS DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SCK SS MOSI MISO SS SPI1 SCK MOSI MISO Interrupt Logic SPI2 SS SPI0 SCK MOSI MISO TXD SCI1 RXD TXD SCI0 RXD BKGD/MODC ECLKX2/XCLKS TAGHI/MODB TAGLO/RE/MODA ECLK S12X_EBI LDS/LSTRB S12X_BDM WE/R/W S12X_DBG IRQ XIRQ S12X_INT EWAIT/ROMCTL NOACC/ADDR22 ADDR21 ADRR20 ADDR19 ADDR18 ADDR17 ADDR16 Figure 22-1. PIM Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 809 Port K Port E Port S Port P PWM Port T Port H Port J Port M Port A Port B Port C Port D TXCAN CAN3 RXCAN TXCAN CAN2 RXCAN TXCAN CAN1 RXCAN TXCAN CAN0 RXCAN SPI0 CAN0 CAN0 CAN4 CAN4 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.2 External Signal Description This section lists and describes the signals that do connect off-chip. 22.2.1 Signal Properties Table 22-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section 22.4, “Functional Description” for the availability of the individual pins in the different package options. NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Table 22-1. Pin Functions and Priorities (Sheet 1 of 7) Port — Pin Name BKGD Pin Function and Priority MODC1 BKGD A PA[7:0] ADDR[15:8] mux IVD[15:8]2 GPIO B PB[7:1] ADDR[7:1] mux IVD[7:1]2 GPIO PB[0] ADDR[0] mux IVD02 UDS GPIO C PC[7:0] DATA[15:8] GPIO D PD[7:0] DATA[7:0] GPIO I/O I I/O O Description MODC input during RESET S12X_BDM communication pin High-order external bus address output (multiplexed with IVIS data) General-purpose I/O Low-order external bus address output (multiplexed with IVIS data) General-purpose I/O Low-order external bus address output (multiplexed with IVIS data) Upper data strobe General-purpose I/O High-order bidirectional data input/output Configurable for reduced input threshold General-purpose I/O Low-order bidirectional data input/output Configurable for reduced input threshold General-purpose I/O Mode dependent3 Mode dependent3 Mode dependent3 Mode dependent3 Pin Function after Reset BKGD I/O O I/O O O I/O I/O I/O I/O I/O MC9S12XDP512 Data Sheet, Rev. 2.17 810 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 2 of 7) Port Pin Name Pin Function and Priority XCLKS1 PE[7] ECLKX2 GPIO MODB1 PE[6] TAGHI GPIO MODA1 RE PE[5] TAGLO GPIO E ECLK PE[4] GPIO EROMCTL1 PE[3] LSTRB LDS GPIO R/W PE[2] WE GPIO IRQ PE[1] GPIO XIRQ PE[0] GPIO I/O General-purpose I/O I/O I General-purpose I/O Non-maskable level-sensitive interrupt input I/O I O O I/O O O I/O I I I/O O I/O I I I/O I I I/O I O Description External clock selection input during RESET Free-running clock output at Core Clock rate (ECLK x 2) General-purpose I/O MODB input during RESET Instruction tagging low pin Configurable for reduced input threshold General-purpose I/O MODA input during RESET Read enable signal Instruction tagging low pin Configurable for reduced input threshold General-purpose I/O Free-running clock output at the Bus Clock rate or programmable divided in normal modes General-purpose I/O EROMON bit control input during RESET Low strobe bar output Lower data strobe General-purpose I/O Read/write output for external bus Write enable signal General-purpose I/O Maskable level- or falling edge-sensitive interrupt input Mode dependent3 Pin Function after Reset MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 811 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 3 of 7) Port Pin Name Pin Function and Priority ROMCTL1 PK[7] EWAIT GPIO ADDR[22:20] mux ACC[2:0]2 GPIO ADDR[19:16] mux IQSTAT[3:0]2 GPIO IOC[7:0] T PT[7:0] GPIO SS0 PS7 GPIO SCK0 PS6 GPIO MOSI0 PS5 GPIO MISO0 PS4 S PS3 GPIO RXD1 PS2 GPIO TXD0 PS1 GPIO RXD0 PS0 GPIO I/O General-purpose I/O I/O I General-purpose I/O Serial Communication Interface 0 receive pin I/O O General-purpose I/O Serial Communication Interface 0 transmit pin I/O I General-purpose I/O Serial Communication Interface 1 receive pin GPIO TXD1 I/O O General-purpose I/O Serial Communication Interface 1 transmit pin GPIO I/O I/O General-purpose I/O Serial Peripheral Interface 0 master in/slave out pin I/O I/O General-purpose I/O Serial Peripheral Interface 0 master out/slave in pin I/O I/O I/O I/O General-purpose I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode. General-purpose I/O Serial Peripheral Interface 0 serial clock pin I/O I I I/O O I/O O I/O I/O Description ROMON bit control input during RESET External Wait signal Configurable for reduced input threshold General-purpose I/O Extended external bus address output (multiplexed with access master output) General-purpose I/O Extended external bus address output (multiplexed with instruction pipe status bits) General-purpose I/O Enhanced Capture Timer Channels 7–0 input/output GPIO Mode dependent3 Pin Function after Reset K PK[6:4] PK[3:0] MC9S12XDP512 Data Sheet, Rev. 2.17 812 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 4 of 7) Port Pin Name Pin Function and Priority TXCAN3 TXCAN4 PM7 TXD3 GPIO RXCAN3 RXCAN4 PM6 RXD3 GPIO TXCAN2 TXCAN0 TXCAN4 PM5 SCK0 GPIO RXCAN2 RXCAN0 M PM4 MOSI0 GPIO TXCAN1 TXCAN0 PM3 SS0 GPIO RXCAN1 RXCAN0 PM2 MISO0 GPIO TXCAN0 PM1 GPIO RXCAN0 PM0 GPIO I/O General-purpose I/O I/O I General-purpose I/O MSCAN0 receive pin I/O I/O O Serial Peripheral Interface 0 master in/slave out pin General-purpose I/O MSCAN0 transmit pin I/O I/O I I I/O I/O O O RXCAN4 I/O I/O I I I I I/O O O O Serial Communication Interface 3 receive pin General-purpose I/O MSCAN2 transmit pin MSCAN0 transmit pin MSCAN4 transmit pin Serial Peripheral Interface 0 serial clock pin If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode. General-purpose I/O MSCAN2 receive pin MSCAN0 receive pin MSCAN4 receive pin Serial Peripheral Interface 0 master out/slave in pin If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode. General-purpose I/O MSCAN1 transmit pin MSCAN0 transmit pin Serial Peripheral Interface 0 slave select output in master mode, input for slave mode or master mode. General-purpose I/O MSCAN1 receive pin MSCAN0 receive pin GPIO O I/O I I Serial Communication Interface 3 transmit pin General-purpose I/O MSCAN3 receive pin MSCAN4 receive pin I/O O O MSCAN3 transmit pin MSCAN4 transmit pin Description Pin Function after Reset MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 813 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 5 of 7) Port Pin Name Pin Function and Priority PWM7 PP7 SCK2 GPIO/KWP7 PWM6 PP6 SS2 GPIO/KWP6 PWM5 PP5 MOSI2 GPIO/KWP5 PWM4 PP4 P PWM3 PP3 SS1 GPIO/KWP3 PWM2 PP2 SCK1 GPIO/KWP2 PWM1 PP1 MOSI1 GPIO/KWP1 PWM0 PP0 MISO1 GPIO/KWP0 O I/O I/O O I/O I/O O I/O I/O O I/O I/O Pulse Width Modulator output channel 3 Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. General-purpose I/O with interrupt Pulse Width Modulator output channel 2 Serial Peripheral Interface 1 serial clock pin General-purpose I/O with interrupt Pulse Width Modulator output channel 1 Serial Peripheral Interface 1 master out/slave in pin General-purpose I/O with interrupt Pulse Width Modulator output channel 0 Serial Peripheral Interface 1 master in/slave out pin General-purpose I/O with interrupt MISO2 GPIO/KWP4 I/O I/O I/O I/O O I/O I/O O I/O I/O O I/O I/O Description Pulse Width Modulator input/output channel 7 Serial Peripheral Interface 2 serial clock pin General-purpose I/O with interrupt Pulse Width Modulator output channel 6 Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode. General-purpose I/O with interrupt Pulse Width Modulator output channel 5 Serial Peripheral Interface 2 master out/slave in pin General-purpose I/O with interrupt Pulse Width Modulator output channel 4 Serial Peripheral Interface 2 master in/slave out pin General-purpose I/O with interrupt GPIO Pin Function after Reset MC9S12XDP512 Data Sheet, Rev. 2.17 814 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 6 of 7) Port Pin Name Pin Function and Priority SS2 PH7 TXD5 GPIO/KWH7 SCK2 PH6 RXD5 GPIO/KWH6 MOSI2 PH5 TXD4 GPIO/KWH5 MISO2 H PH4 RXD4 GPIO/KWH4 SS1 PH3 GPIO/KWH3 SCK1 PH2 GPIO/KWH2 MOSI1 PH1 GPIO/KWH1 MISO1 PH0 GPIO/KWH0 I/O General-purpose I/O with interrupt I/O I/O General-purpose I/O with interrupt Serial Peripheral Interface 1 master in/slave out pin I/O I/O General-purpose I/O with interrupt Serial Peripheral Interface 1 master out/slave in pin I/O I/O I I/O I/O Serial Communication Interface 4 receive pin General-purpose I/O with interrupt Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. General-purpose I/O with interrupt Serial Peripheral Interface 1 serial clock pin I/O I/O O I/O I/O I I/O I/O O I/O I/O Description Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode Serial Communication Interface 5 transmit pin General-purpose I/O with interrupt Serial Peripheral Interface 2 serial clock pin Serial Communication Interface 5 receive pin General-purpose I/O with interrupt Serial Peripheral Interface 2 master out/slave in pin Serial Communication Interface 4 transmit pin General-purpose I/O with interrupt Serial Peripheral Interface 2 master in/slave out pin GPIO Pin Function after Reset MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 815 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1. Pin Functions and Priorities (Sheet 7 of 7) Port Pin Name Pin Function and Priority TXCAN4 SCL0 PJ7 TXCAN0 GPIO/KWJ7 RXCAN4 SDA0 PJ6 RXCAN0 GPIO/KWJ6 SCL1 PJ5 J CS2 GPIO/KWJ7 SDA1 PJ4 CS0 GPIO/KWJ6 CS1 PJ2 GPIO/KWJ2 TXD2 PJ1 GPIO/KWJ1 RXD2 PJ0 CS3 GPIO/KWJ0 GPIO AD0 PAD[07:00] AN[7:0] GPIO AD1 1 2 I/O O O O I/O I I/O I I/O O O I/O I/O O I/O O I/O O I/O I O I/O I/O I I/O I MSCAN4 transmit pin Description Pin Function after Reset Inter Integrated Circuit 0 serial clock line MSCAN0 transmit pin General-purpose I/O with interrupt MSCAN4 receive pin Inter Integrated Circuit 0 serial data line MSCAN0 receive pin General-purpose I/O with interrupt Inter Integrated Circuit 1 serial clock line Chip select 2 General-purpose I/O with interrupt Inter Integrated Circuit 1 serial data line Chip select 0 General-purpose I/O with interrupt Chip select 1 General-purpose I/O with interrupt Serial Communication Interface 2 transmit pin General-purpose I/O with interrupt Serial Communication Interface 2 receive pin Chip select 3 General-purpose I/O with interrupt General-purpose I/O GPIO ATD0 analog inputs General-purpose I/O GPIO ATD1 analog inputs GPIO PAD[23:08] AN[15:0] Function active when RESET asserted. Only available in emulation modes or in Special Test Mode with IVIS on. 3 Refer also to Table 22-70 and S12X_EBI section. MC9S12XDP512 Data Sheet, Rev. 2.17 816 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3 Memory Map and Register Definition This section provides a detailed description of all PIM registers. 22.3.1 Module Memory Map Table 22-2 shows the register map of the port integration module. Table 22-2. PIM Memory Map (Sheet 1 of 3) Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A : 0x000B 0x000C 0x000D 0x000E : 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 : 0x0031 0x0032 0x0033 0x0034 : 0x023F 0x0240 Use Port A Data Register (PORTA) Port B Data Register (PORTB) Port A Data Direction Register (DDRA) Port B Data Direction Register (DDRB) Port C Data Register (PORTC) Port D Data Register (PORTD) Port C Data Direction Register (DDRC) Port D Data Direction Register (DDRD) Port E Data Register (PORTE) Port E Data Direction Register (DDRE) Non-PIM Address Range Access Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write1 Read / Write1 — Pull-up Up Control Register (PUCR) Reduced Drive Register (RDRIV) Non-PIM Address Range Read / Write1 Read / Write1 — ECLK Control Register (ECLKCTL) PIM Reserved IRQ Control Register (IRQCR) PIM Reserved Non-PIM Address Range Read / Write1 — Read / Write1 — — Port K Data Register (PORTK) Port K Data Direction Register (DDRK) Non-PIM Address Range Read / Write Read / Write — Port T Data Register (PTT) Read / Write MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 817 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-2. PIM Memory Map (Sheet 2 of 3) Address 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F 0x0260 0x0261 0x0262 0x0263 Port T Input Register (PTIT) Port T Data Direction Register (DDRT) Port T Reduced Drive Register (RDRT) Port T Pull Device Enable Register (PERT) Port T Polarity Select Register (PPST) Reserved Reserved Port S Data Register (PTS) Port S Input Register (PTIS) Port S Data Direction Register (DDRS) Port S Reduced Drive Register (RDRS) Port S Pull Device Enable Register (PERS) Port S Polarity Select Register (PPSS) Port S Wired-OR Mode Register (WOMS) Reserved Port M Data Register (PTM) Port M Input Register (PTIM) Port M Data Direction Register (DDRM) Port M Reduced Drive Register (RDRM) Port M Pull Device Enable Register (PERM) Port M Polarity Select Register (PPSM) Port M Wired-OR Mode Register (WOMM) Module Routing Register (MODRR) Port P Data Register (PTP) Port P Input Register (PTIP) Port P Data Direction Register (DDRP) Port P Reduced Drive Register (RDRP) Port P Pull Device Enable Register (PERP) Port P Polarity Select Register (PPSP) Port P Interrupt Enable Register (PIEP) Port P Interrupt Flag Register (PIFP) Port H Data Register (PTH) Port H Input Register (PTIH) Port H Data Direction Register (DDRH) Port H Reduced Drive Register (RDRH) Use Access Read Read / Write Read / Write Read / Write Read / Write — — Read / Write Read Read / Write Read / Write Read / Write Read / Write Read / Write — Read / Write Read Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read Read / Write Read / Write MC9S12XDP512 Data Sheet, Rev. 2.17 818 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-2. PIM Memory Map (Sheet 3 of 3) Address 0x0264 0x0265 0x0266 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 0x0276 0x0277 0x0278 0x0279 0x027A 0x027B 0x027C 0x027D 0x027E 0x027F 1 Use Port H Pull Device Enable Register (PERH) Port H Polarity Select Register (PPSH) Port H Interrupt Enable Register (PIEH) Port H Interrupt Flag Register (PIFH) Port J Data Register (PTJ) Port J Input Register (PTIJ) Port J Data Direction Register (DDRJ) Port J Reduced Drive Register (RDRJ) Port J Pull Device Enable Register (PERJ) Port J Polarity Select Register (PPSJ) Port J Interrupt Enable Register (PIEJ) Port J Interrupt Flag Register (PIFJ) Reserved Port AD0 Data Register 1 (PT1AD0) Reserved Port AD0 Data Direction Register 1 (DDR1AD0) Reserved Port AD0 Reduced Drive Register 1 (RDR1AD0) Reserved Port AD0 Pull Up Enable Register 1 (PER1AD0) Port AD1 Data Register 0 (PT0AD1) Port AD1 Data Register 1 (PT1AD1) Port AD1 Data Direction Register 0 (DDR0AD1) Port AD1 Data Direction Register 1 (DDR1AD1) Port AD1 Reduced Drive Register 0 (RDR0AD1) Port AD1 Reduced Drive Register 1 (RDR1AD1) Port AD1 Pull Up Enable Register 0 (PER0AD1) Port AD1 Pull Up Enable Register 1 (PER1AD1) Access Read / Write Read / Write Read / Write Read / Write Read / Write1 Read Read / Write1 Read / Write1 Read / Write1 Read / Write1 Read / Write1 Read / Write1 — Read / Write — Read / Write — Read / Write — Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Write access not applicable for one or more register bits. Refer to Section 22.3.2, “Register Descriptions”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 819 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2 Register Descriptions Table 22-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. Table 22-3. Pin Configuration Summary DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 IO x x x x x x x 0 1 0 1 0 1 0 1 RDR x x x x x x x 0 0 1 1 0 0 1 1 PE 0 1 1 0 0 1 1 x x x x x x x x PS1 x 0 1 0 1 0 1 x x x x 0 1 0 1 IE2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Input Input Input Input Input Input Input Function Pull Device Disabled Pull Up Pull Down Disabled Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Interrupt Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge Disabled Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Always “0” on Port A, B, C, D, E, K, AD0, and AD1. Applicable only on Port P, H, and J. NOTE All register bits in this module are completely synchronous to internal clocks during a register read. MC9S12XDP512 Data Sheet, Rev. 2.17 820 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PORTA R W PORTB R W DDRA R W DDRB R W PORTC R W PORTD R W DDRC R W DDRD R W PORTE R W DDRE R W R Non-PIM W Address Range PUCR R W RDRIV R W R Non-PIM W Address Range Bit 7 PA7 6 PA6 5 PA5 4 PA4 3 PA3 2 PA2 1 PA1 Bit 0 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 PE1 DDRD0 PE0 PE7 PE6 PE5 PE4 PE3 PE2 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 Non-PIM Address Range PUPKE BKPUE 0 0 PUPEE PUPDE PUPCE PUPBE PUPAE RDPK 0 RDPE RDPD RDPC RDPB RDPA Non-PIM Address Range = Unimplemented or Reserved Figure 22-2. PIM Register Summary (Sheet 1 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 821 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name ECLKCTL R W Reserved R W IRQCR R W Reserved R W Non-PIM R Address W Range PORTK R W DDRK R W Non-PIM R Address W Range PTT R W PTIT R W DDRT R W RDRT R W PERT R W PPST R W Bit 7 NECLK 0 6 NCLKX2 0 5 0 4 0 3 0 2 0 1 EDIV1 0 Bit 0 EDIV0 0 0 0 0 0 IRQE 0 IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 Non-PIM Address Range PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Non-PIM Address Range PTT7 PTIT7 PTT6 PTIT6 PTT5 PTIT5 PTT4 PTIT4 PTT3 PTIT3 PTT2 PTIT2 PTT1 PTIT1 PTT0 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 = Unimplemented or Reserved Figure 22-2. PIM Register Summary (Sheet 2 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 822 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name Reserved R W Reserved R W PTS R W PTIS R W DDRS R W RDRS R W PERS R W PPSS R W WOMS R W Reserved R W PTM R W PTIM R W DDRM R W RDRM R W PERM R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 0 0 PTS7 PTIS7 PTS6 PTIS6 PTS5 PTIS5 PTS4 PTIS4 PTS3 PTIS3 PTS2 PTIS2 PTS1 PTIS1 PTS0 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 0 WOMS6 0 WOMS5 0 WOMS4 0 WOMS3 0 WOMS2 0 WOMS1 0 WOMS0 0 PTM7 PTIM7 PTM6 PTIM6 PTM5 PTIM5 PTM4 PTIM4 PTM3 PTIM3 PTM2 PTIM2 PTM1 PTIM1 PTM0 PTIM0 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 = Unimplemented or Reserved Figure 22-2. PIM Register Summary (Sheet 3 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 823 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PPSM R W WOMM R W MODRR R W PTP R W PTIP R W DDRP R W RDRP R W PERP R W PPSP R W PIEP R W PIFP R W PTH R W PTIH R W DDRH R W RDRH R W Bit 7 PPSM7 6 PPSM6 5 PPSM5 4 PPSM4 3 PPSM3 2 PPSM2 1 PPSM1 Bit 0 PPSM0 WOMM7 0 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP7 PTIP7 PTP6 PTIP6 PTP5 PTIP5 PTP4 PTIP4 PTP3 PTIP3 PTP2 PTIP2 PTP1 PTIP1 PTP0 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 PTH7 PTIH7 PTH6 PTIH6 PTH5 PTIH5 PTH4 PTIH4 PTH3 PTIH3 PTH2 PTIH2 PTH1 PTIH1 PTH0 PTIH0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 = Unimplemented or Reserved Figure 22-2. PIM Register Summary (Sheet 4 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 824 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PERH R W PPSH R W PIEH R W PIFH R W PTJ R W PTIJ R W DDRJ R W RDRJ R W PERJ R W PPSJ R W PIEJ R W PIFJ R W Reserved R W PT1AD0 R W Reserved R W Bit 7 PERH7 6 PERH6 5 PERH5 4 PERH4 3 PERH3 2 PERH2 1 PERH1 Bit 0 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 0 PIFH2 PIFH1 PIFH0 PTJ7 PTIJ7 PTJ6 PTIJ6 PTJ5 PTIJ5 PTJ4 PTIJ4 PTJ2 PTIJ2 PTJ1 PTIJ1 PTJ0 PTIJ0 0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 0 DDRJ2 DDRJ1 DDRJ0 RDRJ7 RDRJ6 RDRJ5 RDRJ4 0 RDRJ2 RDRJ1 RDRJ0 PERJ7 PERJ6 PERJ5 PERJ4 0 PERJ2 PERJ1 PERJ0 PPSJ7 PPSJ6 PPSJ5 PPSJ4 0 PPSJ2 PPSJ1 PPSJ0 PIEJ7 PIEJ6 PIEJ5 PIEJ4 0 PIEJ2 PIEJ1 PIEJ0 PPSJ7 0 PPSJ6 0 PPSJ5 0 PPSJ4 0 0 PPSJ2 0 PPSJ1 0 PPSJ0 0 0 PT1AD07 0 PT1AD06 0 PT1AD05 0 PT1AD04 0 PT1AD03 0 PT1AD02 0 PT1AD01 0 PT1AD00 0 = Unimplemented or Reserved Figure 22-2. PIM Register Summary (Sheet 5 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 825 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name Name R W Reserved R W RDR1AD0 R W Reserved R W PER1AD0 R W PT0AD1 R W PT1AD1 R W DDR0AD1 R W DDR1AD1 R W RDR0AD1 R W RDR1AD1 R W PER0AD1 R W PER1AD1 R W Bit 7 6 5 4 3 2 1 Bit 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19 PT1AD18 DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116 DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116 RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18 PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116 PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 PER1AD19 = Unimplemented or Reserved PER1AD18 Figure 22-2. PIM Register Summary (Sheet 6 of 6) MC9S12XDP512 Data Sheet, Rev. 2.17 826 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.1 Port A Data Register (PORTA) 7 6 5 4 3 2 1 0 R PA7 W Alt. Function Reset ADDR15 mux IVD15 0 ADDR14 mux IVD14 0 ADDR13 mux IVD13 0 ADDR12 mux IVD12 0 ADDR11 mux IVD11 0 ADDR10 mux IVD10 0 ADDR9 mux IVD9 0 ADDR8 mux IVD8 0 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Figure 22-3. Port A Data Register (PORTA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-4. PORTA Field Descriptions Field 7–0 PA[7:0] Description Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in expanded modes. When this port is not used for external addresses, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 22.3.2.2 Port B Data Register (PORTB) 7 6 5 4 3 2 1 0 R PB7 W Alt. Function ADDR7 mux IVD7 0 ADDR6 mux IVD6 0 ADDR5 mux IVD5 0 ADDR4 mux IVD4 0 ADDR3 mux IVD3 0 ADDR2 mux IVD2 0 ADDR1 mux IVD1 0 ADDR0 mux IVD0 or UDS 0 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Reset Figure 22-4. Port B Data Register (PORTB) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 827 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-5. PORTB Field Descriptions Field 7–0 PB[7:0] Description Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XDP512 Data Sheet, Rev. 2.17 828 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.3 Port A Data Direction Register (DDRA) 7 6 5 4 3 2 1 0 R DDRA7 W Reset 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Figure 22-5. Port A Data Direction Register (DDRA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-6. DDRA Field Descriptions Field 7–0 DDRA[7:0] Description Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTA after changing the DDRA register. 22.3.2.4 Port B Data Direction Register (DDRB) 7 6 5 4 3 2 1 0 R DDRB7 W Reset 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Figure 22-6. Port B Data Direction Register (DDRB) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-7. DDRB Field Descriptions Field 7–0 DDRB[7:0] Description Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTB after changing the DDRB register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 829 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.5 Port C Data Register (PORTC) 7 6 5 4 3 2 1 0 R PC7 W Exp.: Reset DATA15 0 DATA14 0 DATA13 0 DATA12 0 DATA11 0 DATA10 0 DATA9 0 DATA8 0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Figure 22-7. Port C Data Register (PORTC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-8. PORTC Field Descriptions Field 7–0 PC[7:0] Description Port C — Port C pins 7–0 are associated with data I/O lines DATA15 through DATA8 respectively in expanded modes. When this port is not used for external data, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 22.3.2.6 Port D Data Register (PORTD) 7 6 5 4 3 2 1 0 R PD7 W Exp.: Reset DATA7 0 DATA6 0 DATA5 0 DATA4 0 DATA3 0 DATA2 0 DATA1 0 DATA0 0 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Figure 22-8. Port D Data Register (PORTD) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-9. PORTD Field Descriptions Field 7–0 PD[7:0] Description Port D — Port D pins 7–0 are associated with data I/O lines DATA7 through DATA0 respectively in expanded modes. When this port is not used for external data, these pins can be used as general purpose I/O. — If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XDP512 Data Sheet, Rev. 2.17 830 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.7 Port C Data Direction Register (DDRC) 7 6 5 4 3 2 1 0 R DDRC7 W Reset 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Figure 22-9. Port C Data Direction Register (DDRC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-10. DDRC Field Descriptions Field 7–0 DDRC[7:0] Description Data Direction Port C — This register controls the data direction for port C. When Port C is operating as a general purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTC after changing the DDRC register. 22.3.2.8 Port D Data Direction Register (DDRD) 7 6 5 4 3 2 1 0 R DDRD7 W Reset 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Figure 22-10. Port D Data Direction Register (DDRD) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-11. DDRD Field Descriptions Field 7–0 DDRD[7:0] Description Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTD after changing the DDRD register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 831 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.9 Port E Data Register (PORTE) 7 6 5 4 3 2 1 0 R PE7 W XCLKS or ECLKX2 0 MODB or TAGHI 0 MODA or RE or TAGLO 0 EROMCTL or LSTRB or LDS 0 R/W or WE 0 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Alt. Func. ECLK IRQ XIRQ Reset 0 —1 —1 = Unimplemented or Reserved Figure 22-11. Port E Data Register (PORTE) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-12. PORTE Field Descriptions Field 7–0 PE[7:0] Description Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI, TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ. When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and pins 1–0 can be used as general purpose inputs. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low. Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low. MC9S12XDP512 Data Sheet, Rev. 2.17 832 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.10 Port E Data Direction Register (DDRE) 7 6 5 4 3 2 1 0 R DDRE7 W Reset 0 0 0 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 0 0 = Unimplemented or Reserved Figure 22-12. Port E Data Direction Register (DDRE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-13. DDRE Field Descriptions Field 7–0 DDRE[7:2] Description Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled. 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTE after changing the DDRE register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 833 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 7 6 5 4 3 2 1 0 R PUPKE W Reset 1 1 BKPUE 0 PUPEE 0 1 PUPDE 0 PUPCE 0 PUPBE 0 PUPAE 0 = Unimplemented or Reserved Figure 22-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only. This register is used to enable pull-up devices for the associated ports A, B, C, D, E, and K. Pull-up devices are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input. Table 22-14. PUCR Field Descriptions Field 7 PUPKE 6 BKPUE 4 PUPEE Pull-up Port K Enable 0 Port K pull-up devices are disabled. 1 Enable pull-up devices for Port K input pins. BKGD and VREGEN Pin Pull-up Enable 0 BKGD and VREGEN pull-up devices are disabled. 1 Enable pull-up devices on BKGD and VREGEN pins. Pull-up Port E Enable 0 Port E pull-up devices on bit 7, 4–0 are disabled. 1 Enable pull-up devices for Port E input pins bits 7, 4–0. Note: Bits 5 and 6 of Port E have pull-down devices which are only enabled during reset. This bit has no effect on these pins. Pull-up Port D Enable 0 Port D pull-up devices are disabled. 1 Enable pull-up devices for all Port D input pins. Pull-up Port C Enable 0 Port C pull-up devices are disabled. 1 Enable pull-up devices for all Port C input pins. Pull-up Port B Enable 0 Port B pull-up devices are disabled. 1 Enable pull-up devices for all Port B input pins. Pull-up Port A Enable 0 Port A pull-up devices are disabled. 1 Enable pull-up devices for all Port A input pins. Description 3 PUPDE 2 PUPCE 1 PUPBE 0 PUPAE MC9S12XDP512 Data Sheet, Rev. 2.17 834 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.12 S12X_EBI Ports Reduced Drive Register (RDRIV) 7 6 5 4 3 2 1 0 R RDPK W Reset 0 0 0 RDPE RDPD 0 RDPC 0 RDPB 0 RDPA 0 0 0 0 = Unimplemented or Reserved Figure 22-14. S12X_EBI Ports Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register is used to select reduced drive for the pins associated with the S12X_EBI ports A, B, C, D, E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is independent of which function is being used on a particular pin. The reduced drive functionality does not take effect on the pins in emulation modes. Table 22-15. RDRIV Field Descriptions Field 7 RDPK 4 RDPE 3 RDPD 2 RDPC 1 RDPB 0 RDPA Description Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. Reduced Drive of Port D 0 All port D output pins have full drive enabled. 1 All port D output pins have reduced drive enabled. Reduced Drive of Port C 0 All port C output pins have full drive enabled. 1 All port C output pins have reduced drive enabled. Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. Reduced Drive of Ports A 0 All Port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 835 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.13 ECLK Control Register (ECLKCTL) 7 6 5 4 3 2 1 0 R NECLK W Reset1 SS ES ST EX NS NX Mode Dependent 0 1 0 0 1 0 1 1 1 1 1 1 1 NCLKX2 0 0 0 0 EDIV1 EDIV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mode Special Single-Chip Emulation Single-Chip Special Test Emulation Expanded Normal Single-Chip Normal Expanded = Unimplemented or Reserved Figure 22-15. ECLK Control Register (ECLKCTL) 1 Reset values in emulation modes are identical to those of the target mode. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider. Table 22-16. ECLKCTL Field Descriptions Field 7 NECLK Description No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLK enabled 1 ECLK disabled MC9S12XDP512 Data Sheet, Rev. 2.17 836 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-16. ECLKCTL Field Descriptions (continued) Field 6 NCLKX2 Description No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLKX2 is enabled 1 ECLKX2 is disabled Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The usage of the bits is shown in Table 22-17. Divider is always disabled in emulation modes and active as programmed in all other operating modes. 1–0 EDIV[1:0] Table 22-17. Free-Running ECLK Clock Rate EDIV[1:0] 00 01 10 11 Rate of Free-Running ECLK ECLK = Bus clock rate ECLK = Bus clock rate divided by 2 ECLK = Bus clock rate divided by 3 ECLK = Bus clock rate divided by 4 22.3.2.14 IRQ Control Register (IRQCR) 7 6 5 4 3 2 1 0 R IRQE W Reset 0 1 IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 22-16. IRQ Control Register (IRQCR) Read: See individual bit descriptions below. Write: See individual bit descriptions below. Table 22-18. IRQCR Field Descriptions Field 7 IRQE Description IRQ Select Edge Sensitive Only Special modes: Read or write anytime. Normal and emulation modes: Read anytime, write once. 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. External IRQ Enable Read or write anytime. 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. 6 IRQEN MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 837 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.15 Port K Data Register (PORTK) 7 6 5 4 3 2 1 0 R PK7 W Alt. Func. Reset ROMCTL or EWAIT 0 ADDR22 mux NOACC 0 ADDR21 0 ADDR20 0 ADDR19 mux IQSTAT3 0 ADDR18 mux IQSTAT2 0 ADDR17 mux IQSTAT1 0 ADDR16 mux IQSTAT0 0 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Figure 22-17. Port K Data Register (PORTK) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-19. PORTK Field Descriptions Field 7–0 PK[7:0] Description Port K — Port K pins 7–0 are associated with external bus control signals and internal memory expansion emulation pins. These include ADDR22-ADDR16, No-Access (NOACC), External Wait (EWAIT) and instruction pipe signals IQSTAT3-IQSTAT0. Bits 6-0 carry the external addresses in all expanded modes. In emulation or special test mode with internal visibility enabled the address is multiplexed with the alternate functions NOACC and IQSTAT on the respective pins. In single-chip modes the port pins can be used as general-purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 22.3.2.16 Port K Data Direction Register (DDRK) 7 6 5 4 3 2 1 0 R DDRK7 W Reset 0 0 0 0 0 0 0 0 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Figure 22-18. Port K Data Direction Register (DDRK) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. This register controls the data direction for port K. When Port K is operating as a general purpose I/O port, DDRK determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. MC9S12XDP512 Data Sheet, Rev. 2.17 838 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-20. DDRK Field Descriptions Field 7–0 DDRK[7:0] Description Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTK after changing the DDRK register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 839 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.17 Port T Data Register (PTT) 7 6 5 4 3 2 1 0 R PTT7 W ECT Reset IOC7 0 IOC6 0 IOC5 0 IOC4 0 IOC3 0 IOC2 0 IOC1 0 IOC0 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 Figure 22-19. Port T Data Register (PTT) Read: Anytime. Write: Anytime. Table 22-21. PTT Field Descriptions Field 7–0 PTT[7:0] Description Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used with the ECT, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 22.3.2.18 Port T Input Register (PTIT) 7 6 5 4 3 2 1 0 R W Reset1 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 — — — — — — — — = Unimplemented or Reserved Figure 22-20. Port T Input Register (PTIT) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. Table 22-22. PTIT Field Descriptions Field 7–0 PTIT[7:0] Description Port T Input — This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 840 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.19 Port T Data Direction Register (DDRT) 7 6 5 4 3 2 1 0 R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 Figure 22-21. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this case the data direction bits will not change. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer input capture always monitors the state of the pin. Table 22-23. DDRT Field Descriptions Field 7–0 DDRT[7:0] Description Data Direction Port T 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 841 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.20 Port T Reduced Drive Register (RDRT) 7 6 5 4 3 2 1 0 R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 Figure 22-22. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-24. RDRT Field Descriptions Field 7–0 RDRT[7:0] Description Reduced Drive Port T 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.21 Port T Pull Device Enable Register (PERT) 7 6 5 4 3 2 1 0 R PERT7 W Reset 0 0 0 0 0 0 0 0 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 Figure 22-23. Port T Pull Device Enable Register (PERT) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. Table 22-25. PERT Field Descriptions Field 7–0 PERT[7:0] Description Pull Device Enable Port T 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 842 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.22 Port T Polarity Select Register (PPST) 7 6 5 4 3 2 1 0 R PPST7 W Reset 0 0 0 0 0 0 0 0 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 Figure 22-24. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 22-26. PPST Field Descriptions Field 7–0 PPST[7:0] Description Pull Select Port T 0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 22.3.2.23 Port S Data Register (PTS) 7 6 5 4 3 2 1 0 R PTS7 W SCI/SPI Reset SS0 0 SCK0 0 MOSI0 0 MISO0 0 TXD1 0 RXD1 0 TXD0 0 RXD0 0 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 Figure 22-25. Port S Data Register (PTS) Read: Anytime. Write: Anytime. Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be used as general purpose I/O. Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and 1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and 0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with the SCI, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 843 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.24 Port S Input Register (PTIS) 7 6 5 4 3 2 1 0 R W Reset1 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 — — — — — — — — = Unimplemented or Reserved Figure 22-26. Port S Input Register (PTIS) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 844 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.25 Port S Data Direction Register (DDRS) 7 6 5 4 3 2 1 0 R DDRS7 W Reset 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 Figure 22-27. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. Table 22-27. DDRS Field Descriptions Field 7–0 DDRS[7:0] Description Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 845 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.26 Port S Reduced Drive Register (RDRS) 7 6 5 4 3 2 1 0 R RDRS7 W Reset 0 0 0 0 0 0 0 0 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 Figure 22-28. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-28. RDRS Field Descriptions Field 7–0 RDRS[7:0] Description Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.27 Port S Pull Device Enable Register (PERS) 7 6 5 4 3 2 1 0 R PERS7 W Reset 1 1 1 1 1 1 1 1 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 Figure 22-29. Port S Pull Device Enable Register (PERS) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. Table 22-29. PERS Field Descriptions Field 7–0 PERS[7:0] Description Pull Device Enable Port S 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 846 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.28 Port S Polarity Select Register (PPSS) 7 6 5 4 3 2 1 0 R PPSS7 W Reset 0 0 0 0 0 0 0 0 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 Figure 22-30. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 22-30. PPSS Field Descriptions Field 7–0 PPSS[7:0] Description Pull Select Port S 0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-OR output. 1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input. 22.3.2.29 Port S Wired-OR Mode Register (WOMS) 7 6 5 4 3 2 1 0 R WOMS7 W Reset 0 0 0 0 0 0 0 0 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 Figure 22-31. Port S Wired-OR Mode Register (WOMS) Read: Anytime. Write: Anytime. This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. Table 22-31. WOMS Field Descriptions Field 7–0 Wired-OR Mode Port S WOMS[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 847 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.30 Port M Data Register (PTM) 7 6 5 4 3 2 1 0 R PTM7 W CAN Routed CAN0 Routed CAN4 Routed SPIO Reset 0 0 TXCAN4 RXCAN4 TXCAN3 RXCAN3 TXCAN2 TXCAN0 TXCAN4 SCK0 0 RXCAN2 RXCAN0 RXCAN4 MOSI0 0 SS0 0 MISO0 0 0 0 TXCAN1 TXCAN0 RXCAN1 RXCAN0 TXCAN0 RXCAN0 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 Figure 22-32. Port M Data Register (PTM) Read: Anytime. Write: Anytime. Port M pins 75–0 are associated with the CAN0, CAN1, CAN2, CAN3, SCI3, as well as the routed CAN0, CAN4, and SPI0 modules. When not used with any of the peripherals, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. Table 22-32. PTM Field Descriptions Field 7–6 PTM[7:6] Description The CAN3 function (TXCAN3 and RXCAN3) takes precedence over the CAN4, SCI3 and the general purpose I/O function if the CAN3 module is enabled. Refer to MSCAN section for details. The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the SCI3 and the general purpose I/O function if the CAN4 module is enabled. Refer to MSCAN section for details. The SCI3 function (TXD3 and RXD3) takes precedence over the general purpose I/O function if the SCI3 module is enabled. Refer to SCI section for details. The CAN2 function (TXCAN2 and RXCAN2) takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose I/O function if the CAN2 module is enabled{pim_9xd_prio.m}. The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed CAN4, the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function (TXCAN4 and RXCAN4) takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. Refer to MSCAN section for details. The routed SPI0 function (SCK0 and MOSI0) takes precedence of the general purpose I/O function if the routed SPI0 is enabled. Refer to SPI section for details. 5–4 PTM[5:4] MC9S12XDP512 Data Sheet, Rev. 2.17 848 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-32. PTM Field Descriptions (continued) Field 3–2 PTM[3:2] Description The CAN1 function (TXCAN1 and RXCAN1) takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details. The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed SPI0 is enabled and not in bidirectional mode. Refer to SPI section for details. 1–0 PTM[1:0] The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0 module is enabled. Refer to MSCAN section for details. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 849 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.31 Port M Input Register (PTIM) 7 6 5 4 3 2 1 0 R W Reset1 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 — — — — — — — — = Unimplemented or Reserved Figure 22-33. Port M Input Register (PTIM) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 850 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.32 Port M Data Direction Register (DDRM) 7 6 5 4 3 2 1 0 R DDRM7 W Reset 0 0 0 0 0 0 0 0 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 Figure 22-34. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output (TXCAN[3:0], TXD3). TheyAlso forces the I/O state to be an input for each port line associated with an enabled input (RXCAN[3:0], RXD3). In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. Table 22-33. DDRM Field Descriptions Field 7–0 DDRM[7:0] Description Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 851 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.33 Port M Reduced Drive Register (RDRM) 7 6 5 4 3 2 1 0 R RDRM7 W Reset 0 0 0 0 0 0 0 0 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 Figure 22-35. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-34. RDRM Field Descriptions Field 7–0 RDRM[7:0] Description Reduced Drive Port M 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.34 Port M Pull Device Enable Register (PERM) 7 6 5 4 3 2 1 0 R PERM7 W Reset 0 0 0 0 0 0 0 0 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 Figure 22-36. Port M Pull Device Enable Register (PERM) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset no pull device is enabled. Table 22-35. PERM Field Descriptions Field 7–0 PERM[7:0] Description Pull Device Enable Port M 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 852 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.35 Port M Polarity Select Register (PPSM) 7 6 5 4 3 2 1 0 R PPSM7 W Reset 0 0 0 0 0 0 0 0 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 Figure 22-37. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN[3:0] inputs, but not a pull-down. Table 22-36. PPSM Field Descriptions Field 7–0 PPSM[7:0] Description Pull Select Port M 0 A pull-up device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as general purpose or RXCAN input. 1 A pull-down device is connected to the associated port M pin, if enabled by the associated bit in register PERM and if the port is used as a general purpose but not as RXCAN. 22.3.2.36 Port M Wired-OR Mode Register (WOMM) 7 6 5 4 3 2 1 0 R WOMM7 W Reset 0 0 0 0 0 0 0 0 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 Figure 22-38. Port M Wired-OR Mode Register (WOMM) Read: Anytime. Write: Anytime. This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a multipoint connection of several serial modules. This bit has no influence on pins used as inputs. Table 22-37. WOMM Field Descriptions Field 7–0 Wired-OR Mode Port M WOMM[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 853 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.37 Module Routing Register (MODRR) 7 6 5 4 3 2 1 0 R W Reset 0 MODRR6 0 0 MODRR5 0 MODRR4 0 MODRR3 0 MODRR2 0 MODRR1 0 MODRR0 0 = Unimplemented or Reserved Figure 22-39. Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 22-38. Module Routing Summary MODRR Module 6 x CAN0 x x x x CAN4 x x x 5 x x x x x x x x 4 x x x x x x x x 3 x x x x 0 0 1 1 2 x x x x 0 1 0 1 1 0 0 1 1 x x x x 0 0 1 0 1 x x x x MISO SPI0 SPI1 SPI2 x x x x 0 1 x x 0 1 x x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x PS4 PM2 PP0 PH0 PP4 PH4 RXCAN PM0 PM2 PM4 PJ6 PJ6 PM4 PM6 Reserved MOSI PS5 PM4 PP1 PH1 PP5 PH5 SCK PS6 PM5 PP2 PH2 PP7 PH6 SS PS7 PM3 PP3 PH3 PP6 PH7 TXCAN PM1 PM3 PM5 PJ7 PJ7 PM5 PM7 Related Pins MC9S12XDP512 Data Sheet, Rev. 2.17 854 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.38 Port P Data Register (PTP) 7 6 5 4 3 2 1 0 R PTP7 W PWM SPI Reset PWM7 SCK2 0 PWM6 SS2 0 PWM5 MOSI2 0 PWM4 MISO2 0 PWM3 SS1 0 PWM2 SCK1 0 PWM1 MOSI1 0 PWM0 MISO1 0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 Figure 22-40. Port P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules. These pins can be used as general purpose I/O when not used with any of the peripherals. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. The PWM function takes precedence over the general purpose I/O and the SPI2 or SPI1 function if the associated PWM channel is enabled. While channels 6 and 5-0 are output only if the respective channel is enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section for details. The SPI2 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section for details. The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section for details. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 855 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.39 Port P Input Register (PTIP) 7 6 5 4 3 2 1 0 R W Reset1 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 — — — — — — — — = Unimplemented or Reserved Figure 22-41. Port P Input Register (PTIP) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 856 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.40 Port P Data Direction Register (DDRP) 7 6 5 4 3 2 1 0 R DDRP7 W Reset 0 0 0 0 0 0 0 0 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 Figure 22-42. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on the pins. The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for details. If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details. The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled. Table 22-39. DDRP Field Descriptions Field 7–0 DDRP[7:0] Description Data Direction Port P 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 857 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.41 Port P Reduced Drive Register (RDRP) 7 6 5 4 3 2 1 0 R RDRP7 W Reset 0 0 0 0 0 0 0 0 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 Figure 22-43. Port P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-40. RDRP Field Descriptions Field 7–0 RDRP[7:0] Description Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.42 Port P Pull Device Enable Register (PERP) 7 6 5 4 3 2 1 0 R PERP7 W Reset 0 0 0 0 0 0 0 0 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Figure 22-44. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. Table 22-41. PERP Field Descriptions Field 7–0 PERP[7:0] Description Pull Device Enable Port P 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 858 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.43 Port P Polarity Select Register (PPSP) 7 6 5 4 3 2 1 0 R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 Figure 22-45. Port P Polarity Select Register (PPSP) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-42. PPSP Field Descriptions Field 7–0 PPSP[7:0] Description Polarity Select Port P 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 22.3.2.44 Port P Interrupt Enable Register (PIEP) 7 6 5 4 3 2 1 0 R PIEP7 W Reset 0 0 0 0 0 0 0 0 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 Figure 22-46. Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. Table 22-43. PIEP Field Descriptions Field 7–0 PIEP[7:0] Interrupt Enable Port P 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 859 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.45 Port P Interrupt Flag Register (PIFP) 7 6 5 4 3 2 1 0 R PIFP7 W Reset 0 0 0 0 0 0 0 0 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Figure 22-47. Port P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the PIFP register. Writing a “0” has no effect. Table 22-44. PIFP Field Descriptions Field 7–0 PIFP[7:0] Description Interrupt Flags Port P 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a logic level “1” clears the associated flag. MC9S12XDP512 Data Sheet, Rev. 2.17 860 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.46 Port H Data Register (PTH) 7 6 5 4 3 2 1 0 R PTH7 W Routed SPI Reset SS2 0 SCK2 0 MOSI2 0 MISO2 0 SS1 0 SCK1 0 MOSI1 0 MISO1 0 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 Figure 22-48. Port H Data Register (PTH) Read: Anytime. Write: Anytime. Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules. These pins can be used as general purpose I/O when not used with any of the peripherals. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. The routed SPI2 function takes precedence over the SCI4 and SCI5 and the general purpose I/O function if the routed SPI2 module is enabled. Refer to SPI section for details. The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is enabled. Refer to SPI section for details. The SCI4 and SCI5 function takes precedence over the general purpose I/O function if the SCI4 or SCI5 is enabled. Refer to SCI section for details. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 861 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.47 Port H Input Register (PTIH) 7 6 5 4 3 2 1 0 R W Reset1 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 — — — — — — — — = Unimplemented or Reserved Figure 22-49. Port H Input Register (PTIH) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 862 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.48 Port H Data Direction Register (DDRH) 7 6 5 4 3 2 1 0 R DDRH7 W Reset 0 0 0 0 0 0 0 0 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 Figure 22-50. Port H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output. If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins. The SCI forces the I/O state to be an output for each port line associated with an enabled output (TXD5, TXD4). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD5, RXD4). In those cases the data direction bits will not change. If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details. The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are disabled. Table 22-45. DDRH Field Descriptions Field 7–0 DDRH[7:0] Description Data Direction Port H 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 863 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.49 Port H Reduced Drive Register (RDRH) 7 6 5 4 3 2 1 0 R RDRH7 W Reset 0 0 0 0 0 0 0 0 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 Figure 22-51. Port H Reduced Drive Register (RDRH) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port H output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-46. RDRH Field Descriptions Field 7–0 RDRH[7:0] Description Reduced Drive Port H 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.50 Port H Pull Device Enable Register (PERH) 7 6 5 4 3 2 1 0 R PERH7 W Reset 0 0 0 0 0 0 0 0 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 Figure 22-52. Port H Pull Device Enable Register (PERH) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. Table 22-47. PERH Field Descriptions Field 7–0 PERH[7:0] Description Pull Device Enable Port H 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 864 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.51 Port H Polarity Select Register (PPSH) 7 6 5 4 3 2 1 0 R PPSH7 W Reset 0 0 0 0 0 0 0 0 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 Figure 22-53. Port H Polarity Select Register (PPSH) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-48. PPSH Field Descriptions Field 7–0 PPSH[7:0] Description Polarity Select Port H 0 Falling edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 1 Rising edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 22.3.2.52 Port H Interrupt Enable Register (PIEH) 7 6 5 4 3 2 1 0 R PIEH7 W Reset 0 0 0 0 0 0 0 0 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 Figure 22-54. Port H Interrupt Enable Register (PIEH) Read: Anytime. Write: Anytime. This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H. Table 22-49. PIEH Field Descriptions Field 7–0 PIEH[7:0] Interrupt Enable Port H 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 865 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.53 Port H Interrupt Flag Register (PIFH) 7 6 5 4 3 2 1 0 R PIFH7 W Reset 0 0 0 0 0 0 0 0 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 Figure 22-55. Port H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register. To clear this flag, write logic level “1” to the corresponding bit in the PIFH register. Writing a “0” has no effect. Table 22-50. PIFH Field Descriptions Field 7–0 PIFH[7:0] Description Interrupt Flags Port H 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a logic level “1” clears the associated flag. MC9S12XDP512 Data Sheet, Rev. 2.17 866 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.54 Port J Data Register (PTJ) 7 6 5 4 3 2 1 0 R PTJ7 W CAN4/ SCI2 IICO IIC1 Routed CAN0 Alt. Function Reset 0 0 TXCAN0 RXCAN0 CS2 0 CS0 0 TXCAN4 SCL0 RXCAN4 SDA0 SCL1 SDA1 PTJ6 PTJ5 PTJ4 0 PTJ2 PTJ1 PTJ0 TXD2 RXD2 CS1 0 0 0 CS3 0 = Unimplemented or Reserved Figure 22-56. Port J Data Register (PTJ) Read: Anytime. Write: Anytime. Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0 and IIC1, the routed CAN0 modules and chip select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not used with any of the peripherals. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. Table 22-51. PTJ Field Descriptions Field 7–6 PJ[7:0] Description The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the CAN4 module is enabled. The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as open drain outputs. Refer to IIC section for details. The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details. 5-4 PJ[5:4] The IIC1 function (SCL1 and SDA1) takes precedence over the chip select (CS0, CS2) and general purpose I/O function if the IIC1 is enabled. The chip selects (CS0, CS2) take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1 outputs are configured as open drain outputs. Refer to IIC section for details. The chip select function (CS1) takes precedence over the general purpose I/O. 2 PJ2 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 867 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-51. PTJ Field Descriptions (continued) Field 1 PJ1 0 PJ0 Description The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer to SCI section for details. The SCI2 function takes precedence over the chip select (CS3) and the general purpose I/O function if the SCI2 module is enabled. The chip select (CS3) takes precedence over the general purpose I/O function. Refer to SCI section for details. MC9S12XDP512 Data Sheet, Rev. 2.17 868 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.55 Port J Input Register (PTIJ) 7 6 5 4 3 2 1 0 R W Reset1 PTIJ7 PTIJ6 PTIJ5 PTIJ4 0 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 22-57. Port J Input Register (PTIJ) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This can be used to detect overload or short circuit conditions on output pins. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 869 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.56 Port J Data Direction Register (DDRJ) 7 6 5 4 3 2 1 0 R DDRJ7 W Reset 0 0 0 0 DDRJ6 DDRJ5 DDRJ4 0 DDRJ2 0 0 DDRJ1 0 DDRJ0 0 = Unimplemented or Reserved Figure 22-58. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will not change. The SCI2 forces the I/O state to be an output for each port line associated with an enabled output (TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD2). In these cases the data direction bits will not change. The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. Table 22-52. DDRJ Field Descriptions Field 7–0 DDRJ[7:4] DDRJ[2:0] Description Data Direction Port J 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register. MC9S12XDP512 Data Sheet, Rev. 2.17 870 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.57 Port J Reduced Drive Register (RDRJ) 7 6 5 4 3 2 1 0 R RDRJ7 W Reset 0 0 0 0 RDRJ6 RDRJ5 RDRJ4 0 RDRJ2 0 0 RDRJ1 0 RDRJ0 0 = Unimplemented or Reserved Figure 22-59. Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-53. RDRJ Field Descriptions Field 7–0 RDRJ[7:4] RDRJ[2:0] Description Reduced Drive Port J 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.58 Port J Pull Device Enable Register (PERJ) 7 6 5 4 3 2 1 0 R PERJ7 W Reset 1 1 1 1 PERJ6 PERJ5 PERJ4 0 PERJ2 0 1 PERJ1 1 PERJ0 1 = Unimplemented or Reserved Figure 22-60. Port J Pull Device Enable Register (PERJ) Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. Table 22-54. PERJ Field Descriptions Field 7–0 PERJ[7:4] PERJ[2:0] Description Pull Device Enable Port J 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 871 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.59 Port J Polarity Select Register (PPSJ) 7 6 5 4 3 2 1 0 R PPSJ7 W Reset 0 0 0 0 PPSJ6 PPSJ5 PPSJ4 0 PPSJ2 0 0 PPSJ1 0 PPSJ0 0 = Unimplemented or Reserved Figure 22-61. Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-55. PPSJ Field Descriptions Field 7–0 PPSJ[7:4] PPSJ[2:0] Description Polarity Select Port J 0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as general purpose input or as IIC port. 1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. 22.3.2.60 Port J Interrupt Enable Register (PIEJ) 7 6 5 4 3 2 1 0 R PIEJ7 W Reset 0 0 0 0 PIEJ6 PIEJ5 PIEJ4 0 PIEJ2 0 0 PIEJ1 0 PIEJ0 0 = Unimplemented or Reserved Figure 22-62. Port J Interrupt Enable Register (PIEJ) This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J. Table 22-56. PIEJ Field Descriptions Field 7–0 PIEJ[7:4] PIEJ[2:0] Interrupt Enable Port J 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 872 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.61 Port J Interrupt Flag Register (PIFJ) 7 6 5 4 3 2 1 0 R PIFJ7 W Reset 0 0 0 0 PIFJ6 PIFJ5 PIFJ4 0 PIFJ2 0 0 PIFJ1 0 PIFJ0 0 = Unimplemented or Reserved Figure 22-63. Port J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ register. Writing a “0” has no effect. Table 22-57. PIEJ Field Descriptions Field 7–0 PIFJ[7:4] PIFJ[2:0] Description Interrupt Flags Port J 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a logic level “1” clears the associated flag. 22.3.2.62 Port AD0 Data Register 1 (PT1AD0) 7 6 5 4 3 2 1 0 R PT1AD07 W Reset 0 0 0 0 0 0 0 0 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 Figure 22-64. Port AD0 Data Register 1 (PT1AD0) Read: Anytime. Write: Anytime. This register is associated with AD0 pins PAD[7:0]. These pins can also be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 873 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0) 7 6 5 4 3 2 1 0 R DDR1AD07 W Reset 0 0 0 0 0 0 0 0 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output. Table 22-58. DDR1AD0 Field Descriptions Field 7–0 DDR1AD0[7:0] Description Data Direction Port AD0 Register 1 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD01 register, when changing the DDR1AD0 register. Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to be set to logic level “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 874 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0) 7 6 5 4 3 2 1 0 R RDR1AD07 W Reset 0 0 0 0 0 0 0 0 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 Figure 22-66. Port AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the port is used as input this bit is ignored. Table 22-59. RDR1AD0 Field Descriptions Field 7–0 RDR1AD0[7:0] Description Reduced Drive Port AD0 Register 1 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0) 7 6 5 4 3 2 1 0 R PER1AD07 W Reset 0 0 0 0 0 0 0 0 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 Figure 22-67. Port AD0 Pull Up Enable Register 1 (PER1AD0) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. Table 22-60. PER1AD0 Field Descriptions Field 7–0 PER1AD0[7:0] Pull Device Enable Port AD0 Register 1 0 Pull-up device is disabled. 1 Pull-up device is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 875 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.66 Port AD1 Data Register 0 (PT0AD1) 7 6 5 4 3 2 1 0 R PT0AD123 W Reset 0 0 0 0 0 0 0 0 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 Figure 22-68. Port AD1 Data Register 0 (PT0AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 22.3.2.67 Port AD1 Data Register 1 (PT1AD1) 7 6 5 4 3 2 1 0 R PT1AD115 W Reset 0 0 0 0 0 0 0 0 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19 PT1AD18 Figure 22-69. Port AD1 Data Register 1 (PT1AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[15:08]. These pins can also be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. MC9S12XDP512 Data Sheet, Rev. 2.17 876 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1) 7 6 5 4 3 2 1 0 R DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-70. Port AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output. Table 22-61. DDR0AD1 Field Descriptions Field Description 7–0 Data Direction Port AD1 Register 0 DDR0AD1[23:16] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD10 register, when changing the DDR0AD1 register. Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has to be set to logic level “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 877 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1) 7 6 5 4 3 2 1 0 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 W Reset 0 0 0 0 0 0 0 0 DDR1AD18 Figure 22-71. Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output. Table 22-62. DDR1AD1 Field Descriptions Field 7–0 DDR1AD1[15:8] Description Data Direction Port AD1 Register 1 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTAD11 register, when changing the DDR1AD1 register. Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has to be set to logic level “1”. MC9S12XDP512 Data Sheet, Rev. 2.17 878 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1) 7 6 5 4 3 2 1 0 R RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-72. Port AD1 Reduced Drive Register 0 (RDR0AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-63. RDR0AD1 Field Descriptions Field Description 7–0 Reduced Drive Port AD1 Register 0 RDR0AD1[23:16] 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 22.3.2.71 Port AD1 Reduced Drive Register 1 (RDR1AD1) 7 6 5 4 3 2 1 0 R RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 W Reset 0 0 0 0 0 0 0 0 RDR1AD18 Figure 22-73. Port AD1 Reduced Drive Register 1 (RDR1AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[15:08] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-64. RDR1AD1 Field Descriptions Field 7–0 RDR1AD1[15:8] Description Reduced Drive Port AD1 Register 1 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 879 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.72 Port AD1 Pull Up Enable Register 0 (PER0AD1) 7 6 5 4 3 2 1 0 R PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-74. Port AD1 Pull Up Enable Register 0 (PER0AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull-up device is enabled. Table 22-65. PER0AD1 Field Descriptions Field 7–0 Pull Device Enable Port AD1 Register 0 PER0AD1[23:16] 0 Pull-up device is disabled. 1 Pull-up device is enabled. Description 22.3.2.73 Port AD1 Pull Up Enable Register 1 (PER1AD1) 7 6 5 4 3 2 1 0 R PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 W Reset 0 0 0 0 0 0 0 0 PER1AD19 PER1AD18 Figure 22-75. Port AD1 Pull Up Enable Register 1 (PER1AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[15:08] pin if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull-up device is enabled. Table 22-66. PER1AD1 Field Descriptions Field 7–0 PER1AD1[15:8] Pull Device Enable Port AD1 Register 1 0 Pull-up device is disabled. 1 Pull-up device is enabled. Description MC9S12XDP512 Data Sheet, Rev. 2.17 880 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4 Functional Description Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output from the external bus interface module or a peripheral module or an input to the external bus interface module or a peripheral module. A set of configuration registers is common to all ports with exceptions in the expanded bus interface and ATD ports (Table 22-67). All registers can be written at any time; however a specific configuration might not become active. Example: Selecting a pull-up device This device does not become active while the port is used as a push-pull output. Table 22-67. Register Availability per Port1 Port A B C D E K T S M P H J AD0 AD1 1 Data yes yes yes yes yes yes yes yes yes yes yes yes yes yes Data Direction yes yes yes yes yes yes yes yes yes yes yes yes yes yes Input — — — — — — yes yes yes yes yes yes — — Reduced Drive yes Pull Enable yes Polarity Select — — — — — — Wired-OR Mode — — — — — — — yes yes — — — — — Interrupt Enable — — — — — — — — — yes yes yes — — Interrupt Flag — — — — — — — — — yes yes yes — — yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes — yes yes yes yes yes — — Each cell represents one register with individual configuration bits 22.4.1 22.4.1.1 Registers Data Register This register holds the value driven out to the pin if the pin is used as a general purpose I/O. Writing to this register has only an effect on the pin if the pin is used as general purpose output. When reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to “0”. If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This is independent of any other configuration (Figure 22-76). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 881 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.1.2 Input Register This is a read-only register and always returns the buffered state of the pin (Figure 22-76). 22.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 22-76). PTI 0 1 PT 0 1 PIN DDR data out 0 1 Module output enable module enable Figure 22-76. Illustration of I/O Pin Functionality 22.4.1.4 Reduced Drive Register If the pin is used as an output this register allows the configuration of the drive strength. 22.4.1.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-OR output. 22.4.1.6 Polarity Select Register This register selects either a pull-up or pull-down device if enabled. It becomes active only if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-OR output. If the pin is used as an interrupt input this register selects the active interrupt edge. 22.4.1.7 Wired-OR Mode Register If the pin is used as an output this register turns off the active high drive. This allows wired-OR type connections of outputs. MC9S12XDP512 Data Sheet, Rev. 2.17 882 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.1.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 22.4.1.9 Interrupt Flag Register If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 22.4.1.10 Module Routing Register This register supports the re-routing of the CAN0, CAN4, SPI0, SPI1, and SPI2 pins to alternative ports. This allows a software re-configuration of the pinouts of the different package options with respect to above peripherals. NOTE The purpose of the module routing register is to provide maximum flexibility for derivatives with a lower number of MSCAN and SPI modules. Table 22-68. Module Implementations on Derivatives Number of Modules 5 4 3 2 1 MSCAN Modules CAN0 yes yes yes yes yes CAN1 yes yes yes — — CAN2 yes yes — — — CAN3 yes — — — — CAN4 yes yes yes yes — SPI0 — — yes yes yes SPI Modules SPI1 — — yes yes — SPI2 — — yes — — 22.4.2 22.4.2.1 Ports BKGD Pin The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the BKGD pin is used as MODC input. 22.4.2.2 Port A and B Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port A and port B are associated with the external address bus outputs ADDR15–ADDR8 and ADDR7–ADDR0, respectively. PB0 is the ADDR0 or UDS output. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 883 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.3 Port C and D Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port C and port D are associated with the external data bus inputs/outputs DATA15–DATA8 and DATA7–DATA0, respectively. These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI section). NOTE Port C and D are neither available in 112-pin nor in 80-pin packages. 22.4.2.4 Port E Port E is associated with the external bus control outputs R/W, LSTRB, LDS and RE, the free-running clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and interrupt inputs IRQ and XIRQ. Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions. Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output running at the core clock rate. The clock output is always enabled in emulation modes. Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled in emulation modes. Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (Section 22.3.2.14, “IRQ Control Register (IRQCR)”) and clearing the I-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up. Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to S12X_EBI section). 22.4.2.5 Port K Port K pins PK[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port K pins PK[6:0] are associated with the external address bus outputs ADDR22–ADDR16 and PK7 is associated to the EWAIT input. Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section). NOTE Port K is not available in 80-pin packages. PK[6] is not available in 112-pin packages. MC9S12XDP512 Data Sheet, Rev. 2.17 884 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.6 Port T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer. 22.4.2.7 Port S This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for generalpurpose I/O, or with the SCI and SPI subsystems. The SPI0 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. NOTE PS[7:4] are not available in 80-pin packages. 22.4.2.8 Port M This port is associated with the SCI3, CAN4–0 and SPI0. Port M pins PM[7:0] can be used for either general purpose I/O, or with the CAN, SCI and SPI subsystems. The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. NOTE PM[7:6] are not available in 80-pin packages. 22.4.2.9 Port P This port is associated with the PWM, SPI1 and SPI2. Port P pins PP[7:0] can be used for either general purpose I/O, or with the PWM and SPI subsystems. The pins are shared between the PWM channels and the SPI1 and SPI2 modules. If the PWM is enabled the pins become PWM output channels with the exception of pin 7 which can be PWM input or output. If SPI1 or SPI2 are enabled and PWM is disabled, the respective pin configuration is determined by status bits in the SPI modules. The SPI1 and SPI2 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion (Section 22.4.3, “Pin Interrupts”). NOTE PP[6] is not available in 80-pin packages. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 885 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.10 Port H This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1 and SPI2 modules. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. Port H offers 8 I/O pins with edge triggered interrupt capability (Section 22.4.3, “Pin Interrupts”). NOTE Port H is not available in 80-pin packages. 22.4.2.11 Port J This port is associated with the chip selects CS0, CS1, CS2 and CS3 as well as with CAN4, CAN0, IIC1, IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or with the CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC open-drain output pins. The CAN4 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. Port J pins can be used with the routed CAN0 modules. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. Port J offers 7 I/O pins with edge triggered interrupt capability (Section 22.4.3, “Pin Interrupts”). NOTE PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not available in 80-pin packages. 22.4.2.12 Port AD0 This port is associated with the ATD0. Port AD0 pins PAD07–PAD00 can be used for either general purpose I/O, or with the ATD0 subsystem. 22.4.2.13 Port AD1 This port is associated with the ATD1. Port AD1 pins PAD23–PAD08 can be used for either general purpose I/O, or with the ATD1 subsystem. NOTE PAD[23:16] are not available in 112-pin packages. PAD[23:08] are not available in 80-pin packages. MC9S12XDP512 Data Sheet, Rev. 2.17 886 Freescale Semiconductor Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.3 Pin Interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or WAIT mode. A digital filter on each pin prevents pulses (Figure 22-78) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 22-77 and Table 22-69). Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set uncertain tpign tpval Figure 22-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0) Table 22-69. Pulse Detection Criteria Mode Pulse STOP Ignored Uncertain Valid 1 Unit Bus clocks Bus clocks Bus clocks STOP1 tpulse ≤ tpign tpign < tpulse < tpval tpulse ≥ tpval tpulse ≤ 3 3 < tpulse < 4 tpulse ≥ 4 These values include the spread of the oscillator frequency over temperature, voltage and process. tpulse Figure 22-78. Pulse Illustration MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 887 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is generated by an RC-oscillator in the port integration module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin individually: Sample count 0.15 MHz ? no yes END yes EDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 25-17. Determination Procedure for PRDIV8 and EDIV Bits MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1053 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 25.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the EEPROM module not permitted between the steps. However, EEPROM register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to one address in the EEPROM memory. 2. Write a valid command to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the EADDR registers and the data will be stored in the EDATA registers. If the CBEIF flag in the ESTAT register is clear when the first EEPROM array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the EEPROM command controller indicating that the command was successfully launched. For all command write sequences except sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the ESTAT register. The CCIF flag will set upon completion of all active and buffered commands. 25.4.2 EEPROM Commands Table 25-9 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 25-9. EEPROM Command Description ECMDB 0x05 0x20 0x40 Command Erase Verify Program Sector Erase Function on EEPROM Memory Verify all memory bytes in the EEPROM block are erased. If the EEPROM block is erased, the BLANK flag in the ESTAT register will set upon command completion. Program a word (two bytes) in the EEPROM block. Erase all four memory bytes in a sector of the EEPROM block. MC9S12XDP512 Data Sheet, Rev. 2.17 1054 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Table 25-9. EEPROM Command Description ECMDB 0x41 Command Mass Erase Sector Erase Abort Sector Modify Function on EEPROM Memory Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The EEPROM sector should not be considered erased if the ACCERR flag is set upon command completion. Erase all four memory bytes in a sector of the EEPROM block and reprogram the addressed word. 0x47 0x60 CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1055 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 25-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the ESTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of words in the EEPROM memory plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the ESTAT register will be set if all addresses in the EEPROM memory are verified to be erased. If any address in the EEPROM memory is not erased, the erase verify operation will terminate and the BLANK flag in the ESTAT register will remain clear. MC9S12XDP512 Data Sheet, Rev. 2.17 1056 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: ECMD register Erase Verify Command 0x05 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes no Erase Verify Status BLANK Set? yes no EXIT EEPROM Memory Erased EXIT EEPROM Memory Not Erased Figure 25-18. Example Erase Verify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1057 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 25-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the ESTAT register will set after the program operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1058 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and program Data Write: ECMD register Program Command 0x20 Write: ESTAT register Clear CBEIF 0x80 yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register Bit Polling for Buffer Empty Check CBEIF Set? yes no Sequential Programming Decision Next Word? yes no Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 25-19. Example Program Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1059 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 25-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command. The EEPROM address written determines the sector to be erased while global address bits [1:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be erased is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the ESTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1060 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: EEPROM Sector Address and Dummy Data Write: ECMD register Sector Erase Command 0x40 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 25-20. Example Sector Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1061 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 25-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase command. If the EEPROM memory to be erased contains any protected area, the PVIOL flag in the ESTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1062 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: ECMD register Mass Erase Command 0x41 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 25-21. Example Mass Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1063 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 25-22. The sector erase abort command write sequence is as follows: 1. Write to any EEPROM memory address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the EEPROM sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase or sector modify operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. If the sector erase abort command is launched after the sector modify operation has completed the sector erase step, the program step will be allowed to complete. The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four EECLK periods (see Section 25.4.1.1, “Writing the ECLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the ESTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the ESTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. MC9S12XDP512 Data Sheet, Rev. 2.17 1064 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Execute Sector Erase/Modify Command Flow Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Abort Needed? yes no Sector Erase Completed EXIT 1. Write: Dummy EEPROM Address and Dummy Data Write: ECMD register Sector Erase Abort Cmd 0x47 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 2. 3. Bit Polling for Command Completion Check CCIF Set? yes no Access Error Check ACCERR Set? no yes Write: ESTAT register Clear ACCERR 0x10 Sector Erase or Modify Completed EXIT Sector Erase or Modify Aborted EXIT Figure 25-22. Example Sector Erase Abort Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1065 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 25-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command. The EEPROM address written determines the sector to be erased and word to be reprogrammed while byte address bit 0 is ignored. 2. Write the sector modify command, 0x60, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be modified is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector modify command will not launch. Once the sector modify command has successfully launched, the CCIF flag in the ESTAT register will set after the sector modify operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1066 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: EEPROM Word Address and program Data Write: ECMD register Sector Modify Command 0x60 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 25-23. Example Sector Modify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1067 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.3 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address. 5. Writing a second command to the ECMD register in the same command write sequence. 6. Writing an invalid command to the ECMD register. 7. Writing to an EEPROM address after writing to the ECMD register. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD register. 9. Writing a 0 to the CBEIF flag in the ESTAT register to abort a command write sequence. The ACCERR flag will not be set if any EEPROM register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation (see Section 25.4.2.5, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a command operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 25.5.2, “Stop Mode”). If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the ESTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 25.3.2.6, “EEPROM Status Register (ESTAT)”). The PVIOL flag will be set after the command is written to the ECMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in the command write sequence was in a protected area of the EEPROM memory. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the EEPROM memory. 3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is enabled. 4. Writing the sector modify command if the address written in the command write sequence was in a protected area of the EEPROM memory. If the PVIOL flag is set in the ESTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 25.3.2.6, “EEPROM Status Register (ESTAT)”). MC9S12XDP512 Data Sheet, Rev. 2.17 1068 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.5 25.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 25.8, “Interrupts”). 25.5.2 Stop Mode If a command is active (CCIF = 0) when the MCU enters the stop mode, the operation will be aborted and, if the operation is program, sector erase, mass erase, or sector modify, the EEPROM array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the EEPROM memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 25.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program, sector erase, mass erase, or sector modify operations. 25.5.3 Background Debug Mode In background debug mode (BDM), the EPROT register is writable. If the MCU is unsecured, then all EEPROM commands listed in Table 25-9 can be executed. If the MCU is secured and is in special single chip mode, the only command available to execute is mass erase. 25.6 EEPROM Module Security The EEPROM module does not provide any security information to the MCU. After each reset, the security state of the MCU is a function of information provided by the Flash module (see the specific FTX Block Guide). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1069 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory. After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state. 25.7 25.7.1 Resets EEPROM Reset Sequence On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the EPROT register from the EEPROM memory according to Table 25-1. 25.7.2 Reset While EEPROM Command Active If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted. The state of a word being programmed or the sector / block being erased is not guaranteed. 25.8 Interrupts The EEPROM module can generate an interrupt when all EEPROM command operations have completed, when the EEPROM address, data, and command buffers are empty. Table 25-10. EEPROM Interrupt Sources Interrupt Source EEPROM address, data, and command buffers empty All EEPROM commands completed Interrupt Flag CBEIF (ESTAT register) CCIF (ESTAT register) Local Enable CBEIE (ECNFG register) CCIE (ECNFG register) Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. MC9S12XDP512 Data Sheet, Rev. 2.17 1070 Freescale Semiconductor Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.8.1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 25-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 25-24. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 25.3.2.4, “EEPROM Configuration Register (ECNFG)” and Section 25.3.2.6, “EEPROM Status Register (ESTAT)” . MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1071 Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) MC9S12XDP512 Data Sheet, Rev. 2.17 1072 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.1 Introduction This document describes the EETX4K module which includes a 4 Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The EEPROM memory is ideal for data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The EEPROM module supports both block erase (all memory bytes) and sector erase (4 memory bytes). An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the EEPROM memory is generated internally. It is not possible to read from the EEPROM block while it is being erased or programmed. CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed. 26.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the EEPROM memory. 26.1.2 • • • • • • • • Features 4 Kbytes of EEPROM memory divided into 1024 sectors of 4 bytes Automated program and erase algorithm Interrupts on EEPROM command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase Single power supply for all EEPROM operations including program and erase 26.1.3 Modes of Operation Program, erase and erase verify operations (please refer to Section 26.4.1, “EEPROM Command Operations” for details). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1073 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.1.4 Block Diagram A block diagram of the EEPROM module is shown in Figure 26-1. EETX4K EEPROM Interface Command Pipeline Command Interrupt Request EEPROM cmd2 addr2 data2 cmd1 addr1 data1 2K * 16 Bits sector 0 sector 1 Registers Protection sector 1023 Oscillator Clock Clock Divider EECLK Figure 26-1. EETX4K Block Diagram 26.2 External Signal Description The EEPROM module contains no signals that connect off-chip. 26.3 Memory Map and Register Definition This section describes the memory map and registers for the EEPROM module. 26.3.1 Module Memory Map The EEPROM memory map is shown in Figure 26-2. The HCS12X architecture places the EEPROM memory addresses between global addresses 0x13_F000 and 0x13_FFFF. The EPROT register, described in Section 26.3.2.5, “EEPROM Protection Register (EPROT)”, can be set to protect the upper region in the EEPROM memory from accidental program or erase. The EEPROM addresses covered by this protectable MC9S12XDP512 Data Sheet, Rev. 2.17 1074 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) region are shown in the EEPROM memory map. The default protection setting is stored in the EEPROM configuration field as described in Table 26-1. Table 26-1. EEPROM Configuration Field Global Address 0x13_FFFC 0x13_FFFD 0x13_FFFE – 0x13_FFFF Size (bytes) 1 1 2 Description Reserved EEPROM Protection byte Refer to Section 26.3.2.5, “EEPROM Protection Register (EPROT)” Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1075 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) MODULE BASE+ 0x0000 EEPROM Registers 12 bytes MODULE BASE + 0x000B EEPROM START = 0x13_F000 EEPROM Memory 3584 bytes (up to 4032 bytes) 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 0x13_FF40 0x13_FF80 0x13_FFC0 EEPROM END = 0x13_FFFF EEPROM Configuration Field 4 bytes (0x13_FFFC – 0x13_FFFF) EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, 512 bytes Figure 26-2. EEPROM Memory Map MC9S12XDP512 Data Sheet, Rev. 2.17 1076 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Table 26-2 while their accessibility is detailed in Section 26.3.2, “Register Descriptions”. Table 26-2. EEPROM Register Map Module Base + 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 1 Register Name EEPROM Clock Divider Register (ECLKDIV) RESERVED1 RESERVED2 1 1 Normal Mode Access R/W R R R/W R/W R/W R/W R R R R R 1 EEPROM Configuration Register (ECNFG) EEPROM Protection Register (EPROT) EEPROM Status Register (ESTAT) EEPROM Command Register (ECMD) RESERVED3 1 EEPROM High Address Register (EADDRHI)1 EEPROM Low Address Register (EADDRLO) EEPROM High Data Register (EDATAHI) 1 1 EEPROM Low Data Register (EDATALO) Intended for factory test purposes only. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1077 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.2 Register Name ECLKDIV Register Descriptions Bit 7 R W EDIVLD 6 PRDIV8 0 5 EDIV5 0 4 EDIV4 0 3 EDIV3 0 2 EDIV2 0 1 EDIV1 0 Bit 0 EDIV0 0 RESERVED1 R W 0 RESERVED2 R W 0 0 0 0 0 0 0 0 ECNFG R W CBEIE CCIE RNV6 0 0 0 0 0 0 EPROT R W EPOPEN RNV5 RNV4 EPDIS 0 EPS2 BLANK EPS1 0 EPS0 0 ESTAT R W CBEIF 0 CCIF PVIOL ACCERR ECMD R W CMDB 0 0 0 0 0 0 0 RESERVED3 R W 0 EADDRHI R W 0 0 0 0 0 EABHI EADDRLO R W EABLO EDATAHI R W EDHI EDATALO R W = Unimplemented or Reserved EDLO Figure 26-3. EETX4K Register Summary 26.3.2.1 EEPROM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed events in program and erase algorithms. MC9S12XDP512 Data Sheet, Rev. 2.17 1078 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 7 6 5 4 3 2 1 0 R W Reset EDIVLD PRDIV8 0 0 EDIV5 0 EDIV4 0 EDIV3 0 EDIV2 0 EDIV1 0 EDIV0 0 = Unimplemented or Reserved Figure 26-4. EEPROM Clock Divider Register (ECLKDIV) All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 26-3. ECLKDIV Field Descriptions Field 7 EDIVLD 6 PRDIV8 5–0 EDIV[5:0] Description Clock Divider Loaded 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8 0 The oscillator clock is directly fed into the ECLKDIV divider. 1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider. Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to Section 26.4.1.1, “Writing the ECLKDIV Register” for more information. 26.3.2.2 RESERVED1 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-5. RESERVED1 All bits read 0 and are not writable. 26.3.2.3 RESERVED2 This register is reserved for factory testing and is not accessible. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1079 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-6. RESERVED2 All bits read 0 and are not writable. 26.3.2.4 EEPROM Configuration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 CCIE 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-7. EEPROM Configuration Register (ECNFG) CBEIE and CCIE bits are readable and writable while all remaining bits read 0 and are not writable. Table 26-4. ECNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the EEPROM module. 0 Command Buffer Empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the EEPROM module. 0 Command Complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”) is set. 6 CCIE MC9S12XDP512 Data Sheet, Rev. 2.17 1080 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.2.5 EEPROM Protection Register (EPROT) The EPROT register defines which EEPROM sectors are protected against program or erase operations. 7 6 5 4 3 2 1 0 R EPOPEN W Reset F RNV6 RNV5 RNV4 EPDIS EPS2 F EPS1 F EPS0 F F F F F = Unimplemented or Reserved Figure 26-8. EEPROM Protection Register (EPROT) During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address offset 0x0FFD (see Table 26-1).All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is irrelevant. To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is fully disabled by setting the EPOPEN and EPDIS bits. Table 26-5. EPROT Field Descriptions Field 7 EPOPEN 6–4 RNV[6:4] 3 EPDIS Description Opens the EEPROM for Program or Erase 0 The entire EEPROM memory is protected from program and erase. 1 The EEPROM sectors not protected are enabled for program or erase. Reserved Nonvolatile Bits — The RNV[6:4] bits should remain in the erased state “1” for future enhancements. EEPROM Protection Address Range Disable — The EPDIS bit determines whether there is a protected area in a specific region of the EEPROM memory ending with address offset 0x0FFF. 0 Protection enabled. 1 Protection disabled. EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown inTable 26-6. The EPS bits can only be written to while the EPDIS bit is set. 2–0 EPS[2:0] MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1081 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-6. EEPROM Protection Address Range EPS[2:0] 000 001 010 011 100 101 110 111 Address Offset Range 0x0FC0 – 0x0FFF 0x0F80 – 0x0FFF 0x0F40 – 0x0FFF 0x0F00 – 0x0FFF 0x0EC0 – 0x0FFF 0x0E80 – 0x0FFF 0x0E40 – 0x0FFF 0x0E00 – 0x0FFF Protected Size 64 bytes 128 bytes 192 bytes 256 bytes 320 bytes 384 bytes 448 bytes 512 bytes 26.3.2.6 EEPROM Status Register (ESTAT) The ESTAT register defines the operational status of the module. 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-9. EEPROM Status Register (ESTAT — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL 0 0 0 0 0 = Unimplemented or Reserved Figure 26-10. EEPROM Status Register (ESTAT — Special Mode) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. MC9S12XDP512 Data Sheet, Rev. 2.17 1082 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-7. ESTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request (see Figure 26-24). 0 Buffers are full. 1 Buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request (see Figure 26-24). 0 Command in progress. 1 All commands are completed. Protection Violation Flag — The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the EEPROM memory during a command write sequence. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No failure. 1 A protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the EEPROM memory caused by either a violation of the command write sequence (see Section 26.4.1.2, “Command Write Sequence”), issuing an illegal EEPROM command (see Table 26-9), launching the sector erase abort command terminating a sector erase operation early (see Section 26.4.2.5, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the EEPROM module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 EEPROM block verified as not erased. 1 EEPROM block verified as erased. Flag Indicating a Failed EEPROM Operation — The FAIL flag will set if the erase verify operation fails (EEPROM block verified as not erased). The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL flag has no effect on FAIL. 0 EEPROM operation completed without error. 1 EEPROM operation failed. 6 CCIF 5 PVIOL 4 ACCERR 2 BLANK 1 FAIL MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1083 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.2.7 EEPROM Command Register (ECMD) The ECMD register is the EEPROM command register. 7 6 5 4 3 2 1 0 R W Reset 0 CMDB 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-11. EEPROM Command Register (ECMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 26-8. ECMD Field Descriptions Field 6–0 CMDB[6:0] Description EEPROM Command Bits — Valid EEPROM commands are shown in Table 26-9. Writing any command other than those listed in Table 26-9 sets the ACCERR flag in the ESTAT register. Table 26-9. Valid EEPROM Command List CMDB[6:0] 0x05 0x20 0x40 0x41 0x47 0x60 Command Erase Verify Word Program Sector Erase Mass Erase Sector Erase Abort Sector Modify 26.3.2.8 RESERVED3 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-12. RESERVED3 All bits read 0 and are not writable. EEPROM Address Registers (EADDR) MC9S12XDP512 Data Sheet, Rev. 2.17 1084 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) The EADDRHI and EADDRLO registers are the EEPROM address registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 EABHI 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 26-13. EEPROM Address High Register (EADDRHI) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 EABLO 0 0 0 0 = Unimplemented or Reserved Figure 26-14. EEPROM Address Low Register (EADDRLO) All EABHI and EABLO bits read 0 and are not writable in normal modes. All EABHI and EABLO bits are readable and writable in special modes. The MCU address bit AB0 is not stored in the EADDR registers since the EEPROM block is not byte addressable. 26.3.2.9 EEPROM Data Registers (EDATA) The EDATAHI and EDATALO registers are the EEPROM data registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 EDHI 0 0 0 0 = Unimplemented or Reserved Figure 26-15. EEPROM Data High Register (EDATAHI) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 EDLO 0 0 0 0 = Unimplemented or Reserved Figure 26-16. EEPROM Data Low Register (EDATALO) All EDHI and EDLO bits read 0 and are not writable in normal modes. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1085 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) All EDHI and EDLO bits are readable and writable in special modes. 26.4 26.4.1 Functional Description EEPROM Command Operations Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. Buffer empty as well as command completion are signalled by flags in the EEPROM status register with interrupts generated, if enabled. The next sections describe: 1. How to write the ECLKDIV register 2. Command write sequences to program, erase, erase verify, sector erase abort, and sector modify operations on the EEPROM memory 3. Valid EEPROM commands 4. Effects resulting from illegal EEPROM command write sequences or aborting EEPROM operations 26.4.1.1 Writing the ECLKDIV Register Prior to issuing any EEPROM command after a reset, the user is required to write the ECLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the ECLKDIV determination must take this information into account. If we define: • ECLK as the clock of the EEPROM timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g., INT(4.323)=4) then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 26-17. For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting EECLK frequency is then 190 kHz. As a result, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% If the oscillator clock frequency is 16 MHz and the bus clock frequency is 40 MHz, ECLKDIV bits EDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting EECLK frequency is MC9S12XDP512 Data Sheet, Rev. 2.17 1086 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the EEPROM memory with EECLK < 150 kHz should be avoided. Setting ECLKDIV to a value such that EECLK < 150 kHz can destroy the EEPROM memory due to overstress. Setting ECLKDIV to a value such that (1/EECLK+Tbus) < 5 µs can result in incomplete programming or erasure of the EEPROM memory cells. If the ECLKDIV register is written, the EDIVLD bit is set automatically. If the EDIVLD bit is 0, the ECLKDIV register has not been written since the last reset. If the ECLKDIV register has not been written to, the EEPROM command loaded during a command write sequence will not execute and the ACCERR flag in the ESTAT register will set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1087 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Tbus < 1µs? yes PRDIV8 = 0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock >12.8 MHz? yes no PRDIV8 = 1 PRDCLK = oscillator_clock/8 PRDCLK = oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1 TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0]) 1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.15 MHz ? no yes END yes EDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 26-17. Determination Procedure for PRDIV8 and EDIV Bits MC9S12XDP512 Data Sheet, Rev. 2.17 1088 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the EEPROM module not permitted between the steps. However, EEPROM register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to one address in the EEPROM memory. 2. Write a valid command to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the EADDR registers and the data will be stored in the EDATA registers. If the CBEIF flag in the ESTAT register is clear when the first EEPROM array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the EEPROM command controller indicating that the command was successfully launched. For all command write sequences except sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the ESTAT register. The CCIF flag will set upon completion of all active and buffered commands. 26.4.2 EEPROM Commands Table 26-10 summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block. Table 26-10. EEPROM Command Description ECMDB 0x05 0x20 0x40 Command Erase Verify Program Sector Erase Function on EEPROM Memory Verify all memory bytes in the EEPROM block are erased. If the EEPROM block is erased, the BLANK flag in the ESTAT register will set upon command completion. Program a word (two bytes) in the EEPROM block. Erase all four memory bytes in a sector of the EEPROM block. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1089 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-10. EEPROM Command Description ECMDB 0x41 Command Mass Erase Sector Erase Abort Sector Modify Function on EEPROM Memory Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The EEPROM sector should not be considered erased if the ACCERR flag is set upon command completion. Erase all four memory bytes in a sector of the EEPROM block and reprogram the addressed word. 0x47 0x60 CAUTION An EEPROM word (2 bytes) must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed. MC9S12XDP512 Data Sheet, Rev. 2.17 1090 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 26-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the ESTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of words in the EEPROM memory plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the ESTAT register will be set if all addresses in the EEPROM memory are verified to be erased. If any address in the EEPROM memory is not erased, the erase verify operation will terminate and the BLANK flag in the ESTAT register will remain clear. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1091 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: ECMD register Erase Verify Command 0x05 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes no Erase Verify Status BLANK Set? yes no EXIT EEPROM Memory Erased EXIT EEPROM Memory Not Erased Figure 26-18. Example Erase Verify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1092 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 26-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the ESTAT register will set after the program operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1093 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and program Data Write: ECMD register Program Command 0x20 Write: ESTAT register Clear CBEIF 0x80 yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Read: ESTAT register Bit Polling for Buffer Empty Check CBEIF Set? yes no Sequential Programming Decision Next Word? yes no Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 26-19. Example Program Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1094 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 26-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command. The EEPROM address written determines the sector to be erased while global address bits [1:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be erased is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the ESTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1095 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: EEPROM Sector Address and Dummy Data Write: ECMD register Sector Erase Command 0x40 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 26-20. Example Sector Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1096 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 26-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the mass erase command. If the EEPROM memory to be erased contains any protected area, the PVIOL flag in the ESTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the ESTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1097 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no Write: EEPROM Address and Dummy Data yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: ECMD register Mass Erase Command 0x41 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 26-21. Example Mass Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1098 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 26-22. The sector erase abort command write sequence is as follows: 1. Write to any EEPROM memory address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase or sector modify operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the EEPROM sector may not be fully erased and a new sector erase or sector modify command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase or sector modify operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. If the sector erase abort command is launched after the sector modify operation has completed the sector erase step, the program step will be allowed to complete. The maximum number of cycles required to abort a sector erase or sector modify operation is equal to four EECLK periods (see Section 26.4.1.1, “Writing the ECLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the ESTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the ESTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1099 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Execute Sector Erase/Modify Command Flow Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Abort Needed? yes no Sector Erase Completed EXIT 1. Write: Dummy EEPROM Address and Dummy Data Write: ECMD register Sector Erase Abort Cmd 0x47 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 2. 3. Bit Polling for Command Completion Check CCIF Set? yes no Access Error Check ACCERR Set? no yes Write: ESTAT register Clear ACCERR 0x10 Sector Erase or Modify Completed EXIT Sector Erase or Modify Aborted EXIT Figure 26-22. Example Sector Erase Abort Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1100 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 26-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command. The EEPROM address written determines the sector to be erased and word to be reprogrammed while byte address bit 0 is ignored. 2. Write the sector modify command, 0x60, to the ECMD register. 3. Clear the CBEIF flag in the ESTAT register by writing a 1 to CBEIF to launch the sector erase command. If an EEPROM sector to be modified is in a protected area of the EEPROM memory, the PVIOL flag in the ESTAT register will set and the sector modify command will not launch. Once the sector modify command has successfully launched, the CCIF flag in the ESTAT register will set after the sector modify operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1101 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check NOTE: ECLKDIV needs to be set once after each reset. EDIVLD Set? yes no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. 2. 3. ACCERR/ PVIOL Set? no yes Write: ESTAT register Clear ACCERR/PVIOL 0x30 Write: EEPROM Word Address and program Data Write: ECMD register Sector Modify Command 0x60 Write: ESTAT register Clear CBEIF 0x80 Read: ESTAT register NOTE: command write sequence aborted by writing 0x00 to ESTAT register. NOTE: command write sequence aborted by writing 0x00 to ESTAT register. Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 26-23. Example Sector Modify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1102 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.3 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4. Writing to any EEPROM register other than ECMD after writing to an EEPROM address. 5. Writing a second command to the ECMD register in the same command write sequence. 6. Writing an invalid command to the ECMD register. 7. Writing to an EEPROM address after writing to the ECMD register. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the ECMD register. 9. Writing a 0 to the CBEIF flag in the ESTAT register to abort a command write sequence. The ACCERR flag will not be set if any EEPROM register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase or sector modify operation is active which results in the early termination of the sector erase or sector modify operation (see Section 26.4.2.5, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a command operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 26.5.2, “Stop Mode”). If the EEPROM memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the ESTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”). The PVIOL flag will be set after the command is written to the ECMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in the command write sequence was in a protected area of the EEPROM memory. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the EEPROM memory. 3. Writing the mass erase command to the EEPROM memory while any EEPROM protection is enabled. 4. Writing the sector modify command if the address written in the command write sequence was in a protected area of the EEPROM memory. If the PVIOL flag is set in the ESTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 26.3.2.6, “EEPROM Status Register (ESTAT)”). MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1103 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.5 26.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 26.8, “Interrupts”). 26.5.2 Stop Mode If a command is active (CCIF = 0) when the MCU enters the stop mode, the operation will be aborted and, if the operation is program, sector erase, mass erase, or sector modify, the EEPROM array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the EEPROM memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 26.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program, sector erase, mass erase, or sector modify operations. 26.5.3 Background Debug Mode In background debug mode (BDM), the EPROT register is writable. If the MCU is unsecured, then all EEPROM commands listed in Table 26-10 can be executed. If the MCU is secured and is in special single chip mode, the only command available to execute is mass erase. 26.6 EEPROM Module Security The EEPROM module does not provide any security information to the MCU. After each reset, the security state of the MCU is a function of information provided by the Flash module (see the specific FTX Block Guide). MC9S12XDP512 Data Sheet, Rev. 2.17 1104 Freescale Semiconductor Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory. After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state. 26.7 26.7.1 Resets EEPROM Reset Sequence On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the EPROT register from the EEPROM memory according to Table 26-1. 26.7.2 Reset While EEPROM Command Active If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted. The state of a word being programmed or the sector / block being erased is not guaranteed. 26.8 Interrupts The EEPROM module can generate an interrupt when all EEPROM command operations have completed, when the EEPROM address, data, and command buffers are empty. Table 26-11. EEPROM Interrupt Sources Interrupt Source EEPROM address, data, and command buffers empty All EEPROM commands completed Interrupt Flag CBEIF (ESTAT register) CCIF (ESTAT register) Local Enable CBEIE (ECNFG register) CCIE (ECNFG register) Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1105 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.8.1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 26-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 26-24. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 26.3.2.4, “EEPROM Configuration Register (ECNFG)” and Section 26.3.2.6, “EEPROM Status Register (ESTAT)” . MC9S12XDP512 Data Sheet, Rev. 2.17 1106 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.1 Introduction This document describes the FTX512K4 module that includes a 512K Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The Flash memory is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both block erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 27.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Multiple-Input Signature Register (MISR) — A Multiple-Input Signature Register is an output response analyzer implemented using a linear feedback shift-register (LFSR). A 16-bit MISR is used to compress data and generate a signature that is particular to the data read from a Flash block. 27.1.2 • • • • • • • • Features 512 Kbytes of Flash memory comprised of four 128 Kbyte blocks with each block divided into 128 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion, command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase Single power supply for all Flash operations including program and erase MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1107 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 27.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 27.4.1, “Flash Command Operations” for details). 27.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 27-1. MC9S12XDP512 Data Sheet, Rev. 2.17 1108 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) FTX512K4 Flash Block 0 64K * 16 Bits sector 0 sector 1 Flash Interface Command Interrupt Request Command Pipeline cmd2 addr2 data2_0 data2_1 data2_2 data2_3 cmd1 addr1 data1_0 data1_1 data1_2 data1_3 sector 127 Flash Block 1 64K * 16 Bits sector 0 sector 1 sector 127 Registers Protection Flash Block 2 64K * 16 Bits sector 0 sector 1 Security sector 127 Oscillator Clock Clock Divider FCLK Flash Block 3 64K * 16 Bits sector 0 sector 1 sector 127 Figure 27-1. FTX512K4 Block Diagram 27.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1109 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 27.3.1 Module Memory Map The Flash memory map is shown in Figure 27-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 27.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address 0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. The lower address region can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 27-1. Table 27-1. Flash Configuration Field Global Address 0x7F_FF00 – 0x7F_FF07 0x7F_FF08 – 0x7F_FF0C 0x7F_FF0D 0x7F_FF0E 0x7F_FF0F Size (Bytes) 8 5 1 1 1 Description Backdoor Comparison Key Refer to Section 27.6.1, “Unsecuring the MCU using Backdoor Key Access” Reserved Flash Protection byte Refer to Section 27.3.2.5, “Flash Protection Register (FPROT)” Flash Nonvolatile byte Refer to Section 27.3.2.8, “Flash Control Register (FCTL)” Flash Security byte Refer to Section 27.3.2.2, “Flash Security Register (FSEC)” MC9S12XDP512 Data Sheet, Rev. 2.17 1110 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH START = 0x78_0000 Flash Protected/Unprotected Region 480 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 FLASH END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 27-2. Flash Memory Map MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1111 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) The Flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Table 27-2 while their accessibility is detailed in Section 27.3.2, “Register Descriptions”. Table 27-2. Flash Register Map Module Base + 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Register Name Flash Clock Divider Register (FCLKDIV) Flash Security Register (FSEC) Flash Test Mode Register (FTSTMOD) Flash Configuration Register (FCNFG) Flash Protection Register (FPROT) Flash Status Register (FSTAT) Flash Command Register (FCMD) Flash Control Register (FCTL) Flash High Address Register (FADDRHI) 1 1 Normal Mode Access R/W R R/W R/W R/W R/W R/W R R R R R R R R R Flash Low Address Register (FADDRLO) Flash High Data Register (FDATAHI) Flash Low Data Register (FDATALO) RESERVED11 RESERVED21 RESERVED31 RESERVED41 1 Intended for factory test purposes only. MC9S12XDP512 Data Sheet, Rev. 2.17 1112 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.2 Register Name FCLKDIV Register Descriptions Bit 7 R W FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 6 5 4 3 2 1 Bit 0 FSEC R W KEYEN RNV5 RNV4 RNV3 RNV2 SEC FTSTMOD R W 0 MRDS 0 0 0 0 0 FCNFG R CBEIE W CCIE KEYACC 0 0 0 0 0 FPROT R FPOPEN W RNV6 FPHDIS FPHS FPLDIS FPLS FSTAT R CBEIF W CCIF PVIOL ACCERR 0 BLANK 0 0 FCMD R W 0 CMDB FCTL R W NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 FADDRHI R W FADDRHI FADDRLO R W FADDRLO FDATAHI R W FDATAHI FDATALO R W FDATALO RESERVED1 R W 0 0 0 0 0 0 0 0 Figure 27-3. FTX512K4 Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1113 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Register Name RESERVED2 R W RESERVED3 R W RESERVED4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27-3. FTX512K4 Register Summary (continued) 27.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 27-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. Table 27-3. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5-0 FDIV[5:0] Description Clock Divider Loaded. 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8. 0 The oscillator clock is directly fed into the clock divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 27.4.1.1, “Writing the FCLKDIV Register” for more information. 27.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12XDP512 Data Sheet, Rev. 2.17 1114 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 3 2 1 0 R W Reset F KEYEN RNV5 RNV4 RNV3 RNV2 SEC F F F F F F F = Unimplemented or Reserved Figure 27-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 27-5. Table 27-4. FSEC Field Descriptions Field Description 7-6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 27-5. 5-2 RNV[5:2] 1-0 SEC[1:0] Reserved Nonvolatile Bits — The RNV[5:2] bits should remain in the erased state for future enhancements. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 27-6. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 27-5. Flash KEYEN States KEYEN[1:0] 00 01 1 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 10 11 1 Preferred KEYEN state to disable Backdoor Key Access. Table 27-6. Flash Security States SEC[1:0] 00 011 10 11 Status of Security SECURED SECURED UNSECURED SECURED 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 27.6, “Flash Module Security”. 27.3.2.3 Flash Test Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1115 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 3 2 1 0 R W Reset 0 MRDS 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-6. Flash Test Mode Register (FTSTMOD —Normal Mode) 7 6 5 4 3 2 1 0 R W Reset 0 MRDS 0 0 0 WRALL 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-7. Flash Test Mode Register (FTSTMOD — Special Mode) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0. Table 27-7. FTSTMOD Field Descriptions Field 6–5 MRDS[1:0] 4 WRALL Description Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash array as shown in Table 27-8. Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register address will be written simultaneously during a register write. 0 Write only to the FDATA register bank selected using BKSEL. 1 Write to all FDATA register banks. Table 27-8. FTSTMOD Margin Read Settings MRDS[1:0] 00 01 10 11 Margin Read Setting Normal Program Margin1 Erase Margin2 Normal 1 Flash array reads will be sensitive to program margin. 2 Flash array reads will be sensitive to erase margin. 27.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor writes. MC9S12XDP512 Data Sheet, Rev. 2.17 1116 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-8. Flash Configuration Register (FCNFG — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 BKSEL 0 0 0 0 0 = Unimplemented or Reserved Figure 27-9. Flash Configuration Register (FCNFG — Special Mode) CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. KEYACC is only writable if KEYEN (see Section 27.3.2.2, “Flash Security Register (FSEC)” is set to the enabled state. BKSEL is readable and writable in special mode to simplify mass erase and erase verify operations. When writing to the FCNFG register in special mode, all unimplemented/ reserved bits must be written to 0. Table 27-9. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 27.3.2.6, “Flash Status Register (FSTAT)”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 27.3.2.6, “Flash Status Register (FSTAT)”) is set. Enable Security Key Writing 0 Flash writes are interpreted as the start of a command write sequence. 1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data. 6 CCIE 5 KEYACC 1–0 Block Select — The BKSEL[1:0] bits indicates which register bank is active according to Table 27-10. BKSEL[1:0] Table 27-10. Flash Register Bank Selects BKSEL[1:0] 00 01 Selected Block Flash Block 0 Flash Block 1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1117 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-10. Flash Register Bank Selects BKSEL[1:0] 10 11 Selected Block Flash Block 2 Flash Block 3 27.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. 7 6 5 4 3 2 1 0 R FPOPEN W Reset F RNV6 FPHDIS F F F FPHS F FPLDIS F F FPLS F = Unimplemented or Reserved Figure 27-10. Flash Protection Register (FPROT) All bits in the FPROT register are readable and writable with restrictions (see Section 27.3.2.5.1, “Flash Protection Restrictions”) except for RNV[6] which is only readable. During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as described in Table 27-1 must be reprogrammed. Trying to alter data in any protected area in the Flash memory will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of the Flash sectors contained in the Flash block are protected. Table 27-11. FPROT Field Descriptions Field 7 FPOPEN Description Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown in Table 27-12. 0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM emulation. 1 The FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected area as shown inTable 27-13. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. 6 RNV6 5 FPHDIS 4–3 FPHS[1:0] MC9S12XDP512 Data Sheet, Rev. 2.17 1118 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-11. FPROT Field Descriptions (continued) Field 2 FPLDIS Description Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected area as shown in Table 27-14. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 1–0 FPLS[1:0] Table 27-12. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 0 FPHDIS 1 1 0 0 1 1 0 0 FPLDIS 1 0 1 0 1 0 1 0 No Protection Protected Low Range Protected High Range Protected High and Low Ranges Full Flash memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges Function1 1 For range sizes, refer to Table 27-13 and Table 27-14. Table 27-13. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Global Address Range 0x7F_F800–0x7F_FFFF 0x7F_F000–0x7F_FFFF 0x7F_E000–0x7F_FFFF 0x7F_C000–0x7F_FFFF Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 27-14. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Global Address Range 0x7F_8000–0x7F_83FF 0x7F_8000–0x7F_87FF 0x7F_8000–0x7F_8FFF 0x7F_8000–0x7F_9FFF Protected Size 1 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes All possible Flash protection scenarios are shown in Figure 27-11. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1119 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) FPHDIS=1 FPLDIS=1 0x78_0000 FPHDIS=1 FPLDIS=0 6 FPHDIS=0 FPLDIS=1 5 FPHDIS=0 FPLDIS=0 4 7 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 0x78_0000 2 Scenario 1 0 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region not defined by FPLS, FPHS Protected region with size defined by FPLS Protected region with size defined by FPHS Figure 27-11. Flash Protection Scenarios MC9S12XDP512 Data Sheet, Rev. 2.17 1120 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 27-15 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions. Table 27-15. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 6 7 X X X X X To Protection Scenario1 0 X 1 X X X 2 X 3 X X X X X X X X X X X X X X X X X 4 5 6 7 1 Allowed transitions marked with X. 27.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the operational status of the module. 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-12. Flash Status Register (FSTAT — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL 0 0 0 0 0 = Unimplemented or Reserved Figure 27-13. Flash Status Register (FSTAT — Special Mode) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1121 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 27-16. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space, but before CBEIF is cleared, will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is cleared by writing a 1 to CBEIF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 27-32). 0 Command buffers are full. 1 Command buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 27-32). 0 Command in progress. 1 All commands are completed. Protection Violation Flag —The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash memory during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. The PVIOL flag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 27.4.1.2, “Command Write Sequence”), issuing an illegal Flash command (see Table 27-18), launching the sector erase abort command terminating a sector erase operation early (see Section 27.4.2.6, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR flag has no effect on ACCERR. The ACCERR flag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (selected Flash block verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. 1 Flash operation failed. 6 CCIF 5 PVIOL 4 ACCERR 2 BLANK 1 FAIL MC9S12XDP512 Data Sheet, Rev. 2.17 1122 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 6 5 4 3 2 1 0 R W Reset 0 CMDB 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-14. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 27-17. FCMD Field Descriptions Field 6-0 CMDB[6:0] Description Flash Command — Valid Flash commands are shown in Table 27-18. Writing any command other than those listed in Table 27-18 sets the ACCERR flag in the FSTAT register. Table 27-18. Valid Flash Command List CMDB[6:0] 0x05 0x06 0x20 0x40 0x41 0x47 NVM Command Erase Verify Data Compress Word Program Sector Erase Mass Erase Sector Erase Abort 27.3.2.8 Flash Control Register (FCTL) The FCTL register is the Flash control register. 7 6 5 4 3 2 1 0 R W Reset NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 F F F F F F F F = Unimplemented or Reserved Figure 27-15. Flash Control Register (FCTL) All bits in the FCTL register are readable but are not writable. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1123 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 27-15. Table 27-19. FCTL Field Descriptions Field 7-0 NV[7:0] Description Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 27.3.2.9 Flash Address Registers (FADDR) The FADDRHI and FADDRLO registers are the Flash address registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRHI 0 0 0 0 = Unimplemented or Reserved Figure 27-16. Flash Address High Register (FADDRHI) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRLO 0 0 0 0 = Unimplemented or Reserved Figure 27-17. Flash Address Low Register (FADDRLO) All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written. 27.3.2.10 Flash Data Registers (FDATA) The FDATAHI and FDATALO registers are the Flash data registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATAHI 0 0 0 0 = Unimplemented or Reserved Figure 27-18. Flash Data High Register (FDATAHI) MC9S12XDP512 Data Sheet, Rev. 2.17 1124 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATALO 0 0 0 0 = Unimplemented or Reserved Figure 27-19. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 27.3.2.11 RESERVED1 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-20. RESERVED1 All bits read 0 and are not writable. 27.3.2.12 RESERVED2 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-21. RESERVED2 All bits read 0 and are not writable. 27.3.2.13 RESERVED3 This register is reserved for factory testing and is not accessible. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1125 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-22. RESERVED3 All bits read 0 and are not writable. 27.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 27-23. RESERVED4 All bits read 0 and are not writable. 27.4 27.4.1 Functional Description Flash Command Operations Write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command register, as well as the associated address and data registers, operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row in the Flash block as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register with corresponding interrupts generated, if enabled. The next sections describe: 1. How to write the FCLKDIV register 2. Command write sequences to program, erase, erase verify, erase abort, and data compress operations on the Flash memory 3. Valid Flash commands 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations MC9S12XDP512 Data Sheet, Rev. 2.17 1126 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 27-24. For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz, FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then 182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that (1/FCLK+Tbus) < 5µs can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1127 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 27-24. Determination Procedure for PRDIV8 and FDIV Bits MC9S12XDP512 Data Sheet, Rev. 2.17 1128 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 27.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to as long as the location is at the same relative address in each available Flash block. Multiple addresses must be written in Flash block order starting with the lower Flash block. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. If the CBEIF flag in the FSTAT register is clear when the first Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. 27.4.2 Flash Commands Table 27-20 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 27-20. Flash Command Description FCMDB 0x05 NVM Command Erase Verify Function on Flash Memory Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1129 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-20. Flash Command Description FCMDB 0x06 0x20 0x40 0x41 NVM Command Data Compress Program Sector Erase Mass Erase Sector Erase Abort Function on Flash Memory Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. Program a word (two bytes) in the Flash block. Erase all memory bytes in a sector of the Flash block. Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector should not be considered erased if the ACCERR flag is set upon command completion. 0x47 CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12XDP512 Data Sheet, Rev. 2.17 1130 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 27-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase verified by writing to the same relative address in each Flash block. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the selected Flash blocks are verified to be erased. If any address in a selected Flash block is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify operation. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1131 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Block Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K 2. 3. no Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Verify Status BLANK Set? yes no EXIT Flash Block Erased EXIT Flash Block Not Erased Figure 27-25. Example Erase Verify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1132 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 27-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command. The address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress. If the data value written is 0x0000, 64K addresses or 128 Kbytes will be compressed. Multiple Flash blocks can be simultaneously compressed by writing to the same relative address in each Flash block. If more than one Flash block is written to in this step, the first data written will determine the number of consecutive words to compress in each selected Flash block. 2. Write the data compress command, 0x06, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the data compress command. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus the number of Flash blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Once the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected Flash memory. If the last address of a Flash block is reached during the data compress operation, data compression will continue with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the data compress operation. NOTE Since the FDATA registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence should only be started after reading the signature stored in the FDATA registers. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector should be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1133 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address to start compression and number of word addresses to compress NOTE: address used to select Flash block; data ignored. Simultaneous Multiple Flash Block Decision Next Flash Block? yes Decrement Global Address by 128K 2. 3. no Write: FCMD register Data Compress Command 0x06 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Read: FDATA registers Data Compress Signature no Signature Valid? yes EXIT Erase and Reprogram Flash Sector(s) Compressed Figure 27-26. Example Data Compress Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1134 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 27-1 where MISR is the content of the internal signature register associated with each Flash block and DATA is the data to be compressed as shown in Figure 27-27. DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[15] + DQ M0 > + DQ M1 > + + DQ M2 > + + DQ M3 > + DQ M4 > + + DQ M5 > ... + DQ M15 > + = Exclusive-OR MISR[15:0] = Q[15:0] Figure 27-27. 16-Bit MISR Diagram During the data compress operation, the following steps are executed: 1. MISR for each Flash block is reset to 0xFFFF. 2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block which results in the MISR containing 0x0001. 3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses incrementing. 4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses decrementing. 5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected for compression, the MISR for Flash block 0 contains 0xFFFF. 6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash block 1 is compressed into the MISR for Flash block 0. 7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash block 2 is compressed into the MISR for Flash block 0. 8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash block 3 is compressed into the MISR for Flash block 0. 9. The contents of the MISR for Flash block 0 are written to the FDATA registers. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1135 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 27-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. Multiple Flash blocks can be simultaneously programmed by writing to the same relative address in each Flash block. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. MC9S12XDP512 Data Sheet, Rev. 2.17 1136 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no Write: Flash Address and program Data Next Flash Block? no Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 yes Decrement Global Address by 128K 2. 3. Read: FSTAT register Bit Polling for Buffer Empty Check CBEIF Set? yes no Sequential Programming Decision Next Word? yes no Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 27-28. Example Program Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1137 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 27-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. Multiple Flash sectors can be simultaneously erased by writing to the same relative address in each Flash block. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1138 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Sector Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K 2. 3. no Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 27-29. Example Sector Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1139 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 27-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously mass erased by writing to the same relative address in each Flash block. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1140 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Block Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K 2. 3. no Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 27-30. Example Mass Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1141 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 27-31. The sector erase abort command write sequence is as follows: 1. Write to any Flash block address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, a Flash sector being erased when the abort command was launched will be fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (see Section 27.4.1.1, “Writing the FCLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. If sectors in multiple Flash blocks are being simultaneously erased, the sector erase abort operation will be applied to all active Flash blocks without writing to each Flash block in the sector erase abort command write sequence. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. MC9S12XDP512 Data Sheet, Rev. 2.17 1142 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Abort Needed? yes no Sector Erase Completed EXIT 1. Write: Dummy Flash Address and Dummy Data Write: FCMD register Sector Erase Abort Cmd 0x47 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? yes no Access Error Check ACCERR Set? no yes Write: FSTAT register Clear ACCERR 0x10 Sector Erase Completed EXIT Sector Erase Aborted EXIT Figure 27-31. Example Sector Erase Abort Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1143 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4. Starting a command write sequence while a sector erase abort operation is active. 5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address as the first one written in the same command write sequence. 6. Writing to any Flash register other than FCMD after writing to a Flash address. 7. Writing a second command to the FCMD register in the same command write sequence. 8. Writing an invalid command to the FCMD register. 9. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 10. Writing to a Flash address after writing to the FCMD register. 11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 12. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 27.4.2.6, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 27.5.2, “Stop Mode”). If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 27.3.2.6, “Flash Status Register (FSTAT)”). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if an address written in the command write sequence was in a protected area of the Flash memory 2. Writing the sector erase command if an address written in the command write sequence was in a protected area of the Flash memory 3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the block MC9S12XDP512 Data Sheet, Rev. 2.17 1144 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 27.3.2.6, “Flash Status Register (FSTAT)”). 27.5 27.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 27.8, “Interrupts”). 27.5.2 Stop Mode If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 27.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations. 27.5.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 27-20 can be executed. If the MCU is secured and is in special single chip mode, only mass erase can be executed. 27.6 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 27.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize to a secure operating mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1145 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.2, “Flash Security Register (FSEC)”) and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.2, “Flash Security Register (FSEC)”), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the Flash Configuration Register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0x7F_FF00. 3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEYACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00–0x7F_FF07 in the Flash Configuration Field. The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are MC9S12XDP512 Data Sheet, Rev. 2.17 1146 Freescale Semiconductor Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). 27.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method: • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU. 27.7 27.7.1 Resets Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 27-1: • FPROT — Flash Protection Register (see Section 27.3.2.5). • FCTL - Flash Control Register (see Section 27.3.2.8). • FSEC — Flash Security Register (see Section 27.3.2.2). 27.7.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 27.8 Interrupts The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1147 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-21. Flash Interrupt Sources Interrupt Source Flash Address, Data and Command Buffers empty All Flash commands completed Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE (FCNFG register) CCIE (FCNFG register) Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 27.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is shown in Figure 27-32. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. CBEIF CBEIE Flash Command Interrupt Request CCIF CCIE Figure 27-32. Flash Interrupt Implementation For a detailed description of the register bits, refer to Section 27.3.2.4, “Flash Configuration Register (FCNFG)” and Section 27.3.2.6, “Flash Status Register (FSTAT)” . MC9S12XDP512 Data Sheet, Rev. 2.17 1148 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.1 Introduction This document describes the FTX256K2 module that includes a 256 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The Flash memory is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both block erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 28.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Multiple-Input Signature Register (MISR) — A Multiple-Input Signature Register is an output response analyzer implemented using a linear feedback shift-register (LFSR). A 16-bit MISR is used to compress data and generate a signature that is particular to the data read from a Flash block. 28.1.2 • • • • • • • • Features 256 Kbytes of Flash memory comprised of two 128 Kbyte blocks with each block divided into 128 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion, command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase Single power supply for all Flash operations including program and erase MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1149 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 28.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 28.4.1, “Flash Command Operations” for details). 28.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 28-1. FTX256K2 Command Interrupt Request Flash Interface Command Pipeline cmd2 addr2 data2_0 data2_1 cmd1 addr1 data1_0 data1_1 Flash Block 0 64K * 16 Bits sector 0 sector 1 sector 127 Registers Protection Flash Block 1 64K * 16 Bits sector 0 sector 1 sector 127 Security Oscillator Clock Clock Divider FCLK Figure 28-1. FTX256K2 Block Diagram 28.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XDP512 Data Sheet, Rev. 2.17 1150 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 28.3.1 Module Memory Map The Flash memory map is shown in Figure 28-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 28.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address 0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. The lower address region can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 28-1. Table 28-1. Flash Configuration Field Global Address 0x7F_FF00 – 0x7F_FF07 0x7F_FF08 – 0x7F_FF0C 0x7F_FF0D 0x7F_FF0E 0x7F_FF0F Size (Bytes) 8 5 1 1 1 Description Backdoor Comparison Key Refer to Section 28.6.1, “Unsecuring the MCU using Backdoor Key Access” Reserved Flash Protection byte Refer to Section 28.3.2.5, “Flash Protection Register (FPROT)” Flash Nonvolatile byte Refer to Section 28.3.2.8, “Flash Control Register (FCTL)” Flash Security byte Refer to Section 28.3.2.2, “Flash Security Register (FSEC)” MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1151 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH START = 0x78_0000 Flash Registers 16 bytes Flash Protected/Unprotected Region 128 Kbytes 0x79_FFFF Unimplemented Flash Region 256 Kbytes 0x7E_0000 Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 FLASH END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 28-2. Flash Memory Map MC9S12XDP512 Data Sheet, Rev. 2.17 1152 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 28-3. Detailed descriptions of each register bit are provided. Register Name FCLKDIV R W FSEC R W FTSTMOD R W FCNFG R CBEIE W FPROT R FPOPEN W FSTAT R CBEIF W FCMD R W FCTL R W FADDRHI R W FADDRLO R W FDATAHI R W FDATALO R W FDATALO FDATAHI FADDRLO FADDRHI 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 CMDB CCIF PVIOL ACCERR 0 BLANK 0 0 RNV6 FPHDIS FPHS FPLDIS FPLS CCIE KEYACC 0 0 0 0 0 0 MRDS 0 0 0 0 0 KEYEN RNV5 RNV4 RNV3 RNV2 SEC Bit 7 FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 6 5 4 3 2 1 Bit 0 Figure 28-3. FTX256K2 Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1153 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Register Name RESERVED1 R W RESERVED2 R W RESERVED3 R W RESERVED4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28-3. FTX256K2 Register Summary (continued) 28.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 28-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. Table 28-2. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5:0 FDIV[5:0] Description Clock Divider Loaded. 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8. 0 The oscillator clock is directly fed into the clock divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 28.4.1.1, “Writing the FCLKDIV Register” for more information. 28.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12XDP512 Data Sheet, Rev. 2.17 1154 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R W Reset F KEYEN RNV5 RNV4 RNV3 RNV2 SEC F F F F F F F = Unimplemented or Reserved Figure 28-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 28-5. Table 28-3. FSEC Field Descriptions Field Description 7:6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 28-4. 5:2 RNV[5:2] 1:0 SEC[1:0] Reserved Nonvolatile Bits — The RNV[5:2] bits should remain in the erased state for future enhancements. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 28-5. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 28-4. Flash KEYEN States KEYEN[1:0] 00 011 10 11 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 1 Preferred KEYEN state to disable Backdoor Key Access. Table 28-5. Flash Security States SEC[1:0] 00 01 1 Status of Security SECURED SECURED UNSECURED SECURED 10 11 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 28.6, “Flash Module Security”. 28.3.2.3 Flash Test Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1155 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R W Reset 0 MRDS 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-6. Flash Test Mode Register (FTSTMOD —Normal Mode) 7 6 5 4 3 2 1 0 R W Reset 0 MRDS 0 0 0 WRALL 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-7. Flash Test Mode Register (FTSTMOD — Special Mode) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0. Table 28-6. FTSTMOD Field Descriptions Field 6:5 MRDS[1:0] 4 WRALL Description Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash array as shown in Table 28-7. Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register address will be written simultaneously during a register write. 0 Write only to the FDATA register bank selected using BKSEL. 1 Write to all FDATA register banks. Table 28-7. FTSTMOD Margin Read Settings MRDS[1:0] 00 01 10 11 Margin Read Setting Normal Program Margin1 Erase Margin2 Normal 1 Flash array reads will be sensitive to program margin. 2 Flash array reads will be sensitive to erase margin. 28.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor writes. MC9S12XDP512 Data Sheet, Rev. 2.17 1156 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-8. Flash Configuration Register (FCNFG — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 BKSEL 0 0 0 0 0 = Unimplemented or Reserved Figure 28-9. Flash Configuration Register (FCNFG — Special Mode) CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. KEYACC is only writable if KEYEN (see Section 28.3.2.2, “Flash Security Register (FSEC)” is set to the enabled state. BKSEL is readable and writable in special mode to simplify mass erase and erase verify operations. When writing to the FCNFG register in special mode, all unimplemented/ reserved bits must be written to 0. Table 28-8. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 28.3.2.6, “Flash Status Register (FSTAT)”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 28.3.2.6, “Flash Status Register (FSTAT)”) is set. Enable Security Key Writing 0 Flash writes are interpreted as the start of a command write sequence. 1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data. Block Select — The BKSEL bit indicates which register bank is active. 0 Select register bank associated with Flash block 0. 1 Select register bank associated with Flash block 1. 6 CCIE 5 KEYACC 0 BKSEL 28.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1157 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R FPOPEN W Reset F RNV6 FPHDIS F F F FPHS F FPLDIS F F FPLS F = Unimplemented or Reserved Figure 28-10. Flash Protection Register (FPROT) All bits in the FPROT register are readable and writable with restrictions (see Section 28.3.2.5.1, “Flash Protection Restrictions”) except for RNV[6] which is only readable. During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as described in Table 28-1 must be reprogrammed. Trying to alter data in any protected area in the Flash memory will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of the Flash sectors contained in the Flash block are protected. Table 28-9. FPROT Field Descriptions Field 7 FPOPEN Description Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown in Table 28-10. 0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM emulation. 1 The FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected area as shown inTable 28-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected area as shown in Table 28-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 RNV6 5 FPHDIS 4:3 FPHS[1:0] 2 FPLDIS 1:0 FPLS[1:0] MC9S12XDP512 Data Sheet, Rev. 2.17 1158 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-10. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 0 FPHDIS 1 1 0 0 1 1 0 0 FPLDIS 1 0 1 0 1 0 1 0 No Protection Protected Low Range Protected High Range Protected High and Low Ranges Full Flash memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges Function1 1 For range sizes, refer to Table 28-11 and Table 28-12. Table 28-11. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Global Address Range 0x7F_F800–0x7F_FFFF 0x7F_F000–0x7F_FFFF 0x7F_E000–0x7F_FFFF 0x7F_C000–0x7F_FFFF Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Table 28-12. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Global Address Range 0x7F_8000–0x7F_83FF 0x7F_8000–0x7F_87FF 0x7F_8000–0x7F_8FFF 0x7F_8000–0x7F_9FFF Protected Size 1 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes All possible Flash protection scenarios are shown in Figure 28-11. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1159 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) FPHDIS=1 FPLDIS=1 0x78_0000 FPHDIS=1 FPLDIS=0 6 FPHDIS=0 FPLDIS=1 5 FPHDIS=0 FPLDIS=0 4 7 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 0x78_0000 2 Scenario 1 0 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region not defined by FPLS, FPHS Protected region with size defined by FPLS Protected region with size defined by FPHS Figure 28-11. Flash Protection Scenarios MC9S12XDP512 Data Sheet, Rev. 2.17 1160 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 28-13 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions. Table 28-13. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 6 7 X X X X X To Protection Scenario1 0 X 1 X X X 2 X 3 X X X X X X X X X X X X X X X X X 4 5 6 7 1 Allowed transitions marked with X. 28.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the operational status of the module. 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-12. Flash Status Register (FSTAT — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL 0 0 0 0 0 = Unimplemented or Reserved Figure 28-13. Flash Status Register (FSTAT — Special Mode) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1161 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 28-14. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space, but before CBEIF is cleared, will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is cleared by writing a 1 to CBEIF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 28-32). 0 Command buffers are full. 1 Command buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 28-32). 0 Command in progress. 1 All commands are completed. Protection Violation Flag —The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash memory during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. The PVIOL flag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 28.4.1.2, “Command Write Sequence”), issuing an illegal Flash command (see Table 28-16), launching the sector erase abort command terminating a sector erase operation early (see Section 28.4.2.6, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR flag has no effect on ACCERR. The ACCERR flag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (selected Flash block verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. 1 Flash operation failed. 6 CCIF 5 PVIOL 4 ACCERR 2 BLANK 1 FAIL MC9S12XDP512 Data Sheet, Rev. 2.17 1162 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 6 5 4 3 2 1 0 R W Reset 0 CMDB 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-14. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 28-15. FCMD Field Descriptions Field 6:0 CMDB[6:0] Description Flash Command — Valid Flash commands are shown in Table 28-16. Writing any command other than those listed in Table 28-16 sets the ACCERR flag in the FSTAT register. Table 28-16. Valid Flash Command List CMDB[6:0] 0x05 0x06 0x20 0x40 0x41 0x47 NVM Command Erase Verify Data Compress Word Program Sector Erase Mass Erase Sector Erase Abort 28.3.2.8 Flash Control Register (FCTL) The FCTL register is the Flash control register. 7 6 5 4 3 2 1 0 R W Reset 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 F F F F F F F = Unimplemented or Reserved Figure 28-15. Flash Control Register (FCTL) All bits in the FCTL register are readable but are not writable. The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 28-15. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1163 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-17. FCTL Field Descriptions Field 6:0 NV[6:0] Description Nonvolatile Bits — The NV[6:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 28.3.2.9 Flash Address Registers (FADDR) The FADDRHI and FADDRLO registers are the Flash address registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRHI 0 0 0 0 = Unimplemented or Reserved Figure 28-16. Flash Address High Register (FADDRHI) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRLO 0 0 0 0 = Unimplemented or Reserved Figure 28-17. Flash Address Low Register (FADDRLO) All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written. 28.3.2.10 Flash Data Registers (FDATA) The FDATAHI and FDATALO registers are the Flash data registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATAHI 0 0 0 0 = Unimplemented or Reserved Figure 28-18. Flash Data High Register (FDATAHI) MC9S12XDP512 Data Sheet, Rev. 2.17 1164 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATALO 0 0 0 0 = Unimplemented or Reserved Figure 28-19. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 28.3.2.11 RESERVED1 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-20. RESERVED1 All bits read 0 and are not writable. 28.3.2.12 RESERVED2 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-21. RESERVED2 All bits read 0 and are not writable. 28.3.2.13 RESERVED3 This register is reserved for factory testing and is not accessible. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1165 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-22. RESERVED3 All bits read 0 and are not writable. 28.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 28-23. RESERVED4 All bits read 0 and are not writable. 28.4 28.4.1 Functional Description Flash Command Operations Write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command register, as well as the associated address and data registers, operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row in the Flash block as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register with corresponding interrupts generated, if enabled. The next sections describe: 1. How to write the FCLKDIV register 2. Command write sequences to program, erase, erase verify, erase abort, and data compress operations on the Flash memory 3. Valid Flash commands 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations MC9S12XDP512 Data Sheet, Rev. 2.17 1166 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 28-24. For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz, FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then 182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that (1/FCLK+Tbus) < 5µs can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1167 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 28-24. Determination Procedure for PRDIV8 and FDIV Bits MC9S12XDP512 Data Sheet, Rev. 2.17 1168 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 28.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to as long as the location is at the same relative address in each available Flash block. Multiple addresses must be written in Flash block order starting with the lower Flash block. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. If the CBEIF flag in the FSTAT register is clear when the first Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. 28.4.2 Flash Commands Table 28-18 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 28-18. Flash Command Description FCMDB 0x05 NVM Command Erase Verify Function on Flash Memory Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1169 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-18. Flash Command Description FCMDB 0x06 0x20 0x40 0x41 NVM Command Data Compress Program Sector Erase Mass Erase Sector Erase Abort Function on Flash Memory Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. Program a word (two bytes) in the Flash block. Erase all memory bytes in a sector of the Flash block. Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector should not be considered erased if the ACCERR flag is set upon command completion. 0x47 CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12XDP512 Data Sheet, Rev. 2.17 1170 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 28-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously erase verified by writing to the same relative address in each Flash block. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the selected Flash blocks are verified to be erased. If any address in a selected Flash block is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify operation. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1171 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Block Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K (skip unimplemented Flash) 2. 3. no Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Verify Status BLANK Set? yes no EXIT Flash Block Erased EXIT Flash Block Not Erased Figure 28-25. Example Erase Verify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1172 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 28-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command. The address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress. If the data value written is 0x0000, 64K addresses or 128 Kbytes will be compressed. Multiple Flash blocks can be simultaneously compressed by writing to the same relative address in each Flash block. If more than one Flash block is written to in this step, the first data written will determine the number of consecutive words to compress in each selected Flash block. 2. Write the data compress command, 0x06, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the data compress command. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus the number of Flash blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Once the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected Flash memory. If the last address of a Flash block is reached during the data compress operation, data compression will continue with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the data compress operation. NOTE Since the FDATA registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence should only be started after reading the signature stored in the FDATA registers. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector should be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1173 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address to start compression and number of word addresses to compress NOTE: address used to select Flash block; data ignored. Simultaneous Multiple Flash Block Decision Next Flash Block? yes Decrement Global Address by 128K (skip unimplemented Flash) 2. 3. no Write: FCMD register Data Compress Command 0x06 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Read: FDATA registers Data Compress Signature no Signature Valid? yes EXIT Erase and Reprogram Flash Sector(s) Compressed Figure 28-26. Example Data Compress Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1174 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 28-1 where MISR is the content of the internal signature register associated with each Flash block and DATA is the data to be compressed as shown in Figure 28-27. DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[15] + DQ M0 > + DQ M1 > + + DQ M2 > + + DQ M3 > + DQ M4 > + + DQ M5 > ... + DQ M15 > + = Exclusive-OR MISR[15:0] = Q[15:0] Figure 28-27. 16-Bit MISR Diagram During the data compress operation, the following steps are executed: 1. MISR for each Flash block is reset to 0xFFFF. 2. Initialized DATA equal to 0xFFFF is compressed into the MISR for each selected Flash block which results in the MISR containing 0x0001. 3. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses incrementing. 4. DATA equal to the selected Flash array data range is read and compressed into the MISR for each selected Flash block with addresses decrementing. 5. If Flash block 0 is selected for compression, DATA equal to the contents of the MISR for Flash block 0 is compressed into the MISR for Flash block 0. If data in Flash block 0 was not selected for compression, the MISR for Flash block 0 contains 0xFFFF. 6. If Flash block 1 is selected for compression, DATA equal to the contents of the MISR for Flash block 1 is compressed into the MISR for Flash block 0. 7. If Flash block 2 is selected for compression, DATA equal to the contents of the MISR for Flash block 2 is compressed into the MISR for Flash block 0. 8. If Flash block 3 is selected for compression, DATA equal to the contents of the MISR for Flash block 3 is compressed into the MISR for Flash block 0. 9. If Flash block 4 is selected for compression, DATA equal to the contents of the MISR for Flash block 4 is compressed into the MISR for Flash block 0. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1175 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 10. If Flash block 5 is selected for compression, DATA equal to the contents of the MISR for Flash block 5 is compressed into the MISR for Flash block 0. 11. If Flash block 6 is selected for compression, DATA equal to the contents of the MISR for Flash block 6 is compressed into the MISR for Flash block 0. 12. If Flash block 7 is selected for compression, DATA equal to the contents of the MISR for Flash block 7 is compressed into the MISR for Flash block 0. 13. The contents of the MISR for Flash block 0 are written to the FDATA registers. MC9S12XDP512 Data Sheet, Rev. 2.17 1176 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 28-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. Multiple Flash blocks can be simultaneously programmed by writing to the same relative address in each Flash block. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1177 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no Write: Flash Address and program Data Next Flash Block? no Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 yes Decrement Global Address by 128K (skip unimplemented Flash) 2. 3. Read: FSTAT register Bit Polling for Buffer Empty Check CBEIF Set? yes no Sequential Programming Decision Next Word? yes no Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 28-28. Example Program Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1178 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 28-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. Multiple Flash sectors can be simultaneously erased by writing to the same relative address in each Flash block. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1179 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Sector Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K (skip unimplemented Flash) 2. 3. no Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 28-29. Example Sector Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1180 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 28-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. Multiple Flash blocks can be simultaneously mass erased by writing to the same relative address in each Flash block. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1181 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check NOTE: FCLKDIV needs to be set once after each reset. FDIVLD Set? yes no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check 1. Simultaneous Multiple Flash Block Decision ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Block Address and Dummy Data Next Flash Block? yes Decrement Global Address by 128K (skip unimplemented Flash) 2. 3. no Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes EXIT no Figure 28-30. Example Mass Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1182 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 28-31. The sector erase abort command write sequence is as follows: 1. Write to any Flash block address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, a Flash sector being erased when the abort command was launched will be fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (see Section 28.4.1.1, “Writing the FCLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. If sectors in multiple Flash blocks are being simultaneously erased, the sector erase abort operation will be applied to all active Flash blocks without writing to each Flash block in the sector erase abort command write sequence. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1183 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Abort Needed? yes no Sector Erase Completed EXIT 1. Write: Dummy Flash Address and Dummy Data Write: FCMD register Sector Erase Abort Cmd 0x47 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? yes no Access Error Check ACCERR Set? no yes Write: FSTAT register Clear ACCERR 0x10 Sector Erase Completed EXIT Sector Erase Aborted EXIT Figure 28-31. Example Sector Erase Abort Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1184 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4. Starting a command write sequence while a sector erase abort operation is active. 5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address as the first one written in the same command write sequence. 6. Writing to any Flash register other than FCMD after writing to a Flash address. 7. Writing a second command to the FCMD register in the same command write sequence. 8. Writing an invalid command to the FCMD register. 9. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 10. Writing to a Flash address after writing to the FCMD register. 11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 12. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 28.4.2.6, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 28.5.2, “Stop Mode”). If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 28.3.2.6, “Flash Status Register (FSTAT)”). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if an address written in the command write sequence was in a protected area of the Flash memory 2. Writing the sector erase command if an address written in the command write sequence was in a protected area of the Flash memory 3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the block MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1185 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 28.3.2.6, “Flash Status Register (FSTAT)”). 28.5 28.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 28.8, “Interrupts”). 28.5.2 Stop Mode If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 28.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations. 28.5.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 28-18 can be executed. If the MCU is secured and is in special single chip mode, only mass erase can be executed. 28.6 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 28.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize to a secure operating mode. MC9S12XDP512 Data Sheet, Rev. 2.17 1186 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.2, “Flash Security Register (FSEC)”) and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.2, “Flash Security Register (FSEC)”), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the Flash Configuration Register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0x7F_FF00. 3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEYACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00–0x7F_FF07 in the Flash Configuration Field. The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1187 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). 28.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method: • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU. 28.7 28.7.1 Resets Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 28-1: • FPROT — Flash Protection Register (see Section 28.3.2.5). • FCTL - Flash Control Register (see Section 28.3.2.8). • FSEC — Flash Security Register (see Section 28.3.2.2). 28.7.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 28.8 Interrupts The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty. MC9S12XDP512 Data Sheet, Rev. 2.17 1188 Freescale Semiconductor Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-19. Flash Interrupt Sources Interrupt Source Flash Address, Data and Command Buffers empty All Flash commands completed Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE (FCNFG register) CCIE (FCNFG register) Global (CCR) Mask I Bit I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 28.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is shown in Figure 28-32. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. CBEIF CBEIE Flash Command Interrupt Request CCIF CCIE Figure 28-32. Flash Interrupt Implementation For a detailed description of the register bits, refer to Section 28.3.2.4, “Flash Configuration Register (FCNFG)” and Section 28.3.2.6, “Flash Status Register (FSTAT)” . MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1189 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) MC9S12XDP512 Data Sheet, Rev. 2.17 1190 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.1 Introduction This document describes the FTX128K1 module that includes a 128 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The Flash memory is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both block erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. 29.1.1 Glossary Command Write Sequence — A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Multiple-Input Signature Register (MISR) — A Multiple-Input Signature Register is an output response analyzer implemented using a linear feedback shift-register (LFSR). A 16-bit MISR is used to compress data and generate a signature that is particular to the data read from a Flash block. 29.1.2 • • • • • • • • Features 128 Kbytes of Flash memory comprised of one 128 Kbyte block divided into 128 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion, command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase Single power supply for all Flash operations including program and erase MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1191 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 29.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 29.4.1, “Flash Command Operations” for details). 29.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 29-1. FTX128K1 Flash Interface Command Pipeline Command Interrupt Request Flash Block cmd2 addr2 data2 cmd1 addr1 data1 64K * 16 Bits sector 0 sector 1 Registers Protection sector 127 Security Oscillator Clock Clock Divider FCLK Figure 29-1. FTX128K1 Block Diagram 29.2 External Signal Description The Flash module contains no signals that connect off-chip. MC9S12XDP512 Data Sheet, Rev. 2.17 1192 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 29.3.1 Module Memory Map The Flash memory map is shown in Figure 29-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x7E_0000 and 0x7F_FFFF. The FPROT register, described in Section 29.3.2.5, “Flash Protection Register (FPROT)”, can be set to protect regions in the Flash memory from accidental program or erase. Three separate memory regions, one growing upward from global address 0x7F_8000 in the Flash memory (called the lower region), one growing downward from global address 0x7F_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. The lower address region can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 29-1. Table 29-1. Flash Configuration Field Global Address 0x7F_FF00 – 0x7F_FF07 0x7F_FF08 – 0x7F_FF0C 0x7F_FF0D 0x7F_FF0E 0x7F_FF0F Size (Bytes) 8 5 1 1 1 Description Backdoor Comparison Key Refer to Section 29.6.1, “Unsecuring the MCU using Backdoor Key Access” Reserved Flash Protection byte Refer to Section 29.3.2.5, “Flash Protection Register (FPROT)” Flash Nonvolatile byte Refer to Section 29.3.2.8, “Flash Control Register (FCTL)” Flash Security byte Refer to Section 29.3.2.2, “Flash Security Register (FSEC)” MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1193 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) MODULE BASE + 0x0000 MODULE BASE + 0x000F FLASH START = 0x7E_0000 Flash Registers 16 bytes Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 FLASH END = 0x7F_FFFF Flash Configuration Field 16 bytes (0x7F_FF00 - 0x7F_FF0F) Figure 29-2. Flash Memory Map MC9S12XDP512 Data Sheet, Rev. 2.17 1194 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 29-3. Detailed descriptions of each register bit are provided. Register Name FCLKDIV R W FSEC R W FTSTMOD R W FCNFG R CBEIE W FPROT R FPOPEN W FSTAT R CBEIF W FCMD R W FCTL R W FADDRHI R W FADDRLO R W FDATAHI R W FDATALO R W FDATALO FDATAHI FADDRLO FADDRHI 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 CMDB CCIF PVIOL ACCERR 0 BLANK 0 0 RNV6 FPHDIS FPHS FPLDIS FPLS CCIE KEYACC 0 0 0 0 0 0 MRDS 0 0 0 0 0 KEYEN RNV5 RNV4 RNV3 RNV2 SEC Bit 7 FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 6 5 4 3 2 1 Bit 0 Figure 29-3. FTX128K1 Register Summary MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1195 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Register Name RESERVED1 R W RESERVED2 R W RESERVED3 R W RESERVED4 R W Bit 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-3. FTX128K1 Register Summary (continued) 29.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms. 7 6 5 4 3 2 1 0 R W Reset FDIVLD PRDIV8 0 0 FDIV5 0 FDIV4 0 FDIV3 0 FDIV2 0 FDIV1 0 FDIV0 0 = Unimplemented or Reserved Figure 29-4. Flash Clock Divider Register (FCLKDIV) All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable. Table 29-2. FCLKDIV Field Descriptions Field 7 FDIVLD 6 PRDIV8 5:0 FDIV[5:0] Description Clock Divider Loaded. 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8. 0 The oscillator clock is directly fed into the clock divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 29.4.1.1, “Writing the FCLKDIV Register” for more information. 29.3.2.2 Flash Security Register (FSEC) The FSEC register holds all bits associated with the security of the MCU and Flash module. MC9S12XDP512 Data Sheet, Rev. 2.17 1196 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 6 5 4 3 2 1 0 R W Reset F KEYEN RNV5 RNV4 RNV3 RNV2 SEC F F F F F F F = Unimplemented or Reserved Figure 29-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 29-5. Table 29-3. FSEC Field Descriptions Field Description 7:6 Backdoor Key Security Enable Bits — The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 29-4. 5:2 RNV[5:2] 1:0 SEC[1:0] Reserved Nonvolatile Bits — The RNV[5:2] bits should remain in the erased state for future enhancements. Flash Security Bits — The SEC[1:0] bits define the security state of the MCU as shown in Table 29-5. If the Flash module is unsecured using backdoor key access, the SEC[1:0] bits are forced to 1:0. Table 29-4. Flash KEYEN States KEYEN[1:0] 00 011 10 11 Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED 1 Preferred KEYEN state to disable Backdoor Key Access. Table 29-5. Flash Security States SEC[1:0] 00 01 1 Status of Security SECURED SECURED UNSECURED SECURED 10 11 1 Preferred SEC state to set MCU to secured state. The security function in the Flash module is described in Section 29.6, “Flash Module Security”. 29.3.2.3 Flash Test Mode Register (FTSTMOD) The FTSTMOD register is used to control Flash test features. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1197 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 6 5 4 3 2 1 0 R W Reset 0 MRDS 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-6. Flash Test Mode Register (FTSTMOD) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. Table 29-6. FTSTMOD Field Descriptions Field 6:5 MRDS[1:0] Description Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash array as shown in Table 29-7. Table 29-7. FTSTMOD Margin Read Settings MRDS[1:0] 00 01 10 11 Margin Read Setting Normal Program Margin1 Erase Margin2 Normal 1 Flash array reads will be sensitive to program margin. 2 Flash array reads will be sensitive to erase margin. 29.3.2.4 Flash Configuration Register (FCNFG) The FCNFG register enables the Flash interrupts and gates the security backdoor writes. 7 6 5 4 3 2 1 0 R CBEIE W Reset 0 0 0 CCIE KEYACC 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-7. Flash Configuration Register (FCNFG) CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. KEYACC is only writable if KEYEN (see Section 29.3.2.2, “Flash Security Register (FSEC)” is set to the enabled state. MC9S12XDP512 Data Sheet, Rev. 2.17 1198 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-8. FCNFG Field Descriptions Field 7 CBEIE Description Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 29.3.2.6, “Flash Status Register (FSTAT)”) is set. Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 29.3.2.6, “Flash Status Register (FSTAT)”) is set. Enable Security Key Writing 0 Flash writes are interpreted as the start of a command write sequence. 1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data. 6 CCIE 5 KEYACC 29.3.2.5 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. 7 6 5 4 3 2 1 0 R FPOPEN W Reset F RNV6 FPHDIS F F F FPHS F FPLDIS F F FPLS F = Unimplemented or Reserved Figure 29-8. Flash Protection Register (FPROT) All bits in the FPROT register are readable and writable with restrictions (see Section 29.3.2.5.1, “Flash Protection Restrictions”) except for RNV[6] which is only readable. During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as described in Table 29-1 must be reprogrammed. Trying to alter data in any protected area in the Flash memory will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of the Flash sectors contained in the Flash block are protected. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1199 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-9. FPROT Field Descriptions Field 7 FPOPEN Description Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown in Table 29-10. 0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM emulation. 1 The FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. Reserved Nonvolatile Bit — The RNV[6] bit should remain in the erased state for future enhancements. Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory ending with global address 0x7F_FFFF. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected area as shown inTable 29-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled. Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected area as shown in Table 29-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. 6 RNV6 5 FPHDIS 4:3 FPHS[1:0] 2 FPLDIS 1:0 FPLS[1:0] Table 29-10. Flash Protection Function FPOPEN 1 1 1 1 0 0 0 0 FPHDIS 1 1 0 0 1 1 0 0 FPLDIS 1 0 1 0 1 0 1 0 No Protection Protected Low Range Protected High Range Protected High and Low Ranges Full Flash memory Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges Function1 1 For range sizes, refer to Table 29-11 and Table 29-12. Table 29-11. Flash Protection Higher Address Range FPHS[1:0] 00 01 10 11 Global Address Range 0x7F_F800–0x7F_FFFF 0x7F_F000–0x7F_FFFF 0x7F_E000–0x7F_FFFF 0x7F_C000–0x7F_FFFF Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes MC9S12XDP512 Data Sheet, Rev. 2.17 1200 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-12. Flash Protection Lower Address Range FPLS[1:0] 00 01 10 11 Global Address Range 0x7F_8000–0x7F_83FF 0x7F_8000–0x7F_87FF 0x7F_8000–0x7F_8FFF 0x7F_8000–0x7F_9FFF Protected Size 1 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes All possible Flash protection scenarios are shown in Figure 29-9. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single chip mode while providing as much protection as possible if re-programming is not required. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1201 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) FPHDIS=1 FPLDIS=1 0x7E_0000 FPHDIS=1 FPLDIS=0 6 FPHDIS=0 FPLDIS=1 5 FPHDIS=0 FPLDIS=0 4 7 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 0x7E_0000 2 Scenario 1 0 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region not defined by FPLS, FPHS Protected region with size defined by FPLS Protected region with size defined by FPHS Figure 29-9. Flash Protection Scenarios MC9S12XDP512 Data Sheet, Rev. 2.17 1202 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 29-13 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions. Table 29-13. Flash Protection Scenario Transitions From Protection Scenario 0 1 2 3 4 5 6 7 X X X X X To Protection Scenario1 0 X 1 X X X 2 X 3 X X X X X X X X X X X X X X X X X 4 5 6 7 1 Allowed transitions marked with X. 29.3.2.6 Flash Status Register (FSTAT) The FSTAT register defines the operational status of the module. 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-10. Flash Status Register (FSTAT — Normal Mode) 7 6 5 4 3 2 1 0 R CBEIF W Reset 1 CCIF PVIOL 1 0 ACCERR 0 0 BLANK FAIL 0 0 0 0 0 = Unimplemented or Reserved Figure 29-11. Flash Status Register (FSTAT — Special Mode) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1203 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 29-14. FSTAT Field Descriptions Field 7 CBEIF Description Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space, but before CBEIF is cleared, will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is cleared by writing a 1 to CBEIF. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 29-30). 0 Command buffers are full. 1 Command buffers are ready to accept a new command. Command Complete Interrupt Flag — The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 29-30). 0 Command in progress. 1 All commands are completed. Protection Violation Flag —The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash memory during a command write sequence. Writing a 0 to the PVIOL flag has no effect on PVIOL. The PVIOL flag is cleared by writing a 1 to PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No protection violation detected. 1 Protection violation has occurred. Access Error Flag — The ACCERR flag indicates an illegal access has occurred to the Flash memory caused by either a violation of the command write sequence (see Section 29.4.1.2, “Command Write Sequence”), issuing an illegal Flash command (see Table 29-16), launching the sector erase abort command terminating a sector erase operation early (see Section 29.4.2.6, “Sector Erase Abort Command”) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). Writing a 0 to the ACCERR flag has no effect on ACCERR. The ACCERR flag is cleared by writing a 1 to ACCERR.While ACCERR is set, it is not possible to launch a command or start a command write sequence. If ACCERR is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Flag Indicating the Erase Verify Operation Status — When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. Flag Indicating a Failed Flash Operation — The FAIL flag will set if the erase verify operation fails (Flash block verified as not erased). Writing a 0 to the FAIL flag has no effect on FAIL. The FAIL flag is cleared by writing a 1 to FAIL. 0 Flash operation completed without error. 1 Flash operation failed. 6 CCIF 5 PVIOL 4 ACCERR 2 BLANK 1 FAIL MC9S12XDP512 Data Sheet, Rev. 2.17 1204 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 6 5 4 3 2 1 0 R W Reset 0 CMDB 1 1 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-12. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 29-15. FCMD Field Descriptions Field 6:0 CMDB[6:0] Description Flash Command — Valid Flash commands are shown in Table 29-16. Writing any command other than those listed in Table 29-16 sets the ACCERR flag in the FSTAT register. Table 29-16. Valid Flash Command List CMDB[6:0] 0x05 0x06 0x20 0x40 0x41 0x47 NVM Command Erase Verify Data Compress Word Program Sector Erase Mass Erase Sector Erase Abort 29.3.2.8 Flash Control Register (FCTL) The FCTL register is the Flash control register. 7 6 5 4 3 2 1 0 R W Reset 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0 0 F F F F F F F = Unimplemented or Reserved Figure 29-13. Flash Control Register (FCTL) All bits in the FCTL register are readable but are not writable. The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 29-13. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1205 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-17. FCTL Field Descriptions Field 6:0 NV[6:0] Description Nonvolatile Bits — The NV[6:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 29.3.2.9 Flash Address Registers (FADDR) The FADDRHI and FADDRLO registers are the Flash address registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRHI 0 0 0 0 = Unimplemented or Reserved Figure 29-14. Flash Address High Register (FADDRHI) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FADDRLO 0 0 0 0 = Unimplemented or Reserved Figure 29-15. Flash Address Low Register (FADDRLO) All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written. 29.3.2.10 Flash Data Registers (FDATA) The FDATAHI and FDATALO registers are the Flash data registers. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATAHI 0 0 0 0 = Unimplemented or Reserved Figure 29-16. Flash Data High Register (FDATAHI) MC9S12XDP512 Data Sheet, Rev. 2.17 1206 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 FDATALO 0 0 0 0 = Unimplemented or Reserved Figure 29-17. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 29.3.2.11 RESERVED1 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-18. RESERVED1 All bits read 0 and are not writable. 29.3.2.12 RESERVED2 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-19. RESERVED2 All bits read 0 and are not writable. 29.3.2.13 RESERVED3 This register is reserved for factory testing and is not accessible. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1207 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-20. RESERVED3 All bits read 0 and are not writable. 29.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. 7 6 5 4 3 2 1 0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 29-21. RESERVED4 All bits read 0 and are not writable. 29.4 29.4.1 Functional Description Flash Command Operations Write operations are used to execute program, erase, erase verify, erase abort, and data compress algorithms described in this section. The program and erase algorithms are controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command register, as well as the associated address and data registers, operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command is still in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row in the Flash block as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register with corresponding interrupts generated, if enabled. The next sections describe: 1. How to write the FCLKDIV register 2. Command write sequences to program, erase, erase verify, erase abort, and data compress operations on the Flash memory 3. Valid Flash commands 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations MC9S12XDP512 Data Sheet, Rev. 2.17 1208 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: • FCLK as the clock of the Flash timing control block • Tbus as the period of the bus clock • INT(x) as taking the integer part of x (e.g. INT(4.323) = 4) then FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 29-22. For example, if the oscillator clock frequency is 950kHz and the bus clock frequency is 10MHz, FCLKDIV bits FDIV[5:0] should be set to 0x04 (000100) and bit PRDIV8 set to 0. The resulting FCLK frequency is then 190kHz. As a result, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 190 ) ⁄ 200 × 100 = 5% If the oscillator clock frequency is 16MHz and the bus clock frequency is 40MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0A (001010) and bit PRDIV8 set to 1. The resulting FCLK frequency is then 182kHz. In this case, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash memory with FCLK < 150 kHz should be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that (1/FCLK+Tbus) < 5µs can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written to, the Flash command loaded during a command write sequence will not execute and the ACCERR flag in the FSTAT register will set. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1209 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Tbus < 1µs? yes PRDIV8=0 (reset) no ALL COMMANDS IMPOSSIBLE oscillator_clock 12.8MHz? yes no PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK=oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.15MHz ? no yes END yes FDIV[5:0] > 4? no ALL COMMANDS IMPOSSIBLE Figure 29-22. Determination Procedure for PRDIV8 and FDIV Bits MC9S12XDP512 Data Sheet, Rev. 2.17 1210 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 29.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows: 1. Write to a valid address in the Flash memory. 2. Write a valid command to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command. The address written in step 1 will be stored in the FADDR registers and the data will be stored in the FDATA registers. If the CBEIF flag in the FSTAT register is clear when the first Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. Once a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will set upon completion of all active and buffered commands. 29.4.2 Flash Commands Table 29-18 summarizes the valid Flash commands along with the effects of the commands on the Flash block. Table 29-18. Flash Command Description FCMDB 0x05 NVM Command Erase Verify Data Compress Program Function on Flash Memory Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion. Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. Program a word (two bytes) in the Flash block. 0x06 0x20 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1211 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-18. Flash Command Description FCMDB 0x40 0x41 NVM Command Sector Erase Mass Erase Sector Erase Abort Function on Flash Memory Erase all memory bytes in a sector of the Flash block. Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector should not be considered erased if the ACCERR flag is set upon command completion. 0x47 CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. MC9S12XDP512 Data Sheet, Rev. 2.17 1212 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 29-23. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the selected Flash block are verified to be erased. If any address in a selected Flash block is not erased, the erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify operation. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1213 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Erase Verify Command 0x05 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Erase Verify Status BLANK Set? no yes EXIT Flash Block Erased EXIT Flash Block Not Erased Figure 29-23. Example Erase Verify Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1214 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 29-24. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command. The address written determines the starting address for the data compress operation and the data written determines the number of consecutive words to compress. If the data value written is 0x0000, 64K addresses or 128 Kbytes will be compressed. 2. Write the data compress command, 0x06, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the data compress command. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of consecutive words to compress plus 18 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Once the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected signature to determine the integrity of the selected data stored in the selected Flash memory. If the last address of a Flash block is reached during the data compress operation, data compression will continue with the starting address of the Flash block. The MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the data compress operation. NOTE Since the FDATA registers (or data buffer) are written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence should only be started after reading the signature stored in the FDATA registers. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector should be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1215 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Address to start compression and number of word addresses to compress Write: FCMD register Data Compress Command 0x06 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes Read: FDATA registers Data Compress Signature Signature Valid? yes EXIT no Erase and Reprogram Flash Sector(s) Compressed Figure 29-24. Example Data Compress Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 1216 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature based on selected Flash array data. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn. 29-1 where MISR is the content of the internal signature register and DATA is the data to be compressed as shown in Figure 29-25. DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[15] + DQ M0 > + DQ M1 > + + DQ M2 > + + DQ M3 > + DQ M4 > + + DQ M5 > ... + DQ M15 > + = Exclusive-OR MISR[15:0] = Q[15:0] Figure 29-25. 16-Bit MISR Diagram During the data compress operation, the following steps are executed: 1. MISR is reset to 0xFFFF. 2. Initialized DATA equal to 0xFFFF is compressed into the MISR which results in the MISR containing 0x0001. 3. DATA equal to the selected Flash array data range is read and compressed into the MISR with addresses incrementing. 4. DATA equal to the selected Flash array data range is read and compressed into the MISR with addresses decrementing. 5. DATA equal to the contents of the MISR is compressed into the same MISR. 6. The contents of the MISR are written to the FDATA registers. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1217 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 29-26. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2. Write the program command, 0x20, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command. If a word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a new command write sequence has been buffered. By executing a new program command write sequence on sequential words after the CBEIF flag in the FSTAT register has been set, up to 55% faster programming time per word can be effectively achieved than by waiting for the CCIF flag to set after each program operation. MC9S12XDP512 Data Sheet, Rev. 2.17 1218 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no Write: Flash Address and program Data yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. 2. Write: FCMD register Program Command 0x20 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 3. Bit Polling for Buffer Empty Check CBEIF Set? no yes Sequential Programming Decision Next Word? no Read: FSTAT register yes Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 29-26. Example Program Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1219 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 29-27. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command. The Flash address written determines the sector to be erased while global address bits [9:0] and the data written are ignored. 2. Write the sector erase command, 0x40, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command. If a Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. Once the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1220 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Sector Address and Dummy Data Write: FCMD register Sector Erase Command 0x40 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 29-27. Example Sector Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1221 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 29-28. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2. Write the mass erase command, 0x41, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command. If a Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a new command write sequence has been buffered. MC9S12XDP512 Data Sheet, Rev. 2.17 1222 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes no NOTE: FCLKDIV needs to be set once after each reset. Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? yes no Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Block Address and Dummy Data Write: FCMD register Mass Erase Command 0x41 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? no yes EXIT Figure 29-28. Example Mass Erase Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1223 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 29-29. The sector erase abort command write sequence is as follows: 1. Write to any Flash block address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2. Write the sector erase abort command, 0x47, to the FCMD register. 3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase abort command. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set once the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the Flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, a Flash sector being erased when the abort command was launched will be fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (see Section 29.4.1.1, “Writing the FCLKDIV Register”) plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command should not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. MC9S12XDP512 Data Sheet, Rev. 2.17 1224 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? yes no Erase Abort Needed? yes no Sector Erase Completed EXIT 1. Write: Dummy Flash Address and Dummy Data Write: FCMD register Sector Erase Abort Cmd 0x47 Write: FSTAT register Clear CBEIF 0x80 Read: FSTAT register 2. 3. Bit Polling for Command Completion Check CCIF Set? yes no Access Error Check ACCERR Set? no yes Write: FSTAT register Clear ACCERR 0x10 Sector Erase Completed EXIT Sector Erase Aborted EXIT Figure 29-29. Example Sector Erase Abort Command Flow MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1225 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4. Starting a command write sequence while a sector erase abort operation is active. 5. Writing to any Flash register other than FCMD after writing to a Flash address. 6. Writing a second command to the FCMD register in the same command write sequence. 7. Writing an invalid command to the FCMD register. 8. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 9. Writing to a Flash address after writing to the FCMD register. 10. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 11. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 29.4.2.6, “Sector Erase Abort Command”). 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 29.5.2, “Stop Mode”). If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 29.3.2.6, “Flash Status Register (FSTAT)”). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if an address written in the command write sequence was in a protected area of the Flash memory 2. Writing the sector erase command if an address written in the command write sequence was in a protected area of the Flash memory 3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the block If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 29.3.2.6, “Flash Status Register (FSTAT)”). MC9S12XDP512 Data Sheet, Rev. 2.17 1226 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.5 29.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 29.8, “Interrupts”). 29.5.2 Stop Mode If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 29.4.1.2, “Command Write Sequence”). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations. 29.5.3 Background Debug Mode In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 29-18 can be executed. If the MCU is secured and is in special single chip mode, only mass erase can be executed. 29.6 Flash Module Security The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 29.3.2.2, “Flash Security Register (FSEC)”. The contents of the Flash security byte at 0x7F_FF0F in the Flash Configuration Field must be changed directly by programming 0x7F_FF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte is left in a secured state, any reset will cause the MCU to initialize to a secure operating mode. 29.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 29.3.2.2, “Flash Security Register (FSEC)”) and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1227 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 29.3.2.2, “Flash Security Register (FSEC)”), the MCU can be unsecured by the backdoor key access sequence described below: 1. Set the KEYACC bit in the Flash Configuration Register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00–0xFF07 sequentially starting with 0x7F_FF00. 3. Clear the KEYACC bit. Depending on the user code used to write the backdoor keys, a wait cycle (NOP) may be required before clearing the KEYACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0x7F_FF00–0x7F_FF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEYACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. Once the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00–0x7F_FF07 in the Flash Configuration Field. The security as defined in the Flash security byte (0x7F_FF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0x7F_FF00–0x7F_FF07 are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). MC9S12XDP512 Data Sheet, Rev. 2.17 1228 Freescale Semiconductor Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method: • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: • Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU. 29.7 29.7.1 Resets Flash Reset Sequence On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 29-1: • FPROT — Flash Protection Register (see Section 29.3.2.5). • FCTL - Flash Control Register (see Section 29.3.2.8). • FSEC — Flash Security Register (see Section 29.3.2.2). 29.7.2 Reset While Flash Command Active If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. 29.8 Interrupts The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data and command buffers are empty. Table 29-19. Flash Interrupt Sources Interrupt Source Flash Address, Data and Command Buffers empty All Flash commands completed Interrupt Flag CBEIF (FSTAT register) CCIF (FSTAT register) Local Enable CBEIE (FCNFG register) CCIE (FCNFG register) Global (CCR) Mask I Bit I Bit MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1229 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 29.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is shown in Figure 29-30. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. CBEIF CBEIE Flash Command Interrupt Request CCIF CCIE Figure 29-30. Flash Interrupt Implementation For a detailed description of the register bits, refer to Section 29.3.2.4, “Flash Configuration Register (FCNFG)” and Section 29.3.2.6, “Flash Status Register (FSTAT)” . MC9S12XDP512 Data Sheet, Rev. 2.17 1230 Freescale Semiconductor Chapter 30 Security (S12X9SECV2) 30.1 Introduction This specification describes the function of the security mechanism in the S12X chip family (S12X9SECV2). 30.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the S12X chip family (in secure mode) are: • Protect the contents of non-volatile memories (Flash, EEPROM) • Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) • Disable access to internal Flash/EEPROM in expanded modes • Disable debugging features for CPU and XGATE Table 30-1 gives an overview over availability of security relevant features in unsecure and secure modes. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1231 Chapter 30 Security (S12X9SECV2) Table 30-1. Features Availability in Unsecure and Secure Modes Unsecure Mode NS Flash Array Access EEPROM Array Access NVM Commands BDM DBG Module Trace XGATE Debugging External Bus Interface Internal status visible multiplexed on external bus Internal accesses visible on external bus 1 Secure Mode ST ✔1 ✔ ✔ ✔ ✔ ✔ ✔ — NS ✔ ✔ ✔2 — — — — — SS ✔ ✔ ✔2 ✔3 — — — — NX — — ✔2 — — — ✔ — ES — — ✔2 — — — ✔ ✔ EX — — ✔2 — — — ✔ ✔ ST — — ✔2 — — — ✔ — SS ✔ ✔ ✔ ✔ ✔ ✔ — — NX ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ — ES ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ ✔ EX ✔1 ✔ ✔2 ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔2 ✔ ✔ ✔ — — — — — — — ✔ — — — — — ✔ Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed information. 2 Restricted NVM command set only. Please refer to the FTX/EETX block guides for detailed information. 3 BDM hardware commands restricted to peripheral registers only. 30.1.2 30.1.3 Modes of Operation Securing the Microcontroller Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. 7 6 5 4 3 2 1 0 0xFF0F KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 Figure 30-1. Flash Options/Security Byte MC9S12XDP512 Data Sheet, Rev. 2.17 1232 Freescale Semiconductor Chapter 30 Security (S12X9SECV2) The meaning of the bits KEYEN[1:0] is shown in Table 30-2. Please refer to Section 30.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 30-2. Backdoor Key Access Enable Bits KEYEN[1:0] 00 01 10 11 Backdoor Key Access Enabled 0 (disabled) 0 (disabled) 1 (enabled) 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 30-3. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. Table 30-3. Security Bits SEC[1:0] 00 01 10 11 Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured) NOTE Please refer to the Flash block guide (FTX) for actual security configuration (in section “Flash Module Security”). 30.1.4 Operation of the Secured Microcontroller By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller: MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1233 Chapter 30 Security (S12X9SECV2) 30.1.4.1 • • • • Normal Single Chip Mode (NS) Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. 30.1.4.2 • • • • • Special Single Chip Mode (SS) BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked. 30.1.4.3 • • • • • • Expanded Modes (NX, ES, EX, and ST) BDM operation is completely disabled. Internal Flash memory and EEPROM are disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. MC9S12XDP512 Data Sheet, Rev. 2.17 1234 Freescale Semiconductor Chapter 30 Security (S12X9SECV2) 30.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 30.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • • • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value. The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). It is not possible to download the backdoor keys using background debug mode. The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF. 30.1.5.2 Backdoor Key Access Sequence These are the necessary steps for a successful backdoor key access sequence: 1. Set the KEYACC bit in the Flash configuration register FCNFG. 2. Write the first 16-bit word of the backdoor key to 0xFF00 (0x7F_FF00). 3. Write the second 16-bit word of the backdoor key to 0xFF02 (0x7F_FF02). 4. Write the third 16-bit word of the backdoor key to 0xFF04 (0x7F_FF04). 5. Write the fourth 16-bit word of the backdoor key to 0xFF06 (0x7F_FF06). 6. Clear the KEYACC bit in the Flash Configuration register FCNFG. NOTE Flash cannot be read while KEYACC is set. Therefore the code for the backdoor key access sequence must execute from RAM. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1235 Chapter 30 Security (S12X9SECV2) If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below. If any of the four 16-bit words does not match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will remain secured. 30.1.6 Reprogramming the Security Bits In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected. 30.1.7 Complete Memory Erase (Special Modes) The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset. MC9S12XDP512 Data Sheet, Rev. 2.17 1236 Freescale Semiconductor Chapter 30 Security (S12X9SECV2) Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate value to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPROT register to disable protection. 4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits. 5. Write 0x0000 to the EDATA register (0x011A–0x011B). 6. Write 0x0000 to the EADDR register (0x0118–0x0119). 7. Write 0x41 (mass erase) to the ECMD register. 8. Write 0x80 to the ESTAT register to clear CBEIF. 9. Write an appropriate value to the FCLKDIV register for correct timing. 10. Write 0x00 to the FCNFG register to select Flash block 0. 11. Write 0x10 to the FTSTMOD register (0x0102) to set the WRALL bit, so the following writes affect all Flash blocks. 12. Write 0xFF to the FPROT register to disable protection. 13. Write 0x30 to the FSTAT register to clear the PVIOL and ACCERR bits. 14. Write 0x0000 to the FDATA register (0x010A–0x010B). 15. Write 0x0000 to the FADDR register (0x0108–0x0109). 16. Write 0x41 (mass erase) to the FCMD register. 17. Write 0x80 to the FSTAT register to clear CBEIF. 18. Wait until all CCIF flags are set. 19. Reset back into special single chip mode. 20. Write an appropriate value to the FCLKDIV register for correct timing. 21. Write 0x00 to the FCNFG register to select Flash block 0. 22. Write 0xFF to the FPROT register to disable protection. 23. Write 0xFFBE to Flash address 0xFF0E. 24. Write 0x20 (program) to the FCMD register. 25. Write 0x80 to the FSTAT register to clear CBEIF. 26. Wait until the CCIF flag in FSTAT is are set. 27. Reset into any mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1237 Chapter 30 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev. 2.17 1238 Freescale Semiconductor Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General This supplement contains the most accurate electrical information for the S12XD, S12XB & S12XA families microcontroller available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled “C” in the parameter tables where appropriate. P: C: T: Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. D: A.1.2 Power Supply The MC9S12XDP512 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and parts of the internal voltage regulator. The VDDX, VSSX, VDDR, and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2, and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1239 Appendix A Electrical Characteristics NOTE In the following context VDD35 is used for either VDDA, VDDR, and VDDX; VSS35 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.1 I/O Pins Those I/O pins have a nominal level in the range of 3.15 V to 5.5 V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical; however, some of the functionality may be disabled. For example, for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5 V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on-chip voltage regulator. A.1.4 Current Injection Power supply must maintain regulation within operating VDD35 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD35) is greater than IDD35, the injection current may flow out of VDD35 and could result in external power supply going out of regulation. Ensure external VDD35 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low which would reduce overall power consumption. MC9S12XDP512 Data Sheet, Rev. 2.17 1240 Freescale Semiconductor Appendix A Electrical Characteristics A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS35 or VDD35). Table A-1. Absolute Maximum Ratings1 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 Rating I/O, regulator and analog supply voltage Digital logic supply voltage2 PLL supply voltage 2 Symbol VDD35 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST I D Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –25 –25 –0.25 –65 Max 6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155 Unit V V V V V V V V V mA mA mA °C Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O input voltage Analog reference XFC, EXTAL, XTAL inputs TEST input Instantaneous maximum current Single pin limit for all digital I/O pins3 Instantaneous maximum current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous maximum current Single pin limit for TEST 5 Storage temperature range IDL IDT Tstg Beyond absolute maximum ratings device might be damaged. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3 All digital I/O pins are internally clamped to V SSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4 Those pins are internally clamped to VSSPLL and VDDPLL. 5 This pin is clamped low to V SSPLL, but not clamped high. This pin must be tied low in applications. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1241 Appendix A Electrical Characteristics specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2. ESD and Latch-up Test Conditions Model Human Body Series resistance Storage capacitance Number of pulse per pin Positive Negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C — — Value 1500 100 3 3 –2.5 7.5 V V Unit Ohm pF Table A-3. ESD and Latch-Up Protection Characteristics Num 1 2 3 C C C C Rating Human Body Model (HBM) Charge Device Model (CDM) Latch-up current at TA = 125°C Positive Negative Latch-up current at TA = 27°C Positive Negative Symbol VHBM VCDM ILAT +100 –100 ILAT +200 –200 — — — — mA Min 2000 500 Max — — Unit V V mA 4 C MC9S12XDP512 Data Sheet, Rev. 2.17 1242 Freescale Semiconductor Appendix A Electrical Characteristics A.1.7 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4. Operating Conditions Rating I/O, regulator and analog supply voltage Digital logic supply voltage1 PLL supply voltage 2 Symbol VDD35 VDD VDDPLL ∆VDDX ∆VSSX fosc fbus TJ TA TJ TA TJ TA Min 3.15 2.35 2.35 –0.1 –0.1 0.5 0.5 –40 –40 –40 –40 –40 –40 Typ 5 2.5 2.5 0 0 — — — 27 — 27 — 27 Max 5.5 2.75 2.75 0.1 0.1 16 40 100 85 Unit V V V V V MHz MHz °C Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Oscillator Bus frequency C parts Operating junction temperature range Operating ambient temperature range2 V parts Operating junction temperature range Operating ambient temperature range2 M parts Operating junction temperature range Operating ambient temperature range2 1 °C 120 105 °C 140 125 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2 Please refer to Section A.1.8, “Power Dissipation and Thermal Characteristics” for more details about the relation between ambient temperature TA and device junction temperature TJ. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1243 Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be obtained from: T T T J A D = Junction Temperature, [ ° C ] = Ambient Temperature, [ ° C ] = Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ ° C/W] J = T + (P • Θ ) A D JA P Θ JA The total power dissipation can be calculated from: P P INT = Chip Internal Power Dissipation, [W] D =P INT +P IO Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal voltage regulator disabled P INT =I DD ⋅V DD IO +I = DDPLL ⋅V DDPLL +I DDA ⋅V DDA P ∑ RDSON ⋅ IIOi2 i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: R V OL = ----------- ;for outputs driven low DSON I OL respectively R V –V DD5 OH = ----------------------------------- ;for outputs driven high DSON I OH 2. Internal voltage regulator enabled P INT =I DDR ⋅V DDR +I DDA ⋅V DDA IDDR is the current shown in Table A-10. and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. P IO = ∑ RDSON ⋅ IIOi2 i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. MC9S12XDP512 Data Sheet, Rev. 2.17 1244 Freescale Semiconductor Appendix A Electrical Characteristics Table A-5. Thermal Package Characteristics1 Num C Rating LQFP144 1 2 3 4 5 T T Thermal resistance LQFP144, single sided PCB2 Thermal resistance LQFP144, double sided PCB with 2 internal planes3 Junction to Board LQFP 144 Junction to Case LQFP 1444 Junction to Package Top LQFP144 5 Symbol Min Typ Max Unit θJA θJA θJB θJC ΨJT — — — — — — — — — — 41 32 22 7/4 3 °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W LQFP112 6 7 8 9 10 T T Thermal resistance LQFP112, single sided PCB2 Thermal resistance LQFP112, double sided PCB with 2 internal planes5 Junction to Board LQFP112 Junction to Case LQFP112 4 5 θJA θJA θJB θJC ΨJT — — — — — — — — — — 433/494 323/394 223/274 73/114 3/2 Junction to Package Top LQFP112 QFP80 11 12 13 14 15 1 2 3 4 5 6 T T T T T Thermal resistance QFP 80, single sided PCB2 Thermal resistance QFP 80, double sided PCB with 2 internal planes3 Junction to Board QFP 80 Junction to Case QFP 80 6 7 θJA θJA θJB θJC ΨJT — — — — — — — — — — 453/494 333/364 193/204 113/144 3 Junction to Package Top QFP 80 7 The values for thermal resistance are achieved by package simulations Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Maskset L15Y / M84E in LQFP112 or QFP80 Maskset M42E in LQFP112 or QFP80 Junction to ambient thermal resistance, θJA was simulated to be equivalent to the JEDEC specification JESD51-7 in a horizontal configuration in natural convection. Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the “case” temperature. This basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. Thermal characterization parameter ΨJT is the “resistance” from junction to reference point thermocouple on top center of the case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in a steady state customer enviroment. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1245 Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL,XFC,TEST,VREGEN and supply pins. CAUTION The internal pull up/pull down device specification is different depending on maskset. Table A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < VDD35 < 3.6 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins. Num C 1 P Input high voltage T Input high voltage 2 P Input low voltage T Input low voltage 3 4 C Input hysteresis C Input leakage current (pins in high impedance input mode)1 Vin = VDD35 or VSS35 C Output high voltage (pins in output mode) Partial drive IOH = –0.75 mA P Output high voltage (pins in output mode) Full drive IOH = –4 mA C Output low voltage (pins in output mode) Partial Drive IOL = +0.9 mA P Output low voltage (pins in output mode) Full Drive IOL = +4.75 mA Rating Symbol VIH VIH VIL VIL VHYS Iin –1 Min 0.65*VDD35 — — VSS35 – 0.3 Typ — — — — 250 — 1 Max — VDD35 + 0.3 0.35*VDD35 — Unit V V V V mV µA 5 6 7 8 V OH VDD35 – 0.4 VDD35 – 0.4 — — — — — — — — 0.4 0.4 V V V V VOH VOL V OL Internal pull up/pull down device specification (items 9 to 12) only valid for masksets 0L15Y & 1L15Y 9 10 11 12 P Internal pull up device current, tested at VIL max. C Internal pull up device current, tested at VIH min. P Internal pull down device current, tested at VIH min. C Internal pull down device current, tested at VIL max. IPUL IPUH IPDH IPDL — -6 — 6 — — — — –60 60 — µA µA µA µA Internal pull up/pull down device specification (items 13 to 14) valid for all other masksets 13 14 15 16 P Internal pull up resistance VIH min > input voltage > VIL max P Internal pull down resistance VIH min > input voltage > VIL max D Input capacitance T Injection current Single pin limit Total device limit, sum of all injected currents 2 RPUL RPDH Cin IICS IICP 25 25 — –2.5 –25 6 — 55 55 — 2.5 25 KΩ KΩ pF mA MC9S12XDP512 Data Sheet, Rev. 2.17 1246 Freescale Semiconductor Appendix A Electrical Characteristics Table A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < VDD35 < 3.6 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins. 17 18 1 C Port H, J, P interrupt input pulse filtered3 C Port H, J, P interrupt input pulse passed 3 tPULSE tPULSE — 10 — — 3 — µs µs Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temper ature range from 50°C to 125°C. 2 Refer to Section A.1.4, “Current Injection” for more details 3 Parameter only applies in stop or pseudo stop mode. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1247 Appendix A Electrical Characteristics Table A-7. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins. Num C 1 P Input high voltage T Input high voltage 2 P Input low voltage T Input low voltage 3 4 C Input hysteresis P Input leakage current (pins in high impedance input mode)1 Measured at Vin = 5.5V and Vin=0V C Output high voltage (pins in output mode) Partial drive IOH = –2 mA P Output high voltage (pins in output mode) Full drive IOH = –10 mA C Output low voltage (pins in output mode) Partial drive IOL = +2 mA P Output low voltage (pins in output mode) Full drive IOL = +10 mA Rating Symbol V IH Min 0.65*VDD35 — — VSS35 – 0.3 Typ — — — — 250 Max — VDD35 + 0.3 0.35*VDD35 — — 1 Unit V V V V mV µA VIH VIL VIL VHYS I in –1 — 5 6 7 8 V OH VDD35 – 0.8 VDD35 – 0.8 — — — — — — — — 0.8 0.8 V V V V VOH VOL V OL Internal pull up/pull down device specification (items 9 to 12) only valid for masksets 0L15Y & 1L15Y 9 10 11 12 P Internal pull up device current, tested at VIL max C Internal pull up device current, tested at VIH min P Internal pull down device current, tested at VIH min C Internal pull down device current, tested at VIL max IPUL IPUH IPDH IPDL — –10 — 10 — — — — –130 — 130 — µA µA µA µA Internal pull up/pull down device specification (items 13 to 14) valid for all other masksets 13 14 15 16 P Internal pull up resistance VIH min > input voltage > VIL max P Internal pull down resistance VIH min > input voltage > VIL max D Input capacitance T Injection current Single pin limit Total device Limit, sum of all injected currents P Port H, J, P interrupt input pulse filtered3 P Port H, J, P interrupt input pulse passed 3 2 RPUL RPDH Cin IICS IICP tPULSE tPULSE 25 25 — –2.5 –25 — 10 — — 6 — 55 55 — 2.5 25 3 — KΩ KΩ pF mA 17 18 1 µs µs Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temper ature range from 50°C to 125°C. 2 Refer to Section A.1.4, “Current Injection” for more details 3 Parameter only applies in stop or pseudo stop mode. MC9S12XDP512 Data Sheet, Rev. 2.17 1248 Freescale Semiconductor Appendix A Electrical Characteristics Table A-8. I/O Characteristics for Port C, D, PE5, PE6, and PK7 for Reduced Input Voltage Thresholds Conditions are 4.5 V < VDD35 < 5.5 V Temperature from –40°C to +140°C, unless otherwise noted Num C 1 2 3 P Input high voltage P Input low voltage C Input hysteresis Rating Symbol VIH VIL VHYS Min 1.75 — — Typ — — 100 Max — 0.75 — Unit V V mV A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode and the CPU and XGATE code is executed from RAM, VDD35=5.5V, internal voltage regulator is enabled and the bus frequency is 40MHz using a 4-MHz external clock source (PE7=XCLKS=0). Production testing is performed using a square wave signal at the EXTAL input. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1249 Appendix A Electrical Characteristics Table A-9. shows the configuration of the peripherals for run current measurement. Table A-9. Peripheral Configurations for Run Supply Current Measurements Peripheral MSCAN SPI Configuration configured to loop-back mode using a bit rate of 1Mbit/s configured to master mode, continously transmit data (0x55 or 0xAA) at 1Mbit/s configured into loop mode, continously transmit data (0x55) at speed of 57600 baud operate in master mode and continously transmit data (0x55 or 0xAA) at the bit rate of 100Kbit/s configured to toggle its pins at the rate of 40kHz the peripheral shall be configured to output compare mode, Pulse accumulator and modulus counter enabled. the peripheral is configured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence. XGATE fetches code from RAM, XGATE runs in an infinite loop , it reads the Status and Flag registers of CAN’s, SPI’s, SCI’s in sequence and does some bit manipulation on the data COP Warchdog Rate 224 enabled, RTI Control Register (RTICTL) set to $FF the module is configured to run from the RC oscillator clock source. PIT is enabled, Micro-timer register 0 and 1 loaded with $0F and timer registers 0 to 3 are loaded with $03/07/0F/1F. the module is enabled and the comparators are configured to trigger in outside range. The range covers all the code executed by the core. SCI IIC PWM ECT ATD XGATE COP RTI API PIT DBG MC9S12XDP512 Data Sheet, Rev. 2.17 1250 Freescale Semiconductor Appendix A Electrical Characteristics A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. No generally applicable numbers can given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-10. Run and Wait Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 Rating Symbol Min Typ Max Unit Run supply current (Peripheral Configuration see Table A-9.) 1 2 C T T 3 T T T 4 T T T 5 T T T 6 T T T 7 T T T 8 9 T T 10 1 2 3 4 5 6 P Peripheral Set fosc=4MHz, fbus=40MHz Peripheral Set1 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set2 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set3 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set4 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set5 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz Peripheral Set6 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=20MHz fosc=4MHz, fbus=8MHz IDD35 110 mA 90 45 18 70 35 15 60 30 13 56 28 12 53 26 11 50 25 10 Wait supply current IDDW 95 mA P Peripheral Set ,PLL on XGATE executing code from RAM Peripheral Set2 fosc=4MHz, fbus=40MHz fosc=4MHz, fbus=8MHz All modules disabled, RTI enabled, PLL off 1 50 10 10 P The following peripherals are on: ATD0/ATD1/ECT/IIC1/PWM/SPI0-SPI2/SCI0-SCI2/CAN0-CAN4/XGATE The following peripherals are on: ATD0/ATD1/ECT/IIC1/PWM/SPI0-SPI2/SCI0-SCI2/CAN0-CAN4 The following peripherals are on: ATD0/ATD1/ECT/IIC1/PWM/SPI0-SPI2/SCI0-SCI2/ The following peripherals are on: ATD0/ATD1/ECT/IIC1/PWM/SPI0-SPI2 The following peripherals are on: ATD0/ATD1/ECT/IIC1/PWM/ The following peripherals are on: ATD0/ATD1/ECT/IIC1/ MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1251 Appendix A Electrical Characteristics Table A-11. Pseudo Stop and Full Stop Current Conditions are shown in Table A-4 unless otherwise noted Num C Rating –40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C –40°C 27°C 70°C 85°C 105°C 125°C 140°C Stop Current 12 C P C C P C P C P –40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C IDDS — — — — — — — — — 20 30 100 200 250 400 500 600 1000 — 100 — — 2000 — 3000 — 7000 µA Symbol Min Typ Max Unit µA Pseudo stop current (API, RTI, and COP disabled) PLL off 10 C P C C P C P C P C C C C C C C IDDPS — — — — — — — — — — — — — — — — 200 300 400 500 600 800 1000 1200 1500 500 750 850 1000 1200 1500 2000 — 500 — — 2500 — 3500 — 7000 — — — — — — — Pseudo stop current (API, RTI, and COP enabled) PLL off 11 IDDPS µA MC9S12XDP512 Data Sheet, Rev. 2.17 1252 Freescale Semiconductor Appendix A Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-12 and Table A-13 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-12. ATD 5-V Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted, supply voltage 4.5 V < VDDA < 5.5 V Num C 1 D Reference potential Low High C Differential reference voltage1 D ATD clock frequency D ATD 10-bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D ATD 8-Bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D Recovery time (VDDA = 5.0 Volts) P Reference supply current 2 ATD blocks on P Reference supply current 1 ATD block on Rating Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tREC IREF IREF Min VSSA VDDA/2 4.50 0.5 14 7 12 6 — — — — — — — — — — Typ — — 5.00 Max VDDA/2 VDDA 5.5 2.0 28 14 26 13 20 0.750 0.375 Unit V V V MHz Cycles µs Cycles µs µs mA mA 2 3 4 5 6 7 8 1 2 Full accuracy is not guaranteed when differential voltage is less than 4.50 V The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1253 Appendix A Electrical Characteristics Table A-13. ATD Operating Characteristics 3.3V Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 3.15V < VDDA < 3.6V Num C 1 D Reference potential Low High C Differential reference voltage1 D ATD clock frequency D ATD 10-bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D ATD 8-bit conversion period Clock cycles2 Conv, time at 2.0 MHz ATD clock fATDCLK D Recovery time (VDDA = 5.0 Volts) P Reference supply current 2 ATD blocks on P Reference supply current 1 ATD block on Rating Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tREC IREF IREF Min VSSA VDDA/2 3.15 0.5 14 7 12 6 — — — Typ — — 3.3 — — — — — — — — Max VDDA/2 VDDA 3.6 2.0 28 14 26 13 20 0.500 0.250 Unit V V V MHz Cycles µs Cycles µs µs mA mA 2 3 4 5 6 7 8 1 2 Full accuracy is not guaranteed when differential voltage is less than 3.15 V The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.2 Factors Influencing Accuracy Three factors — source resistance, source capacitance and current injection — have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance Due to the input pin leakage current as specified in Table A-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS–CINN). MC9S12XDP512 Data Sheet, Rev. 2.17 1254 Freescale Semiconductor Appendix A Electrical Characteristics A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as: VERR = K * RS * IINJ with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-14. ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol RS CINN CINS INA Kp Kn Min — — — –2.5 — — Typ — — — — — — Max 1 10 22 2.5 10-4 10-2 mA A/A A/A Unit KΩ pF C Max input source resistance T Total input capacitance Non sampling Sampling C Disruptive analog input current1 C Coupling ratio positive current injection C Coupling ratio negative current injection 3 4 5 1 See also Table A-7. item 14 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1255 Appendix A Electrical Characteristics A.2.3 A.2.3.1 ATD Accuracy 5-V Range Table A-15 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance, and source resistance. Table A-15. 5-V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH–VRL = 5.12 V. Resulting to one 8-bit count = 20 mV and one 10-bit count = 5 mV fATDCLK = 2.0 MHz Num C 1 2 3 4 5 6 7 8 1 Rating Symbol LSB DNL INL AE LSB DNL INL AE Min — –1 –2.5 –3 — –0.5 –1.0 –1.5 Typ 5 — ±1.5 ±2.0 20 — ±0.5 ±1.0 Max — 1 2.5 3 — 0.5 1.0 1.5 Unit mV Counts Counts Counts mV Counts Counts Counts P 10-bit resolution P 10-bit differential nonlinearity P 10-bit integral nonlinearity P 10-bit absolute error P 8-bit resolution P 8-bit differential nonlinearity P 8-bit integral nonlinearity P 8-bit absolute error 1 1 These values include the quantization error which is inherently 1/2 count for any A/D converter. A.2.3.2 3.3-V Range Table A-16 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance, and source resistance. Table A-16. 3.3-V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH–VRL = 3.328 V. Resulting to one 8-bit count = 13mV and one 10-bit count = 3.25 mV fATDCLK = 2.0 MHz Num C 1 2 3 4 5 6 7 8 1 Rating Symbol LSB DNL INL AE LSB DNL INL AE Min — –1.5 –3.5 –5 — –0.5 –1.5 –2.0 Typ 3.25 — ±1.5 ±2.5 13 — ±1.0 ±1.5 Max — 1.5 3.5 5 — 0.5 1.5 2.0 Unit mV Counts Counts Counts mV Counts Counts Counts P 10-bit resolution P 10-bit differential nonlinearity P 10-bit integral nonlinearity P 10-bit absolute error P 8-bit resolution P 8-bit differential nonlinearity P 8-bit integral nonlinearity P 8-bit absolute error 1 1 These values include the quantization error which is inherently 1/2 count for any A/D converter. MC9S12XDP512 Data Sheet, Rev. 2.17 1256 Freescale Semiconductor Appendix A Electrical Characteristics A.2.3.3 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = -------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: INL ( n ) = i=1 ∑ n V –V n 0 DNL ( i ) = -------------------- – n 1LSB MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1257 Appendix A Electrical Characteristics DNL Vi-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 10-Bit Resolution $3F3 LSB 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $FF $FE $FD 8-Bit Resolution Vin mV 9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50 Ideal Transfer Curve 2 10-Bit Transfer Curve 1 8-Bit Transfer Curve 50555060506550705075508050855090509551005105511051155120 Figure A-1. ATD Accuracy Definitions NOTE Figure A-1 shows only definitions, for specification values refer to Table A-15. MC9S12XDP512 Data Sheet, Rev. 2.17 1258 Freescale Semiconductor Appendix A Electrical Characteristics A.3 NVM, Flash, and EEPROM NOTE Unless otherwise noted the abbreviation NVM (nonvolatile memory) is used for both Flash and EEPROM. A.3.1 NVM Timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-17 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2 MHz. A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula. t swpgm 1 1 = 9 ⋅ ------------------------ + 25 ⋅ ----------f f bus NVMOP A.3.1.2 Burst Programming This applies only to the Flash where up to 64 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: t bwpgm 1 1 = 4 ⋅ ------------------------ + 9 ⋅ ----------f f NVMOP bus The time to program a whole row is: t brpgm =t swpgm + 63 ⋅ t bwpgm Burst programming is more than 2 times faster than single word programming. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1259 Appendix A Electrical Characteristics A.3.1.3 Sector Erase Erasing a 1024-byte Flash sector or a 4-byte EEPROM sector takes: t era 1 ≈ 4000 ⋅ -----------------------f NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: t mass 1 ≈ 20000 ⋅ -----------------------f NVMOP The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc MC9S12XDP512 Data Sheet, Rev. 2.17 1260 Freescale Semiconductor Appendix A Electrical Characteristics Table A-17. NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 Rating Symbol fNVMOSC fNVMBUS fNVMOP tswpgm 4 Min 0.5 1 150 46 2 2 2 Typ — — — — — — — — — — Max 801 — 200 74.5 31 3 Unit MHz MHz kHz µs µs 3 D External oscillator clock D Bus frequency for programming or erase operations D Operating frequency P Single word programming time D Flash burst programming consecutive word D Flash burst programming time for 64 words P Sector erase time P Mass erase time D Blank check time Flash per block D Blank check time EEPROM per block tbwpgm tbrpgm tera tmass tcheck tcheck 20.4 3 4 1331.2 205 100 11 11 5 2027.5 26.73 133 3 µs ms ms 6 6 65546 2058 7 tcyc tcyc 7 Restrictions for oscillator in crystal mode apply. Minimum programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. Maximum erase and programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1, “Single Word Programming” – Section A.3.1.4, “Mass Erase” for guidance. Burst programming operations are not applicable to EEPROM Minimum erase times are achieved under maximum NVM operating frequency, fNVMOP. Minimum time, if first word in the array is not blank Maximum time to complete check on an erased block MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1261 Appendix A Electrical Characteristics A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A-18. NVM Reliability Characteristics1 Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Flash Reliability Characteristics 1 2 3 4 C Data retention after 10,000 program/erase cycles at an average junction temperature of TJavg ≤ 85°C C Data retention with =100 nF — See PLL specification chapter Type Ceramic Ceramic X7R Ceramic X7R X7R/tantalum Ceramic X7R X7R/tantalum Value 220 nF 220 nF >=100 nF >=100 nF 220 nF >=100 nF Comes from crystal manufacturer See PLL specification chapter MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1295 Appendix C Recommended PCB Layout Figure C-1. 144-Pin LQFP Recommended PCB Layout VDDX C6 VREGEN VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VDDX2 C11 VSSX2 C12 VSSR2 VDDR2 VSSR1 C5 VDDR1 C4 Q1 C8 C7 VSSPLL VDDPLL R1 MC9S12XDP512 Data Sheet, Rev. 2.17 1296 Freescale Semiconductor C10 C9 Appendix C Recommended PCB Layout Figure C-2. 112-Pin LQFP Recommended PCB Layout VDDX C6 VSSX VREGEN VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 C5 VDDR Q1 C8 C7 VSSPLL VDDPLL R1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1297 C10 C9 Appendix C Recommended PCB Layout Figure C-3. 80-Pin QFP Recommended PCB Layout VDDX C6 VREGEN VSSX VSSA C3 VDDA VDD1 VSS2 C1 VSS1 VDD2 C2 C4 VSSR VDDR C5 Q1 C8 C7 VSSPLL VSSPLL C10 R1 VDDPLL C9 1298 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor Appendix D Using L15Y Silicon Appendix D Using L15Y Silicon The following items should be considerd when using L15Y Silicon: • Do not write or read to registers which are marked “Reserved” in Table 1-1. • Fill the interrupt vector locations which are marked “Reserved” in Table 1-12. according to your coding policies for unused interrupts • L15Y Silicon includes two analog to digital converters ATD0 and ATD1. ATD0 channels 7 to 0 are connected to PAD07 to PAD00 and ATD1 channels 7 to 0 are connected to PAD15 to PAD08. • L15Y Silicon integrates the S12X_DBG module Version 2. L15Y Silicon integrates the S12X_MMC module Version 2. This Version doesn’t support the following enhancement which is available on S12X_MMC Version 3: — S12XCPU and S12XBDM can access MCU resources which are on different target busses at the same time. I.E S12XCPU can access XSRAM and S12XBDM can access Register Space at the same time. MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1299 Appendix E Derivative Differences Appendix E Derivative Differences E.1 Memory Sizes and Package Options S12XD - Family Device 9S12XDP512 Package 144 LQFP 112 LQFP 144 LQFP Flash RAM 32K EEPROM ROM 512K 20K 9S12XDT512 112 LQFP 80 QFP 144 LQFP 9S12XDT384 112 LQFP 80 QFP 144 LQFP 384K 20K 4K 9S12XDQ256 112 LQFP 80 QFP 16K 144 LQFP 9S12XDT256 112 LQFP 80 QFP 144 LQFP 256K 9S12XD256 112 LQFP 80 QFP 144 LQFP 14K 3S12XDT256 112 LQFP 80 QFP 112 LQFP 16K 256K 9S12XDG128 80 QFP 112 LQFP 3S12XDG128 80 QFP 128K 12K 2K 128K MC9S12XDP512 Data Sheet, Rev. 2.17 1300 Freescale Semiconductor Appendix E Derivative Differences Device 9S12XD128 Package 112 LQFP Flash 128K RAM 8K 4K EEPROM 2K 1K ROM 80 QFP 9S12XD64 80 QFP 64K MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1301 Appendix E Derivative Differences E.2 Memory Sizes and Package Options S12XA & S12XB Family Table 1 S12XA - Family Memory Sizes Device Package 144 LQFP 9S12XA512 112 LQFP 80 QFP 4K 144 LQFP 9S12XA256 112 LQFP 80 QFP 112 LQFP 9S12XA128 80 QFP 128K 12K 2K 256K 16K 512K 32K Flash RAM EEPROM Table 2 S12XB - Family Memory Sizes Device 9S12XB256 80 QFP 112 LQFP 9S12XB128 80 QFP 128K 6K 1K Package 112 LQFP 256K 10K 2K Flash RAM EEPROM MC9S12XDP512 Data Sheet, Rev. 2.17 1302 Freescale Semiconductor Appendix E Derivative Differences E.3 MC9S12XD-Family Flash Configuration1 2 3 4 5 Global Address $78_0000 (PPAGE $E0) DP512 A512 128k DT384 DQ256 A/B256 128k DG128 A/B128 D64 128k $7A_0000 (PPAGE $E8) 128k $7C_0000 (PPAGE $F0) 128k $7E_0000 (PPAGE $F8) 128k 128k 128k 128k 128k 64k Shared XGATE/CPU area Not implemented 1. XGATE read access to Flash not possible on DG128/D128/A128/B128 and D64 2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF 3. Program Pages available on B256/A256/DQ256/DT256/D256 are $E0 - $E7 and $F8 - $FF 4. Shared XGATE/CPU area on A512/DP512/DT512/DT384 at global address $78_0800 to $78_FFFF (30Kbyte) 5. Shared XGATE/CPU area on A256/B256/DT256/DQ256/D256 at global address $78_0800 to $78_FFFF (30Kbyte) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1303 Appendix E Derivative Differences E.4 MC9S12XD/A/B -Family SRAM & EEPROM Configuration Figure E-1. Available RAM Pages on S12XD-Family1 RAM Page RP[7:0] 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 32K Byte 0xFC 0xFD 0xFE 0xFF 1 DP512 A512 DT512 DT384 DQ256 A256 DG128 A128 D128 D64 20K Byte 16K Byte 12K Byte 8K Byte 4K Byte On 9S12XD256 14K byte RAM available pages FF,FE,FD and upper half of page FC On 9S12XB256 10K byte RAM available pages FF, FE upper half of page FD On 9S12XB218 6K byte RAM available pages FF and upper half of page FE Table E-1. Available EEPROM Pages on MC9S12XD-Family DP512 DT512 DT384 DQ256 A256 A512 DG128 D128 A128 B256 EEPROM Page EP[7:0] D64 B128 0xFA 0xFB 0xFC 0xFD 4K Byte 0xFE 2K Byte 0xFF 1K Byte MC9S12XDP512 Data Sheet, Rev. 2.17 1304 Freescale Semiconductor Appendix E Derivative Differences E.5 Peripheral Sets S12XD - Family Device 9S12XDP512 Package 144LQFP 112LQFP 144LQFP XGATE CAN 5 5 3 3 3 3 3 3 4 4 SCI 6 6 6 6 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 IIC 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ECT 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIT 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 A/D 2/24 2/16 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 1/162 1/8 1/16(2) 1/8 1/16(2) 1/8 1/8 I/O 119 91 119 91 59 119 91 59 119 91 59 119 91 59 119 91 59 119 91 59 91 59 91 59 91 59 59 9S12XDT512 112LQFP 80QFP 144LQFP 9S12XDT384 112LQFP 80QFP 144LQFP 9S12XDQ256 112LQFP yes 80QFP 144LQFP 9S12XDT256 4 3 3 3 1 1 1 3 3 3 2 2 2 yes1 112LQFP 80QFP 144LQFP 9S12XD256 112LQFP 80QFP 144LQFP 3S12XDT256 112LQFP 80QFP 112LQFP 9S12XDG128 80QFP 112LQFP 3S12XDG128 80QFP 112LQFP 9S12XD128 2 1 1 1 80QFP 9S12XD64 1Can 80QFP execute code only from RAM MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1305 Appendix E Derivative Differences 2 ATD1 routed to PAD00-15 instead of PAD08-23. E.6 Peripheral Sets S12XA & S12XB - Family Device Package 144LQFP XGATE CAN SCI 6 4 2 SPI 3 3 2 3 3 2 2 2 IIC 1 1 1 1 1 1 1 1 ECT 8 8 8 8 8 8 8 8 PIT 4 4 4 4 4 4 2 2 A/D 2/24 2/16 1/8 2/24 2/16 1/8 1/162 1/8 I/O 119 91 59 119 91 59 91 59 9S12XA512 112LQFP 80QFP yes 144LQFP no 9S12XA256 4 4 2 2 yes1 112LQFP 80QFP 112LQFP 9S12XA128 80QFP 1 2 2 Can execute code only from RAM ATD1 routed to PAD00-15 instead of PAD08-23 Device 9S12XB256 Package 112LQFP 80QFP 112LQFP XGATE CAN 1 1 SCI 2 2 2 2 SPI 1 1 1 1 IIC 1 1 1 1 ECT 8 8 8 8 PIT 4 4 2 2 A/D 1/16 1/8 1/162 1/8 yes1 1 9S12XB128 80QFP 1 2 Can execute code only from RAM ATD1 routed to PAD00-15 instead of PAD08-23 MC9S12XDP512 Data Sheet, Rev. 2.17 1306 Freescale Semiconductor Appendix E Derivative Differences E.7 • • Pinout explanations: A/D is the number of modules/total number of A/D channels. I/O is the sum of ports capable to act as digital input or output. – 144 Pin Packages: Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only, H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 24 25 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ) 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) 80 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ) – – • • • • • • • • • • • • • • CAN0 can be routed under software control from PM[1:0] to pins PM[3:2] or PM[5:4] or PJ[7:6]. CAN4 pins are shared between IIC0 pins. CAN4 can be routed under software control from PJ[7:6] to pins PM[5:4] or PM[7:6]. Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4 Versions with 3 CAN modules will have CAN0, CAN1 and CAN4. Versions with 2 CAN modules will have CAN0 and CAN4. Versions with 1 CAN modules will have CAN0 Versions with 2 SPI modules will have SPI0 and SPI1. Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4. Versions with 2 SCI modules will have SCI0 and SCI1. Versions with 1 IIC module will have IIC0. SPI0 can be routed to either Ports PS[7:4] or PM[5:2]. SPI1 pins are shared with PWM[3:0]; In 144 and 112-pin versions, SPI1 can be routed under software control to PH[3:0]. SPI2 pins are shared with PWM[7:4]; In 144 and 112-pin versions, SPI2 can be routed under software control to PH[7:4]. In 80-pin packages, SS-signal of SPI2 is not bonded out! MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1307 Appendix F Ordering Information Appendix F Ordering Information The following figure provides an ordering number example for the devices covered by this data book. There are two options when ordering a device. Customers must choose between ordering either the mask-specific partnumber or the generic / mask-independent partnumber Ordering the mask-specific partnumber enables the customer to specify which particular maskset they will receive whereas FSL will ship the currently preferred maskset against any orders for the generic partnumber. In either case, the marking on the device will always show the generic / mask-independent partnumber and the mask set number. For specific partnumbers, please contact your local sales office. The below figure illustrates a mask-specific ordering number. Part numbers may be abbreviated: check with manufacturer for exact part number S 9 12XDP512 J1 M AL R Part name (abbreviated) see Table 1-6 Tape & Reel Suffix (Optional): No R = No Tape & Reel R = Tape & Reel Package Option FU = 80QFP (non lead -free) PV = 112LQFP (non lead -free) FV = 144LQFP (non lead -free) AA = 80QFP (lead free) AL=112LQFP (lead free) AG = 144LQFP (Lead free) Temperature Option C = -40 to 85 °C V = -40 to 105 °C M = -40 to 125 °C Status / Partnumber type S or SC = Maskset specific partnumber MC = Generic/mask independent partnumber P or PC = Prototype status Maskset identifier suffix (two digits): First digit references wafer fab Second digit differentiates mask This suffix is omitted in generic partnumbers J1 = 1L15Y maskset in this case F0 = 0M42E maskset in this case Main Memory Type 9=Flash 3=ROM MC9S12XDP512 Data Sheet, Rev. 2.17 1308 Freescale Semiconductor Appendix G Detailed Register Map Appendix G Detailed Register Map The following tables show the detailed register map of the MC9S12XD-Family. 0x0000–0x0009 Port Integration Module (PIM) Map 1 of 5 Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 Name PORTA PORTB DDRA DDRB PORTC PORTD DDRC DDRD PORTE DDRE R W R W R W R W R W R W R W R W R W R W Bit 7 PA7 PB7 DDRA7 DDRB7 PC7 PD7 DDRC7 DDRD7 PE7 DDRE7 Bit 6 PA6 PB6 DDRA6 DDRB6 PC6 PD6 DDRC6 DDRD6 PE6 DDRE6 Bit 5 PA5 PB5 DDRA5 DDRB5 PC5 PD5 DDRC5 DDRD5 PE5 DDRE5 Bit 4 PA4 PB4 DDRA4 DDRB4 PC4 PD4 DDRC4 DDRD4 PE4 DDRE4 Bit 3 PA3 PB3 DDRA3 DDRB3 PC3 PD3 DDRC3 DDRD3 PE3 DDRE3 Bit 2 PA2 PB2 DDRA2 DDRB2 PC2 PD2 DDRC2 DDRD2 PE2 DDRE2 Bit 1 PA1 PB1 DDRA1 DDRB1 PC1 PD1 DDRC1 DDRD1 PE1 0 Bit 0 PA 0 PB0 DDRA0 DDRB0 PC0 PD0 DDRC0 DDRD0 PE0 0 0x000A–0x000B Module Mapping Control (S12XMMC) Map 1 of 4 Address 0x000A 0x000B Name MMCCTL0 MODE R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 0 Bit 3 0 0 Bit 2 CS2E 0 Bit 1 CS1E 0 Bit 0 CS0E 0 MODC MODB MODA 0x000C–0x000D Port Integration Module (PIM) Map 2 of 5 Address 0x000C 0x000D Name PUCR RDRIV R W R W Bit 7 PUPKE RDPK Bit 6 BKPUE 0 Bit 5 0 0 Bit 4 PUPEE RDPE Bit 3 PUPDE RDPD Bit 2 PUPCE RDPC Bit 1 PUPBE RDPB Bit 0 PUPAE RDPA MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1309 Appendix G Detailed Register Map 0x000E–0x000F External Bus Interface (S12XEBI) Map Address 0x000E 0x000F Name EBICTL0 EBICTL1 Bit 7 R ITHRS W R EWAITE W Bit 6 0 0 Bit 5 HDBE 0 Bit 4 ASIZ4 0 Bit 3 ASIZ3 0 Bit 2 ASIZ2 EXSTR2 Bit 1 ASIZ1 EXSTR1 Bit 0 ASIZ0 EXSTR0 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4 Address 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 Name GPAGE DIRECT Reserved MMCCTL1 Reserved Reserved RPAGE EPAGE R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 GP6 DP14 0 0 0 0 Bit 5 GP5 DP13 0 0 0 0 Bit 4 GP4 DP12 0 0 0 0 Bit 3 GP3 DP11 0 0 0 0 Bit 2 GP2 DP10 0 Bit 1 GP1 DP9 0 Bit 0 GP0 DP8 0 DP15 0 0 0 0 EROMON 0 0 ROMHM 0 0 ROMON 0 0 RP7 EP7 RP6 EP6 RP5 EP5 RP4 EP4 RP3 EP3 RP2 EP2 RP1 EP1 RP0 EP0 0x0018–0x001B Miscellaneous Peripheral Address 0x0018 0x0019 0x001A 0x001B Name Reserved Reserved PARTIDH PARTIDL R W R W R W R W Bit 7 0 0 1 0 Bit 6 0 0 1 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 1 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0 0x001C–0x001F Port Integration Module (PIM) Map 3 of 5 Address 0x001C Name ECLKCTL R W Bit 7 NECLK Bit 6 NCLKX2 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 EDIV1 Bit 0 EDIV0 MC9S12XDP512 Data Sheet, Rev. 2.17 1310 Freescale Semiconductor Appendix G Detailed Register Map 0x001C–0x001F Port Integration Module (PIM) Map 3 of 5 Address 0x001D Name Reserved R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0 0x001E 0x001F IRQCR Reserved IRQE 0 IRQEN 0 0x0020–0x0027 Debug Module (S12XDBG) Map Address 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x00281 0x00282 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 1 Name DBGC1 DBGSR DBGTCR DBGC2 DBGTBH DBGTBL DBGCNT DBGSCRX DBGXCTL (COMPA/C) DBGXCTL (COMPB/D) DBGXAH DBGXAM DBGXAL DBGXDH DBGXDL DBGXDHM DBGXDLM R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 ARM TBF Bit 6 0 TRIG EXTF Bit 5 XGSBPE 0 Bit 4 BDM 0 Bit 3 Bit 2 Bit 1 Bit 0 DBGBRK 0 SSF2 COMRV SSF1 SSF0 TSOURCE 0 Bit 15 Bit 7 0 0 0 0 0 0 Bit 14 Bit 6 0 TRANGE 0 Bit 12 Bit 4 TRCMOD CDCM Bit 11 Bit 3 CNT 0 Bit 10 Bit 2 TALIGN ABCM Bit 9 Bit 1 Bit 8 Bit 0 Bit 13 Bit 5 SC3 RW RW 19 11 3 11 3 11 3 SC2 RWE RWE 18 10 2 10 2 10 2 SC1 SRC SRC 17 9 1 9 1 9 1 SC0 COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 NDB SZ Bit 22 14 6 14 6 14 6 TAG TAG 21 13 5 13 5 13 5 BRK BRK 20 12 4 12 4 12 4 SZE 0 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 This represents the contents if the Comparator A or C control register is blended into this address MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1311 Appendix G Detailed Register Map 2 This represents the contents if the Comparator B or D control register is blended into this address MC9S12XDP512 Data Sheet, Rev. 2.17 1312 Freescale Semiconductor Appendix G Detailed Register Map 0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4 Address 0x0030 0x0031 Name PPAGE Reserved R W R W Bit 7 PIX7 0 Bit 6 PIX6 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5 Address 0x0032 0x0033 Name PORTK DDRK R W R W Bit 7 PK7 DDRK7 Bit 6 PK6 DDRK6 Bit 5 PK5 DDRK5 Bit 4 PK4 DDRK4 Bit 3 PK3 DDRK3 Bit 2 PK2 DDRK2 Bit 1 PK1 DDRK1 Bit 0 PK0 DDRK0 0x0034–0x003F Clock and Reset Generator (CRG) Map Address 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F Name SYNR REFDV CTFLG CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP CTCTL ARMCOP Bit 7 R 0 W 0 R W R 0 W R RTIF W R RTIE W R PLLSEL W R CME W R RTDEC W R WCOP W R 0 W R 0 W R 0 W Bit 7 Bit 6 0 0 0 Bit 5 SYN5 REFDV5 0 Bit 4 SYN4 REFDV4 Bit 3 SYN3 REFDV3 Bit 2 SYN2 REFDV2 Bit 1 SYN1 REFDV1 0 Bit 0 SYN0 REFDV0 0 SCM 0 PORF ILAF PSTP PLLON RTR6 RSBCK 0 0 0 6 LVRF 0 0 0 0 0 Reserved For Factory Test LOCK TRACK LOCKIF LOCKIE 0 0 0 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1 PLLWAI FSTWKP RTR3 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0 AUTO RTR5 0 0 0 0 5 ACQ RTR4 0 PRE RTR2 CR2 0 0 0 2 0 0 Reserved For Factory Test 0 Reserved For Factory Test 0 0 4 3 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1313 Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 IOS7 0 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0 TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0 TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0 PRNT TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0 TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 C6F 0 C5F 0 C4F 0 14 6 14 6 14 6 13 5 13 5 13 5 12 4 12 4 12 4 11 3 11 3 11 3 10 2 10 2 10 2 9 1 9 1 9 1 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1314 Freescale Semiconductor Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3) Address 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064 0x0065 0x0066 0x0067 0x0068 0x0069 0x006A 0x006B 0x006C Name TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved Bit 7 R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R 0 W R 0 W R Bit 7 W R Bit 7 W R Bit 7 W R Bit 7 W R MCZI W R MCZF W R 0 W R DLY7 W R NOVW7 W R SH37 W R 0 W Bit 6 14 6 14 6 14 6 14 6 14 6 PAEN 0 Bit 5 13 5 13 5 13 5 13 5 13 5 PAMOD 0 Bit 4 12 4 12 4 12 4 12 4 12 4 PEDGE 0 Bit 3 11 3 11 3 11 3 11 3 11 3 CLK1 0 Bit 2 10 2 10 2 10 2 10 2 10 2 CLK0 0 Bit 1 9 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0 6 6 6 6 MODMC 0 0 5 5 5 5 RDMCL 0 0 4 4 4 4 0 ICLAT 0 0 3 3 3 3 0 FLMC POLF3 2 2 2 2 MCEN POLF2 PA3EN DLY3 NOVW3 TFMOD 0 PA2EN DLY2 NOVW2 PACMX 0 PA1EN DLY1 NOVW1 BUFEN 0 PA0EN DLY0 NOVW0 LATQ 0 DLY6 NOVW6 SH26 0 DLY5 NOVW5 SH15 0 DLY4 NOVW4 SH04 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1315 Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3) Address 0x006D 0x006E 0x006F 0x0070 0x0071 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 0x0078 0x0079 0x007A 0x007B 0x007C 0x007D 0x007E 0x007F Name TIMTST PTPSR PTMCPSR PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Bit 7 R 0 W R PTPS7 W R PTMPS7 W R 0 W R 0 W R PA3H7 W R PA2H7 W R PA1H7 W R PA0H7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W R Bit 15 W R Bit 7 W Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 0 Bit 1 0 Bit 0 0 0 0 Reserved For Factory Test PTPS4 PTMPS4 0 0 PA3H4 PA2H4 PA1H4 PA0H4 PTPS3 PTMPS3 0 0 PA3H3 PA2H3 PA1H3 PA0H3 PTPS6 PTMPS6 PBEN 0 PA3H6 PA2H6 PA1H6 PA0H6 PTPS5 PTMPS5 0 0 PA3H5 PA2H5 PA1H5 PA0H5 PTPS2 PTMPS2 0 0 PA3H2 PA2H2 PA1H2 PA0H2 PTPS1 PTMPS1 PBOVI PBOVF PA3H1 PA2H1 PA1H1 PA0H1 PTPS0 PTMPS0 0 0 PA3H0 PA2H0 PA1H 0 PA0H0 14 6 14 6 14 6 14 6 14 6 13 5 13 5 13 5 13 5 13 5 12 4 12 4 12 4 12 4 12 4 11 3 11 3 11 3 11 3 11 3 10 2 10 2 10 2 10 2 10 2 9 1 9 1 9 1 9 1 9 1 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1316 Freescale Semiconductor Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Address 0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086 0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 0x0093 0x0094 0x0095 Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0 ATD1TEST1 ATD1STAT2 ATD1STAT1 ATD1DIEN0 ATD1DIEN ATD1PTAD0 ATD1PTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L R W R W R W R W R W R W R W R W R W R W Bit 7 0 ETRIG SEL ADPU 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 WRAP3 ETRIG CH3 ETRIGP S1C PRS3 CD CC3 0 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 0 U U CCF10 CCF2 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 0 U U CCF9 CCF1 Bit 0 WRAP0 ETRIG CH0 ASCIF AFFC S8C SMP1 DSGN 0 0 U U CCF14 CCF6 AWAI S4C SMP0 SCAN ETORF 0 U U CCF13 CCF5 ETRIGLE S2C PRS4 MULT FIFOR 0 FRZ0 PRS0 CA CC0 0 U SRES8 DJM SCF 0 U U U U Reserved For Factory Test U U CCF12 CCF4 CCF11 CCF3 SC CCF8 CCF0 R CCF15 W R CCF7 W R IEN15 W R IEN7 W R PTAD15 W R PTAD7 W R Bit15 W R Bit7 W R Bit15 W R Bit7 W R Bit15 W R Bit7 W IEN14 IEN6 PTAD14 PTAD6 14 Bit6 14 Bit6 14 Bit6 IEN13 IEN5 PTAD13 PTAD5 13 0 13 0 13 0 IEN12 IEN4 PTAD12 PTAD4 12 0 12 0 12 0 IEN11 IEN3 PTAD11 PTAD3 11 0 11 0 11 0 IEN10 IEN2 PTAD10 PTAD2 10 0 10 0 10 0 IEN9 IEN1 PTAD9 PTAD1 9 0 9 0 9 0 IEN8 IEN0 PTAD8 PTAD0 Bit8 0 Bit8 0 Bit8 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1317 Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 2 of 3) Address 0x0096 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C 0x009D 0x009E 0x009F 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB Name ATD1DR3H ATD1DR3L ATD1DR4H ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L ATD1DR8H ATD1DR8L ATD1DR9H ATD1DR9L ATD1DR10H ATD1DR10L ATD1DR11H ATD1DR11L ATD1DR12H ATD1DR12L ATD1DR13H ATD1DR13L R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1318 Freescale Semiconductor Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 3 of 3) Address 0x00AC 0x00AD 0x00AE 0x00AF Name ATD1DR14H R W R ATD1DR14L W R ATD1DR15H W R ATD1DR15L W Bit 7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 Bit 4 12 0 12 0 Bit 3 11 0 11 0 Bit 2 10 0 10 0 Bit 1 9 0 9 0 Bit 0 Bit8 0 Bit8 0 0x00B0–0x00B7 Inter IC Bus (IIC1) Map Address 0x00B0 0x00B1 0x00B2 0x00B3 0x00B4 0x00B5 0x00B6 0x00B7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 Bit 0 0 IBC0 IBSWAI RXAK IBIF D1 0 0 0 D7 0 0 0 D6 0 0 0 D5 0 0 0 D3 0 0 0 D2 0 0 0 D0 0 0 0 0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map Address 0x00B8 0x00B9 0x00BA 0x00B8 0x00B9 0x00BA Name SCI2BDH1 SCI2BDL1 SCI2CR11 SCI2ASR12 SCI2ACR12 SCI2ACR22 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE BERRM1 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1319 Appendix G Detailed Register Map 0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map (continued) Address 0x00BB 0x00BC 0x00BD 0x00BE 0x00BF 1 2 Name SCI2CR2 SCI2SR1 SCI2SR2 SCI2DRH SCI2DRL R W R W R W R W R W Bit 7 TIE TDRE Bit 6 TCIE TC 0 Bit 5 RIE RDRF 0 0 R5 T5 Bit 4 ILIE IDLE Bit 3 TE OR Bit 2 RE NF Bit 1 RWU FE Bit 0 SBK PF RAF 0 R0 T0 AMAP R8 R7 T7 TXPOL 0 R4 T4 RXPOL 0 R3 T3 BRK13 0 R2 T2 TXDIR 0 R1 T1 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI2SR2 register is set to one 0x00C0–0x00C7 Asynchronous Serial Interface (SCI3) Map Address 0x00C0 0x00C1 0x00C2 0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5 0x00C6 0x00C7 1 2 Name SCI3BDH1 SCI3BDL1 SCI3CR11 SCI3ASR12 SCI3ACR12 SCI3ACR22 SCI3CR2 SCI3SR1 SCI3SR2 SCI3DRH SCI3DRL Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0 BERRM1 RE NF TCIE TC 0 RIE RDRF 0 0 R5 T5 ILIE IDLE TE OR TXPOL 0 R4 T4 RXPOL 0 R3 T3 BRK13 0 R2 T2 TXDIR 0 R1 T1 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI3SR2 register is set to one MC9S12XDP512 Data Sheet, Rev. 2.17 1320 Freescale Semiconductor Appendix G Detailed Register Map 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address 0x00C8 0x00C9 0x00CA 0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00CE 0x00CF 1 2 Name SCI0BDH1 SCI0BDL1 SCI0CR11 SCI0ASR12 SCI0ACR12 SCI0ACR22 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0 BERRM1 RE NF TCIE TC 0 RIE RDRF 0 0 R5 T5 ILIE IDLE TE OR TXPOL 0 R4 T4 RXPOL 0 R3 T3 BRK13 0 R2 T2 TXDIR 0 R1 T1 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map Address 0x00D0 0x00D1 0x00D2 0x00D0 0x00D1 0x00D2 0x00D3 0x00D4 Name SCI1BDH1 SCI1BDL1 SCI1CR11 SCI1ASR12 SCI1ACR12 SCI1ACR22 SCI1CR2 SCI1SR1 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF BERRM1 RE NF TCIE TC RIE RDRF ILIE IDLE TE OR MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1321 Appendix G Detailed Register Map 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address 0x00D5 0x00D6 0x00D7 1 2 Name SCI1SR2 SCI1DRH SCI1DRL R W R W R W Bit 7 AMAP R8 R7 T7 Bit 6 0 Bit 5 0 0 R5 T5 Bit 4 TXPOL 0 R4 T4 Bit 3 RXPOL 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one 0x00D8–0x00DF Serial Peripheral Interface (SPI0) Map Address 0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE 0x00DF Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 SPIE 0 0 SPIF 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF 0 Bit 3 CPOL BIDIROE 0 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 SPPR2 0 0 SPPR1 SPTEF 0 SPR2 0 0 Bit7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit0 0 0 0x00E0–0x00E7 Inter IC Bus (IIC0) Map Address 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 Name IBAD IBFD IBCR IBSR IBDR R W R W R W R W R W Bit 7 ADR7 IBC7 IBEN TCF Bit 6 ADR6 IBC6 IBIE IAAS Bit 5 ADR5 IBC5 MS/SL IBB Bit 4 ADR4 IBC4 TX/RX IBAL D4 Bit 3 ADR3 IBC3 TXAK 0 Bit 2 ADR2 IBC2 0 RSTA SRW Bit 1 ADR1 IBC1 0 Bit 0 0 IBC0 IBSWAI RXAK IBIF D1 D7 D6 D5 D3 D2 D0 MC9S12XDP512 Data Sheet, Rev. 2.17 1322 Freescale Semiconductor Appendix G Detailed Register Map 0x00E0–0x00E7 Inter IC Bus (IIC0) Map (continued) Address 0x00E5 0x00E6 0x00E7 Name Reserved Reserved Reserved R W R W R W Bit 7 0 0 0 Bit 6 0 0 0 Bit 5 0 0 0 Bit 4 0 0 0 Bit 3 0 0 0 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0 0x00E8–0x00EF Reserved Address 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 0x00F0–0x00F7 Serial Peripheral Interface (SPI1) Map Address 0x00F0 0x00F1 0x00F2 0x00F3 0x00F4 0x00F5 0x00F6 0x00F7 Name SPI1CR1 SPI1CR2 SPI1BR SPI1SR Reserved SPI1DR Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 SPIE 0 0 SPIF 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF 0 Bit 3 CPOL BIDIROE 0 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 SPPR2 0 0 SPPR1 SPTEF 0 SPR2 0 0 Bit7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit0 0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1323 Appendix G Detailed Register Map 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address 0x00F8 0x00F9 0x00FA 0x00FB 0x00FC 0x00FD 0x00FE 0x00FF Name SPI2CR1 SPI2CR2 SPI2BR SPI2SR Reserved SPI2DR Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 SPIE 0 0 SPIF 0 Bit 6 SPE 0 Bit 5 SPTIE 0 Bit 4 MSTR MODFEN SPPR0 MODF 0 Bit 3 CPOL BIDIROE 0 0 0 Bit 2 CPHA 0 Bit 1 SSOE SPISWAI SPR1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 SPPR2 0 0 SPPR1 SPTEF 0 SPR2 0 0 Bit7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit0 0 0 0x0100–0x010F Flash Control Register (FTX512K4) Map Address 0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B Name FCLKDIV FSEC FTSTMOD FCNFG FPROT FSTAT FCMD FCTL FADDRHI FADDRLO FDATAHI FDATALO Bit 7 R FDIVLD W R KEYEN1 W R 0 W R CBEIE W R FPOPEN W R CBEIF W R 0 W R NV7 W R W R W R W R W Bit 6 PRDIV8 KEYEN0 Bit 5 FDIV5 RNV5 Bit 4 FDIV4 RNV4 Bit 3 FDIV3 RNV3 0 0 Bit 2 FDIV2 RNV2 0 0 Bit 1 FDIV1 SEC1 0 0 Bit 0 FDIV0 SEC0 0 0 MRDS CCIE RNV6 CCIF KEYACC FPHDIS PVIOL WRALL 0 FPHS1 ACCERR FPHS0 0 FPLDIS BLANK FPLS1 0 FPLS0 0 CMDB[6:0] NV6 NV5 NV4 NV3 NV2 NV1 NV0 FADDRHI FADDRLO FDATAHI FDATALO MC9S12XDP512 Data Sheet, Rev. 2.17 1324 Freescale Semiconductor Appendix G Detailed Register Map 0x0100–0x010F Flash Control Register (FTX512K4) Map (continued) Address 0x010C 0x010D 0x010E 0x010F Name Reserved Reserved Reserved Reserved R W R W R W R W Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 0 0 Bit 2 0 0 0 0 Bit 1 0 0 0 0 Bit 0 0 0 0 0 0x0110–0x011B EEPROM Control Register (EETX4K) Map Address 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011A 0x011B Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT ECMD Reserved EADDRHI EADDRLO EDATAHI EDATALO Bit 7 R EDIVLD W R 0 W R 0 W R CBEIE W R EPOPEN W R CBEIF W R 0 W R 0 W R 0 W R W R W R W Bit 6 PRDIV8 0 0 Bit 5 EDIV5 0 0 0 RNV5 Bit 4 EDIV4 0 0 0 RNV4 Bit 3 EDIV3 0 0 0 Bit 2 EDIV2 0 0 0 Bit 1 EDIV1 0 0 0 Bit 0 EDIV0 0 0 0 CCIE RNV6 CCIF EPDIS 0 EPS2 BLANK EPS1 0 EPS0 0 PVIOL ACCERR CMDB[6:0] 0 0 0 0 0 0 EABLO EDHI EDLO 0 0 0 0 EABHI 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1325 Appendix G Detailed Register Map 0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4 Address 0x011C 0x011D 0x011E 0x011F Name RAMWPC RAMXGU RAMSHL RAMSHU R W R W R W R W Bit 7 RPWE 1 1 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 AVIE XGU1 SHL1 SHU1 Bit 0 AVIF XGU0 SHL0 SHU0 XGU6 SHL6 SHU6 XGU5 SHL5 SHU5 XGU4 SHL4 SHU4 XGU3 SHL3 SHU3 XGU2 SHL2 SHU2 0x0120–0x012F Interrupt Module (S12XINT) Map Address 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 Name Reserved IVBR Reserved Reserved Reserved Reserved INT_XGPRIO INT_CFADDR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 IVB_ADDR[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XILVL[2:0] 0 0 INT_CFADDR[7:4] RQST RQST RQST RQST RQST RQST RQST RQST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0128 INT_CFDATA0 0x0129 INT_CFDATA1 0x012A INT_CFDATA2 0x012B INT_CFDATA3 0x012C INT_CFDATA4 0x012D INT_CFDATA5 0x012E INT_CFDATA6 0x012F INT_CFDATA7 PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] PRIOLVL[2:0] MC9S12XDP512 Data Sheet, Rev. 2.17 1326 Freescale Semiconductor Appendix G Detailed Register Map 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address 0x0130 0x0131 0x0132 0x0130 0x0131 0x0132 0x0133 0x0134 0x0135 0x0136 0x0137 1 2 Name SCI4BDH1 SCI4BDL1 SCI4CR11 SCI4ASR12 SCI4ACR12 SCI4ACR22 SCI4CR2 SCI4SR1 SCI4SR2 SCI4DRH SCI4DRL Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF RAF 0 R0 T0 BERRM1 RE NF TCIE TC 0 RIE RDRF 0 0 R5 T5 ILIE IDLE TE OR TXPOL 0 R4 T4 RXPOL 0 R3 T3 BRK13 0 R2 T2 TXDIR 0 R1 T1 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI4SR2 register is set to one 0x0138–0x013F Asynchronous Serial Interface (SCI5) Map Address 0x0138 0x0139 0x013A 0x0138 0x0139 0x013A 0x013B 0x013C Name SCI5BDH1 SCI5BDL1 SCI5CR11 SCI5ASR12 SCI5ACR12 SCI5ACR22 SCI5CR2 SCI5SR1 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W Bit 6 TNP1 SBR6 SCISWAI 0 0 0 Bit 5 TNP0 SBR5 RSRC 0 0 0 Bit 4 SBR12 SBR4 M 0 0 0 Bit 3 SBR11 SBR3 WAKE 0 0 0 Bit 2 SBR10 SBR2 ILT BERRV 0 Bit 1 SBR9 SBR1 PE BERRIF BERRIE BERRM0 RWU FE Bit 0 SBR8 SBR0 PT BKDIF BKDIE BKDFE SBK PF BERRM1 RE NF TCIE TC RIE RDRF ILIE IDLE TE OR MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1327 Appendix G Detailed Register Map 0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued) Address 0x013D 0x013E 0x013F 1 2 Name SCI5SR2 SCI5DRH SCI5DRL R W R W R W Bit 7 AMAP R8 R7 T7 Bit 6 0 Bit 5 0 0 R5 T5 Bit 4 TXPOL 0 R4 T4 Bit 3 RXPOL 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0 T8 R6 T6 Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI5SR2 register is set to one 0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map Address 0x0140 0x0141 0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 0x0148 0x0149 0x014A 0x014B 0x014C 0x014D 0x014E 0x014F Name CAN0CTL0 Bit 7 Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK R RXFRM W R CAN0CTL1 CANE W R CAN0BTR0 SJW1 W R CAN0BTR1 SAMP W R CAN0RFLG WUPIF W R CAN0RIER WUPIE W R 0 CAN0TFLG W R 0 CAN0TIER W R 0 CAN0TARQ W R 0 CAN0TAAK W R 0 CAN0TBSEL W R 0 CAN0IDAC W R 0 Reserved W R 0 CAN0MISC W R RXERR7 CAN0RXERR W R TXERR7 CAN0TXERR W CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 LISTEN BRP4 TSEG20 RSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 RSTATE1 0 0 0 0 0 RSTATE0 0 0 0 0 0 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 TX1 IDHIT1 0 0 RXERR1 TXERR1 TX0 IDHIT0 0 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 BOHOLD RXERR0 TXERR0 MC9S12XDP512 Data Sheet, Rev. 2.17 1328 Freescale Semiconductor Appendix G Detailed Register Map 0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued) Address Name R W R W R W R W R CAN0RXFG W R W Bit 7 AC7 AM7 AC7 AM7 Bit 6 AC6 AM6 AC6 AM6 Bit 5 AC5 AM5 AC5 AM5 Bit 4 AC4 AM4 AC4 AM4 Bit 3 AC3 AM3 AC3 AM3 Bit 2 AC2 AM2 AC2 AM2 Bit 1 AC1 AM1 AC1 AM1 Bit 0 AC0 AM0 AC0 AM0 0x0150– CAN0IDAR0– 0x0153 CAN0IDAR3 0x0154– CAN0IDMR0– 0x0157 CAN0IDMR3 0x0158– CAN0IDAR4– 0x015B CAN0IDAR7 0x015C CAN0IDMR4– – CAN0IDMR7 0x015F 0x0160– 0x016F 0x0170– 0x017F FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) CAN0TXFG Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address 0xXXX0 Name R R W R R W R R W R R W R CANxRDSR0– CANxRDSR7 W CANRxDLR Extended ID Standard ID CANxRIDR0 Extended ID Standard ID CANxRIDR1 Extended ID Standard ID CANxRIDR2 Extended ID Standard ID CANxRIDR3 Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15 0xXXX1 ID9 ID8 ID7 0xXXX2 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR 0xXXX3 0xXXX4 – 0xXXXB 0xXXXC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R W R 0xXXXD Reserved W R 0xXXXE CANxRTSRH W R 0xXXXF CANxRTSRL W Extended ID R CANxTIDR0 W 0xXX10 Standard ID R W DLC3 DLC2 DLC1 DLC0 TSR15 TSR7 TSR14 TSR6 TSR13 TSR5 TSR12 TSR4 TSR11 TSR3 TSR10 TSR2 TSR9 TSR1 TSR8 TSR0 ID28 ID10 ID27 ID9 ID26 ID8 ID25 ID7 ID24 ID6 ID23 ID5 ID22 ID4 ID21 ID3 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1329 Appendix G Detailed Register Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address 0xXX0x XX10 Name R W R W Extended ID R CANxTIDR2 W Standard ID R W Extended ID R CANxTIDR3 W Standard ID R W R CANxTDSR0– CANxTDSR7 W R W R CANxTTBPR W R CANxTTSRH W R CANxTTSRL W CANxTDLR Extended ID CANxTIDR1 Standard ID Bit 7 ID20 ID2 ID14 Bit 6 ID19 ID1 ID13 Bit 5 ID18 ID0 ID12 Bit 4 SRR=1 RTR ID11 Bit 3 IDE=1 IDE=0 ID10 ID9 ID8 ID7 Bit 2 ID17 Bit 1 ID16 Bit 0 ID15 0xXX12 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR 0xXX13 0xXX14 – 0xXX1B 0xXX1C 0xXX1D 0xXX1E 0xXX1F DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 PRIO2 TSR10 TSR2 DB1 DLC1 PRIO1 TSR9 TSR1 DB0 DLC0 PRIO0 TSR8 TSR0 PRIO7 TSR15 TSR7 PRIO6 TSR14 TSR6 PRIO5 TSR13 TSR5 PRIO4 TSR12 TSR4 PRIO3 TSR11 TSR3 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 1 of 3) Address 0x0180 0x0181 0x0182 0x0183 0x0184 0x0185 0x0186 0x0187 0x0188 Name CAN1CTL0 CAN1CTL1 CAN1BTR0 CAN1BTR1 CAN1RFLG CAN1RIER CAN1TFLG CAN1TIER CAN1TARQ Bit 7 R RXFRM W R CANE W R SJW1 W R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W R 0 W Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 LISTEN BRP4 TSEG20 RSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 RSTATE1 0 0 0 RSTATE0 0 0 0 TSTATE1 0 0 0 TSTATE0 TXE2 TXEIE2 ABTRQ2 MC9S12XDP512 Data Sheet, Rev. 2.17 1330 Freescale Semiconductor Appendix G Detailed Register Map 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 2 of 3) Address 0x0189 0x018A 0x018B 0x018C 0x018D 0x018E 0x018F 0x0190 0x0191 0x0192 0x0193 0x0194 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E Name CAN1TAAK CAN1TBSEL CAN1IDAC Reserved CAN1MISC CAN1RXERR CAN1TXERR CAN1IDAR0 CAN1IDAR1 CAN1IDAR2 CAN1IDAR3 CAN1IDMR0 CAN1IDMR1 CAN1IDMR2 CAN1IDMR3 CAN1IDAR4 CAN1IDAR5 CAN1IDAR6 CAN1IDAR7 CAN1IDMR4 CAN1IDMR5 CAN1IDMR6 Bit 7 R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W R AM7 W R AM7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W R AM7 W Bit 6 0 0 0 0 0 RXERR6 TXERR6 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 0 0 0 RXERR3 TXERR3 Bit 2 ABTAK2 Bit 1 ABTAK1 Bit 0 ABTAK0 TX2 IDHIT2 0 0 RXERR2 TXERR2 TX1 IDHIT1 0 0 RXERR1 TXERR1 TX0 IDHIT0 0 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 BOHOLD RXERR0 TXERR0 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1331 Appendix G Detailed Register Map 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 3 of 3) Address Name Bit 7 AM7 Bit 6 AM6 Bit 5 AM5 Bit 4 AM4 Bit 3 AM3 Bit 2 AM2 Bit 1 AM1 Bit 0 AM0 R 0x019F CAN1IDMR7 W R 0x01A0– CAN1RXFG 0x01AF W R 0x01B0– CAN1TXFG 0x01BF W FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) 0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map Address 0x01C0 0x01C1 0x01C2 0x01C3 0x01C4 0x01C5 0x01C6 0x01C7 0x01C8 0x01C9 0x01CA 0x01CB 0x01CC 0x01CD 0x01CE 0x01CF 0x01D0 Name Bit 7 Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK R CAN2CTL0 RXFRM W R CAN2CTL1 CANE W R CAN2BTR0 SJW1 W R CAN2BTR1 SAMP W R CAN2RFLG WUPIF W R CAN2RIER WUPIE W R 0 CAN2TFLG W R 0 CAN2TIER W R 0 CAN2TARQ W R 0 CAN2TAAK W R 0 CAN2TBSEL W R 0 CAN2IDAC W R 0 Reserved W R 0 CAN2MISC W R RXERR7 CAN2RXERR W R TXERR7 CAN2TXERR W R CAN2IDAR0 AC7 W CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 LISTEN BRP4 TSEG20 RSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 RSTATE1 0 0 0 0 0 RSTATE0 0 0 0 0 0 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 TX1 IDHIT1 0 0 RXERR1 TXERR1 TX0 IDHIT0 0 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 BOHOLD RXERR0 TXERR0 AC6 AC5 AC4 AC3 AC2 AC1 AC0 MC9S12XDP512 Data Sheet, Rev. 2.17 1332 Freescale Semiconductor Appendix G Detailed Register Map 0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map (continued) Address 0x01D1 0x01D2 0x01D3 0x01D4 0x01D5 0x01D6 0x01D7 0x01D8 0x01D9 0x01DA 0x01DB 0x01DC 0x01DD 0x01DE 0x01DF 0x01E0– 0x01EF 0x01F0– 0x01FF Name CAN2IDAR1 CAN2IDAR2 CAN2IDAR3 CAN2IDMR0 CAN2IDMR1 CAN2IDMR2 CAN2IDMR3 CAN2IDAR4 CAN2IDAR5 CAN2IDAR6 CAN2IDAR7 CAN2IDMR4 CAN2IDMR5 CAN2IDMR6 CAN2IDMR7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 CAN2RXFG FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) CAN2TXFG MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1333 Appendix G Detailed Register Map 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) Address 0x0200 0x0201 0x0202 0x0203 0x0204 0x0205 0x0206 0x0207 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 Name CAN3CTL0 CAN3CTL1 CAN3BTR0 CAN3BTR1 CAN3RFLG CAN3RIER CAN3TFLG CAN3TIER CAN3TARQ CAN3TAAK CAN3TBSEL CAN3IDAC Reserved Reserved CAN3RXERR CAN3TXERR CAN3IDAR0 CAN3IDAR1 CAN3IDAR2 CAN3IDAR3 CAN3IDMR0 CAN3IDMR1 Bit 7 R RXFRM W R CANE W R SJW1 W R SAMP W R WUPIF W R WUPIE W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 0 RXERR6 TXERR6 LISTEN BRP4 TSEG20 RSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 RSTATE1 0 0 0 0 0 RSTATE0 0 0 0 0 0 TSTATE1 0 0 0 0 0 0 0 0 RXERR3 TXERR3 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 0 RXERR2 TXERR2 TX1 IDHIT1 0 0 RXERR1 TXERR1 TX0 IDHIT0 0 IDAM1 0 0 RXERR5 TXERR5 IDAM0 0 0 RXERR4 TXERR4 BOHOLD RXERR0 TXERR0 AC6 AC6 AC6 AC6 AM6 AM6 AC5 AC5 AC5 AC5 AM5 AM5 AC4 AC4 AC4 AC4 AM4 AM4 AC3 AC3 AC3 AC3 AM3 AM3 AC2 AC2 AC2 AC2 AM2 AM2 AC1 AC1 AC1 AC1 AM1 AM1 AC0 AC0 AC0 AC0 AM0 AM0 MC9S12XDP512 Data Sheet, Rev. 2.17 1334 Freescale Semiconductor Appendix G Detailed Register Map 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) (continued) Address 0x0216 0x0217 0x0218 0x0219 0x021A 0x021B 0x021C 0x021D 0x021E 0x021F 0x0220– 0x022F 0x0230– 0x023F Name CAN3IDMR2 CAN3IDMR3 CAN3IDAR4 CAN3IDAR5 CAN3IDAR6 CAN3IDAR7 CAN3IDMR4 CAN3IDMR5 CAN3IDMR6 CAN3IDMR7 R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 AM7 AM7 AC7 AC7 AC7 AC7 AM7 AM7 AM7 AM7 Bit 6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 Bit 5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 Bit 4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 Bit 3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 Bit 2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 Bit 1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 Bit 0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 CAN3RXFG FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) CAN3TXFG 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 1 of 4) Address 0x0240 0x0241 0x0242 0x0243 0x0244 0x0245 0x0246 0x0247 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved R W R W R W R W R W R W R W R W Bit 7 PTT7 PTIT7 Bit 6 PTT6 PTIT6 Bit 5 PTT5 PTIT5 Bit 4 PTT4 PTIT4 Bit 3 PTT3 PTIT3 Bit 2 PTT2 PTIT2 Bit 1 PTT1 PTIT1 Bit 0 PTT0 PTIT0 DDRT7 RDRT7 PERT7 PPST7 0 0 DDRT7 RDRT6 PERT6 PPST6 0 0 DDRT5 RDRT5 PERT5 PPST5 0 0 DDRT4 RDRT4 PERT4 PPST4 0 0 DDRT3 RDRT3 PERT3 PPST3 0 0 DDRT2 RDRT2 PERT2 PPST2 0 0 DDRT1 RDRT1 PERT1 PPST1 0 0 DDRT0 RDRT0 PERT0 PPST0 0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1335 Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 2 of 4) Address 0x0248 0x0249 0x024A 0x024B 0x024C 0x024D 0x024E 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F Name PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PTS7 PTIS7 Bit 6 PTS6 PTIS6 Bit 5 PTS5 PTIS5 Bit 4 PTS4 PTIS4 Bit 3 PTS3 PTIS3 Bit 2 PTS2 PTIS2 Bit 1 PTS1 PTIS1 Bit 0 PTS0 PTIS0 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM7 PTIM7 PTM6 PTIM6 PTM5 PTIM5 PTM4 PTIM4 PTM3 PTIM3 PTM2 PTIM2 PTM1 PTIM1 PTM0 PTIM0 DDRM7 RDRM7 PERM7 PPSM7 WOMM7 0 DDRM7 RDRM6 PERM6 PPSM6 WOMM6 MODRR6 PTP6 PTIP6 DDRM5 RDRM5 PERM5 PPSM5 WOMM5 MODRR5 PTP5 PTIP5 DDRM4 RDRM4 PERM4 PPSM4 WOMM4 MODRR4 PTP4 PTIP4 DDRM3 RDRM3 PERM3 PPSM3 WOMM3 MODRR3 PTP3 PTIP3 DDRM2 RDRM2 PERM2 PPSM2 WOMM2 MODRR2 PTP2 PTIP2 DDRM1 RDRM1 PERM1 PPSM1 WOMM1 MODRR1 PTP1 PTIP1 DDRM0 RDRM0 PERM0 PPSM0 WOMM0 MODRR0 PTP0 PTIP0 PTP7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 MC9S12XDP512 Data Sheet, Rev. 2.17 1336 Freescale Semiconductor Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 3 of 4) Address 0x0260 0x0261 0x0262 0x0263 0x0264 0x0265 0x0266 0x0267 0x0268 0x0269 0x026A 0x026B 0x026C 0x026D 0x026E 0x026F 0x0270 0x0271 0x0272 0x0273 0x0274 0x0275 0x0276 0x0277 Name PTH PTIH DDRH RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved PT1AD0 Reserved DDR1AD0 Reserved RDR1AD0 Reserved PER1AD0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PTH7 PTIH7 Bit 6 PTH6 PTIH6 Bit 5 PTH5 PTIH5 Bit 4 PTH4 PTIH4 Bit 3 PTH3 PTIH3 Bit 2 PTH2 PTIH2 Bit 1 PTH1 PTIH1 Bit 0 PTH0 PTIH0 DDRH7 RDRH7 PERH7 PPSH7 PIEH7 PIFH7 PTJ7 PTIJ7 DDRH7 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRH5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 PTJ5 PTIJ5 DDRH4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 PTJ4 PTIJ4 DDRH3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0 0 DDRH2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 PTJ2 PTIJ2 DDRH1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRH0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ7 RDRJ7 PERJ7 PPSJ7 PIEJ7 PIFJ7 0 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 0 DDRJ5 RDRJ5 PERJ5 PPSJ5 PIEJ5 PIFJ5 0 DDRJ4 RDRJ4 PERJ4 PPSJ4 PIEJ4 PIFJ4 0 DDRJ2 RDRJ2 PERJ2 PPSJ2 PIEJ2 PIFJ2 0 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 0 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 0 PT1AD07 0 PT1AD06 0 PT1AD05 0 PT1AD04 0 PT1AD03 0 PT1AD02 0 PT1AD01 0 PT1AD00 0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 DDR1AD0 7 6 5 4 3 2 1 1 0 0 0 0 0 0 0 0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 RDR1AD0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 PER1AD0 7 6 5 4 3 2 1 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1337 Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 4 of 4) Address 0x0278 0x0279 0x027A 0x027B 0x027C 0x027D 0x027E 0x027F Name PT0AD1 PT1AD1 DDR0AD1 DDR1AD1 RDR0AD1 RDR1AD1 PER0AD1 PER1AD1 R W R W R W R W R W R W R W R W Bit 7 PT0AD1 23 PT1AD1 15 Bit 6 PT0AD1 22 PT1AD1 14 Bit 5 PT0AD1 21 PT1AD1 13 Bit 4 PT0AD1 20 PT1AD1 12 Bit 3 PT0AD1 19 PT1AD1 11 Bit 2 PT0AD1 18 PT1AD1 10 Bit 1 PT0AD1 17 PT1AD1 9 Bit 0 PT0AD1 16 PT1AD1 8 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 DDR0AD1 23 22 21 20 19 18 17 16 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 DDR1AD1 15 14 13 12 11 10 9 8 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 RDR0AD1 23 22 21 20 19 18 17 16 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 RDR1AD1 15 14 13 12 11 10 9 8 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 PER0AD1 23 22 21 20 19 18 17 16 PER1AD1 PER1AD1 PER1AD1 PER1AD1 PER1AD1 PER1A1D PER1AD1 PER1AD1 15 14 13 12 11 10 9 8 0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map Address 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A 0x028B 0x028C Name Bit 7 Bit 6 RXACT Bit 5 CSWAI LOOPB BRP5 TSEG21 RSTAT1 Bit 4 SYNCH Bit 3 TIME BORM BRP3 TSEG13 TSTAT1 Bit 2 WUPE WUPM BRP2 TSEG12 TSTAT0 Bit 1 SLPRQ SLPAK Bit 0 INITRQ INITAK R CAN4CTL0 RXFRM W R CAN4CTL1 CANE W R CAN4BTR0 SJW1 W R CAN4BTR1 SAMP W R CAN4RFLG WUPIF W R CAN4RIER WUPIE W R 0 CAN4TFLG W R 0 CAN4TIER W R 0 CAN4TARQ W R 0 CAN4TAAK W R 0 CAN4TBSEL W R 0 CAN4IDAC W R 0 Reserved W CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0 LISTEN BRP4 TSEG20 RSTAT0 BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1 BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0 RSTATE1 0 0 0 0 0 RSTATE0 0 0 0 0 0 TSTATE1 0 0 0 0 0 0 0 TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2 TX2 IDHIT2 0 TX1 IDHIT1 0 TX0 IDHIT0 0 IDAM1 0 IDAM0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1338 Freescale Semiconductor Appendix G Detailed Register Map 0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map (continued) Address 0x028D 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F 0x02A0– 0x02AF 0x02B0– 0x02BF Name CAN4MISC CAN4RXERR CAN4TXERR CAN4IDAR0 CAN4IDAR1 CAN4IDAR2 CAN4IDAR3 CAN4IDMR0 CAN4IDMR1 CAN4IDMR2 CAN4IDMR3 CAN4IDAR4 CAN4IDAR5 CAN4IDAR6 CAN4IDAR7 CAN4IDMR4 CAN4IDMR5 CAN4IDMR6 CAN4IDMR7 Bit 7 R 0 W R RXERR7 W R TXERR7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W R AM7 W R AM7 W R AC7 W R AC7 W R AC7 W R AC7 W R AM7 W R AM7 W R AM7 W R AM7 W R W R W Bit 6 0 RXERR6 TXERR6 Bit 5 0 RXERR5 TXERR5 Bit 4 0 RXERR4 TXERR4 Bit 3 0 RXERR3 TXERR3 Bit 2 0 RXERR2 TXERR2 Bit 1 0 RXERR1 TXERR1 Bit 0 BOHOLD RXERR0 TXERR0 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC6 AC6 AC6 AC6 AM6 AM6 AM6 AM6 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC5 AC5 AC5 AC5 AM5 AM5 AM5 AM5 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC4 AC4 AC4 AC4 AM4 AM4 AM4 AM4 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC3 AC3 AC3 AC3 AM3 AM3 AM3 AM3 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC2 AC2 AC2 AC2 AM2 AM2 AM2 AM2 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC1 AC1 AC1 AC1 AM1 AM1 AM1 AM1 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 AC0 AC0 AC0 AC0 AM0 AM0 AM0 AM0 CAN4RXFG FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) CAN4TXFG MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1339 Appendix G Detailed Register Map 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map Address 0x02C0 0x02C1 0x02C2 0x02C3 0x02C4 0x02C5 0x02C6 0x02C7 0x02C8 0x02C9 0x02CA 0x02CB 0x02CC 0x02CD 0x02CE 0x02CF 0x02D0 0x02D1 0x02D2 0x02D3 0x02D4 0x02D5 Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved ATD0PTAD0 ATD0DR0H ATD0DR0L ATD0DR1H ATD0DR1L ATD0DR2H ATD0DR2L R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 ETRIG SEL ADPU 0 Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 WRAP2 ETRIG CH2 ETRIGE FIFO PRS2 CC CC2 U U 0 0 CCF2 0 Bit 1 WRAP1 ETRIG CH1 ASCIE FRZ1 PRS1 CB CC1 U U 0 0 CCF1 0 Bit 0 WRAP0 ETRIG CH0 ASCIF AFFC S8C SMP1 DSGN 0 U U U 0 CCF6 0 AWAI S4C SMP0 SCAN ETORF U U 0 0 CCF5 0 ETRIGLE S2C PRS4 MULT FIFOR U U 0 0 CCF4 0 ETRIGP S1C PRS3 0 0 U U 0 0 CCF3 0 FRZ0 PRS0 CA CC0 U U SRES8 DJM SCF U U U 0 CCF7 0 SC 0 CCF0 0 IEN7 0 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 IEN6 0 6 14 Bit6 14 Bit6 14 Bit6 IEN5 0 5 13 0 13 0 13 0 IEN4 0 4 12 0 12 0 12 0 IEN3 0 3 11 0 11 0 11 0 IEN2 0 2 10 0 10 0 10 0 IEN1 0 1 9 0 9 0 9 0 IEN0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1340 Freescale Semiconductor Appendix G Detailed Register Map 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map (continued) Address 0x02D6 0x02D7 0x02D8 0x02D9 0x02DA 0x02DB 0x02DC 0x02DD 0x02DE 0x02DF Name ATD0DR3H ATD0DR3L ATD0DR4H ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H ATD0DR6L ATD0DR7H ATD0DR7L R W R W R W R W R W R W R W R W R W R W Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 13 0 13 0 13 0 Bit 4 12 0 12 0 12 0 12 0 12 0 Bit 3 11 0 11 0 11 0 11 0 11 0 Bit 2 10 0 10 0 10 0 10 0 10 0 Bit 1 9 0 9 0 9 0 9 0 9 0 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 0x02E0–0x02EF Reserved Address 0x02E0– 0x02EF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x02F0–0x02F7 Voltage Regulator (VREG_3V3) Map Address 0x02F0 0x02F1 0x02F2 0x02F3 0x02F4 0x02F5 0x02F6 0x02F7 Name VREGHTCL VREGCTRL VREGAPICL VREGAPITR VREGAPIRH VREGAPIRL Reserved Reserved Bit 7 R W R 0 W R APICLK W R APITR5 W R 0 W R APIR7 W R 0 W R 0 W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved for Factory Test 0 0 0 0 0 0 0 0 LVDS LVIE APIE 0 LVIF APIF 0 APIFE APITR0 APIR10 APIR2 0 0 APITR4 0 APITR3 0 APITR2 0 APITR1 APIR11 APIR3 0 0 APIR9 APIR1 0 0 APIR8 APIR0 0 0 APIR6 0 0 APIR5 0 0 APIR4 0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1341 Appendix G Detailed Register Map 0x02F8–0x02FF Reserved Address 0x02F8– 0x02FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 Name PWME Bit 7 Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 Bit 3 PWME3 PPOL3 PCLK3 0 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 PWMTST Test Only W R 0 PWMPRSC W R PWMSCLA Bit 7 W R PWMSCLB Bit 7 W R 0 PWMSCNTA W R 0 PWMSCNTB W R Bit 7 PWMCNT0 W 0 R Bit 7 PWMCNT1 W 0 R Bit 7 PWMCNT2 W 0 R Bit 7 PWMCNT3 W 0 R Bit 7 PWMCNT4 W 0 R Bit 7 PWMCNT5 W 0 R Bit 7 PWMCNT6 W 0 R Bit 7 PWMCNT7 W 0 CAE3 PSWAI 0 0 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 1342 Freescale Semiconductor Appendix G Detailed Register Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address 0x0314 0x0315 0x0316 0x0317 0x0318 0x0319 0x031A 0x031B 0x031C 0x031D 0x031E 0x031F 0x0320 0x0321 0x0322 0x0323 Name PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMPER6 PWMPER7 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMDTY6 PWMDTY7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 0 PWM RSTRT 0 0 0 Bit 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 PWMLVL 0 0 0 0 0 0 0 0 0 Bit 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PWM7IN PWM7INL 0 0 0 Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PWM7 ENA 0 0 0 0x0324 PWMSDN PWMIF 0 0 0 PWMIE 0 0 0 0x0325 0x0326 0x0327 Reserved Reserved Reserved MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1343 Appendix G Detailed Register Map 0x0328–0x033F Reserved Address 0x0328– 0x033F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map Address 0x0340 0x0341 0x0342 0x0343 0x0344 0x0345 0x0346 0x0347 0x0348 0x0349 0x034A 0x034B 0x034C 0x034D 0x034E 0x034F 0x0350 0x0351 0x0352 0x0353 Name PITCFLMT PITFLT PITCE PITMUX PITINTE PITTF PITMTLD0 PITMTLD1 PITLD0 (hi) PITLD0 (lo) PITCNT0 (hi) PITCNT0 (lo) PITLD1 (hi) PITLD1 (lo) PITCNT1 (hi) PITCNT1 (lo) PITLD2 (hi) PITLD2 (lo) PITCNT2 (hi) PITCNT2 (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 PITE 0 0 0 0 0 Bit 6 PITSWAI 0 0 0 0 0 Bit 5 PITFRZ 0 0 0 0 0 0 Bit 4 0 0 0 0 Bit 3 0 0 PFLT3 PCE3 PMUX3 PINTE3 PTF3 PMTLD3 PMTLD3 PLD11 PLD3 PCNT11 PCNT3 PLD11 PLD3 PCNT11 PCNT3 PLD11 PLD3 PCNT11 PCNT3 Bit 2 0 0 PFLT2 PCE2 PMUX2 PINTE2 PTF2 PMTLD2 PMTLD2 PLD10 PLD2 PCNT10 PCNT2 PLD10 PLD2 PCNT10 PCNT2 PLD10 PLD2 PCNT10 PCNT2 Bit 1 0 PFLMT1 0 PFLT1 PCE1 PMUX1 PINTE1 PTF1 PMTLD1 PMTLD1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 PLD9 PLD1 PCNT9 PCNT1 Bit 0 0 PFLMT0 0 PFLT0 PCE0 PMUX0 PINTE0 PTF0 PMTLD0 PMTLD0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PLD8 PLD0 PCNT8 PCNT0 PMTLD7 PMTLD7 PLD15 PLD7 PCNT15 PCNT7 PLD15 PLD7 PCNT15 PCNT7 PLD15 PLD7 PCNT15 PCNT7 PMTLD6 PMTLD6 PLD14 PLD6 PCNT14 PCNT6 PLD14 PLD6 PCNT14 PCNT6 PLD14 PLD6 PCNT14 PCNT6 PMTLD5 PMTLD5 PLD13 PLD5 PCNT13 PCNT5 PLD13 PLD5 PCNT13 PCNT5 PLD13 PLD5 PCNT13 PCNT5 PMTLD4 PMTLD4 PLD12 PLD4 PCNT12 PCNT4 PLD12 PLD4 PCNT12 PCNT4 PLD12 PLD4 PCNT12 PCNT4 MC9S12XDP512 Data Sheet, Rev. 2.17 1344 Freescale Semiconductor Appendix G Detailed Register Map 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map (continued) Address Name Bit 7 Bit 6 PLD14 PLD6 PCNT14 PCNT6 0 Bit 5 PLD13 PLD5 PCNT13 PCNT5 0 Bit 4 PLD12 PLD4 PCNT12 PCNT4 0 Bit 3 PLD11 PLD3 PCNT11 PCNT3 0 Bit 2 PLD10 PLD2 PCNT10 PCNT2 0 Bit 1 PLD9 PLD1 PCNT9 PCNT1 0 Bit 0 PLD8 PLD0 PCNT8 PCNT0 0 R 0x0354 PITLD3 (hi) PLD15 W R 0x0355 PITLD3 (lo) PLD7 W R 0x0356 PITCNT3 (hi) PCNT15 W R 0x0357 PITCNT3 (lo) PCNT7 W R 0 0x0358– Reserved 0x0367 W 0x0368–0x037F Reserved Address 0x0368– 0x037F Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0x0380–0x03BF XGATE Map (Sheet 1 of 3) Address 0x0380 Name XGMCTL R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 XGEM XGE 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 XGFRZM XGFRZ Bit 5 0 XGDBGM XGDBG Bit 4 0 XGSSM XGSS Bit 3 0 XGFACTM XGFACT XGCHID[6:0] 0 0 00 0 0 0 0 0 0 0 0 0 0 Bit 2 0 Bit 1 0 XGS WEIFM XGSWEIF Bit 0 XGIEM 0x0381 0x0382 0x0383 0x0384 0x0385 0x0386 0x0387 0x0388 0x0389 0x038A 0x023B 0x023C XGMCTL XGCHID Reserved XGVBR XGVBR XGVBR XGVBR XGIF XGIF XGIF XGIF XGIF XGIE XGVBR[15:8] XGVBR[7:1] 0 0 0 0 0 0 0 0 XGIF_78 XGIF_70 XGIF_68 XGIF_60 XGIF_58 XGIF_77 XGIF_6F XGIF_67 XGIF_5F XGIF_76 XGIF_6E XGIF_66 XGIF_5E XGIF_75 XGIF_6D XGIF_65 XGIF_5D XGIF_74 XGIF_6C XGIF_64 XGIF_5C XGIF_73 XGIF_6B XGIF_63 XGIF_5B XGIF_72 XGIF_6A XGIF_62 XGIF_5A XGIF_71 XGIF_69 XGIF_61 XGIF_59 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1345 Appendix G Detailed Register Map 0x0380–0x03BF XGATE Map (Sheet 2 of 3) Address 0x038D 0x038E 0x038F 0x0390 0x0391 0x0392 0x0393 0x0394 0x0395 0x0396 0x0397 0x0398 0x0399 0x039A 0x039B 0x039C 0x039D 0x039E 0x039F 0x03A0 0x03A1 0x03A2 0x03A3 Name XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGIF XGSWT (hi) XGSWT (lo) XGSEM (hi) XGSEM (lo) Reserved XGCCR XGPC (hi) XGPC (lo) Reserved Reserved XGR1 (hi) XGR1 (lo) R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 XGIF_57 XGIF_4F XGIF_47 XGIF_3F XGIF_37 XGIF_2F XGIF_27 XGIF_1F XGIF_17 XGIF_0F 0 0 Bit 6 XGIF_56 XGIF_4E XGIF_46 XGIF_3E XGIF_36 XGIF_2E XGIF_26 XGIF_1E XGIF_16 XGIF_0E 0 0 Bit 5 XGIF_55 XGIF_4D XGIF_45 XGIF_3D XGIF_35 XGIF_2D XGIF_25 XGIF_1D XGIF_15 XGIF_0D 0 0 Bit 4 XGIF_54 XGIF_4C XGIF_44 XGIF_3C XGIF_34 XGIF_2C XGIF_24 XGIF_1C XGIF_14 XGIF_0C 0 Bit 3 XGIF_53 XGIF_4B XGIF_43 XGIF_3B XGIF_33 XGIF_2B XGIF_23 XGIF_1B XGIF_13 XGIF_0B 0 Bit 2 XGIF_52 XGIF_4A XGIF_42 XGIF_3A XGIF_32 XGIF_2A XGIF_22 XGIF_1A XGIF_12 XGIF_0A 0 0 Bit 1 XGIF_51 XGIF_49 XGIF_41 XGIF_39 XGIF_31 XGIF_29 XGIF_21 XGIF_19 XGIF_11 XGIF_09 0 0 Bit 0 XGIF_50 XGIF_48 XGIF_40 XGIF_38 XGIF_30 XGIF_28 XGIF_20 XGIF_18 XGIF_10 0 0 0 0 0 XGSWTM[7:0] XGSWT[7:0] 0 0 0 0 0 XGSEMM[7:0] XGSEM[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XGN XGZ XGV XGC XGPC[15:8] XGPC[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XGR1[15:8] XGR1[7:0] MC9S12XDP512 Data Sheet, Rev. 2.17 1346 Freescale Semiconductor Appendix G Detailed Register Map 0x0380–0x03BF XGATE Map (Sheet 3 of 3) Address 0x03A4 0x03A5 0x03A6 0x03A7 0x03A8 0x03A9 0x03AA 0x03AB 0x03AC 0x03AD 0x03AE 0x03AF 0x03B0– 0x03BF Name XGR2 (hi) XGR2 (lo) XGR3 (hi) XGR3 (lo) XGR4 (hi) XGR4 (lo) XGR5 (hi) XGR5(lo) XGR6 (hi) XGR6 (lo) XGR7 (hi) XGR7 (lo) Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XGR2[15:8] XGR2[7:0] XGR3[15:8] XGR3[7:0] XGR4[15:8] XGR4[7:0] XGR5[15:8] XGR5[7:0] XGR6[15:8] XGR6[7:0] XGR7[15:8] XGR7[7:0] 0 0 0 0 0 0 0 0 0x03C0–0x07FF Reserved Address 0x03C0 –0x07FF Name Reserved R W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 1347 Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.17 1348 Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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The Bluetooth trademarks are owned by their proprietor and used by Freescale Semiconductor, Inc. under license. © Freescale Semiconductor, Inc. 2005. All rights reserved. MC9S12XDP512 Rev. 2.17 July 2007