SC9RS08KA2 SC9RS08KA1
Data Sheet
RS08 Microcontrollers
SC9RS08KA2 Rev. 1 9/2009
freescale.com
SC9RS08KA2 Features
8-Bit RS08 Central Processor Unit (CPU) System Protection
•
• • •
Simplified S08 instruction set with added high-performance instructions — LDA, STA, and CLR instructions support the short addressing mode; address $0000 to $001F can be accessed via a single-byte instruction — ADD, SUB, INC, and DEC instructions support the tiny addressing mode; address $0000 to $000F can be accessed via a single-byte instruction with reduced instruction cycle — Shadow PC register instructions: SHA and SLA Pending interrupt indication Index addressing via D[X] and X register Direct page access to the entire memory map through paging window
• •
Computer operating properly (COP) reset running off bus-independent clock source Low-voltage detection with reset or stop wakeup
Peripherals
• •
•
MTIM — 8-bit modulo timer ACMP — Analog comparator — Full rail-to-rail supply operation — Option to compare to fixed internal bandgap reference voltage — Can operate in stop mode KBI — Keyboard interrupt ports — Three KBI ports in 6-pin package — Five KBI ports in 8-pin package
Development Support
Memory
•
•
On-chip Flash EEPROM — SC9RS08KA2: 2048 bytes — SC9RS08KA1: 1024 bytes 63 bytes on-chip RAM
• •
Background debug system Breakpoint capability to allow single breakpoint setting during in-circuit debug
Package Options
•
Power-Saving Modes
• •
Wait and stop Wakeup from power-saving modes using real-time interrupt (RTI), KBI, or ACMP
Clock Source
•
•
ICS — Trimmable 20-MHz internal clock source — Up to 10-MHz internal bus operation — 0.2% trimmable resolution, 2% deviation over temperature and voltage range
•
6-pin dual flat no lead (DFN) package — Two general-purpose input/output (I/O) pins — One general-purpose input pin — One general-purpose output pin 8-pin plastic dual in-line pin (PDIP) package — Four general-purpose input/output (I/O) pins — One general-purpose input pin — One general-purpose output pin 8-pin narrow body SOIC package — Four general-purpose input/output (I/O) pins — One general-purpose input pin — One general-purpose output pin
SC9RS08KA2 Series Data Sheet, Rev. 1 4 Freescale Semiconductor
SC9RS08KA2 Series Data Sheet
Covers: SC9RS08KA2 SC9RS08KA1
SC9RS08KA2 Rev. 1 9/2009
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document.
Revision Number 1.0 Revision Date 9/2009 Initial public release version
Description of Changes
This product incorporates SuperFlash® technology licensed from SST. Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
SC9RS08KA2 Series Data Sheet, Rev. 1 6 Freescale Semiconductor
List of Chapters
Chapter
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Appendix A Appendix B
List of Chapters
Title
Page
SC9RS08KA2 Series Device Overview .......................................... 15 Pins and Connections ..................................................................... 17 Modes of Operation ......................................................................... 21 Memory............................................................................................. 25 Resets, Interrupts, and General System Control.......................... 35 Parallel Input/Output Control ......................................................... 45 Keyboard Interrupt (RS08KBIV1) ................................................... 51 Central Processor Unit (RS08CPUV1) ........................................... 57 Internal Clock Source (RS08ICSV1)............................................... 75 Analog Comparator (RS08ACMPV1).............................................. 83 Modulo Timer (RS08MTIMV1) ......................................................... 89 Development Support ..................................................................... 97 Electrical Characteristics.............................................................. 109 Ordering Information and Mechanical Drawings........................ 123
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 7
Table of Contents
Section Number Title Page
Chapter 1 SC9RS08KA2 Series Device Overview
1.1 1.2 1.3 Overview .........................................................................................................................................15 MCU Block Diagram ......................................................................................................................15 System Clock Distribution ..............................................................................................................16
Chapter 2 Pins and Connections
2.1 2.2 2.3 2.4 Introduction .....................................................................................................................................17 Device Pin Assignment ...................................................................................................................17 Recommended System Connections ...............................................................................................18 Pin Detail .........................................................................................................................................18 2.4.1 Power ..............................................................................................................................19 2.4.2 PTA2/KBIP2/TCLK/RESET/VPP ........................................................................................................ 19 2.4.3 PTA3/ACMPO/BKGD/MS ............................................................................................19 2.4.4 General-Purpose I/O and Peripheral Ports .....................................................................20
Chapter 3 Modes of Operation
3.1 3.2 3.3 3.4 3.5 3.6 Introduction .....................................................................................................................................21 Features ...........................................................................................................................................21 Run Mode ........................................................................................................................................21 Active Background Mode ...............................................................................................................21 Wait Mode .......................................................................................................................................22 Stop Mode .......................................................................................................................................23 3.6.1 Active BDM Enabled in Stop Mode ..............................................................................24 3.6.2 LVD Enabled in Stop Mode ...........................................................................................24
Chapter 4 Memory
4.1 4.2 4.3 4.4 4.5 4.6 Memory Map ...................................................................................................................................25 Unimplemented Memory ................................................................................................................27 Indexed/Indirect Addressing ...........................................................................................................27 RAM and Register Addresses and Bit Assignments .......................................................................27 RAM ................................................................................................................................................29 Flash ................................................................................................................................................29 4.6.1 Features ...........................................................................................................................29 4.6.2 Flash Programming Procedure .......................................................................................30 4.6.3 Flash Mass Erase Operation ...........................................................................................30
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 9
Section Number
4.7 4.8
Title
Page
4.6.4 Security ...........................................................................................................................31 Flash Registers and Control Bits .....................................................................................................32 4.7.1 Flash Options Register (FOPT and NVOPT) .................................................................32 4.7.2 Flash Control Register (FLCR) ......................................................................................33 Page Select Register (PAGESEL) ...................................................................................................33
Chapter 5 Resets, Interrupts, and General System Control
5.1 5.2 5.3 5.4 5.5 5.6 Introduction .....................................................................................................................................35 Features ...........................................................................................................................................35 MCU Reset ......................................................................................................................................35 Computer Operating Properly (COP) Watchdog .............................................................................36 Interrupts .........................................................................................................................................36 Low-Voltage Detect (LVD) System ................................................................................................37 5.6.1 Power-On Reset Operation .............................................................................................37 5.6.2 LVD Reset Operation .....................................................................................................37 5.6.3 LVD Interrupt Operation ................................................................................................37 Real-Time Interrupt (RTI) ...............................................................................................................37 Reset, Interrupt, and System Control Registers and Control Bits ...................................................38 5.8.1 System Reset Status Register (SRS) ...............................................................................38 5.8.2 System Options Register (SOPT) ...................................................................................39 5.8.3 System Device Identification Register (SDIDH, SDIDL) .............................................40 5.8.4 System Real-Time Interrupt Status and Control Register (SRTISC) .............................41 5.8.5 System Power Management Status and Control 1 Register (SPMSC1) .........................43 5.8.6 System Interrupt Pending Register (SIP1) .....................................................................44
5.7 5.8
Chapter 6 Parallel Input/Output Control
6.1 6.2 6.3 Pin Behavior in Low-Power Modes ................................................................................................46 Parallel I/O Registers ......................................................................................................................46 6.2.1 Port A Registers ..............................................................................................................46 Pin Control Registers ......................................................................................................................47 6.3.1 Port A Pin Control Registers ..........................................................................................47 6.3.1.1 Internal Pulling Device Enable .......................................................................47 6.3.1.2 Pullup/Pulldown Control ................................................................................48 6.3.1.3 Output Slew Rate Control Enable ...................................................................48
Chapter 7 Keyboard Interrupt (RS08KBIV1)
7.1 Introduction .....................................................................................................................................51 7.1.1 Features ...........................................................................................................................51 7.1.2 Modes of Operation ........................................................................................................52 7.1.2.1 Operation in Wait Mode ..................................................................................52 7.1.2.2 Operation in Stop Mode ..................................................................................52 7.1.2.3 Operation in Active Background Mode ..........................................................52
SC9RS08KA2 Series Data Sheet, Rev. 1 10 Freescale Semiconductor
Section Number
7.2 7.3
Title
Page
7.4
7.1.3 Block Diagram ................................................................................................................52 External Signal Description ............................................................................................................52 Register Definition ..........................................................................................................................53 7.3.1 KBI Status and Control Register (KBISC) .....................................................................53 7.3.2 KBI Pin Enable Register (KBIPE) .................................................................................54 7.3.3 KBI Edge Select Register (KBIES) ................................................................................54 Functional Description ....................................................................................................................55 7.4.1 Edge Only Sensitivity .....................................................................................................55 7.4.2 Edge and Level Sensitivity .............................................................................................55 7.4.3 KBI Pullup/Pulldown Device .........................................................................................55 7.4.4 KBI Initialization ............................................................................................................55
Chapter 8 Central Processor Unit (RS08CPUV1)
8.1 8.2 Introduction .....................................................................................................................................57 Programmer’s Model and CPU Registers .......................................................................................57 8.2.1 Accumulator (A) .............................................................................................................58 8.2.2 Program Counter (PC) ....................................................................................................59 8.2.3 Shadow Program Counter (SPC) ....................................................................................59 8.2.4 Condition Code Register (CCR) .....................................................................................59 8.2.5 Indexed Data Register (D[X]) ........................................................................................60 8.2.6 Index Register (X) ..........................................................................................................60 8.2.7 Page Select Register (PAGESEL) ..................................................................................61 Addressing Modes ...........................................................................................................................61 8.3.1 Inherent Addressing Mode (INH) ..................................................................................61 8.3.2 Relative Addressing Mode (REL) ..................................................................................61 8.3.3 Immediate Addressing Mode (IMM) .............................................................................62 8.3.4 Tiny Addressing Mode (TNY) .......................................................................................62 8.3.5 Short Addressing Mode (SRT) .......................................................................................63 8.3.6 Direct Addressing Mode (DIR) ......................................................................................63 8.3.7 Extended Addressing Mode (EXT) ................................................................................63 8.3.8 Indexed Addressing Mode (IX, Implemented by Pseudo Instructions) .........................63 Special Operations ...........................................................................................................................63 8.4.1 Reset Sequence ...............................................................................................................64 8.4.2 Interrupts .........................................................................................................................64 8.4.3 Wait and Stop Mode .......................................................................................................64 8.4.4 Active Background Mode ...............................................................................................64 Summary Instruction Table .............................................................................................................65
8.3
8.4
8.5
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 11
Section Number
Title Chapter 9 Internal Clock Source (RS08ICSV1)
Page
9.1
9.2 9.3
9.4
Introduction .....................................................................................................................................75 9.1.1 Features ...........................................................................................................................76 9.1.2 Modes of Operation ........................................................................................................76 9.1.2.1 FLL Engaged Internal (FEI) ...........................................................................76 9.1.2.2 FLL Bypassed Internal (FBI) ..........................................................................76 9.1.2.3 FLL Bypassed Internal Low Power (FBILP) .................................................76 9.1.2.4 Stop (STOP) ....................................................................................................76 9.1.3 Block Diagram ................................................................................................................76 External Signal Description ............................................................................................................77 Register Definition ..........................................................................................................................77 9.3.1 ICS Control Register 1 (ICSC1) .....................................................................................77 9.3.2 ICS Control Register 2 (ICSC2) .....................................................................................78 9.3.3 ICS Trim Register (ICSTRM) ........................................................................................79 9.3.4 ICS Status and Control (ICSSC) ....................................................................................79 Functional Description ....................................................................................................................80 9.4.1 Operational Modes .........................................................................................................80 9.4.1.1 FLL Engaged Internal (FEI) ...........................................................................80 9.4.1.2 FLL Bypassed Internal (FBI) ..........................................................................80 9.4.1.3 FLL Bypassed Internal Low Power (FBILP) .................................................80 9.4.1.4 Stop .................................................................................................................81 9.4.2 Mode Switching ..............................................................................................................81 9.4.3 Bus Frequency Divider ...................................................................................................81 9.4.4 Low Power Bit Usage .....................................................................................................81 9.4.5 Internal Reference Clock ................................................................................................81 9.4.6 Fixed Frequency Clock ...................................................................................................82
Chapter 10 Analog Comparator (RS08ACMPV1)
10.1 Introduction .....................................................................................................................................83 10.1.1 Features ...........................................................................................................................84 10.1.2 Modes of Operation ........................................................................................................84 10.1.2.1 Operation in Wait Mode ..................................................................................84 10.1.2.2 Operation in Stop Mode ..................................................................................84 10.1.2.3 Operation in Active Background Mode ..........................................................84 10.1.3 Block Diagram ................................................................................................................84 10.2 External Signal Description ............................................................................................................86 10.3 Register Definition ..........................................................................................................................86 10.3.1 ACMP Status and Control Register (ACMPSC) ............................................................86 10.4 Functional Description ....................................................................................................................87
SC9RS08KA2 Series Data Sheet, Rev. 1 12 Freescale Semiconductor
Section Number
Title Chapter 11 Modulo Timer (RS08MTIMV1)
Page
11.1 Introduction .....................................................................................................................................89 11.1.1 Features ...........................................................................................................................90 11.1.2 Modes of Operation ........................................................................................................90 11.1.2.1 Operation in Wait Mode ..................................................................................90 11.1.2.2 Operation in Stop Modes ................................................................................90 11.1.2.3 Operation in Active Background Mode ..........................................................90 11.1.3 Block Diagram ................................................................................................................91 11.2 External Signal Description ............................................................................................................91 11.3 Register Definition ..........................................................................................................................91 11.3.1 MTIM Status and Control Register (MTIMSC) .............................................................92 11.3.2 MTIM Clock Configuration Register (MTIMCLK) ......................................................93 11.3.3 MTIM Counter Register (MTIMCNT) ..........................................................................93 11.3.4 MTIM Modulo Register (MTIMMOD) .........................................................................94 11.4 Functional Description ....................................................................................................................95 11.4.1 MTIM Operation Example .............................................................................................96
Chapter 12 Development Support
12.1 Introduction .....................................................................................................................................97 12.2 Features ...........................................................................................................................................97 12.3 RS08 Background Debug Controller (BDC) ..................................................................................98 12.3.1 BKGD Pin Description ...................................................................................................99 12.3.2 Communication Details ..................................................................................................99 12.3.3 SYNC and Serial Communication Timeout .................................................................102 12.4 BDC Registers and Control Bits ...................................................................................................103 12.4.1 BDC Status and Control Register (BDCSCR) .............................................................103 12.4.2 BDC Breakpoint Match Register ..................................................................................104 12.5 RS08 BDC Commands ..................................................................................................................105
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 13
Section Number
Title Appendix A Electrical Characteristics
Page
Introduction ...................................................................................................................................109 Absolute Maximum Ratings ..........................................................................................................109 Thermal Characteristics .................................................................................................................110 Electrostatic Discharge (ESD) Protection Characteristics ............................................................111 DC Characteristics .........................................................................................................................111 Supply Current Characteristics ......................................................................................................115 Analog Comparator (ACMP) Electricals ......................................................................................117 Internal Clock Source Characteristics ...........................................................................................117 AC Characteristics .........................................................................................................................118 A.9.1 Control Timing ...............................................................................................................118 A.10 FLASH Specifications ...................................................................................................................119
A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9
Appendix B Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................123 B.2 Mechanical Drawings ....................................................................................................................123
SC9RS08KA2 Series Data Sheet, Rev. 1 14 Freescale Semiconductor
Chapter 1 SC9RS08KA2 Series Device Overview
1.1 Overview
The SC9RS08KA2 Series microcontroller unit (MCU) is an extremely low-cost, small pin count device for home appliances, toys, and small geometry applications. This device is composed of standard on-chip modules including, a very small and highly efficient RS08 CPU core, 63 bytes RAM, 2K bytes Flash, an 8-bit modulo timer, keyboard interrupt, and analog comparator. The device is available in small 6- and 8-pin packages.
1.2
MCU Block Diagram
RS08 CORE BDC CPU
The block diagram, Figure 1-1, shows the structure of the SC9RS08KA2 Series MCU.
5-BIT KEYBOARD INTERRUPT MODULE (KBI) 5
ACMP+ RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI WAKEUP COP LVD TCLK ACMPO
PTA
RS08 SYSTEM CONTROL
ANALOG COMPARATOR MODULE (ACMP)
ACMP-
PTA0/KBIP0/ACMP+ (1) PTA1/KBIP1/ACMP- (1) PTA2/KBIP2/TCLK/RESET/VPP (1),( 2) PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1), (3)
MODULO TIMER MODULE (MTIM)
USER FLASH SC9RS08KA2 — 2048 BYTES SC9RS08KA1 — 1024 BYTES
USER RAM — 63 BYTES
INTERNAL CLOCK SOURCE (ICS)
VSS VDD
POWER AND INTERNAL REGULATOR
NOTES: (1) Pins are software configurable with pullup/pulldown device if input port. (2) Integrated pullup device enabled if reset enabled (RSTPE=1). (3) These pins are not available in 6-pin package.
Figure 1-1. SC9RS08KA2 Series Block Diagram
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 15
Chapter 1 SC9RS08KA2 Series Device Overview
Table 1-1 provides the functional versions of the on-chip modules.
Table 1-1. Block Versions
Module Analog Comparator (ACMP) Keyboard Interrupt (KBI) Modulo Timer (MTIM) Internal Clock Source (ICS) Version 1 1 1 1
1.3
System Clock Distribution
SYSTEM CONTROL LOGIC TCLK RTICLKS 1-kHz ICSIRCLK ICSFFCLK ICS ICSOUT ÷32 ÷2 BUS CLOCK RTI FIXED CLOCK (XCLK) MTIM
SYNC
÷2
COP CPU
1
BDC
FLASH
The fixed clock (XCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency
Figure 1-2. System Clock Distribution Diagram
Figure 1-2 shows a simplified clock connection diagram for the MCU. The bus clock frequency is half of the ICS output frequency and is used by all of the internal modules.
SC9RS08KA2 Series Data Sheet, Rev. 1 16 Freescale Semiconductor
Chapter 2 Pins and Connections
2.1 Introduction
This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and a detailed discussion of signals.
2.2
Device Pin Assignment
Figure 2-1 and Figure 2-3 show the pin assignments in the packages available for the SC9RS08KA2 Series.
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS VDD
1 6
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP-
2
5
3
4
VSS
Figure 2-1. SC9RS08KA2 Series in 6-Pin DFN
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS VDD VSS
1
8
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 PTA5/KBIP5
2
7
3
6
4
5
Figure 2-2. SC9RS08KA2 Series in 8-Pin PDIP
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 17
Chapter 2 Pins and Connections
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS VDD VSS
1
8
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 PTA5/KBIP5
2
7
3 4
6 5
Figure 2-3. SC9RS08KA2 Series in 8-Pin Narrow Body SOIC
2.3
Recommended System Connections
VDD SC9RS08KA2 VDD CBUK 10 μF CBY 0.1 μF VSS
Figure 2-4 shows reference connection for background debug and Flash programming.
VDD
BKGD/MS
BACKGROUND HEADER
RESET/VPP
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 (Note 1)
NOTES: 1. This pin is not available in the 6-pin package.
PTA5/KBIP5 (Note 1)
Figure 2-4. Reference System Connection Diagram
2.4
Pin Detail
This section provides a detailed description of system connections.
SC9RS08KA2 Series Data Sheet, Rev. 1 18 Freescale Semiconductor
Chapter 2 Pins and Connections
2.4.1
Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the overall system, and a bypass capacitor, such as a 0.1-μF ceramic capacitor, located as near to the MCU power pins as practical to suppress high-frequency noise.
2.4.2
PTA2/KBIP2/TCLK/RESET/VPP
After a power-on reset (POR) into user mode, the PTA2/KBIP2/TCLK/RESET/VPP pin defaults to a general-purpose input port pin, PTA2. Setting RSTPE in SOPT configures the pin to be the RESET input pin. After configured as RESET, the pin will remain as RESET until the next POR. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), the internal pullup device is automatically enabled. External VPP voltage (typically 12 V, see Section A.10, “FLASH Specifications”) is required on this pin when performing Flash programming or erasing. The VPP connection is always connected to the internal Flash module regardless of the pin function. To avoid over stressing the Flash, external VPP voltage must be removed and voltage higher than VDD must be avoided when Flash programming or erasing is not taking place. NOTE This pin does not contain a clamp diode to VDD and should not be driven above VDD when Flash programming or erasing is not taking place.
2.4.3
PTA3/ACMPO/BKGD/MS
The background / mode select function is shared with an output-only pin on PTA3 pin and the optional analog comparator output. While in reset, the pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. While functioning as a background / mode select pin, this pin has an internal pullup device enabled. To use as an output-only port, BKGDPE in SOPT must be cleared. If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the power-on-reset, which forces the MCU to active background mode. The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock equals the bus clock rate; therefore, no significant capacitance should connected to the BKGD/MS pin that could interfere with background serial communications. Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 19
Chapter 2 Pins and Connections
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall times on the BKGD pin.
2.4.4
General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers and analog comparator. Immediately after reset, all of these pins are configured as high-impedance general-purpose inputs with internal pullup/pulldown devices disabled. NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program should either enable on-chip pullup/pulldown devices or change the direction of unused pins to outputs.
Table 2-1. Pin Sharing Reference
Pin Name VDD VSS PTA0 Direction — — I/O Pullup/Pulldown1 — — SWC PTA0 KBIP0 ACMP+ PTA1 KBIP1 ACMPPTA2 KBIP2 TCLK RESET VPP PTA3 ACMPO BKGD MS PTA4 KBIP4 PTA5 KBIP5 Alternative Functions2 Power Ground General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) Analog comparator input General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) Analog comparator input General-purpose input Keyboard interrupt (stop/wait wakeup only) Modulo timer clock source Reset VPP General-purpose output Analog comparator output Background debug data Mode select General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only)
PTA1
I/O
SWC
PTA2
I
SWC4
PTA3
I/O3
—4
PTA45 PTA55
1
I/O I/O
SWC SWC
2
SWC is software-controlled pullup/pulldown resistor; the register is associated with the respective port. Alternative functions are listed lowest priority first. For example, GPIO is the lowest priority alternative function of the PTA0 pin; ACMP+ is the highest priority alternative function of the PTA0 pin. 3 Output-only when configured as PTA3 function. 4 When PTA2 or PTA3 is configured as RESET or BKGD/MS, respectively, pullup is enabled. When V PP is attached, pullup/pulldown is disabled automatically. 5 This pin is not available in 6-pin package. Enabling either the pullup or pulldown device is recommended to prevent extra current leakage from the floating input pin.
SC9RS08KA2 Series Data Sheet, Rev. 1 20 Freescale Semiconductor
Chapter 3 Modes of Operation
3.1 Introduction
This chapter describes the operating modes of the SC9RS08KA2 Series are described in this chapter. It also details entry into each mode, exit from each mode, and functionality while in each of the modes.
3.2
• •
Features
Active background mode for code development Wait mode: — CPU shuts down to conserve power — System clocks continue to run — Full voltage regulation is maintained Stop mode: — System clocks are stopped; voltage regulator in standby — All internal circuits remain powered for fast recovery
•
3.3
Run Mode
This is the normal operating mode for the SC9RS08KA2 Series. This mode is selected when the BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with execution beginning at the address $3FFD. A JMP instruction (opcode $BC) with operand located at $3FFE–$3FFF must be programmed for correct reset operation into the user application. The operand defines the location at which the user program will start. Instead of using the vector fetching process as in HC08/S08 families, the user program is responsible for performing a JMP instruction to relocate the program counter to the correct user program start location.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in the RS08 core. The BDC provides the means for analyzing MCU operation during software development. Active background mode is entered in any of four ways: • When the BKGD/MS pin is low during power-on-reset (POR) or immediately after issuing a background debug force reset (BDC_RESET) command • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 21
Chapter 3 Modes of Operation
•
When a BDC breakpoint is encountered
After active background mode is entered, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running, can be issued through the BKGD pin while the MCU is in run mode. Non-intrusive commands can also be executed when the MCU is in the active background mode. Non-intrusive commands include: — Memory access commands — Memory-access-with-status commands — BACKGROUND command • Active background commands, which can be executed only while the MCU is in active background mode, include commands to: — Read or write CPU registers — Trace one user program instruction at a time — Leave active background mode to return to the user application program (GO) Active background mode is used to program user application code into the Flash program memory before the MCU is operated in run mode for the first time. When the SC9RS08KA2 Series is shipped from the Freescale Semiconductor factory, the Flash program memory is usually erased so there is no program that could be executed in run mode until the Flash memory is initially programmed. The active background mode can also be used to erase and reprogram the Flash memory after it has been previously programmed. For additional information about the active background mode, refer to the Development Support chapter of this data sheet.
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The program counter (PC) is halted at the position where the WAIT instruction is executed. When an interrupt request occurs: 1. MCU exits wait mode and resumes processing. 2. PC is incremented by one and fetches the next instruction to be processed. It is the responsibility of the user program to probe the corresponding interrupt source that woke the MCU, because no vector fetching process is involved. While the MCU is in wait mode, not all background debug commands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode.
SC9RS08KA2 Series Data Sheet, Rev. 1 22 Freescale Semiconductor
Chapter 3 Modes of Operation
Table 3-1 summarizes the behavior of the MCU in wait mode.
Table 3-1. Wait Mode Behavior
Mode Wait CPU Standby Digital Peripherals Optionally on ICS On ACMP Optionally on Regulator On I/O Pins States held RTI Optionally on
3.6
Stop Mode
Stop mode is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In stop mode, all internal clocks to the CPU and the modules are halted. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter stop mode and an illegal opcode reset is forced. Table 3-2 summarizes the behavior of the MCU in stop mode.
Table 3-2. Stop Mode Behavior
Mode Stop
1
CPU Standby
Digital Peripherals Standby
ICS1 Optionally on
ACMP2 Optionally on
Regulator Standby
I/O Pins States held
RTI3 Optionally on
ICS requires IREFSTEN = 1 and LVDE and LVDSE must be set to allow operation in stop. If bandgap reference is required, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop. 3 If the 32-kHz trimmed clock in the ICS module is selected as the clock source for the RTI, LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop.
2
Upon entering stop mode, all of the clocks in the MCU are halted. The ICS is turned off by default when the IREFSTEN bit is cleared and the voltage regulator is put in standby. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are held. Exit from stop is done by asserting RESET, any asynchronous interrupt that has been enabled, or the real-time interrupt. The asynchronous interrupts are the KBI pins, LVD interrupt, or the ACMP interrupt. If stop is exited by asserting the RESET pin, the MCU will be reset and program execution starts at location $3FFD. If exited by means of an asynchronous interrupt or real-time interrupt, the next instruction after the location where the STOP instruction was executed will be executed accordingly. It is the responsibility of the user program to probe for the corresponding interrupt source that woke the CPU. A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop mode with no external components. When RTIS = 000, the real-time interrupt function and the 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case, the real-time interrupt cannot wake the MCU from stop. The trimmed 32-kHz clock in the ICS module can also be enabled for the real-time interrupt to allow a wakeup from stop mode with no external components. The 32-kHz clock reference is enabled by setting
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 23
Chapter 3 Modes of Operation
the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop.
3.6.1
Active BDM Enabled in Stop Mode
Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state; it maintains full internal regulation. Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After active background mode is entered, all background commands are available. Table 3-3 summarizes the behavior of the MCU in stop when entry into the active background mode is enabled.
Table 3-3. BDM Enabled Stop Mode Behavior
Mode Stop CPU Standby Digital Peripherals Standby ICS On ACMP Optionally on Regulator On I/O Pins States held RTI Optionally on
3.6.2
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, the voltage regulator remains active. Table 3-4 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-4. LVD Enabled Stop Mode Behavior
Mode Stop CPU Standby Digital Peripherals Standby ICS Optionally on ACMP Optionally on Regulator On I/O Pins States held RTI Optionally on
SC9RS08KA2 Series Data Sheet, Rev. 1 24 Freescale Semiconductor
Chapter 4 Memory
4.1 Memory Map
The memory map of the MCU is divided into the following groups: • Fast access RAM using tiny and short instructions ($0000–$000E1) • Indirect data access D[X] ($000E) • Index register X for D[X] ($000F) • Frequently used peripheral registers ($0010–$001E) • PAGESEL register ($001F) • RAM ($0020–$004F) • Paging window ($00C0–$00FF) • Other peripheral registers ($0200–$023F) • Nonvolatile memory — SC9RS08KA2: $3800–$3FFF — SC9RS08KA1: $3C00—$3FFF
1. Physical RAM in $000E can be accessed through the D[X] register when the content of the index register X is $0E. SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 25
Chapter 4 Memory
$0000 $000D $000E $000F $0010 $001E $001F $0020
FAST ACCESS RAM 14 BYTES D[X] REGISTER X FREQUENTLY USED REGISTERS PAGESEL RAM 48 BYTES
PAGE REGISTER CONTENT $00
$0000 $000D $000E $000F $0010 $001E $001F $0020
FAST ACCESS RAM 14 BYTES D[X] REGISTER X FREQUENTLY USED REGISTERS PAGESEL RAM 48 BYTES
PAGE REGISTER CONTENT $00
$004F UNIMPLEMENTED $00C0 PAGING WINDOW $00FF
$004F UNIMPLEMENTED $00C0 PAGING WINDOW $00FF
UNIMPLEMENTED
UNIMPLEMENTED
$0200 $023F HIGH PAGE REGISTERS
$08 (reset value)
$0200 $023F HIGH PAGE REGISTERS
$08 (reset value)
UNIMPLEMENTED $3800 FLASH 2044 BYTES $3FFB $3FFC $3FFD NVOPT $E0 $3C00 $3FFB $3FFC $3FFD
UNIMPLEMENTED
FLASH 1020 BYTES NVOPT
$F0
FLASH $3FFF SC9RS08KA2 $3FFF
FLASH
SC9RS08KA1
Figure 4-1. SC9RS08KA2 Series Memory Maps
SC9RS08KA2 Series Data Sheet, Rev. 1 26 Freescale Semiconductor
Chapter 4 Memory
4.2
Unimplemented Memory
Attempting to access either data or an instruction at an unimplemented memory address will cause reset.
4.3
Indexed/Indirect Addressing
Register D[X] and register X together perform the indirect data access. Register D[X] is mapped to address $000E. Register X is located in address $000F. The 8-bit register X contains the address that is used when register D[X] is accessed. Register X is cleared to zero upon reset. By programming register X, any location on the first page ($0000–$00FF) can be read/written via register D[X]. Figure 4-2 shows the relationship between D[X] and register X. For example, in HC08/S08 syntax lda ,x is comparable to lda D[X] in RS08 coding when register X has been programmed with the index value. The physical location of $000E is in RAM. Accessing the location through D[X] returns $000E RAM content when register X contains $0E. The physical location of $000F is register X, itself. Reading the location through D[X] returns register X content; writing to the location modifies register X.
$0000
$000E $000F
D[X] Register X Register X can specify any location between $0000–$00FF
Address indicated in Register X
Content of this location can be accessed via D[X]
$00FF $0100
Figure 4-2. Indirect Addressing Registers
4.4
RAM and Register Addresses and Bit Assignments
The fast access RAM area can be accessed by instructions using tiny, short, and direct addressing mode instructions. For tiny addressing mode instructions, the operand is encoded along with the opcode to a single byte.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 27
Chapter 4 Memory
Frequently used registers can make use of the short addressing mode instructions for faster load, store, and clear operations. For short addressing mode instructions, the operand is encoded along with the opcode to a single byte.
Table 4-1. Register Summary
Address Register Name $0000– $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020– $004F $0050– $00BF $00C0– $00FF $0100– $01FF $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B Bit 7 6 5 4 3 2 1 Bit 0
Fast Access RAM D[X]1 X PTAD PTADD Unimplemented ACMPSC ICSC1 ICSC2 ICSTRM ICSSC MTIMSC MTIMCLK MTIMCNT MTIMMOD KBISC KBIPE KBIES PAGESEL Bit 7 Bit 7 0 0 — ACME 0 BDIV 0 TOF 0 0 TOIE 0 6 6 0 0 — ACBGS CLKS 4 3 4 3 PTAD4 PTAD3 PTADD4 0 — — ACIE ACO 0 0 0 LP TRIM 0 0 0 TRST TSTP 0 CLKS COUNT MOD 0 0 KBF KBIPE5 KBIPE4 — KBEDG5 KBEDG4 — AD11 AD10 AD9 RAM Unimplemented — — — — — — — — 5 5 PTAD5 PTADD5 — ACF 0 0 2 2 PTAD2 0 — ACOPE 0 0 CLKST 0 PS 1 Bit 0 1 Bit 0 PTAD1 PTAD0 PTADD1 PTADD0 — — ACMOD 0 IREFSTEN 0 0 0 0 FTRIM 0
0 — — AD13
0 — — AD12
KBACK KBIPE2 KBEDG2 AD8
KBIE KBIPE1 KBEDG1 AD7
KBIMOD KBIPE0 KBEDG0 AD6
Paging Window Unimplemented SRS SOPT SIP1 Unimplemented Reserved Unimplemented SDIDH SDIDL SRTISC SPMSC1 Reserved Reserved — POR COPE — — — — REV3 RTIF LVDF — — — PIN COPT — — — — REV2 RTIACK LVDACK — — — COP STOPE — — — — REV1 RTICLKS LVDIE — — — ILOP 0 KBI — — — REV0 ID RTIE LVDRE — — 0 LVDSE — — LVDE — — RTIS 0 — — BGBE — — — ILAD 0 ACMP — — — — 0 0 MTIM — — — ID — LVD BKGDPE RTI — — — — 0 RSTPE LVD — — —
= Unimplemented or Reserved
SC9RS08KA2 Series Data Sheet, Rev. 1 28 Freescale Semiconductor
Chapter 4 Memory
Table 4-1. Register Summary (continued)
Address Register Name $020C– $020F $0210 $0211 $0212– $0213 $0214– $021F $0220 $0221 $0222 $0223– $023F $3FF8 $3FF9 $3FFA2 $3FFB2 $3FFC Unimplemented FOPT FLCR Reserved Unimplemented PTAPE PTAPUD PTASE Unimplemented Bit 7 — 0 0 — — — 0 0 0 — 6 — 0 0 — — — 0 0 0 — 5 — 0 0 — — — PTAPE5 PTAPUD5 PTASE5 — 4 — 0 0 — — — PTAPE4 PTAPUD4 PTASE4 — 3 — 0 HVEN — — — 0 0 PTASE3 — 2 — 0 MASS — — — PTAPE2 PTAPUD2 0 — 1 — 0 0 — — — PTAPE1 PTAPUD1 PTASE1 — Bit 0 — SECD PGM — — — PTAPE0 PTAPUD0 PTASE0 —
Reserved Reserved Reserved Reserved NVOPT
— —
— —
0
0
— — — — — — — — Reserved for Room Temperature ICS Trim Reserved 0 0 0 0
— —
— — FTRIM SECD
0
= Unimplemented or Reserved
1 2
Physical RAM in $000E can be accessed through D[X] register when the content of the index register X is $0E. If using the MCU untrimmed, $3FFA and $3FFB may be used by applications.
4.5
RAM
The device includes two sections of static RAM. The locations from $0000 to $000D can be directly accessed using the more efficient tiny addressing mode instructions and short addressing mode instructions. Location $000E RAM can either be accessed through D[X] register when register X is $0E or through the paging window location $00CE when PAGESEL register is $00. The second section of RAM starts from $0020 to $004F, and it can be accessed using direct addressing mode instructions. The RAM retains data when the MCU is in low-power wait and stop mode. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention.
4.6
Flash
The Flash memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the Flash memory after final assembly of the application product. It is possible to program the entire array through the single-wire background debug interface. Because the device does not include on-chip charge pump circuitry, external VPP is required for program and erase operations.
4.6.1
Features
Features of the Flash memory include:
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 29
Chapter 4 Memory
• •
Up to 1000 program/erase cycles at typical voltage and temperature Security feature for Flash
4.6.2
Flash Programming Procedure
Programming of Flash memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $3X00, $3X40, $3X80, or $3XC0. Use the following procedure to program a row of Flash memory: 1. Apply external VPP. 2. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 3. Write any data to any Flash location, via the high page accessing window $00C0–$00FF, within the address range of the row to be programmed. (Prior to the data writing operation, the PAGESEL register must be configured correctly to map the high page accessing window to the corresponding Flash row). 4. Wait for a time, tnvs. 5. Set the HVEN bit. 6. Wait for a time, tpgs. 7. Write data to the Flash location to be programmed. 8. Wait for a time, tprog. 9. Repeat steps 7 and 8 until all bytes within the row are programmed. 10. Clear the PGM bit. 11. Wait for a time, tnvh. 12. Clear the HVEN bit. 13. After time, trcv, the memory can be accessed in read mode again. 14. Remove external VPP. This program sequence is repeated throughout the memory until all data is programmed. NOTE Flash memory cannot be programmed or erased by software code executed from Flash locations. To program or erase Flash, commands must be executed from RAM or BDC commands. User code should not enter wait or stop during erase or program sequence. These operations must be performed in the order shown; other unrelated operations may occur between the steps.
4.6.3
Flash Mass Erase Operation
Use the following procedure to mass erase the entire Flash memory: 1. Apply external VPP. 2. Set the MASS bit in the Flash control register.
SC9RS08KA2 Series Data Sheet, Rev. 1 30 Freescale Semiconductor
Chapter 4 Memory
3. Write any data to any Flash location, via the high page accessing window $00C0–$00FF. (Prior to the data writing operation, the PAGESEL register must be configured correctly to map the high page accessing window to the any Flash locations). 4. Wait for a time, tnvs. 5. Set the HVEN bit. 6. Wait for a time tme. 7. Clear the MASS bit. 8. Wait for a time, tnvh1. 9. Clear the HVEN bit. 10. After time, trcv, the memory can be accessed in read mode again. 11. Remove external VPP. NOTE Flash memory cannot be programmed or erased by software code executed from Flash locations. To program or erase Flash, commands must be executed from RAM or BDC commands. User code should not enter wait or stop during an erase or program sequence. These operations must be performed in the order shown, but other unrelated operations may occur between the steps.
4.6.4
Security
The SC9RS08KA2 Series includes circuitry to help prevent unauthorized access to the contents of Flash memory. When security is engaged, Flash is considered a secure resource. The RAM, direct-page registers, and background debug controller are considered unsecured resources. Attempts to access a secure memory location through the background debug interface, or whenever BKGDPE is set, are blocked (reads return all 0s). Security is engaged or disengaged based on the state of a nonvolatile register bit (SECD) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the working FOPT register in high-page register space. A user engages security by programming the NVOPT location, which can be done at the same time the Flash memory is programmed. Notice the erased state (SECD = 1) makes the MCU unsecure. When SECD in NVOPT is programmed (SECD = 0), next time the device is reset via POR, internal reset, or external reset, security is engaged. In order to disengage security, mass erase must be performed via BDM commands and followed by any reset. The separate background debug controller can still be used for registers and RAM access. Flash mass erase is possible by writing to the Flash control register that follows the Flash mass erase procedure listed in Section 4.6.3, “Flash Mass Erase Operation,” via BDM commands. Security can always be disengaged through the background debug interface by following these steps: 1. Mass erase Flash via background BDM commands or RAM loaded program. 2. Perform reset and the device will boot up with security disengaged.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 31
Chapter 4 Memory
NOTE When the device boots up to normal operating mode, where MS pin is high during reset, with SECD programmed (SECD = 0), Flash security is engaged. BKGDPE is reset to 0, and all BDM communication is blocked, and background debug is not allowed.
4.7
Flash Registers and Control Bits
The Flash module has a nonvolatile register, NVOPT ($3FFC), in Flash memory which is copied into the corresponding control register, FOPT ($0210), at reset.
4.7.1
Flash Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT is copied from Flash into FOPT. Bits 7 through 1 are not used and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this register, erase and reprogram the NVOPT location in Flash memory as usual and then issue a new MCU reset.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
SECD
This register is loaded from nonvolatile location NVOPT during reset. = Unimplemented or Reserved
Figure 4-3. Flash Options Register (FOPT) Table 4-2. FOPT Field Descriptions
Field 0 SECD Description Security State Code — This bit field determines the security state of the MCU. When the MCU is secured, the contents of Flash memory cannot be accessed by instructions from any unsecured source including the background debug interface; refer to Section 4.6.4, “Security”. 0 Security engaged. 1 Security disengaged.
SC9RS08KA2 Series Data Sheet, Rev. 1 32 Freescale Semiconductor
Chapter 4 Memory
4.7.2
Flash Control Register (FLCR)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 HVEN MASS 0
0
PGM1 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-4. Flash Control Register (FLCR) Table 4-3. FLCR Field Descriptions
Field 3 HVEN Description High Voltage Enable — This read/write bit enables high voltages to the Flash array for program and erase operations. HVEN can be set only if either PGM = 1 or MASS = 1 and the proper sequence for program or erase is followed. 0 High voltage disabled to array. 1 High voltage enabled to array. Mass Erase Control Bit — This read/write bit configures the memory for mass erase operation. 0 Mass erase operation not selected. 1 Mass erase operation selected. Program Control Bit — This read/write bit configures the memory for program operation. PGM is interlocked with the MASS bit such that both bits cannot be equal to 1 or set to 1 at the same time. 0 Program operation not selected. 1 Program operation selected.
2 MASS 0 PGM1
1
When Flash security is engaged, writing to PGM bit has no effect. As a result, Flash programming is not allowed.
4.8
Page Select Register (PAGESEL)
There is a 64-byte window ($00C0–$00FF) in the direct-page reserved for paging access. Programming the page select register determines the corresponding 64-byte block on the memory map for direct-page access. For example, when the PAGESEL register is programmed with value $08, the high page registers ($0200–$023F) can be accessed through the paging window ($00C0–$00FF) via direct addressing mode instructions.
7 6 5 4 3 2 1 0
R AD13 W Reset 0 0 0 0 1 0 0 0 AD12 AD11 AD10 AD9 AD8 AD7 AD6
Figure 4-5. Page Select Register (PAGESEL) Table 4-4. PAGESEL Field Descriptions
Field 7:0 AD[13:6] Description Page Selector— These bits define the address line bit 6 to bit 13, which determines the 64-byte block boundary of the memory block accessed via the direct page window. See Figure 4-6 and Table 4-5.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 33
Chapter 4 Memory
14-bit memory address Start address of memory block selected AD[13:6] 0 0 0 0 0 0
Figure 4-6. Memory Block Boundary Selector
Table 4-5 shows the memory block to be accessed through paging window ($00C0–$00FF).
Table 4-5. Paging Window for $00C0–$00FF
Page $00 $01 $02 $03 $04 . . . $FE $FF Memory Address $0000–$003F $0040–$007F $0080–$00BF $00C0–$00FF $0100–$013F . . . $3F80–$3FBF $3FC0–$3FFF
NOTE Physical location $0000-$000E is RAM. Physical location $000F is register X. D[X] register is mapped to address $000E only. The physical RAM in $000E can be accessing through D[X] register when X register is either $0E or $CE with PAGESEL is $00. When PAGESEL register is $00, paging window is mapped to the first page ($00-$3F). Paged location $00C0–$00CE is mapped to physical location $0000-$000E, i.e., RAM. Paged location $00CF is mapped to register X. Therefore, accessing address $CE returns the physical RAM content in $000E, accessing address $000E returns D[X] register content.
SC9RS08KA2 Series Data Sheet, Rev. 1 34 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and General System Control
5.1 Introduction
This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the SC9RS08KA2 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data sheet. This chapter gathers basic information about all reset and interrupt sources in one place for easy reference. A few reset and wakeup sources, including the computer operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral systems with their own chapters but are part of the system control logic.
5.2
Features
Reset and interrupt features include: • Multiple sources of reset for flexible system configuration and reliable operation • System reset status register (SRS) to indicate the source of the most recent reset • System interrupt pending register (SIP1) to indicate the status of pending system interrupts — Analog comparator interrupt with enable — Keyboard interrupt with enable — Low-voltage detect interrupt with enable — Modulo timer interrupt with enable — Real-time interrupt with enable; available in stop with multiple rates based on a separate 1-kHz self-clocked source
5.3
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is started from location $3FFD. A JMP instruction (opcode $BC) with operand located at $3FFE–$3FFF must be programmed into the user application for correct reset operation. The operand defines the location at which the user program will start. On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pullup/pulldown devices disabled. The SC9RS08KA2 Series has seven sources for reset: • External pin reset (PIN) — enabled using RSTPE in SOPT • Power-on reset (POR) • Low-voltage detect (LVD)
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 35
Chapter 5 Resets, Interrupts, and General System Control
• • • •
Computer operating properly (COP) timer Illegal opcode detect (ILOP) Illegal address detect (ILAD) Background debug forced reset via BDC command BDC_RESET
Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (SRS).
5.4
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset if the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point. After any reset, the COPE becomes set in SOPT, which enables the COP watchdog (see Section 5.8.2, “System Options Register (SOPT),” for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a reset signal to the COP counter. There is an associated short and long time-out controlled by COPT in SOPT. Table 5-1 summaries the control functions of the COPT bit. The COP watchdog operates from the 1-kHz clock source and defaults to the associated long time-out (28 cycles).
Table 5-1. COP Configuration Options
COPT 0 1
1
COP Overflow Count1 25 cycles (32 ms) 28 cycles (256 ms)
Values shown in this column are based on tRTI ≈ 1 ms. See tRTI in the Section A.9.1, “Control Timing,” for the tolerance of this value.
Even if the application will use the reset default settings of COPE and COPT, the user should write to the write-once SOPT registers during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application program gets lost. The initial write to SOPT will reset the COP counter. In background debug mode, the COP counter will not increment. When the MCU enters stop mode, the COP counter is re-initialized to zero upon entry to stop mode. The COP counter begins from zero as soon as the MCU exits stop mode.
5.5
Interrupts
The SC9RS08KA2 Series does not include an interrupt controller with vector table lookup mechanism as used on the HC08 and HCS08 devices. However, the interrupt sources from modules such as LVD, KBI,
SC9RS08KA2 Series Data Sheet, Rev. 1 36 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and General System Control
and ACMP are still available to wake the CPU from wait or stop mode. It is the responsibility of the user application to poll the corresponding module to determine the source of wakeup. Each wakeup source of the module is associated with a corresponding interrupt enable bit. If the bit is disabled, the interrupt source is gated, and that particular source cannot wake the CPU from wait or stop mode. However, the corresponding interrupt flag will still be set to indicate that an external wakeup event has occurred. The system interrupt pending register (SIP1) indicates the status of the system pending interrupt. When the read-only bit of the SIP1 is enabled, it shows there is a pending interrupt to be serviced from the indicated module. Writing to the register bit has no effect. The pending interrupt flag will be cleared automatically when the all corresponding interrupt flags from the indicated module are cleared.
5.6
Low-Voltage Detect (LVD) System
The SC9RS08KA2 Series includes a system to protect against low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit with a predefined trip voltage. The LVD circuit is enabled with LVDE in SPMSC1. The LVD is disabled upon entering stop mode unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, the current consumption in stop with the LVD enabled will be greater.
5.6.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above the VLVD level. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level VLVD. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt operation (LVDE set, LVDIE set, and LVDRE clear), LVDF in SPMSC1 will be set and an LVD interrupt request will occur.
5.7
Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts. The RTI is driven from either the 1-kHz internal clock reference or the trimmed 32-kHz internal clock reference from the ICS module. The 32-kHz internal clock reference is divided by 32 by the RTI logic to produce a trimmed 1-kHz clock
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 37
Chapter 5 Resets, Interrupts, and General System Control
for applications requiring more accurate real-time interrupts. The RTICLKS bit in SRTISC is used to select the RTI clock source. Both the1-kHz and 32-kHz clock sources for the RTI can be used when the MCU is in run, wait or stop mode. For the 32-kHz clock source to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering stop. The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS) used to select one of seven wakeup periods or disable RTI. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to 0s, and no interrupts will be generated. See Section 5.8.4, “System Real-Time Interrupt Status and Control Register (SRTISC),” for detailed information about this register.
5.8
Reset, Interrupt, and System Control Registers and Control Bits
Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments for all registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some control bits in the SOPT register are related to modes of operation. Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of Operation”.
5.8.1
System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by the BDC_RESET command, all of the status bits in SRS will be cleared. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
7 6 5 4 3 2 1 0
R W POR: LVR: Any other reset:
POR
PIN
COP
ILOP
ILAD
0
LVD
0
Writing any value to SRS address clears COP watchdog timer. 1 0 0 0 0 Note 1 0 0 Note 1 0 0 Note 1 0 0 Note 1 0 0 0 1 1 0 0 0 0
1. Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared.
Figure 5-1. System Reset Status (SRS)
SC9RS08KA2 Series Data Sheet, Rev. 1 38 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and General System Control
Table 5-2. SRS Field Descriptions
Field 7 POR Description Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the internal supply was below the LVR threshold. 0 Reset not caused by POR. 1 POR caused reset. External Reset Pin — Reset was caused by an active-low level on the external reset pin. 0 Reset not caused by external reset pin. 1 External reset pin caused reset. Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by COPE = 0. 0 Reset not caused by COP timeout. 1 COP timeout caused reset. Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 An illegal opcode caused reset. Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 Reset not caused by an illegal address. 1 An illegal address caused reset. Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. 0 Reset not caused by LVD trip or POR. 1 Either LVD trip or POR caused reset.
6 PIN 5 COP
4 ILOP
3 ILAD
1 LVD
5.8.2
System Options Register (SOPT)
This high page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT must be written during the user’s reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
7 6 5 4 3 2 1 0
R COPE W Reset: POR: 1 1 1 1 0 0 COPT STOPE
0
0
0 BKGDPE RSTPE u 0
0 0
0 0
0 0
1 (Note 1) 1 (Note1)
= Unimplemented or Reserved
u = Unaffected
Figure 5-2. System Options Register 1 (SOPT)
1. When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 39
Chapter 5 Resets, Interrupts, and General System Control
Table 5-3. SOPT Register Field Descriptions
Field 7 COPE 6 COPT 5 STOPE Description COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. 0 Short timeout period selected. 1 Long timeout period selected. Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced. 0 Stop mode disabled. 1 Stop mode enabled.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS 1 BKGDPE1,2 pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This pin defaults to the BKGD/MS function following any MCU reset. 0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO. 1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS. 0 RSTPE RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/VPP pin to function as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET. 0 PTA2/KBIP2/TCLK/RESET/VPP pin functions as PTA2/KBIP2/TCLK/VPP. 1 PTA2/KBIP2/TCLK/RESET/VPP pin functions as RESET/VPP.
1
When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed. 2 BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be changed back to 1 only by a POR or reset with proper condition as stated in Note 1.
5.8.3
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the RS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
7 6 5 4 3 2 1 0
R W Reset:
REV3
REV2
REV1
REV0
ID11
ID10
ID9
ID8
0 (Note 1)
0 (Note 1)
0 (Note 1)
0 (Note 1)
1
0
0
0
= Unimplemented or Reserved
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-3. System Device Identification Register — High (SDIDH)
SC9RS08KA2 Series Data Sheet, Rev. 1 40 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and General System Control
Table 5-4. SDIDH Register Field Descriptions
Field 7:4 REV[3:0] 3:0 ID[11:8] Description Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set revision number (0–F). Part Identification Number — Each derivative in the RS08 Family has a unique identification number. The SC9RS08KA2 Series is hard coded to the value $0800. See also ID bits in Figure 5-4.
7
6
5
4
3
2
1
0
R W Reset:
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-4. System Device Identification Register — Low (SDIDL) Table 5-5. SDIDL Register Field Descriptions
Field 7:0 ID[7:0] Description Part Identification Number — Each derivative in the RS08 Family has a unique identification number. The SC9RS08KA2 Series is hard coded to the value $0800. See also ID bits in Figure 5-3.
5.8.4
System Real-Time Interrupt Status and Control Register (SRTISC)
This high page register contains status and control bits for the RTI.
7 6 5 4 3 2 1 0
R W Reset:
RTIF
0 RTICLKS RTIACK RTIE 0
0 RTIS 0 0 0 0
0
0
0
= Unimplemented or Reserved
Figure 5-5. System RTI Status and Control Register (SRTISC) Table 5-6. SRTISC Register Field Descriptions
Field 7 RTIF 6 RTIACK 5 RTICLKS Description Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out. 0 Periodic wakeup timer not timed out. 1 Periodic wakeup timer timed out. Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request (write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0. Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt. 0 Real-time interrupt request clock source is internal 1-kHz oscillator. 1 Real-time interrupt request clock source is internal trimmed 32-kHz oscillator (ICS module) and is divided by 32 in RTI logic to produce a trimmed 1-kHz clock source for RTI counter.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 41
Chapter 5 Resets, Interrupts, and General System Control
Table 5-6. SRTISC Register Field Descriptions (continued)
Field 4 RTIE 2:0 RTIS Description Real-Time Interrupt Enable — This read-write bit enables real-time interrupts. 0 Real-time interrupts disabled. 1 Real-time interrupts enabled. Real-Time Interrupt Delay Selects — These read/write bits select the period for the RTI. See Table 5-7.
Table 5-7. Real-Time Interrupt Period
RTIS 000 001 010 011 100 101 110 111
1
RTI Timeout1 Disable RTI 8 ms 32 ms 64 ms 128 ms 256 ms 512 ms 1.024 s
Timeout values shown based on RTI clock source of 1 ms period. Consult electricals for tolerances of internal 1-kHz source, tRTI (Table A-8) and the internal 32-kHz from ICS (Table A-7).
NOTE To power down the internal 1-kHz oscillator completely in MCU STOP mode, RTIS bits must be selected to %000 and RTICLKS bit must be set to 1.
SC9RS08KA2 Series Data Sheet, Rev. 1 42 Freescale Semiconductor
Chapter 5 Resets, Interrupts, and General System Control
5.8.5
System Power Management Status and Control 1 Register (SPMSC1)
This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ACMP and the LVD module.
7 6 5 4 3 2 1 0
R W Reset:
LVDF
0 LVDIE LVDACK
LVDRE(1) 1
LVDSE 1
LVDE(1) 1
0 BGBE 0 0
0
0
0
= Unimplemented or Reserved
1
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-6. System Power Management Status and Control 1 Register (SPMSC1) Table 5-8. SPMSC1 Register Field Descriptions
Field 7 LVDF 6 LVDACK 5 LVDIE 4 LVDRE Description Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event. Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads always return 0. Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVDF = 1. Low-Voltage Detect Reset Enable — This write-once bit enables low-voltage detect events to generate a hardware reset (provided LVDE = 1). 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the ACMP module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled.
3 LVDSE
2 LVDE
0 BGBE
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 43
Chapter 5 Resets, Interrupts, and General System Control
5.8.6
System Interrupt Pending Register (SIP1)
This high page register contains status of the pending interrupt from the modules.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
KBI
ACMP
MTIM
RTI
LVD
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-7. System Interrupt Pending Register (SIP1) Table 5-9. SIP1 Register Field Descriptions
Field 4 KBI Description Keyboard Interrupt Pending — This read-only bit indicates there is a pending interrupt from the KBI module. Clearing the KBF flag of the KBISC register clears this bit. Reset also clears this bit. 0 There is no pending KBI interrupt; i.e., KBF flag and/or KBIE bit is cleared. 1 There is a pending KBI interrupt; i.e., KBF flag and KBIE bit are set. Analog Comparator Interrupt Pending — This read-only bit indicates there is a pending interrupt from the ACMP module. Clearing the ACF flag of the ACMPSC register clears this bit. Reset also clears this bit. 0 There is no pending ACMP interrupt; i.e., ACF flag and/or ACIE bit is cleared. 1 There is a pending a ACMP interrupt; i.e., ACF flag and ACIE bit are set. Modulo Timer Interrupt Pending — This read-only bit indicates there is a pending interrupt from the MTIM module. Clearing the TOF flag of the MTIMSC register clears this bit. Reset also clears this bit. 0 There is no pending MTIM interrupt; i.e., TOF flag and/or TOIE bit is cleared. 1 There is a pending MTIM interrupt; i.e., TOF flag and TOIE bit are set. Real-Time Interrupt Pending — This read-only bit indicates there is a pending interrupt from the RTI. Clearing the RTIF flag of the SRTISC register clears this bit. Reset also clears this bit. 0 There is no pending RTI interrupt; i.e., RTIF flag and/or RTIE bit is cleared. 1 There is a pending RTI interrupt; i.e., RTIF flag and RTIE bit are set. Low-Voltage Detect Interrupt Pending — This read-only bit indicates there is a pending interrupt from the low voltage detect module. Clearing the LVDF flag of the SPMSC1 register clears this bit. Reset also clears this bit. 0 There is no pending LVD interrupt; i.e., LVDF flag and/or LVDE bit is cleared. 1 There is a pending LVD interrupt; i.e., LVDF flag, LVDIE, and LVDE bits are set.
3 ACMP
2 MTIM
1 RTI
0 LVD
SC9RS08KA2 Series Data Sheet, Rev. 1 44 Freescale Semiconductor
Chapter 6 Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The SC9RS08KA2 Series has one parallel I/O port, which includes two I/O pins in the 6-pin package or four I/O pins in the 8-pin packages, one output-only pin, and one input-only pin. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations for these pins. All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-1. The peripheral modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are controlled by the I/O. All of the I/Os are configured as inputs (PTADDn = 0) with pullup/pulldown devices disabled (PTAPEn = 0), except for output-only pin PTA3, which defaults to the BKGD/MS function. Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram shown in Figure 6-1.
PTADDn D Q Output Enable
PTADn D Q Output Data
1 Port Read Data 0 Synchronizer Input Data
BUSCLK
Figure 6-1. Parallel I/O Block Diagram
The data direction control bit (PTADDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 45
Chapter 6 Parallel Input/Output Control
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data direction register bit will continue to control the source for reads of the port data register. When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any port data bit where the bit is an input (PTADDn = 0) and the input buffer is disabled. In general, whenever a pin is shared with both an alternative digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven temporarily with an old data value that happened to be in the port data register. Associated with the parallel I/O ports is a set of registers located in the high page register space that operate independently of the parallel I/O registers. These registers are used to control pullup/pulldown and slew rate for the pins. See Section 6.3, “Pin Control Registers” for more information.
6.1
Pin Behavior in Low-Power Modes
In wait and stop modes, all pin states are maintained because internal logic stays powered up. Upon recovery, all pin functions are the same as before entering stop.
6.2
Parallel I/O Registers
This section provides information about the registers associated with the parallel I/O ports. The parallel I/O registers are located within the $001F memory boundary of the memory map, so that short and direct addressing mode instructions can be used. Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.2.1
Port A Registers
Port A parallel I/O function is controlled by the data and data direction registers described in this section.
7
6
5
4
3
2
1
0
R W Reset:
0
0
PTAD5 PTAD4 0 PTAD3 0
PTAD2 PTAD1 0 0 PTAD0 0
0
0
0
Figure 6-2. Port A Data Register (PTAD)
SC9RS08KA2 Series Data Sheet, Rev. 1 46 Freescale Semiconductor
Chapter 6 Parallel Input/Output Control
Table 6-1. PTAD Register Field Descriptions
Field 5:0 PTAD[5:0] Description Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullup/pulldowns disabled.
7
6
5
4
3
2
1
0
R W Reset:
0
0
PTADD5 PTADD4 0
0
0
PTADD1 PTADD0 0
0
0
0
0
0
0
Figure 6-3. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field 5:4,1:0 PTADD[5:4,1:0] Description Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.3
Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports that are used for pin control functions. Refer to tables in Chapter 4, “Memory,” for the absolute address assignments of the pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.3.1
Port A Pin Control Registers
The pins associated with port A are controlled by the registers provided in this section. These registers control the pin pullup/pulldown and slew rate of the port A pins independent of the parallel I/O registers.
6.3.1.1
Internal Pulling Device Enable
An internal pulling device can be enabled for each port pin by setting the corresponding bit in the pulling device enable register (PTAPEn). The pulling device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral output function regardless of the state of the
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 47
Chapter 6 Parallel Input/Output Control
corresponding pulling device enable register bit. The pulling device is also disabled if the pin is controlled by an analog function.
7
6
5
4
3
2
1
0
R W Reset:
0
0
PTAPE5 PTAPE4 0
0
PTAPE2 0 0 PTAPE1 0 PTAPE0 0
0
0
0
Figure 6-4. Internal Pulling Device Enable for Port A Register (PTAPE) Table 6-3. PTAPE Register Field Descriptions
Field Description
5:4,2:0 Internal Pulling Device Enable for Port A Bits — Each of these control bits determines whether the internal PTAPE[5:4,2:0] pulling device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled. 0 Internal pulling device disabled for port A bit n. 1 Internal pulling device enabled for port A bit n.
6.3.1.2
Pullup/Pulldown Control
Pullup/pulldown control is used to select the pullup or pulldown device enabled by the corresponding PTAPE bit.
7 6 5 4 3 2 1 0
R W Reset:
0
0
PTAPUD5 PTAPUD4 0
0
PTAPUD2 0 0 PTAPUD1 0 PTAPUD0 0
0
0
0
Figure 6-5. Pullup/Pulldown Device Control for Port A (PTAPUD) Table 6-4. PTAPUD Register Field Descriptions
Field Description
5:4,2:0 Pullup/Pulldown Device Control for Port A Bits — Each of these control bits determines whether the PTAPUD[5:4,2:0] internal pullup or pulldown device is selected for the associated PTA pin. The actual pullup/pulldown device is only enabled by enabling the associated PTAPE bit. 0 Internal pullup device is selected for port A bit n. 1 Internal pulldown device is selected for port A bit n.
6.3.1.3
Output Slew Rate Control Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (PTASEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
SC9RS08KA2 Series Data Sheet, Rev. 1 48 Freescale Semiconductor
Chapter 6 Parallel Input/Output Control
7
6
5
4
3
2
1
0
R W Reset:
0
0
PTASE5 PTASE4 1 PTASE3 1
0
PTASE1 0 1 PTASE0 1
0
0
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE) Table 6-5. PTASE Register Field Descriptions
Field Description
5:3;1:0 Output Slew Rate Enable for Port A Bits — Each of these control bits determines whether the output slew PTASE[5:3;1:0] rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 49
Chapter 6 Parallel Input/Output Control
SC9RS08KA2 Series Data Sheet, Rev. 1 50 Freescale Semiconductor
Chapter 7 Keyboard Interrupt (RS08KBIV1)
7.1 Introduction
The keyboard interrupt (KBI) module provides independently enabled external interrupt sources.
RS08 CORE BDC CPU 5-BIT KEYBOARD INTERRUPT MODULE (KBI) 5
ACMP+ RESET AND STOP WAKEUP MODES OF OPERATION POWER MANAGEMENT RTI WAKEUP COP LVD TCLK ACMPO PTA RS08 SYSTEM CONTROL ANALOG COMPARATOR MODULE (ACMP) ACMP-
PTA0/KBIP0/ACMP+ (1) PTA1/KBIP1/ACMP- (1) PTA2/KBIP2/TCLK/RESET/VPP (1),( 2) PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1), (3)
MODULO TIMER MODULE (MTIM)
USER FLASH — 2,048 BYTES
USER RAM — 63 BYTES
INTERNAL CLOCK SOURCE (ICS)
VSS VDD
POWER AND INTERNAL REGULATOR
NOTES: (1) Pins are software configurable with pullup/pulldown device if input port. (2) Integrated pullup device enabled if reset enabled (RSTPE=1). (3) These pins are not available in 6-pin package
Figure 7-1. SC9RS08KA2 Series Block Diagram with KBI Block and Pins Highlighted
7.1.1
Features
The KBI features include: • Each keyboard interrupt pin has an individual pin enable bit • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity • One software-enabled keyboard interrupt • Exit from low-power modes
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 51
Chapter 7 Keyboard Interrupt (RS08KBIV1)
7.1.2
Modes of Operation
This section defines the KBI operation in wait, stop, and background debug modes.
7.1.2.1
Operation in Wait Mode
The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore, an enabled KBI pin (KBPEn = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBIE = 1).
7.1.2.2
Operation in Stop Mode
The KBI operates asynchronously in stop mode if enabled before executing the STOP instruction. Therefore, an enabled KBI pin (KBPEn = 1) can be used to bring the MCU out of stop mode if the KBI interrupt is enabled (KBIE = 1).
7.1.2.3
Operation in Active Background Mode
When the microcontroller is in active background mode, the KBI will continue to operate normally.
7.1.3
Block Diagram
KBACK 1 VDD S KBIPE0 D CLR Q CK RESET SYNCHRONIZER BUSCLK KBF
The block diagram for the keyboard interrupt module is shown Figure 7-2.
KBIP0
0
KBEDG0 1 KBIPn 0 S KBIPEn KBMOD KBIE KBEDGn KEYBOARD INTERRUPT FF STOP STOP BYPASS KBI INTERRUPT REQUEST
Figure 7-2. Keyboard Interrupt (KBI) Block Diagram
7.2
External Signal Description
The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high level interrupt requests. The signal properties of KBI are shown in Table 7-1.
Table 7-1. Signal Properties
Signal KBIPn Function Keyboard interrupt pins I/O I
SC9RS08KA2 Series Data Sheet, Rev. 1 52 Freescale Semiconductor
Chapter 7 Keyboard Interrupt (RS08KBIV1)
7.3
Register Definition
The KBI includes three registers: • An 8-bit pin status and control register • An 8-bit pin enable register • An 8-bit edge select register Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names. The KBI registers are summarized in Table 7-2.
Table 7-2. KBI Register Summary
Name R KBISC W R KBIPE W R KBIES W 0 0 KBEDG5 KBEDG4 0 KBEDG2 KBEDG1 KBEDG0 0 0 KBIPE5 KBIPE4 0 KBIPE2 KBIPE1 KBIPE0 KBACK
7 6 5 4 3 2 1 0
0
0
0
0
KBF
0 KBIE KBMOD
7.3.1
KBI Status and Control Register (KBISC)
KBISC contains the status flag and control bits, which are used to configure the KBI.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
KBF
0 KBIE KBACK KBMOD 0
0
0 = Unimplemented
0
0
0
0
0
Figure 7-3. KBI Status and Control Register (KBISC) Table 7-3. KBISC Register Field Descriptions
Field 3 KBF 2 KBACK Description Keyboard Interrupt Flag — KBF indicates that a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected. Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag-clearing mechanism. KBACK always reads as 0.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 53
Chapter 7 Keyboard Interrupt (RS08KBIV1)
Table 7-3. KBISC Register Field Descriptions (continued)
Field 1 KBIE 0 KBMOD Description Keyboard Interrupt Enable — KBIE enables keyboard interrupt requests. 0 Keyboard interrupt request not enabled. 1 Keyboard interrupt request enabled. Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard interrupt pins. 0 Keyboard detects edges only. 1 Keyboard detects both edges and levels.
7.3.2
KBI Pin Enable Register (KBIPE)
KBIPE contains the pin enable control bits.
7 6 5 4 3 2 1 0
R W Reset:
0
0 KBIPE5 KBIPE4 0
0 KBIPE2 0 0 KBIPE1 0 KBIPE0 0
0
0
0
Figure 7-4. KBI Pin Enable Register (KBIPE) Table 7-4. KBIPE Register Field Descriptions
Field 5,4, 2:0 KBIPEn Description Keyboard Pin Enables — Each of the KBIPEn bits enables the corresponding keyboard interrupt pin. 0 Corresponding pin not enabled as keyboard interrupt. 1 Corresponding pin enabled as keyboard interrupt.
7.3.3
KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.
7 6 5 4 3 2 1 0
R W Reset:
0
0 KBEDG5 KBEDG4 0
0 KBEDG2 0 0 KBEDG1 0 KBEDG0 0
0
0
0
Figure 7-5. KBI Edge Select Register (KBIES) Table 7-5. KBIES Register Field Descriptions
Field 5,4, 2:0 KBEDGn Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin. 0 Falling edge/low level. 1 Rising edge/high level.
SC9RS08KA2 Series Data Sheet, Rev. 1 54 Freescale Semiconductor
Chapter 7 Keyboard Interrupt (RS08KBIV1)
7.4
Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because it was originally designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes. The KBI module allows its pins to act as additional interrupt sources. Writing to the KBIPEn bits in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES). Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle.
7.4.1
Edge Only Sensitivity
A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.
7.4.2
Edge and Level Sensitivity
A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC, provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK.
7.4.3
KBI Pullup/Pulldown Device
The KBI pins does not automatically configure an internal pullup/pulldown device when a KBI pin is enabled. An internal pull device can be used by configuring the associated I/O port pull device enable register (PTAPE) and pullup/pulldown control register (PTAPUD).
7.4.4
KBI Initialization
When a keyboard interrupt pin is first enabled, it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user should do the following: 1. Mask keyboard interrupts by clearing KBIE in KBISC. 2. If using internal pullup/pulldown device, configure the associated I/O port pullup/pulldown device. 3. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 55
Chapter 7 Keyboard Interrupt (RS08KBIV1)
5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts.
SC9RS08KA2 Series Data Sheet, Rev. 1 56 Freescale Semiconductor
Chapter 8 Central Processor Unit (RS08CPUV1)
8.1 Introduction
This chapter is a summary of information about the registers, addressing modes, and instruction set of the RS08 Family CPU. For a more detailed discussion, refer to the RS08 Core Reference Manual, volume 1, Freescale Semiconductor document order number RS08RMv1. The RS08 CPU has been developed to target extremely low-cost embedded applications using a process-independent design methodology, allowing it to keep pace with rapid developments in silicon processing technology. The main features of the RS08 core are: • Streamlined programmer’s model • Subset of HCS08 instruction set with minor instruction extensions • Minimal instruction set for cost-sensitive embedded applications • New instructions for shadow program counter manipulation, SHA and SLA • New short and tiny addressing modes for code size optimization • 16K bytes accessible memory space • Reset will fetch the first instruction from $3FFD • Low-power modes supported through the execution of the STOP and WAIT instructions • Debug and FLASH programming support using the background debug controller module • Illegal address and opcode detection with reset
8.2
Programmer’s Model and CPU Registers
Figure 8-1 shows the programmer’s model for the RS08 CPU. These registers are not located in the memory map of the microcontroller. They are built directly inside the CPU logic.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 57
Chapter 8 Central Processor Unit (RS08CPUV1)
7 ACCUMULATOR 13 13 SHADOW PROGRAM COUNTER 87 PROGRAM COUNTER
0 A 0 PC 0 SPC
CONDITION CODE REGISTER Z C CCR
CARRY ZERO
Figure 8-1. CPU Registers
In addition to the CPU registers, there are three memory mapped registers that are tightly coupled with the core address generation during data read and write operations. They are the indexed data register (D[X]), the index register (X), and the page select register (PAGESEL). These registers are located at $000E, $000F, and $001F, respectively.
7 0 INDEXED DATA REGISTER 7 INDEX REGISTER 7 PAGE SELECT REG 0 PAGESEL (location $001F) 0 X (location $000F) D[X] (location $000E)
Figure 8-2. Memory Mapped Registers
8.2.1
Accumulator (A)
This general-purpose 8-bit register is the primary data register for RS08 MCUs. Data can be read from memory into A with a load accumulator (LDA) instruction. The data in A can be written into memory with a store accumulator (STA) instruction. Various addressing mode variations allow a great deal of flexibility in specifying the memory location involved in a load or store instruction. Exchange instructions allow values to be exchanged between A and SPC high (SHA) and also between A and SPC low (SLA). Arithmetic, shift, and logical operations can be performed on the value in A as in ADD, SUB, RORA, INCA, DECA, AND, ORA, EOR, etc. In some of these instructions, such as INCA and LSLA, the value in A is the only input operand and the result replaces the value in A. In other cases, such as ADD and AND, there are two operands: the value in A and a second value from memory. The result of the arithmetic or logical operation replaces the value in A. Some instructions, such as memory-to-memory move instructions (MOV), do not use the accumulator. DBNZ also relieves A because it allows a loop counter to be implemented in a memory variable rather than the accumulator. During reset, the accumulator is loaded with $00.
SC9RS08KA2 Series Data Sheet, Rev. 1 58 Freescale Semiconductor
Chapter 8 Central Processor Unit (RS08CPUV1)
8.2.2
Program Counter (PC)
The program counter is a 14-bit register that contains the address of the next instruction or operand to be fetched. During normal execution, the program counter automatically increments to the next sequential memory location each time an instruction or operand is fetched. Jump, branch, and return operations load the program counter with an address other than that of the next sequential location. This is called a change-of-flow. During reset, the program counter is loaded with $3FFD and the program will start execution from this specific location.
8.2.3
Shadow Program Counter (SPC)
The shadow program counter is a 14-bit register. During a subroutine call using either a JSR or a BSR instruction, the return address will be saved into the SPC. Upon completion of the subroutine, the RTS instruction will restore the content of the program counter from the shadow program counter. During reset, the shadow program counter is loaded with $3FFD.
8.2.4
Condition Code Register (CCR)
The 2-bit condition code register contains two status flags. The content of the CCR in the RS08 is not directly readable. The CCR bits can be tested using conditional branch instructions such as BCC and BEQ. These two register bits are directly accessible through the BDC interface. The following paragraphs provide detailed information about the CCR bits and how they are used. Figure 8-3 identifies the CCR bits and their bit positions.
CONDITION CODE REGISTER ZC CCR
CARRY ZERO
Figure 8-3. Condition Code Register (CCR)
The status bits (Z and C) are cleared to 0 after reset. The two status bits indicate the results of arithmetic and other instructions. Conditional branch instructions will either branch to a new program location or allow the program to continue to the next instruction after the branch, depending on the values in the CCR status bit. Conditional branch instructions, such as BCC, BCS, and BNE, cause a branch depending on the state of a single CCR bit. Often, the conditional branch immediately follows the instruction that caused the CCR bit(s) to be updated, as in this sequence:
more: lower: cmp blo deca #5 lower ;compare accumulator A to 5 ;branch if A smaller 5 ;do this if A not higher than or same as 5
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 59
Chapter 8 Central Processor Unit (RS08CPUV1)
Other instructions may be executed between the test and the conditional branch as long as the only instructions used are those which do not disturb the CCR bits that affect the conditional branch. For instance, a test is performed in a subroutine or function and the conditional branch is not executed until the subroutine has returned to the main program. This is a form of parameter passing (that is, information is returned to the calling program in the condition code bits). Z — Zero Flag The Z bit is set to indicate the result of an operation was $00. Branch if equal (BEQ) and branch if not equal (BNE) are simple branches that branch based solely on the value in the Z bit. All load, store, move, arithmetic, logical, shift, and rotate instructions cause the Z bit to be updated. C — Carry After an addition operation, the C bit is set if the source operands were both greater than or equal to $80 or if one of the operands was greater than or equal to $80 and the result was less than $80. This is equivalent to an unsigned overflow. A subtract or compare performs a subtraction of a memory operand from the contents of a CPU register so after a subtract operation, the C bit is set if the unsigned value of the memory operand was greater than the unsigned value of the CPU register. This is equivalent to an unsigned borrow or underflow. Branch if carry clear (BCC) and branch if carry set (BCS) are branches that branch based solely on the value in the C bit. The C bit is also used by the unsigned branches BLO and BHS. Add, subtract, shift, and rotate instructions cause the C bit to be updated. The branch if bit set (BRSET) and branch if bit clear (BRCLR) instructions copy the tested bit into the C bit to facilitate efficient serial-to-parallel conversion algorithms. Set carry (SEC) and clear carry (CLC) allow the carry bit to be set or cleared directly. This is useful in combination with the shift and rotate instructions and for routines that pass status information back to a main program, from a subroutine, in the C bit. The C bit is included in shift and rotate operations so those operations can easily be extended to multi-byte operands. The shift and rotate operations can be considered 9-bit shifts that include an 8-bit operand or CPU register and the carry bit of the CCR. After a logical shift, C holds the bit that was shifted out of the 8-bit operand. If a rotate instruction is used next, this C bit is shifted into the operand for the rotate, and the bit that gets shifted out the other end of the operand replaces the value in C so it can be used in subsequent rotate instructions.
8.2.5
Indexed Data Register (D[X])
This 8-bit indexed data register allows the user to access the data in the direct page address space indexed by X. This register resides at the memory mapped location $000E. For details on the D[X] register, please refer to Section 8.3.8, “Indexed Addressing Mode (IX, Implemented by Pseudo Instructions).”
8.2.6
Index Register (X)
This 8-bit index register allows the user to index or address any location in the direct page address space. This register resides at the memory mapped location $000F. For details on the X register, please refer to Section 8.3.8, “Indexed Addressing Mode (IX, Implemented by Pseudo Instructions).”
SC9RS08KA2 Series Data Sheet, Rev. 1 60 Freescale Semiconductor
Chapter 8 Central Processor Unit (RS08CPUV1)
8.2.7
Page Select Register (PAGESEL)
This 8-bit page select register allows the user to access all memory locations in the entire 16K-byte address space through a page window located from $00C0 to $00FF. This register resides at the memory mapped location $001F. For details on the PAGESEL register, please refer to the RS08 Core Reference Manual.
8.3
Addressing Modes
Whenever the MCU reads information from memory or writes information into memory, an addressing mode is used to determine the exact address where the information is read from or written to. This section explains several addressing modes and how each is useful in different programming situations. Every opcode tells the CPU to perform a certain operation in a certain way. Many instructions, such as load accumulator (LDA), allow several different ways to specify the memory location to be operated on, and each addressing mode variation requires a separate opcode. All of these variations use the same instruction mnemonic, and the assembler knows which opcode to use based on the syntax and location of the operand field. In some cases, special characters are used to indicate a specific addressing mode (such as the # [pound] symbol, which indicates immediate addressing mode). In other cases, the value of the operand tells the assembler which addressing mode to use. For example, the assembler chooses short addressing mode instead of direct addressing mode if the operand address is from $0000 to $001F. Besides allowing the assembler to choose the addressing mode based on the operand address, assembler directives can also be used to force direct or tiny/short addressing mode by using the “>” or “ VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 109
Appendix A Electrical Characteristics
A.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table A-2. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance 6-pin DFN 1s 2s2p 8-pin PDIP 1s 2s2p 8-pin SOIC 1s 2s2p
1 1,2,3,4
Symbol TA TJMAX
Value TL to TH –40 to 85 105
Unit °C
°C
225 53 θJA 115 74 160 98 °C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s - Single Layer Board, one signal layer 4 2s2p - Four Layer Board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA) Eqn. A-1
where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O 2.3 V) (all digital inputs) Input low voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs) Input hysteresis (all digital inputs) Input leakage current (per pin) VIn = VDD or VSS, all input only pins High impedance (off-state) leakage current (per pin) VIn = VDD or VSS, all input/output Internal pullup/pulldown resistors2 (all port pins) Output high voltage (port A) IOH = –5 mA (VDD ≥ 4.5 V) IOH = –3 mA (VDD ≥ 3 V) IOH = –2 mA (VDD ≥ 1.8 V) Maximum total IOH for all port pins Output low voltage (port A) IOL = 5 mA (VDD ≥ 4.5 V) IOL = 3 mA (VDD ≥ 3 V) IOL = 2 mA (VDD ≥ 1.8 V) Maximum total IOL for all port pins dc injection current VIn < VSS, VIn > VDD Single pin limit Total MCU limit, includes sum of all stressed pins Input capacitance (all non-supply pins)
1 2 3 4 5 3, 4, 5 6
Symbol VIL VIL Vhys |IIn| |IOZ| RPU VOH
Min — — 0.06 × VDD — — 20
Typical — — — 0.025 0.025 45
Max 0.30 × VDD 0.30 × VDD — 1.0 1.0 65 — — — 40 0.8 0.8 0.8 40
Unit V V V μA μA kΩ
VDD – 0.8 —
—
V mA
|IOHT| VOL IOLT |IIC| CIn
—
—
—
V
—
—
mA
—
—
0.2 0.8 7
mA mA pF
—
—
6
This parameter is characterized and not tested on each device. Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped to VSS only. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. This parameter is characterized and not tested on each device.
SC9RS08KA2 Series Data Sheet, Rev. 1 112 Freescale Semiconductor
Appendix A Electrical Characteristics
Figure 12-8. Typical IOH vs. VDD-VOH VDD = 5 V
Figure 12-9. Typical IOH vs. VDD-VOH VDD = 3 V
Figure 12-10. Typical IOH vs. VDD-VOH VDD = 1.8 V
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 113
Appendix A Electrical Characteristics
Figure 12-11. Typical IOL vs. VOL VDD = 5 V
Figure 12-12. Typical IOL vs. VOL VDD = 3 V
Figure 12-13. Typical VDD-VOH vs. VDD at IOH=2mA
SC9RS08KA2 Series Data Sheet, Rev. 1 114 Freescale Semiconductor
Appendix A Electrical Characteristics
Figure 12-14. Typical VOL vs. VDD at IOL=2mA
A.6
Supply Current Characteristics
Table A-5. Supply Current Characteristics
Parameter Symbol RIDD10 VDD (V) 5 3 1.8 RIDD1 5 3 1.8 5 3 1.8 5 Typical1 5.6 mA 5.8 mA 4.7 mA 4.8 mA 2.3 mA 2.4 mA 1 mA 1.1 mA 0.9 mA 0.95 mA 0.6 mA 0.62 mA 1 μA 3 μA 0.9 μA 2.5 μA 0.7 μA 2 μA 20 μA Max2 6.5 mA 5.5 mA 3 mA 1.5 mA 1.2 mA 0.8 mA 2 μA 5 μA 2 μA 5 μA 2 μA 4 μA 30 μA Temp. (°C) 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85
Run supply current measured at (fBus = 10 MHz)
3
Run supply current measured at (fBus = 1.25 MHz)
3
SIDD Stop mode supply current
Bandgap buffer adder from stop (BGBE = 1)
—
3
20 μA
30 μA
25 85
1.8
20 μA
30 μA
25 85
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 115
Appendix A Electrical Characteristics
Table A-5. Supply Current Characteristics (continued)
Parameter Symbol VDD (V) 5 Typical1 15 μA Max2 20 μA Temp. (°C) 25 85 ACMP adder from stop (ACME = 1) — 3 15 μA 20 μA 25 85 1.8 15 μA 20 μA 25 85 5 RTI adder from stop with 1-kHz clock source enabled4 — 3 1.8 5 RTI adder from stop with 32-kHz ICS internal clock source reference enabled — 3 1.8 5 LVI adder from stop (LVDE=1 and LVDSE=1) — 3 1.8
1 2
300 nA 300 nA 300 nA 140 μA 140 μA 135 μA 70 μA 70 μA 65 μA
500 nA 500 nA 500 nA 165 μA 165 μA 160 μA 85 μA 85 μA 80 μA
25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85 25 85
Typicals are measured at 25°C. Maximum value is measured at the nominal VDD voltage times 10% tolerance. Values given here are preliminary estimates prior to completing characterization 3 Does not include any dc loads on port pins 4 Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode. Wait mode typical is 560 μA at 3 V and 422 μA at 2V with fBus = 1 MHz.
SC9RS08KA2 Series Data Sheet, Rev. 1 116 Freescale Semiconductor
Appendix A Electrical Characteristics
Figure 12-15. Typical Run IDD vs. VDD for FEI mode
A.7
Analog Comparator (ACMP) Electricals
Table A-6. Analog Comparator Electrical Specifications
Characteristic Symbol VDD VAIN RAS VAIO VH VBG IDDAC IALKG
1
Min 1.80 VSS – 0.3 — — 3.0 1.155 — — —
Typical — — — 20 9.0 1.190 20 — —
Max 5.5 VDD 10 40 15.0 1.230 35 1.0 1.0
Unit V V kΩ mV mV V μA μA μs
Supply voltage Analog input voltage Analog source impedance Analog input offset voltage1 Analog Comparator hysteresis1 Analog Comparator bandgap reference voltage1 Supply current (active)1 Analog input leakage current1 Analog Comparator initialization delay
1
tAINIT
These data are characterized but not production tested. Measurements are made with the device entered STOP mode.
A.8
Internal Clock Source Characteristics
Table A-7. Internal Clock Source Specifications
Characteristic Symbol fint_ft fint_ut fint_t fdco_ut fdco_t Δfdco_res_t Δfdco_t tacquire Min — 25 31.25 12.8 16 — — — Typ1 20 31.25 31.25 16 16 — — — Max — 41.66 39.0625 21.33 20 ±0.2 ±2 1 Unit MHz kHz kHz MHz MHz %fdco %fdco ms
Average internal reference frequency — factory trimmed at VDD = 5 V and temperature = 25°C Average internal reference frequency - untrimmed Average internal reference frequency - trimmed DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature Total deviation of trimmed DCO output frequency over voltage and temperature FLL acquisition time2,3
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 117
Appendix A Electrical Characteristics
Table A-7. Internal Clock Source Specifications
Characteristic Stop recovery time (FLL wakeup to previous acquired frequency) IREFSTEN=0 IREFSTEN=1
1 2
Symbol t_wakeup tir_wu tfll_wu
Min
Typ1
Max
Unit μs
—
100 86
—
Data in typical column was characterized at 3.0 V and 5.0 V, 25°C or is typical recommended value. This parameter is characterized and not tested on each device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
A.9
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.9.1
Control Timing
Table A-8. Control Timing
Parameter Symbol fBus tRTI textrst tKBIPW stop1 pF)3 tKBIPWS tRise, tFall Min dc 700 150 1.5 tcyc 100 — — Typical — 1000 — — — 11 35 Max 10 1300 — — — — — Unit MHz μs ns ns ns ns
Bus frequency (tcyc = 1/fBus) Real time interrupt internal oscillator period External RESET pulse KBI pulse width2 width1
KBI pulse width in
Port rise and fall time (load = 50 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
1
This is the shortest pulse that is guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized. 2 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 3 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
textrst RESET
Figure A-1. Reset Timing
SC9RS08KA2 Series Data Sheet, Rev. 1 118 Freescale Semiconductor
Appendix A Electrical Characteristics
tKBIPWS tKBIPW KBI Pin (rising or high level)
KBI Pin (falling or low level) tKBIPW tKBIPWS
Figure A-2. KBI Pulse Width
A.10
FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH memory. For detailed information about program/erase operations, see Chapter 4, “Memory.”
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 119
Appendix A Electrical Characteristics
Table A-9. FLASH Characteristics
Characteristic Supply voltage for program/erase Program/Erase voltage VPP current Program Mass erase Supply voltage for read operation 0 < fBus < 10 MHz Byte program time Mass erase time Cumulative program HV time2 Total cumulative HV time (total of tme & thv applied to device) HVEN to program setup time PGM/MASS to HVEN setup time HVEN hold time for PGM HVEN hold time for MASS VPP to PGM/MASS setup time HVEN to VPP hold time VPP rise time3 Recovery time Program/erase endurance TL to TH = –40°C to + 85°C Data retention
1 2
Symbol VDD VPP IVPP_prog IVPP_erase VRead tprog tme thv thv_total tpgs tnvs tnvh tnvh1 tvps tvph tvrs trcv — tD_ret
Min 2.7 11.8 — — 1.8 20 500 — — 10 5 5 100 20 20 200 1 1000 15
Typical1 — 12 — — — — — — — — — — — — — — — — 100
Max 5.5 12.2 200 100 5.5 40 — 8 2 — — — — — — — — — —
Unit V V μA μA V μs ms ms hours μs μs μs μs ns ns ns μs cycles years
Typicals are measured at 25°C. thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be programmed more than twice before next erase. 3 Fast V PP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP filter is shown in Figure A-3.
SC9RS08KA2 Series Data Sheet, Rev. 1 120 Freescale Semiconductor
Appendix A Electrical Characteristics
100 Ω VPP 12 V 1 nF
Figure A-3. Example VPP Filtering
tprog WRITE DATA1 tpgs
Data Next Data
PGM tnvs HVEN trs VPP2 tnvh trcv
tvps thv
tvph
1
2V
Next Data applies if programming multiple bytes in a single row, reference 4.6.2, “Flash Programming Procedure”. DD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure A-4. Flash Program Timing
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 121
Appendix A Electrical Characteristics
tme trcv MASS tnvs HVEN trs VPP1 tnvh1
tvps
tvph
1V
DD
must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure A-5. Flash Mass Erase Timing
SC9RS08KA2 Series Data Sheet, Rev. 1 122 Freescale Semiconductor
Appendix B Ordering Information and Mechanical Drawings
B.1 Ordering Information
This section contains ordering numbers for SC9RS08KA2 Series devices. See below for an example of the device numbering system.
Table B-1. Device Numbering System
Memory Device Number FLASH SC9RS08KA2 SC9RS08KA1 2 KB 1 KB RAM 63 bytes Type 6 DFN 8 PDIP 8 NB-SOIC Designator DB PC SC Document No. 98ARL10602D 98ASB42420B 98ASB42564B Package
SC 9 RS08 KA 2 J 3 C XX Status (SC = Semi-Customer) Memory (9 = FLASH-based) Core Family Package designator (See Table B-1) Temperature range (C = –40 °C to 85 ° C) (3 = Revision 3) (J = TSMC3) Memory designator (2 = 2 KB) (1 = 1 KB)
B.2
Mechanical Drawings
This following pages contain mechanical specifications for SC9RS08KA2 Series package options: • 6-pin DFN (dual flat no-lead) • 8-pin PDIP (plastic dual in-line pin) • 8-pin NB-SOIC (narrow body small outline integrated circuit)
SC9RS08KA2 Series Data Sheet, Rev. 1 Freescale Semiconductor 123
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Document Number: SC9RS08KA2 Rev. 1 9/2009
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