MC9S12XEP100 Reference Manual Covers MC9S12XE Family
HCS12 Microcontrollers
MC9S12XEP100 Rev. 1.07 05/2007
freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to the CPU S12 Reference Manual Version 2 .
Revision History
Date Oct, 2006 Revision Level 1.01 Description VREG, NVM electrical parameter updates Use of external regulator now prohibited Corrected package option code. Added dataflash to derivative table. Included revision history in module sections Removed internal text NVM timing parameters, PLL parameters. Minor typo corrections. NVM timing parameters and EEE description updated. EBI/NVM/IDD parameter updates Partnumber coding explanation updated in Appendix F Ex256 memory map correction ATD/PLL electricals updated Revised FTM section Version ID added to Part ID section EPROT/FPROT configuration field locations changed !! Various electricals updated following characterization Revised PIM section : corrected ATD pin mapping Revised INT section : software interrupt priorities changed Revised DBG section: NDB functionality, simultaneous arm and disarm Revised SEC section : added disclaimer, corrected backdoor key text Revised SPI section: typo fixes only Revised TIM section : removed redundant table, corrected bit name Revised FTM section: Updated security description.
Nov, 2006 Dec, 2006 Jan, 2007 Feb, 2007
1.02 1.03 1.04 1.05
Mar, 2007
1.06
May, 2007
1.07
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 Chapter 23
Device Overview MC9S12XE-Family. . . . . . . . . . . . . . . . . . . . . 21 Port Integration Module (S12XEPIMV1) . . . . . . . . . . . . . . . . . . 77 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . 177 Memory Protection Unit (S12XMPUV1) . . . . . . . . . . . . . . . . . 219 External Bus Interface (S12XEBIV4) . . . . . . . . . . . . . . . . . . . . 233 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . 271 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 297 Security (S12XE9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 XGATE (S12XGATEV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 S12XE Clocks and Reset Generator (S12XECRGV1) . . . . . . 469 Pierce Oscillator (S12XOSCLCPV2) . . . . . . . . . . . . . . . . . . . . 503 Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . 507 Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . . 533 Inter-Integrated Circuit (IICV3) . . . . . . . . . . . . . . . . . . . . . . . . 587 Scalable Controller Area Network (S12MSCANV3) . . . . . . . . 615 Periodic Interrupt Timer (S12PIT24B8CV1) . . . . . . . . . . . . . . 673 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . 693 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 725 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 763 Timer Module (TIM16B8CV2) . . . . . . . . . . . . . . . . . . . . . . . . . 793 Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . . 821 1024 KByte Flash Module (S12XFTM1024K5V2) . . . . . . . . . . 837
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
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Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 Appendix E Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 978 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
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Chapter 1Device Overview MC9S12XE-Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.5 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.4.4 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 1.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1.7 ATD0 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.8 ATD1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.9 MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.10 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.11 S12XEPIM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.12 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 2 Port Integration Module (S12XEPIMV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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2.2 2.3
2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . 102 S12X_EBI ports Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Module Routing Register (MODRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 2.3.57 2.3.58 2.3.59 2.3.60 2.3.61 2.3.62 2.3.63 2.3.64 2.3.65 2.3.66 2.3.67 2.3.68 2.3.69 2.3.70 2.3.71 2.3.72 2.3.73 2.3.74 2.3.75 2.3.76 2.3.77 2.3.78 2.3.79 2.3.80 2.3.81 2.3.82 2.3.83 2.3.84 2.3.85 2.3.86 2.3.87 2.3.88 2.3.89 2.3.90 2.3.91
Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Port AD0 Data Register 0 (PT0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Port AD0 Data Register 1 (PT1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Port AD0 Data Direction Register 0 (DDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Port AD0 Data Direction Register 1 (DDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Port AD0 Reduced Drive Register 0 (RDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Port AD0 Reduced Drive Register 1 (RDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Port AD0 Pull Up Enable Register 0 (PER0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Port AD0 Pull Up Enable Register 1 (PER1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Port AD1 Data Register 0 (PT0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Port AD1 Data Register 1 (PT1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Port AD1 Data Direction Register 0 (DDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Port AD1 Data Direction Register 1 (DDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Port AD1 Reduced Drive Register 0 (RDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Port AD1 Reduced Drive Register 1 (RDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Port AD1 Pull Up Enable Register 0 (PER0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Port AD1 Pull Up Enable Register 1 (PER1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Port R Data Register (PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Port R Input Register (PTIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Port R Data Direction Register (DDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Port R Reduced Drive Register (RDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Port R Pull Device Enable Register (PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Port R Polarity Select Register (PPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
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2.3.92 Port R Routing Register (PTRRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 2.3.93 Port L Data Register (PTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 2.3.94 Port L Input Register (PTIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 2.3.95 Port L Data Direction Register (DDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 2.3.96 Port L Reduced Drive Register (RDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2.3.97 Port L Pull Device Enable Register (PERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2.3.98 Port L Polarity Select Register (PPSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2.3.99 Port L Wired-Or Mode Register (WOML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2.3.100Port L Routing Register (PTLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 2.3.101Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 2.3.102Port F Input Register (PTIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.103Port F Data Direction Register (DDRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.104Port F Reduced Drive Register (RDRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 2.3.105Port F Pull Device Enable Register (PERF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.106Port F Polarity Select Register (PPSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 2.3.107PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 2.3.108Port F Routing Register (PTFRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Chapter 3 Memory Mapping Control (S12XMMCV4)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 3.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 3.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 3.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 3.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 3.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 3.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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3.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 4 Memory Protection Unit (S12XMPUV1)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 4.1.1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 4.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 4.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 4.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 4.4.1 Protection Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 4.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
4.2 4.3 4.4
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Chapter 5 External Bus Interface (S12XEBIV4)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.1.1 Glossary or Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 5.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 5.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 5.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 5.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 5.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 5.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 5.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
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Chapter 6 Interrupt (S12XINTV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
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6.5
6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 6.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 6.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 6.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 6.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 6.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Chapter 7 Background Debug Module (S12XBDMV2)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 7.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 7.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 7.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 7.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 7.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 7.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 7.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 7.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
7.2 7.3
7.4
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Chapter 8 S12X Debug (S12XDBGV3) Module
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 8.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 8.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 8.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 8.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 8.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 8.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.2 8.3
8.4
Chapter 9 Security (S12XE9SECV2)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 9.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 9.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 9.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 9.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 9.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Chapter 10 XGATE (S12XGATEV3)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 10.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 10.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
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10.5
10.6
10.7 10.8
10.9
10.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 10.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 10.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 10.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 10.6.2 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 10.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 10.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 10.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 10.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 10.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 10.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 10.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 10.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 10.9.3 Stack Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 11.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 11.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 11.2.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 11.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 11.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 11.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 11.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
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Chapter 12 Pierce Oscillator (S12XOSCLCPV2)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 12.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 504 12.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 12.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 13.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 13.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 14.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 14.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 14.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 535
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14.3.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.3.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 535 14.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 14.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 14.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 14.5.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 14.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 15.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 15.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 15.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 15.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 16.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
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16.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 16.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 16.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 16.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 16.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 16.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 16.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 16.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 16.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 16.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 16.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 17.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 17.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 17.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 17.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 17.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 17.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 17.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 17.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 17.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
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18.3
18.4
18.5 18.6
18.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 18.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 18.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 18.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 18.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Chapter 19 Serial Communication Interface (S12SCIV5)
19.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 19.2.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 19.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 19.2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 19.2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.3.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.3.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.4.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 19.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 19.5.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 19.5.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 19.5.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 19.5.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 19.5.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 19.5.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 19.5.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 19.5.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 19.6.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 19.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 19.6.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 19.6.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
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19.6.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Chapter 20 Serial Peripheral Interface (S12SPIV5)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 20.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 20.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 20.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 20.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 20.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 20.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 20.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 20.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 20.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 20.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 20.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 20.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Chapter 21 Timer Module (TIM16B8CV2) Block Description
21.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 21.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 21.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 21.2.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 21.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 21.3.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 796 21.3.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 797 21.3.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 797 21.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 21.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
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21.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 21.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 21.5.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 21.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 21.5.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 21.5.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 21.5.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 21.5.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 21.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 21.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 21.7.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 21.7.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 21.7.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 21.7.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Chapter 22 Voltage Regulator (S12VREGL3V3V1)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 22.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 22.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 22.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 824 22.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 22.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 825 22.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 22.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 22.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 825 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 22.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 22.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 22.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 22.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 22.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 22.4.6 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 22.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 22.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 22.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 22.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
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Chapter 23 1024 KByte Flash Module (S12XFTM1024K5V2)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 23.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 23.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 23.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 23.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 23.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875 23.4.3 .....Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 23.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.4.6 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 23.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 23.5.1 Flash Module Operation while Unsecure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 23.5.2 Flash Module Operation while Secure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 23.5.3 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 23.5.4 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 908 23.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908 23.6.1 Flash Reset Sequence - Core Hold Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 23.6.2 Flash Reset Sequence - Core Active Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 23.6.3 Error Handling during Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 23.6.4 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
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A.3
A.4 A.5
A.6
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 NVM, Flash and Emulated EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 A.3.2 NVM Reliability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 A.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 A.5.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 A.5.3 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 A.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 A.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 A.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 A.6.4 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 A.6.5 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 A.6.6 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Appendix B Package Information
B.1 B.2 B.3 B.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Appendix C PCB Layout Guidelines Appendix D Derivative Differences
D.1 Memory Sizes and Package Options S12XE - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 D.2 Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Appendix E Detailed Register Address Map
23.6.5 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Appendix F Ordering Information
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Chapter 1 Device Overview MC9S12XE-Family
1.1 Introduction
The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including new features for enhanced system integrity and greater functionality. These new features include a Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship MC9S12XE100. The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of compatibility between the S12XE and S12XD families. The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor which is programmable in “C” language and runs at twice the bus frequency of the S12X with an instruction set optimized for data movement, logic and bit manipulation instructions and which can service any peripheral module on the device. The new enhanced version has improved interrupt handling capability and is fully compatible with the existing XGATE module. The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM, eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit standard timer module (TIM). The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories. The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy interface to external memories. In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.
1.1.1
Features
Features of the MC9S12XE-Family are listed here. Please see Table D-1.for memory options and Table D-2. for the peripheral features that are available on the different family members. • 16-Bit CPU12X
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Chapter 1 Device Overview MC9S12XE-Family
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•
— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions (MEM, WAV, WAVR, REV, REVW) which have been removed — Enhanced indexed addressing — Access to large data segments independent of PPAGE INT (interrupt module) — Eight levels of nested interrupts — Flexible assignment of interrupt sources to each interrupt level. — External non-maskable high priority interrupt (XIRQ) — Internal non-maskable high priority Memory Protection Unit interrupt — Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts EBI (external bus interface)(available in 208-Pin and 144-Pin packages only) — Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces — Each chip select output can be configured to complete transaction on either the time-out of one of the two wait state generators or the deassertion of EWAIT signal MMC (module mapping control) DBG (debug module) — Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests — 64 x 64-bit circular trace buffer captures change-of-flow or memory access information BDM (background debug mode) MPU (memory protection unit) — 8 address regions definable per active program task — Address range granularity as low as 8-bytes — No write / No execute Protection Attributes — Non-maskable interrupt on access violation XGATE — Programmable, high performance I/O coprocessor module — Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states — Performs logical, shifts, arithmetic, and bit operations on data — Can interrupt the HCS12X CPU signalling transfer completion — Triggers from any hardware module as well as from the CPU possible — Two interrupt levels to service high priority tasks — Hardware support for stack pointer initialisation OSC_LCP (oscillator) — Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal — Good noise immunity — Full-swing Pierce option utilizing a 2MHz to 40MHz crystal — Transconductance sized for optimum start-up margin for typical crystals IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation) — No external components required
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Chapter 1 Device Overview MC9S12XE-Family
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•
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•
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) CRG (clock and reset generation) — COP watchdog — Real time interrupt — Clock monitor — Fast wake up from STOP in self clock mode Memory Options — 128K, 256k, 384K, 512K, 768K and 1M byte Flash — 2K, 4K byte emulated EEPROM — 12K, 16K, 24K, 32K, 48K and 64K Byte RAM Flash General Features — 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure correction and double fault detection — Erase sector size 1024 bytes — Automated program and erase algorithm D-Flash Features — Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access. — Dedicated commands to control access to the D-Flash memory over EEE operation. — Single bit fault correction and double bit fault detection within a word during read operations. — Automated program and erase algorithm with verify and generation of ECC parity bits. — Fast sector erase and word program operation. — Ability to program up to four words in a burst sequence Emulated EEPROM Features — Automatic EEE file handling using an internal Memory Controller. — Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset. — Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D-Flash memory. — Ability to disable EEE operation and allow priority access to the D-Flash memory. — Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory. Two 16-channel, 12-bit Analog-to-Digital Converters — 8/10/12 Bit resolution — 3µs, 10-bit single conversion time — Left/right, signed/unsigned result data — External and internal conversion trigger capability — Internal oscillator for conversion in Stop modes — Wake from low power modes on analog comparison > or 0), all valid EEE records from the D-Flash EEE partition will be copied to the buffer RAM EEE partition.
1.6.3.3
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
I/O Pins
Refer to the PIM block description for reset configurations of all peripheral module ports.
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Chapter 1 Device Overview MC9S12XE-Family
1.6.3.5
Memory
The RAM arrays are not initialized out of reset.
1.6.3.6
COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash register FOPT. See Table 1-14 and Table 1-15 for coding. The FOPT register is loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence. If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP reset.
Table 1-14. Initial COP Rate Configuration
NV[2:0] in FCTL Register 000 001 010 011 100 101 110 111 CR[2:0] in COPCTL Register 111 110 101 100 011 010 001 000
Table 1-15. Initial WCOP Configuration
NV[3] in FCTL Register 1 0 WCOP in COPCTL Register 0 1
1.7
ATD0 External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-16 shows the connection of the external trigger inputs.
Table 1-16. ATD0 External Trigger Sources
External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connectivity Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1
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Chapter 1 Device Overview MC9S12XE-Family
Consult the ATD block description for information about the analog-to-digital converter module. ATD block description refererences to freeze mode are equivalent to active BDM mode.
1.8
ATD1 External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger events. Table 1-17 shows the connection of the external trigger inputs.
Table 1-17. ATD1 External Trigger Sources
External Trigger Input ETRIG0 ETRIG1 ETRIG2 ETRIG3 Connectivity Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger 0 Periodic interrupt timer hardware trigger 1
Consult the ATD block description for information about the analog-to-digital converter module. ATD block description refererences to freeze mode are equivalent to active BDM mode.
1.9
MPU Configuration
The MPU has the option of a third bus master (CPU + XGATE + other) which is not present on this device family but may be on other parts.
1.10
VREG Configuration
The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage regulator is always enabled with VDDR connected to a positive supply voltage. The device must be configured with the internal voltage regulator enabled. Operation in conjunction with an external voltage regulator is not supported. The internal bandgap reference voltage is mapped to ATD0 analog input channel 17. The autonomus periodic interrupt clock output is mapped to PortT[5]. The API trimming register APITR is loaded on rising edge of RESET from the Flash IFR option field at global address 0x40_00F0 bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported. Read access to reserved VREG register space returns “0”. Wtite accesses have no effect. This device does not support access abort of reserved VREG register space.
1.11
S12XEPIM Configuration
On smaller derivatives the S12XEPIM module is a subset of the XEP100. The registers of the unavailable ports are unimplemented.
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Chapter 1 Device Overview MC9S12XE-Family
1.12
Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. For this device XCLKS is mapped to PE7. The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above described reset cases.
EXTAL C1 MCU XTAL C2 VSSPLL Crystal or Ceramic Resonator
Figure 1-9. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
EXTAL C1 MCU RS XTAL C2 RB=1MΩ ; RS specified by crystal vendor VSSPLL RB Crystal or Ceramic Resonator
Figure 1-10. Full Swing Pierce Oscillator Connections (XCLKS = 0)
EXTAL MCU XTAL
CMOS-Compatible External Oscillator
Not Connected
Figure 1-11. External Clock Connections (XCLKS = 0)
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Chapter 2 Port Integration Module (S12XEPIMV1)
Revision History
Rev. No. Date (Item No.) (Submitted By) V01.13 V01.14 V01.15 18 Jul 2006 01 Aug 2006 16 Apr 2007 Sections Affected 2.3.5/2-103 2.3.17/2-112 2.3.1/2-93 2.3.69/2-149 2.3.70/2-149 2.3.77/2-153 2.3.78/2-154 2.4.3.12/2-179 2.4.3.13/2-179 Substantial Change(s) Corrected DDRA address. Removed ‘PRR’ from IRQCR register. Revised PAD0 and PAD1 register bit names. Corrected ATD pin mappings
2.1
2.1.1
Introduction
Overview
The S12XE Family Port Integration Module establishes the interface between the peripheral modules including the non-multiplexed External Bus Interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. This document covers: • Port A and B used as address output of the S12X_EBI • Port C and D used as data I/O of the S12X_EBI • Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs • Port K associated with address output and control signals of the S12X_EBI • Port T associated with 1 ECT module • Port S associated with 2 SCI and 1 SPI modules • Port M associated with 4 MSCAN and 1 SCI module • Port P connected to the PWM and 2 SPI modules - inputs can be used as an external interrupt source • Port H associated with 4 SCI modules - inputs can be used as an external interrupt source • Port J associated with 1 MSCAN, 1 SCI, 2 IIC modules and chip select outputs - inputs can be used as an external interrupt source
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Chapter 2 Port Integration Module (S12XEPIMV1)
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Port AD0 and AD1 associated with two 16-channel ATD modules Port R associated with 1 stardard timer (TIM) module Port L associated with 4 SCI modules Port F associated with IIC, SCI and chip select outputs
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and select pull-up or pull-down devices. NOTE This document assumes the availabitity of all features (208-pin package option). Some functions are not available on lower pin count package options. Refer to the pin-out summary in the SOC Guide.
2.1.2
Features
The Port Integration Module includes these distinctive registers: • Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, AD1, R, L, and F when used as general-purpose I/O • Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P, H, J, R, L, and F on per-pin basis • Control registers to enable/disable pull-up devices on Ports AD0 and AD1 on per-pin basis • Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis and on BKGD pin • Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, AD1, R, L, and F on per-pin basis • Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on per-port basis • Control registers to enable/disable open-drain (wired-or) mode on Ports S, M, and L • Interrupt flag register for pin interrupts on Ports P, H, and J • Control register to configure IRQ pin operation • Free-running clock outputs A standard port pin has the following minimum features: • Input/output selection • 5V output drive with two selectable drive strengths • 5V digital and analog input • Input with selectable pull-up or pull-down device Optional features supported on dedicated pins: • • • Open drain for wired-or connections Interrupt inputs with glitch filtering Reduced input threshold to support low voltage applications
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.2
External Signal Description
This section lists and describes the signals that do connect off-chip. Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module. Refer to the SOC Guide for the availability of the individual pins in the different package options. NOTE If there is more than one function associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority).
Table 2-1. Pin Functions and Priorities
Port A Pin Name BKGD PA[7:0] Pin Function & Priority1 MODC 2 BKGD ADDR[15:8] mux IVD[15:8] 3 GPIO B PB[7:1] ADDR[7:1] mux IVD[7:1] 3 GPIO PB[0] ADDR[0] mux IVD0 3 UDS GPIO C PC[7:0] DATA[15:8] GPIO D PD[7:0] DATA[7:0] GPIO I/O I O Description MODC input during RESET High-order external bus address output (multiplexed with IVIS data) Pin Function after Reset BKGD Mode dependent 4
I/O S12X_BDM communication pin
I/O General-purpose I/O O Low-order external bus address output (multiplexed with IVIS data) Mode dependent 4
I/O General-purpose I/O O Low-order external bus address output (multiplexed with IVIS data) Upper data strobe Mode dependent 4 Mode dependent 4
O
I/O General-purpose I/O I/O High-order bidirectional data input/output Configurable for reduced input threshold I/O General-purpose I/O I/O Low-order bidirectional data input/output Configurable for reduced input threshold I/O General-purpose I/O
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port E
Pin Name PE[7]
Pin Function & Priority1 XCLKS 2 ECLKX2 GPIO
I/O I I I I
Description External clock selection input during RESET Free-running clock output at Core Clock rate (ECLK x 2) MODB input during RESET Instruction tagging low pin Configurable for reduced input threshold MODA input during RESET Read enable signal Instruction tagging low pin Configurable for reduced input threshold Free-running clock output at the Bus Clock rate or programmable divided in normal modes EROMON bit control input during RESET Low strobe bar output Lower data strobe Read/write output for external bus Write enable signal Maskable level- or falling edge-sensitive interrupt input General-purpose input Non-maskable level-sensitive interrupt input General-purpose input ROMON bit control input during RESET External Wait signal Configurable for reduced input threshold Extended external bus address output (multiplexed with access master output)
Pin Function after Reset Mode dependent 4
I/O General-purpose I/O
2
PE[6]
MODB
TAGHI GPIO PE[5] MODA RE TAGLO GPIO PE[4] ECLK GPIO PE[3] EROMCTL LSTRB LDS GPIO PE[2] RW WE GPIO PE[1] PE[0] K PK[7] IRQ GPI XIRQ GPI ROMCTL EWAIT GPIO PK[6:4] ADDR[22:20] mux ACC[2:0] 3 GPIO PK[3:0] ADDR[19:16] mux IQSTAT[3:0] 3 GPIO
2 2 2
I/O General-purpose I/O I O I
I/O General-purpose I/O O
I/O General-purpose I/O I O O O O I I I I I I
I/O General-purpose I/O
I/O General-purpose I/O
Mode dependent 3
I/O General-purpose I/O O
I/O General-purpose I/O O Extended external bus address output (multiplexed with instruction pipe status bits)
I/O General-purpose I/O
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port T
Pin Name PT[7]
Pin Function & Priority1 IOC[7] GPIO IOC[5]
I/O
Description
Pin Function after Reset GPIO
I/O Enhanced Capture Timer Channels 7 input/output I/O General-purpose I/O I/O Enhanced Capture Timer Channel 5 input/output O VREG Autonomous Periodical Interrupt output I/O General-purpose I/O I/O Enhanced Capture Timer Channels 4 - 0 input/output I/O General-purpose I/O I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode. I/O General-purpose I/O I/O Serial Peripheral Interface 0 serial clock pin I/O General-purpose I/O I/O Serial Peripheral Interface 0 master out/slave in pin I/O General-purpose I/O I/O Serial Peripheral Interface 0 master in/slave out pin I/O General-purpose I/O O I O I Serial Communication Interface 1 transmit pin Serial Communication Interface 1 receive pin Serial Communication Interface 0 transmit pin Serial Communication Interface 0 receive pin I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O
PT[5] PT[4:0] S PS7
VREG_API GPIO IOC[4:0] GPIO SS0 GPIO
GPIO
PS6 PS5 PS4 PS3 PS2 PS1 PS0
SCK0 GPIO MOSI0 GPIO MISO0 GPIO TXD1 GPIO RXD1 GPIO TXD0 GPIO RXD0 GPIO
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port M
Pin Name PM7
Pin Function & Priority1 TXCAN3 (TXCAN4) TXD3 GPIO
I/O O O O I I I O O O MSCAN3 transmit pin MSCAN4 transmit pin
Description
Pin Function after Reset GPIO
Serial Communication Interface 3 transmit pin MSCAN3 receive pin MSCAN4 receive pin Serial Communication Interface 3 receive pin MSCAN2 transmit pin MSCAN0 transmit pin MSCAN4 transmit pin
I/O General-purpose I/O
PM6
RXCAN3 (RXCAN4) RXD3 GPIO
I/O General-purpose I/O
PM5
TXCAN2 (TXCAN0) (TXCAN4) (SCK0)
I/O Serial Peripheral Interface 0 serial clock pin If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode. I/O General-purpose I/O I I I MSCAN2 receive pin MSCAN0 receive pin MSCAN4 receive pin
GPIO PM4 RXCAN2 (RXCAN0) (RXCAN4) (MOSI0)
I/O Serial Peripheral Interface 0 master out/slave in pin If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode. I/O General-purpose I/O O O MSCAN1 transmit pin MSCAN0 transmit pin
GPIO PM3 TXCAN1 (TXCAN0) (SS0) GPIO PM2 RXCAN1 (RXCAN0) (MISO0) GPIO PM1 PM0 TXCAN0 GPIO RXCAN0 GPIO
I/O Serial Peripheral Interface 0 slave select output in master mode, input for slave mode or master mode. I/O General-purpose I/O I I MSCAN1 receive pin MSCAN0 receive pin
I/O Serial Peripheral Interface 0 master in/slave out pin I/O General-purpose I/O O I MSCAN0 transmit pin MSCAN0 receive pin I/O General-purpose I/O I/O General-purpose I/O
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port P
Pin Name PP7
Pin Function & Priority1 PWM7 SCK2 (TIMIOC7) GPIO/KWP7
I/O
Description
Pin Function after Reset GPIO
I/O Pulse Width Modulator input/output channel 7 I/O Serial Peripheral Interface 2 serial clock pin I/O Timer Channel 7 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 6 I/O Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode. I/O Timer Channel 6 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 5 I/O Serial Peripheral Interface 2 master out/slave in pin I/O Timer Channel 5 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 4 I/O Serial Peripheral Interface 2 master in/slave out pin I/O Timer Channel 4 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 3 I/O Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. I/O Timer Channel 3 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 2 I/O Serial Peripheral Interface 1 serial clock pin I/O Timer Channel 2 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 1 I/O Serial Peripheral Interface 1 master out/slave in pin I/O Timer Channel 1 input/output I/O General-purpose I/O with interrupt O Pulse Width Modulator output channel 0 I/O Serial Peripheral Interface 1 master in/slave out pin I/O Timer Channel 0 input/output I/O General-purpose I/O with interrupt
PP6
PWM6 SS2 (TIMIOC6) GPIO/KWP6
PP5
PWM5 MOSI2 (TIMIOC5) GPIO/KWP5
PP4
PWM4 MISO2 (TIMIOC4) GPIO/KWP4
PP3
PWM3 SS1 (TIMIOC3) GPIO/KWP3
PP2
PWM2 SCK1 (TIMIOC2) GPIO/KWP2
PP1
PWM1 MOSI1 (TIMIOC1) GPIO/KWP1
PP0
PWM0 MISO1 (TIMIOC0) GPIO/KWP0
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port H
Pin Name PH7
Pin Function & Priority1 (SS2) TXD5 GPIO/KWH7
I/O
Description
Pin Function after Reset GPIO
I/O Serial Peripheral Interface 2 slave select output in master mode, input for slave mode or master mode O Serial Communication Interface 5 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 2 serial clock pin I Serial Communication Interface 5 receive pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 2 master out/slave in pin O Serial Communication Interface 4 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 2 master in/slave out pin I Serial Communication Interface 4 receive pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 slave select output in master mode, input for slave mode or master mode. O Serial Communication Interface 7 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 serial clock pin I Serial Communication Interface 7 receive pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 master out/slave in pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt I/O Serial Peripheral Interface 1 master in/slave out pin O Serial Communication Interface 6 transmit pin I/O General-purpose I/O with interrupt
PH6
(SCK2) RXD5 GPIO/KWH6
PH5
(MOSI2) TXD4 GPIO/KWH5
PH4
(MISO2) RXD4 GPIO/KWH4
PH3
(SS1) TXD7 GPIO/KWH3
PH2
(SCK1) RXD7 GPIO/KWH2
PH1
(MOSI1) TXD6 GPIO/KWH1
PH0
(MISO1) TXD6 GPIO/KWH0
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port J
Pin Name PJ7
Pin Function & Priority1 TXCAN4 SCL0 (TXCAN0) GPIO/KWJ7
I/O O O O I I O O MSCAN4 transmit pin
Description
Pin Function after Reset GPIO
Inter Integrated Circuit 0 serial clock line MSCAN0 transmit pin MSCAN4 receive pin MSCAN0 receive pin Inter Integrated Circuit 1 serial clock line Chip select 2
I/O General-purpose I/O with interrupt I/O Inter Integrated Circuit 0 serial data line I/O General-purpose I/O with interrupt
PJ6
RXCAN4 SDA0 (RXCAN0) GPIO/KWJ6
PJ5
SCL1 CS2 GPIO/KWJ5
I/O General-purpose I/O with interrupt I/O Inter Integrated Circuit 1 serial data line O Chip select 0 I/O General-purpose I/O with interrupt I/O General-purpose I/O with interrupt O O I O Chip select 1 Serial Communication Interface 2 transmit pin Serial Communication Interface 2 receive pin Chip select 3 GPIO GPIO GPIO I/O General-purpose I/O with interrupt I/O General-purpose I/O with interrupt
PJ4
SDA1 CS0 GPIO/KWJ4
PJ3 PJ2 PJ1 PJ0
GPIO/KWJ3 CS1 GPIO/KWJ2 TXD2 GPIO/KWJ1 RXD2 CS3 GPIO/KWJ0
I/O General-purpose I/O with interrupt I/O General-purpose I/O I I ATD0 analog inputs ATD1 analog inputs I/O General-purpose I/O I/O Timer Channels 7- 0 input/output I/O General-purpose I/O
AD0
PAD[15:0]
GPIO AN[15:0] GPIO AN[15:0] TIMIOC[7:0] GPIO
AD1 PAD[31:16] R PR[7:0]
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port L
Pin Name PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
Pin Function & Priority1 (TXD7) GPIO (RXD7) GPIO (TXD6) GPIO (RXD6) GPIO (TXD5) GPIO (RXD5) GPIO (TXD4) GPIO (RXD4) GPIO (TXD3) GPIO (RXD3) GPIO (SCL0) GPIO (SDA0) GPIO (CS3) GPIO (CS2) GPIO (CS1) GPIO (CS0) GPIO
I/O O I O I O I O I O I O
Description Serial Communication Interface 7 transmit pin Serial Communication Interface 7 receive pin Serial Communication Interface 6 transmit pin Serial Communication Interface 6 receive pin Serial Communication Interface 5 transmit pin Serial Communication Interface 5 receive pin Serial Communication Interface 4 transmit pin Serial Communication Interface 4 receive pin Serial Communication Interface 3 transmit pin Serial Communication Interface 3 receive pin Inter Integrated Circuit 0 serial clock line
Pin Function after Reset GPIO
I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O GPIO I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O Inter Integrated Circuit 0 serial data line I/O General-purpose I/O O O O O Chip select 3 Chip select 2 Chip select 1 Chip select 0 I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O I/O General-purpose I/O
F
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
1 2
Signals in brackets denote alternative module routing pins. Function active when RESET asserted. 3 Only available in emulation modes or in Special Test Mode with IVIS on. 4 Refer to S12X_EBI section.
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.1
Register Name 0x0000 PORTA 0x0001 PORTB 0x0002 DDRA 0x0003 DDRB 0x0004 PORTC 0x0005 PORTD 0x0006 DDRC 0x0007 DDRD 0x0008 PORTE 0x0009 DDRE
Memory Map
Bit 7 R W R W R W R W R W R W R W R W R W R W PA7
6 PA6
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
Bit 0 PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1 PE1
DDRD0 PE0
PE7
PE6
PE5
PE4
PE3
PE2
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
0x000A R 0x000B W Non-PIM Address Range 0x000C PUCR 0x000D RDRIV R W R W PUPKE BKPUE 0 0
Non-PIM Address Range
PUPEE
PUPDE
PUPCE
PUPBE
PUPAE
RDPK
0
RDPE
RDPD
RDPC
RDPB
RDPA
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name 0x000E– R 0x001B W Non-PIM Address Range 0x001C R ECLKCTL W 0x001D R Reserved W 0x001E IRQCR 0x001F Reserved R W R W
Bit 7
6
5
4
3
2
1
Bit 0
Non-PIM Address Range
NECLK 0
NCLKX2 0
DIV16 0
EDIV4 0
EDIV3 0
EDIV2 0
EDIV1 0
EDIV0 0
IRQE 0
IRQEN 0
0
0
0
0
0
0
0
0
0
0
0
0
0x0020– R 0x0031 W Non-PIM Address Range 0x0032 PORTK 0x0033 DDRK R W R W PK7 PK6 PK5
Non-PIM Address Range
PK4
PK3
PK2
PK1
PK0
DDRK7
DDRK6
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
0x0034– R 0x023F W Non-PIM Address Range 0x0240 PTT 0x0241 PTIT 0x0242 DDRT 0x0243 RDRT R W R W R W R W DDRT7 DDRT6 DDRT5 PTT7 PTIT7 PTT6 PTIT6 PTT5 PTIT5
Non-PIM Address Range
PTT4 PTIT4
PTT3 PTIT3
PTT2 PTIT2
PTT1 PTIT1
PTT0 PTIT0
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name 0x0244 PERT 0x0245 PPST R W R W
Bit 7 PERT7
6 PERT6
5 PERT5
4 PERT4
3 PERT3
2 PERT2
1 PERT1
Bit 0 PERT0
PPST7 0
PPST6 0
PPST5 0
PPST4 0
PPST3 0
PPST2 0
PPST1 0
PPST0 0
0x0246 R Reserved W 0x0247 R Reserved W 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS R W R W R W R W R W R W R W
0
0
0
0
0
0
0
0
PTS7 PTIS7
PTS6 PTIS6
PTS5 PTIS5
PTS4 PTIS4
PTS3 PTIS3
PTS2 PTIS2
PTS1 PTIS1
PTS0 PTIS0
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7 0
WOMS6 0
WOMS5 0
WOMS4 0
WOMS3 0
WOMS2 0
WOMS1 0
WOMS0 0
0x024F R Reserved W 0x0250 PTM 0x0251 PTIM 0x0252 DDRM R W R W R W
PTM7 PTIM7
PTM6 PTIM6
PTM5 PTIM5
PTM4 PTIM4
PTM3 PTIM3
PTM2 PTIM2
PTM1 PTIM1
PTM0 PTIM0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 MODRR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP 0x0260 PTH 0x0261 PTIH 0x0262 DDRH R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 RDRM7
6 RDRM6
5 RDRM5
4 RDRM4
3 RDRM3
2 RDRM2
1 RDRM1
Bit 0 RDRM0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM7 0
WOMM6
WOMM5
WOMM4
WOMM3
WOMM2
WOMM1
WOMM0
MODRR6
MODRR5
MODRR4
MODRR3
MODRR2
MODRR1
MODRR0
PTP7 PTIP7
PTP6 PTIP6
PTP5 PTIP5
PTP4 PTIP4
PTP3 PTIP3
PTP2 PTIP2
PTP1 PTIP1
PTP0 PTIP0
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
PTH7 PTIH7
PTH6 PTIH6
PTH5 PTIH5
PTH4 PTIH4
PTH3 PTIH3
PTH2 PTIH2
PTH1 PTIH1
PTH0 PTIH0
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
= Unimplemented or Reserved
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Register Name 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 PT0AD0 0x0271 PT1AD0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
6
5
4
3
2
1
Bit 0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
PTJ7 PTIJ7
PTJ6 PTIJ6
PTJ5 PTIJ5
PTJ4 PTIJ4
PTJ3 PTIJ3
PTJ2 PTIJ2
PTJ1 PTIJ1
PTJ0 PTIJ0
DDRJ7
DDRJ6
DDRJ5
DDRJ4
DDRJ3
DDRJ2
DDRJ1
DDRJ0
RDRJ7
RDRJ6
RDRJ5
RDRJ4
RDRJ3
RDRJ2
RDRJ1
RDRJ0
PERJ7
PERJ6
PERJ5
PERJ4
PERJ3
PERJ2
PERJ1
PERJ0
PPSJ7
PPSJ6
PPSJ5
PPSJ4
PPSJ3
PPSJ2
PPSJ1
PPSJ0
PIEJ7
PIEJ6
PIEJ5
PIEJ4
PIEJ3
PIEJ2
PIEJ1
PIEJ0
PIFJ7
PIFJ6
PIFJ5
PIFJ4
PIFJ3
PIFJ2
PIFJ1
PIFJ0
PT0AD07
PT0AD06
PT0AD05
PT0AD04
PT0AD03
PT0AD02
PT0AD01
PT0AD00
PT1AD07
PT1AD06
PT1AD05
PT1AD04
PT1AD03
PT1AD02
PT1AD01
PT1AD00
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0272 R DDR0AD0 W DDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00 0x0273 R DDR1AD0 W DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0x0274 R RDR0AD0 W RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00 0x0275 R RDR1AD0 W RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0x0276 R PER0AD0 W PER0AD07 0x0277 R PER1AD0 W PER1AD07 0x0278 PT0AD1 0x0279 PT1AD1 R W R W PT0AD17 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00
PER1AD06
PER1AD05
PER1AD04
PER1AD03
PER1AD02
PER1AD01
PER1AD00
PT0AD16
PT0AD15
PT0AD14
PT0AD13
PT0AD12
PT0AD11
PT0AD10
PT1AD17
PT1AD16
PT1AD15
PT1AD14
PT1AD13
PT1AD12
PT1AD11
PT1AD10
0x027A R DDR0AD1 W DDR0AD17 DDR0AD16 DDR0AD15 DDR0AD14 DDR0AD13 DDR0AD12 DDR0AD11 DDR0AD10 0x027B R DDR1AD1 W DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD12 DDR1AD11 DDR1AD10 0x027C R RDR0AD1 W RDR0AD17 RDR0AD16 RDR0AD15 RDR0AD14 RDR0AD13 RDR0AD12 RDR0AD11 RDR0AD10 0x027D R RDR1AD1 W RDR1AD17 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD13 RDR1AD12 RDR1AD11 RDR1AD10 0x027E R PER0AD1 W PER0AD17 0x027F R PER1AD1 W PER1AD17 0x0280– R 0x0267 W Non-PIM Address Range PER0AD16 PER0AD15 PER0AD14 PER0AD13 PER0AD12 PER0AD1‘ PER0AD10
PER1AD16
PER1AD15
PER1AD14
PER1AD13
PER1AD12
PER1AD11
PER1AD10
Non-PIM Address Range
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name 0x0368 PTR 0x0369 PTIR 0x036A DDRR 0x036B RDRR 0x036C PERR 0x036D PPSR R W R W R W R W R W R W
Bit 7 PTR7 PTIR7
6 PTR6 PTIR6
5 PTR5 PTIR5
4 PTR4 PTIR4
3 PTR3 PTIR3
2 PTR2 PTIR2
1 PTR1 PTIR1
Bit 0 PTR0 PTIR0
DDRR7
DDRR6
DDRR5
DDRR4
DDRR3
DDRR2
DDRR1
DDRR0
RDRR7
RDRR6
RDRR5
RDRR4
RDRR3
RDRR2
RDRR1
RDRR0
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
PPSR7 0
PPSR6 0
PPSR5 0
PPSR4 0
PPSR3 0
PPSR2 0
PPSR1 0
PPSR0 0
0x036E R Reserved W 0x036F PTRRR 0x0370 PTL 0x0371 PTIL 0x0372 DDRL 0x0373 RDRL 0x0374 PERL 0x0375 PPSL 0x0376 WOML 0x0377 PTLRR R W R W R W R W R W R W R W R W R W
PTRRR7
PTRRR6
PTRRR5
PTRRR4
PTRRR3
PTRRR2
PTRRR1
PTRRR0
PTL7 PTIL7
PTL6 PTIL6
PTL5 PTIL5
PTL4 PTIL4
PTL3 PTIL3
PTL2 PTIL2
PTL1 PTIL1
PTL0 PTIL0
DDRL7
DDRL6
DDRL5
DDRL4
DDRL3
DDRL2
DDRL1
DDRL0
RDRL7
RDRL6
RDRL5
RDRL4
RDRL3
RDRL2
RDRL1
RDRL0
PERL7
PERL6
PERL5
PERL4
PERL3
PERL2
PERL1
PERL0
PPSL7
PPSL6
PPSL5
PPSL4
PPSL3
PPSL2
PPSL1
PPSL0
WOML7
WOML6
WOML5
WOML4
WOML3 0
WOML2 0
WOML1 0
WOML0 0
PTLRR7
PTLRR6
PTLRR5
PTLRR4
= Unimplemented or Reserved MC9S12XE-Family Reference Manual Rev. 1.07 Freescale Semiconductor 99
Chapter 2 Port Integration Module (S12XEPIMV1)
Register Name 0x0378 PTF 0x0379 PTIF 0x037A DDRF 0x037B RDRF 0x037C PERF 0x037D PPSF R W R W R W R W R W R W
Bit 7
6
5
4
3
2
1
Bit 0
PTF7 PTIF7
PTF6 PTIF6
PTF5 PTIF5
PTF4 PTIF4
PTF3 PTIF3
PTF2 PTIF2
PTF1 PTIF1
PTF0 PTIF0
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
RDRF7
RDRF6
RDRF5
RDRF4
RDRF3
RDRF2
RDRF1
RDRF0
PERF7
PERF6
PERF5
PERF4
PERF3
PERF2
PERF1
PERF0
PPSF7 0
PPSF6 0
PPSF5 0
PPSF4 0
PPSF3 0
PPSF2 0
PPSF1 0
PPSF0 0
0x037E R Reserved W 0x037F PTFRR R W
0
0
PTFRR5
PTFRR4
PTFRR3
PTFRR2
PTFRR1
PTFRR0
= Unimplemented or Reserved
2.3.2
Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull device activity. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active.
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Table 2-2. Pin Configuration Summary
DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 2
IO x x x x x x x 0 1 0 1 0 1 0 1
RDR x x x x x x x 0 0 1 1 0 0 1 1
PE 0 1 1 0 0 1 1 x x x x x x x x
PS1 x 0 1 0 1 0 1 x x x x 0 1 0 1
IE2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Input Input Input Input Input Input Input
Function
Pull Device Disabled Pull Up Pull Down Disabled Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Interrupt Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge Disabled Disabled Disabled Disabled Falling edge Rising edge Falling edge Rising edge
Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1 Output, full drive to 0 Output, full drive to 1 Output, reduced drive to 0 Output, reduced drive to 1
Always “0” on Port A, B, C, D, E, K, AD0, and AD1. Applicable only on Port P, H, and J.
NOTE All register bits in this module are completely synchronous to internal clocks during a register read.
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2.3.3
Port A Data Register (PORTA)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0000 (PRR)
7
R PA7 W Altern. Function ADDR15 mux IVD15 0 ADDR14 mux IVD14 0 ADDR13 mux IVD13 0 ADDR12 mux IVD12 0 ADDR11 mux IVD11 0 ADDR10 mux IVD10 0 ADDR9 mux IVD9 0 ADDR8 mux IVD8 0 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Reset
Figure 2-1. Port A Data Register (PORTA)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-3. PORTA Register Field Descriptions
Field 7-0 PA Description Port A general purpose input/output data—Data Register Port A pins 7 through 0 are associated with address outputs ADDR[15:8] respectively in expanded modes. In emulation modes the address is multiplexed with IVD[15:8]. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.4
Port B Data Register (PORTB)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0001 (PRR)
7
R PB7 W Altern. Function ADDR0 mux IVD0 or UDS 0 PB6 PB5 PB4 PB3 PB2 PB1 PB0
ADDR7 mux IVD7
ADDR6 mux IVD6
ADDR5 mux IVD5
ADDR4 mux IVD4
ADDR3 mux IVD3
ADDR2 mux IVD2
ADDR1 mux IVD1
Reset
0
0
0
0
0
0
0
Figure 2-2. Port B Data Register (PORTB)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
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Table 2-4. PORTB Register Field Descriptions
Field 7-0 PB Description Port B general purpose input/output data—Data Register Port B pins 7 through 0 are associated with address outputs ADDR[7:0] respectively in expanded modes. In emulation modes the address is multiplexed with IVD[7:0]. In normal expanded mode pin 0 is related to the UDS input. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.5
Port A Data Direction Register (DDRA)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0002 (PRR)
7
R DDRA7 W Reset 0 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Figure 2-3. Port A Data Direction Register (DDRA)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-5. DDRA Register Field Descriptions
Field 7-0 DDRA Description Port A Data Direction— This register controls the data direction of pins 7 through 0. The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
2.3.6
Port B Data Direction Register (DDRB)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0003 (PRR)
7
R DDRB7 W Reset 0 0 0 0 0 0 0 0 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Figure 2-4. Port B Data Direction Register (DDRB)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-6. DDRB Register Field Descriptions
Field 7-0 DDRB Description Port B Data Direction— This register controls the data direction of pins 7 through 0. The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
2.3.7
Port C Data Register (PORTC)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0004 (PRR)
7
R PC7 W Altern. Function Reset DATA15 0 DATA14 0 DATA13 0 DATA12 0 DATA11 0 DATA10 0 DATA9 0 DATA8 0 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Figure 2-5. Port C Data Register (PORTC)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-7. PORTC Register Field Descriptions
Field 7-0 PC Description Port C general purpose input/output data—Data Register Port C pins 7 through 0 are associated with data I/O lines DATA[15:8] respectively in expanded modes. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.8
Port D Data Register (PORTD)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0005 (PRR)
7
R PD7 W Altern. Function Reset DATA7 0 DATA6 0 DATA5 0 DATA4 0 DATA3 0 DATA2 0 DATA1 0 DATA0 0 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Figure 2-6. Port D Data Register (PORTD)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-8. PORTD Register Field Descriptions
Field 7-0 PD Description Port D general purpose input/output data—Data Register Port D pins 7 through 0 are associated with data I/O lines DATA[7:0] respectively in expanded modes. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.9
Port C Data Direction Register (DDRC)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0006 (PRR)
7
R DDRC7 W Reset 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Figure 2-7. Port C Data Direction Register (DDRC)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-9. DDRC Register Field Descriptions
Field 7-0 DDRC Description Port C Data Direction— This register controls the data direction of pins 7 through 0. The external bus function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
2.3.10
Port D Data Direction Register (DDRD)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0007 (PRR)
7
R DDRD7 W Reset 0 0 0 0 0 0 0 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Figure 2-8. Port D Data Direction Register (DDRD)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-10. DDRD Register Field Descriptions
Field 7-0 DDRD Description Port D Data Direction— This register controls the data direction of pins 7 through 0. When used with the external bus this function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.11
Port E Data Register (PORTE)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0008 (PRR)
7
R PE7 W Altern. Function MODA or RE or TAGLO 0 EROMCTL or LSTRB or LDS 0 PE6 PE5 PE4 PE3 PE2
PE1
PE0
XCLKS or ECLKX2
MODB or TAGHI
ECLK
RW or WE
IRQ
XIRQ
Reset
0
0
0
0
—2
—2
= Unimplemented or Reserved
Figure 2-9. Port E Data Register (PORTE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 2 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values.
1
Table 2-11. PORTE Register Field Descriptions
Field 7-0 PE Description Port E general purpose input/output data—Data Register Port E bits 7 through 0 are associated with external bus control signals and interrupt inputs. These include mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI, TAGLO), Read/Write (RW), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ. When not used with the alternative functions, Port E pins 7-2 can be used as general purpose I/O and pins 1-0 can be used as general purpose inputs. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low. Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
2.3.12
Port E Data Direction Register (DDRE)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0009 (PRR)
7
R DDRE7 W Reset 0 0 0 0 0 0 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2
0
0
0
0
= Unimplemented or Reserved
Figure 2-10. Port E Data Direction Register (DDRE)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-12. DDRE Register Field Descriptions
Field 7-2 DDRE Description Port E Data Direction— This register controls the data direction of pins 7 through 2. The external bus function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input. Reserved— Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
1-0
2.3.13
S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x000C (PRR)
7
R PUPKE W Reset 1 1 BKPUE
0 PUPEE 0 1 PUPDE 0 PUPCE 0 PUPBE 0 PUPAE 0
= Unimplemented or Reserved
Figure 2-11. S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
1
Read:Anytime in single-chip modes. Write:Anytime, except BKPUE which is writable in Special Test Mode only.
Table 2-13. PUCR Register Field Descriptions
Field 7 PUPKE Description Pull-up Port K Enable—Enable pull-up devices on all Port K input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are enabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. BKGD pin pull-up Enable—Enable pull-up devices on BKGD pin This bit configures whether a pull-up device is activated, if the pin is used as input. This bit has no effect if the pin is used as outputs. Out of reset the pull-up device is enabled. 1 Pull-up device enabled. 0 Pull-up device disabled. Reserved—
6 BKPUE
5
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Table 2-13. PUCR Register Field Descriptions (continued)
Field 4 PUPEE Description Pull-up Port E Enable—Enable pull-up devices on all Port E input pins except on pins 5 and 6 which have pull-down devices only enabled during reset. This bit has no effect on these pins. This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are enabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Pull-up Port D Enable—Enable pull-up devices on all Port D input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Pull-up Port C Enable—Enable pull-up devices on all Port C input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Pull-up Port B Enable—Enable pull-up devices on all Port B input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled. Pull-up Port A Enable—Enable pull-up devices on all Port A input pins This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the pins are used as outputs. Out of reset the pull-up devices are disabled. 1 Pull-up devices enabled. 0 Pull-up devices disabled.
3 PUPDE
2 PUPCE
1 PUPBE
0 PUPAE
2.3.14
S12X_EBI ports Reduced Drive Register (RDRIV)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x000D (PRR)
7
R RDPK W Reset 0
0
0 RDPE RDPD 0 RDPC 0 RDPB 0 RDPA 0
0
0
0
= Unimplemented or Reserved
Figure 2-12. S12X_EBI ports Reduced Drive Register (RDRIV)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to select reduced drive for the pins associated with the S12X_EBI ports A, B, C, D, E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is independent of which function is being used on a particular pin.
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The reduced drive functionality does not take effect on the pins in emulation modes.
Table 2-14. RDRIV Register Field Descriptions
Field 7 RDPK Description Port K reduced drive—Select reduced drive for outputs This bit configures the drive strength of all Port K output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Reserved— Port E reduced drive—Select reduced drive for outputs This bit configures the drive strength of all Port E output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Port D reduced drive—Select reduced drive for outputs This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Port C reduced drive—Select reduced drive for outputs This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Port B reduced drive—Select reduced drive for outputs This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. Port A reduced drive—Select reduced drive for outputs This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
6-5 4 RDPE
3 RDPD
2 RDPC
1 RDPB
0 RDPA
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2.3.15
ECLK Control Register (ECLKCTL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x001C (PRR)
7
R NECLK W
2
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
Reset :
Mode Dependent 0 1 0 0 1 0
1
0
0
0
0
0
0
SS ES ST EX NS NX
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
= Unimplemented or Reserved
Figure 2-13. ECLK Control Register (ECLKCTL)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 2 Reset values in emulation modes are identical to those of the target mode.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider.
Table 2-15. ECLKCTL Register Field Descriptions
Field 7 NECLK Description No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes. 1 ECLK disabled 0 ECLK enabled No ECLKX2—Disable ECLKX2 output This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal Bus Clock. Clock output is always active in emulation modes and if enabled in all other operating modes. 1 ECLKX2 disabled 0 ECLKX2 enabled
6 NCLKX2
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-15. ECLKCTL Register Field Descriptions (continued)
Field 5 DIV16 Description Free-running ECLK predivider—Divide by 16 This bit enables a divide-by-16 stage on the selected EDIV rate. 1 Divider enabled: ECLK rate = EDIV rate divided by 16 0 Divider disabled: ECLK rate = EDIV rate Free-running ECLK Divider—Configure ECLK rate These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation modes and active as programmed in all other operating modes. 00000 ECLK rate = Bus Clock rate 00001 ECLK rate = Bus Clock rate divided by 2 00010 ECLK rate = Bus Clock rate divided by 3, ... 11111 ECLK rate = Bus Clock rate divided by 32
4-0 EDIV
2.3.16
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
Address 0x001D (PRR)
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-14. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
2.3.17
IRQ Control Register (IRQCR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x001E
7
R IRQE W Reset 0 1 IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-15. IRQ Control Register (IRQCR)
1
Read: See individual bit descriptions below. Write: See individual bit descriptions below.
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-16. IRQCR Register Field Descriptions
Field 7 IRQE Description IRQ select edge sensitive only— Special modes: Read or write anytime. Normal & emulation modes: Read anytime, write once. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. 0 IRQ configured for low level recognition. External IRQ enable— Read or write anytime. 1 External IRQ pin is connected to interrupt logic. 0 External IRQ pin is disconnected from interrupt logic. Reserved—
6 IRQEN
5-0
2.3.18
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Address 0x001F
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-16. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
NOTE Writing to this register when in special modes can alter the pin functionality.
2.3.19
Port K Data Register (PORTK)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0032 (PRR)
7
R PK7 W Altern. Function ROMCTL or EWAIT 0 ADDR22 mux NOACC 0 ADDR19 mux IQSTAT3 0 ADDR18 mux IQSTAT2 0 ADDR17 mux IQSTAT1 0 ADDR16 mux IQSTAT0 0 PK6 PK5 PK4 PK3 PK2 PK1 PK0
ADDR21
ADDR20
Reset
0
0
Figure 2-17. Port K Data Register (PORTK)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-17. PORTK Register Field Descriptions
Field 7-0 PK Description Port K general purpose input/output data—Data Register Port K pins 7 through 0 are associated with external bus control signals and internal memory expansion emulation pins. These include ADDR[22:16], No-Access (NOACC), External Wait (EWAIT) and instruction pipe signals IQSTAT[3:0]. Bits 6-0 carry the external addresses in all expanded modes. In emulation modes the address is multiplexed with the alternate functions NOACC and IQSTAT on the respective pins. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.20
Port K Data Direction Register (DDRK)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0033 (PRR)
7
R DDRK7 W Reset 0 0 0 0 0 0 0 0 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
Figure 2-18. Port K Data Direction Register (DDRK)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-18. DDRK Register Field Descriptions
Field 7-0 DDRK Description Port K Data Direction— This register controls the data direction of pins 7 through 0. The external bus function controls the data direction for the associated pins. In this case the data direction bits will not change. When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input or output. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.21
Port T Data Register (PTT)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0240
7
R PTT7 W Altern. Function IOC7 — Reset 0 IOC6 — 0 IOC5 VREG_API 0 IOC4 — 0 IOC3 — 0 IOC2 — 0 IOC1 — 0 IOC0 — 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
Figure 2-19. Port T Data Register (PTT)
1
Read: Anytime. Write: Anytime.
Table 2-19. PTT Register Field Descriptions
Field 7-6 PTT Description Port T general purpose input/output data—Data Register Port T pins 7 through 0 are associated with ECT channels IOC7 and IOC6. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port T general purpose input/output data—Data Register Port T pins 5 is associated with ECT channel IOC5 and the VREG_API output. The ECT function takes precedence over the VREG_API and the general purpose I/O function if the related channel is enabled. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port T general purpose input/output data—Data Register Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
5 PTT
4-0 PTT
2.3.22
Port T Input Register (PTIT)
Access: User read1
6 5 4 3 2 1 0
Address 0x0241
7
R W Reset
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-20. Port T Input Register (PTIT)
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1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-20. PTIT Register Field Descriptions
Field 7-0 PTIT Description Port T input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
2.3.23
Port T Data Direction Register (DDRT)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0242
7
R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Figure 2-21. Port T Data Direction Register (DDRT)
1
Read: Anytime. Write: Anytime.
Table 2-21. DDRT Register Field Descriptions
Field 7-0 DDRT Description Port T data direction— This register controls the data direction of pins 7 through 0. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this case the data direction bits will not change. The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer Input Capture always monitors the state of the pin. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.24
Port T Reduced Drive Register (RDRT)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0243
7
R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Figure 2-22. Port T Reduced Drive Register (RDRT)
1
Read: Anytime. Write: Anytime.
Table 2-22. RDRT Register Field Descriptions
Field 7-0 RDRT Description Port T reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.25
Port T Pull Device Enable Register (PERT)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0244
7
R PERT7 W Reset 0 0 0 0 0 0 0 0 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Figure 2-23. Port T Pull Device Enable Register (PERT)
1
Read: Anytime. Write: Anytime.
Table 2-23. PERT Register Field Descriptions
Field 7-0 PERT Description Port T pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
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2.3.26
Port T Polarity Select Register (PPST)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0245
7
R PPST7 W Reset 0 0 0 0 0 0 0 0 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Figure 2-24. Port T Polarity Select Register (PPST)
1
Read: Anytime. Write: Anytime.
Table 2-24. PPST Register Field Descriptions
Field 7-0 PPST Description Port T pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
2.3.27
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
Address 0x0246
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-25. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
2.3.28
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
Address 0x0247
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-26. PIM Reserved Register
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Chapter 2 Port Integration Module (S12XEPIMV1)
1
Read: Always reads 0x00 Write: Unimplemented
2.3.29
Port S Data Register (PTS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0248
7
R PTS7 W Altern. Function Reset SS0 0 SCK0 0 MOSI0 0 MISO0 0 TXD1 0 RXD1 0 TXD0 0 RXD0 0 PTST6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
Figure 2-27. Port S Data Register (PTS)
1
Read: Anytime. Write: Anytime.
Table 2-25. PTS Register Field Descriptions
Field 7 PTS Description Port S general purpose input/output data—Data Register Port S pin 7 is associated with the SS signal of the SPI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S pin 6 is associated with the SCK signal of the SPI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S pin 5 is associated with the MOSI signal of the SPI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S pin 4 is associated with the MISO signal of the SPI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S pin 3 is associated with the TXD signal of the SCI1 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
6 PTS
5 PTS
4 PTS
3 PTS
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Table 2-25. PTS Register Field Descriptions (continued)
Field 2 PTS Description Port S general purpose input/output data—Data Register Port S bits 2 is associated with the RXD signal of the SCI1 module . When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S pin 3 is associated with the TXD signal of the SCI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port S general purpose input/output data—Data Register Port S bits 2 is associated with the RXD signal of the SCI0 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
1 PTS
0 PTS
2.3.30
Port S Input Register (PTIS)
Access: User read1
6 5 4 3 2 1 0
Address 0x0249
7
R W Reset
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-28. Port S Input Register (PTIS)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-26. PTIS Register Field Descriptions
Field 7-0 PTIS Description Port S input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.31
Port S Data Direction Register (DDRS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0249
7
R DDRS7 W Reset 0 0 0 0 0 0 0 0 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
Figure 2-29. Port S Data Direction Register (DDRS)
1
Read: Anytime. Write: Anytime.
Table 2-27. DDRS Register Field Descriptions
Field 7-0 DDRS Description Port S data direction— This register controls the data direction of pins 7 through 0.This register configures each Port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTS or PTIS registers, when changing the DDRS register.
2.3.32
Port S Reduced Drive Register (RDRS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x024A
7
R RDRS7 W Reset 0 0 0 0 0 0 0 0 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
Figure 2-30. Port S Reduced Drive Register (RDRS)
1
Read: Anytime. Write: Anytime.
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Table 2-28. RDRS Register Field Descriptions
Field 7-0 RDRS Description Port S reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.33
Port S Pull Device Enable Register (PERS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x024B
7
R PERS7 W Reset 1 1 1 1 1 1 1 1 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
Figure 2-31. Port S Pull Device Enable Register (PERS)
1
Read: Anytime. Write: Anytime.
Table 2-29. PERS Register Field Descriptions
Field 7-0 PERS Description Port S pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.34
Port S Polarity Select Register (PPSS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x024C
7
R PPSS7 W Reset 0 0 0 0 0 0 0 0 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
Figure 2-32. Port S Polarity Select Register (PPSS)
1
Read: Anytime. Write: Anytime.
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Table 2-30. PPSS Register Field Descriptions
Field 7-0 PPSS Description Port S pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
2.3.35
Port S Wired-Or Mode Register (WOMS)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x024C
7
R WOMS7 W Reset 0 0 0 0 0 0 0 0 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
Figure 2-33. Port S Wired-Or Mode Register (WOMS)
1
Read: Anytime. Write: Anytime.
Table 2-31. WOMS Register Field Descriptions
Field 7-0 WOMS Description Port S wired-or mode—Enable wired-or functionality This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs.
2.3.36
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
Address 0x024F
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-34. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.37
Port M Data Register (PTM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0250
7
R PTM7 W Altern. Function TXCAN3 — (TXCAN4) — TXD3 Reset 0 RXCAN3 — (RXCAN4) — RXD3 0 TXCAN2 (TXCAN0) (TXCAN4) (SCK0) — 0 RXCAN2 (RXCAN0) (RXCAN4) (MOSI0) — 0 TXCAN1 (TXCAN0) — (SS0) — 0 RXCAN1 (RXCAN0) — (MISO0) — 0 TXCAN0 — — — — 0 RXCAN0 — — — — 0 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
Figure 2-35. Port M Data Register (PTM)
1
Read: Anytime. Write: Anytime.
Table 2-32. PTM Register Field Descriptions
Field 7-6 PTM Description Port M general purpose input/output data—Data Register Port M pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN3 and the routed CAN4, as well as with TXD and RXD signals of SCI3, respectively. The CAN3 function takes precedence over the CAN4, SCI3 and the general purpose I/O function if the CAN3 module is enabled. The CAN4 function takes precedence over the SCI3 and the general purpose I/O function if the CAN4 module is enabled. The SCI3 function takes precedence over the general purpose I/O function if the SCI3 module is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port M general purpose input/output data—Data Register Port M pin 5 is associated with the TXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with SCK signals of SPI0. The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
5 PTM
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Table 2-32. PTM Register Field Descriptions (continued)
Field 4 PTM Description Port M general purpose input/output data—Data Register Port M pin 4 is associated with the RXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with MOSI signals of SPI0. The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port M general purpose input/output data—Data Register Port M pin 5 is associated with the TXCAN signal of CAN1 and the routed CAN0, as well as with SS0 signals of SPI0. The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port M general purpose input/output data—Data Register Port M pin 4 is associated with the RXCAN signal of CAN1 and the routed CAN0, as well as with MISO signals of SPI0. The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port M general purpose input/output data—Data Register Port M pins 1 and 0 are associated with TXCAN and RXCAN signals of CAN0, respectively. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
3 PTM
2 PTM
1-0 PTM
2.3.38
Port M Input Register (PTIM)
Access: User read1
6 5 4 3 2 1 0
Address 0x0251
7
R W Reset
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-36. Port M Input Register (PTIM)
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1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-33. PTIM Register Field Descriptions
Field 7-0 PTIM Description Port M input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
2.3.39
Port M Data Direction Register (DDRM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0252
7
R DDRM7 W Reset 0 0 0 0 0 0 0 0 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
Figure 2-37. Port M Data Direction Register (DDRM)
1
Read: Anytime. Write: Anytime.
Table 2-34. DDRM Register Field Descriptions
Field 7 DDRM Description Port M data direction— This register controls the data direction of pin 7. The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 6. The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an input. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 5. The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
6 DDRM
5 DDRM
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Table 2-34. DDRM Register Field Descriptions (continued)
Field 4 DDRM Description Port M data direction— This register controls the data direction of pin 4. The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 3. The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 2. The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 1. The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port M data direction— This register controls the data direction of pin 0. The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
3 DDRM
2 DDRM
1 DDRM
0 DDRM
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register.
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2.3.40
Port M Reduced Drive Register (RDRM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0253
7
R RDRM7 W Reset 0 0 0 0 0 0 0 0 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
Figure 2-38. Port M Reduced Drive Register (RDRM)
1
Read: Anytime. Write: Anytime.
Table 2-35. RDRM Register Field Descriptions
Field 7-0 RDRM Description Port M reduced drive—Select reduced drive for outputs This register configures the drive strength of Port M output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.41
Port M Pull Device Enable Register (PERM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0254
7
R PERM7 W Reset 0 0 0 0 0 0 0 0 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
Figure 2-39. Port M Pull Device Enable Register (PERM)
1
Read: Anytime. Write: Anytime.
Table 2-36. PERM Register Field Descriptions
Field 7-0 PERM Description Port M pull device enable—Enable pull-up devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input or wired-or output. This bit has no effect if the pin is used as push-pull output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.42
Port M Polarity Select Register (PPSM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0255
7
R PPSM7 W Reset 0 0 0 0 0 0 0 0 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
Figure 2-40. Port M Polarity Select Register (PPSM)
1
Read: Anytime. Write: Anytime.
Table 2-37. PPSM Register Field Descriptions
Field 7-0 PPSM Description Port M pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN[3:0] inputs, but not a pull-down. 1 A pull-down device is connected to the associated Port M pin, if enabled by the associated bit in register PERM and if the port is used as a general purpose but not as RXCAN. 0 A pull-up device is connected to the associated Port M pin, if enabled by the associated bit in register PERM and if the port is used as general purpose or RXCAN input.
2.3.43
Port M Wired-Or Mode Register (WOMM)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0256
7
R WOMM7 W Reset 0 0 0 0 0 0 0 0 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
Figure 2-41. Port M Wired-Or Mode Register (WOMM)
1
Read: Anytime. Write: Anytime.
Table 2-38. WOMM Register Field Descriptions
Field 7-0 WOMM Description Port M wired-or mode—Enable wired-or functionality This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs.
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2.3.44
Module Routing Register (MODRR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0257
7
R W Reset
0 MODRR6 0 0 MODRR5 0 MODRR4 0 MODRR3 0 MODRR2 0 MODRR1 0 MODRR0 0
= Unimplemented or Reserved
Figure 2-42. Module Routing Register (MODRR)
1
Read: Anytime. Write: Anytime.
This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports.
Table 2-39. Module Routing Summary
Module 6 5 4 MODRR 3 2 1 0 RXCAN CAN0 x x x x CAN4 x x x x x x x x x x x x x x x x x x x x x x x x 0 0 1 1 x x x x 0 1 0 1 0 0 1 1 x x x x 0 1 0 1 x x x x MISO SPI0 SPI1 SPI2 x x x x 0 1 x x 0 1 x x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x PS4 PM2 PP0 PH0 PP4 PH4 PM0 PM2 PM4 PJ6 PJ6 PM4 PM6 Reserved MOSI PS5 PM4 PP1 PH1 PP5 PH5 SCK PS6 PM5 PP2 PH2 PP7 PH6 SS PS7 PM3 PP3 PH3 PP6 PH7 TXCAN PM1 PM3 PM5 PJ7 PJ7 PM5 PM7 Related Pins
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.45
Port P Data Register (PTP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0258
7
R PTP7 W Altern. Function Reset PWM7 SCK2 0 PWM6 SS2 0 PWM5 MOSI2 0 PWM4 MISO2 0 PWM3 SS1 0 PWM2 SCK1 0 PWM1 MOSI1 0 PWM0 MISO1 0 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
Figure 2-43. Port P Data Register (PTP)
1
Read: Anytime. Write: Anytime.
Table 2-40. PTP Register Field Descriptions
Field 7 PTP Description Port P general purpose input/output data—Data Register Port P pin 6 is associated with the PWM output channel 7 and the SCK signal of SPI2 . The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 7 is enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 6 is associated with the PWM output channel 6 and the SS signal of SPI2 . The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 6 is enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 5 is associated with the PWM output channel 5 and the MOSI signal of SPI2 . The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 5 is enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 4 is associated with the PWM output channel 4 and the MISO signal of SPI2 . The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 4 is enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
6 PTP
5 PTP
4 PTP
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Table 2-40. PTP Register Field Descriptions (continued)
Field 3 PTP Description Port P general purpose input/output data—Data Register Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1 . The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1 . The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1 . The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port P general purpose input/output data—Data Register Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1 . The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled. When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2 PTP
1 PTP
0 PTP
2.3.46
Port P Input Register (PTIP)
Access: User read1
6 5 4 3 2 1 0
Address 0x0259
7
R W Reset
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-44. Port P Input Register (PTIP)
1
Read: Anytime. Write:Never, writes to this register have no effect.
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Table 2-41. PTIP Register Field Descriptions
Field 7-0 PTIP Description Port P input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
2.3.47
Port P Data Direction Register (DDRP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025A
7
R DDRP7 W Reset 0 0 0 0 0 0 0 0 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
Figure 2-45. Port P Data Direction Register (DDRP)
1
Read: Anytime. Write: Anytime.
Table 2-42. DDRP Register Field Descriptions
Field 7 DDRP Description Port P data direction— This register controls the data direction of pin 7. The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin is forced to be an input. In these cases the data direction bit will not change. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port P data direction— The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this case the data direction bit will not change. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
6-0 DDRP
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTP or PTIP registers, when changing the DDRP register.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.48
Port P Reduced Drive Register (RDRP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025B
7
R RDRP7 W Reset 0 0 0 0 0 0 0 0 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
Figure 2-46. Port P Reduced Drive Register (RDRP)
1
Read: Anytime. Write: Anytime.
Table 2-43. RDRP Register Field Descriptions
Field 7-0 RDRP Description Port P reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.49
Port P Pull Device Enable Register (PERP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025C
7
R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
Figure 2-47. Port P Pull Device Enable Register (PERP)
1
Read: Anytime. Write: Anytime.
Table 2-44. PERP Register Field Descriptions
Field 7-0 PERP Description Port P pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
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2.3.50
Port P Polarity Select Register (PPSP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025D
7
R PPSP7 W Reset 0 0 0 0 0 0 0 0 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
Figure 2-48. Port P Polarity Select Register (PPSP)
1
Read: Anytime. Write: Anytime.
Table 2-45. PPSP Register Field Descriptions
Field 7-0 PPSP Description Port P pull device select—Determine pull device polarity on input pins This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 A rising edge on the associated Port P pin sets the associated flag bit in the PIFP register. A pull-down device is connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used as input.
2.3.51
Read: Anytime.
Port P Interrupt Enable Register (PIEP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025E
7
R PIEP7 W Reset 0 0 0 0 0 0 0 0 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
Figure 2-49. Port P Interrupt Enable Register (PIEP)
1
Read: Anytime. Write: Anytime.
Table 2-46. PPSP Register Field Descriptions
Field 7-0 PIEP Description Port P interrupt enable— This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt flag masked).
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2.3.52
Port P Interrupt Flag Register (PIFP)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025F
7
R PIFP7 W Reset 0 0 0 0 0 0 0 0 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
Figure 2-50. Port P Interrupt Flag Register (PIFP)
1
Read: Anytime. Write: Anytime.
Table 2-47. PPSP Register Field Descriptions
Field 7-0 PIFP Description Port P interrupt flag— Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write logic level 1 to the corresponding bit in the PIFP register. Writing a 0 has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 No active edge pending.
2.3.53
Port H Data Register (PTH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0260
7
R PTH7 W Altern. Function Reset SS2 TXD5 0 SCK2 RXD5 0 MOSI2 TXD4 0 MISO2 RXD4 0 SS1 TXD7 0 SCK1 RXD7 0 MOSI1 TXD6 0 MISO1 RXD6 0 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
Figure 2-51. Port H Data Register (PTH)
1
Read: Anytime. Write: Anytime.
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Table 2-48. PTH Register Field Descriptions
Field 7 PTH Description Port H general purpose input/output data—Data Register Port H pin 7 is associated with the TXD signal of the SCI5 module and the SS signal of the routed SPI2. The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2 module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 6 is associated with the RXD signal of the SCI5 module and the SCK signal of the routed SPI2. The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2 module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 5 is associated with the TXD signal of the SCI4 module and the MOSI signal of the routed SPI2. The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2 module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 4 is associated with the RXD signal of the SCI4 module and the MISO signal of the routed SPI2. The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2 module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 3 is associated with the TXD signal of the SCI7 module and the SS signal of the routed SPI1. The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1 module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 2 is associated with the RXD signal of the SCI7 module and the SCK signal of the routed SPI1. The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1 module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
6 PTH
5 PTH
4 PTH
3 PTH
2 PTH
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Table 2-48. PTH Register Field Descriptions (continued)
Field 1 PTH Description Port H general purpose input/output data—Data Register Port H pin 1 is associated with the TXD signal of the SCI6 module and the MOSI signal of the routed SPI1. The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1 module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port H general purpose input/output data—Data Register Port H pin 0 is associated with the RXD signal of the SCI6 module and the MISO signal of the routed SPI1. The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1 module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
0 PTH
2.3.54
Port H Input Register (PTIH)
Access: User read1
6 5 4 3 2 1 0
Address 0x0261
7
R W Reset
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-52. Port H Input Register (PTIH)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-49. PTIH Register Field Descriptions
Field 7-0 PTIH Description Port H input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.55
Port H Data Direction Register (DDRH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0262
7
R DDRH7 W Reset 0 0 0 0 0 0 0 0 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
Figure 2-53. Port H Data Direction Register (DDRH)
1
Read: Anytime. Write: Anytime.
Table 2-50. DDRH Register Field Descriptions
Field 7 DDRH Description Port H data direction— This register controls the data direction of pin 7. The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 6. The enabled SCI5 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 5. The enabled SCI4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 4. The enabled SCI4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 3. The enabled SCI7 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
6 DDRH
5 DDRH
4 DDRH
3 DDRH
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-50. DDRH Register Field Descriptions (continued)
Field 2 DDRH Description Port H data direction— This register controls the data direction of pin 2. The enabled SCI7 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 1. The enabled SCI6 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port H data direction— This register controls the data direction of pin 0. The enabled SCI6 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1 this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
1 DDRH
0 DDRH
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register.
2.3.56
Port H Reduced Drive Register (RDRH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0263
7
R RDRH7 W Reset 0 0 0 0 0 0 0 0 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
Figure 2-54. Port H Reduced Drive Register (RDRH)
1
Read: Anytime. Write: Anytime.
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Table 2-51. RDRH Register Field Descriptions
Field 7-0 RDRH Description Port H reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.57
Port H Pull Device Enable Register (PERH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0264
7
R PERH7 W Reset 0 0 0 0 0 0 0 0 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
Figure 2-55. Port H Pull Device Enable Register (PERH)
1
Read: Anytime. Write: Anytime.
Table 2-52. PERH Register Field Descriptions
Field 7-0 PERH Description Port H pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.58
Port H Polarity Select Register (PPSH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025D
7
R PPSH7 W Reset 0 0 0 0 0 0 0 0 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
Figure 2-56. Port H Polarity Select Register (PPSH)
1
Read: Anytime. Write: Anytime.
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Table 2-53. PPSH Register Field Descriptions
Field 7-0 PPSH Description Port H pull device select—Determine pull device polarity on input pins This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 A rising edge on the associated Port H pin sets the associated flag bit in the PIFH register. A pull-down device is connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 0 A falling edge on the associated Port H pin sets the associated flag bit in the PIFH register.A pull-up device is connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used as input.
2.3.59
Read: Anytime.
Port H Interrupt Enable Register (PIEH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025E
7
R PIEH7 W Reset 0 0 0 0 0 0 0 0 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
Figure 2-57. Port H Interrupt Enable Register (PIEH)
1
Read: Anytime. Write: Anytime.
Table 2-54. PPSP Register Field Descriptions
Field 7-0 PIEH Description Port H interrupt enable— This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt flag masked).
2.3.60
Port H Interrupt Flag Register (PIFH)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x025F
7
R PIFH7 W Reset 0 0 0 0 0 0 0 0 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
Figure 2-58. Port H Interrupt Flag Register (PIFH)
1
Read: Anytime. Write: Anytime.
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Table 2-55. PPSP Register Field Descriptions
Field 7-0 PIFH Description Port H interrupt flag— Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing a 0 has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 No active edge pending.
2.3.61
Port J Data Register (PTJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0268
7
R PTJ7 W Altern. Function TXCAN4 SCL0 (TXCAN0) Reset 0 RXCAN4 SDA0 (RXCAN0) 0 — SCL1 CS2 0 — SDA1 CS0 0 — — — 0 — — CS1 0 TXD2 — — 0 RXD2 — CS3 0 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0
Figure 2-59. Port J Data Register (PTJ)
1
Read: Anytime. Write: Anytime.
Table 2-56. PTJ Register Field Descriptions
Field 7-6 PTJ Description Port J general purpose input/output data—Data Register Port J pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN4 and the routed CAN0, as well as with SCL and SDA signals of IIC0, respectively. The CAN4 function takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the CAN4 module is enabled. The IIC0 function takes precedence over the routed CAN0 and the general purpose I/O function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as open drain outputs. The routed CAN0 function takes precedence over the general purpose I/O function if the routed CAN0 module is enabled. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port J general purpose input/output data—Data Register This pin is associated with the SCL and SDA signals of IIC1, and with chip select outputs CS2 and CS0, respectivley. The IIC1 function takes precedence over the chip select and general purpose I/O function if the IIC1 is enabled. The chip selects take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1 outputs are configured as open drain outputs. Refer to IIC section for details. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
5-4 PTJ
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Table 2-56. PTJ Register Field Descriptions (continued)
Field 3 PTJ Description Port J general purpose input/output data—Data Register This pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port J general purpose input/output data—Data Register This pin is associated with the chip select output signal CS2. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port J general purpose input/output data—Data Register This pin is associated with the TXD signal of SCI2. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port J general purpose input/output data—Data Register This pin is associated with the TXD signal of SCI2 and chip select output CS3. The SCI function takes precedence over the chip select and general purpose I/O function if the SCI2 is enabled. The chip select takes precedence over the general purpose I/O. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2 PTJ
1 PTJ
0 PTJ
2.3.62
Port J Input Register (PTIJ)
Access: User read1
6 5 4 3 2 1 0
Address 0x0269
7
R W Reset
PTIJ7
PTIJ6
PTIJ5
PTIJ4
PTIJ3
PTIJ2
PTIJ1
PTIJ0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-60. Port J Input Register (PTIJ)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-57. PTIJ Register Field Descriptions
Field 7-0 PTIJ Description Port J input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
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2.3.63
Port J Data Direction Register (DDRJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026A
7
R DDRJ7 W Reset 0 0 0 0 0 0 0 0 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0
Figure 2-61. Port J Data Direction Register (DDRJ)
1
Read: Anytime. Write: Anytime.
Table 2-58. DDRJ Register Field Descriptions
Field 7 DDRJ Description Port J data direction— This register controls the data direction of pin 7. The enabled CAN4 or routed CAN0 forces the I/O state to be an output. The enabled IIC0 module forces this pin to be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 6. The enabled CAN4 or routed CAN0 forces the I/O state to be an input. The enabled IIC0 module forces this pin to be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 5. The enabled CS2 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 4. The enabled CS0 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 3. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
6 DDRJ
5 DDRJ
4 DDRJ
3 DDRJ
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Table 2-58. DDRJ Register Field Descriptions (continued)
Field 2 DDRJ Description Port J data direction— This register controls the data direction of pin 2. The enabled CS1 signal forces the I/O state to be an output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 1. The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input. Port J data direction— This register controls the data direction of pin 0. The enabled SCI3 or CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
1 DDRJ
0 DDRJ
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register.
2.3.64
Port J Reduced Drive Register (RDRJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026B
7
R RDRJ7 W Reset 0 0 0 0 0 0 0 0 RDRJ6 RDRJ5 RDRJ4 RDRJ3 RDRJ2 RDRJ1 RDRJ0
Figure 2-62. Port J Reduced Drive Register (RDRJ)
1
Read: Anytime. Write: Anytime.
Table 2-59. RDRJ Register Field Descriptions
Field 7-0 RDRJ Description Port J reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
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2.3.65
Port J Pull Device Enable Register (PERJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026C
7
R PERJ7 W Reset 1 1 1 1 1 1 1 1 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0
Figure 2-63. Port J Pull Device Enable Register (PERJ)
1
Read: Anytime. Write: Anytime.
Table 2-60. PERJ Register Field Descriptions
Field 7-0 PERJ Description Port J pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull device are enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.66
Port J Polarity Select Register (PPSJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026D
7
R PPSJ7 W Reset 0 0 0 0 0 0 0 0 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0
Figure 2-64. Port J Polarity Select Register (PPSJ)
1
Read: Anytime. Write: Anytime.
Table 2-61. PPSJ Register Field Descriptions
Field 7-0 PPSJ Description Port J pull device select—Determine pull device polarity on input pins This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 1 A rising edge on the associated Port J pin sets the associated flag bit in the PIFJ register. A pull-down device is connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input. 0 A falling edge on the associated Port J pin sets the associated flag bit in the PIFJ register.A pull-up device is connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as input.
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2.3.67
Read: Anytime.
Port J Interrupt Enable Register (PIEJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026E
7
R PIEJ7 W Reset 0 0 0 0 0 0 0 0 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
1
Read: Anytime. Write: Anytime.
Table 2-62. PPSP Register Field Descriptions
Field 7-0 PIEJ Description Port J interrupt enable— This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J. 1 Interrupt is enabled. 0 Interrupt is disabled (interrupt flag masked).
2.3.68
Port J Interrupt Flag Register (PIFJ)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x026F
7
R PIFJ7 W Reset 0 0 0 0 0 0 0 0 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
1
Read: Anytime. Write: Anytime.
Table 2-63. PPSP Register Field Descriptions
Field 7-0 PIFJ Description Port J interrupt flag— Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing a 0 has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). 0 No active edge pending.
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2.3.69
Port AD0 Data Register 0 (PT0AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0270
7
R PT0AD07 W Altern. Function Reset AN15 0 AN14 0 AN13 0 AN12 0 AN11 0 AN10 0 AN9 0 AN8 0 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00
Figure 2-67. Port AD0 Data Register 0 (PT0AD0)
1
Read: Anytime. Write: Anytime.
Table 2-64. PT0AD0 Register Field Descriptions
Field 7-0 PT0AD0 Description Port AD0 general purpose input/output data—Data Register This register is associated with ATD0 analog inputs AN[15:8] on PAD[15:8], respectively. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.70
Port AD0 Data Register 1 (PT1AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0271
7
R PT1AD07 W Altern. Function Reset AN7 0 AN6 0 AN5 0 AN4 0 AN3 0 AN2 0 AN1 0 AN0 0 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00
Figure 2-68. Port AD0 Data Register 1 (PT1AD0)
1
Read: Anytime. Write: Anytime.
Table 2-65. PT1AD0 Register Field Descriptions
Field 7-0 PT1AD0 Description Port AD0 general purpose input/output data—Data Register This register is associated with ATD0 analog inputs AN[7:0] on PAD[7:0], respectively. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
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2.3.71
Port AD0 Data Direction Register 0 (DDR0AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0272
7
R DDR0AD07 W Reset 0 0 0 0 0 0 0 0 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
1
Read: Anytime. Write: Anytime.
Table 2-66. DDR0AD0 Register Field Descriptions
Field Description
7-0 Port AD0 data direction— DDR0AD0 This register controls the data direction of pins 15 through 8. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD0 registers, when changing the DDR0AD0 register. NOTE To use the digital input function on Port AD0 the ATD Digital Input Enable Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.72
Port AD0 Data Direction Register 1 (DDR1AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0273
7
R DDR1AD07 W Reset 0 0 0 0 0 0 0 0 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)
1
Read: Anytime. Write: Anytime.
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Table 2-67. DDR1AD0 Register Field Descriptions
Field Description
7-0 Port AD0 data direction— DDR1AD0 This register controls the data direction of pins 7 through 0. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD0 registers, when changing the DDR1AD0 register. NOTE To use the digital input function on Port AD0 the ATD Digital Input Enable Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.73
Port AD0 Reduced Drive Register 0 (RDR0AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0274
7
R RDR0AD07 W Reset 0 0 0 0 0 0 0 0 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
Figure 2-71. Port AD0 Reduced Drive Register 0 (RDR0AD0)
1
Read: Anytime. Write: Anytime.
Table 2-68. RDR0AD0 Register Field Descriptions
Field Description
7-0 Port AD0 reduced drive—Select reduced drive for Port AD0 outputs RDR0AD0 This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduce. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
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2.3.74
Port AD0 Reduced Drive Register 1 (RDR1AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0275
7
R RDR1AD07 W Reset 0 0 0 0 0 0 0 0 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00
Figure 2-72. Port AD0 Reduced Drive Register 1 (RDR1AD0)
1
Read: Anytime. Write: Anytime.
Table 2-69. RDR1AD0 Register Field Descriptions
Field Description
7-0 Port AD0 reduced drive—Select reduced drive for Port AD0 outputs RDR1AD0 This register configures the drive strength of Port AD0 output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.75
Port AD0 Pull Up Enable Register 0 (PER0AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0276
7
R PER0AD07 W Reset 0 0 0 0 0 0 0 0 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00
Figure 2-73. Port AD0 Pull Device Up Register 0 (PER0AD0)
1
Read: Anytime. Write: Anytime.
Table 2-70. PER0AD0 Register Field Descriptions
Field Description
7-0 Port AD0 pull device enable—Enable pull devices on input pins PER0AD0 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
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2.3.76
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0277
7
R PER1AD07 W Reset 0 0 0 0 0 0 0 0 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00
Figure 2-74. Port AD0 Pull Up Enable Register 1 (PER1AD0)
1
Read: Anytime. Write: Anytime.
Table 2-71. PER1AD0 Register Field Descriptions
Field Description
7-0 Port AD0 pull device enable—Enable pull devices on input pins PER1AD0 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.77
Port AD1 Data Register 0 (PT0AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0278
7
R PT0AD17 W Altern. Function Reset AN15 0 AN14 0 AN13 0 AN12 0 AN11 0 AN10 0 AN9 0 AN8 0 PT0AD16 PT0AD15 PT0AD14 PT0AD13 PT0AD12 PT0AD11 PT0AD10
Figure 2-75. Port AD1 Data Register 0 (PT0AD1)
1
Read: Anytime. Write: Anytime.
Table 2-72. PT0AD1 Register Field Descriptions
Field 7-0 PT0AD1 Description Port AD1 general purpose input/output data—Data Register This register is associated with ATD1 analog inputs AN[15:8] on PAD[31:24], respectively. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
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2.3.78
Port AD1 Data Register 1 (PT1AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0279
7
R PT1AD17 W Altern. Function Reset AN7 0 AN6 0 AN5 0 AN4 0 AN3 0 AN2 0 AN1 0 AN0 0 PT1AD16 PT1AD15 PT1AD14 PT1AD13 PT1AD12 PT1AD11 PT1AD10
Figure 2-76. Port AD1 Data Register 1 (PT1AD1)
1
Read: Anytime. Write: Anytime.
Table 2-73. PT1AD1 Register Field Descriptions
Field 7-0 PT1AD1 Description Port AD1 general purpose input/output data—Data Register This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.79
Port AD1 Data Direction Register 0 (DDR0AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027A
7
R DDR0AD17 W Reset 0 0 0 0 0 0 0 0 DDR0AD16 DDR0AD15 DDR0AD14 DDR0AD13 DDR0AD12 DDR0AD11 DDR0AD10
Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)
1
Read: Anytime. Write: Anytime.
Table 2-74. DDR0AD1 Register Field Descriptions
Field Description
7-0 Port AD1 data direction— DDR0AD1 This register controls the data direction of pins 15 through 8. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
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NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD1 registers, when changing the DDR0AD1 register. NOTE To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”.
2.3.80
Port AD1 Data Direction Register 1 (DDR1AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027B
7
R DDR1AD17 W Reset 0 0 0 0 0 0 0 0 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD12 DDR1AD11 DDR1AD10
Figure 2-78. Port AD1 Data Direction Register 1 (DDR1AD1)
1
Read: Anytime. Write: Anytime.
Table 2-75. DDR1AD1 Register Field Descriptions
Field Description
7-0 Port AD1 data direction— DDR1AD1 This register controls the data direction of pins 7 through 0. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PT0AD1 registers, when changing the DDR1AD1 register. NOTE To use the digital input function on Port AD1 the ATD Digital Input Enable Register (ATD1DIEN1) has to be set to logic level “1”.
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2.3.81
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027C
7
R RDR0AD17 W Reset 0 0 0 0 0 0 0 0 RDR0AD16 RDR0AD15 RDR0AD14 RDR0AD13 RDR0AD12 RDR0AD11 RDR0AD10
Figure 2-79. Port AD1 Reduced Drive Register 0 (RDR0AD1)
1
Read: Anytime. Write: Anytime.
Table 2-76. RDR0AD1 Register Field Descriptions
Field Description
7-0 Port AD1 reduced drive—Select reduced drive for Port AD1 outputs RDR0AD1 This register configures the drive strength of Port AD1 output pins 15 through 8 as either full or reduce. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.82
Port AD1 Reduced Drive Register 1 (RDR1AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027D
7
R RDR1AD17 W Reset 0 0 0 0 0 0 0 0 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD13 RDR1AD12 RDR1AD11 RDR1AD10
Figure 2-80. Port AD1 Reduced Drive Register 1 (RDR1AD1)
1
Read: Anytime. Write: Anytime.
Table 2-77. RDR1AD1 Register Field Descriptions
Field Description
7-0 Port AD1 reduced drive—Select reduced drive for Port AD1 outputs RDR1AD1 This register configures the drive strength of Port AD1 output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
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2.3.83
Port AD1 Pull Up Enable Register 0 (PER0AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027E
7
R PER0AD17 W Reset 0 0 0 0 0 0 0 0 PER0AD16 PER0AD15 PER0AD14 PER0AD13 PER0AD12 PER0AD11 PER0AD10
Figure 2-81. Port AD1 Pull Device Up Register 0 (PER0AD1)
1
Read: Anytime. Write: Anytime.
Table 2-78. PER0AD1 Register Field Descriptions
Field Description
7-0 Port AD1 pull device enable—Enable pull devices on input pins PER0AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.84
Port AD1 Pull Up Enable Register 1 (PER1AD1)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x027F
7
R PER1AD17 W Reset 0 0 0 0 0 0 0 0 PER1AD16 PER1AD15 PER1AD14 PER1AD13 PER1AD12 PER1AD11 PER1AD10
Figure 2-82. Port AD1 Pull Up Enable Register 1 (PER1AD1)
1
Read: Anytime. Write: Anytime.
Table 2-79. PER1AD1 Register Field Descriptions
Field Description
7-0 Port AD1 pull device enable—Enable pull devices on input pins PER1AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
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2.3.85
Port R Data Register (PTR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0368
7
R PTR7 W Altern. Function Reset TIMIOC7 0 TIMIOC6 0 TIMIOC5 0 TIMIOC4 0 TIMIOC3 0 TIMIOC2 0 TIMIOC1 0 TIMIOC0 0 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTR0
Figure 2-83. Port R Data Register (PTR)
1
Read: Anytime. Write: Anytime.
Table 2-80. PTR Register Field Descriptions
Field 7-0 PTR Description Port R general purpose input/output data—Data Register Port R pins 7 through 0 are associated with TIM channels TIMIOC7 through TIMIOC0. When not used with the alternative function, these pins can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
2.3.86
Port R Input Register (PTIR)
Access: User read1
6 5 4 3 2 1 0
Address 0x0369
7
R W Reset
PTIR7
PTIR6
PTIR5
PTIR4
PTIR3
PTIR2
PTIR1
PTIR0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-84. Port R Input Register (PTIR)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-81. PTIR Register Field Descriptions
Field 7-0 PTIR Description Port R input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
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2.3.87
Port R Data Direction Register (DDRR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x036A
7
R DDRR7 W Reset 0 0 0 0 0 0 0 0 DDRR6 DDRR5 DDRR4 DDRR3 DDRR2 DDRR1 DDRR0
Figure 2-85. Port R Data Direction Register (DDRR)
1
Read: Anytime. Write: Anytime.
Table 2-82. DDRR Register Field Descriptions
Field 7-0 DDRR Description Port R data direction— This register controls the data direction of pins 7 through 0. The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this case the data direction bits will not change. The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer Input Capture always monitors the state of the pin. 1 Associated pin is configured as output. 0 Associated pin is configured as high-impedance input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTR or PTIR registers, when changing the DDRR register.
2.3.88
Port R Reduced Drive Register (RDRR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x036B
7
R RDRR7 W Reset 0 0 0 0 0 0 0 0 RDRR6 RDRR5 RDRR4 RDRR3 RDRR2 RDRR1 RDRR0
Figure 2-86. Port R Reduced Drive Register (RDRR)
1
Read: Anytime. Write: Anytime.
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Table 2-83. RDRR Register Field Descriptions
Field 7-0 RDRR Description Port R reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.89
Port R Pull Device Enable Register (PERR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x036C
7
R PERR7 W Reset 0 0 0 0 0 0 0 0 PERR6 PERR5 PERR4 PERR3 PERR2 PERR1 PERR0
Figure 2-87. Port R Pull Device Enable Register (PERR)
1
Read: Anytime. Write: Anytime.
Table 2-84. PERR Register Field Descriptions
Field 7-0 PERR Description Port R pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset no pull device is enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.90
Port R Polarity Select Register (PPSR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x036D
7
R PPSR7 W Reset 0 0 0 0 0 0 0 0 PPSR6 PPSR5 PPSR4 PPSR3 PPSR2 PPSR1 PPSR0
Figure 2-88. Port R Polarity Select Register (PPSR)
1
Read: Anytime. Write: Anytime.
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Table 2-85. PPSR Register Field Descriptions
Field 7-0 PPSR Description Port R pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
2.3.91
PIM Reserved Register
Access: User read1
6 5 4 3 2 1 0
Address 0x036E
7
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-89. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
2.3.92
Port R Routing Register (PTRRR)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x036F
7
R PTRRR7 W Reset 0 0 0 0 0 0 0 0 PTRRR6 PTRRR5 PTRRR4 PTRRR3 PTRRR2 PTRRR1 PTRRR0
= Unimplemented or Reserved
Figure 2-90. Port R Routing Register (PTRRR)
1
Read: Anytime. Write: Anytime.
Table 2-86. PTR Routing Register Field Descriptions
Field 7 PTRRR Description Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC7 is available on PP7 0 TIMIOC7 is available on PR7 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC6 is available on PP6 0 TIMIOC6 is available on PR6
6 PTRRR
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Table 2-86. PTR Routing Register Field Descriptions (continued)
Field 5 PTRRR Description Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC5 is available on PP5 0 TIMIOC5 is available on PR5 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC4 is available on PP4 0 TIMIOC4 is available on PR4 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC3 is available on PP3 0 TIMIOC3 is available on PR3 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC2 is available on PP2 0 TIMIOC2 is available on PR2 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC1 is available on PP1 0 TIMIOC1 is available on PR1 Port R routing— This register configures the re-routing of the associated TIM channel. 1 TIMIOC0 is available on PP0 0 TIMIOC0 is available on PR0
4 PTRRR
3 PTRRR
2 PTRRR
1 PTRRR
0 PTRRR
2.3.93
Port L Data Register (PTL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0370
7
R PTL7 W Altern. Function Reset (TXD7) 0 (RXD7) 0 (TXD6) 0 (RXD6) 0 (TXD5) 0 (RXD5) 0 (TXD4) 0 (RXD4) 0 PTLT6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0
Figure 2-91. Port L Data Register (PTL)
1
Read: Anytime. Write: Anytime.
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Table 2-87. PTL Register Field Descriptions
Field 7 PTL Description Port L general purpose input/output data—Data Register Port L pin 7 is associated with the TXD signal of the SCI7 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 6 is associated with the RXD signal of the SCI7 module . When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 5 is associated with the TXD signal of the SCI6 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 4 is associated with the RXD signal of the SCI6 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 3 is associated with the TXD signal of the SC5 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 2 is associated with the RXD signal of the SCI5 module . When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 3 is associated with the TXD signal of the SCI4 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port L general purpose input/output data—Data Register Port L pin 2 is associated with the RXD signal of the SCI4 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
6 PTL
5 PTL
4 PTL
3 PTL
2 PTL
1 PTL
0 PTL
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2.3.94
Port L Input Register (PTIL)
Access: User read1
6 5 4 3 2 1 0
Address 0x0371
7
R W Reset
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-92. Port L Input Register (PTIL)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-88. PTIL Register Field Descriptions
Field 7-0 PTIL Description Port L input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
2.3.95
Port L Data Direction Register (DDRL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0372
7
R DDRL7 W Reset 0 0 0 0 0 0 0 0 DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0
Figure 2-93. Port L Data Direction Register (DDRL)
1
Read: Anytime. Write: Anytime.
Table 2-89. DDRL Register Field Descriptions
Field 7-0 DDRL Description Port L data direction— This register controls the data direction of pins 7 through 0.This register configures each Port L pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
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NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTL or PTIL registers, when changing the DDRL register.
2.3.96
Port L Reduced Drive Register (RDRL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0373
7
R RDRL7 W Reset 0 0 0 0 0 0 0 0 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0
Figure 2-94. Port L Reduced Drive Register (RDRL)
1
Read: Anytime. Write: Anytime.
Table 2-90. RDRL Register Field Descriptions
Field 7-0 RDRL Description Port L reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
2.3.97
Port L Pull Device Enable Register (PERL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0374
7
R PERL7 W Reset 1 1 1 1 1 1 1 1 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0
Figure 2-95. Port L Pull Device Enable Register (PERL)
1
Read: Anytime. Write: Anytime.
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Table 2-91. PERL Register Field Descriptions
Field 7-0 PERL Description Port L pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.98
Port L Polarity Select Register (PPSL)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0375
7
R PPSL7 W Reset 0 0 0 0 0 0 0 0 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0
Figure 2-96. Port L Polarity Select Register (PPSL)
1
Read: Anytime. Write: Anytime.
Table 2-92. PPSL Register Field Descriptions
Field 7-0 PPSL Description Port L pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
2.3.99
Port L Wired-Or Mode Register (WOML)
Access: User read/write1
6 5 4 3 2 1 0
Address 0x0376
7
R WOML7 W Reset 0 0 0 0 0 0 0 0 WOML6 WOML5 WOML4 WOML3 WOML2 WOML1 WOML0
Figure 2-97. Port L Wired-Or Mode Register (WOML)
1
Read: Anytime. Write: Anytime.
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Table 2-93. WOML Register Field Descriptions
Field 7-0 WOML Description Port L wired-or mode—Enable wired-or functionality This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs.
2.3.100 Port L Routing Register (PTLRR)
Address 0x0377
7 6 5 4 3 2
Access: User read/write1
1 0
R PTLRR7 W Reset 0 0 0 0 PTLRR6 PTLRR5 PTLRR4
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-98. Port L Routing Register (PTLRR)
1
Read: Anytime. Write: Anytime.
This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports.
Table 2-94. Port L Routing Summary
Module 7 PTLRR 6 5 4 TXD SCI7 SCI6 SCI5 SCI4 0 1 x x x x x x x x 0 1 x x x x x x x x 0 1 x x x x x x x x 0 1 PH3 PL7 PH1 PL5 PH7 PL3 PH5 PL1 RXD PH2 PL6 PH0 PL4 PH6 PL2 PH4 PL0 Related Pins
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2.3.101 Port F Data Register (PTF)
Address 0x0378
7 6 5 4 3 2
Access: User read/write1
1 0
R PTF7 W Altern. Function Reset (TXD3) 0 (RXD3) 0 (SCL0) 0 (SDA0) 0 (CS3) 0 (CS2) 0 (CS1) 0 (CS0) 0 PTFT6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
Figure 2-99. Port F Data Register (PTF)
1
Read: Anytime. Write: Anytime.
Table 2-95. PTF Register Field Descriptions
Field 7 PTF Description Port F general purpose input/output data—Data Register Port F pin 7 is associated with the TXD signal of the SCI3 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 6 is associated with the RXD signal of the SCI3 module . When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 5 is associated with the TXD signal of the SCI6 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 4 is associated with the RXD signal of the SCI6 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 3 is associated with the TXD signal of the SC5 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 2 is associated with the RXD signal of the SCI5 module . When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
6 PTF
5 PTF
4 PTF
3 PTF
2 PTF
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Table 2-95. PTF Register Field Descriptions (continued)
Field 1 PTF Description Port F general purpose input/output data—Data Register Port F pin 3 is associated with the TXD signal of the SCI4 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Port F general purpose input/output data—Data Register Port F pin 2 is associated with the RXD signal of the SCI4 module. When not used with the alternative function, this pin can be used as general purpose I/O. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read.
0 PTF
2.3.102 Port F Input Register (PTIF)
Address 0x0379
7 6 5 4 3 2 1
Access: User read1
0
R W Reset
PTIF7
PTIF6
PTIF5
PTIF4
PTIF3
PTIF2
PTIF1
PTIF0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-100. Port F Input Register (PTIF)
1
Read: Anytime. Write:Never, writes to this register have no effect.
Table 2-96. PTIF Register Field Descriptions
Field 7-0 PTIF Description Port F input data— This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.
2.3.103 Port F Data Direction Register (DDRF)
Address 0x037A
7 6 5 4 3 2
Access: User read/write1
1 0
R DDRF7 W Reset 0 0 0 0 0 0 0 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Figure 2-101. Port F Data Direction Register (DDRF)
1
Read: Anytime. Write: Anytime.
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Table 2-97. DDRF Register Field Descriptions
Field 7-0 DDRF Description Port F data direction— This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled. 1 Associated pin is configured as output. 0 Associated pin is configured as input.
NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTF or PTIF registers, when changing the DDRF register.
2.3.104 Port F Reduced Drive Register (RDRF)
Address 0x037B
7 6 5 4 3 2
Access: User read/write1
1 0
R RDRF7 W Reset 0 0 0 0 0 0 0 0 RDRF6 RDRF5 RDRF4 RDRF3 RDRF2 RDRF1 RDRF0
Figure 2-102. Port F Reduced Drive Register (RDRF)
1
Read: Anytime. Write: Anytime.
Table 2-98. RDRF Register Field Descriptions
Field 7-0 RDRF Description Port F reduced drive—Select reduced drive for outputs This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled.
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2.3.105 Port F Pull Device Enable Register (PERF)
Address 0x037C
7 6 5 4 3 2
Access: User read/write1
1 0
R PERF7 W Reset 1 1 1 1 1 1 1 1 PERF6 PERF5 PERF4 PERF3 PERF2 PERF1 PERF0
Figure 2-103. Port F Pull Device Enable Register (PERF)
1
Read: Anytime. Write: Anytime.
Table 2-99. PERF Register Field Descriptions
Field 7-0 PERF Description Port F pull device enable—Enable pull devices on input pins These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect if the pin is used as an output. Out of reset all pull devices are enabled. 1 Pull device enabled. 0 Pull device disabled.
2.3.106 Port F Polarity Select Register (PPSF)
Address 0x037D
7 6 5 4 3 2
Access: User read/write1
1 0
R PPSF7 W Reset 0 0 0 0 0 0 0 0 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0
Figure 2-104. Port F Polarity Select Register (PPSF)
1
Read: Anytime. Write: Anytime.
Table 2-100. PPSF Register Field Descriptions
Field 7-0 PPSF Description Port F pull device select—Determine pull device polarity on input pins This register selects whether a pull-down or a pull-up device is connected to the pin. 1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input. 0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
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2.3.107 PIM Reserved Register
Address 0x037E
7 6 5 4 3 2 1
Access: User read1
0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-105. PIM Reserved Register
1
Read: Always reads 0x00 Write: Unimplemented
2.3.108 Port F Routing Register (PTFRR)
Address 0x037F
7 6 5 4 3 2
Access: User read/write1
1 0
R W Reset
0
0 PTFRR5 PTFRR4 0 PTFRR3 0 PTFRR2 0 PTFRR1 0 PTFRR0 0
0
0
0
= Unimplemented or Reserved
Figure 2-106. Port F Routing Register (PTFRR)
1
Read: Anytime. Write: Anytime.
This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports.
Table 2-101. Port F Routing Summary
Module 5 4 PTFRR 3 2 1 0 TXD SCI3 0 1 x x x x x x x x x x PM7 PF7 SCL IIC0 x x 0 1 x x x x x x x x PJ7 PF5 RXD PM6 PF6 SDA PJ6 PF4 Related Pins
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Table 2-101. Port F Routing Summary
Module PTFRR Related Pins CS CS3 CS2 CS1 CS0 x x x x x x x x x x x x x x x x 0 1 x x x x x x x x 0 1 x x x x x x x x 0 1 x x x x x x x x 0 1 PJ0 PF3 PJ5 PF2 PJ2 PF1 PJ4 PF0
2.4
2.4.1
Functional Description
General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output from the external bus interface module or a peripheral module or an input to the external bus interface module or a peripheral module.
2.4.2
Registers
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and ATD ports (Table 2-102). All registers can be written at any time, however a specific configuration might not become active.
Example 2-1. Selecting a pull-up device
This device does not become active while the port is used as a push-pull output.
Table 2-102. Register availability per port1
Port A B C D E K T S M Data yes yes yes yes yes yes yes yes yes Input yes yes yes Data Reduced Direction Drive yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes Pull Enable yes Polarity Select yes yes yes WiredOr Mode yes yes Interrupt Enable Interrupt Flag Routing yes yes
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Table 2-102. Register availability per port1
Port P H J AD0 AD1 R L F
1
Data yes yes yes yes yes yes yes yes
Input yes yes yes yes yes yes
Data Reduced Direction Drive yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Pull Enable yes yes yes yes yes yes yes yes
Polarity Select yes yes yes yes yes yes
WiredOr Mode yes -
Interrupt Enable yes yes yes -
Interrupt Flag yes yes yes -
Routing yes yes
Each cell represents one register with individual configuration bits
2.4.2.1
Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O. Writing to this register has only an effect on the pin if the pin is used as general purpose output. When reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to “0”. If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This is independent of any other configuration (Figure 2-107).
2.4.2.2
Input register (PTIx)
This is a read-only register and always returns the buffered state of the pin (Figure 2-107).
2.4.2.3
Data direction register (DDRx)
This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-107).
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PTI
0 1
PT
0 1
PIN
DDR
data out
0 1
Module
output enable module enable
Figure 2-107. Illustration of I/O pin functionality
2.4.2.4
Reduced drive register (RDRx)
If the pin is used as an output this register allows the configuration of the drive strength.
2.4.2.5
Pull device enable register (PERx)
This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-or output.
2.4.2.6
Polarity select register (PPSx)
This register selects either a pull-up or pull-down device if enabled. It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-or output.
2.4.2.7
Wired-or mode register (WOMx)
If the pin is used as an output this register turns off the active high drive. This allows wired-or type connections of outputs.
2.4.2.8
Interrupt enable register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt.
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2.4.2.9
Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.10
Module routing register (MODRR, PTRRR, PTLRR, PTFRR)
This register supports the re-routing of the CAN0, CAN4, SPI2-0, SCI7-3, IIC0, TIM and CS[3:0] pins to alternative ports. This allows a software re-configuration of the pinouts of the different package options with respect to above peripherals.
2.4.3
Pins and Ports
NOTE Please refer to the SOC Guide to determine the pin availability in the different package options.
2.4.3.1
BKGD pin
The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the BKGD pin is used as MODC input.
2.4.3.2
Port A, B
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O with the external bus interface. In this case Port A and Port B are associated with the external address bus outputs ADDR15-ADDR8 and ADDR7-ADDR0, respectively. PB0 is the ADDR0 or UDS output.
2.4.3.3
Port C, D
Port C pins PC[7:0] and Port D pins PD[7:0] can be used for either general-purpose I/O with the external bus interface. In this case Port C and Port D are associated with the external data bus inputs/outputs DATA15-DATA8 and DATA7-DATA0, respectively. These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI section).
2.4.3.4
Port E
Port E is associated with the external bus control outputs RW, LSTRB, LDS and RE, the free-running clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and interrupt inputs IRQ and XIRQ. Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions. Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output running at the Core Clock rate. The clock output is always enabled in emulation modes. Port E pin PE[6] an be used for either general-purpose I/O, as TAGHI input or as MODB input during reset.
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Port E pin PE[5] an be used for either general-purpose I/O, as TAGLO input, RE output or as MODB input during reset. Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output running at the Bus Clock rate or at the programmed divided clock rate. The clock output is always enabled in emulation modes. Port E pin PE[3] an be used for either general-purpose I/O, as LSTRB or LDS output, or as EROMCTL input during reset. Port E pin PE[2] an be used for either general-purpose I/O, or as RW or RE output. Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.17/2-112) and clearing the I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up. Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to S12X_EBI section).
2.4.3.5
Port K
Port K pins PK[7:0] can be used for either general-purpose I/O, or with the external bus interface. In this case Port K pins PK[6:0] are associated with the external address bus outputs ADDR22-ADDR16 and PK7 is associated to the EWAIT input. Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
2.4.3.6
Port T
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the Enhanced Capture Timer.
2.4.3.7
Port S
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem. Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem. Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem. The SPI0 pins can be re-routed.
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2.4.3.8
Port M
This port is associated with the SCI3 CAN4-0 and SPI0. Port M pins PM[7:6] can be used for either general purpose I/O, or with the CAN3 subsystem. Port M pins PM[5:4] can be used for either general purpose I/O, or with the CAN2 subsystem. Port M pins PM[3:2] can be used for either general purpose I/O, or with the CAN1 subsystem. Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN0 subsystem. Port M pins PM[5:2] can be used for either general purpose I/O, or with the SPI0 subsystem. The CAN0, CAN4 and SPI0 pins can be re-routed.
2.4.3.9
Port P
This port is associated with the PWM, SPI1, SPI2 and TIM. Port P pins PP[7:0] can be used for either general purpose I/O, or with the PWM or with the channels of the standard Timer.subsystem. Port P pins PP[7:4] can be used for either general purpose I/O, or with the SPI2 subsystem. Port P pins PP[3:0] can be used for either general purpose I/O, or with the SPI1 subsystem.
2.4.3.10
Port H
This port is associated with the SPI1, SPI2, and SCI7-4. Port H pins PH[7:4] can be used for either general purpose I/O, or with the SPI2 subsystem. Port H pins PH[3:0] can be used for either general purpose I/O, or with the SPI1 subsystem. Port H pins PH[7:6] can be used for either general purpose I/O, or with the SCI5 subsystem. Port H pins PH[5:4] can be used for either general purpose I/O, or with the SCI4 subsystem. Port H pins PH[3:2] can be used for either general purpose I/O, or with the SCI7 subsystem. Port H pins PH[1:0] can be used for either general purpose I/O, or with the SCI6 subsystem.
2.4.3.11
Port J
This port is associated with the chip selects CS[3:0] as well as with CAN4, CAN0, IIC1, IIC0, and SCI2. Port J pins PJ[7:6] can be used for either general purpose I/O, or with the CAN4, IIC0 or CAN0 subsystems. Port J pins PJ[5:4] can be used for either general purpose I/O, or with the IIC1 subsystem or as chip select outputs. Port J pin PJ[3] can be used for general purpose I/O. Port J pin PJ[2] can be used for either general purpose I/O or as chip select output.
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Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem. Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select output.
2.4.3.12
Port AD0
This port is associated with the ATD0. Port AD0 pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.3.13
Port AD1
This port is associated with the ATD1. Port AD1 pins PAD[31:16] can be used for either general purpose I/O, or with the ATD1 subsystem.
2.4.3.14
Port R
This port is associated with the TIM module. Port R pins PR[7:0] can be used for either general-purpose I/O, or with the channels of the standard Timer. The TIM channels can be re-routed.
2.4.3.15
Port L
This port is associated with SCI7-4. Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI7 subsystem. Port L pins PL[5:4] can be used for either general purpose I/O, or with SCI6 subsystem. Port L pins PL[3:2] can be used for either general purpose I/O, or with SCI5 subsystem. Port L pins PL[1:0] can be used for either general purpose I/O, or with SCI4 subsystem.
2.4.3.16
Port F
This port is associated with SCI3, IIC0 and chip selects. Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem. Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem. Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects.
2.4.4
Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
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An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or WAIT mode. A digital filter on each pin prevents pulses (Figure 2-109) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-108 and Table 2-103).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
tpign tpval Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Table 2-103. Pulse Detection Criteria Mode Pulse STOP Unit
Ignored Uncertain Valid
1These
STOP1
tpulse ≤ 3 3 < tpulse < 4 tpulse ≥ 4
bus clocks bus clocks bus clocks
tpulse ≤ tpign tpign < tpulse < tpval tpulse ≥ tpval
values include the spread of the oscillator frequency over temperature, voltage and process.
tpulse
Figure 2-109. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly.
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The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin individually: Sample count
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0] DATA[15:0] (write) RW ... ... ... addr 0 ? 0 0 0 0 ... ... ... high
Access #1 3
... low 000 addr 0 0000 x data 0 0 0 ... 1 ... ... ... ... addr 1 high
1
low acc 0 iqstat-1 ? addr 0 high
2
low 000 iqstat 0 x high
n
low acc 1 0000 x x 1
... ... ... ... ... ... ...
ADDR[19:16] / IQSTAT[3:0] ...
5.4.2.4.3
Read-Write-Read Access Timing
Table 5-17. Interleaved Read-Write-Read Accesses (1 Cycle) Access #0 Access #1 2
low acc 0 addr 0 iqstat -1 ? addr 1 high low acc 1 iqstat 0 ivd 0 addr 2 high
Access #2 3
low acc 2 iqstat 1 x ... ... ... ... ...
Bus cycle ->
ECLK phase ADDR[22:20] / ACC[2:0] ADDR[15:0] / IVD[15:0]
... ... ... ... high
1
ADDR[19:16] / IQSTAT[3:0] ...
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Table 5-17. Interleaved Read-Write-Read Accesses (1 Cycle)
DATA[15:0] (internal read) DATA[15:0] (external read) RW ... ... ... ? ? 1 z z 1 z data 0 0 (write) data 1 (write) data 1 0 1 z z 1 ... ... ...
5.4.3
Accesses to Port Replacement Registers
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode. If writing to these addresses in emulation modes, the access is directed to both, the internal register and the external resource while reads will be treated external. The XEBI control registers also belong to this category.
5.4.4
Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI supports stretched external bus accesses (wait states) for each external address range related to one of the 4 chip select lines individually. This feature is available in normal expanded mode and emulation expanded mode for accesses to all external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2 cycles, respectively.
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Stretched accesses are controlled by: 1. EXSTR1[2:0] and EXSTR0[2:0] bits in the EBICTL1 register configuring a fixed amount of stretch cycles individually for each CSx line in MMCCTL0 2. Activation of the external wait feature for each CSx line MMCCTL0 register 3. Assertion of the external EWAIT signal when at least one CSx line is configured for EWAIT The EXSTRx[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An arbitrary amount of stretch cycles can be added using the EWAIT input. EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional cycles will cause the external bus access to be stretched accordingly. Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed and controlled by external wait after the data have been driven out on the external bus. This results in an extension of time the bus signals and the related control signals are valid externally. Read data are not captured by the system in normal expanded mode until the specified setup time before the RE rising edge. Read data are not captured in emulation expanded mode until the specified setup time before the falling edge of ECLK. In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched as programmed and controlled by external wait.
5.4.5
Data Select and Data Direction Signals
The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses. The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this module exclusively supports these kind of accesses in a single cycle. With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to odd addresses. In expanded modes the data access type is externally determined by a set of control signals, i.e., data select and data direction signals, as described below. The data select signals are not available if using the external bus interface with an 8-bit data bus.
5.4.5.1
Normal Expanded Mode
In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write), data size and alignment of an external bus access (Table 5-18).
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Table 5-18. Access in Normal Expanded Mode
DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Indicates No Access Unimplemented RE WE UDS LDS I/O data(addr) I/O data(addr) 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 Out data(even) Out In In In In In In In x data(even) x data(even) x x x Out In In In In In In In Out data(even) data(odd) data(odd) x data(odd) data(odd) x x x x DATA[7:0]
5.4.5.2
Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 5-19.
Table 5-19. Access in Emulation Modes and Special Test Mode
DATA[15:8] Access Word write of data on DATA[15:0] at an even and even+1 address Byte write of data on DATA[7:0] at an odd address Byte write of data on DATA[15:8] at an even address Word write at an odd and odd+1 internal RAM address (misaligned — only in emulation modes) Word read of data on DATA[15:0] at an even and even+1 address Byte read of data on DATA[7:0] at an odd address Byte read of data on DATA[15:8] at an even address Word read at an odd and odd+1 internal RAM address (misaligned - only in emulation modes) RW LSTRB ADDR0 I/O 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Out In Out data(addr) data(even) x data(odd) I/O Out Out In data(addr) data(odd) data(odd) x data(odd) data(even+1) data(odd) x data(odd) DATA[7:0]
Out data(odd+1) Out In In In In data(even) x data(even) data(odd+1) In In In In
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5.4.6
Low-Power Options
The XEBI does not support any user-controlled options for reducing power consumption.
5.4.6.1
Run Mode
The XEBI does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface. Operation in expanded modes results in a higher power consumption, however any unnecessary toggling of external bus signals is reduced to the lowest indispensable activity by holding the previous states between external accesses.
5.4.6.2
Wait Mode
The XEBI does not support any options for reducing power in wait mode.
5.4.6.3
Stop Mode
The XEBI will cease to function in stop mode.
5.5
Initialization/Application Information
This section describes the external bus interface usage and timing. Typical customer operating modes are normal expanded mode and emulation modes, specifically to be used in emulator applications. Taking the availability of the external wait feature into account the use cases are divided into four scenarios: • Normal expanded mode — External wait feature disabled – External wait feature enabled • Emulation modes – Emulation single-chip mode (without wait states) – Emulation expanded mode (with optional access stretching) Normal single-chip mode and special single-chip mode do not have an external bus. Special test mode is used for factory test only. Therefore, these modes are omitted here. All timing diagrams referred to throughout this section are available in the Electrical Characteristics appendix of the SoC section.
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5.5.1
Normal Expanded Mode
This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access.
5.5.1.1
Example 1a: External Wait Feature Disabled
The first example of bus timing of an external read and write access with the external wait feature disabled is shown in • Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’ The associated supply voltage dependent timing are numbers given in • • Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’ Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAIT disabled)’
Systems designed this way rely on the internal programmable access stretching. These systems have predictable external memory access times. The additional stretch time can be programmed up to 8 cycles to provide longer access times.
5.5.1.2
Example 1b: External Wait Feature Enabled
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles over the programmed number in EXSTR[2:0]. The feature must be enabled by configuring at least one CSx line for EWAIT. If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If EWAIT is asserted within the predefined time window during the access it will be strobed active and another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is finished. EWAIT can be held asserted as long as desired to stretch the access. An access with 1 cycle stretch by EWAIT assertion is shown in • Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’ • Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’ The associated timing numbers for both operations are given in • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAIT enabled)’ • Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAIT enabled)’ It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize the EWAIT input signal.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2
Emulation Modes
In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are directed to the external bus in emulation modes which are substituted by PRR as part of the PRU. Accesses to these registers take a constant time of 2 cycles. Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait state operation (stretching) of the external bus access is done in emulation modes when accessing internal memory or emulation memory addresses. In both modes observation of the internal operation is supported through the external bus (internal visibility).
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2.1
Example 2a: Emulation Single-Chip Mode
This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 5-5 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator
PRU PRR Ports
LSTRB RW
ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] ECLK ECLKX2
Figure 5-5. Application in Emulation Single-Chip Mode
The timing diagram for this operation is shown in: • Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’ The associated timing numbers are given in: • Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’ Timing considerations: • Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing. • LSTRB has the same timing as RW. • ECLKX2 rising edges have the same timing as ECLK edges. • The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2.2
Example 2b: Emulation Expanded Mode
This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals. Figure 5-6 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM Emulator
PRU PRR Ports
LSTRB RW
UDS LDS RE WE
ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] CS[3:0] EWAIT ECLK ECLKX2
Figure 5-6. Application in Emulation Expanded Mode
The timings of accesses with 1 stretch cycle are shown in • Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’ • Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’ The associated timing numbers are given in • Table ‘Example 2b: Emulation Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’ (this also includes examples for alternative settings of 2 and 3 additional stretch cycles) Timing considerations: • If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode.
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Chapter 6 Interrupt (S12XINTV2)
Table 6-1. Revision History
Version Number 02.00 Revision Date 01 JUL 2005 Effective Date 01 JUL 2005 Author Description of Changes initial V2 release, added new features: - XGATE threads can be interrupted - SYS instruction vector - access violation interrupt vectors - added Notes for devices without XGATE module - fixed priority definition for software exceptions in “1.4.6 Exception Priority”
02.04 02.05
11 JAN 2007 20 MAR 2007
11 JAN 2007 23 MAR 2007
6.1
Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the CPU or the XGATE module. The XINT module supports: • I bit and X bit maskable interrupt requests • One non-maskable unimplemented op-code trap • One non-maskable software interrupt (SWI) or background debug mode request • One non-maskable system call interrupt (SYS) • Three non-maskable access violation interrupt • One spurious interrupt vector request • Three system reset vector requests Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be handled by the XGATE module can be nested one level deep.
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NOTE The HPRIO register and functionality of the original S12 interrupt module is no longer supported, since it is superseded by the 7-level interrupt request priority scheme.
6.1.1
Glossary
The following terms and abbreviations are used in the document.
Table 6-2. Terminology Term CCR DMA INT IPL ISR MCU XGATE IRQ XIRQ Meaning
Condition Code Register (in the S12X CPU) Direct Memory Access Interrupt Interrupt Processing Level Interrupt Service Routine Micro-Controller Unit please refer to the "XGATE Block Guide" refers to the interrupt request associated with the IRQ pin refers to the interrupt request associated with the XIRQ pin
6.1.2
• • • • • • • • • • •
Features
Interrupt vector base register (IVBR) One spurious interrupt vector (at address vector base1 + 0x0010). One non-maskable system call interrupt vector request (at address vector base + 0x0012). Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−0x0018). 2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2). Each I bit maskable interrupt request has a configurable priority level and can be configured to be handled by either the CPU or the XGATE module2. I bit maskable interrupts can be nested, depending on their priority levels. One X bit maskable interrupt vector request (at address vector base + 0x00F4). One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base + 0x00F6). One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8). Three system reset vectors (at addresses 0xFFFA–0xFFFE).
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). 2. The IRQ interrupt can only be handled by the CPU MC9S12XE-Family Reference Manual , Rev. 1.07 262 Freescale Semiconductor
Chapter 6 Interrupt (S12XINTV2)
• • •
Determines the highest priority XGATE and interrupt vector requests, drives the vector to the XGATE module or to the bus on CPU request, respectively. Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever XIRQ is asserted, even if X interrupt is masked. XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
6.1.3
• •
Modes of Operation
Run mode This is the basic mode of operation. Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 6.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 6.5.3, “Wake Up from Stop or Wait Mode” for details. Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 6.3.2.1, “Interrupt Vector Base Register (IVBR)” for details.
•
•
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6.1.4
Block Diagram
Figure 6-1 shows a block diagram of the XINT module.
Peripheral Interrupt Requests Wake Up CPU
Non I Bit Maskable Channels Vector Address Priority Decoder
IRQ Channel
IVBR New IPL Current IPL
Interrupt Requests PRIOLVL2 PRIOLVL1 PRIOLVL0
RQST One Set Per Channel (Up to 108 Channels)
INT_XGPRIO XGATE Requests Priority Decoder Wake up XGATE Vector ID XGATE Interrupts RQST XGATE Request Route, PRIOLVLn Priority Level = bits from the channel configuration in the associated configuration register INT_XGPRIO = XGATE Interrupt Priority IVBR = Interrupt Vector Base IPL = Interrupt Processing Level
To XGATE Module
Figure 6-1. XINT Block Diagram
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To CPU
Chapter 6 Interrupt (S12XINTV2)
6.2
External Signal Description
The XINT module has no external signals.
6.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XINT module.
6.3.1
Module Memory Map
Table 6-3 gives an overview over all XINT module registers.
Table 6-3. XINT Memory Map
Address 0x0120 0x0121 0x0122–0x0125 0x0126 0x0127 0x0128 0x0129 0x012A 0x012B 0x012C 0x012D 0x012E 0x012F Use RESERVED Interrupt Vector Base Register (IVBR) RESERVED XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Interrupt Request Configuration Address Register (INT_CFADDR) Interrupt Request Configuration Data Register 0 (INT_CFDATA0) Interrupt Request Configuration Data Register 1 (INT_CFDATA1) Interrupt Request Configuration Data Register 2 (INT_CFDATA2 Interrupt Request Configuration Data Register 3 (INT_CFDATA3) Interrupt Request Configuration Data Register 4 (INT_CFDATA4) Interrupt Request Configuration Data Register 5 (INT_CFDATA5) Interrupt Request Configuration Data Register 6 (INT_CFDATA6) Interrupt Request Configuration Data Register 7 (INT_CFDATA7) Access — R/W — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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6.3.2
Register Descriptions
This section describes in address order all the XINT module registers and their individual bits.
Address 0x0121 Register Name IVBR R W 0x0126 INT_XGPRIO R W 0x0127 INT_CFADDR R W 0x0128 INT_CFDATA0 R W 0x0129 INT_CFDATA1 R W 0x012A INT_CFDATA2 R W 0x012B INT_CFDATA3 R W 0x012C INT_CFDATA4 R W 0x012D INT_CFDATA5 R W 0x012E INT_CFDATA6 R W 0x012F INT_CFDATA7 R W RQST INT_CFADDR[7:4] 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0
IVB_ADDR[7:0]7 0 0
XILVL[2:0] 0 0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
RQST
0
0
0
0
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 6-2. XINT Register Summary
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6.3.2.1
Interrupt Vector Base Register (IVBR)
Address: 0x0121
7 6 5 4 3 2 1 0
R W Reset 1 1 1
IVB_ADDR[7:0] 1 1 1 1 1
Figure 6-3. Interrupt Vector Base Register (IVBR)
Read: Anytime Write: Anytime
Table 6-4. IVBR Field Descriptions
Field Description
7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to HCS12. Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors (0xFFFA–0xFFFE). Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
6.3.2.2
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Address: 0x0126
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0
XILVL[2:0] 0 1
= Unimplemented or Reserved
Figure 6-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime Write: Anytime
Table 6-5. INT_XGPRIO Field Descriptions
Field 2–0 XILVL[2:0] Description XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”). Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read accesses to this register will return all 0.
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Table 6-6. XGATE Interrupt Priority Levels
Priority XILVL2 0 low 0 0 0 1 1 1 high 1 XILVL1 0 0 1 1 0 0 1 1 XILVL0 0 1 0 1 0 1 0 1 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7
6.3.2.3
Interrupt Request Configuration Address Register (INT_CFADDR)
Address: 0x0127
7 6 5 4 3 2 1 0
R W Reset 0
INT_CFADDR[7:4] 0 0 1
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
Figure 6-5. Interrupt Configuration Address Register (INT_CFADDR)
Read: Anytime Write: Anytime
Table 6-7. INT_CFADDR Field Descriptions
Field Description
7–4 Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128 INT_CFADDR[7:4] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7. Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to INT_CFDATA0–7 will be ignored and read accesses will return all 0.
6.3.2.4
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively.
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Address: 0x0128
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x0129
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012A
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012B
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
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Address: 0x012C
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012D
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012E
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012F
7 6 5 4 3 2 1 0
R W Reset
RQST 0
0 0
0 0
0 0
0 0 0
PRIOLVL[2:0] 0 11
= Unimplemented or Reserved
Figure 6-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime Write: Anytime
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Table 6-8. INT_CFDATA0–7 Field Descriptions
Field 7 RQST Description XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the location of the RQST bit in this register will be ignored and a read access will return 0. Note: If the XGATE module is not available on the device, writing a 1 to the location of the RQST bit in this register will be ignored and a read access will return 0.
2–0 Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”) to provide backwards compatibility with previous HCS12 interrupt controllers. Please also refer to Table 6-9 for available interrupt request priority levels. Note: Write accesses to configuration data registers of unused interrupt channels will be ignored and read accesses will return all 0. For information about what interrupt channels are used in a specific MCU, please refer to the Device Reference Manual of that MCU. Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The corresponding vectors do not have configuration data registers associated with them. Note: When vectors (vector base + 0x0010–0x001E) are selected by writing 0x10 to INT_CFADDR, writes to INT_CFDATA1–INT_CFDATA4 (0x0012–0x0018) will be ignored and read accesses will return all 0s. The corresponding vectors do not have configuration data registers associated with them. Note: Write accesses to the configuration register for the spurious interrupt vector request (vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the CPU, PRIOLVL = 7).
Table 6-9. Interrupt Priority Levels
Priority PRIOLVL2 0 low 0 0 0 1 1 1 high 1 PRIOLVL1 0 0 1 1 0 0 1 1 PRIOLVL0 0 1 0 1 0 1 0 1 Meaning Interrupt request is disabled Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7
6.4
Functional Description
The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.
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6.4.1
S12X Exception Requests
The CPU handles both reset requests and interrupt requests. The XINT module contains registers to configure the priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate the priority of a pending interrupt request.
6.4.2
Interrupt Prioritization
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2) are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base + 0x0010) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A priority level of 0 effectively disables the associated I bit maskable interrupt request. If more than one interrupt request is configured to the same interrupt priority level the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I bit maskable interrupt request to be processed. 1. The local interrupt enabled bit in the peripheral module must be set. 2. The setup in the configuration register associated with the interrupt request channel must meet the following conditions: a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request. b) The priority level must be set to non zero. c) The priority level must be greater than the current interrupt processing level in the condition code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]). 3. The I bit in the condition code register (CCR) of the CPU must be cleared. 4. There is no access violation interrupt request pending. 5. There is no SYS, SWI, BDM, TRAP, or XIRQ request pending. NOTE All non I bit maskable interrupt requests always have higher priority than I bit maskable interrupt requests. If an I bit maskable interrupt request is interrupted by a non I bit maskable interrupt request, the currently active interrupt processing level (IPL) remains unaffected. It is possible to nest non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
6.4.2.1
Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched. The previous IPL is automatically restored by executing the RTI instruction.
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Chapter 6 Interrupt (S12XINTV2)
6.4.3
XGATE Requests
If the XGATE module is implemented on the device, the XINT module is also used to process all exception requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed in the subsections below.
6.4.3.1
XGATE Request Prioritization
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the associated configuration register is set to 1 (please refer to Section 6.3.2.4, “Interrupt Request Configuration Data Registers (INT_CFDATA0–7)”). The priority level configuration (PRIOLVL) for this channel becomes the XGATE priority which will be used to determine the highest priority XGATE request to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST bits are set. The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority configuration register (please refer to Section 6.3.2.2, “XGATE Interrupt Priority Configuration Register (INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time, the channel with the highest vector address wins the prioritization.
6.4.4
Priority Decoders
The XINT module contains priority decoders to determine the priority for all interrupt requests pending for the respective target. There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of both priority decoders is basically the same with one exception: the priority decoder for the XGATE module does not take the current XGATE thread processing level into account. Instead, XGATE requests are handed to the XGATE module including a 1-bit priority identifier. The XGATE module uses this additional information to decide if the new request can interrupt a currently running thread. The 1-bit priority identifier corresponds to the most significant bit of the priority level configuration of the requesting channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE threads with priority levels 1, 2 and 3. A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher priority interrupt request could override the original exception which caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request. If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector.
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NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0010)).
6.4.5
Reset Exception Requests
The XINT module supports three system reset exception request types (for details please refer to the Clock and Reset Generator module (CRG)): 1. Pin reset, power-on reset, low-voltage reset, or illegal address reset 2. Clock monitor reset request 3. COP watchdog reset request
6.4.6
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon request by the CPU is shown in Table 6-10. Generally, all non-maskable interrupts have higher priorities than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur simultaneously (the S12XCPU executes one instruction at a time).
Table 6-10. Exception Vector Map and Priority
Vector Address1 0xFFFE 0xFFFC 0xFFFA (Vector base + 0x00F8) (Vector base + 0x00F6) (Vector base + 0x0012) (Vector base + 0x0018) (Vector base + 0x0016) (Vector base + 0x0014) (Vector base + 0x00F4) (Vector base + 0x00F2) (Vector base + 0x00F0–0x001A) (Vector base + 0x0010)
1 2
Source Pin reset, power-on reset, low-voltage reset, illegal address reset Clock monitor reset COP watchdog reset Unimplemented op-code trap Software interrupt instruction (SWI) or BDM vector request System call interrupt instruction (SYS) (reserved for future use) XGATE Access violation interrupt request2 CPU Access violation interrupt request3 XIRQ interrupt request IRQ interrupt request Device specific I bit maskable interrupt sources (priority determined by the associated configuration registers, in descending order) Spurious interrupt
16 bits vector address based only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor 3 only implemented if device features a Memory Protection Unit (MPU)
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Chapter 6 Interrupt (S12XINTV2)
6.5
6.5.1
Initialization/Application Information
Initialization
After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests. • If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and configure the XGATE module (please refer the XGATE Block Guide for details). • Enable I maskable interrupts by clearing the I bit in the CCR. • Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
6.5.2
Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I bit maskable interrupt requests handled by the CPU. • I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority, so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 6-14 for an example using up to three nested interrupt requests). I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can interrupt the current ISR. An ISR of an interruptible I bit maskable interrupt request could basically look like this: • Service interrupt, e.g., clear interrupt flags, copy data, etc. • Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with higher priority) • Process data • Return from interrupt by executing the instruction RTI
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Chapter 6 Interrupt (S12XINTV2)
0 Stacked IPL 0 4 0 0 0
IPL in CCR 7 6 5 4 Processing Levels 3 2 1 0
0
4
7
4
3
1
0
L7
RTI
RTI L3 (Pending) L4 L1 (Pending) Reset RTI RTI
Figure 6-14. Interrupt Processing Example
6.5.3
6.5.3.1
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode: • If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU. • An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the current IPL in CCR. • I bit maskable interrupt requests which are configured to be handled by the XGATE module are not capable of waking up the CPU. An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
6.5.3.2
XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE module are capable of waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect the state of the CPU.
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Chapter 7 Background Debug Module (S12XBDMV2) Revision History
Revision Number
s12x_bdm.01.00.00 s12x_bdm.02.00.02
Date
Bluefin1 Bluefin2
Author
Summary of Changes
First version of S12XBDMV1 First version of S12XBDMV2
7.1
Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions: • TAGGO command no longer supported by BDM • External instruction tagging feature now part of DBG module • BDM register map and register content extended/modified • Global page access functionality • Enabled but not active out of reset in emulation modes (if modes available) • CLKSW bit set out of reset in emulation modes (if modes available). • Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices is 0xC1)
7.1.1
Features
The BDM includes these distinctive features: • Single-wire communication with host development system
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Chapter 7 Background Debug Module (S12XBDMV2)
• • • • • • • • • • • • • • • •
Enhanced capability for allowing more flexibility in clock rates SYNC command to determine communication rate GO_UNTIL command Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single chip mode Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 14 firmware commands execute from the standard BDM firmware lookup table Software control of BDM operation during wait mode Software selectable clocks Global page access functionality Enabled but not active out of reset in emulation modes (if modes available) CLKSW bit set out of reset in emulation modes (if modes available). When secured, hardware commands are allowed to access the register space in special single chip mode, if the non-volatile memory erase test fail. Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices is 0xC1) BDM hardware commands are operational until system stop mode is entered (all bus masters are in stop mode)
7.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have a control bit that allows suspending thefunction during background debug mode.
7.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode. • Normal modes General operation of the BDM is available and operates the same in all normal modes. • Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. • Emulation modes (if modes available) In emulation mode, background operation is enabled but not active out of reset. This allows debugging and programming a system in this mode more easily.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2.2
Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or EEPROM) other than allowing erasure. For more information please see Section 7.4.1, “Security”.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2.3
Low-Power Modes
The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter a low power mode during BDM active mode. If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command.
7.1.3
Block Diagram
A block diagram of the BDM is shown in Figure 7-1.
Host System BKGD Serial Interface Data Control Register Block Address TRACE BDMACT Instruction Code and Execution Bus Interface and Control Logic Data Control Clocks 16-Bit Shift Register
ENBDM SDV Standard BDM Firmware LOOKUP TABLE Secured BDM Firmware LOOKUP TABLE
UNSEC CLKSW BDMSTS Register
Figure 7-1. BDM Block Diagram
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Chapter 7 Background Debug Module (S12XBDMV2)
7.2
External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.
7.3
7.3.1
Memory Map and Register Definition
Module Memory Map
Table 7-1 shows the BDM memory map when BDM is active.
Table 7-1. BDM Memory Map
Global Address 0x7FFF00–0x7FFF0B 0x7FFF0C–0x7FFF0E 0x7FFF0F 0x7FFF10–0x7FFFFF Module BDM registers BDM firmware ROM Family ID (part of BDM firmware ROM) BDM firmware ROM Size (Bytes) 12 3 1 240
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Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2
Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 7-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global Address 0x7FFF00
Register Name Reserved R W
Bit 7 X
6 X
5 X
4 X
3 X
2 X
1 0
Bit 0 0
0x7FFF01
BDMSTS
R W
ENBDM X
BDMACT
0
SDV
TRACE
CLKSW X
UNSEC
0
0x7FFF02
Reserved
R W
X
X
X
X
X
X
0x7FFF03
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF04
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF05
Reserved
R W
X
X
X
X
X
X
X
X
0x7FFF06
BDMCCRL R W
CCR7 0
CCR6 0
CCR5 0
CCR4 0
CCR3 0
CCR2
CCR1
CCR0
0x7FFF07
BDMCCRH R W
CCR10
CCR9
CCR8
0x7FFF08
BDMGPR
R W
BGAE 0
BGP6 0
BGP5 0
BGP4 0
BGP3 0
BGP2 0
BGP1 0
BGP0 0
0x7FFF09
Reserved
R W
0x7FFF0A
Reserved
R W
0
0
0
0
0
0
0
0
0x7FFF0B
Reserved
R W
0
0
0
0
0
0
0
0
= Unimplemented, Reserved X = Indeterminate 0
= Implemented (do not alter) = Always read zero
Figure 7-2. BDM Register Summary
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7.3.2.1
BDM Status Register (BDMSTS)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF01
R W Reset Special Single-Chip Mode Emulation Modes
(if modes available)
ENBDM
BDMACT
0
SDV
TRACE
CLKSW
UNSEC
0
01 1 0
1 0 0
0 0 0
0 0 0
0 0 0
0 1
2
03 0 0
0 0 0
All Other Modes
0
= Unimplemented, Reserved 0
1
= Implemented (do not alter)
= Always read zero
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed. 2 CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when secured if emulation modes available. 3 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description).
Figure 7-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single chip and emulation modes). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. — CLKSW can only be written via BDM hardware WRITE_BD commands. — All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution.
Table 7-2. BDMSTS Field Descriptions
Field 7 ENBDM Description Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware out of reset in special single chip mode. In emulation modes (if modes available) the ENBDM bit is set by BDM hardware out of reset. In special single chip mode with the device secured, this bit will not be set by the firmware until after the non-volatile memory erase verify tests are complete. In emulation modes (if modes available) with the device secured, the BDM operations are blocked.
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Chapter 7 Background Debug Module (S12XBDMV2)
Table 7-2. BDMSTS Field Descriptions (continued)
Field 6 BDMACT Description BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware or hardware read command or after data has been received as part of a firmware or hardware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 0 Data phase of command not complete 1 Data phase of command is complete TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands: GO or GO_UNTIL. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the command send to change the clock source should occur before the next command can be send. The delay should be obtained no matter which bit is modified to effectively change the clock source (either PLLSEL bit or CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent BDM communications. Table 7-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG module, the bit is part of the CLKSEL register) bits. Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency restriction on the alternate clock which was required on previous versions. Refer to the device specification to determine which clock connects to the alternate clock source input. Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new rate for the write command which changes it. Note: In emulation modes (if modes available), the CLKSW bit will be set out of RESET. Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map overlapping the standard BDM firmware lookup table. The secure BDM firmware lookup table verifies that the non-volatile memories (e.g. on-chip EEPROM and/or Flash EEPROM) are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode. 1 System is in a unsecured mode. Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect when the security byte in the Flash EEPROM is configured for unsecure mode.
4 SDV
3 TRACE
2 CLKSW
1 UNSEC
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Chapter 7 Background Debug Module (S12XBDMV2)
Table 7-3. BDM Clock Sources
PLLSEL 0 0 1 1 CLKSW 0 1 0 1 Bus clock dependent on oscillator Bus clock dependent on oscillator Alternate clock (refer to the device specification to determine the alternate clock source) Bus clock dependent on the PLL BDMCLK
7.3.2.2
BDM CCR LOW Holding Register (BDMCCRL)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF06
R W Reset Special Single-Chip Mode All Other Modes
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
1 0
1 0
0 0
0 0
1 0
0 0
0 0
0 0
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NOTE When BDM is made active, the CPU stores the content of its CCRL register in the BDMCCRL register. However, out of special single-chip reset, the BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the CCRL register in this CPU mode. Out of reset in all other modes the BDMCCRL register is read zero. When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte of the condition code register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2.3
BDM CCR HIGH Holding Register (BDMCCRH)
7 6 5 4 3 2 1 0
Register Global Address 0x7FFF07
R W Reset
0 0
0 0
0 0
0 0
0 0
CCR10 0
CCR9 0
CCR8 0
= Unimplemented or Reserved
Figure 7-5. BDM CCR HIGH Holding Register (BDMCCRH)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured When entering background debug mode, the BDM CCR HIGH holding register is used to save the high byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be written to modify the CCR value.
7.3.2.4
BDM Global Page Index Register (BDMGPR)
7 6 BGP6 0 5 BGP5 0 4 BGP4 0 3 BGP3 0 2 BGP2 0 1 BGP1 0 0 BGP0 0
Register Global Address 0x7FFF08
R W Reset
BGAE 0
Figure 7-6. BDM Global Page Register (BDMGPR)
Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured
Table 7-4. BDMGPR Field Descriptions
Field 7 BGAE Description BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and WRITE_BD_) can not be used for global accesses even if the BGAE bit is set. 0 BDM Global Access disabled 1 BDM Global Access enabled BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
6–0 BGP[6:0]
7.3.3
Family ID Assignment
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only value is a unique family ID which is 0xC1 for S12X devices.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 7.4.3, “BDM Hardware Commands”. Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 7.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see Section 7.4.3, “BDM Hardware Commands”) and in secure mode (see Section 7.4.1, “Security”). Firmware commands can only be executed when the system is not secure and is in active background debug mode (BDM).
7.4.1
Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the non-volatile memory. BDM operation is not possible in any other mode than special single chip mode when the device is secured. The device can be unsecured via BDM serial interface in special single chip mode only. For more information regarding security, please see the S12X_9SEC Block Guide.
7.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE.
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Chapter 7 Background Debug Module (S12XBDMV2)
After being enabled, BDM is activated by one of the following1: • Hardware BACKGROUND command • CPU BGND instruction • External instruction tagging mechanism2 • Breakpoint force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs.
7.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU on the SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM hardware commands are listed in Table 7-5. The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is provided by the S12X_DBG module.
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Chapter 7 Background Debug Module (S12XBDMV2)
Table 7-5. Hardware Commands
Command BACKGROUND ACK_ENABLE ACK_DISABLE READ_BD_BYTE READ_BD_WORD READ_BYTE READ_WORD WRITE_BD_BYTE WRITE_BD_WORD WRITE_BYTE WRITE_WORD Opcode (hex) 90 D5 D6 E4 EC E0 E8 C4 CC C0 C8 Data None None None Description Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. Enable Handshake. Issues an ACK pulse after the command is executed. Disable Handshake. This command does not issue an ACK pulse.
16-bit address Read from memory with standard BDM firmware lookup table in map. 16-bit data out Odd address data on low byte; even address data on high byte. 16-bit address Read from memory with standard BDM firmware lookup table in map. 16-bit data out Must be aligned access. 16-bit address Read from memory with standard BDM firmware lookup table out of map. 16-bit data out Odd address data on low byte; even address data on high byte. 16-bit address Read from memory with standard BDM firmware lookup table out of map. 16-bit data out Must be aligned access. 16-bit address Write to memory with standard BDM firmware lookup table in map. 16-bit data in Odd address data on low byte; even address data on high byte. 16-bit address Write to memory with standard BDM firmware lookup table in map. 16-bit data in Must be aligned access. 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Odd address data on low byte; even address data on high byte. 16-bit address Write to memory with standard BDM firmware lookup table out of map. 16-bit data in Must be aligned access.
NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
7.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands, see Section 7.4.2, “Enabling and Activating BDM”. Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 7-6.
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Table 7-6. Firmware Commands
Command1 READ_NEXT2 READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO GO_UNTIL3 TRACE1 TAGGO -> GO Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 0C 10 18 Data Description
16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. 16-bit data out Read program counter. 16-bit data out Read D accumulator. 16-bit data out Read X index register. 16-bit data out Read Y index register. 16-bit data out Read stack pointer. 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in none none none none Increment X index register by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed as a GO command.
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources are accessed rather than user code. Writing BDM firmware is not possible. 3 System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL” condition (BDM active again) is reached (see Section 7.4.7, “Serial Interface Hardware Handshake Protocol” last Note).
1
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7.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. 16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For devices with external bus: The following cycle count information is only valid when the external wait function is not used (see wait bit of EBI sub-block). During an external wait the BDM can not steal a cycle. Hence be careful with the external wait function if the BDM serial interface is much faster than the bus, because of the BDM soft-reset after time-out (see Section 7.4.11, “Serial Communication Time Out”). For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. This includes the potential of extra cycles when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port replacement unit) in emulation modes (if modes available). The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus. On previous BDM modules this extra time could be hidden within the serial time. For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed.
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The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing or the external wait function is used, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 7-7 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1
8 Bits AT ~16 TC/Bit Hardware Read Command 16 Bits AT ~16 TC/Bit Address 150-BC Delay 16 Bits AT ~16 TC/Bit Data 150-BC Delay Hardware Write Command 48-BC DELAY Firmware Read Command Data 36-BC DELAY Firmware Write Command 76-BC Delay GO, TRACE Command Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Data Next Command Next Command Address Data Next Command Next Command
Figure 7-7. BDM Command Structure
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 7.4.6, “BDM Serial Interface” and Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
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7.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 7.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 7-8 and that of target-to-host in Figure 7-9 and Figure 7-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 7-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
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BDM Clock (Target MCU)
Host Transmit 1
Host Transmit 0 Perceived Start of Bit Time 10 Cycles Synchronization Uncertainty Target Senses Bit Earliest Start of Next Bit
Figure 7-8. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 7-9 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse Perceived Start of Bit Time R-C Rise BKGD Pin
High-Impedance
High-Impedance
High-Impedance
10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit
Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
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Figure 7-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
BDM Clock (Target MCU) Host Drive to BKGD Pin Target System Drive and Speedup Pulse Perceived Start of Bit Time BKGD Pin 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit
High-Impedance Speedup Pulse
Figure 7-10. BDM Target-to-Host Serial Bit Timing (Logic 0)
7.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 7-11). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon the CPU bus frequency, which in some cases could be very slow
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compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM Clock (Target MCU)
16 Cycles Target Transmits ACK Pulse High-Impedance 32 Cycles Speedup Pulse Minimum Delay From the BDM Command BKGD Pin Earliest Start of Next Bit High-Impedance
16th Tick of the Last Command Bit
Figure 7-11. Target Acknowledge Pulse (ACK)
NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending. Figure 7-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
Target BKGD Pin READ_BYTE Host Byte Address Target Host New BDM Command Host BDM Issues the ACK Pulse (out of scale) BDM Executes the READ_BYTE Command Target
(2) Bytes are Retrieved
BDM Decodes the Command
Figure 7-12. Handshake Protocol at Command Level
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Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 7-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other “highs” are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command (e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol provides a mechanism in which a command, and its corresponding ACK, can be aborted. NOTE The ACK pulse does not provide a time out. This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 7.4.8, “Hardware Handshake Abort Procedure”.
7.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 7.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware READ or WRITE command that is issued and if the serial interface is running on a different clock rate than the bus. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or
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GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 7.4.9, “SYNC — Request Timed Reference Pulse”. Figure 7-13 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer.
READ_BYTE CMD is Aborted by the SYNC Request (Out of Scale) BKGD Pin READ_BYTE Host Memory Address Target SYNC Response From the Target (Out of Scale) READ_STATUS Host Target New BDM Command Host Target
BDM Decode and Starts to Execute the READ_BYTE Command
New BDM Command
Figure 7-13. ACK Abort Procedure at the Command Level
NOTE Figure 7-13 does not represent the signals in a true timing scale Figure 7-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
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Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conflict from happening.
At Least 128 Cycles BDM Clock (Target MCU) ACK Pulse Target MCU Drives to BKGD Pin Host Drives SYNC To BKGD Pin Host and Target Drive to BKGD Pin Host SYNC Request Pulse BKGD Pin 16 Cycles High-Impedance Electrical Conflict Speedup Pulse
Figure 7-14. ACK Pulse and SYNC Request Conflict
NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could eventually occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows: • ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. • ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 7.4.3, “BDM Hardware Commands” and Section 7.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands.
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The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.
7.4.9
SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by CLKSW.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed
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within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.
7.4.10
Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time. If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing the BGND instruction will result in a return address pointing to BDM firmware address space. When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction and still being in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
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stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command.
7.4.11
Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
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Chapter 8 S12X Debug (S12XDBGV3) Module Revision History
Revision Number
03.17 03.18 03.19
Date
20.MAR.2007 20.APR.2007 24.APR.2007
Author
Summary of Changes
Tabulated glossary Renamed S12XCPU to CPU12X Added “Data Bus Comparison NDB Dependency” section Clarified effect TRIG has on state sequencer Clarified simultaneous arm and disarm effect
8.1
Introduction
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit architecture and allows debugging of CPU12Xand XGATE module operations. Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user configures the S12XDBG module for a debugging session over the BDM interface. Once configured the S12XDBG module is armed and the device leaves BDM Mode returning control to the user program, which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured over a serial interface using SWI routines.
8.1.1
Term
Glossary
Table 8-1. Glossary Of Terms
Definition
COF BDM DUG WORD
Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt Background Debug Mode Device User Guide, describing the features of the device into which the DBG is integrated 16 bit data entity
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Table 8-1. Glossary Of Terms
Term Definition
Data Line CPU Tag
64 bit data entity CPU12X module Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs.
8.1.2
Overview
The comparators monitor the bus activity of the CPU12X and XGATE. When a match occurs the control logic can trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered by the external TAGHI and TAGLO signals, or by an XGATE module S/W breakpoint request or by writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
8.1.3
•
Features
Four comparators (A, B, C, and D) — Comparators A and C compare the full address bus and full 16-bit data bus — Comparators A and C feature a data bus mask register — Comparators B and D compare the full address bus only — Each comparator can be configured to monitor CPU12X or XGATE buses — Each comparator features selection of read or write access cycles — Comparators B and D allow selection of byte or word access cycles — Comparisons can be used as triggers for the state sequencer Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin ≤ Address ≤ Addmax — Outside address range match mode, Address < Addmin or Address > Addmax Two types of triggers — Tagged — This triggers just before a specific instruction begins execution — Force — This triggers on the first instruction boundary after a match occurs. The following types of breakpoints — CPU12X breakpoint entering BDM on breakpoint (BDM) — CPU12X breakpoint executing SWI on breakpoint (SWI) — XGATE breakpoint
•
•
•
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• • • •
•
External CPU12X instruction tagging trigger independent of comparators XGATE S/W breakpoint request trigger independent of comparators TRIG Immediate software trigger independent of comparators Four trace modes — Normal: change of flow (COF) PC information is stored (see Section 8.4.5.2.1) for change of flow definition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Pure PC: All program counter addresses are stored. 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin, End, and Mid alignment of tracing to trigger
8.1.4
Modes of Operation
The S12XDBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled. Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed. The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be generated if the MCU is secure.
Table 8-2. Mode Dependent Restriction Summary
BDM Enable x 0 0 1 1 BDM Active x 0 1 0 1 MCU Secure 1 0 0 0 0 Yes XGATE only Comparator Matches Enabled Yes Yes Breakpoints Possible Yes Only SWI Yes XGATE only Tagging Possible Yes Yes Yes XGATE only Tracing Possible No Yes Yes XGATE only
Active BDM not possible when not enabled
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8.1.5
Block Diagram
TAGS BREAKPOINT REQUESTS CPU12X & XGATE
TAGHITS EXTERNAL TAGHI / TAGLO XGATE S/W BREAKPOINT REQUEST SECURE COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D MATCH0 COMPARATOR MATCH CONTROL MATCH1 MATCH2 MATCH3 TAG & TRIGGER CONTROL LOGIC
TRIGGER STATE STATE SEQUENCER STATE
CPU12X BUS
XGATE BUS
BUS INTERFACE
TRACE CONTROL TRIGGER
TRACE BUFFER READ TRACE DATA (DBG READ DATA BUS)
Figure 8-1. Debug Module Block Diagram
8.2
External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation modes only.
Table 8-3. External System Pins Associated With S12XDBG
Pin Name TAGHI (See DUG) TAGLO (See DUG) TAGLO (See DUG) Pin Functions TAGHI TAGLO Unconditional Tagging Enable Description When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the end of reset enables the Unconditional Tagging function.
8.3
8.3.1
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 8-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
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Address 0x0020
Name DBGC1 R W R W R W R W R W R W R W R W R W
Bit 7 ARM TBF
6 0 TRIG EXTF
5 XGSBPE 0
4 BDM 0
3 DBGBRK 0
2
1
Bit 0 COMRV
0x0021
DBGSR
SSF2
SSF1
SSF0
0x0022
DBGTCR
TSOURCE 0 0 0
TRANGE 0
TRCMOD
TALIGN
0x0023
DBGC2
CDCM Bit 11 Bit 10 Bit 9
ABCM Bit 8
0x0024
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 12
0x0025
DBGTBL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0026
DBGCNT
0
CNT
0x0027 0x0027 0x00281 0x00282
DBGSCRX DBGMFR
0 0
0 0
0 0
0 0
SC3 MC3
SC2 MC2
SC1 MC1
SC0 MC0
DBGXCTL R (COMPA/C) W DBGXCTL R (COMPB/D) W DBGXAH R W R W R W R W R W R W
0
NDB SZ
TAG TAG
BRK BRK
RW RW
RWE RWE
SRC SRC
COMPE COMPE
SZE 0
0x0029
Bit 22
21
20
19
18
17
Bit 16
0x002A
DBGXAM
Bit 15
14
13
12
11
10
9
Bit 8
0x002B
DBGXAL
Bit 7
6
5
4
3
2
1
Bit 0
0x002C
DBGXDH
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
DBGXDL
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
DBGXDHM
Bit 15
14
13
12
11
10
9
Bit 8
R Bit 7 6 5 4 3 2 W 1 This represents the contents if the Comparator A or C control register is blended into this address. 2 This represents the contents if the Comparator B or D control register is blended into this address 0x002F DBGXDLM
1
Bit 0
Figure 8-2. Quick Reference to S12XDBG Registers
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8.3.2
Register Descriptions
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
8.3.2.1
Debug Control Register 1 (DBGC1)
Address: 0x0020
7 6 5 4 3 2 1 0
R W Reset
ARM 0
0 TRIG 0
XGSBPE 0
BDM 0 0
DBGBRK 0 0
COMRV 0
Figure 8-3. Debug Control Register (DBGC1)
Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 5:2 anytime S12XDBG is not armed. NOTE If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the ARM bit is cleared due to the hardware disarm. NOTE When disarming the S12XDBG by clearing ARM with software, the contents of bits[5:2] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required.
Table 8-4. DBGC1 Field Descriptions
Field 7 ARM Description Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. 0 Debugger disarmed 1 Debugger armed Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If TSOURCE are clear no tracing is carried out. If tracing has already commenced using BEGIN- or MID trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit settings, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect. 0 Do not trigger until the state sequencer enters the Final State. 1 Trigger immediately .
6 TRIG
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Table 8-4. DBGC1 Field Descriptions (continued)
Field 5 XGSBPE Description XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can request an CPU12X breakpoint depending on the state of this bit. 0 XGATE S/W breakpoint request is disabled 1 XGATE S/W breakpoint request is enabled Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please refer to Section 8.4.7 for further details. XGATE software breakpoints are independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent of the DBGBRK bit field configuration. See Table 8-5. Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 8-6.
4 BDM
3–2 DBGBRK
1–0 COMRV
Table 8-5. DBGBRK Encoding
DBGBRK 00 01 10 11 Resource Halted by Breakpoint No breakpoint generated XGATE breakpoint generated CPU12X breakpoint generated Breakpoints generated for CPU12X and XGATE
Table 8-6. COMRV Encoding
COMRV 00 01 10 11 Visible Comparator Comparator A Comparator B Comparator C Comparator D Visible Register at 0x0027 DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR
8.3.2.2
Debug Status Register (DBGSR)
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Address: 0x0021
7 6 5 4 3 2 1 0
R W Reset POR
TBF — 0
EXTF 0 0
0 0 0
0 0 0
0 0 0
SSF2 0 0
SSF1 0 0
SSF0 0 0
= Unimplemented or Reserved
Figure 8-4. Debug Status Register (DBGSR)
Read: Anytime Write: Never
Table 8-7. DBGSR Field Descriptions
Field 7 TBF Description Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0]. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was met since arming. This bit is cleared when ARM in DBGC1 is written to a one. 0 External tag hit has not occurred 1 External tag hit has occurred State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 8-8.
6 EXTF
2–0 SSF[2:0]
Table 8-8. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0] 000 001 010 011 100 101,110,111 Current State State0 (disarmed) State1 State2 State3 Final State Reserved
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8.3.2.3
Debug Trace Control Register (DBGTCR)
Address: 0x0022
7 6 5 4 3 2 1 0
R W Reset 0
TSOURCE 0 0
TRANGE 0 0
TRCMOD 0 0
TALIGN 0
Figure 8-5. Debug Trace Control Register (DBGTCR)
Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed.
Table 8-9. DBGTCR Field Descriptions
Field 7–6 TSOURCE 5–4 TRANGE Description Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU system is secured, these bits cannot be set and tracing is inhibited. See Table 8-10. Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when tracing from the CPU12X in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To use a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state sequence triggers. If the corresponding SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect on the valid address range, memory accesses within the whole memory map are traced. See Table 8-11. Trace Mode Bits — See Section 8.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See Table 8-12. Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a tracing session. See Table 8-13.
3–2 TRCMOD
1–0 TALIGN
Table 8-10. TSOURCE — Trace Source Bit Encoding
TSOURCE 00 01 10
1 2 1
Tracing Source No tracing requested CPU12X XGATE Both CPU12X and XGATE
111,2
No range limitations are allowed. Thus tracing operates as if TRANGE = 00. No Detail Mode tracing supported. If TRCMOD = 10, no information is stored.
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Table 8-11. TRANGE Trace Range Encoding
TRANGE 00 01 10 11 Tracing Range Trace from all addresses (No filter) Trace only in address range from $00000 to Comparator D Trace only in address range from Comparator C to $7FFFFF Trace only in range from Comparator C to Comparator D
Table 8-12. TRCMOD Trace Mode Bit Encoding
TRCMOD 00 01 10 11 Description Normal Loop1 Detail Pure PC
Table 8-13. TALIGN Trace Alignment Encoding
TALIGN 00 01 10 11 Description Trigger at end of stored data Trigger before storing data Trace buffer entries before and after trigger Reserved
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8.3.2.4
Debug Control Register2 (DBGC2)
Address: 0x0023
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0 0
CDCM 0 0
ABCM 0
= Unimplemented or Reserved
Figure 8-6. Debug Control Register2 (DBGC2)
Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching.
Table 8-14. DBGC2 Field Descriptions
Field 3–2 CDCM[1:0] 1–0 ABCM[1:0] Description C and D Comparator Match Control — These bits determine the C and D comparator match mapping as described in Table 8-15. A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 8-16.
Table 8-15. CDCM Encoding
CDCM 00 01 10 11
1
Description Match2 mapped to comparator C match....... Match3 mapped to comparator D match. Match2 mapped to comparator C/D inside range....... Match3 disabled. Match2 mapped to comparator C/D outside range....... Match3 disabled. Reserved1
Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D
Table 8-16. ABCM Encoding
ABCM 00 01 10 11
1
Description Match0 mapped to comparator A match....... Match1 mapped to comparator B match. Match 0 mapped to comparator A/B inside range....... Match1 disabled. Match 0 mapped to comparator A/B outside range....... Match1 disabled. Reserved1
Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B
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8.3.2.5
Debug Trace Buffer Register (DBGTBH:DBGTBL)
Address: 0x0024, 0x0025
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W POR Other Resets
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 X — X — X — X — X — X — X —
Bit 8 X —
Bit 7 X —
Bit 6 X —
Bit 5 X —
Bit 4 X —
Bit 3 X —
Bit 2 X —
Bit 1 X —
Bit 0 X —
Figure 8-7. Debug Trace Buffer Register (DBGTB)
Read: Only when unlocked AND not secured AND not armed AND with a TSOURCE bit set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents.
Table 8-17. DBGTB Field Descriptions
Field 15–0 Bit[15:0] Description Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. The POR state is undefined Other resets do not affect the trace buffer contents. .
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8.3.2.6
Debug Count Register (DBGCNT)
Address: 0x0026
7 6 5 4 3 2 1 0
R W Reset POR
0 0 0 — 0 — 0 — 0
CNT — 0 — 0 — 0 — 0
= Unimplemented or Reserved
Figure 8-8. Debug Count Register (DBGCNT)
Read: Anytime Write: Never
Table 8-18. DBGCNT Field Descriptions
Field 6–0 CNT[6:0] Description Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer. Table 8-19 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer.
Table 8-19. CNT Decoding Table
TBF (DBGSR) 0 0 0 CNT[6:0] 0000000 0000001 0000010 0000100 0000110 .. 1111100 1111110 0000000 0000010 .. .. 1111110 Description No data valid 32 bits of one line valid1 1 line valid 2 lines valid 3 lines valid .. 62 lines valid 63 lines valid 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 64 lines valid, oldest data has been overwritten by most recent data
0 1 1
1
This applies to Normal/Loop1/PurePC Modes when tracing from either CPU12X or XGATE only.
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8.3.2.7
Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR).
Table 8-20. State Control Register Access Encoding
COMRV 00 01 10 11 Visible State Control Register DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR
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8.3.2.7.1
Address: 0x0027
7
Debug State Control Register 1 (DBGSCR1)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-21. DBGSCR1 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State1, based upon the match event.
Table 8-22. State1 Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state2 Any match triggers to state3 Any match triggers to Final State Match2 triggers to State2....... Other matches have no effect Match2 triggers to State3....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2 Reserved Reserved Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
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8.3.2.7.2
Address: 0x0027
7
Debug State Control Register 2 (DBGSCR2)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-23. DBGSCR2 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State2, based upon the match event.
Table 8-24. State2 —Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state3 Any match triggers to Final State Match3 triggers to State1....... Other matches have no effect Match3 triggers to State3....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect Match2 triggers to State1..... Match3 trigger to Final State Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State Reserved Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
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8.3.2.7.3
Address: 0x0027
7
Debug State Control Register 3 (DBGSCR3)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
SC3 0
SC2 0
SC1 0
SC0 0
= Unimplemented or Reserved
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10 Write: If COMRV[1:0] = 10 and S12XDBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-25. DBGSCR3 Field Descriptions
Field 3–0 SC[3:0] Description These bits select the targeted next state whilst in State3, based upon the match event.
Table 8-26. State3 — Sequencer Next State Selection
SC[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Any match triggers to state1 Any match triggers to state2 Any match triggers to Final State Match0 triggers to State1....... Other matches have no effect Match0 triggers to State2....... Other matches have no effect Match0 triggers to Final State.......Match1 triggers to State1 Match1 triggers to State1....... Other matches have no effect Match1 triggers to State2....... Other matches have no effect Match1 triggers to Final State....... Other matches have no effect Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect Match2 triggers to Final State....... Other matches have no effect Match3 triggers to Final State....... Other matches have no effect Reserved Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
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8.3.2.7.4
Address: 0x0027
7
Debug Match Flag Register (DBGMFR)
6
5
4
3
2
1
0
R W Reset
0 0
0 0
0 0
0 0
MC3 0
MC2 0
MC1 0
MC0 0
= Unimplemented or Reserved
Figure 8-12. Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding flag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag is set, further triggers on the same channel have no affect.
8.3.2.8
Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparators B and D consist of four register bytes (three address bus compare registers and a control register). Each set of comparator registers is accessible in the same 8-byte window of the register address map and can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for comparators B and D differ from those of comparators A and C.
Table 8-27. Comparator Register Layout
0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F CONTROL ADDRESS HIGH ADDRESS MEDIUM ADDRESS LOW DATA HIGH COMPARATOR DATA LOW COMPARATOR DATA HIGH MASK DATA LOW MASK Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Comparators A,B,C,D Comparators A,B,C,D Comparators A,B,C,D Comparators A,B,C,D Comparator A and C only Comparator A and C only Comparator A and C only Comparator A and C only
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8.3.2.8.1
Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map.
Address: 0x0028
7 6 5 4 3 2 1 0
R W Reset
0 0
NDB 0
TAG 0
BRK 0
RW 0
RWE 0
SRC 0
COMPE 0
= Unimplemented or Reserved
Figure 8-13. Debug Comparator Control Register (Comparators A and C)
Address: 0x0028
7 6 5 4 3 2 1 0
R W Reset
SZE 0
SZ 0
TAG 0
BRK 0
RW 0
RWE 0
SRC 0
COMPE 0
Figure 8-14. Debug Comparator Control Register (Comparators B and D)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding. The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 8-28.
Table 8-28. Comparator Address Register Visibility
COMRV 00 01 10 11 Visible Comparator DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM DBGBCTL, DBGBAH, DBGBAM, DBGBAL DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM DBGDCTL, DBGDAH, DBGDAM, DBGDAL
Table 8-29. DBGXCTL Field Descriptions
Field 7 SZE (Comparators B and D) 6 NDB (Comparators A and C Description Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set. 0 Word/Byte access size is not used in comparison 1 Word/Byte access size is used in comparison Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. Furthermore data bus bits can be individually masked using the comparator data mask registers. This bit is only available for comparators A and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for comparators B and D. 0 Match on data bus equivalence to comparator register contents 1 Match on data bus difference to comparator register contents
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Table 8-29. DBGXCTL Field Descriptions (continued)
Field 6 SZ (Comparators B and D) 5 TAG Description Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. This bit position has NDB functionality for comparators A and C 0 Word access size will be compared 1 Byte access size will be compared Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue. 0 Trigger immediately on match 1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated Break — This bit controls whether a channel match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using DBGBRK. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed. Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator . The RW bit is not used if RWE = 0. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator. This bit is not used for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Determines mapping of comparator to CPU12X or XGATE 0 The comparator is mapped to CPU12X buses 1 The comparator is mapped to XGATE address and data buses Determines if comparator is enabled 0 The comparator is not enabled 1 The comparator is enabled for state sequence triggers or tag generation
4 BRK
3 RW
2 RWE
1 SRC 0 COMPE
Table 8-30 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Thus these bits are ignored if tagged triggering is selected.
Table 8-30. Read or Write Comparison Logic Table
RWE Bit 0 0 1 1 1 1 RW Bit x x 0 0 1 1 RW Signal 0 1 0 1 0 1 Comment RW not used in comparison RW not used in comparison Write No match No match Read
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8.3.2.8.2
Address: 0x0029
7
Debug Comparator Address High Register (DBGXAH)
6
5
4
3
2
1
0
R W Reset
0 0
Bit 22 0
Bit 21 0
Bit 20 0
Bit 19 0
Bit 18 0
Bit 17 0
Bit 16 0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-31. DBGXAH Field Descriptions
Field 6–0 Bit[22:16] Description Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is ignored for XGATE compares. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
8.3.2.8.3
Address: 0x002A
7
Debug Comparator Address Mid Register (DBGXAM)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 8-16. Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-32. DBGXAM Field Descriptions
Field 7–0 Bit[15:8] Description Comparator Address Mid Compare Bits— The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits [15:8] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
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8.3.2.8.4
Address: 0x002B
7
Debug Comparator Address Low Register (DBGXAL)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 8-17. Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-33. DBGXAL Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator will compare the address bus bits [7:0] to a logic one or logic zero. 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one
8.3.2.8.5
Address: 0x002C
7
Debug Comparator Data High Register (DBGXDH)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 8-18. Debug Comparator Data High Register (DBGXDH)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-34. DBGXAH Field Descriptions
Field 7–0 Bits[15:8] Description Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one
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8.3.2.8.6
Address: 0x002D
7
Debug Comparator Data Low Register (DBGXDL)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 8-19. Debug Comparator Data Low Register (DBGXDL)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-35. DBGXDL Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparators A and C. 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one
8.3.2.8.7
Address: 0x002E
7
Debug Comparator Data High Mask Register (DBGXDHM)
6
5
4
3
2
1
0
R W Reset
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12 0
Bit 11 0
Bit 10 0
Bit 9 0
Bit 8 0
Figure 8-20. Debug Comparator Data High Mask Register (DBGXDHM)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-36. DBGXDHM Field Descriptions
Field 7–0 Bits[15:8] Description Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit
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8.3.2.8.8
Address: 0x002F
7
Debug Comparator Data Low Mask Register (DBGXDLM)
6
5
4
3
2
1
0
R W Reset
Bit 7 0
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 0
Figure 8-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime. See Table 8-28 for visible register encoding. Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-37. DBGXDLM Field Descriptions
Field 7–0 Bits[7:0] Description Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register is available only for comparators A and C. 0 Do not compare corresponding data bit 1 Compare corresponding data bit
8.4
Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure mode, the S12XDBG module can generate breakpoints but tracing is not possible.
8.4.1
S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the trace buffer and can be used to cause breakpoints to the CPU12X or the XGATE module. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU12X and XGATE. Comparators can be configured to monitor address and databus. Comparators can also be configured to mask out individual data bus bits during a compare and to use R/W and word/byte access qualification in the comparison. When a match with a comparator register value occurs the associated control logic can trigger the state sequencer to another state (see Figure 8-22). Either forced or tagged triggers are possible. Using a forced trigger, the trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. Tracing of both CPU12X and/or XGATE bus activity is possible. Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals or by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads.
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8.4.2
Comparator Modes
The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor CPU12X or XGATE buses. Each comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C also compare the data buses to the data stored in DBGXDH, DBGXDL and allow masking of individual data bus bits. S12X comparator matches are disabled in BDM and during BDM accesses. The comparator match control logic configures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the specified range generates a match condition. The comparator configuration is controlled by the control register contents and the range control by the DBGC2 contents. On a match a trigger can initiate a transition to another state sequencer state (see Section 8.4.3”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare. Only comparators B and D feature SZE and SZ. The TAG bit in each comparator control register is used to determine the triggering condition. By setting TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). Whilst tagging, the RW, RWE, SZE, and SZ bits are ignored and the comparator register must be loaded with the exact opcode address. If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not verified again on subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data value when a subsequent match occurs. Comparators C and D can also be used to select an address range to trace from. This is determined by the TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 8-11. If the TRANGE bits select a range definition using comparator D, then comparator D is configured for trace range definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range definition using comparator C, then comparator C is configured for trace range definition and cannot be used for address bus comparisons. Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see Section 8.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 8.4.3.6”).
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8.4.2.1
Exact Address Comparator Match (Comparators A and C)
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible. Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match. Table 8-39 lists access considerations without data bus compare. Table 8-38 lists access considerations with data bus comparison. To compare byte accesses DBGXDH must be loaded with the data byte, the low byte must be masked out using the DBGXDLM mask register. On word accesses the data byte of the lower address is mapped to DBGXDH.
Table 8-38. Comparator A and C Data Bus Considerations
Access Word Byte Word Word Address ADDR[n] ADDR[n] ADDR[n] ADDR[n] DBGxDH Data[n] Data[n] Data[n] x DBGxDL Data[n+1] x x Data[n+1] DBGxDHM $FF $FF $FF $00 DBGxDLM $FF $00 $00 $FF Example Valid Match MOVW #$WORD ADDR[n] MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] MOVW #$WORD ADDR[n]
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents.
8.4.2.2
Exact Address Comparator Match (Comparators B and D)
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not lead to match.
Table 8-39. Comparator Access Size Considerations
Comparator Comparators A and C Comparators B and D Comparators B and D Comparators B and D
1
Address ADDR[n]
SZE —
SZ8 —
Condition For Valid Match Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word and byte accesses of ADDR[n]1 MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n] Word accesses of ADDR[n]1 MOVW #$WORD ADDR[n] Byte accesses of ADDR[n] MOVB #$BYTE ADDR[n]
ADDR[n]
0
X
ADDR[n] ADDR[n]
1 1
0 1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address used in the code.
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8.4.2.3
Data Bus Comparison NDB Dependency
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match.
Table 8-40. NDB and MASK bit dependency
NDB 0 0 1 1 DBGxDHM[n] / DBGxDLM[n] 0 1 0 1 Comment Do not compare data bus bit. Compare data bus bit. Match on equivalence. Do not compare data bus bit. Compare data bus bit. Match on difference.
8.4.2.4
Range Comparisons
When using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator C data and data mask registers. Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both COMPEC and COMPED must be set. If a range mode is selected SRCA and SRCC select the source (S12X or XGATE), SRCB and SRCD are ignored. The comparator A and C BRK bits are used for the AB and CD ranges respectively, the comparator B and D BRK bits are ignored in range mode. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries. 8.4.2.4.1 Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons by the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one
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comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 8.4.2.4.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are from an unexpected range. In forced trigger modes the outside range trigger would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $7FFFFF or lower range limit to $000000 respectively. When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR register and hence vector address can be modified.
8.4.3
Trigger Modes
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in the following sections.
8.4.3.1
Forced Trigger On Comparator Match
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines the next state for each trigger. Forced triggers are generated as soon as the matching address appears on the address bus, which in the case of opcode fetches occurs several cycles before the opcode execution. For this reason a forced trigger of an opcode address precedes a tagged trigger at the same address by several cycles.
8.4.3.2
Trigger On Comparator Related Taghit
If a CPU12X or XGATE taghit occurs, a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first generate tags based on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU12X/XGATE. The state control register for the current state determines the next state for each trigger.
8.4.3.3
External Tagging Trigger
In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session
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and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device emulation modes.
8.4.3.4
Trigger On XGATE S/W Breakpoint Request
The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU12X immediately independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1 determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI).
8.4.3.5
TRIG Immediate Trigger
Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. If configured for begin or mid aligned tracing, this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued immediately (end alignment) or when tracing has completed (begin or mid alignment).
8.4.3.6
Trigger Priorities
In case of simultaneous triggers, the priority is resolved according to Table 8-41. The lower priority trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger of a higher priority. The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches independent of current state sequencer state. When configured for range modes a simultaneous match of comparators A and C generates an active match0 whilst match2 is suppressed. If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
Table 8-41. Trigger Priorities
Priority Highest Source XGATE TRIG External TAGHI/TAGLO Match0 (force or tag hit) Match1 (force or tag hit) Match2 (force or tag hit) Lowest Match3 (force or tag hit) Action Immediate forced breakpoint......(Tracing terminated immediately). Trigger immediately to final state (begin or mid aligned tracing enabled) Trigger immediately to state 0 (end aligned or no tracing enabled) Enter State0 Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers Trigger to next state as defined by state control registers
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8.4.4
State Sequence Control
ARM = 0 State 0 (Disarmed) ARM = 1 State1 ARM = 0 Session Complete (Disarm) Final State ARM = 0 State3 State2
Figure 8-22. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and depend upon a selected trigger mode condition being met. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. Alternatively by setting the TRIG bit in DBGSC1, the state machine can be triggered to state0 or Final State depending on tracing alignment. A tag hit through TAGHI/TAGLO brings the state sequencer immediately into state0, causes a breakpoint, if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits TALIGN[1:0]. Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed. An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint request to the CPU12X immediately.
8.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 8.3.2.3”). If TSOURCE in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the
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DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed.
8.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace information in the RAM array in a circular buffer format. The RAM array can be accessed through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace buffer line is read, an internal pointer into the RAM is incremented so that the next read will receive fresh information. Data is stored in the format shown in Table 8-42. After each store the counter register bits DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active but tracing of XGATE activity is still possible. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.
8.4.5.1
Trace Trigger Alignment
Using the TALIGN bits (see Section 8.3.2.3”) it is possible to align the trigger with the end, the middle, or the beginning of a tracing session. If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered. The transition to Final State if End is selected signals the end of the tracing session. The transition to Final State if Mid is selected signals that another 32 lines will be traced before ending the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. 8.4.5.1.1 Storing with Begin-Trigger
Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 8.4.5.1.2 Storing with Mid-Trigger
Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed. When the trigger condition is met, another 32 lines will be traced before ending the tracing session, irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is disarmed and no more data is stored. Using Mid-trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
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8.4.5.1.3
Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
8.4.5.2
Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in the DBGTCR register. In each mode tracing of XGATE or CPU12X information is possible. The source for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the following subsections. The trace buffer organization is shown in Table 8-42. 8.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored. COF addresses are defined as follows for the CPU12X: • Source address of taken conditional branches (long, short, bit-conditional, and loop primitives) • Destination address of indexed JMP, JSR, and CALL instruction. • Destination address of RTI, RTS, and RTC instructions • Vector address of interrupts, except for SWI and BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as change of flow and are not stored in the trace buffer. COF addresses are defined as follows for the XGATE: • Source address of taken conditional branches • Destination address of indexed JAL instructions. • First XGATE code address in a thread Change-of-flow addresses stored include the full 23-bit address bus of CPU12X, the 16-bit address bus for the XGATE module and an information byte, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When an CPU12X COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program flow gets exectuted after the interrupt service routine.
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In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place.
MARK1 MARK2 SUB_1 LDX JMP NOP BRN NOP DBNE LDAB STAB RTI #SUB_1 0,X ; IRQ interrupt occurs during execution of this ; ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 ; ; Source address TRACE BUFFER ENTRY 4 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 ;
*
ADDR1 IRQ_ISR
A,PART5 #$F0 VAR_C1
The execution flow taking into account the IRQ is as follows
MARK1 IRQ_ISR LDX JMP LDAB STAB RTI BRN NOP DBNE #SUB_1 0,X #$F0 VAR_C1 * A,PART5 ; ; ; ; ;
SUB_1 ADDR1
8.4.5.2.2
Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the S12XDBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches.
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Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the S12XDBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the background comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below:
LOOP INX BRCLR CMPTMP,#$0c, LOOP ; 1-byte instruction fetched by 1st P-cycle of BRCLR ; the BRCLR instruction also will be fetched by 1st ; P-cycle of BRCLR ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE
LOOP2
BRN NOP DBNE
* A,LOOP2
8.4.5.2.3
Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. In the case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information byte entries to the trace buffer, for each address byte entry. The information byte indicates the size of access (word or byte) and the type of access (read or write). When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the time of the trace buffer entry. When tracing CPU12X activity alone in Detail Mode, the address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses comparators C and D to define an address range inside which CPU12X activity should be traced (see Table 8-42). Thus the traced CPU12X activity can be restricted to particular register range accesses. When tracing XGATE activity in Detail Mode, all load and store cycles are traced. Additionally the CPU12X program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of CPU12X activity. 8.4.5.2.4 Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes, are stored. In Pure PC Mode, tracing from the XGATE the PC addresses of all executed opcodes are stored.
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8.4.5.3
Trace Buffer Organization
Referring to Table 8-42. An X prefix denotes information from the XGATE module, a C prefix denotes information from the CPU12X. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst tracing from XGATE or CPU12X only, in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry. XGATE and CPU12X COFs occur independently of each other and the profile of COFs for the two sources is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one source, there may be many COFs from the other source, depending on user code. COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF, but is simply a snapshot of the PC contents at the time of the COF from the other source. Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Table 8-42. Trace Buffer Organization
Mode 8-Byte Wide Word Buffer 7 CXINF1 CXINF2 CXINF1 CXINF2 XINF0 XINF1 XINF1 XINF3 CINF1 CINF3 CPCH1 CPCH3 6 CADRH1 CADRH2 CADRH1 CADRH2 5 CADRM1 CADRM2 CADRM1 CADRM2 XPCM0 XPCM1 XPCM1 XPCM3 CPCM1 CPCM3 4 CADRL1 CADRL2 CADRL1 CADRL2 XPCL0 XPCL1 XPCL1 XPCL3 CPCL1 CPCL3 3 XDATAH1 XDATAH2 CDATAH1 CDATAH2 CINF0 CINF1 XINF0 XINF2 CINF0 CINF2 CPCH0 CPCH2 2 XDATAL1 XDATAL2 CDATAL1 CDATAL2 CPCH0 CPCH1 1 XADRM1 XADRM2 XADRM1 XADRM2 CPCM0 CPCM1 XPCM0 XPCM2 CPCM0 CPCM2 0 XADRL1 XADRL2 XADRL1 XADRL2 CPCL0 CPCL1 XPCL0 XPCL2 CPCL0 CPCL2
XGATE Detail CPU12X Detail Both Other Modes XGATE Other Modes CPU12X Other Modes
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8.4.5.3.1
Information Byte Organization
The format of the control information byte is dependent upon the active trace mode as described below. In Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control information. In Detail Mode, CXINF contains the control information XGATE Information Byte
Bit 7 XSD Bit 6 XSOT Bit 5 XCOT Bit 4 XDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Figure 8-23. XGATE Information Byte XINF Table 8-43. XINF Field Descriptions
Field 7 XSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source address 1 Destination address or Start of Thread or Continuation of Thread Source Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread address. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a start of thread 1 Stored address from a start of thread Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing. NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels. 0 Stored address not from a continuation of thread 1 Stored address from a continuation of thread Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid
6 XSOT
5 XCOT
4 XDV
XGATE info bit setting
XGATE FLOW XSD XSOT XCOT
SOT1
SOT2
JAL
RTS
COT1
RTS
Figure 8-24. XGATE info bit setting
Figure 8-24 indicates the XGATE information bit setting when switching between threads, the initial thread starting at SOT1 and continuing at COT1 after the higher priority thread2 has ended.
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CPU12X Information Byte
Bit 7 CSD Bit 6 CVA Bit 5 0 Bit 4 CDV Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Figure 8-25. CPU12X Information Byte CINF Table 8-44. CINF Field Descriptions
Field 7 CSD Description Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source address 1 Destination address Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal and Loop1 mode tracing. This bit has no meaning in Pure PC mode. 0 Indexed jump destination address 1 Vector destination address Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid. 0 Trace buffer entry is invalid 1 Trace buffer entry is valid
6 CVA
4 CDV
CXINF Information Byte
Bit 7 CFREE Bit 6 CSZ Bit 5 CRW Bit 4 COCF Bit 3 XACK Bit 2 XSZ Bit 1 XRW Bit 0 XOCF
Figure 8-26. Information Byte CXINF
This describes the format of the information byte used only when tracing from CPU12X or XGATE in Detail Mode. When tracing from the CPU12X in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made by the CPU12X, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The CPU12X entry stored on the same line is a snapshot of the CPU12X program counter. In this case the XSZ and XRW bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF bits indicate if the simultaneous CPU12X cycle is a free cycle or opcode fetch cycle.
Table 8-45. CXINF Field Descriptions
Field 7 CFREE Description CPU12X Free Cycle Indicator — This bit indicates if the stored CPU12X address corresponds to a free cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle MC9S12XE-Family Reference Manual Rev. 1.07 Freescale Semiconductor 339
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Table 8-45. CXINF Field Descriptions (continued)
Field 6 CSZ Description Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains valid information when tracing CPU12X activity in Detail Mode. 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing CPU12X activity in Detail Mode. 0 Write Access 1 Read Access CPU12X Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit only contains valid information when tracing the CPU12X accesses in Detail Mode. 0 Stored information corresponds to free cycle 1 Stored information does not correspond to free cycle Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Word Access 1 Byte Access Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in Detail Mode. 0 Write Access 1 Read Access XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.This bit only contains valid information when tracing the CPU12X accesses in Detail Mode. 0 Stored information does not correspond to opcode fetch cycle 1 Stored information corresponds to opcode fetch cycle
5 CRW
4 COCF
3 XACK
2 XSZ
1 XRW
0 XOCF
8.4.5.4
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module, the XGATE or the CPU12X provided the S12XDBG module is not armed, is configured for tracing and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid 64-bit lines can be determined. DBGCNT will not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
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DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 8-42. The bytes containing invalid information (shaded in Table 8-42) are also read out. Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur.
8.4.5.5
Trace Buffer Reset State
The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session. Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer.
8.4.6
Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer. Each comparator control register features a TAG bit, which controls whether the comparator match will cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address for the trigger to occur. Both CPU12X and XGATE opcodes can be tagged with the comparator register TAG bits. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the size of access. Thus these bits are ignored if tagged triggering is selected. When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
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S12X tagging is disabled when the BDM becomes active. XGATE tagging is possible when the BDM is active.
8.4.6.1
External Tagging using TAGHI and TAGLO
External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU12X opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other. External tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge of the external clock (ECLK) performs the function indicated in the Table 8-46. It is possible to tag both bytes of an instruction word. If a taghit occurs, a breakpoint can be generated as defined by the DBGBRK and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag is replaced by a new one.
Table 8-46. Tag Pin Function
TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes
8.4.6.2
Unconditional Tagging Function
In emulation modes a low assertion of PE5/TAGLO/MODA in the 7th or 8th bus cycle after reset enables the unconditional tagging function, allowing immediate tagging via TAGHI/TAGLO with breakpoint to BDM independent of the ARM, BDM and DBGBRK bits. Conversely these bits are not affected by unconditional tagging. The unconditional tagging function remains enabled until the next reset. This function allows an immediate entry to BDM in emulation modes before user code execution. The TAGLO assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior RESET pin assertion lasts the full 192 bus cycles.
8.4.7
Breakpoints
Breakpoints can be generated as follows. • Through XGATE software breakpoint requests. • From comparator channel triggers to final state. • Using software to write to the TRIG bit in the DBGC1 register. • From taghits generated using the external TAGHI and TAGLO pins. Breakpoints generated by the XGATE module or via the BDM BACKGROUND command have no affect on the CPU12X in STOP or WAIT mode.
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8.4.7.1
XGATE Software Breakpoints
The XGATE software breakpoint instruction BRK can request an CPU12X breakpoint, via the S12XDBG module. In this case, if the XGSBPE bit is set, the S12XDBG module immediately generates a forced breakpoint request to the CPU12X, the state sequencer is returned to state0 and tracing, if active, is terminated. If configured for BEGIN trigger and tracing has not yet been triggered from another source, the trace buffer contains no information. Breakpoint requests from the XGATE module do not depend upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the CPU12X program flow, but it is necessary to set XGSBPE. Furthermore, if a breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an CPU12X breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module.
8.4.7.2
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-47). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment.
Table 8-47. Breakpoint Setup For Both XGATE and CPU12X Breakpoints
BRK 0 0 0 0 0 0 1 1 x TALIGN 00 00 01 01 10 10 00,01,10 00,01,10 11 DBGBRK[n] 0 1 0 1 0 1 1 0 x Breakpoint Alignment Fill Trace Buffer until trigger (no breakpoints — keep running) Fill Trace Buffer until trigger, then breakpoint request occurs Start Trace Buffer at trigger (no breakpoints — keep running) Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full Store a further 32 Trace Buffer line entries after trigger (no breakpoints — keep running) Store a further 32 Trace Buffer line entries after trigger Request breakpoint after the 32 further Trace Buffer entries Terminate tracing and generate breakpoint immediately on trigger Terminate tracing immediately on trigger Reserved
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8.4.7.3
Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-47). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the S12XDBG module is disarmed.
8.4.7.4
Breakpoints Via TAGHI Or TAGLO Pin Taghits
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is always end aligned, independent of internal channel trigger alignment configuration.
8.4.7.5
S12XDBG Breakpoint Priorities
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a comparator channel, it has no effect, since tracing has already started. If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of the tracing trigger alignment bits TALIGN[1:0]. 8.4.7.5.1 S12XDBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is active, the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
Table 8-48. Breakpoint Mapping Summary
DBGBRK[1] (DBGC1[3]) 0 1 1 1 1 1 BDM Bit (DBGC1[4]) X 0 0 1 1 1 BDM Enabled X X X 0 1 1 BDM Active X 0 1 X 0 1 S12X Breakpoint Mapping No Breakpoint Breakpoint to SWI No Breakpoint Breakpoint to SWI Breakpoint to BDM No Breakpoint
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually
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executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU12X flow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code and DBG breakpoint could occur simultaneously. The CPU12X ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re triggering a breakpoint. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. To avoid re triggering a breakpoint at the same location reconfigure the S12XDBG module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program flow past the tagged instruction. An XGATE software breakpoint is forced immediately, the tracing session terminated and the XGATE module execution stops. The user can thus determine if an XGATE breakpoint has occurred by reading out the XGATE program counter over the BDM interface.
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Chapter 9 Security (S12XE9SECV2)
Table 9-1. Revision History
Version Number 02.00 02.01 02.02 Revision Date 27 Aug 2004 21 Feb 2007 19 Apr 2007 Effective Date 08 Sep 2004 21 Feb 2007 19 Apr 2007 Author Description of Changes reviewed and updated for S12XD architecture added S12XE, S12XF and S12XS architectures corrected statement about Backdoor key access via BDM on XE, XF, XS
9.1
Introduction
NOTE No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH and/or EEPROM difficult for unauthorized users.
This specification describes the function of the security mechanism in the S12XE chip family (9SEC).
9.1.1
Features
The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the S12XE chip family (in secure mode) are: • Protect the content of non-volatile memories (Flash, EEPROM) • Execution of NVM commands is restricted • Disable access to internal memory via background debug module (BDM) • Disable access to internal Flash/EEPROM in expanded modes • Disable debugging features for the CPU and XGATE
9.1.2
Modes of Operation
Table 9-2 gives an overview over availability of security relevant features in unsecure and secure modes.
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Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XE
Unsecure Mode NS Flash Array Access EEPROM Array Access NVM Commands BDM DBG Module Trace XGATE Debugging External Bus Interface Internal status visible multiplexed on external bus ✔ ✔ ✔
(2)
Secure Mode EX ✔1 ✔ ✔
2
SS ✔ ✔ ✔ ✔ ✔ ✔ — —
NX ✔(1) ✔ ✔
2
ES ✔1 ✔ ✔
2
ST ✔1 ✔ ✔ ✔ ✔ ✔ ✔ —
NS ✔ ✔ ✔
2
SS ✔ ✔ ✔
2
NX — — ✔
2
ES — — ✔
2
EX — — ✔
2
ST — — ✔2 — — — ✔ —
✔ ✔ ✔ — —
✔ ✔ ✔ ✔ —
✔ ✔ ✔ ✔ ✔
✔ ✔ ✔ ✔ ✔
— — — — —
✔(3) — — — —
— — — ✔ —
— — — ✔ ✔
— — — ✔ ✔
Internal accesses visible — — — — — ✔ — — — — — ✔ on external bus 1. Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed information. 2. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. 3. BDM hardware commands restricted to peripheral registers only.
9.1.3
Securing the Microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence.
7 6 5 4 3 2 1 0
0xFF0F
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
Figure 9-1. Flash Options/Security Byte
The meaning of the bits KEYEN[1:0] is shown in Table 9-3. Please refer to Section 9.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information.
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Table 9-3. Backdoor Key Access Enable Bits
KEYEN[1:0] 00 01 10 11 Backdoor Key Access Enabled 0 (disabled) 0 (disabled) 1 (enabled) 0 (disabled)
The meaning of the security bits SEC[1:0] is shown in Table 9-4. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 9-4. Security Bits
SEC[1:0] 00 01 10 11 Security State 1 (secured) 1 (secured) 0 (unsecured) 1 (secured)
NOTE Please refer to the Flash block guide for actual security configuration (in section “Flash Module Security”).
9.1.4
Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller:
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9.1.4.1
• • • •
Normal Single Chip Mode (NS)
Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled.
9.1.4.2
• • • • •
Special Single Chip Mode (SS)
BDM firmware commands are disabled. BDM hardware commands are restricted to the register space. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands depends on the security state of the device. The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked.
9.1.4.3
• • • • •
Expanded Modes (NX, ES, EX, and ST)
BDM operation is completely disabled. Internal Flash memory and EEPROM are disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the FTM block guide for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled
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9.1.5
Unsecuring the Microcontroller
Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes)
9.1.5.1
Unsecuring the MCU Using the Backdoor Key Access
In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that: • • • The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been programmed to a valid value. The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’. In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations.
The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF.
9.1.6
Reprogramming the Security Bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that: • The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is first disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte. • The Flash sector containing the Flash options/security byte is not protected.
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9.1.7
Complete Memory Erase (Special Modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset.
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Chapter 10 XGATE (S12XGATEV3) Revision History
Version Number 03.22 03.23 03.24
Date 6 Oct 2005 14 Dec 2005 17 Jan 2006
Author Dirk Heisswolf Dirk Heisswolf Dirk Heisswolf Internal updates Updated code example Internal updates
Description of Changes
10.1
Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 10-1 gives an overview on the XGATE architecture. This document describes the functionality of the XGATE module, including: • XGATE registers (Section 10.3, “Memory Map and Register Definition”) • XGATE RISC core (Section 10.4.1, “XGATE RISC Core”) • Hardware semaphores (Section 10.4.4, “Semaphores”) • Interrupt handling (Section 10.5, “Interrupts”) • Debug features (Section 10.6, “Debug Mode”) • Security (Section 10.7, “Security”) • Instruction set (Section 10.8, “Instruction Set”)
10.1.1
Glossary of Terms
XGATE Request
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A service request from a peripheral module which is directed to the XGATE by the S12X_INT module (see Figure 10-1). Each XGATE request attempts to activate a XGATE channel at a certain priority level. XGATE Channel The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request Vector, Interrupt Flag) which are associated with a particular XGATE Request. XGATE Channel ID A 7-bit identifier associated with an XGATE channel. In S12XE designs valid Channel IDs range from $0D to $78. XGATE Priority Level A priority ranging from 1 to 7 which is associated with an XGATE channel. The priority level of an XGATE channel is selected in the S12X_INT module. XGATE Register Bank A register bank consists of registers R1-R7, CCR and the PC. Each interrupt level is associated with one register bank. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel Special XGATE channel that is not associated with any peripheral service request. A Software Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module. XGATE Semaphore A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE. (see Section 10.4.4, “Semaphores”) XGATE Thread A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request. XGATE Debug Mode A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables the XGATE’s debug features (see Section 10.6, “Debug Mode”). XGATE Software Error The XGATE is able to detect a number of error conditions caused by erratic software (see Section 10.4.5, “Software Error Detection”). These error conditions will cause the XGATE to seize program execution and flag an Interrupt to the S12X_CPU. Word A 16 bit entity. Byte An 8 bit entity.
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10.1.2
Features
The XGATE module includes these features: • Data movement between various targets (i.e. Flash, RAM, and peripheral modules) • Data manipulation through built in RISC core • Provides up to 108 XGATE channels, including 8 software triggered channels • Interruptible thread execution • Two register banks to support fast context switching between threads • Hardware semaphores which are shared between the S12X_CPU and the XGATE module • Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer • Software error detection to catch erratic application code
10.1.3
Modes of Operation
There are four run modes on S12XE devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active) In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 10.3.1.1, “XGATE Control Register (XGMCTL)”).
10.1.4
Block Diagram
Figure 10-1 shows a block diagram of the XGATE.
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Peripheral Interrupts
S12X_INT
XGATE Interrupts (XGIF) XGATE Requests
XGATE
Interrupt Flags Semaphores
Software Triggers
RISC Core
Software Triggers
SWE Interrupt
Software Error Logic
Data/Code
S12X_DBG
Peripherals S12X_MMC
Figure 10-1. XGATE Block Diagram
10.2
External Signal Description
The XGATE module has no external pins.
10.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Figure 10-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved registers have no effect.
10.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bits and field functions follow the register diagrams, in bit order.
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Register Name 0x0000 R XGMCTL
15 0
14 0
13 0
12 0
11 0
10 0
9 0
XG SWEFM
8 0
7
6
5
4
3
2 0
1
0
XG XG XG XGEM XGSSM W FRZM DBGM FACTM
XG XGE XGFRZ XGDBG XGSS FACT XGIEM 0
XG XGIE SWEF
0x0002 R XGCHID W 0x0003 R XGCHPL W 0x0004 R Reserved W 0x0005 R XGISPSEL W 0x0006 R XGISP74 W 0x0006 R XGISP31 W 0x0006 XGVBR R W = Unimplemented or Reserved
XGCHID[6:0]
0
0
0
0
0
XGCHPL[2:0]
0
0
0
0
0
0
XGISPSEL[1:0] 0 0 0
XGISP74[15:1] XGISP31[15:1] XGVBR[15:1]
Figure 10-2. XGATE Register Summary (Sheet 1 of 3)
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127 0x0008 XGIF R W 111 0x000A XGIF R W 0
126 0
125 0
124 0
123 0
122 0
121 0
120
119
118
117
116
115
114
113
112
XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
95 0x000C XGIF R W
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
79 0x000E XGIF R W
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
63 0x0010 XGIF R W
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
47 0x0012 XGIF R W
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
31 0x0014 XGIF R W
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
15 0x0016 XGIF R W
14
13
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
XGIF_0F XGIF_0E XGIF_0D
= Unimplemented or Reserved
Figure 10-2. XGATE Register Summary (Sheet 2 of 3)
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15 0x0018 R XGSWTM W 0x001A R XGSEMM W 0x001C R Reserved W 0x001D XGCCR 0x001E XGPC R W R W 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7
6
5
4
3
2
1
0
XGSWTM[7:0] 0 0 0 0 0 0 0 0
XGSWT[7:0]
XGSEMM[7:0]
XGSEM[7:0]
0
0
0
0
XGN XGZ
XGV XGC
XGPC
0x0020 R Reserved W 0x0021 R Reserved W 0x0022 XGR1 0x0024 XGR2 0x0026 XGR3 0x0028 XGR4 0x002A XGR5 0x002C XGR6 0x002E XGR7 R W R W R W R W R W R W R W = Unimplemented or Reserved XGR1
XGR2
XGR3
XGR4
XGR5
XGR6
XGR7
Figure 10-2. XGATE Register Summary (Sheet 3 of 3)
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10.3.1.1
XGATE Control Register (XGMCTL)
All module level switches and flags are located in the XGATE Module Control Register Figure 10-3.
Module Base +0x00000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 XGEM 0
0
0
0 XG SSM 0
0 XG FACTM 0
0
0
0 XGE 0 XGFRZ XGDBG XGSS XGFACT 0 0 0 0
0
XG XG FRZM DBGM 0 0
XG XGIEM SWEFM 0 0 0
XG SWEF 0
XGIE 0
0
= Unimplemented or Reserved
Figure 10-3. XGATE Control Register (XGMCTL)
Read: Anytime Write: Anytime
Table 10-1. XGMCTL Field Descriptions (Sheet 1 of 3)
Field 15 XGEM Description XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is written to the XGEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGE in the same bus cycle 1 Enable write access to the XGE in the same bus cycle XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared if a "1" is written to the XGFRZM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFRZ in the same bus cycle 1 Enable write access to the XGFRZ in the same bus cycle XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared if a "1" is written to the XGDBGM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGDBG in the same bus cycle 1 Enable write access to the XGDBG in the same bus cycle XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a "1" is written to the XGSSM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSS in the same bus cycle 1 Enable write access to the XGSS in the same bus cycle
14 XGFRZM
13 XGDBGM
12 XGSSM
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Table 10-1. XGMCTL Field Descriptions (Sheet 2 of 3)
Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGFACT in the same bus cycle 1 Enable write access to the XGFACT in the same bus cycle
9 XGSWEF Mask — This bit controls the write access to the XGSWEF bit. The XGSWEF bit can only be cleared XGSWEFM if a "1" is written to the XGSWEFM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSWEF in the same bus cycle 1 Enable write access to the XGSWEF in the same bus cycle 8 XGIEM XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1" is written to the XGIEM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGIE in the same bus cycle 1 Enable write access to the XGIE in the same bus cycle XGATE Module Enable (Request Enable)— This bit enables incoming XGATE requests from the S12X_INT module. If the XGE bit is cleared, pending XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will continue to run. Read: 0 Incoming requests are disabled 1 Incoming requests are enabled Write: 0 Disable incoming requests 1 Enable incoming requests Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active). Read: 0 RISC core operates normally in Freeze (BDM active) 1 RISC core stops in Freeze Mode (BDM active) Write: 0 Don’t stop RISC core in Freeze Mode (BDM active) 1 Stop RISC core in Freeze Mode (BDM active) XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see Section 10.6, “Debug Mode”). Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see S12X_DBG Section), or by writing a "1" to this bit. Read: 0 RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
7 XGE
6 XGFRZ
5 XGDBG
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Chapter 10 XGATE (S12XGATEV3)
Table 10-1. XGMCTL Field Descriptions (Sheet 3 of 3)
Field 4 XGSS Description XGATE Single Step — This bit forces the execution of a single instruction.1 Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed. Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE idle periods Read: 0 XGATE will only flag activity if it is not idle or in debug mode. 1 XGATE will always signal activity to the MCU. Write: 0 Only flag activity if not idle or in debug mode. 1 Always signal XGATE activity. XGATE Software Error Flag — This bit signals a software error. It is set whenever the RISC core detects an error condition2. The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread and cause the XGATE to become idle. Read: 0 No software error detected 1 Software error detected Write: 0 No effect 1 Clears the XGSWEF bit XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module Read: 0 All outgoing XGATE interrupts disabled (except software error interrupts) 1 All outgoing XGATE interrupts enabled Write: 0 Disable all outgoing XGATE interrupts (except software error interrupts) 1 Enable all outgoing XGATE interrupts
3 XGFACT
1 XGSWEF
0 XGIE
1 2
Refer to Section 10.6.1, “Debug Features” Refer to Section 10.4.5, “Software Error Detection”
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.2
XGATE Channel ID Register (XGCHID)
The XGATE Channel ID Register (Figure 10-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads. Refer to Section 10.6.1, “Debug Features” for further information.
Module Base +0x0002
7 6 5 4 3 2 1 0
R W Reset
0 0 0 0 0
XGCHID[6:0] 0 0 0 0
= Unimplemented or Reserved
Figure 10-4. XGATE Channel ID Register (XGCHID)
Read: Anytime Write: In Debug Mode1
Table 10-2. XGCHID Field Descriptions
Field Description
6–0 Request Identifier — ID of the currently active channel XGCHID[6:0]
10.3.1.3
XGATE Channel Priority Level (XGCHPL)
The XGATE Channel Priority Level Register (Figure 10-5) shows the priority level of the current thread. In debug mode this register can be used to select a priority level when launching a thread (see Section 10.6.1, “Debug Features”).
Module Base +0x0003
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0 0
XGCHPL[2:0] 0 0
= Unimplemented or Reserved
Figure 10-5. XGATE Channel Priority Level Register (XGCHPL)
Read: Anytime Write: In Debug Mode1
1. Refer to Section 10.6.1, “Debug Features” MC9S12XE-Family Reference Manual Rev. 1.07 Freescale Semiconductor 363
Chapter 10 XGATE (S12XGATEV3)
Table 10-3. XGCHPL Field Descriptions
Field 2-0 XGCHPL[2:0] Description Priority Level— Priority level of the currently active channel
10.3.1.4
XGATE Initial Stack Pointer Select Register (XGISPSEL)
The XGATE Initial Stack Pointer Select Register (Figure 10-6) determines the register which is mapped to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting this register to a channel priority level (non-zero value) selects the corresponding Initial Stack Pointer Registers XGISP74 or XGISP31 (see Table 10-5).
Module Base +0x0005
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
XGISPSEL[1:0] 0 0
= Unimplemented or Reserved
Figure 10-6. XGATE Initial Stack Pointer Select Register (XGISPSEL)
Read: Anytime Write: Anytime
Table 10-4. XGISPSEL Field Descriptions
Field Description
1-0 Register select— Determines whether XGISP74, XGISP31, or XGVBR is mapped to “Module Base +0x0006”. XGISPSEL[1:0] See Table 10-5.
Table 10-5. XGISP74, XGISP31, XGVBR Mapping
XGISPSEL[1:0] 3 2 1 0 Register Mapped to “Module Base +0x0006“ Reserved XGISP74 XGISP31 XGVBR
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.5
XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
The XGISP74 register is intended to point to the stack region that is used by XGATE channels of priority 7 to 4. Every time a thread of such priority is started, RISC core register R7 will be initialized with the content of XGISP74.
Module Base +0x0006
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0
XGISP74[15:1] 0 0 0 0 0 0 0 0 0
0 0
= Unimplemented or Reserved
Figure 10-7. XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
Read: Anytime Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-6. XGISP74 Field Descriptions
Field 15–1 XBISP74[15:1] Description Initial Stack Pointer— The XGISP74 register holds the initial value of RISC core register R7, for threads of priority 7 to 4.
10.3.1.6
XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
The XGISP31 register is intended to point to the stack region that is used by XGATE channels of priority 3 to 1. Every time a thread of such priority is started, RISC core register R7 will be initialized with the content of XGISP31.
Module Base +0x0006
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0
XGISP31[15:1] 0 0 0 0 0 0 0 0 0
0 0
= Unimplemented or Reserved
Figure 10-8. XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
Read: Anytime Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-7. XGISP31 Field Descriptions
Field 15–1 XBISP31[15:1] Description Initial Stack Pointer— The XGISP31 register holds the initial value of RISC core register R7, for threads of priority 3 to 1.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.7
XGATE Vector Base Address Register (XGVBR)
The Vector Base Address Register (Figure 10-9) determines the location of the XGATE vector block (see Section Figure 10-23., “XGATE Vector Block).
Module Base +0x0006
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 1 1 1 1 1 1 1
XGVBR[15:1] 0 0 0 0 0 0 0 0
0 0
= Unimplemented or Reserved
Figure 10-9. XGATE Vector Base Address Register (XGVBR)
Read: Anytime Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-8. XGVBR Field Descriptions
Field Description
15–1 Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE XBVBR[15:1] memory map.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.8
XGATE Channel Interrupt Flag Vector (XGIF)
The XGATE Channel Interrupt Flag Vector (Figure 10-10) provides access to the interrupt flags of all channels. Each flag may be cleared by writing a "1" to its bit location. Refer to Section 10.5.2, “Outgoing Interrupt Requests” for further information.
Module Base +0x0008
127 126 125 124 123 122 121 120
XGIF_78
119
XGF_77
118
117
116
115
114
113
112
R W Reset
0 0
111
0 0
110
0 0
109
0 0
108
0 0
107
0 0
106
0 0
105
XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
0
104
0
103
XGF_67
0
102
0
101
0
100
0
99
0
98
0
97
0
96
R W Reset
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68
XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
0
95
0
94
0
93
0
92
0
91
0
90
0
89
0
88
0
87
XGF_57
0
86
0
85
0
84
0
83
0
82
0
81
0
80
R W Reset
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58
XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
0
79
0
78
0
77
0
76
0
75
0
74
0
73
0
72
0
71
0
70
0
69
0
68
0
67
0
66
0
65
0
64
R W Reset
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
0
63
0
62
0
61
0
60
0
59
0
58
0
57
0
56
0
55
0
54
0
53
0
52
0
51
0
50
0
49
0
48
R W Reset
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
0
47
0
46
0
45
0
44
0
43
0
42
0
41
0
40
0
39
0
38
0
37
0
36
0
35
0
34
0
33
0
32
R W Reset
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
0
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
R W Reset
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
R W Reset
XGIF_0F XGIF_0E XGIF_0D
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
= Unimplemented or Reserved
Figure 10-10. XGATE Channel Interrupt Flag Vector (XGIF)
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Chapter 10 XGATE (S12XGATEV3)
Read: Anytime Write: Anytime
Table 10-9. XGIV Field Descriptions
Field 127–9 XGIF[78:9] Description Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core (see SIF instruction on page 10-455). Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Section “Interrupts” of the SoC Guide for a list of implemented Interrupts. Read: 0 Channel interrupt is not pending 1 Channel interrupt is pending if XGIE is set Write: 0 No effect 1 Clears the interrupt flag
NOTE Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0])
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.9
XGATE Software Trigger Register (XGSWT)
The eight software triggers of the XGATE module can be set and cleared through the XGATE Software Trigger Register (Figure 10-11). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle. Refer to Section 10.5.2, “Outgoing Interrupt Requests” for further information.
Module Base +0x00018
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
XGSWTM[7:0]
XGSWT[7:0] 0 0 0 0 0
Figure 10-11. XGATE Software Trigger Register (XGSWT)
Read: Anytime Write: Anytime
Table 10-10. XGSWT Field Descriptions
Field Description
15–8 Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access. Read: These bits will always read "0". Write: 0 Disable write access to the XGSWT in the same bus cycle 1 Enable write access to the corresponding XGSWT bit in the same bus cycle 7–0 XGSWT[7:0] Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels. They can only be set and cleared by software. Read: 0 No software trigger pending 1 Software trigger pending if the XGIE bit is set Write: 0 Clear Software Trigger 1 Set Software Trigger
NOTE The XGATE channel IDs that are associated with the eight software triggers are determined on chip integration level. (see Section “Interrupts“ of the Soc Guide) XGATE software triggers work like any peripheral interrupt. They can be used as XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.10 XGATE Semaphore Register (XGSEM)
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE Semaphore Register (Figure 10-12). Refer to section Section 10.4.4, “Semaphores” for details.
Module Base +0x0001A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0
XGSEMM[7:0]
XGSEM[7:0] 0 0 0 0 0
Figure 10-12. XGATE Semaphore Register (XGSEM)
Read: Anytime Write: Anytime (see Section 10.4.4, “Semaphores”)
Table 10-11. XGSEM Field Descriptions
Field Description
15–8 Semaphore Mask — These bits control the write access to the XGSEM bits. XGSEMM[7:0] Read: These bits will always read "0". Write: 0 Disable write access to the XGSEM in the same bus cycle 1 Enable write access to the XGSEM in the same bus cycle 7–0 XGSEM[7:0] Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access. Read: 0 Semaphore is unlocked or locked by the RISC core 1 Semaphore is locked by the S12X_CPU Write: 0 Clear semaphore if it was locked by the S12X_CPU 1 Attempt to lock semaphore by the S12X_CPU
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 10-13) provides access to the RISC core’s condition code register.
Module Base +0x001D
7 6 5 4 3 2 1 0
R W Reset
0 0
0 0
0 0
0 0
XGN 0
XGZ 0
XGV 0
XGC 0
= Unimplemented or Reserved
Figure 10-13. XGATE Condition Code Register (XGCCR)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-12. XGCCR Field Descriptions
Field 3 XGN 2 XGZ 1 XGV 0 XGC Sign Flag — The RISC core’s Sign flag Zero Flag — The RISC core’s Zero flag Overflow Flag — The RISC core’s Overflow flag Carry Flag — The RISC core’s Carry flag Description
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.12 XGATE Program Counter Register (XGPC)
The XGPC register (Figure 10-14) provides access to the RISC core’s program counter.
Module Base +0x0001E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0
XGPC 0 0 0 0 0 0 0 0 0
Figure 10-14. XGATE Program Counter Register (XGPC)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-13. XGPC Field Descriptions
Field 15–0 XGPC[15:0] Description Program Counter — The RISC core’s program counter
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.13 XGATE Register 1 (XGR1)
The XGR1 register (Figure 10-15) provides access to the RISC core’s register 1.
Module Base +0x00022
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR1 0 0 0 0 0 0 0 0
Figure 10-15. XGATE Register 1 (XGR1)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-14. XGR1 Field Descriptions
Field 15–0 XGR1[15:0] Description XGATE Register 1 — The RISC core’s register 1
10.3.1.14 XGATE Register 2 (XGR2)
The XGR2 register (Figure 10-16) provides access to the RISC core’s register 2.
Module Base +0x00024
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR2 0 0 0 0 0 0 0 0
Figure 10-16. XGATE Register 2 (XGR2)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-15. XGR2 Field Descriptions
Field 15–0 XGR2[15:0] Description XGATE Register 2 — The RISC core’s register 2
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.15 XGATE Register 3 (XGR3)
The XGR3 register (Figure 10-17) provides access to the RISC core’s register 3.
Module Base +0x00026
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR3 0 0 0 0 0 0 0 0
Figure 10-17. XGATE Register 3 (XGR3)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-16. XGR3 Field Descriptions
Field 15–0 XGR3[15:0] Description XGATE Register 3 — The RISC core’s register 3
10.3.1.16 XGATE Register 4 (XGR4)
The XGR4 register (Figure 10-18) provides access to the RISC core’s register 4.
Module Base +0x00028
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR4 0 0 0 0 0 0 0 0
Figure 10-18. XGATE Register 4 (XGR4)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-17. XGR4 Field Descriptions
Field 15–0 XGR4[15:0] Description XGATE Register 4 — The RISC core’s register 4
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.17 XGATE Register 5 (XGR5)
The XGR5 register (Figure 10-19) provides access to the RISC core’s register 5.
Module Base +0x0002A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR5 0 0 0 0 0 0 0 0
Figure 10-19. XGATE Register 5 (XGR5)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-18. XGR5 Field Descriptions
Field 15–0 XGR5[15:0] Description XGATE Register 5 — The RISC core’s register 5
10.3.1.18 XGATE Register 6 (XGR6)
The XGR6 register (Figure 10-20) provides access to the RISC core’s register 6.
Module Base +0x0002C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR6 0 0 0 0 0 0 0 0
Figure 10-20. XGATE Register 6 (XGR6)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-19. XGR6 Field Descriptions
Field 15–0 XGR6[15:0] Description XGATE Register 6 — The RISC core’s register 6
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.19 XGATE Register 7 (XGR7)
The XGR7 register (Figure 10-21) provides access to the RISC core’s register 7.
Module Base +0x0002E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W Reset 0 0 0 0 0 0 0 0
XGR7 0 0 0 0 0 0 0 0
Figure 10-21. XGATE Register 7 (XGR7)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00) Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-20. XGR7 Field Descriptions
Field 15–0 XGR7[15:0] Description XGATE Register 7 — The RISC core’s register 7
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Chapter 10 XGATE (S12XGATEV3)
10.4
Functional Description
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 10-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence (thread) that is associated with the requested XGATE channel. Each thread can run on a priority level ranging from 1 to 7. Refer to the S12X_INT Section for information on how to select priority levels for XGATE threads. Low priority threads (interrupt levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE hardware. To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE channel has its own interrupt vector. Refer to the S12X_INT Section for detailed information. The XGATE module also provides a set of hardware semaphores which are necessary to ensure data consistency whenever RAM locations or peripherals are shared with the S12X_CPU. The following sections describe the components of the XGATE module in further detail.
10.4.1
XGATE RISC Core
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit manipulations, and simple arithmetic operations (see Section 10.8, “Instruction Set”). It is able to access the MCU’s internal memories and peripherals without blocking these resources from the S12X_CPU1. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core will be stalled until the resource becomes available again.1 The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC core can perform up to two RAM accesses per S12X_CPU bus cycle. Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU cycle can not be exceeded. The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral modules or by software.
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10.4.2
Programmer’s Model
Register Block
15 15 15 15 15 15 15 15
Program Counter
0 0 0 0 0 0 0 0 15
R7 (Stack Pointer) R6 R5 R4 R3 R2 R1(Data Pointer) R0 = 0
PC
0
Condition Code Register NZVC 3210
Figure 10-22. Programmer’s Model
The programmer’s model of the XGATE RISC core is shown in Figure 10-22. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Registers R1 and R7 have additional functionality. R1 is preloaded with the initial data pointer of the channel’s service request vector (see Figure 10-23). R7 is either preloaded with the content of XGISP74 if the interrupt priority of the current channel is in the range 7 to 4, or it is with preloaded the content of XGISP31 if the interrupt priority of the current channel is in the range 3 to 1. The remaining general purpose registers will be reset to an unspecified value at the beginning of each thread. The 16 bit program counter allows the addressing of a 64 kbyte address space. The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and the carry bit (C). The initial content of the condition code register is undefined.
10.4.3
Memory Map
The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed information. The XGATE vector block assigns a start address and a data pointer to each XGATE channel. Its position in the XGATE memory map can be adjusted through the XGVBR register (see Section 10.3.1.7, “XGATE Vector Base Address Register (XGVBR)”). Figure 10-23 shows the layout of the vector block. Each vector consists of two 16 bit words. The first contains the start address of the service routine. This value will be loaded into the program counter before a service routine is executed. The second word is a pointer to the service routine’s data space. This value will be loaded into register R1 before a service routine is executed.
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XGVBR
+$0000 unused
Code
+$0024 Channel $09 Initial Program Counter Channel $09 Initial Data Pointer +$0028 Channel $0A Initial Program Counter Channel $0A Initial Data Pointer +$002C Channel $0B Initial Program Counter Channel $0B Initial Data Pointer +$0030 Channel $0C Initial Program Counter Channel $0C Initial Data Pointer
Data
Code
+$01E0
Channel $78 Initial Program Counter Channel $78 Initial Data Pointer
Data
Figure 10-23. XGATE Vector Block
10.4.4
Semaphores
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the S12X_CPU and one running on the XGATE RISC core. Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore register (XGSEM, see Section 10.3.1.10, “XGATE Semaphore Register (XGSEM)”). The RISC core does this through its SSEM and CSEM instructions. IFigure 10-24 illustrates the valid state transitions.
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set_xgsem: clr_xgsem: ssem: csem:
1 is written to XGSEM[n] (and 1 is written to XGSEMM[n]) 0 is written to XGSEM[n] (and 1 is written to XGSEMM[n]) Executing SSEM instruction (on semaphore n) Executing CSEM instruction (on semaphore n) clr_xgsem csem
LOCKED BY S12X_CPU
LOCKED BY XGATE
clr_xgsem ssem & set_xgsem
csem ssem
UNLOCKED
ssem & set_xgsem
Figure 10-24. Semaphore State Transitions
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Figure 10-25 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown.
S12X_CPU
......... 1 ⇒ XGSEM[n]
XGATE
......... SSEM
XGSEM[n] 1?
BCC?
critical code sequence
critical code sequence
0 ⇒ XGSEM[n] .........
CSEM .........
Figure 10-25. Algorithm for Locking and Releasing Semaphores
10.4.5
Software Error Detection
Upon detecting an error condition caused by erratic application code, the XGATE module will immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There are three error conditions: • Execution of an illegal opcode • Illegal opcode fetches • Illegal load or store accesses All opcodes which are not listed in section Section 10.8, “Instruction Set” are illegal opcodes. Illegal opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the S12X_MMC Section for a detailed information.
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NOTE When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS instruction, the XGATE prefetches and discards the opcode of the following instruction. The XGATE will perform its software error handling actions (see above) if this opcode fetch is illegal.
10.5
10.5.1
Interrupts
Incoming Interrupt Requests
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide.
10.5.2
Outgoing Interrupt Requests
There are three types of interrupt requests which can be triggered by the XGATE module: 4. Channel interrupts For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector (XGIF, see Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to the S12X_CPU when the XGATE has completed one of its task. 5. Software triggers Software triggers are interrupt flags, which can be set and cleared by software (see Section 10.3.1.9, “XGATE Software Trigger Register (XGSWT)”). They are typically used to trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software. 6. Software error interrupt The software error interrupt signals to the S12X_CPU the detection of an error condition in the XGATE application code (see Section 10.4.5, “Software Error Detection”). This is a non-maskable interrupt. Executing the interrupt service routine will automatically reset the interrupt line. All outgoing XGATE interrupts, except software error interrupts, can be disabled by the XGIE bit in the XGATE module control register (XGMCTL, see Section 10.3.1.1, “XGATE Control Register (XGMCTL)”).
10.6
Debug Mode
The XGATE debug mode is a feature to allow debugging of application code.
10.6.1
Debug Features
In debug mode the RISC core will be halted and the following debug features will be enabled:
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•
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)1 All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue program execution with the modified register values.
1. Only possible if MCU is unsecured
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•
•
Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly. Write accesses to the XGCHID register and the XGCHPL register XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is shown in Table 10-21. Once a thread has been initiated it’s code can be either single stepped or it can be executed by leaving debug mode.
Table 10-21. Initiating and Terminating Threads in Debug Mode
Register Content XGCHID 0 XGCHPL 0 Single Cycle Write Access to... XGCHID 1..127 XGCHPL -1 Set new XGCHID Set XGCHPL to 0x01 Initiate new thread Set new XGCHID Set new XGCHPL Initiate new thread Interrupt current thread Set new XGCHID Set new XGCHPL Initiate new thread Terminate current thread. Resume interrupted thread or become idle if no interrupted thread is pending No action
Action
0
0
1..127
0..7
1..127
0..3
1..127
4..7
0..7 1..127 0..7 0 -1
All other combinations
1
8 bit write access to XGCHID
NOTE Even though zero is not a valid interrupt priority level of the S12X_INT module, a thread of priority level 0 can be initiated in debug mode. The XGATE handles requests of priority level 0 in the same way as it handles requests of priority levels 1 to 3. NOTE All channels 1 to 127 can be initiated by writing to the XGCHID register, even if they are not assigned to any peripheral module. NOTE In Debug Mode the XGATE will ignore all requests from peripheral modules.
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10.6.1.0.1
Entering Debug Mode
Debug mode can be entered in four ways: 1. Setting XGDBG to "1" Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter debug mode upon completion of the current instruction. NOTE After writing to the XGDBG bit the XGATE will not immediately enter debug mode. Depending on the instruction that is executed at this time there may be a delay of several clock cycles. The XGDBG will read "0" until debug mode is entered. 2. Software breakpoints XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A software breakpoint is set by replacing an instruction of the program code with the "BRK" instruction. As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode. Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the "BRK" instruction. The other RISC core registers will hold the result of the previous instruction. To resume program execution, the "BRK" instruction must be replaced by the original instruction before leaving debug mode. 3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion of the current instruction.
10.6.2
Leaving Debug Mode
Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been cleared in debug mode), program execution will resume at the value of XGPC.
10.7
Security
In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug features have been made. These are: • Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device
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• •
Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device Single stepping is not possible on a secured device
10.8
10.8.1
Instruction Set
Addressing Modes
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all operations must have one of the eight general purpose registers R0 … R7 as their source as well their destination. All word accesses must work with a word aligned address, that is A[0] = 0!
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10.8.1.1
Naming Conventions
Destination register, allowed range is R0–R7 Low byte of the destination register, bits [7:0] High byte of the destination register, bits [15:8] Source register, allowed range is R0–R7 Low byte of the source register, bits [7:0] High byte of the source register, bits[15:8] Base register for indexed addressing modes, allowed range is R0–R7 Offset register for indexed addressing modes with register offset, allowed range is R0–R7 Offset register for indexed addressing modes with register offset and post-increment, Allowed range is R0–R7 (R0+ is equivalent to R0) Offset register for indexed addressing modes with register offset and pre-decrement, Allowed range is R0–R7 (–R0 is equivalent to R0)
RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.H RB RI RI+
–RI
NOTE Even though register R1 is intended to be used as a pointer to the data segment, it may be used as a general purpose data register as well. Selecting R0 as destination register will discard the result of the instruction. Only the condition code register will be updated
10.8.1.2
Inherent Addressing Mode (INH)
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE registers. Examples:
BRK RTS
10.8.1.3
Immediate 3-Bit Wide (IMM3)
Operands for immediate mode instructions are included in the instruction stream and are fetched into the instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an immediate addressing mode operand. This address mode is used for semaphore instructions. Examples:
CSEM SSEM #1 #3 ; Unlock semaphore 1 ; Lock Semaphore 3
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10.8.1.4
Immediate 4 Bit Wide (IMM4)
The 4 bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ IMM4 Examples:
LSL LSR R4,#1 R4,#3 ; R4 = R4 > 3; shift register R4 by 3 bits to the right
10.8.1.5
Immediate 8 Bit Wide (IMM8)
The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples:
ADDL SUBL LDH CMPL R1,#1 R2,#2 R3,#3 R4,#4 ; ; ; ; adds an 8 bit value to register R1 subtracts an 8 bit value from register R2 loads an 8 bit immediate into the high byte of Register R3 compares the low byte of register R4 with an immediate value
10.8.1.6
Immediate 16 Bit Wide (IMM16)
The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode. RD = RD ∗ IMM16 Examples:
LDW ADD R4,#$1234 R4,#$5678 ; translated to LDL R4,#$34; LDH R4,#$12 ; translated to ADDL R4,#$78; ADDH R4,#$56
10.8.1.7
Monadic Addressing (MON)
In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)), the target (RD = f()), or both source and target of the operation (RD = f(RD)). Examples:
JAL SIF R1 R2 ; PC = R1, R1 = PC+2 ; Trigger IRQ associated with the channel number in R2.L
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10.8.1.8
Dyadic Addressing (DYA)
In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated. This addressing mode is used only for shift operations with a variable shift value Examples:
LSL LSR R4,R5 R4,R5 ; R4 = R4 > R5
10.8.1.9
Triadic Addressing (TRI)
In this mode the result of an operation between two or three registers is stored into a third one. RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code flags are updated. This addressing mode is used for all arithmetic and logical operations. Examples:
ADC SUB R5,R6,R7 R5,R6,R7 ; R5 = R6 + R7 + Carry ; R5 = R6 - R7
10.8.1.10 Relative Addressing 9-Bit Wide (REL9)
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for conditional branch instructions. Examples:
BCC BEQ REL9 REL9 ; PC = PC + 2 + (REL9 R2;arithmetic shift register R4 right by the amount ; of bits contained in R2[3:0].
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10.8.2.5
Bit Field Operations
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word 7 15 43 W4 O4 5 2 W4=3, O4=2 0 RS2 0 RS1 Bit Field Extract Bit Field Insert 15 3 0 RD
Figure 10-26. Bit Field Addressing
BFEXT R3,R4,R5 ; R5: W4+1 bits with offset O4, will be extracted from R4 into R3
10.8.2.6
Special Instructions for DMA Usage
The XGATE offers a number of additional instructions for flag manipulation, program flow control and debugging: 1. SIF: Set a channel interrupt flag 2. SSEM: Test and set a hardware semaphore 3. CSEM: Clear a hardware semaphore 4. BRK: Software breakpoint 5. NOP: No Operation 6. RTS: Terminate the current thread
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10.8.3
Cycle Notation
Table 10-22 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
Table 10-22. Access Detail Notation V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle r — 8 bit data read: lasts for at least one RISC core cycle R — 16 bit data read: lasts for at least one RISC core cycle w — 8 bit data write: lasts for at least one RISC core cycle W — 16 bit data write: lasts for at least one RISC core cycle A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles f — Free cycle: no read or write, lasts for one RISC core cycles Special Cases PP/P — Branch: PP if branch taken, P if not
10.8.4
Thread Execution
When the RISC core is triggered by an interrupt request (see Figure 10-1) it first executes a vector fetch sequence which performs three bus accesses: 1. A V-cycle to fetch the initial content of the program counter. 2. A V-cycle to fetch the initial content of the data segment pointer (R1). 3. A P-cycle to load the initial opcode. Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If further interrupt requests are pending after a thread has been terminated, a new vector fetch will be performed. Otherwise the RISC core will either resume a previous thread (beginning with a P-cycle to refetch the interrupted opcode) or it will become idle until a new interrupt request is received. A thread can only be interrupted by an interrupt request of higher priority.
10.8.5
Instruction Glossary
This section describes the XGATE instruction set in alphabetical order.
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ADC
Operation RS1 + RS2 + C ⇒ RD
Add with Carry
ADC
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions. Example:
ADD ADC BCC R6,R2,R2 R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2 ; conditional branch on 32 bit addition
CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000 and Z was set before this operation; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Code and CPU Cycles
Source Form ADC RD, RS1, RS2 Address Mode TRI 0 0 0 1 1 Machine Code RD RS1 RS2 1 1 Cycles P
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ADD
Operation
Add without Carry
ADD
RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #IMM16[15:8]) Performs a 16 bit addition and stores the result in the destination register RD.
NOTE When using immediate addressing mode (ADD RD, #IMM16), the V-flag and the C-Flag of the first instruction (ADDL RD, #IMM16[7:0]) are not considered by the second instruction (ADDH RD, #IMM16[15:8]). ⇒ Don’t rely on the V-Flag if RD + IMM16[7:0] ≥ 215. ⇒ Don’t rely on the C-Flag if RD + IMM16[7:0] ≥ 216.
CCR Effects
N ∆ N: Z: V: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations. Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Refer to ADDH instruction for #IMM16 operations.
C:
Code and CPU Cycles
Source Form ADD RD, RS1, RS2 ADD RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 1 0 Cycles P P P
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ADDH
Operation RD + IMM8:$00 ⇒ RD
Add Immediate 8 bit Constant (High Byte)
ADDH
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition. Example:
ADDL ADDH R2,#LOWBYTE R2,#HIGHBYTE ; R2 = R2 + 16 bit immediate
CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new
Code and CPU Cycles
Source Form ADDH RD, #IMM8 Address Mode IMM8 1 1 1 0 1 Machine Code RD IMM8 Cycles P
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ADDL
Operation RD + $00:IMM8 ⇒ RD
Add Immediate 8 bit Constant (Low Byte)
ADDL
Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise. RD[15]old & RD[15]new Set if there is a carry from the bit 15 of the result; cleared otherwise. RD[15]old & RD[15]new
Code and CPU Cycles
Source Form ADDL RD, #IMM8 Address Mode IMM8 1 1 1 0 0 Machine Code RD IMM8 Cycles P
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AND
Operation
Logical AND
AND
RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
NOTE When using immediate addressing mode (AND RD, #IMM16), the Z-flag of the first instruction (ANDL RD, #IMM16[7:0]) is not considered by the second instruction (ANDH RD, #IMM16[15:8]). ⇒ Don’t rely on the Z-Flag.
CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Refer to ANDH instruction for #IMM16 operations. 0; cleared. Not affected.
Code and CPU Cycles
Source Form AND RD, RS1, RS2 AND RD, #IMM16 Address Mode TRI IMM8 IMM8 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Machine Code RD RD RD RS1 RS2 IMM16[7:0] IMM16[15:8] 0 0 Cycles P P P
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ANDH
Operation RD.H & IMM8 ⇒ RD.H
Logical AND Immediate 8 bit Constant (High Byte)
ANDH
Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form ANDH RD, #IMM8 Address Mode IMM8 1 0 0 0 1 Machine Code RD IMM8 Cycles P
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ANDL
Operation RD.L & IMM8 ⇒ RD.L
Logical AND Immediate 8 bit Constant (Low Byte)
ANDL
Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form ANDL RD, #IMM8 Address Mode IMM8 1 0 0 0 0 Machine Code RD IMM8 Cycles P
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ASR
Operation
b15
Arithmetic Shift Right
ASR
C
n
RD
n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is equal to 0. In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS is greater than 15. CCR Effects
N ∆ N: Z: V: C: Z ∆ V ∆ C ∆
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise. RD[15]old ^ RD[15]new Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form ASR RD, #IMM4 ASR RD, RS Address Mode IMM4 DYA 0 0 0 0 0 0 0 0 1 1 Machine Code RD RD IMM4 RS 1 1 0 0 0 0 0 1 1 Cycles P P
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BCC
Operation
Branch if Carry Cleared (Same as BHS)
BCC
If C = 0, then PC + $0002 + (REL9 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits.
15 7 W4 15 3 4 3 O4 0 RS1 Inverted Bit Field Insert 15 5 2 0 RD 0 RS2
W4=3, O4=2
CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form BFINSI RD, RS1, RS2 Address Mode TRI 0 1 1 1 0 Machine Code RD RS1 RS2 1 1 Cycles P
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BFINSX
Operation
Bit Field Insert and XNOR
BFINSX
!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back to RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits.
15 7 W4 15 3 4 3 O4 0 RS1 Bit Field Insert XNOR 15 5 2 0 RD 0 RS2
W4=3, O4=2
CCR Effects
N ∆ N: Z: V: C: Z ∆ V 0 C —
Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
Code and CPU Cycles
Source Form BFINSX RD, RS1, RS2 Address Mode TRI 0 1 1 1 1 Machine Code RD RS1 RS2 1 1 Cycles P
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BGE
Operation Branch if RS1 ≥ RS2:
SUB BGE
Branch if Greater than or Equal to Zero
BGE
If N ^ V = 0, then PC + $0002 + (REL9 RS2:
SUB BGT R0,RS1,RS2 REL9
Branch if Greater than Zero
BGT
If Z | (N ^ V) = 0, then PC + $0002 + (REL9 RS2:
SUB BHI R0,RS1,RS2 REL9
Branch if Higher
BHI
If C | Z = 0, then PC + $0002 + (REL9 1) ;########################################### ;# INITIALIZE XGATE # ;########################################### MOVW #XGMCTL_CLEAR, XGMCTL ;clear all XGMCTL bits TST BNE LDX LDD STD STD STD STD STD STD STD STD XGCHID ;wait until current thread is finished INIT_XGATE_BUSY_LOOP #XGIF #$FFFF 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ ;clear all channel interrupt flags
INIT_SCI
INIT_INT
INIT_XGATE INIT_XGATE_BUSY_LOOP
CLR XGISPSEL ;set vector base register MOVW #XGATE_VECTORS_XG, XGVBR MOVW #$FF00, XGSWT ;clear all software triggers ;########################################### ;# INITIALIZE XGATE VECTOR TABLE # ;########################################### LDAA #128 ;build XGATE vector table LDY #XGATE_VECTORS MOVW #XGATE_DUMMY_ISR_XG, 4,Y+ DBNE A, INIT_XGATE_VECTAB_LOOP MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC) MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2 ;########################################### ;# COPY XGATE CODE # ;########################################### LDX #XGATE_DATA_FLASH MOVW 2,X+, 2,Y+
INIT_XGATE_VECTAB_LOOP
COPY_XGATE_CODE COPY_XGATE_CODE_LOOP
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MOVW MOVW MOVW CPX BLS
2,X+, 2,Y+ 2,X+, 2,Y+ 2,X+, 2,Y+ #XGATE_CODE_FLASH_END COPY_XGATE_CODE_LOOP
START_XGATE
;########################################### ;# START XGATE # ;########################################### MOVW #XGMCTL_ENABLE, XGMCTL ;enable XGATE BRA * ;########################################### ;# DUMMY INTERRUPT SERVICE ROUTINE # ;########################################### RTI CPU XGATE ;########################################### ;# XGATE DATA # ;########################################### ALIGN 1 EQU * EQU *-XGATE_DATA_FLASH DW SCI_REGS ;pointer to SCI register space EQU *-XGATE_DATA_FLASH DB XGATE_DATA_MSG ;string pointer EQU *-XGATE_DATA_FLASH FCC "Hello World! ;ASCII string DB $0D ;CR ;########################################### ;# XGATE CODE # ;########################################### ALIGN 1 LDW R2,(R1,#XGATE_DATA_SCI) ;SCI -> R2 LDB R3,(R1,#XGATE_DATA_IDX) ;msg -> R3 LDB R4,(R1,R3+) ;curr. char -> R4 STB R3,(R1,#XGATE_DATA_IDX) ;R3 -> idx LDB R0,(R2,#(SCISR1-SCI_REGS)) ;initiate SCI transmit STB R4,(R2,#(SCIDRL-SCI_REGS)) ;initiate SCI transmit CMPL R4,#$0D BEQ XGATE_CODE_DONE RTS LDL R4,#$00 ;disable SCI interrupts STB R4,(R2,#(SCICR2-SCI_REGS)) LDL R3,#XGATE_DATA_MSG;reset R3 STB R3,(R1,#XGATE_DATA_IDX) RTS EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
DUMMY_ISR
XGATE_DATA_FLASH XGATE_DATA_SCI XGATE_DATA_IDX XGATE_DATA_MSG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END XGATE_DUMMY_ISR_XG
10.9.3
Stack Support
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined: One for threads of priority level 7 to 4 (refer to Section 10.3.1.5, “XGATE Initial Stack Pointer for
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Interrupt Priorities 7 to 4 (XGISP74)”) and one for threads of priority level 3 to 1 (refer to Section 10.3.1.6, “XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)”).
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description Revision History
Version Revision Effective Number Date Date
V01.00 V01.01 26 Oct. 05 26 Oct. 05 2 Nov. 06 2 Nov. 06
Author
Initial release
Description of Changes
Tabe “Examples of IPLL Divider settings”: corrected $32 to $31
11.1
Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1
Features
The main features of this block are: • Phase Locked Loop (IPLL) frequency multiplier with internal filter — Reference divider — Post divider — Configurable internal filter (no external pin) — Optional frequency modulation for defined jitter and reduced emission — Automatic frequency lock detector — Interrupt request on entry or exit from locked condition — Self Clock Mode in absence of reference clock • System Clock Generator — Clock Quality Check — User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate program execution — Clock switch for either Oscillator or PLL based system clocks
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• •
•
Computer Operating Properly (COP) watchdog timer with time-out clear window. System Reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset Real-Time Interrupt (RTI)
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11.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12XECRG. • Run Mode All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a non zero value. • Wait Mode In this mode the IPLL can be disabled automatically depending on the PLLWAI bit. • Stop Mode Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode (PSTP = 0) and Pseudo Stop Mode (PSTP = 1). — Full Stop Mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. — Pseudo Stop Mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set the COP and RTI will continue to run, else they remain frozen. • Self Clock Mode Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality check. Self Clock Mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions.
11.1.3
Block Diagram
Figure 11-1 shows a block diagram of the S12XECRG.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
Illegal Address Reset S12X_MMC Power on Reset Voltage Regulator Low Voltage Reset
ICRG RESET Clock Monitor CM Fail COP Timeout Reset Generator System Reset
XCLKS EXTAL
OSCCLK Oscillator XTAL
Clock Quality Checker
Bus Clock Core Clock
COP
RTI Oscillator Clock
Registers PLLCLK VDDPLL VSSPLL IPLL Clock and Reset Control Real Time Interrupt PLL Lock Interrupt Self Clock Mode Interrupt
Figure 11-1. Block diagram of S12XECRG
11.2
Signal Description
This section lists and describes the signals that connect off chip.
11.2.1
VDDPLL, VSSPLL
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL and VSSPLL must be connected to properly.
11.2.2
RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered.
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11.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1
Module Memory Map
Figure 11-2 gives an overview on all S12XECRG registers.
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B Name SYNR REFDV POSTDIV CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP2 CTCTL2 ARMCOP R W R W R W R W R W R W R W R W R W R W R W R W 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 RTIF RTIE PLLSEL CME RTDEC WCOP 0 PORF 0 LVRF 0 XCLKS LOCKIF LOCKIE 0 LOCK 0 Bit 7 6 5 4 3 2 1 Bit 0
VCOFRQ[1:0] REFFRQ[1:0] 0 0 0
SYNDIV[5:0] REFDIV[5:0] POSTDIV[4:0] ILAF 0 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 SCM 0
PSTP PLLON RTR6 RSBCK 0
PLLWAI FSTWKP RTR3 0 0
COPWAI SCME RTR0 CR0 0
FM1 RTR5 0 WRTMASK 0
FM0 RTR4 0 0
PRE RTR2 CR2 0
2. FORBYP and CTCTL are intended for factory test purposes only. = Unimplemented or Reserved
Figure 11-2. CRG Register Summary
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
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11.3.2
Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
11.3.2.1
S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Module Base + 0x0000
7 6 5 4 3 2 1 0
R VCOFRQ[1:0] W Reset 0 0 0 0 0 0 0 0 SYNDIV[5:0]
Figure 11-3. S12XECRG Synthesizer Register (SYNR)
Read: Anytime Write: Anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit.
( SYNDIV + 1 ) f VCO = 2 × f OSC × -----------------------------------( REFDIV + 1 ) f VCO f PLL = ----------------------------------2 × POSTDIV f PLL f BUS = -----------2
NOTE fVCO must be within the specified VCO frequency lock range. F.BUS (Bus Clock) must not exceed the specified maximum. If POSTDIV = $00 then fPLL is same as fVCO (divide by one). The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown in Table 11-1. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL (no locking and/or insufficient stability).
Table 11-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges 32MHz
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