SPC5606CEMLU

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5606S Rev. 1, 10/2008 MPC5606S LQFP–144 MAPBGA–225 QFN12 20 15 mm x 15 mm mm x 20 mm ##_mm_x_##mm MPC560xS Microcontroller Data Sheet LQFP–176 24 mm x 24 mm SOT-343R ##_mm_x_##mm TBD PKG-TBD ## mm x ## mm 32-bit MCU for cluster applications with stepper motor, TFT graphic controller and LCD driver The MPC5606S family of devices is designed to enable the development of automotive instrument cluster applications by providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip color TFT display controller. MPC5606S devices incorporate a cost-efficient host processor core compliant with the Power Architecture™ embedded category. The processor is 100% user-mode compatible with the original PowerPC user instruction set architecture (UISA) and capitalizes on the available development infrastructure of current Power ArchitectureTM devices with full support from available software drivers, operating systems and configuration code to assist with users' implementations. Offering high performance processing at speeds up to 64 MHz, the MPC5606S family is optimized for low power consumption and supports a range of on-chip SRAM and internal flash memories. The 1 MB flash version (MPC5606S) features 160 KB of on-chip graphics SRAM. Refer to Table 1 for specific memory and feature sets of the product family members. This document describes the features of the MPC5606S family of microcontrollers and highlights important electrical and physical characteristics of the devices. For functional characteristics, refer to the MPC5606S Microcontroller Reference Manual. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary—Subject to Change Without Notice Table of Contents 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 MPC5606S Features. . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 MPC5606S Series Blocks . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.2 Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pinout and Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . .9 2.1 144 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .10 2.2 176 LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . .11 2.3 208 MAPBGA Package Pinout . . . . . . . . . . . . . . . . . . .11 2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.4.1 Pad Configuration during Reset Phases . . . . . .13 2.4.2 Voltage Supply Pins. . . . . . . . . . . . . . . . . . . . . .13 2.4.3 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4.4 System Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4.5 Nexus Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.6 Functional Ports A, B, C, D, E, F, G, H, I, J, K . .18 2.4.7 Signal Details. . . . . . . . . . . . . . . . . . . . . . . . . . .36 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .39 3.1.1 Recommended Operating Conditions . . . . . . . .41 3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .44 3.2.1 General Notes for Specifications at Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .45 3.3 EMI (Electromagnetic Interference) Characteristics . . .47 3.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.4.1 Voltage Regulator Electrical Characteristics . . .47 3.4.2 Voltage monitor electrical characteristics. . . . . .48 3.4.3 Low voltage domain power consumption. . . . . .49 3.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .50 3.6 I/O Pad Electrical Characteristics . . . . . . . . . . . . . . . . .50 3.6.1 I/O Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6.2 I/O Input DC Characteristics . . . . . . . . . . . . . . 50 3.6.3 I/O Output DC Characteristics . . . . . . . . . . . . . 51 3.6.4 I/O Pad Current Specification. . . . . . . . . . . . . . 55 3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . 57 3.8 Main Oscillator Electrical Characteristics . . . . . . . . . . 59 3.9 Low Power Oscillator Electrical Characteristics. . . . . . 61 3.10 FMPLL Electrical Characteristics. . . . . . . . . . . . . . . . . 62 3.11 Main RC Oscillator Electrical Characteristics . . . . . . . 63 3.12 Low Power RC Oscillator Electrical Characteristics . . 64 3.13 Flash Memory Electrical Characteristics . . . . . . . . . . . 64 3.14 Analog to Digital Converter (ADC) Electrical Characteristics 65 3.14.1 Input Impedance and ADC Accuracy . . . . . . . . 66 3.14.2 ADC Electrical Characteristics . . . . . . . . . . . . . 70 3.15 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.15.1 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 72 3.16 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.16.1 IEEE 1149.1 Interface Timing . . . . . . . . . . . . . 74 3.16.2 Nexus Debug Interface. . . . . . . . . . . . . . . . . . . 77 3.16.3 Interface to TFT LCD Panels . . . . . . . . . . . . . . 78 3.16.4 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing . . . . . . . . . . . . . . . . . . . 81 3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing 82 3.16.6 FlexCAN Timing . . . . . . . . . . . . . . . . . . . . . . . . 82 3.16.7 Deserial Serial Peripheral Interface (DSPI) . . . 83 3.16.8 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.16.9 Mechanical Outline Drawings. . . . . . . . . . . . . . 89 3.17 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.18 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2 3 4 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview 1 1.1 .. Overview Device Comparison Table 1. MPC5606S Family Feature CPU Execution Speed Flash (ECC) EEPROM Emulation Block (ECC) RAM (ECC) Graphics RAM MPU eDMA Display Control Unit Parallel Data Interface Stepper Motor Controller Stepper Motor Stall Detect Sound Generation LCD Segment Driver 32 kHz External Crystal Oscillator Real Time Counter and Autonomous Periodic Interrupt Periodic Interrupt Timer System Watchdog Timer System Timer Module Timed I/O2 Yes Yes 64 × 6 No No 24 KB No 256 KB MPC5602S MPC5604S e200z0h Static - 64 MHz 512 KB 4 × 16 KB 48 KB No 12 entry 16 channels No No 6 motors Yes Yes 64 × 6 Yes Yes Yes Using eMIOS 40 × 4, 38 × 61 Yes Yes 48 KB 160 KB 1 MB MPC5606S The following sections provide high-level descriptions of the features found on the MPC5606S. 4 ch, 32-bit Yes 4 ch, 32-bit 8 ch, 16-bit IC/OC 16 ch, 16-bit OPWM/IC/OC ADC3 CAN (64 Mailboxes) CAN Sampler SCI SPI QuadSPI Serial Flash Interface 2 × DSPI No 1 × FlexCAN 16 channels, 10-bit 2 × FlexCAN Yes 2 × LINFlex 2 × DSPI No 34 × DSPI Yes 2 × FlexCAN MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 3 Overview Table 1. MPC5606S Family (continued) Feature I2C GPIO Debug Package MPC5602S 2 105 Nexus 1 144 LQFP MPC5604S 2 105 Nexus 1 144 LQFP MPC5606S 4 105 / 132 Nexus 2+5 144 LQFP6 176 LQFP 208 MAPBGA7 1 2 3 4 5 6 7 Configuration is software-programmable IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation Support for external multiplexer enabling up to 23 channels QuadSPI serial Flash controller can be optionally used as a third DSPI Nexus2+ available on 176 LQFP as alternate pin function and on 208 MAPBGA Not all features are available simultaneously in 144 LQFP package option The 208-pin package is not a production package; it is available in limited quantities for tool development only. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 4 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview 1.2 • MPC5606S Features Single issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z0h) — Compatible with classic PowerPC instruction set — Includes variable length encoding (VLE) instruction set for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional Book E compliant code On-chip ECC flash memory with flash controller — Up to 1 MB primary flash—two 512 KB modules with prefetch buffer and 128-bit data access port — 64 KB data flash—separate 4×16 KB flash block for EEPROM Emulation with prefetch buffer and 128-bit data access port Up to 48 KB on-chip ECC SRAM with SRAM controller Up to 160 KB on-chip non-ECC graphics SRAM with SRAM controller Memory protection unit (MPU) with up to 12 region descriptors and 32-byte region granularity to provide basic memory access permission Interrupt controller (INTC) with up to 127 peripheral interrupt sources and eight software interrupts Two frequency-modulated phase-locked loops (FMPLLs) — Primary FMPLL provides a 64 MHz system clock — Auxiliary FMPLL is available for use as an alternate, modulated or non-modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus masters (AMBA 2.0 v6 AHB) 16-channel enhanced direct memory access controller (eDMA) with multiple transfer request sources using a DMA channel multiplexer Boot assist module (BAM) for embedded boot code supports boot options including download of code via a serial link (CAN or SPI) Display control unit to drive TFT LCD displays. It includes processing of up to four planes that can be blended together and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to drastically minimize graphic memory requirements and provide fast animations. Programmable display resolutions are available up to WVGA. Parallel Data Interface for digital video input The LCD segment driver module has two software programmable configurations: — Up to 40 front plane drivers and 4 backplane drivers — Up to 38 frontplane drivers and 6 backplane drivers Stepper Motor Controller module with high-current drivers for up to six instrument cluster gauges driven in full dual H-Bridge configuration including full diagnostics for short circuit detection Stepper motor return-to-zero and stall detection module Sound generation and playback utilizing PWM channels and eDMA; supports monotonic and polyphonic sound 24 eMIOs channels providing up to 16 PWM and 24 input capture / output compare channels 10-bit analog-to-digital converter (ADC) with a maximum conversion time of 1μs — 16 internal channels — Extendable to eight multiplexed external channels Up to three DSPI (Deserial Serial Peripheral Interface) modules for full-duplex, synchronous, communications with external devices QuadSPI serial flash memory controller supporting single, dual and quad modes of operation to interface to external serial flash memory or optionally can be configured to function as another DSPI module (MPC5606S only) Two Local Interconnect Network (LIN) controller modules capable of autonomous message handling (master), autonomous header handling (slave mode), and UART support. Compliant with LIN protocol rev 2.1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 • • • • • • • • • • • • • • • • • • • • Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 Overview • • • • • • • • • • • • • • • Two full CAN 2.0B controllers with 64 configurable buffers each; the bit rate can be programmed up to 1 Mb/s Up to four Inter-integrated circuit (I2C) internal bus controllers with master/slave bus interface Up to 132 configurable general purpose pins supporting input and output operations Real Time Counter (RTC). Clock sources are: — Internal 128 kHz or 16 MHz RC oscillator supporting autonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds — External 32 kHz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour — External 4 - 16 MHz oscillator System Timers: — 4-channel 32-bit System Timer Module (STM)—included in processor platform — 4-channel 32-bit Periodic Interrupt Timer (PIT) module — System watchdog timer System Integration Unit (SIU) module to manage resets, external interrupts, GPIO and pad control System Status and Configuration Module (SSCM) to provide information for identification of the device, last boot mode, or debug status and provides an entry point for the censorship password mechanism Clock Generation Module (CGM) to generate system clock sources and provide a unified register interface, enabling access to all clock sources Clock Monitor Unit (CMU) to monitor the integrity of the main crystal oscillator and the PLL and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock Mode Entry Module (MEM) to control the device power mode, i.e., RUN, HALT, STOP, or STANDBY, control mode transition sequences, and manage the power control, voltage regulator, clock generation and clock management modules Reset Generation Module (RGM) to manage reset assertion and release to the device at initial power-up Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator controller for regulating the 3.3 or 5 V supply voltage down to 1.2 V for core logic (requires external ballast transistor) The MPC5606S microcontrollers are offered in the following packages:1 — 144 LQFP, 0.5 mm pitch, 20 mm × 20 mm outline — 176 LQFP, 0.5 mm pitch, 24 mm × 24 mm outline — 208 MAPBGA, 1.0 mm pitch, 17 mm × 17 mm outline 1.3 1.3.1 MPC5606S Series Blocks Block Diagram Figure 1 shows a top-level block diagram of the MPC5606S series. 1. See the device comparison table or orderable parts summary for package offerings for each device in the family. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 6 Preliminary—Subject to Change Without Notice Freescale Semiconductor Overview NMI Nexus Port JTAG Port SRAM Nexus Port Controller Test Controller JTAG FLASH Video SRAM SRAM FLASH Controller Controller Instructions SRAM Controller IRC 16 MHz NMI XTAL/ EXTAL XTAL32/ EXTAL32 Nexus 2+ Voltage Regulator DMA External Interrupts from Peripheral Blocks XOSC 4-16 MHz XOSC 32 kHz 2× FMPLL 4 x 4 32-bit Crossbar Switch IRC 128 kHz Data MPU (Memory Protection Unit) SIU Clock Monitor Unit (CMU) e200z0h Interrupt Controller (INTC) DCU QuadSPI Data and Clock RGB TFT Output Clock Generation Module Parallel Data Interface (PDI) speaker/ buzzer STM Sound Generation 4×PIT SSCM Mode Entry Module Power Control Unit RTC/ API SWT BAM Reset Generation Module 40 × 4 LCD LCD FP and BP signals Peripheral Bridge SIU External Interrupts Reset Control External Interrupt Request IMUX GPIO & Pad Control 16 ch. 10-bit ADC Six Gauge Drivers Stepper Stall Detect (SSD) with 2x eMIOS 16 + 8 ch. 2× LINFlex 2× DSPI 4 × I2C 2× FlexCAN I/O ... ... ... ... ... ... Figure 1. MPC5606S Series Block Diagram 1.3.2 Block Summary Table 2 summarizes the functions of all blocks present in the MPC5606S series microcontrollers. Please note that the presence and number of blocks varies by device and package. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 7 Overview Table 2. MPC5606S Series Block Summary Block 16-channel 2nd-generation Direct Memory Access (eDMA) AHB crossbar switch “lite” (XBAR-Lite) Analog-to-digital converter (ADC) Boot assist module (BAM) Clock generation module (CGM) Clock monitor unit (CMU) Display control unit (DCU) Function Second-generation platform module capable of performing complex data transfers with minimal intervention from a host processor via “n” programmable channels Internal busmaster 16-channel, 10-bit analog to digital converter A block of read-only memory containing VLE code which is executed according to the boot mode of the device Provides logic and control required for the generation of system and peripheral clocks Monitors clock source (internal and external) integrity Generates all signals required to drive a TFT LCD display, allowing blending of data of up to 16 layers; can also display digital video/graphics in the background plane Provides a synchronous serial interface for communication with external devices Provides a synchronous serial bus for communication with external serial flash memory and is optionally configurable as a third DSPI module Provides the functionality to generate or measure events Provides non-volatile storage for program code, constants and variables Supports the standard CAN communications protocol Two FMPLLs generate high-speed system clocks and support programmable frequency modulation A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Provides priority-based preemptive scheduling of interrupt requests Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode Provides 40 × 4 (frontplane drivers × backplane drivers) or 6 × 38 driver configuration for driving LCD segments Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Provides hardware access control for all memory references generated in a device Provides miscellaneous control functions including program-visible information about the platform configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and generic access error information for the processor core Deserial serial peripheral interface (DSPI) QuadSPI (QSPI) Enhanced modular input output system (eMIOS) Flash memory FlexCAN (controller area network) FMPLL (frequency-modulated phase-locked loop) Inter-integrated circuit (I2C™) bus Interrupt controller (INTC) JTAG controller LCD driver module LINflex controller Memory protection unit (MPU) Error Correction Status Module (ECSM) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 8 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinout and Signal Descriptions Table 2. MPC5606S Series Block Summary (continued) Block Mode entry module (MEM) Function Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Produces periodic interrupts and triggers Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Provides storage for program code, constants, and variables Centralizes reset sources and manages the device reset sequence of the device A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a pre-defined interval independent of the mode of operation (run mode or low-power mode) Provides monotonic and polyphonic sound generation capability A PWM motor controller suitable for driving instruments in a cluster configuration or any other loads requiring a PWM signal The SSD module connects to one stepper (SM) motor with 2 coils and is used to monitor the movement of the SM to detect that the attached gauge pointer has reached the stall position of the scale Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Nexus development interface (NDI) level Peripheral interrupt timer (PIT) Power control unit (PCU) Static random-access memory (SRAM) Reset generation module (RGM) Real time counter (RTC) Sound generation logic (SGL) Stepper motor controller (SMC) Stepper stall detect (SDD) System integration unit (SIU) System status configuration module (SSCM) Provides system configuration and status data, e.g., memory size and status, device mode and security status, DMA status, etc., device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer (STM) System watchdog timer (SWT) Test control unit (TCU) Provides a set of output compare events to support AutoSAR and operating system tasks Provides protection from runaway code An extension of the JTAG controller module, the TCU provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode 2 Pinout and Signal Descriptions MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 9 Pinout and Signal Descriptions 2.1 144 LQFP Package Pinout WARNING Any pins labeled “NC” must not be connected to any external circuit. PA9/DCU_G1/eMIOSB18/SDA_C/FP14 PA8/DCU_G0/eMIOSB23/SCL_C/FP15 PA7/DCU_R7/eMIOSA16/FP16 PA6/DCU_R6/eMIOSA15/FP17 PA5/DCU_R5/eMIOSA17/FP18 PA4/DCU_R4/eMIOSA18/FP19 PA3/DCU_R3/eMIOSA19/sscm7/FP20 PA2/DCU_R2/eMIOSA20/sscm6/FP21 PA1/DCU_R1/eMIOSA21/sscm5/FP22 PA0/DCU_R0/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/SCK_C/FP24 PF14/SOUT_C/CNTX_B/sscm4/FP25 PF13/SIN_C/CNRX_B/sscm3/FP26 PF12/eMIOSB16/PCS_C2/sscm2/FP27 PF11/eMIOSB23/PCS_C1/sscm1/FP28 PF10/eMIOSA16/PCS_C0/sscm0/FP29 PG12/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/SCL_B/PCS_B0/TXD_B/FP31 PF8/SDA_B/PCS_B1/RXD_B/FP32 PF7/SCL_A/PCS_B2/FP33 PF6/SDA_A/FP34 VSS12 VDD12 PF5/eMIOSA9/DCU_TAG/FP35 PF4/eMIOSA10/PDI7/FP36 PF3/eMIOSA11/PDI6/FP37 PF1/eMIOSA12/PDI5/eMIOSA21/FP38 PF0/eMIOSA13/PDI4/eMIOSA22/FP39 PB2/TXD_A PB3/RXD_A VSSE_E VDDE_E FP13/eMIOSB20/DCU_G2/PA10 FP12/eMIOSA13/DCU_G3/PA11 FP11/eMIOSA12/DCU_G4/PA12 FP10/eMIOSA11/DCU_G5/PA13 FP9/eMIOSA10/DCU_G6/PA14 FP8/eMIOSA9/DCU_G7/PA15 VDDE_A VSSE_A FP7/SOUND/SCL_D/DCU_B0/PG0 FP6/SDA_D/DCU_B1/PG1 FP5/eMIOSB19/DCU_B2/PG2 FP4/eMIOSB21/DCU_B3/PG3 FP3/eMIOSB17/DCU_B4/PG4 FP2/eMIOSA8/DCU_B5/PG5 FP1/DCU_B6/PG6 FP0/DCU_B7/PG7 BP0/DCU_VSYNC/PG8 BP1/DCU_HSYNC/PG9 BP2/DCU_DE/PG10 BP3/DCU_PCLK/PG11 VLCD/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL NC TDI/PH1 TDO/PH2 TMS/PH3 TCK/PH0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 2 shows the pinout for the 144-pin LQFP package. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144-Pin LQFP PB11/CNTX_B/PDI3/eMIOSA16 PB10/CNRX_B/PDI2/eMIOSA23 PB0/CNTX_A/PDI1 PB1/CNRX_A/PDI0 VSS12 VDD12 PE7/M5C1P/SSD5_3/eMIOSA8 PE6/M5C1M/SSD5_2/eMIOSA9 PE5/M5C0P/SSD5_1/eMIOSA10 PE4/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/M4C1P/SSD4_3/eMIOSA12 PE2/M4C1M/SSD4_2/eMIOSA13 PE1/M4C0P/SSD4_1/eMIOSA14 PE0/M4C0M/SSD4_0/eMIOSA15 PD15/M3C1P/SSD3_3 PD14/M3C1M/SSD3_2 PD13/M3C0P/SSD3_1 PD12/M3C0M/SSD3_0 VSSMB VDDMB PD11/M2C1P/SSD2_3 PD10/M2C1M/SSD2_2 PD9/M2C0P/SSD2_1 PD8/M2C0M/SSD2_0 PD7/M1C1P/SSD1_3/eMIOSB16 PD6/M1C1M/SSD1_2/eMIOSB17 PD5/M1C0P/SSD1_1/eMIOSB18 PD4/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/M0C1P/SSD0_3/eMIOSB20 PD2/M0C1M/SSD0_2/eMIOSB21 PD1/M0C0P/SSD0_1/eMIOSB22 PD0/M0C0M/SSD0_0/eMIOSB23 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 10 Preliminary—Subject to Change Without Notice Freescale Semiconductor NMI/PF2 VDDE_B VSSE_B PCS_A2/eMIOSB19/RXD_B/PB12 PCS_A1/eMIOSB18/TXD_B/PB13 VDD12 VSS12 eMIOSB20/SCK_A/PB9 eMIOSB21/SOUT_A/PB8 eMIOSB22/SIN_A/PB7 CLKOUT/eMIOSB16/PCS_A0/PH4 MA0/SCK_B/PB4 FABM/MA1/SOUT_B/PB5 ABS[0]/MA2/SIN_B/PB6 VDD12 VSS12 VDDA VSSA XTAL32/AN15/PC15 EXTAL32/AN14/PC14 PCS_B0/MA2/AN13/PC13 PCS_B1/MA1/AN12/PC12 PCS_B2/MA0/AN11/PC11 SOUND/AN10(mux)/PC10 AN9/PC9 AN8/PC8 VDDE_C VSSE_C AN7/PC7 AN6/PC6 AN5/PC5 AN4/PC4 AN3/PC3 AN2/PC2 AN1/PC1 AN0/PC0 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Figure 2. 144-pin LQFPPinout Pinout and Signal Descriptions 2.2 176 LQFP Package Pinout WARNING Any pins labeled “NC” must not be connected to any external circuit. PA9/DCU_G1/eMIOSB18/SDA_C/FP14 PA8/DCU_G0/eMIOSB23/SCL_C/FP15 PA7/DCU_R7/eMIOSA16/FP16 PA6/DCU_R6/eMIOSA15/FP17 PA5/DCU_R5/eMIOSA17/FP18 VSSE_A VDDE_A PA4/DCU_R4/eMIOSA18/FP19 PA3/DCU_R3/eMIOSA19/sscm7/FP20 PA2/DCU_R2/eMIOSA20/sscm6/FP21 PA1/DCU_R1/eMIOSA21/sscm5/FP22 PA0/DCU_R0/eMIOSA22/SOUND/FP23 VSS12 VDD12 PF15/SCK_C/FP24 PF14/SOUT_C/CNTX_B/sscm4/FP25 PF13/SIN_C/CNRX_B/sscm3/FP26 PF12/eMIOSB16/PCS_C2/sscm2/FP27 PF11/eMIOSB23/PCS_C1/sscm1/FP28 PF10/eMIOSA16/PCS_C0/sscm0/FP29 PG12/eMIOSA23/SOUND/eMIOSA8/FP30 VSSE_A VDDE_A PF9/SCL_B/PCS_B0/TXD_B/FP31 PF8/SDA_B/PCS_B1/RXD_B/FP32 PF7/SCL_A/PCS_B2/FP33 PF6/SDA_A/FP34 VSS12 VDD12 PF5/eMIOSA9/DCU_TAG/FP35 PF4/eMIOSA10/PDI7/FP36 PF3/eMIOSA11/PDI6/FP37 PF1/eMIOSA12/PDI5/eMIOSA21/FP38 PF0/eMIOSA13/PDI4/eMIOSA22/FP39 PK1/PDI13/eMIOSA17 PK0/PDI12/eMIOSA18/DCU_TAG PB2/TXD_A PB3/RXD_A PJ15/PDI11/eMIOSA19 PJ14/PDI10/eMIOSA20 PJ13/PDI9/eMIOSB20 PJ12/PDI8/eMIOSB17 VSSE_E VDDE_E FP13/eMIOSB20/DCU_G2/PA10 FP12/eMIOSA13/DCU_G3/PA11 FP11/eMIOSA12/DCU_G4/PA12 FP10/eMIOSA11/DCU_G5/PA13 FP9/eMIOSA10/DCU_G6/PA14 FP8/eMIOSA9/DCU_G7/PA15 VDDE_A VSSE_A FP7/SOUND/SCL_D/DCU_B0/PG0 FP6/SDA_D/DCU_B1/PG1 FP5/eMIOSB19/DCU_B2/PG2 FP4/eMIOSB21/DCU_B3/PG3 FP3/eMIOSB17/DCU_B4/PG4 FP2/eMIOSA8/DCU_B5/PG5 FP1/DCU_B6/PG6 FP0/DCU_B7/PG7 BP0/DCU_VSYNC/PG8 BP1/DCU_HSYNC/PG9 BP2/DCU_DE/PG10 BP3/DCU_PCLK/PG11 VLCD/PH5 VDDR VSSR RESET VRC_CTRL VPP XTAL VSSOSC EXTAL VSSPLL VDDPLL NC PDI10/MCKO/PK2 PDI11/MSEO/PK3 PDI12/EVTO/PK4 TDI/PH1 PDI13/EVTI/PK5 PDI14/MDO0/PK6 TDO/PH2 PDI15/MDO1/PK7 TMS/PH3 PDI16/MDO2/PK8 TCK/PH0 PDI17/MDO3/PK9 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 Figure 3 shows the pinout for the 176-pin LQFP package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176-Pin LQFP 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PB11/CNTX_B/PDI3/eMIOSA16 PB10/CNRX_B/PDI2/eMIOSA23 PB0/CNTX_A/PDI1 PB1/CNRX_A/PDI0 PJ11/PDI7 PJ10/PDI6 PJ9/PDI5 PJ8/PDI4 VSS12 VDD12 PJ3/PDI_PCLK PJ2/PDI_VSYNC PJ1/PDI_HSYNC PJ0/PDI_DE PE7/M5C1P/SSD5_3/eMIOSA8 PE6/M5C1M/SSD5_2/eMIOSA9 PE5/M5C0P/SSD5_1/eMIOSA10 PE4/M5C0M/SSD5_0/eMIOSA11 VSSMC VDDMC PE3/M4C1P/SSD4_3/eMIOSA12 PE2/M4C1M/SSD4_2/eMIOSA13 PE1/M4C0P/SSD4_1/eMIOSA14 PE0/M4C0M/SSD4_0/eMIOSA15 PD15/M3C1P/SSD3_3 PD14/M3C1M/SSD3_2 PD13/M3C0P/SSD3_1 PD12/M3C0M/SSD3_0 VSSMB VDDMB PD11/M2C1P/SSD2_3 PD10/M2C1M/SSD2_2 PD9/M2C0P/SSD2_1 PD8/M2C0M/SSD2_0 PD7/M1C1P/SSD1_3/eMIOSB16 PD6/M1C1M/SSD1_2/eMIOSB17 PD5/M1C0P/SSD1_1/eMIOSB18 PD4/M1C0M/SSD1_0/eMIOSB19 VSSMA VDDMA PD3/M0C1P/SSD0_3/eMIOSB20 PD2/M0C1M/SSD0_2/eMIOSB21 PD1/M0C0P/SSD0_1/eMIOSB22 PD0/M0C0M/SSD0_0/eMIOSB23 2.3 208 MAPBGA Package Pinout Figure 4 shows the pinout for the 208-pin BGA package. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 11 NMI/PF2 VDDE_B VSSE_B PCS_A2/eMIOSB19/RXD_B/PB12 PCS_A1/eMIOSB18/TXD_B/PB13 VDD12 VSS12 eMIOSA15/SDA_B/PK10 eMIOSA14/SCL_B/PK11 eMIOSB20/SCK_A/PB9 eMIOSB21/SOUT_A/PB8 eMIOSB22/SIN_A/PB7 CNRX_A/PDI0/PJ4 CNTX_A/PDI1/PJ5 eMIOSA22/CNRX_B/PDI2/PJ6 eMIOSA21/CNTX_B/PDI3/PJ7 CLKOUT/eMIOSB16/PCS_A0/PH4 MA0/SCK_B/PB4 FABM/MA1/SOUT_B/PB5 VDDE_B VSSE_B ABS[0]/MA2/SIN_B/PB6 VDD12 VSS12 VDDA VSSA XTAL32/AN15/PC15 EXTAL32/AN14/PC14 PCS_B0/MA2/AN13/PC13 PCS_B1/MA1/AN12/PC12 PCS_B2/MA0/AN11/PC11 SOUND/AN10(mux)/PC10 AN9/PC9 AN8/PC8 VDDE_C VSSE_C AN7/PC7 AN6/PC6 AN5/PC5 AN4/PC4 AN3/PC3 AN2/PC2 AN1/PC1 AN0/PC0 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Figure 3. 176-pin LQFP Pinout WARNING Any pins labeled “NC” must not be connected to any external circuit. 1 A B PA0 PA1 PA2 2 3 4 5 6 7 8 9 10 11 12 NC 13 NC NC NC 14 15 16 Pinout and Signal Descriptions 12 PJ0 VDDE_A PA3 PJ1 PJ2 VDDE_A PJ3 PJ4 PJ9 VDD12 PJ5 PJ6 PJ10 PJ11 PJ7 PJ8 PJ12 PJ13 PJ14 PJ15 PK0 PK1 PF0 PF1 PF3 PF4 PF5 PF6 PF7 VDD12 PK9 NC NC PK5 PK6 PK7 PK8 PF10 NC PF11 VDDE_E NC PF12 PF13 PF14 PF15 NC NC NC VSSMC PD8 PD7 PK2 PK3 PK4 C VDDE_ E NC NC NC PE7 PE6 PE2 PD13 PD12 Preliminary—Subject to Change Without Notice Freescale Semiconductor D PA4 PA6 PA8 PA10 PA12 RESET EXTAL VSSPLL PA5 PA7 PA9 PA11 PA13 PA14 VDDE_A VDDPLL PG0 PG1 PG3 PG5 PA15 PG12 VDD12 NC NC NC NC NC PE1 VDDMC PE0 E F G H J K PG2 PG4 PG6 PG7 PG10 PG11 MDO3 VREG BYPASS VDD12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MPC560xS Microcontroller Data Sheet, Rev. 1 NC PE5 PE4 PE3 PD15 PG8 PG9 NMI/PF2 PD9 VDDMB L VSSM B PD6 M XTAL VPP PH3 PH2 VDDE_B PD14 PD11 PD5 N VDDR VRC_ CTRL VLCD PK11 MDO1 PH4 MDO0 PK10 PB13 PB8 PB7 PB5 PB4 PC13 PC12 PC9 PC8 PC6 PC5 PB11 PC3 VDDMA PB10 PD10 NC PD4 PD2 PD3 PD1 P PH1 VDDE_B MDO2 PF9 PF8 R T PH0 MCKO EVTO EVTI PB12 PB9 PB6 VDDE_C PC15 PC14 PC11 PC10 PC7 VSSA PC4 VDDA PC2 PC1 PB3 PC0 PB2 PB1 VDDE_B PB0 PD0 VSSMA MSEO Figure 4. 208-pin MAPBGA Pinout 2.4 Signal Description Pinout and Signal Descriptions The following sections provide signal descriptions and related information about the functionality and configuration. 2.4.1 Pad Configuration during Reset Phases All pads have a fixed configuration under reset. During the power-up phase, all pads are forced to tristate. After power-up phase, all pads are floating with the following exceptions: • • • • • • • • • • • • • • • • • • • • • • • • • Analog input pins AN[0:9] are pull-up EVTI (208-pin package only) is pull-up. PB[6] (FAB) is pull-up. Without external strong pull-up the device starts fetching from flash RESET pad is driven low. This is released only after PHASE2 reset completion. Main oscillator pads (EXTAL, XTAL) are tristate. PA[0] DCU_R0 is pull-up PB[1] CNRX_A is pull-up PB[10] CNRX_B is pull-up PB[12] RXD_B is pull-up PB[3] RXD_A is pull-up PB[4] SCK_B is pull-up PF[0] eMIOSA13 is pull-up PF[11] eMIOSB23 is pull-up PF[13] SIN_C is pull-up PF[2] NMI is pull-up PF[3] eMIOSA11 is pull-up PF[5] eMIOSA9 is pull-up PF[6] SDA_A is pull-up PF[8] SDA_B is pull-up PH[0] TCK is pull-up PH[1] TDI is pull-up PH[3] TMS is pull-up PJ[4] PDI0 is pull-up PJ[6] PDI2 is pull-up PK[9] MDO3 is pull-up 2.4.2 Voltage Supply Pins Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 13 Pinout and Signal Descriptions Table 3. Voltage Supply Pin Descriptions Pin Number Supply pin VDD121 VSS12 VSS Function 144 LQFP 1.2 V core supply (1.08 V - 1.32 V) Low voltage ground for core domain Low voltage ground 42, 51, 103, 118, 133 43, 52, 104, 119, 134 — 176 LQFP 50, 67, 123, 148, 163 51, 68, 124, 149, 164 — 208 MAPBGA D4, D9, D13, N4 — G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10 T11 T10 N1 — B2, C3, K2 VDDA VSSA VDDR VSSR VDDE_A 3.3 V/5 V reference voltage and analog supply for A/D converter Reference ground and analog ground for A/D converter Voltage regulator VREG supply Voltage regulator ground 3.3 V/5 V I/O supply. This supply is shared with internal flash and 16 MHz IRC oscillator. 3.3 V/5 V I/O supply ground 3.3 V/5 V I/O supply. 4-16 MHz crystal oscillator shares this supply. 3.3 V/5 V I/O supply ground 3.3 V/5 V I/O supply. 32 KHz oscillator shares this supply with ADC. 3.3 V/5 V I/O supply ground 3.3 V/5 V I/O supply 3.3 V/5 V I/O supply ground Stepper motor 5 V pad supply. SSD shares this supply. Stepper motor ground Stepper motor 5 V pad supply. SSD shares this supply. Stepper motor ground Stepper motor 5 V pad supply. SSD shares this supply. Stepper motor ground 1.2 V PLL supply 53 54 22 23 7, 124 69 70 22 23 7, 154, 170 VSSE_A VDDE_B VSSE_B VDDE_C VSSE_C VDDE_E VSSE_E VDDMA2 VSSMA VDDMB2 VSSMB VDDMC 2 8, 125 38 39 63 64 109 110 77 78 87 88 97 98 31 8, 155, 171 46, 64 47, 65 79 80 133 134 93 94 103 104 113 114 31 — P3, R2, R15 — T7 — B15, C14 — N13 T16 L15 L16 H15 H16 L2 VSSMC VDDPLL MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 14 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinout and Signal Descriptions Table 3. Voltage Supply Pin Descriptions (continued) Pin Number Supply pin VSSPLL VSSOSC VLCD3 VPP4 1 2 Function 144 LQFP PLL ground Oscillator ground LCD supply option 9 V - 12 V flash test analog write signal 30 28 21 26 176 LQFP 30 28 21 26 208 MAPBGA L1 — N2 M2 Decoupling capacitors must be connected between these pins and the nearest VSS12 pin. All stepper motor supplies need to be at same level (3.3 V or 5 V). 3 Refer to LCD segment of Reference manual for usage of VLCD as supply/reference voltage source. 4 This signal needs to be connected to ground during normal operation. 2.4.3 Pad Types S = Slow1 M = Medium1,2 F = Fast1,2 I = Input only with analog feature1 J = Input/Output with analog feature X = Oscillator In the device the following types of pads are available for system pins and functional port pins: 2.4.4 System Pins The system pins are listed in Table 4. 1. Refer to Section 3.6, “I/O Pad Electrical Characteristics, for details 2. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (refer to PCR.SRC in the device reference manual, Pad Configuration Registers (PCR0 - PCR120)). MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 15 Pinout and Signal Descriptions Table 4. System Pin Descriptions System pin RESET Function Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Analog output of the oscillator amplifier circuit. Input for the clock generator in bypass mode. Analog input of the oscillator amplifier circuit. Needs to be grounded if oscillator bypass mode is used. Analog input of the 32KHz oscillator amplifier circuit. Analog output of the 32 KHz oscillator amplifier circuit. Input for the clock generator in bypass mode. Non-Maskable Interrupt I/O Pad direction type I/O M RESET configuration Input, weak pull up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 24 24 J1 EXTAL O X — 29 29 K1 XTAL I X — 27 27 M1 EXTAL32 XTAL32 O I — — 56 55 72 71 — — NMI I/O Input, weak pull up — 37 25 45 25 L3 P1 VRC_CTRL Voltage Regulator external NPN Ballast base control pin 2.4.5 Nexus Pins Table 5. Nexus Pins Pin Number System pin EVTI EVTO MCKO MDO[0] Function 144 LQFP Nexus Event In Nexus Event Out Nexus Msg Clock Out Nexus Msg Data Out — — — — 176 LQFP 37 35 33 38 208 MAPBGA T3 R3 T1 T5 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 16 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinout and Signal Descriptions Table 5. Nexus Pins (continued) Pin Number System pin MDO[1] MDO[2] MDO[3] MSE0 Function 144 LQFP Nexus Msg Data Out Nexus Msg Data Out Nexus Msg Data Out Nexus Msg Start/End Out — — — — 176 LQFP 40 42 44 34 208 MAPBGA P5 P4 L4 T2 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 17 2.4.6 Functional Ports A, B, C, D, E, F, G, H, I, J, K Table 6. Port Pin Summary Pinout and Signal Descriptions 18 Preliminary—Subject to Change Without Notice Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 The functional port pins are listed in Table 6. Port Pin PCR Alternate Register Function1 PCR[0] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[0] DCU_R0 eMIOSA[[22] SOUND GPIO[1] DCU_R1 eMIOSA[21] — GPIO[2] DCU_R2 eMIOSA[20] — GPIO[3] DCU_R3 eMIOSA[19] — GPIO[4] DCU_R4 eMIOSA[18] — GPIO[5] DCU_R5 eMIOSA[17] — GPIO[6] DCU_R6 eMIOSA[15] — GPIO[7] DCU_R7 eMIOSA[16] — Special Function FP23 Peripheral SIU DCU PWM/Timer Sound SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — Pad RESET I/O Type Config. Direction 2 3 I/O M Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 135 165 A1 PA[0] PA[1] PCR[1] FP22 I/O M None, None 136 166 B1 PA[2] PCR[2] FP21 I/O M None, None 137 167 C1 PA[3] PCR[3] FP20 I/O M None, None 138 168 C2 PA[4] PCR[4] FP19 I/O M None, None 139 169 D1 PA[5] PCR[5] FP18 I/O M None, None 140 172 D2 PA[6] PCR[6] FP17 I/O M None, None 141 173 E1 PA[7] PCR[7] FP16 I/O M None, None 142 174 E2 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[8] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[8] DCU_G0 eMIOSB[23] SCL_C GPIO[9] DCU_G1 eMIOSB[18] SDA_C GPIO[10] DCU_G2 eMIOSB[20] — GPIO[11] DCU_G3 eMIOSA[13] — GPIO[12] DCU_G4 eMIOSA[12] — GPIO[13] DCU_G5 eMIOSA[11] — GPIO[14] DCU_G6 eMIOSA[10] — GPIO[15] DCU_G7 eMIOSA[9] — Special Function FP15 Peripheral SIU DCU PWM/Timer I2C_2 SIU DCU PWM/Timer I2C_2 SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — Pad RESET I/O Type Config. Direction 2 3 I/O M None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 143 175 F1 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 19 PA[8] PA[9] PCR[9] FP14 I/O M None, None 144 176 F2 PA[10] PCR[10] FP13 I/O M None, None 1 1 G1 PA[11] PCR[11] FP12 I/O M None, None 2 2 G2 PA[12] PCR[12] FP11 I/O M None, None 3 3 H1 PA[13] PCR[13] FP10 I/O M None, None 4 4 H2 PA[14] PCR[14] FP9 I/O M None, None 5 5 J2 Pinout and Signal Descriptions PA[15] PCR[15] FP8 I/O M None, None 6 6 H3 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[16] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option3 Option 0 Option 1 Option 2 Option3 Option 0 Option 1 Option 2 Option3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[16] CANTX_A PDI1 — GPIO[17] CANRX_A PDI0 — GPIO[18] TXD_A — — GPIO[19] RXD_A — — GPIO[20] SCK_B MA0 — GPIO[21] SOUT_B MA1 FABM GPIO[22] SIN_B MA2 ABS[0] GPIO[23] SIN_A eMIOSB[22] — Special Function — Peripheral SIU CAN-A PDI — SIU CAN-A PDI — SIU LIN_A — — SIU LIN_A — — SIU SPI_1 ADC — SIU SPI_1 ADC Control SIU SPI_1 ADC Control SIU SPI_A PWM/Timer — Pad RESET I/O Type Config. Direction 2 3 I/O M None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 106 130 T15 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 20 PB[0] PB[1] PCR[17] — I/O S Input, Pull Up 105 129 T14 PB[2] PCR[18] — I/O S None, None 112 140 R14 PB[3] PCR[19] — I/O S Input, Pull Up 111 139 R13 PB[4] PCR[20] — I/O M Input, Pull Up 48 62 P8 PB[5] PCR[21] — I/O M Input, Pull Down Input, Pull Up 49 63 N8 PB[6] PCR[22] — I/O S 50 66 R7 Pinout and Signal Descriptions PB[7] PCR[23] — I/O S None, None 46 56 P7 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[24] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 — — Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[24] SOUT_A eMIOSB[21] — GPIO[25] SCK_A eMIOSB[20] — GPIO[26] CNRX_B PDI2 eMIOSA[23] GPIO[27] CNTX_B PDI3 eMIOSA[16] GPIO[28] RXD_B eMIOSB[19] PCS_A2 GPIO[29] TXD_B eMIOSB[18] PCS_A1 Reserved Reserved GPIO[30] AN[0] — — GPIO[31] AN[1] — — Special Function — Peripheral SIU SPI_A PWM/Timer — SIU SPI_A PWM/Timer — SIU CAN-B PDI PWM/Timer SIU CAN-B PDI PWM/Timer SIU LIN_B PWM/Timer SPI_0 SIU LIN_B PWM/Timer SPI_0 — — SIU ADC — — SIU ADC — — I Pad RESET I/O Type Config. Direction 2 3 I/O M None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 45 55 N7 Pinout and Signal Descriptions 21 PB[8] PB[9] Preliminary—Subject to Change Without Notice Freescale Semiconductor PCR[25] MPC560xS Microcontroller Data Sheet, Rev. 1 PB[10] PCR[26] PB[11] PCR[27] PB[12] PCR[28] PB[13] PCR[29] PB[14] PB[15] PC[0] — — PCR[30] PC[1] PCR[31] — I/O M Input, Pull Up 44 54 T6 — I/O S Input, Pull Up 107 131 P13 — I/O M None, None 108 132 N12 — I/O S Input, Pull Up 40 48 R6 — I/O S None, None 41 49 P6 — — — — — — — A — — Input, Pull Up — — 72 — — 88 A11 — T13 — I A Input, Pull Up 71 87 T12 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[32] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[32] AN[2] — — GPIO[33] AN[3] — — GPIO[34] AN[4] — — GPIO[35] AN[5] — — GPIO[36] AN[6] — — GPIO[37] AN[7] — — GPIO[38] AN[8] — — GPIO[39] AN[9] — — Special Function — Peripheral SIU ADC — — SIU ADC — — SIU ADC — — SIU ADC — — SIU ADC — — SIU ADC — — SIU ADC — — SIU ADC — — Pad RESET I/O Type Config. Direction 2 3 I A Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 70 86 R12 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 22 PC[2] PC[3] PCR[33] — I A Input, Pull Up 69 85 P12 PC[4] PCR[34] — I A Input, Pull Up 68 84 R11 PC[5] PCR[35] — I A Input, Pull Up 67 83 P11 PC[6] PCR[36] — I A Input, Pull Up 66 82 N11 PC[7] PCR[37] — I A Input, Pull Up 65 81 R10 PC[8] PCR[38] — I A Input, Pull Up 62 78 P10 Pinout and Signal Descriptions PC[9] PCR[39] — I A Input, Pull Up 61 77 N10 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[40] AN[10] SOUND — GPIO[41] AN[11] MA0 PCS_B2 GPIO[42] AN[12] MA1 PCS_B1 GPIO[43] AN[13] MA2 PCS_B0 GPIO[44] AN[14] EXTAL32 — GPIO[45] AN[15] XTAL32 — GPIO[46] M0C0M SSD0_0 eMIOSB[23] GPIO[47] M0C0P SSD0_1 eMIOSB[22] Special Function — Peripheral SIU ADC Sound — SIU ADC ADC SPI_B SIU ADC ADC SPI_B SIU ADC ADC SPI_B SIU ADC Osc — SIU ADC Osc — SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer Pad RESET I/O Type Config. Direction 2 3 I/O S Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 60 76 T9 Pinout and Signal Descriptions 23 PC[10] PCR[40] PC[11] PCR[41] Preliminary—Subject to Change Without Notice Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 PC[12] PCR[42] PC[13] PCR[43] PC[14] PCR[44] PC[15] PCR[45] PD[0] PCR[46] PD[1] PCR[47] — I/O S None, None 59 75 R9 — I/O S None, None 58 74 P9 — I/O S None, None 57 73 N9 — I/O S None, None 56 72 T8 — I/O S None, None 55 71 R8 — I/O SMD None, None 73 89 R16 — I/O SMD None, None 74 90 P16 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[48] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[48] M0C1M SSD0_2 eMIOSB[21] GPIO[49] M0C1P SSD0_3 eMIOSB[20] GPIO[50] M1C0M SSD1_0 eMIOSB[19] GPIO[51] M1C0P SSD1_1 eMIOSB[18] GPIO[52] M1C1M SSD1_2 eMIOSB[17] GPIO[53] M1C1P SSD1_3 eMIOSB[16] GPIO[54] M2C0M SSD2_0 — GPIO[55] M2C0P SSD2_1 — Special Function — Peripheral SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD — SIU SMD SSD — Pad RESET I/O Type Config. Direction 2 3 I/O SMD None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 75 91 P15 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 24 PD[2] PD[3] PCR[49] — I/O SMD None, None 76 92 N16 PD[4] PCR[50] — I/O SMD None, None 79 95 N15 PD[5] PCR[51] — I/O SMD None, None 80 96 M15 PD[6] PCR[52] — I/O SMD None, None 81 97 M16 PD[7] PCR[53] — I/O SMD None, None 82 98 K16 PD[8] PCR[54] — I/O SMD None, None 83 99 J16 Pinout and Signal Descriptions PD[9] PCR[55] — I/O SMD None, None 84 100 K15 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[56] M2C1M SSD2_2 — GPIO[57] M2C1P SSD2_3 — GPIO[58] M3C0M SSD3_0 — GPIO[59] M3C0P SSD3_1 — GPIO[60] M3C1M SSD3_2 — GPIO[61] M3C1P SSD3_3 — GPIO[62] M4C0M SSD4_0 eMIOSA[15] GPIO[63] M4C0P SSD4_1 eMIOSA[14] Special Function — Peripheral SIU SMD SSD — SIU SMD SSD — SIU SMD SSD — SIU SMD SSD — SIU SMD SSD — SIU SMD SSD — SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer Pad RESET I/O Type Config. Direction 2 3 I/O SMD None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 85 101 N14 Pinout and Signal Descriptions 25 PD[10] PCR[56] PD[11] PCR[57] Preliminary—Subject to Change Without Notice Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 PD[12] PCR[58] PD[13] PCR[59] PD[14] PCR[60] PD[15] PCR[61] PE[0] PCR[62] PE[1] PCR[63] — I/O SMD None, None 86 102 M14 — I/O SMD None, None 89 105 L14 — I/O SMD None, None 90 106 K14 — I/O SMD None, None 91 107 M13 — I/O SMD None, None 92 108 L13 — I/O SMD None, None 93 109 J15 — I/O SMD None, None 94 110 G15 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[64] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 — — — — — — — — Function GPIO[64] M4C1M SSD4_2 eMIOSA[13] GPIO[65] M4C1P SSD4_3 eMIOSA[12] GPIO[66] M5C0M SSD5_0 eMIOSA[11] GPIO[67] M5C0P SSD5_1 eMIOSA[10] GPIO[68] M5C1M SSD5_2 eMIOSA[9] GPIO[69] M5C1P SSD5_3 eMIOSA[8] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Special Function — Peripheral SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer SIU SMD SSD PWM/Timer — — — — — — — — — — — — — — Pad RESET I/O Type Config. Direction 2 3 I/O SMD None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 95 111 J14 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 26 PE[2] PE[3] PCR[65] — I/O SMD None, None 96 112 K13 PE[4] PCR[66] — I/O SMD None, None 99 115 J13 PE[5] PCR[67] — I/O SMD None, None 100 116 H13 PE[6] PCR[68] — I/O SMD None, None 101 117 H14 PE[7] PCR[69] — I/O SMD None, None 102 118 G14 PE[8] PE[9] PE[10] PE[11] PE[12] PE[13] PE[14] PE[15] — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Pinout and Signal Descriptions — — — — — — — Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[70] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[70] eMIOSA[13] PDI4 eMIOSA[22] GPIO[71] eMIOSA[12] PDI5 eMIOSA[21] GPIO[72] NMI — — GPIO[73] eMIOSA[11] PDI6 — GPIO[74] eMIOSA[10] PDI7 — GPIO[75] eMIOSA[9] DCU_TAG — GPIO[76] SDA_A — — GPIO[77] SCL_A PCS_B2 — FP37 Special Function FP39 Peripheral SIU PWM/Timer PDI PWM/Timer SIU PWM/Timer PDI PWM/Timer — SIU NMI — — SIU PWM/Timer PDI — SIU PWM/Timer PDI — SIU PWM/Timer DCU — SIU I2C_A — — SIU I2C_A SPI_B — Pad RESET I/O Type Config. Direction 2 3 I/O S Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 113 143 A8 Pinout and Signal Descriptions 27 PF[0] PF[1] Preliminary—Subject to Change Without Notice Freescale Semiconductor PCR[71] MPC560xS Microcontroller Data Sheet, Rev. 1 PF[2] PCR[72] PF[3] PCR[73] PF[4] PCR[74] PF[5] PCR[75] PF[6] PCR[76] PF[7] PCR[77] FP38 I/O S None, None 114 144 B8 I/O S Input, Pull Up 37 45 L3 I/O M Input, Pull Up 115 145 C8 FP36 I/O M None, None 116 146 D8 FP35 I/O M Input, Pull Up 117 147 A9 FP34 I/O S Input, Pull Up 120 150 B9 FP33 I/O S None, None 121 151 C9 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[78] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[78] SDA_B PCS_B1 RXD_B GPIO[79] SCL_B PCS_B0 TXD_B GPIO[80] eMIOSA[16] PCS_C0 — GPIO[81] eMIOSB[23] PCS_C1 — GPIO[82] eMIOSB[16] PCS_C2 — GPIO[83] SIN_C CNRX_B — GPIO[84] SOUT_C CANTX_B — GPIO[85] SCK_C — — Special Function FP32 Peripheral SIU I2C_B SPI_B LIN_B SIU I2C_B SPI_B LIN_B SIU PWM/Timer SPI_C — SIU PWM/Timer SPI_C — SIU PWM/Timer SPI_C — SIU SPI_C CAN_B — SIU SPI_C CAN_B — SIU SPI_C — — Pad RESET I/O Type Config. Direction 2 3 I/O S Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 122 152 T4 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 28 PF[8] PF[9] PCR[79] FP31 I/O S None, None 123 153 R4 PF[10] PCR[80] FP29 I/O M None, None 127 157 A14 PF[11] PCR[81] FP28 I/O M Input, Pull Up 128 158 A15 PF[12] PCR[82] FP27 I/O M None, None 129 159 A16 PF[13] PCR[83] FP26 I/O M Input, Pull Up 130 160 B16 PF[14] PCR[84] FP25 I/O M None, None 131 161 C16 Pinout and Signal Descriptions PF[15] PCR[85] FP24 I/O F None, None 132 162 D16 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[86] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Function GPIO[86] DCU_B0 SCL_D SOUND GPIO[87] DCU_B1 SDA_D — GPIO[88] DCU_B2 eMIOSB[19] — GPIO[89] DCU_B3 eMIOSB[21] — GPIO[90] DCU_B4 eMIOSB[17] — GPIO[91] DCU_B5 eMIOSA[8] — GPIO[92] DCU_B6 — — GPIO[93] DCU_B7 — — Special Function FP7 Peripheral SIU DCU I2C_3 Sound SIU DCU I2C_3 — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU PWM/Timer — SIU DCU — — SIU DCU — — Pad RESET I/O Type Config. Direction 2 3 I/O M None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 9 9 D3 Pinout and Signal Descriptions 29 PG[0] PG[1] Preliminary—Subject to Change Without Notice Freescale Semiconductor PCR[87] MPC560xS Microcontroller Data Sheet, Rev. 1 PG[2] PCR[88] PG[3] PCR[89] PG[4] PCR[90] PG[5] PCR[91] PG[6] PCR[92] PG[7] PCR[93] FP6 I/O M None, None 10 10 E3 FP5 I/O M None, None 11 11 E4 FP4 I/O M None, None 12 12 F3 FP3 I/O M None, None 13 13 F4 FP2 I/O M None, None 14 14 G3 FP1 I/O M None, None 15 15 G4 FP0 I/O M None, None 16 16 H4 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[94] Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 Option 0 Option 1 Option 2 Option 3 — — — Option 0 Option 1 Option 2 Option 3 Function GPIO[94] DCU_VSYNC — — GPIO[95] DCU_HSYNC — — GPIO[96] DCU_DE — — GPIO[97] DCU_PCLK — — GPIO[98] eMIOSA[23] SOUND eMIOSA[8] Reserved Reserved Reserved GPIO[99] TCK — — GPIO[100] TDI — — Special Function BP0 Peripheral SIU DCU — — SIU DCU — — SIU DCU — — SIU DCU — — SIU PWM/Timer Sound PWM/Timer — — — — SIU JTAG — — SIU JTAG — — — — — I/O Pad RESET I/O Type Config. Direction 2 3 I/O M Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA 17 17 J3 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 30 PG[8] PG[9] PCR[95] BP1 I/O M Input, Pull Up 18 18 K3 PG[10] PCR[96] BP2 I/O M None, None 19 19 J4 PG[11] PCR[97] BP3 I/O M None, None 20 20 K4 PG[12] PCR[98] FP30 I/O S None, None 126 156 D10 PG[13] PG[14] PG[15] — — — — — — — — — S — — — Input, Pull Up — — — 36 — — — 43 — — — R1 Pinout and Signal Descriptions PH[0]4 PCR[99] PH[1]4 PCR[100] Option 0 Option 1 Option 2 Option 3 — I/O S Input, Pull Up 33 36 P2 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 Function GPIO[101] TDO — — GPIO[102] TMS — — GPIO[103] PCS_A0 eMIOSB[16] CLKOUT GPIO[104] VLCD — — Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GPIO[105] PDI_DE — — Special Function — Peripheral SIU JTAG — — SIU JTAG — — SIU SPI_0 PWM/Timer Control SIU LCD — — — — — — — — — — — — SIU PDI — — I/O — — — — — — — — — — — — — — — — — — — — S — — — — — — — — — — None, None Pad RESET I/O Type Config. Direction 2 3 I/O M Output, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA 34 39 N3 Pinout and Signal Descriptions 31 PH[2]4 PCR[101] Option 0 Option 1 Option 2 Option 3 PH[3]4 PCR[102] Option 0 Option 1 Option 2 Option 3 MPC560xS Microcontroller Data Sheet, Rev. 1 PH[4] PCR[103] Option 0 Option 1 Option 2 Option 3 PCR[104] Option 0 Option 1 Option 2 Option 3 — — — — — — — — — — — — — — — — — — — — Preliminary—Subject to Change Without Notice Freescale Semiconductor PH[5] PH[6] PH[7] PH[8] PH[9] PH[10] PH[11] PH[12] PH[13] PH[14] PH[15] PJ[0] PCR[105] Option 0 Option 1 Option 2 Option 3 — I/O S Input, Pull Up 35 41 M3 — I/O F None, None 47 61 R5 — 21 21 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 119 — — — — — — — — — — A2 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[106] Option 0 Option 1 Option 2 Option 3 PCR[107] Option 0 Option 1 Option 2 Option 3 PCR[108] Option 0 Option 1 Option 2 Option 3 PCR[109] Option 0 Option 1 Option 2 Option 3 PCR[110] Option 0 Option 1 Option 2 Option 3 PCR[111] Option 0 Option 1 Option 2 Option 3 PCR[112] Option 0 Option 1 Option 2 Option 3 PCR[113] Option 0 Option 1 Option 2 Option 3 Function GPIO[106] PDI_HSYNC — — GPIO[107] PDI_VSYNC — — GPIO[108] PDI_PCLK — — GPIO[109] PDI[0] CNRX_A — GPIO[110] PDI[1] CNTX_A — GPIO[111] PDI[2] CNRX_B eMIOSA[22] GPIO[112] PDI[3] CNTX_B eMIOSA[21] GPIO[113] PDI[4] — — Special Function — Peripheral SIU PDI — — SIU PDI — — SIU PDI — — SIU PDI CAN-A — SIU PDI CAN-A — SIU PDI CAN-B PWM/Timer SIU PDI CAN-B PWM/Timer SIU PDI — — Pad RESET I/O Type Config. Direction 2 3 I/O S None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA — 120 A3 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 32 PJ[1] PJ[2] — I/O S None, None — 121 B3 PJ[3] — I/O M None, None — 122 A4 PJ[4] — I/O S Input, Pull Up — 57 B4 PJ[5] — I/O M None, None — 58 A5 PJ[6] — I/O S Input, Pull Up — 59 B5 PJ[7] — I/O M None, None — 60 A6 Pinout and Signal Descriptions PJ[8] — I/O S None, None — 125 B6 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[114] Option 0 Option 1 Option 2 Option 3 PCR[115] Option 0 Option 1 Option 2 Option 3 PCR[116] Option 0 Option 1 Option 2 Option 3 PCR[117] Option 0 Option 1 Option 2 Option 3 PCR[118] Option 0 Option 1 Option 2 Option 3 PCR[119] Option 0 Option 1 Option 2 Option 3 PCR[120] Option 0 Option 1 Option 2 Option 3 PCR[121] Option 0 Option 1 Option 2 Option 3 Function GPIO[114] PDI[5] — — GPIO[115] PDI[6] — — GPIO[116] PDI[7] — — GPIO[117] PDI[8] eMIOSB[17] — GPIO[118] PDI[9] eMIOSB[20] — GPIO[119] PDI[10] eMIOSA[20] — GPIO[120] PDI[11] eMIOSA[19] — GPIO[121] PDI[12] eMIOSA[18] DCU_TAG Special Function — Peripheral SIU PDI — — SIU PDI — — SIU PDI — — SIU PDI PWM/Timer — SIU PDI PWM/Timer — SIU PDI PWM/Timer — SIU PDI PWM/Timer — SIU PDI PWM/Timer DCU Pad RESET I/O Type Config. Direction 2 3 I/O S None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA — 126 C4 Pinout and Signal Descriptions 33 PJ[9] PJ[10] Preliminary—Subject to Change Without Notice Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 PJ[11] PJ[12] PJ[13] PJ[14] PJ[15] PK[0] — I/O S None, None — 127 C5 — I/O S None, None — 128 D5 — I/O M None, None — 135 C6 — I/O M None, None — 136 D6 — I/O M None, None — 137 A7 — I/O M None, None — 138 B7 — I/O M None, None — 141 C7 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[122] Option 0 Option 1 Option 2 Option 3 PCR[123] Option 0 Option 1 Option 2 Option 3 PCR[124] Option 0 Option 1 Option 2 Option 3 PCR[125] Option 0 Option 1 Option 2 Option 3 PCR[126] Option 0 Option 1 Option 2 Option 3 PCR[127] Option 0 Option 1 Option 2 Option 3 PCR[128] Option 0 Option 1 Option 2 Option 3 PCR[129] Option 0 Option 1 Option 2 Option 3 Function GPIO[122] PDI[13] eMIOSA[17] — GPIO[123] MCKO PDI[10] — GPIO[124] MSEO PDI[11] — GPIO[125] EVTO PDI[12] — GPIO[126] EVTI PDI[13] — GPIO[127] MDO0 PDI[14] — GPIO[128] MDO1 PDI[15] — GPIO[129] MDO2 PDI[16] — Special Function — Peripheral SIU PDI PWM/Timer — SIU Nexus PDI — SIU Nexus PDI — SIU Nexus PDI — SIU Nexus PDI — SIU Nexus PDI — SIU Nexus PDI — SIU Nexus PDI — Pad RESET I/O Type Config. Direction 2 3 I/O M None, None Pin Number 144 LQFP 176 LQFP 208 MAPBGA — 142 D7 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 34 PK[1] PK[2] — I/O F None, None — 33 B12 PK[3] — I/O M None, None — 34 C12 PK[4] — I/O M None, None — 35 D12 PK[5] — I/O M None, None — 37 — PK[6] — I/O M None, None — 38 B11 PK[7] — I/O M None, None — 40 C11 Pinout and Signal Descriptions PK[8] — I/O M None, None — 42 D11 Table 6. Port Pin Summary (continued) Port Pin PCR Alternate Register Function1 PCR[130] Option 0 Option 1 Option 2 Option 3 PCR[131] Option 0 Option 1 Option 2 Option 3 PCR[132] Option 0 Option 1 Option 2 Option 3 — — — — — — — — Function GPIO[130] MDO3 PDI[17] — GPIO[131] SDA_B eMIOSA[15] — GPIO[132] SCL_B eMIOSA[14] — Reserved Reserved Reserved Reserved Special Function — Peripheral SIU Nexus PDI — SIU I2C_B PWM/Timer — SIU I2C_B PWM/Timer — — — — — Pad RESET I/O Type Config. Direction 2 3 I/O M Input, Pull Up Pin Number 144 LQFP 176 LQFP 208 MAPBGA — 44 A10 Freescale Semiconductor MPC560xS Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 35 PK[9] PK[10] — I/O S None, None — 52 N6 PK[11] — I/O S None, None — 53 N5 PK[12] PK[13] PK[14] PK[15] 1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 -> Option 0; PCR.PA = 01 -> Option 1; PCR.PA = 10 -> Option 2; PCR.PA = 11-> Option 3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”. 2 A=A, S=Slow, M=Medium, F=Fast, SMD=Stepper Motor Driver 3 Reset configuration is given as I/O direction and pull, e.g., “Input, pullup”. 4 Out of reset pins PH[0:3] are available as JTAG pins (TCK, TDI, TDO and TMS respectively). It is up to the user to configure pins PH[0:3] when needed. Pinout and Signal Descriptions Pinout and Signal Descriptions 2.4.7 Signal Details Table 7. Signal Details Signal Peripheral BAM Analog-to-digital conversion (ADC) Description Alternate Boot Select. gives an option to boot by downloading code via CAN or LIN. Inputs used to bring into the device sensor-based signals for A/D conversion. Force Alternate Boot mode. Forces the device to boot from the external bus (Can or LIN). If not asserted, the device boots up from the lowest flash sector containing a valid boot signature. Display Control Unit Indicates that valid pixels are present when high; otherwise low to allow a sub frame display for pixels. Display Control Unit Horizontal sync pulse for TFT-LCD display. Display Control Unit Output pixel clock for TFT-LCD display Display Control Unit Red, green and blue color 8 bit Pixel values for TFT-LCD displays. ABS[0] AN[0:15] FABM DCU_DE DCU_HSYNC, DCU_PCLK DCU_R[0:7], DCU_G[0:7] DCU_B[0:7] DCU_TAG Display Control Unit High indicates certain pixels that can be called as tagged pixels, upon which internal CRC has been calculated based on pixel values and pixel position. Display Control Unit Vertical sync pulse for TFT-LCD display. DSPI Peripheral chip selects when device is in Master mode; not used in slave modes. SPI clock signal - bi-directional. DCU_VSYNC PCS_A[0:2], PCS_B[0:2], PCS_C[0:2} SCK_A, SCK_B, SCK_C SIN _A, SIN _B, SIN _C SOUT _A, SOUT _B, SOUT _C eMIOSA[0:23], eMIOSB[0:23] DSPI DSPI SPI data input signal. DSPI SPI data output signal. eMIOS Enhanced Modular Input Output System. 16+9 channel eMIOS for timed input or output functions. Receive (RX) pins for the CAN bus transceiver. Transmit (TX) pins for the CAN bus transceiver. Bidirectional serial clock compatible with I2C specifications. CNRX_A, CNRX_B FlexCAN CNTX_A, CNTX_B SCL_A, SCL_B, SCL_C, SCL_D SDA_A, SDA_B, SDA_C, SDA_D FlexCAN I2C I2C Bidirectional serial data compatible with I2C specifications. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 36 Preliminary—Subject to Change Without Notice Freescale Semiconductor Pinout and Signal Descriptions Table 7. Signal Details (continued) Signal TCK TDI TDO TMS Peripheral JTAG JTAG JTAG JTAG Description Debug port serial clock as per JTAG specifications. Debug port serial data input port as per JTAG standards specifications. Debug port serial data output port as per JTAG standards specifications. Debug port Test Mode Select signal for the JTAG TAP controller state machine and indicates various state transitions for the TAP controller in the device. Back plane signals from the LCD controlling the back plane reference voltage for the LCD display. Front plane signals for LCD segments. Nexus2+ event input trigger. Nexus2+ event output trigger. Output clock for the development tool Message output port pins that send information bits to the development tools for messages such as Branch Trace Message (BTM), Ownership Trace Message (OTM), Data Trace Message (DTM). Only available in reduced port mode. Output pin. Indicates the start or end of the variable length message on the MDO pins. Video/graphic data in various RGB modes input to the DCU. Input signal indicates the validity of pixel data on the Input PDI data bus. For valid Pixel Data this is high, otherwise low. Input indicates the timing reference for the start of each frame line for the PDI Input data. Output pixel clock for PDI. Input indicates the timing reference for the start of a frame for the PDI input data. SCI/LIN Receive data signal. This port is used to download the code for the BAM boot sequence SCI/LIN Receive data signal. Input pad for the LIN SCI module. Connects to the internal LIN second port. This port is used to download the code for the BAM boot sequence SCI/LIN Transmit data signal. Transmit (output) port for the second LIN module in the chip . Sound signal to the speaker/buzzer. BP[0:3] FP[0:39] EVTI EVTO MCKO MDO[0:3] LCD LCD Nexus Nexus Nexus Nexus MSEO PDI[0:17] PDI_DE PDI_HSYNC PDI_PCLK PDI_VSYNC RXD_A RXD_B TXD_A TXD_B SOUND Nexus Parallel Display Interface Parallel Display Interface Parallel Display Interface Parallel Display Interface Parallel Display Interface LINFlex-UART LINFlex-UART LINFlex-UART LINFlex-UART Sound generation logic (SGL) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 37 Pinout and Signal Descriptions Table 7. Signal Details (continued) Signal SSD[0..5]_0 SSD[0..5]_1 SSD[0..5]_2 SSD[0..5]_3 M[0:5]C0M M[0:5]C0P M[0:5]C1M M[0:5]C1P CLKOUT MA[0:2] Peripheral SSD (Stepper Stall Detect) Interface Description Bidirectional SSD inputs and control signals Stepper Motor Control (SMC) Interface Clock generation module (CGM) ADC Controls stepper motors in Dual H bridge configuration. Output clock. It can be selected from several internal clocks of the device from the clock generation module. These three control bits are output to enable the selection for an external Analog Mux for expansion channels. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 38 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3 Electrical Characteristics This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the Symbol column. 3.1 Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Value Symbol VDDA Parameter SR Voltage on VDDA pin (ADC reference) with respect to ground (VSSA) SR Voltage on VSSA (ADC reference) pin with respect VSS CC Voltage on VDDPLL (1.2 V PLL supply) pin with respect to ground (VSSPLL) SR Voltage on VSSMC (stepper motor supply ground) pin with respect to VSS SR Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) SR Voltage on VSSR (regulator ground) pin with respect to VSS CC Voltage on VDD12 pin with respect to ground (VSS12) CC Voltage on VSS12 pin with respect to VSS SR Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) SR Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) SR Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) SR Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) Conditions Min -0.3 Relative to VDD VDD-0.3 VSS-0.1 1.08 Relative to VDD VDD-0.3 VSS-0.1 -0.3 Relative to VDD VDD-0.3 VSS-0.1 1.08 VSS-0.1 -0.3 -0.3 -0.3 -0.3 Max +5.5 VDD+0.3 VSS+0.1 1.32 VDD+0.3 VSS+0.1 +5.5 VDD+0.3 VSS+0.1 1.4 VSS+0.1 +5.5 +5.5 +5.5 +5.5 V V V V V V V V V V V V Unit VSSA VDDPLL VSSPLL VDDR VSSR VDD12 VSS12 VDDE_A1 VDDE_B1 VDDE_C1 VDDE_E1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 39 Electrical Characteristics Table 8. Absolute Maximum Ratings (continued) Value Symbol VDDMA1 VDDMB1 VDDMC1 VSS2 VSSOSC VLCD VIN Parameter SR Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) SR Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC) SR I/O supply ground SR Voltage on VSSOSC (oscillator ground) pin with respect to VSS SR Voltage on VLCD (LCD supply) pin with respect to VSS SR Voltage on any GPIO pin with respect to ground (VSS) SR Injected input current on any pin during overload condition SR Absolute sum of all injected input currents during overload condition Conditions Min -0.3 -0.3 -0.3 0 VSS-0.1 0 -0.3 Relative to VDD -0.3 -10 -50 -55 Max +5.5 +5.5 +5.5 0 VSS+0.1 VDDE_A +0.3 +5.5 VDD+0.3 10 50 150 2000 °C V mA V V V V V V V Unit IINJPAD IINJSUM TSTORAGE SR Storage temperature ESDHBM 1 SR ESD Susceptibility (Human Body Model) Throughout the remainder of this document VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC, unless otherwise noted. 2 Throughout the remainder of this document V SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC, unless otherwise noted. NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 40 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.1.1 Recommended Operating Conditions Table 9. Recommended Operating Conditions (3.3 V) Value Symbol VDDA1 Parameter SR Voltage on VDDA pin (ADC reference) with respect to ground (VSS) SR Voltage on VSSA (ADC reference) pin with respect VSS CC Voltage on VDDPLL (1.2 V PLL supply) pin with respect to ground (VSSPLL) SR Voltage on VSSMC (stepper motor supply ground) pin with respect to VSS SR Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) SR Voltage on VSSR (regulator ground) pin with respect to VSS Conditions Min +3.0 Relative to VDD VDD-0.1 VSS-0.1 1.08 VSS-0.1 +3.0 Relative to VDD VDD-0.1 VSS-0.1 1.08 VSS-0.1 +3.0 Max +3.6 VDD+0.1 VSS+0.1 1.32 VSS+0.1 +3.6 VDD+0.1 VSS+0.1 1.4 VSS+0.1 +3.6 V V V V V V V V V Unit VSSA VDDPLL VSSPLL VDDR2 VSSR VDD123,4 CC Voltage on VDD12 pin with respect to ground (VSS12) VSS12 VDD5,6,7 CC Voltage on VSS12 pin with respect to VSS SR Voltage on VDD pins (VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC) with respect to ground (VSS) SR I/O supply ground SR Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) SR Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) VSS8 VDDE_A VDDE_B 0 +3.0 +3.0 +3.0 +3.0 +3.0 +3.0 +3.0 0 0 +3.6 +3.6 +3.6 +3.6 +3.6 +3.6 +3.6 0 V V V V V V V V V VDDE_C9 SR Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) VDDE_E VDDMA VDDMB VDDMC VSSOSC SR Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) SR Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) SR Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC) SR Voltage on VSSOSC (oscillator ground) pin with respect to VSS MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 41 Electrical Characteristics Table 9. Recommended Operating Conditions (3.3 V) (continued) Value Symbol VLCD TVDD TA TJ 1 2 Parameter SR Voltage on VLCD (LCD supply) pin with respect to VSS SR VDD slope to ensure correct power up10 SR Ambient temperature under bias SR Junction temperature under bias Conditions Min 0 Max VDDE_A +0.3 0.25 -40 -40 +105 +150 Unit V V/µs °C 100 nF capacitance needs to be provided between VDDA/VSSA pair. 200 μF capacitance must be connected between VDDR and VSS12. 3 VDD12 cannot be used to drive any external component. 4 Each VDD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF. 5V DD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 6 100 nF capacitance needs to be provided between each V /V DD SS pair 7 Full electrical specification cannot be guaranteed when voltage drops below 3.0V. In particular, ADC electrical characteristics and I/O’s DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL device is reset. 8V SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and VSSMC) unless otherwise noted. 9V DDE_C should not be less than VDDA. 10 Guaranteed by device validation Table 10. Recommended Operating Conditions (5.0 V) Value Symbol VDDA1 Parameter SR Voltage on VDDA pin (ADC reference) with respect to ground (VSS) Conditions Min +4.5 Voltage drop2 +3.0 VDD-0.1 VSS-0.1 1.08 VSS-0.1 +4.5 Voltage drop2 +3.0 VDD-0.1 VSS-0.1 1.08 Max +5.5 +5.5 VDD+0.1 VSS+0.1 1.32 VSS+0.1 +5.5 +5.5 VDD+0.1 VSS+0.1 1.4 V V V V V V V Unit Relative to VDD VSSA VDDPLL VSSPLL VDDR3 SR Voltage on VSSA (ADC reference) pin with respect VSS CC Voltage on VDDPLL (1.2 V PLL supply) pin with respect to ground (VSSPLL) SR Voltage on VSSMC (stepper motor supply ground) pin with respect to VSS SR Voltage on VDDR pin (regulator supply) with respect to ground (VSSR) Relative to VDD VSSR VDD124,5 SR Voltage on VSSR (regulator ground) pin with respect to VSS CC Voltage on VDD12 pin with respect to ground (VSS12) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 42 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 10. Recommended Operating Conditions (5.0 V) (continued) Value Symbol VSS12 VDD 6,7 Parameter CC Voltage on VSS12 pin with respect to VSS SR Voltage on VDD pins (VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB, VDDMC) with respect to ground (VSS) SR I/O supply ground SR Voltage on VDDE_A (I/O supply) pin with respect to ground (VSSE_A) SR Voltage on VDDE_B (I/O supply) pin with respect to ground (VSSE_B) Conditions Min VSS-0.1 Voltage drop 2 Unit Max VSS+0.1 +5.5 V V +4.5 VSS8 VDDE_A VDDE_B 0 +4.5 +4.5 +4.5 +4.5 +4.5 +4.5 +4.5 0 0 0 +5.5 +5.5 +5.5 +5.5 +5.5 +5.5 +5.5 0 VDDE_A +0.3 0.25 V V V V V V V V V V V/µs °C VDDE_C9 SR Voltage on VDDE_C (I/O supply) pin with respect to ground (VSSE_C) VDDE_E VDDMA VDDMB VDDMC VSSOSC VLCD TVDD TA SR Voltage on VDDE_E (I/O supply) pin with respect to ground (VSSE_E) SR Voltage on VDDMA (stepper motor supply) pin with respect to ground (VSSMA) SR Voltage on VDDMB (stepper motor supply) pin with respect to ground (VSSMB) SR Voltage on VDDMC (stepper motor supply) pin with respect to ground (VSSMC) SR Voltage on VSSOSC (oscillator ground) pin with respect to VSS SR Voltage on VLCD (LCD supply) pin with respect to VSS SR VDD slope to ensure correct power up10 SR Ambient temperature under bias -40 -40 +105 +105 +150 TJ 1 2 SR Junction temperature under bias -40 100 nF capacitance needs to be provided between VDDA/VSSA pair. Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical characteristics may not be guaranteed below 4.5 V during the voltage drop sequence. 3 200 μF capacitance must be connected between V DDR and VSS12. 4V cannot be used to drive any external component. DD12 5 Each V DD12/VSS12 supply pair should have a 10 μF capacitor. Absolute combined maximum capacitance is 40 μF. 6 VDD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC. 7 100 nF capacitance needs to be provided between each V /V DD SS pair 8V refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and SS VSSMC) unless otherwise noted. 9V DDE_C should not be less than VDDA. 10 Guaranteed by device validation MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 43 Electrical Characteristics 3.2 Thermal Characteristics Table 11. Thermal Characteristics for 144-pin LQFP1 Symbol RθJA RθJA RθJMA RθJMA RθJB RθJCtop ΨJT 1 2 Parameter CC CC CC CC CC CC CC Junction to Ambient Natural Junction to Ambient 2 Conditions Convection2 Single layer board - 1s Four layer board - 2s2p @200 ft./min., single layer board - 1s @200 ft./min., four layer board- 2s2p Value 50 41 41 35 29 10 2 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Junction to Ambient Natural Convection2 Junction to Ambient2 Junction to Board3 Junction to Case 4 Junction to Package Top Natural Convection5 Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Table 12. Thermal Characteristics for 176-pin LQFP1 Symbol RθJA RθJA RθJMA RθJMA RθJB RθJCtop ΨJT 1 2 Parameter CC CC CC CC CC CC CC Junction to Ambient Natural Junction to Ambient Natural Junction to Ambient2 Junction to Ambient2 Junction to Board3 Junction to Case (Top)4 Junction to Package Top Natural Convection5 Convection2 Convection2 Conditions Single layer board - 1s Four layer board - 2s2p @200 ft./min., single layer board - 1s @200 ft./min., Four layer board - 2s2p Value 43 35 35 30 24 9 2 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 44 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.2.1 General Notes for Specifications at Maximum Junction Temperature TJ = TA + (RθJA * PD) Eqn. 1 An estimate of the chip junction temperature, TJ, can be obtained from the equation: where: TA= ambient temperature for the package (oC) RθJA= junction to ambient thermal resistance (oC/W) PD= power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: • • • • Construction of the application board (number of planes) Effective size of the board which cools the component Quality of the thermal and electrical connections to the planes Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: • • • One oz. (35 micron nominal thickness) internal planes Components are well separated Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB * PD) where: TB= board temperature for the package perimeter (oC) RθJB= junction-to-board thermal resistance (oC/W) per JESD51-8S PD= power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RθJA = RθJC + RθCA Eqn. 3 Eqn. 2 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 45 Electrical Characteristics where: RθJA = junction to ambient thermal resistance (oC/W) RθJC= junction to case thermal resistance (oC/W) RθCA= case to ambient thermal resistance (oC/W) RθJC s device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RθCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (ΨJT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT x PD) where: TT= thermocouple temperature on top of the package (oC) ΨJT= thermal characterization parameter (oC/W) PD= power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International Middlefield Rd. CA 94043 805 East Mountain View, (415) 964-5111 Eqn. 4 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 46 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.3 EMI (Electromagnetic Interference) Characteristics Table 13. EMI Testing Specifications1 Value Symbol Parameter min — — — — — — 1 Unit typ TBD TBD TBD TBD TBD TBD max TBD TBD TBD TBD TBD TBD MHz MHz V V dBuV oC SR SR SR SR SR SR Scan Range Operating Frequency VDD12, VDDPLL Operating Voltages VDD, VDDA Operating Voltages Maximum Amplitude Operating Temperature TBD TBD TBD TBD TBD TBD EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. 3.4 3.4.1 Power Management Voltage Regulator Electrical Characteristics The internal voltage regulator requires an external NPN (BCP56 or BCP68) ballast to be connected as shown in Figure 5 as well as an external capacitance (CREG) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 15 nH. For the MPC5606S microcontroller , 10 µF should be placed between each of the three VDD12/VSS12 supply pairs and also between the VDDPLL/VSSPLL pair. Additionally, 200 μF should be placed between the VDDR pin and the adjacent VSS pin. VDDR = 3.0 V to 3.6 V / 4.5 V to 5.5 V, TA = -40 to 105 °C, unless otherwise specified. VDDR VRC_CTRL VDD12 Figure 5. External NPN Ballast Connections MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 47 Electrical Characteristics Table 14. Voltage Regulator Electrical Characteristics1 No. 1 2 3 Symbol VDDR TJ IREG SR Power supply SR Junction temperature CC Current consumption Reference included, @ 55 °C No load @ Full load DC load current Pre-trimming sigma < 7 mV Post-trimming Output voltage (value @ IL = Imax) 6 SR External decoupling/stability capacitor Post-trimming 4 capacitances of 10 µF each ESR of external cap 1 bond wire R + 1 pad R 7 8 LBOND CC Bonding Inductance for Bipolar Base Control pad CC Power supply rejection @ DC @ no load @ 200 kHz @ no load @ DC @ 400 mA @ 200 kHz @ 400 mA 9 CC Load current transient Cload = 10 µF * 4 — Cload = 10 µF * 4 Parameter Conditions Min 3.0 -40 — 2 11 — — 1.270 1.145 10 * 4 0.05 0.2 0 — 0.2 1 15 -30 -100 -30 -30 10% to 90% of IL (max) in 100 ns 500 µs 200 1.330 1.280 — µF ohm ohm nH dB mA V Max 5.5 150 Unit V °C mA 4 5 IL VDD12 CC Output current capacity CC Output voltage (value @ IL = 0 @ 27°C) 10 1 2 tSU CC Start-up time after input supply stabilizes2 Cload = 10 µF * 4 — All values in this table are PRELIMINARY. Time after the input supply to the voltage regulator has ramped up (VDDR) and the voltage regulator has asserted the Power OK signal. 3.4.2 • • • • • Voltage monitor electrical characteristics POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 The device implements a Power On Reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the VDD and the VDD12 voltage while device is supplied: MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 48 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 15. Low voltage monitor electrical characteristics Symbol VPORH VLVDHV3H VLVDHV3L VLVDHV5H VLVDHV5L Parameter CC Power-on reset threshold CC LVDHV3 low voltage detector high threshold CC LVDHV3 low voltage detector low threshold CC LVDHV5 low voltage detector high threshold CC LVDHV5 low voltage detector low threshold Conditions1 Min TA = 25°C, after trimming 1.5 — 2.7 — 4.2 — 1.095 Value2 Unit Typ — — — — — — — Max 2.7 2.8 — 4.37 — 1.185 — V VLVDLVCORH CC LVDLVCOR low voltage detector high threshold VLVDLVCORL CC LVDLVCOR low voltage detector low threshold 1 2 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +105°C, unless otherwise specified All values need to be confirmed during device validation. 3.4.3 Low voltage domain power consumption Table 16 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 16. DC electrical characteristics Symbol IDDMAX IDDRUN 3 Parameter SR Maximum current CC RUN mode current CC WAIT mode current CC HALT mode current CC STOP mode current CC STOP mode current CC STOP mode current Conditions1 Min — — — 4.5 IRC 16 MHz oscillator off HPVREG off IRC 16 MHz oscillator on IRC 16 MHz oscillator off IRC 16 MHz oscillator on — — — — — Value2 Unit Typ — 130 30 — 1.5 800 4 29 300 Max 135 — — 12 — — — — — mA mA mA mA mA µA mA µA µA IDDWAIT IDDHALT IDDSTOP IDDSTOP IDDSTOP IDDSTDBY CC STANDBY mode current IDDSTDBY CC STANDBY mode current 1 2 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +125 °C All values need to be confirmed during device validation. 3 Value is for maximum peripherals turned on. May vary significantly based on different configurations, active peripherals, operating frequency, etc. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 49 Electrical Characteristics 3.5 3.6 3.6.1 • • • DC Electrical Specifications I/O Pad Electrical Characteristics I/O Pad Types Slow pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads provide fast enough transition for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads provide maximum speed. There are used for improved NEXUS debugging capability. The device provides four main I/O pad types depending of the associated alternate functions: Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 3.6.2 I/O Input DC Characteristics Table 17 provides input DC electrical characteristics as described in Figure 6. VIN VDD VIH VHYS VIL VINTERNAL (SIU register) Figure 6. I/O Input DC Electrical Characteristics Definition Table 17. I/O Input DC Electrical Characteristics Symbol VIH VIL VHYS Parameter Conditions1 Min SR Input high level CMOS Schmitt Trigger SR Input low level CMOS Schmitt Trigger CC3 Input hysteresis CMOS Schmitt Trigger 0.65VDD -0.4 0.1VDD Value2 Unit Typ Max VDD+0.4 0.35VDD V MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 50 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C. All values need to be confirmed during device validation. 3 Parameter value guaranteed by design. 1 2 3.6.3 • • • • I/O Output DC Characteristics Table 18 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 19 provides output driver characteristics for I/O pads when in SLOW configuration. Table 20 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 21 provides output driver characteristics for I/O pads when in FAST configuration. Table 18. I/O Pull-up/Pull-down DC Electrical Characteristics Symbol Parameter Conditions1 Min 10 10 Value2 Unit Typ Max — — µA The following tables provide DC characteristics for bidirectional pads: |IWPU| |IWPD| 1 2 CC Weak pull-up current absolute value CC Weak pull-down current absolute value VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified. All values need to be confirmed during device validation. Table 19. SLOW Configuration Output Buffer Electrical Characteristics Symbol VOH Parameter Conditions1 Min CC Output high level SLOW configuration Push Pull, IOH = -2mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOH = -2mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOH = -1mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) VOL CC Output low level SLOW configuration Push Pull, IOL = 2mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOL = 2mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOL = 1mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) 0.8VDD Value2 Unit Typ Max V 0.8VDD VDD-0. 8 0.1VDD V 0.1VDD 0.5 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 51 Electrical Characteristics Table 19. SLOW Configuration Output Buffer Electrical Characteristics (continued) Symbol Ttr Parameter Conditions 1 Value2 Unit Min Typ Max 506 1006 1254 406 506 754 2 mA/ns ns CC4 Output transition time output pin5 CL = 25pF, SLOW configuration VDD = 5.0V ± 10%, ipp_hve = 0 CL = 50pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 100pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 50pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 100pF, VDD = 3.3V ± 10%, ipp_hve = 1 ΔItr50 CC4 Current slew at CL = 50pF SLOW configuration recommended configuration at VDD = 5.0V ± 10%, ipp_hve = 0, VDD = 3.3V ± 10%, ipp_hve = 1 VDD = 5.0V ± 10%, ipp_hve = 1 7 1 2 3 4 5 6 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified All values need to be confirmed during device validation. This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. Data based on characterization results, not tested in production CL calculation should include device and package capacitances (CPKG < 5pF). Data based on simulation results, not tested in production Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics Symbol VOH Parameter Conditions1 Min CC Output high level MEDIUM configuration Push Pull, IOH = -2mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOH = -1mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOH = -1mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) 0.8VDD Value2 Unit Typ Max V 0.8VDD VDD-0.8 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 52 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 20. MEDIUM Configuration Output Buffer Electrical Characteristics (continued) Symbol VOL Parameter Conditions 1 Value2 Unit Min Typ Max 0.1VDD V CC Output low level MEDIUM configuration Push Pull, IOL = 2mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOL = 1mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) 0.1VDD 0.5 Ttr CC4 Output transition time output pin5 MEDIUM configuration CL = 25pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 50pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 100pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 50pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 100pF, VDD = 3.3V ± 10%, ipp_hve = 1 10 20 40 12 25 40 7 ns ΔItr50 CC4 Current slew at CL = 50pF MEDIUM configuration recommended configuration at VDD = 5.0V ± 10%, ipp_hve = 0 VDD = 3.3V ± 10%, ipp_hve = 1 VDD = 5.0V ± 10%, ipp_hve = 1 mA/ns 16 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. 4 Data based on characterization results, not tested in production 5 C calculation should include device and package capacitance (C L PKG < 5pF). 1 2 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 53 Electrical Characteristics Table 21. FAST Configuration Output Buffer Electrical Characteristics Symbol VOH Parameter Conditions1 Min CC Output high level FAST configuration Push Pull, IOH = -14mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOH = -7mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOH = -11mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) VOL CC Output low level FAST configuration Push Pull, IOL = 14mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOL = 7mA, VDD = 5.0V ± 10%, ipp_hve = 13 Push Pull, IOL = 11mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) Ttr CC4 Output transition time output CL = 25pF, pin5 VDD = 5.0V ± 10%, ipp_hve = 0 FAST configuration CL = 50pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 100pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 50pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 100pF, VDD = 3.3V ± 10%, ipp_hve = 1 ΔItr504 CC Current slew at CL = 50pF FAST configuration VDD = 5.0V ± 10%, ipp_hve = 0 (recommended configuration) VDD = 3.3V ± 10%, ipp_hve = 1 (recommended configuration) VDD = 5.0V ± 10%, ipp_hve = 1 1 2 Value2 Unit Typ Max V 0.8VDD 0.8VDD VDD-0.8 0.1VDD V 0.1VDD 0.5 4 6 12 4 7 12 55 40 100 ns mA/n s VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 to +105°C, unless otherwise specified All values need to be confirmed during device validation. 3 This is a transient configuration during power-up. All pads but RESET and NEXUS output (MDOx, EVTO, MCK) are configured in input or in high impedance state. 4 Data based on characterization results, not tested in production 5 C calculation should include device and package capacitance (C L PKG < 5pF). MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 54 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.6.4 I/O Pad Current Specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 22. Table 23 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 22. I/O Supply Segment Supply segment Package 144 LQFP 176 LQFP 1 2 3 4 5 6 A1 pins 1 - 21 pins 113 - 144 pins 1 - 21 pins 143 - 176 B2 pins 22 - 52 pins 22 - 68 C3,4 pins 53 - 72 pins 69 - 88 D5 pins 73 - 102 pins 89 - 118 E6 pins 103 - 112 pins 119 - 142 LCD pad segment containing pad supplies VDDE_A Misc. pad segment containing pad supplies VDDE_B ADC pad segment containing pad supplies VDDE_C ADC VDDA and VDDE_C should be at the same voltage level Stepper Motor pad segment containing I/O supplies VDDMA, VDDMB, VDDMC Misc pad segment containing pad supplies VDDE_E Table 23. I/O Consumption Symbol Parameter Conditions1 Min ISWTSLW CC3 Dynamic I/O current for SLOW configuration CL = 25pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 ISWTMED CC3 Dynamic I/O current for MEDIUM configuration CL = 25pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 ISWTFST3 CC3 Dynamic I/O current for FAST configuration CL = 25pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 Value2 Unit Typ Max 20 16 29 17 110 50 mA mA mA MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 55 Electrical Characteristics Table 23. I/O Consumption (continued) Symbol IRMSSLW Parameter Conditions 1 Value2 Unit Min Typ Max 2.33 3.23 6.64 1.63 2.33 4.74 6.63 13.43 18.34 5.03 8.53 11.04 22.03 mA 33.03 56.04 14.03 20.03 25.04 110 65 70 65 mA mA mA mA CC RMS I/O current for SLOW configuration CL = 25 pF, 2 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 25 pF, 4 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 100 pF, 2 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 CL = 25 pF, 4 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 CL = 100 pF, 2 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 IRMSMED CC Average I/O current for SLOW configuration CL = 25 pF, 2 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 25 pF, 4 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 100 pF, 2 MHz VDD = 5.0 V ± 10%, ipp_hve = 0 CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 CL = 25 pF, 4 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 CL = 100 pF, 2 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 IRMSFST CC Average I/O current for SLOW configuration CL = 25 pF, 2 MHz VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25 pF, 4 MHz VDD = 5.0V ± 10%, ipp_hve = 0 CL = 100 pF, 2 MHz VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25 pF, 2 MHz VDD = 3.3V±10%, ipp_hve = 1 CL = 25 pF, 4 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 CL = 100 pF, 2 MHz VDD = 3.3 V ± 10%, ipp_hve = 1 IDYNSEG SR Sum of all the dynamic and static I/O VDD = 5.0 V ± 10%, ipp_hve = 0 current within a supply segment VDD = 3.3 V ± 10%, ipp_hve = 1 SR Sum of all the static I/O current within VDD = 5.0 V ± 10%, ipp_hve = 0 a supply segment VDD = 3.3 V ± 10%, ipp_hve = 1 IAVGSEG MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 56 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105°C, unless otherwise specified All values need to be confirmed during device validation. 3 Data based on simulation results, not tested in production 4 Data based on characterization results, not tested in production 1 2 3.7 RESET electrical characteristics Figure 7. Start-up reset requirements VDD VDDMIN The device implements a dedicated bidirectional RESET pin. RESET VIH VIL device reset forced by RESET TRSTREM device start-up phase Figure 8. Noise filtering on reset signal VRESET hw_rst VDD ‘1’ VIH VIL ‘0’ filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter WFRST WNFRST unknown reset state device under hardware reset MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 57 Electrical Characteristics Table 24. Reset electrical characteristics Symbol VIH VIL VHYS VOL Parameter Conditions 1 Value2 Unit Min Typ Max VDD+0.4 0.35VDD V V V 0.1VDD V 0.65VDD -0.4 0.1VDD SR Input High Level CMOS Schmitt Trigger SR Input low Level CMOS Schmitt Trigger CC3 Input hysteresis CMOS Schmitt Trigger CC4 Output low level Push Pull, IOL = 2mA, VDD = 5.0V ± 10%, ipp_hve = 0 (recommended) Push Pull, IOL = 1mA, VDD = 5.0V ± 10%, ipp_hve = 15 Push Pull, IOL = 1mA, VDD = 3.3V ± 10%, ipp_hve = 1 (recommended) 0.1VDD 0.5 Ttr CC4 Output transition time output pin6 MEDIUM configuration CL = 25pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 50pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 100pF, VDD = 5.0V ± 10%, ipp_hve = 0 CL = 25pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 50pF, VDD = 3.3V ± 10%, ipp_hve = 1 CL = 100pF, VDD = 3.3V ± 10%, ipp_hve = 1 10 20 40 12 25 40 1000 10 40 - ns WFRST WNFRS T SR RESET Input Filtered Pulse SR RESET Input Not Filtered Pulse CC4 Weak pull-up current absolute value ns ns µA |IWPU| 1 2 3 4 5 6 VDD = 3.3V ± 10% / 5.0V ± 10%, TA = -40 / +105oC, unless otherwise specified All values need to be confirmed during device validation. Data based on characterization results, not tested in production Guaranteed by design simulation. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the reference manual). CL calculation should include device and package capacitance (CPKG < 5pF). MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 58 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.8 Main Oscillator Electrical Characteristics The device provides an oscillator/resonator driver. Figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. EXTAL CL Crystal EXTAL RP XTAL DEVICE VDD CL I R EXTAL XTAL Resonator XTAL DEVICE DEVICE Figure 9. Crystal Oscillator and Resonator Connection Scheme NOTE XTAL/EXTAL must not be directly used to drive external circuits. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 59 Electrical Characteristics VDD VDDMIN VXTAL VXOSCHS 90% VXOSCHSOP 10% TXOSCHSSU valid internal clock 1/fXOSCHS Figure 10. Main Oscillator Electrical Characteristics Table 25. Main Oscillator Electrical Characteristics Symbol fXOSCHS gmXOSCHS Parameter SR Oscillator frequency CC3 Oscillator transconductance VDD = 3.3 V ± 10%, OSCILLATOR_MARGIN = 0 VDD = 5.0 V ± 10%, OSCILLATOR_MARGIN = 0 VDD = 3.3 V ± 10%, OSCILLATOR_MARGIN = 1 VDD = 5.0 V ± 10%, OSCILLATOR_MARGIN = 1 VXOSCHS CC3 Oscillation amplitude fOSC = 4 MHz, VDD = 3.3 V ± 10% fOSC = 16 MHz, VDD = 3.3 V ± 10% fOSC = 4 MHz, VDD = 5.0 V ± 10% fOSC = 16 MHz, VDD = 5.0 V ± 10% VXOSCHSOP CC3 Oscillation operating point VDD = 3.3 V ± 10% VEXTAL VXTAL VDD = 5.0 V ± 10% VEXTAL VXTAL Conditions1 Min 4.0 4.11 3.67 4.93 4.54 2.51 1.68 4.74 3.02 0.894 0.894 0.904 0.904 Value2 Unit Typ — 5.59 5.04 6.70 6.22 — — — — — — — — Max 16.0 7.38 6.73 8.86 8.31 — — — — 1.143 1.146 1.166 1.169 V V MHz mA/V MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 60 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 25. Main Oscillator Electrical Characteristics (continued) Symbol IXOSCHS Parameter CC3 Oscillator consumption Conditions fOSC = 4 MHz fOSC = 16 MHz TXOSCHSSU CC3 Oscillator start-up time fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 VIH VIL 1 2 1 Value2 Unit Min — — — — 0.65VDD -0.4 Typ — — — — Max 2.43 2.52 6.0 1.8 VDD+0.4 0.35VDD V V ms mA SR Input high level CMOS Schmitt Trigger SR Input low level CMOS Schmitt Trigger Oscillator bypass mode Oscillator bypass mode VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Data based on simulation results, not tested in production 3.9 Low Power Oscillator Electrical Characteristics The device provides a low power oscillator/resonator driver. PC[15] CX RF PC[15] Resonator PC[14] CY PC[14] DEVICE Crystal DEVICE Figure 11. Crystal Oscillator and Resonator Connection Scheme NOTE PC[14]/PC[15] must not be directly used to drive external circuits. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 61 Electrical Characteristics VDD VDDMIN VXTAL VXOSCLP 90% 1/fXOSCLP 10% TXOSCLPSU valid internal clock Figure 12. Low Power Oscillator Electrical Characteristics Table 26. Low Power Oscillator Electrical Characteristics Symbol fXOSCLP VXOSCLP Parameter SR Oscillator frequency CC3 Oscillation amplitude VDD=3.3V±10%, VDD=5.0V±10%, IXOSCLP CC3 Oscillator consumption TXOSCLPSU CC3 Oscillator start-up time VIH VIL 1 Conditions1 Min 32 1.12 1.12 Value2 Unit Typ 1.33 1.37 Max 40 1.74 1.74 5 2 µA s V V kHz V SR Input high level CMOS Schmitt Trigger SR Input low level CMOS Schmitt Trigger Oscillator bypass mode 0.65VDD Oscillator bypass mode -0.4 VDD+0.4 0.35VDD VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified All values need to be confirmed during device validation. 3 Granted by device validation 2 3.10 FMPLL Electrical Characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 62 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 27. FMPLL Electrical Characteristics Symbol fPLLIN ΔPLLIN Parameter Conditions1 Min SR PLL reference clock3 SR PLL reference clock duty cycle 4 3 Value2 Unit Typ Max 64 60 64 645 MHz % MHz MHz µs ps ns mA 4 40 16 fPLLOUT CC fCPU TLOCK ΔTLTJIT IPLL 1 2 3 4 5 6 PLL output clock frequency CC4 System clock frequency CC4 PLL lock time 4 4 Stable oscillator (fPLLIN = 16 MHz) fPLLIN = 16 MHz (resonator) fPLLIN = 16 MHz (resonator) TA = 25°C 200 500 1.5 4 ΔTPKJIT CC CC PLL jitter (pk to pk) PLL long term jitter CC6 Oscillator consumption VDDPLL = 1.2 V ± 10%, TA = -40 to +105 °C, unless otherwise specified. All values need to be confirmed during device validation. PLLIN clock retrieved directly from XOSCHS clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and ΔPLLIN. Data based on device simulation. fCPU 64 MHz can be achieved only at up to 105 °C Data based on characterization results, not tested in production 3.11 Main RC Oscillator Electrical Characteristics Table 28. Main RC Oscillator Electrical Characteristics Symbol fRCM IRCMRUN IRCMPWD Parameter CC3 RC oscillator high frequency CC3 RC oscillator high frequency current in running mode Conditions1 Min TA = 25 °C, trimmed TA = 25 °C, trimmed Value2 Unit Typ 16 200 10 -1 -5 +1 +5 Max MHz µA µA % % The device provides a 16 MHz internal RC oscillator. This is used as the default clock at the power-up of the device. CC3 RC oscillator high frequency current in power TA = 25 °C down mode CC3 RC oscillator precision after trimming of fRC TA = 25 °C ΔRCMTRI M ΔRCMVAR CC4 RC oscillator variation in temperature and supply with respect to fRC at TA = 55 °C in high-frequency configuration VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Guaranteed by device simulation, not tested in production 4 Guaranteed by device characterization, not tested in production 2 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 63 Electrical Characteristics 3.12 Low Power RC Oscillator Electrical Characteristics Table 29. Low Power RC Oscillator Electrical Characteristics Symbol fRCL IRCL 3 The device provides a low power internal RC oscillator. This can be used as the reference clock for the RTC module. Parameter Conditions 1 Value2 Unit Min Typ 128 5 -2 -10 +2 +10 Max kHz µA % % CC3 RC oscillator low frequency CC RC oscillator low frequency current 3 TA = 25 °C, trimmed TA = 25 °C, trimmed ΔRCLTRIM CC3 RC oscillator precision after trimming of fRCL TA = 25 °C High frequency ΔRCLVAR CC RC oscillator variation in temperature and supply with respect to fRC at TA = 55 °C in high configuration frequency configuration 3 1 2 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified. All values need to be confirmed during device validation. 3 Guaranteed by device simulation, not tested in production 3.13 Flash Memory Electrical Characteristics Table 30. Program and Erase Specifications Symbol Tdwprogram T16kpperase T32kpperase T128kpperase Parameter Double Word (64 bits) Program Time4 16 KB Block Pre-program and Erase Time 32 KB Block Pre-program and Erase Time 128 KB Block Pre-program and Erase Time Min Value Typical Value1 — — — — Initial Max2 22 500 600 1300 Max3 500 5000 5000 7500 Unit μs ms ms ms Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization. 2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage. 3 The maximum program & erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 64 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 31. Flash Module Life Value Symbol P/E Parameter Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 32 Kbyte blocks over the operating temperature range (TJ) Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (TJ) Conditions Min — 100,000 Typ — cycles Unit P/E — 10,000 100,000 (TBD) 100,000 (TBD) — — — cycles P/E — 1,000 cycles Retention Minimum data retention at 85 °C average ambient temperature1 Blocks with 0 - 1,000 P/E cycles Blocks with 10,000 P/E cycles Blocks with 100,000 P/E cycles 20 10 1-5 (TBD) years years years 1 Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. 3.14 Analog to Digital Converter (ADC) Electrical Characteristics The device provides a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 65 Electrical Characteristics Offset Error OSE 1023 Gain Error GE 1022 1021 1020 1019 1 LSB ideal = VDDA / 1024 1018 (2) code out 7 (1) 6 5 (5) 4 (4) 3 (3) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE Figure 13. ADC Characteristics and Error Definitions 3.14.1 Input Impedance and ADC Accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 66 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330kΩ is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 5: Eqn. 5 R S + R F + R L + R SW + R AD -1 V A • -------------------------------------------------------------------------- < -- LSB R EQ 2 Equation 5 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 14. Input Equivalent Circuit (Precise Channels) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 67 Electrical Characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Channel Selection RSW1 Extended Switch RSW2 Sampling Source RS Filter RF Current Limiter RL RAD VA CF CP1 CP3 CP2 CS RS RF CF RL RSW RAD CP CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance Figure 15. Input Equivalent Circuit (Extended Channels) A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 14): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). VCS VA VA2 Voltage Transient on CS ΔV < 0.5 LSB 1 2 τ1 < (RSW + RAD) CS 2048 • C S 3.14.2 ADC Electrical Characteristics MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 70 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 32. ADC Electrical Characteristics Symbol VSSA Parameter Conditions1 Min SR Voltage on VSSA (ADC reference) pin with respect to ground (VSS)3 SR Voltage on VDDA pin (ADC reference) with respect to ground (VSS) SR Analog input voltage4 SR ADC analog frequency -0.1 Value2 Unit Typ Max 0.1 V VDDA VDD-0.1 VDD+0.1 V VAINx fADC VSSA-0.1 6 VDDA+0.1 32 1.5 V MHz µs µs tADC_PU SR ADC power up delay tADC_S CC5 Sample time6 fADC = 32 MHz, ADC_conf_sample_input = 17 fADC = 6 MHz, ADC_conf_sample_input = 127 tADC_C CC5 Conversion time7 CS CP1 CP2 CP3 RSW1 RSW2 RAD IINJ CC5 ADC input sampling capacitance CC5 ADC input pin capacitance 1 CC5 ADC input pin capacitance 2 CC5 ADC input pin capacitance 3 CC5 Internal resistance of analog source CC5 Internal resistance of analog source CC5 Internal resistance of analog source SR Input current Injection Current injection on one ADC input, different from the converted one No overload -10 fADC = 32 MHz, ADC_conf_comp = 2 0.625 0.5 21 µs 3 3 1 1 3 2 0.1 10 pF pF pF pF kΩ kΩ kΩ mA INL DNL OFS GNE CC5 Integral Non Linearity -1.5 -1.0 -1.0 -1.0 1.5 1.0 1.0 1.0 LSB LSB LSB LSB CC5 Differential Non Linearity No overload CC Offset error CC5 Gain error 5 After offset cancellation MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 71 Electrical Characteristics Table 32. ADC Electrical Characteristics (continued) Symbol TUEP Parameter Conditions 1 Value2 Unit Min Typ Max 2 LSB LSB -3 3 LSB LSB -2 CC5 Total Unadjusted Error for No overload precise channels, input overload conditions on only pins adjacent channel CC5 Total Unadjusted Error for No overload extended channel, overload conditions on adjacent channel TUEX 1 2 3 4 5 6 7 VDDA = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to +105 °C, unless otherwise specified. All values need to be confirmed during device validation. Analog and digital VSS must be common (to be tied together externally). VAINx may exceed VSSA and VDDA limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF Guaranteed by design During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result’s register with the conversion result. 3.15 3.15.1 AC Specifications Pad AC Specifications Table 33. Pad AC specifications (5.0 V, IPP_HVE=1)1 Tswitchon1 (ns) Min 1 Slow 1.5 1.5 1.5 1.5 2 Medium 1 1 1 1 Typ Max 30 30 30 30 15 15 15 15 Rise/Fall2 (ns) Min 6 9 12 16 3 5 9 12 Typ Max 50 100 125 150 10 20 40 70 Frequency (MHz) Min Typ Max 4 2 2 2 40 20 13 7 Current slew3 (mA/ns) Min 0.04 0.04 0.04 0.04 2.5 2.5 2.5 2.5 Typ Max 2 2 2 2 7 7 8 8 25 50 100 200 25 50 100 200 Load drive (pF) Num Pad MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 72 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Table 33. Pad AC specifications (5.0 V, IPP_HVE=1)1 (continued) Tswitchon1 (ns) Min 3 Fast 1 1 1 1 4 5 1 2 Num Pad Rise/Fall2 (ns) Min 1 1.5 3 5 1 Typ Max 4 6 12 16 4 5000 Frequency (MHz) Min Typ Max 100 80 40 25 50 - Current slew3 (mA/ns) Min 18 18 18 18 10 Typ Max 55 55 55 55 25 - Load drive (pF) 25 50 100 200 25 50 Typ - Max 6 6 6 6 5 - Symmetric Pull Up/Down (5.5 V max) 1 - Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition Slope at rising/falling edge 3 Data based on characterization results, not tested in production Table 34. Pad AC specifications (3.3 V, IPP_HVE=0)1 Tswitchon1 (ns) Min 1 Slow 3 3 3 3 2 Medium 1 1 1 1 3 Fast 1 1 1 1 4 5 1 2 Num Pad Rise/Fall2 (ns) Min 4 6 10 14 2 4 8 14 1 1.5 3 5 2 Typ Max 40 50 75 100 12 25 40 70 4 7 12 18 6 7500 Frequency (MHz) Min Typ Max 4 2 2 2 40 20 13 7 72 55 40 25 50 - Current slew3 (mA/ns) Min 0.01 0.01 0.01 0.01 2.5 2.5 2.5 2.5 3 3 3 3 3 Typ Max 2 2 2 2 7 7 7 7 40 40 40 40 25 - Load drive (pF) 25 50 100 200 25 50 100 200 25 50 100 200 25 50 Typ - Max 40 40 40 40 15 15 15 15 6 6 6 6 6 - Symmetric Pull Up/Down (3.6 V max) 1 - Propagation delay from VDD/2 of internal signal to Pchannel/Nchannel on condition Slope at rising/falling edge 3 Data based on characterization results, not tested in production MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 73 Electrical Characteristics VDD/2 Pad Data Input Rising Edge Output Delay Falling Edge Output Delay VOH Pad Output VOL Figure 18. Pad Output Delay 3.16 3.16.1 Num 1 2 3 4 5 6 7 8 9 10 11 12 13 1 AC Timing IEEE 1149.1 Interface Timing Table 35. JTAG Interface Timing1 Symbol tJCYC tJDC tTCKRISE tTMSS, tTDIS tTMSH, tTDIH tTDOV tTDOI tTDOHZ tBSDV tBSDVZ tBSDHZ tBSDST tBSDHT CC2 TCK Cycle Time CC2 TCK Clock Pulse Width (Measured at VDD/2) Characteristic Min 100 40 — 5 25 — 0 — — — — 50 50 Max — 60 3 — — 35 — 30 35 50 50 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns CC2 TCK Rise and Fall Times (40% – 70%) CC2 CC2 CC2 TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid CC2 TCK Low to TDO Data Invalid CC2 CC2 CC 2 TCK Low to TDO High Impedance TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance CC2 TCK Falling Edge to Output High Impedance CC2 Boundary Scan Input Valid to TCK Rising Edge CC2 TCK Rising Edge to Boundary Scan Input Invalid These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 3.0 V to 5.5 V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b11. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 74 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 2 Parameter values guaranteed by design. TCK 2 3 2 1 3 Figure 19. JTAG Test Clock Input Timing TCK 4 5 TMS, TDI 6 7 8 TDO Figure 20. JTAG Test Access Port Timing MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 75 Electrical Characteristics TCK 9 11 Output Signals 10 Output Signals 12 13 Input Signals Figure 21. JTAG Boundary Scan Timing MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 76 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.16.2 Num 1 2 3 4 5 6 7 8 9 10 11 12 1 Nexus Debug Interface Table 36. Nexus Debug Port Timing1 Symbol tMCYC tMDC tMDOV tMSEOV tEVTOV tEVTIPW tEVTOPW tTCYC tTDC tNTDIS, tNTMSS tNTDIH, tNTMSH tJOV CC2 CC CC 2 2 Characteristic MCKO Cycle Time MCKO Duty Cycle MCKO Low to MDO Data Valid 3 Min 22 40 –2 –2 –2 4 1 100 40 25 5 0 Max — 60 14 14 14 — — — 60 — — 35 Unit ns % ns ns ns tTCYC tMCYC ns % ns ns ns CC2 CC CC 2 2 MCKO Low to MSEO Data Valid3 MCKO Low to EVTO Data Valid EVTI Pulse Width EVTO Pulse Width TCK Cycle Time4 TCK Duty Cycle TDI, TMS Data Setup Time TDI, TMS Data Hold Time TCK Low to TDO Data Valid 3 CC2 CC2 CC2 CC2 CC2 CC2 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 5.5V, TA = -40 to 105 °C, and CL = 50 pF (Cl=30 pF on MCKO), with SRC = 0b11. 2 Parameter values guaranteed by design. 3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 4 The system clock frequency needs to be three times faster that the TCK frequency. Figure 22. Nexus Clock Timing 1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid Figure 23. Nexus Output Timing MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 77 Electrical Characteristics TCK 9 8 9 Figure 24. Nexus TCK Timing TCK 10 11 TMS, TDI 12 TDO Figure 25. Nexus TDI, TMS, TDO Timing 3.16.3 • Interface to TFT LCD Panels Figure 26 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with positive polarity. The sequence of events for active matrix interface timing is: DCU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DCU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 78 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics • • • DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse. DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. DCU_VSYNC DCU_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n DCU_HSYNC DCU_DE 1 DCU_CLK 2 3 m-1 m DCU_LD[23:0] Figure 26. TFT LCD InterfaceTiming Overview1 3.16.3.1 Interface to TFT LCD Panels—Pixel Level Timings Figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal (meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL register, whether active-high or active-low. The default is active-high. The DCU_DE signal is always active-high. Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU Clock Confide Register (DCCR) in the system clock module. The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the VSYN_PARA register. Table 37. LCD Interface Timing Parameters—Horizontal and Vertical Num 1 2 3 4 5 Symbol tPCP tPWH tBPH tFPH tSW CC1 CC1 CC1 CC1 CC1 Characteristic Display pixel clock period HSYNC pulse width HSYNC back porch width HSYNC front porch width Screen width Value 31.25 PW_H * tPCP BP_H * tPCP FP_H * tPCP DELTA_X * tPCP Unit ns ns ns ns ns 1. In Figure 26, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and DCU_B[0:7]. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 79 Electrical Characteristics Table 37. LCD Interface Timing Parameters—Horizontal and Vertical (continued) Num 6 7 8 Symbol tHSP tPWV tBPV tFPV tSH tVSP 1 Characteristic 1 Value (PW_H + BP_H + FP_H + DELTA_X ) * tPCP PWV * tHSP BP_V * tHSP FP_V * tHSP DELTA_Y * tHSP (PW_V + BP_V + FP_V + DELTA_Y ) * tHSP Unit ns ns ns ns ns ns CC HSYNC (line) period VSYNC pulse width VSYNC back porch width VSYNC front porch width Screen height VSYNC (frame) period CC1 CC1 CC1 CC 1 CC1 Parameter values guaranteed by design. tHSP Start of line tPWH tPCP DCU_CLK tBPH tSW tFPH DCU_LD[23:0] Invalid Data 1 2 3 DELTA_X Invalid Data DCU_HSYNC DCU_DE Figure 27. Horizontal Sync Timing tVSP Start of Frame tPWV tHCP DCU_HSYNC tBPV tSH tFPV DCU_LD[23:0] (Line Data) Invalid Data 1 2 3 DELTA_Y Invalid Data DCU_HSYNC DCU_DE Figure 28. Vertical Sync Pulse MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 80 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.16.3.2 Interface to TFT LCD Panels—Access Level Table 38. LCD Interface Timing Parameters1,2,3,4—Access Level Num 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 Symbol tCKP tCHD tDSU tDHD tCSU tCHD CC5 CC5 CC 5 Characteristic PDI Clock Period Duty cycle interface data setup time PDI interface data access hold time PDI interface control signal setup time PDI interface control signal hold time TFT interface data valid after pixel clock TFT interface HSYNC valid after pixel clock TFT interface VSYNC valid after pixel clock TFT interface DE valid after pixel clock TFT interface hold time for data and control bits Relative skew between the data bits Min. Value 31.25 40 6 1 3 1 Typical Value — — — — — — — — — — Max. Value Unit ns 60 % ns ns ns ns CC5 CC5 CC5 CC 5 6 5 5.5 5.6 ns ns ns ns ns CC5 CC5 CC5 CC5 CC5 2 — — 3.7 ns The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve edge Intra bit skew is less than 2 ns Load CL = 50 pf for frequency up to 20 MHz Load CL = 25 pf for display freq from 20 to 32 MHz Parameter values guaranteed by design. tCHD DCU_HSYNC DCU_VSYNC DCU_DE tCSU DCU_CLK tCKH tCKL tDSU tDHD DCU_LD[23:0] Figure 29. LCD Interface Timing Parameters—Access Level 3.16.4 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Timing MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 81 Electrical Characteristics Table 39. IRQ and NMI Timing Num 1 2 3 1 2 Symbol tIPWL tIPWH tICYC Characteristic Min. Value 200 200 400 Max. Value — — — Unit ns ns ns CC1 IRQ/NMI Pulse Width Low CC1 IRQ/NMI Pulse Width High CC1 IRQ/NMI Edge to Edge Time2 Parameter values guaranteed by design. Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both. 1,2 3 1,2 Figure 30. IRQ and NMI Timing 3.16.5 Enhanced Modular I/O Subsystem (eMIOS) Timing Table 40. eMIOS Timing1 Min. Value2 4 1 Max. Value — — Num 1 2 1 Symbol tMIPW tMOPW Characteristic Unit tCYC tCYC CC3 eMIOS Input Pulse Width CC3 eMIOS Output Pulse Width eMIOS timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b00 2 There is no limitation on the peripheral for setting the minimum pulse width, the actual width is restricted by the pad delays. Refer to the pad specification section for the details. 3 Parameter values guaranteed by design. 3.16.6 FlexCAN Timing The CAN functions are available as TX pins at normal IO pads and as RX pins at the always on domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup if configured. Table 41. FlexCAN Timing1 Num 1 2 Symbol tCANOV tCANSU Characteristic Min. Value — — Max. Value 22.48 12.46 Unit ns ns CC2 CTNX Output Valid after CLKOUT Rising Edge (Output Delay) CC2 CNRX Input Valid to CLKOUT Rising Edge (Setup Time) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 82 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 1 FlexCAN timing specified at fSYS = 64 MHz, VDD12 = 1.14 V to 1.32 V, VDDE_x = 3.0 V to 5.5 V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b00. 2 Parameter values guaranteed by design. 3.16.7 Num 1 2 3 4 5 6 7 Deserial Serial Peripheral Interface (DSPI) Table 42. DSPI Timing1 Symbol tSCK tCSC tASC tSDC tA tDIS tSUI CC2 CC CC 2 2 Characteristic SCK Cycle TIme3,4 PCS to SCK Delay After SCK Delay SCK Duty Cycle Slave Access Time (PCSx active to SOUT driven) Slave SOUT Disable Time (PCSx inactive to SOUT High-Z or invalid) Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA=0) Master (MTFE = 1, CPHA=1) Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) 6 5 Min 60 20 tSCK/2 –2ns — — Max — — — tSCK/2 + 2ns Unit ns ns ns ns ns ns CC2 CC2 CC2 CC2 25 25 35 5 5 35 –4 10 26 –4 — — — — –15 5.5 0 –15 — — — — — — — — 15 35 30 15 — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 tHI CC2 9 tSUO CC2 10 tHO CC2 1 2 3 4 5 6 7 DSPI timing specified at VDDE_x = 3.0 V to 5.5V, TA = -40 to 105 °C, and CL = 50 pF with SRC = 0b11. Parameter values guaranteed by design. The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. The actual minimum SCK Cycle Time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK], program PSSCK=2 & CSSCK = 2 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC] This delay value is corresponding to SMPL_PT=00b which is bit field 9 and 8 of DSPI_MCR register. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 83 Electrical Characteristics 2 PCSx 4 SCK Output (CPOL=0) 4 1 3 SCK Output (CPOL=1) 7 SIN 8 Data 10 SOUT First Data Data Last Data 9 Last Data First Data Figure 31. DSPI Classic SPI Timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) 8 SCK Output (CPOL=1) 7 SIN First Data 10 SOUT First Data Data Data Last Data 9 Last Data Figure 32. DSPI Classic SPI Timing — Master, CPHA = 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 84 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 2 PCSx 1 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 7 SIN 8 Data 10 Data 9 4 3 6 Last Data First Data Last Data Figure 33. DSPI Classic SPI Timing — Slave, CPHA = 0 PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 9 10 First Data 7 8 Data Last Data Data Last Data 6 SIN First Data Figure 34. DSPI Classic SPI Timing — Slave, CPHA = 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 85 Electrical Characteristics 3 PCSx 4 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 7 SIN First Data 10 SOUT First Data Data Data 9 Last Data Last Data 4 1 8 Figure 35. DSPI Modified Transfer Format Timing — Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 7 SIN First Data Data 10 SOUT First Data Data 8 Last Data 9 Last Data Figure 36. DSPI Modified Transfer Format Timing — Master, CPHA = 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 86 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics PCSx 2 1 3 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 7 SIN First Data Data Data 9 10 Last Data 8 Last Data 6 4 Figure 37. DSPI Modified Transfer Format Timing — Slave, CPHA = 0 PCSx SCK Input (CPOL=0) SCK Input (CPOL=1) 5 SOUT 9 10 First Data 7 8 Data Last Data Data Last Data 6 SIN First Data Figure 38. DSPI Modified Transfer Format Timing — Slave, CPHA = 1 MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 87 Electrical Characteristics 3.16.8 Num 1 2 4 6 7 8 9 1 2 I2C Timing Table 43. I2C Input Timing Specifications—SCL and SDA Symbol — — — — — — — Characteristic Min. Value 2 8 0.0 4 0.0 2 2 Max. Value — — — — — — — Unit IP-Bus Cycle2 IP-Bus Cycle2 ns IP-Bus Cycle2 ns IP-Bus Cycle2 IP-Bus Cycle2 CC1 Start condition hold time CC1 Clock low time CC1 Data hold time CC1 Clock high time CC1 Data setup time CC 1 Start condition setup time (for repeated start condition only) CC1 Stop condition setup time Parameter values guaranteed by design. Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device Table 44. I2C Output Timing Specifications—SCL and SDA Num 11 21 34 41 51 6 1 Symbol — — — — — — — — — Characteristic Min. Value 6 10 — 7 — 10 2 20 10 Max. Value — — 99.6 — 99.5 — — — — Unit IP-Bus Cycle3 IP-Bus Cycle2 ns IP-Bus Cycle2 ns IP-Bus Cycle2 IP-Bus Cycle2 IP-Bus Cycle2 IP-Bus Cycle2 CC2 Start condition hold time CC2 Clock low time CC2 SCL/SDA rise time CC2 Data hold time CC2 SCL/SDA fall time CC2 Clock high time 71 81 91 1 CC2 Data setup time CC2 Start condition setup time (for repeated start condition only) CC2 Stop condition setup time Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Parameter values guaranteed by design. 3 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device 4 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 88 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 2 6 5 SCL 1 SDA 4 7 8 3 9 Figure 39. I2C Input/Output Timing 3.16.9 Mechanical Outline Drawings 3.17 144 LQFP MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 89 Electrical Characteristics Figure 40. LQFP144 Mechanical Drawing (Part 1 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 90 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Figure 41. LQFP144 Mechanical Drawing (Part 2 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 91 Electrical Characteristics Figure 42. LQFP144 Mechanical Drawing (Part 3 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 92 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics 3.18 176 LQFP Figure 43. LQFP176 Mechanical Drawing (Part 1 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 93 Electrical Characteristics Figure 44. LQFP176 Mechanical Drawing (Part 2 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 94 Preliminary—Subject to Change Without Notice Freescale Semiconductor Electrical Characteristics Figure 45. LQFP176 Mechanical Drawing (Part 3 of 3) MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 95 Ordering Information 4 Ordering Information Table 45. Orderable Part Number Summary Part Number Flash/SRAM Package 144 LQFP 144 LQFP 144 LQFP 144 LQFP 176 LQFP Speed (MHz) 64 64 64 64 64 Table 45 shows the orderable part numbers for the MPC5606S series. MPC5602SEMLQ 256 KB/24 KB MPC5604SEMLQ 512 KB/48 KB MPC5604SEMLQ 512 KB/48 KB MPC5606SEMLQ MPC5606SEMLU 1 1 MB/48 KB 1 MB/48 KB 1 1 Device also includes 160 KB of graphics SRAM. Figure 46. Commercial product code structure Example code: Qualification Status PowerPC Core Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Temperature spec. Package Code R = Tape & Reel (blank if Tray) M PC 56 0 4 S E M LL R Qualification Status M = MC status S = Auto qualified P = PC status Flash Size (z0 core) 2 = 256 KB 4 = 512 KB 6 = 1024 KB Temperature spec. C = –40° C to 85°C V = –40° C to 105°C M = –40° C to 125°C Automotive Platform 56 = PPC in 90nm 57 = PPC in 65nm Product B = Body C = Gateway Package Code LQ = 144 LQFP LU = 176 LQFP MG = 208 MAPBGA1 1 208 MAPBGA available only as development package for Nexus2+ MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 96 Preliminary—Subject to Change Without Notice Freescale Semiconductor Ordering Information MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1 Freescale Semiconductor Preliminary—Subject to Change Without Notice 97 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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