TBD

Freescale Semiconductor Data Sheet: Product Preview Document Number: MSC8144E Rev. 6, 12/2007 MSC8144E FC-PBGA–783 29 mm × 29 mm Quad Core Digital Signal Processor • Four StarCore™ SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes. • Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets. • 128 Kbyte L2 shared instruction cache. • 512 Kbyte M2 memory for critical data and temporary data buffering. • 10 Mbyte 128-b8t wide M3 memory. • 96 Kbyte boot ROM. • Three input clocks (shared, global, and differential). • Four PLLs (system, core, global, and serial RapidIO). • Security Engine (SEC0 optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP using 4 crypto-channels with multi-command chains, integrated controller for assignment of the six execution units (PKEU, DEU, AESU, AFEU, MDEU, and KEU0) and the random number generator (RNG), and XOR engine to accelerate parity checking for RAID storage applications. • DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2. • DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration. • Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • QUICC Engine™ technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three communication controllers with one ATM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores. – The two Ethernet controllers support 10/100/1000 Mbps operations via MII/RMII/SMII/RGMII/SGMII and the SGMII protocol using a 4-pin SerDes interface at 1000 Mbps data rate only. – The ATM controller supports UTOPIA level II 8/16 bits at 25/50 MHz in UTOPIA/POS mode with adaptation layer support AAL0, AAL2, and AAL5. PCI designed to comply with the PCI specification revision 2.2 at 33 MHz or 66 MHz with access to all PCI address spaces. Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2 of the RapidIO trade association, and supports read, write, messages, doorbells, and maintenance accesses in inbound mode, and messages and doorbells in outbound mode. I/O interrupt concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes them to INT_OUT, NMI_OUT, and the cores. UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. Serial peripheral interface (SPI). Four timer modules, each with four configurable16-bit timers. Four software watchdog timer (SWT) modules. Up to 32 general-purpose input/output (GPIO) ports, 16 of which can be configured as maskable interrupt inputs. I2C interface that allows booting from EEPROM devices. Eight programmable hardware semaphores. Thirty two virtual maskable interrupts and one virtual NMI that can be generated by a simple write access. Optional booting via serial RapidIO port, PCI, I2C, SPI, or Ethernet interfaces. • • • • • • • • • • • • Note: This document supports mask set M31H. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2007. All rights reserved. Table of Contents 1 2 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4 1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4 1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27 2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .27 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28 2.5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29 2.7 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .64 3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64 3.2 Power Supply Design Considerations. . . . . . . . . . . . . .65 3.3 Clock and Timing Signal Board Layout Considerations 65 3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66 3.5 External DDR SDRAM Selection . . . . . . . . . . . . . . . . .74 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Figure 12.Differential VPP of Transmitter or Receiver . . . . . . . . . . 42 Figure 13.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 45 Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 47 Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 48 Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 17.PCI Input AC Timing Measurement Conditions . . . . . . . 50 Figure 18.PCI Output AC Timing Measurement Condition . . . . . . 50 Figure 19.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 24.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 25.MII Management Interface Timing . . . . . . . . . . . . . . . . . 54 Figure 26.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 27.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 56 Figure 30.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . 58 Figure 33.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . . 59 Figure 34.ATM/UTOPIAPOS AC Timing (External Clock) . . . . . . . 59 Figure 35.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 36.SPI AC Timing in Slave Mode (External Clock). . . . . . . 60 Figure 37.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 61 Figure 38.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . . 61 Figure 39.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 40.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 62 Figure 41.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 42.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 43.VDDM3, VDDM3IO and V25M3 Power-on Sequence . . . . . 64 Figure 45.MSC8144E Mechanical Information, 783-ball FC-PBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3 4 5 6 7 List of Figures MSC8144E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3 StarCore SC3400 DSP Core Subsystem Block Diagram 3 MSC8144E FC-PBGA Package, Top View . . . . . . . . . . . 4 MSC8144E FC-PBGA Package, Bottom View . . . . . . . . 5 SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31 Overshoot/Undershoot Voltage for VIH and VIL. . . . . . . 34 Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 8. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38 Figure 9. Timing for tDDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41 Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 2 Freescale Semiconductor DDR Interface 16/32-bit at 400 MHz data rate 512 Kbytes M2 Memory 10 Mbytes M3 Memory 128-bit at 400 MHz CLASS QUICC Engine™ Subsystem Dual RISC Processors Ether- Ethernet ATM SPI net DDR Controller I/O-Interrupt Concentrator UART Clocks Timers Reset Four DSP Subsystems Ser. RapidIO Subsystem Semaphores Virtual Interrupts Boot ROM I2C Other Modules Security Engine Core 8 TDMs DMA 128 Kbyte L2 ICache PCI RMU SRIO JTAG Eight TDMs 256-Channels each 10/100/1000 Mbps 10/100/1000 Mbps SPI 16-bit/8-bit UTOPIA 1x/4x PCI 32-bit 33/66 MHz Note: The arrow direction indicates master or slave. Figure 1. MSC8144E Block Diagram Two Internal Buses (128 bits wide each) Interrupts Bus Interface IQBus TWB DQBus EPIC Timer Task Protection Debug Support OCE30 DPU Instruction Cache WriteThrough Buffer Data Cache WriteBack Buffer Address Translation MMU (WTB) (WBB) SC3400 Core P-bus Xa-bus Xb-bus Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 3 Pin Assignments and Reset States 1 Pin Assignments and Reset States This section includes diagrams of the MSC8144E package ball grid array layouts and tables showing how the pinouts are allocated for the package. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MSC8144E Figure 3. MSC8144E FC-PBGA Package, Top View MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 4 Freescale Semiconductor Bottom View AH AG AF AE AD AC AB AA Y W V U R P N M L K J H G F E D C B A 1 2 3 4 5 Figure 4. MSC8144E FC-PBGA Package, Bottom View MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 5 MSC8144E 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 T 1.2 Signal List By Ball Location Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The specified reference supply must be tied to the voltage level specified in this document if any of the related signal functions are used (active). Table 1. Signal List by Ball Number Ball Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 B1 B2 B3 B4 B5 B6 B7 B8 B9 GND GE2_RX_ER/PCI_AD31 VDDGE2 GE2_RX_DV/PCI_AD30 GE2_TD0/PCI_CBE0 SRIO_IMP_CAL_RX Reserved1 Reserved 1 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND Ethernet 2 PCI Ethernet 2 VDDGE2 VDDGE2 Ethernet 2 Ethernet 2 PCI PCI Ethernet 2 Ethernet 2 VDDGE2 VDDGE2 VDDSXC — — — — VDDSXC VDDSXC VDDSXC VDDSXC VDDSXC GNDRIOPLL GNDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC VDDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC VDDSXC VDDSXP VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — Ethernet 2 Ethernet 2 PCI PCI Ethernet Ethernet 2 Ethernet 2 VDDGE2 VDDGE2 VDDGE2 GND Ethernet VDDGE2 GNDSXC — — Reserved1 Reserved1 SRIO_RXD0 VDDSXC SRIO_RXD1 VDDSXC SRIO_REF_CLK VDDRIOPLL GNDSXC SRIO_RXD2/ GE1_SGMII_RX VDDSXC SRIO_RXD3/ GE2_SGMII_RX VDDSXC SRIO_IMP_CAL_TX MDQ28 MDQ29 MDQ30 MDQ31 MDQS3 Reserved1 GE2_TD1/PCI_CBE1 GE2_TX_EN/PCI_CBE2 GE_MDIO GND GE_MDC GNDSXC Reserved1 Reserved 1 MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 6 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply — — VDDSXC GNDSXC VDDSXC GNDSXC VDDSXC — VDDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC GNDSXC SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC GNDSXC GNDSXP VDDDDR VDDDDR GND VDDDDR VDDDDR — Ethernet 2 PCI Ethernet 2 VDDGE2 VDDGE2 TDM TDM PCI PCI Ethernet 2 Ethernet 2 UTOPIA UTOPIA VDDGE2 VDDGE2 VDDGE2 Ethernet 2 PCI Ethernet 2 VDDGE2 — — — — VDDSXP VDDSXP VDDSXP VDDSXP GNDSXC GNDRIOPLL — VDDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP Signal Name Reserved1 Reserved1 SRIO_RXD0 GNDSXC SRIO_RXD1 GNDSXC SRIO_REF_CLK Reserved1 VDDSXC SRIO_RXD2/ GE1_SGMII_RX GNDSXC SRIO_RXD3/ GE2_SGMII_RX GNDSXC GNDSXP MDQ27 VDDDDR GND VDDDDR MDQS3 Reserved1 GE2_RX_CLK/PCI_AD29 VDDGE2 TDM7RSYN/GE2_TD2/ PCI_AD2/UTP_TER TDM7RCLK/GE2_RD2/ PCI_AD0/UTP_RVL VDDGE2 GE2_RD0/PCI_AD27 Reserved1 Reserved 1 Reserved1 Reserved1 VDDSXP SRIO_TXD0 VDDSXP SRIO_TXD1 GNDSXC GNDRIOPLL Reserved1 VDDSXP SRIO_TXD2/GE1_SGMII_T X MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 7 Table 1. Signal List by Ball Number (continued) Ball Number C21 C22 C23 C24 C25 C26 C27 C28 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 E1 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP VDDSXP VDDDDR VDDDDR VDDDDR GND VDDDDR — Ethernet 2 PCI Ethernet 2 VDDGE2 GND TDM TDM UTOPIA TDM Ethernet 1 PCI PCI PCI PCI UTOPIA Ethernet 2 Ethernet 2 UTOPIA UTOPIA VDDGE2 VDDGE2 VDDGE1 VDDGE2 — — — — GNDSXP VDDSXP GNDSXP VDDSXP VDDSXC — — GNDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP GNDSXP SGMII support on SERDES is enabled by Reset Configuration Word VDDSXP GNDSXP VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — Signal Name VDDSXP SRIO_TXD3/GE2_SGMII_T X VDDSXP MDQ26 MDQ25 MDM3 GND MDQ24 Reserved1 GE2_RD1/PCI_AD28 GND TDM7TDAT/GE2_TD3/ PCI_AD3/UTP_TMD TDM7RDAT/GE2_RD3/ PCI_AD1/UTP_STA GE1_RD0/UTP_RD2/ PCI_CBE2 TDM7TCLK/GE2_TCK/ PCI_IDS/UTP_RER Reserved1 Reserved 1 Ethernet 1 UTOPIA Ethernet 2 UTOPIA Reserved1 Reserved1 GNDSXP SRIO_TXD0 GNDSXP SRIO_TXD1 VDDSXC Reserved1 Reserved1 GNDSXP SRIO_TXD2/GE1_SGMII_T X GNDSXP SRIO_TXD3/GE2_SGMII_T X GNDSXP MDQ23 VDDDDR MDQ22 MDQ21 MDQS2 Reserved1 MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 8 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 F1 F2 F3 F4 F5 F6 F7 F8 F9 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) UTOPIA UTOPIA UTOPIA UTOPIA 1 (001) 2 (010) 3 (011) PCI PCI PCI PCI 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDGE1 VDDGE1 VDDGE1 VDDGE1 VDDGE1 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 — — GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDDDDR VDDDDR GND VDDDDR GND VDDDDR — UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 UTOPIA UTOPIA Ethernet 1 Ethernet 1 PCI PCI UTOPIA UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 GND UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1 VDDGE1 GND Signal Name GE1_RX_CLK/UTP_RD6/ PCI_PAR GE1_RD2/UTP_RD4/ PCI_FRAME GE1_RD1/UTP_RD3/ PCI_CBE3 GE1_RD3/UTP_RD5/ PCI_IRDY VDDGE1 GE1_TX_EN/UTP_TD6/ PCI_CBE0 Reserved1 Reserved1 GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDDDDR MDQ20 GND VDDDDR GND MDQS2 Reserved1 GE1_TX_CLK/UTP_RD0/ PCI_AD31 VDDGE1 GE1_TD3/UTP_TD5/ PCI_AD30 GE1_TD1/UTP_TD3/ PCI_AD28 GND GE1_TD0/UTP_TD2/ PCI_AD27 VDDGE1 GND Ethernet 1 Ethernet 1 Ethernet 1 Ethernet 1 UTOPIA UTOPIA UTOPIA UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 9 Table 1. Signal List by Ball Number (continued) Ball Number F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 VDD GND VDD GND VDD GND VDD GND VDD GND VDD Reserved VDDDDR GND MDQ19 MDQ18 MDM2 MDQ17 MDQ16 Reserved1 SRESET4 GND PORESET4 GE1_COL/UTP_RD1 GE1_TD2/UTP_TD4/ PCI_AD29 GE1_RX_DV/UTP_RD7 GE1_TX_ER/UTP_TD7/ PCI_CBE1 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND Reserved1 GND — UTOPIA UTOPIA UTOPIA UTOPIA Ethernet 1 Ethernet 1 Ethernet 1 Ethernet 1 PCI PCI UTOPIA UTOPIA UTOPIA UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPIA 1 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDD GND VDD GND VDD GND VDD GND VDD GND VDD — VDDDDR GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — VDDIO GND VDDIO VDDIO VDDGE1 VDDGE1 VDDGE1 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND — GND MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 10 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number G23 G24 G25 G26 G27 G28 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 J1 J2 J3 J4 J5 J6 J7 MBA1 MA3 MA8 VDDDDR GND MCK0 Reserved1 CLKIN HRESET PCI_CLK_IN NMI URXD/GPIO14/IRQ8/ RC_LDF3, 6 GE1_RX_ER/PCI_AD6/ GPIO25/IRQ153, 6 GE1_CRS/PCI_AD5 GND VDD GND VDD GND VDD VDD VDD GND VDD GND VDD VDD VDDDDR MBA0 MA15 VDDDDR MA9 MA7 MCK0 Reserved GND VDDIO STOP_BS NMI_OUT4 INT_OUT4 SDA/GPIO27 3, 4, 6 1 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR — VDDIO VDDIO VDDIO VDDIO RC_LDF GPIO/ IRQ PCI Ethernet 1 Ethernet 1 UART/GPIO/IRQ PCI PCI GPIO/ IRQ Ethernet 1 Ethernet 1 VDDIO VDDIO VDDIO GND VDD GND VDD GND VDD VDD VDD GND VDD GND VDD VDD VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — GND VDDIO VDDIO VDDIO VDDIO I2C/GPIO VDDIO MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 11 Table 1. Signal List by Ball Number (continued) Ball Number J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 VDDIO VDD GND VDD GND VDD GND GND GND VDD GND VDD GND GND GND GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 Reserved1 Reserved 1 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDD GND VDD GND VDD GND GND GND VDD GND VDD GND GND GND GND VDDDDR GND VDDDDR GND VDDDDR — — — — VDDPLL2A GND VDDPLL0A VDDPLL1A VDD GND VDD GND VDD VDD VDD VDD VDD GND VDD GND VDD VDDDDR Reserved1 VDDPLL2A GND VDDPLL0A VDDPLL1A VDD GND VDD GND VDD VDD VDD VDD VDD GND VDD GND VDD VDDDDR MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 12 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number K23 K24 K25 K26 K27 K28 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 M1 M2 M3 M4 M5 M6 M7 MBA2 MA10 MA12 MA14 MA4 MVREF Reserved1 CLKOUT TMR1/UTP_IR/PCI_CBE3/ GPIO173, 6 TMR4/PCI_PAR/GPIO203, 6/ UTP_REOP GND TMR2/PCI_FRAME/ GPIO183, 6 SCL/GPIO263, 4, 6 UTXD/GPIO15/IRQ93, 6 GND VDD GND VDD GND VDD Reserved VDD GND VDD GND VDD GND GND MCKE1 MA1 VDDDDR GND VDDDDR MCK1 Reserved TRST EE0 EE1 UTP_RCLK/PCI_AD13 UTP_RADDR0/PCI_AD7 UTP_TD8/PCI_AD30 UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA 1 1 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — VDDIO UTOPIA TMR/ GPIO UTOPIA PCI PCI UTOPIA TIMER/GPIO VDDIO VDDIO GND TIMER/GPIO PCI I2C/GPIO UART/GPIO/IRQ TIMER/GPIO UTOPIA VDDIO VDDIO VDDIO GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR — VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO TIMER/GPIO MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 13 Table 1. Signal List by Ball Number (continued) Ball Number M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 VDDIO VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDDDDR MCS1 MA13 MA2 MA0 GND MCK1 Reserved1 VDDIO TMS UTP_RD10/PCI_AD145 VDDIO UTP_RADDR1/PCI_AD8 UTP_TD9/PCI_AD31 TMR3/PCI_IRDY/GPIO193, 6 / UTP_TEOP GND VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 GND UTOPIA UTOPIA PCI PCI PCI UTOPIA PCI Power UTOPIA UTOPIA TIMER/GPIO UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR — VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 VDD VDDM3 GND Signal Name TIMER/GPIO MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 14 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number N22 N23 N24 N25 N26 N27 N28 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 R1 R2 R3 R4 R5 R6 GND MODT1 MCKE0 VDDDDR MA5 MA6 MA11 Reserved1 TDI5 UTP_RD11/PCI_AD15 GND UTP_RADDR3/PCI_AD10 UTP_RADDR2/PCI_AD9 PCI_GNT/GPIO29/IRQ73. 6 PCI_STOP/GPIO30/IRQ23, 6 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — VDDIO UTOPIA PCI UTOPIA VDDIO GND UTOPIA UTOPIA GPIO/IRQ GPIO/IRQ PCI PCI PCI PCI UTOPIA UTOPIA GPIO/IRQ GPIO/IRQ VDDIO VDDIO VDDIO VDDIO GND GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR GND VDDDDR — VDDIO VDDIO UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA VDDIO VDDIO VDDIO GND GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MCS0 MRAS GND VDDDDR GND MCK2 Reserved1 TCK TDO UTP_RD12/PCI_AD16 UTP_RCLAV_PDRPA/ PCI_AD12 UTP_RADDR4/PCI_AD11 MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 15 Table 1. Signal List by Ball Number (continued) Ball Number R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 VDDIO PCI_REQ GND GND GND GND GND GND GND GND GND GND GND GND GND GND MODT0 MDIC1 MDIC0 MCAS MWE MCK2 Reserved1 UTP_RPRTY/PCI_AD21 UTP_RD13/PCI_AD17 VDDIO UTP_RD14/PCI_AD18 UTP_RD15/PCI_AD19 PCI_TRDY PCI_DEVSEL/GPIO31/ IRQ33, 6 GND GND GND GND GND GND GND GND GND GND GND GND GPIO/IRQ PCI UTOPIA UTOPIA PCI PCI PCI GPIO/IRQ UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA PCI PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND GND GND GND GND Signal Name MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 16 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number T21 T22 T23 T24 T25 T26 T27 T28 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 V1 V2 V3 V4 V5 V6 V7 GND VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 UTP_TCLK/PCI_AD29 UTP_TADDR4/PCI_AD27 UTP_TADDR2 GND UTP_REN/PCI_AD20 PCI_AD26 PCI_AD25 Reserved1 VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND MDQ7 MDQ3 MDQ4 MDQ5 MDQ1 MDQ0 Reserved1 UTP_TD10/PCI_CBE0 UTP_TADDR3 UTP_TD1/PCI_PERR UTP_TADDR0/PCI_AD23 UTP_TADDR1/PCI_AD24 UTP_TCLAV/PCI_AD28 UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI PCI PCI UTOPIA PCI UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR — VDDIO VDDIO VDDIO GND VDDIO VDDIO VDDIO VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO Signal Name MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 17 Table 1. Signal List by Ball Number (continued) Ball Number V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 VDDIO Reserved1 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MDQ2 VDDDDR MDQ6 GND VDDDDR MDQS0 Reserved1 UTP_TD12/PCI_CBE2 UTP_TD11/PCI_CBE1 VDDIO GND UTP_TD15/PCI_IRDY UTP_TD0/PCI_SERR UTP_RSOC/PCI_AD22 Reserved1 VDDM3 GND V25M3 GND VDDM3 V25M3 VDDM3 GND V25M3 GND VDDM3 GND GND UTOPIA UTOPIA UTOPIA PCI PCI PCI UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA PCI PCI UTOPIA UTOPIA PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR — VDDIO VDDIO VDDIO GND VDDIO VDDIO VDDIO VDDIO VDDM3 GND V25M3 GND VDDM3 V25M3 VDDM3 GND V25M3 GND VDDM3 GND GND Signal Name MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 18 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number W23 W24 W25 W26 W27 W28 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 AA1 AA2 AA3 AA4 AA5 AA6 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDDDR GND VDDDDR VDDDDR GND VDDDDR UTOPIA TDM/GPIO TDM TDM TDM RC14 UTOPIA PCI PCI PCI PCI PCI PCI UTOPIA UTOPIA UTOPIA TDM/GPIO TDM TDM TDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR GND VDDDDR VDDDDR VDDDDR — UTOPIA TDM/GPIO TDM/GPIO TDM/GPIO PCI PCI PCI PCI UTOPIA TDM/GPIO TDM/GPIO TDM/GPIO VDDIO VDDIO VDDIO VDDIO GND Signal Name MDQ10 GND MDQ11 MDM0 GND MDQS0 Reserved1 UTP_TD14/PCI_FRAME TDM5TSYN/PCI_AD18/ GPIO123, 6 TDM5TCLK/PCI_AD16 TDM4RCLK/PCI_AD7 TDM4TSYN/PCI_AD12 UTP_TPRTY/RC14 UTP_TEN/PCI_PAR Reserved1 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR MDQ13 VDDDDR GND MDQ9 VDDDDR MDQ8 Reserved1 UTP_TD13/PCI_CBE3 TDM5RSYN/PCI_AD15/ GPIO103, 6 TDM5TDAT, AT/PCI_AD17/ GPIO116 TDM5RCLK/PCI_AD13/ GPIO283, 6 GND MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 19 Table 1. Signal List by Ball Number (continued) Ball Number AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) TDM TDM 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) TDM TDM 7 (111) Ref. Supply VDDIO VDDIO VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR RC15 UTOPIA VDDIO VDDIO TDM/GPIO/ IRQ TDM/GPIO TDM/GPIO/IRQ TDM/GPIO/IRQ TDM TDM PCI PCI PCI PCI PCI PCI TDM/GPIO/ IRQ TDM/GPIO TDM/GPIO/IRQ TDM/GPIO/IRQ TDM TDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND Signal Name TDM4TCLK/PCI_AD10 TDM4TDAT/PCI_AD11 VDDIO VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND GND MDQ15 MDQ14 MDM1 MDQ12 PCI PCI MDQS1 MDQS1 Reserved1 UTP_TSOC/RC15 VDDIO TDM6RDAT/PCI_AD20/ GPIO5/IRQ113, 6 TDM5RDAT/PCI_AD14/ GPIO93, 6 TDM6TSYN/PCI_AD24/ GPIO8/ IRQ143, 6 TDM6RCLK/PCI_AD19/ GPIO4/IRQ103, 6 TDM4RSYN/PCI_AD9 TDM4RDAT/PCI_AD8 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 20 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AD1 AD2 AD3 VDDM3 GND GND VDDDDR MECC7 MECC1 MECC4 MECC5 MECC2 ECC_MDQS Reserved1 UTP_RD9/RC13 UTP_RD8/RC12 TDM6TCLK/PCI_AD22 TDM6RSYN/PCI_AD21/ GPIO6/ IRQ123, 6 VDDIO TDM3TSYN/RC11 PCI_AD23/GPIO7/IRQ13/ TDM6TDAT3, 6/UTP_RMOD TDM7TSYN/ PCI_AD4 VDDM3IO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3IO Reserved1 MECC6 MECC3 ECC_MDM VDDDDR MECC0 VDDDDR ECC_MDQS Reserved1 GPIO1 3, 6 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDM3 GND GND VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — RC13 RC12 TDM TDM/GPIO/IRQ UTOPIA UTOPIA PCI PCI TDM TDM/GPIO/IRQ VDDIO VDDIO VDDIO VDDIO VDDIO RC11 TDM/GPIO/IRQ TDM PCI TDM PCI TDM/GPIO/IRQ reserved UTOPIA VDDIO VDDIO VDDIO VDDM3IO GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3 GND VDDM3IO — VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR VDDDDR — GPIO TIMER/GPIO VDDIO VDDIO TMR0/GPIO13 MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 21 Table 1. Signal List by Ball Number (continued) Ball Number AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) GPIO 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO GND TDM RC10 RC9 RC8 TDM TDM TDM VDDIO VDDIO VDDIO VDDIO GND V25M3 GND VDDM3 GND V25M3 GND VDDM3 GND V25M3 GND 1 Signal Name GPIO23, 6 GND TDM1TCLK TDM3TDAT/RC10 TDM3RSYN/RC9 TDM3RDAT/RC8 GND V25M3 GND VDDM3 GND V25M3 GND VDDM3 GND V25M3 GND Reserved VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 GPIO03, 6 GPIO33, 6 TDM1RCLK TDM1TSYN/RC3 TDM1TDAT/RC2 TDM1RSYN/RC1 TDM3RCLK/RC16 TDM3TCLK TDM2TDAT/RC6 GPIO21/IRQ13. 6/SPICLK GND Reserved GND Reserved1 Reserved1 Reserved1 GND 1 — VDDDDR GND VDDDDR GND VDDDDR GND VDDDDR — GPIO GPIO TDM RC3 RC2 RC1 RC16 TDM TDM TDM TDM TDM RC6 TDM GPIO/IRQ/SPI VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO GND — GND — — — GND MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 22 Freescale Semiconductor Table 1. Signal List by Ball Number (continued) Ball Number AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AF1 AF2 AF3 AF4 GND VDDM3IO Reserved1 GND GND GND VDDDDR GND VDDDDR GND Reserved1 VDDIO GND TDM0RDAT/ RCFG_CLKIN_RNG TDM0TSYN/RCW_SRC2 TDM1RDAT/RC0 VDDIO GND TDM2RDAT/RC4 TDM2TCLK GPIO22/IRQ4 GND GND VDDM3IO GND GND Reserved VDDM3IO GND Reserved1 Reserved 1 1 3, 6 Signal Name PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply GND VDDM3IO — GND GND GND VDDDDR GND VDDDDR GND — VDDIO GND RCFG_ CLKIN_ RNG RCW_ SRC2 RC0 TDM VDDIO AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AG1 AG2 AG3 TDM TDM VDDIO VDDIO VDDIO GND RC4 TDM TDM VDDIO VDDIO VDDIO GND GND VDDM3IO GND GND — VDDM3IO GND — — VDDM3IO GND VDDDDR GND VDDDDR GND VDDDDR — /SPIMOSI GPIO/IRQ/SPI M3_RESET GND VDDDDR GND VDDDDR GND VDDDDR Reserved1 GPIO16/IRQ03, 6 TDM0TCLK GPIO/IRQ TDM VDDIO VDDIO MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 23 Table 1. Signal List by Ball Number (continued) Ball Number AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 PowerOn Reset Value RCW_ SRC0 I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO — GND GND GND GND 1 Signal Name TDM0RSYN/RCW_SRC0 TDM0RCLK TDM0TDAT/RCW_SRC1 TDM2TSYN/RC7 TDM2RCLK TDM2RSYN/RC5 GPIO24/IRQ63, 6/SPISEL GPIO23/IRQ5 Reserved1 GND GND GND GND Reserved Reserved1 GND GND VDDM3IO GND GND GND VDDDDR GND VDDDDR GND Reserved 1 3, 6 TDM TDM RCW_ SRC1 RC7 TDM TDM TDM RC5 TDM GPIO/IRQ/SPI GPIO/IRQ/SPI /SPIMISO — — GND GND VDDM3IO GND GND GND VDDDDR GND VDDDDR GND — — — — — — — — — — — — — — — — Reserved1 Reserved1 Reserved1 Reserved 1 Reserved1 Reserved 1 Reserved1 Reserved 1 Reserved1 Reserved 1 Reserved1 Reserved1 Reserved1 Reserved 1 Reserved1 MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 24 Freescale Semiconductor Electrical Characteristics Table 1. Signal List by Ball Number (continued) Ball Number AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 Notes: PowerOn Reset Value I/O Multiplexing Mode2 0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111) Ref. Supply — — — — — — — — — — — — Signal Name Reserved1 Reserved1 Reserved1 Reserved 1 Reserved1 Reserved 1 Reserved1 Reserved1 Reserved1 Reserved 1 Reserved1 Reserved 1. 2. 3. 4. 5. 6. 1 Reserved signals should be disconnected for compatibility with future revisions of the device. For signals with same functionality in all modes the appropriate cells are empty. The choice between GPIO function and other function is by GPIO registers setup. For configuration details, see Chapter 23, GPIO in the MSC8144E Reference Manual. Open-drain signal. Internal 20 KΩ pull-up resistor. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register programming. See Chapter 23, GPIO of the MSC8144E Reference Manual for configuration details. 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8144E Reference Manual. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 25 Electrical Characteristics Table 2 describes the maximum electrical ratings for the MSC8144E. Table 2. Absolute Maximum Ratings Rating Core supply voltage PLL supply voltage Symbol Vdd VDDPLL0 VDDPLL1 VDDPLL2 VDDM3 VDDDDR Value –0.3 to 1.1 –0.3 to 1.1 Unit V V M3 memory Internal voltage DDR memory supply voltage • DDR mode • DDR2 mode DDR reference voltage Input DDR voltage Ethernet 1 I/O voltage Input Ethernet 1 I/O voltage Ethernet 2 I/O voltage Input Ethernet 2I/O voltage I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines Input I/O voltage M3 memory I/O and M3 memory charge pump voltage –0.3 to 1.32 –0.3 to 2.75 –0.3 to 1.98 V V V V V V V V V V V V MVREF VINDDR VDDGE1 VINGE1 VDDGE2 VINGE2 VDDIO VINIO VDDM3IO V25M3 VINM3IO VDDSXC VDDSXP VDDRIOPLL TJ TSTG –0.3 to 0.51 × VDDDDR –0.3 to VDDDDR + 0.3 –0.3 to 3.465 –0.3 to VDDGE1 + 0.3 –0.3 to 3.465 –0.3 to VDDGE2 + 0.3 –0.3 to 3.465 –0.3 to VDDIO + 0.3 –0.3 to 2.75 Input M3 memory I/O voltage Rapid I/O C voltage Rapid I/O P voltage Rapid I/O PLL voltage Operating temperature Storage temperature range Notes: 1. 2. 3. –0.3 to VDDM3IO + 0.3 –0.3 to 1.21 –0.3 to 1.26 –0.3 to 1.21 –40 to 105 –55 to +150 V V V V °C °C Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 44) MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 26 Freescale Semiconductor Electrical Characteristics 2.2 Recommended Operating Conditions Table 3. Recommended Operating Conditions Rating Symbol VDD VDDPLL0 VDDPLL1 VDDPLL2 VDDM3 VDDDDR 2.375 1.71 0.49 × VDDDDR 2.375 3.135 VDDGE2 2.375 3.135 VDDIO VDDM3IO V25M3 VDDSXC VDDSXP 0.95 1.14 VDDRIOPLL TJ TA TJ 0.95 0 –40 — 1.0 1.2 1.0 1.05 1.26 1.05 90 — 105 V V V °C °C °C 3.135 2.375 0.95 2.5 3.3 3.3 2.5 1.0 2.625 3.465 3.465 2.625 1.05 V V V V V 2.5 1.8 0.5 × VDDDDR 2.5 3.3 2.625 1.89 0.51 × VDDDDR 2.625 3.465 V V V V V Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Min 0.97 0.97 Nominal 1.0 1.0 Max 1.05 1.05 Unit V V Core supply voltage PLL supply voltage M3 memory Internal voltage DDR memory supply voltage • DDR mode • DDR2 mode DDR reference voltage Ethernet 1 I/O voltage • 2.5 V mode • 3.3 V mode Ethernet 2 I/O voltage • 2.5 V mode • 3.3 V mode I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines M3 memory I/O and M3 charge pump voltage Rapid I/O C voltage Rapid I/O P voltage • Short run (haul) mode • Long run (haul) mode Rapid I/O PLL voltage Operating temperature range: • Standard • Extended Note: 1.213 1.25 1.313 V MVREF VDDGE1 PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 44). 2.3 Default Output Driver Characteristics Table 4. Output Drive Impedance Driver Type Output Impedance (Ω) 18 18 35 (half strength mode) 25 100 50 Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. DDR signal DDR2 signal PCI signals Rapid I/O signals Other signals MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 27 Electrical Characteristics 2.4 Thermal Characteristics Table 5. Thermal Characteristics for the MSC8144E FC-PBGA 29 × 29 mm5 Natural Convection 200 ft/min (1 m/s) airflow 15 12 °C/W °C/W °C/W °C/W Table 5 describes thermal characteristics of the MSC8144E for the FC-PBGA packages. Characteristic Symbol Unit Junction-to-ambient1, 2 Junction-to-ambient, four-layer board Junction-to-board (bottom)4 Junction-to-case5 Notes: 1. 1, 3 RθJA RθJA RθJB RθJC 20 15 7 0.8 2. 3. 4. 5. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. 2.5 Power Characteristics Table 6. Power Dissipation Extended Core Frequency 266 Core Frequency 400 533 667 800 333 500 667 833 1000 400 400 600 800 1000 500 500 750 1000 Typical TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD W W W Unit W The estimated typical power dissipation for MSC8144E versus the core frequency is shown in Table 6. Note: Measured for 1.0 V core at 25°C junction temperature. The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 28 Freescale Semiconductor Electrical Characteristics all four cores. It was created using CodeWarrior® 3.0. These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of this document. At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AVDD supplies for the MSC8144E PLLs. Table 7. MSC8144E PLLs Power Dissipation PLL supply VDDPLL0 VDDPLL1 VDDPLL2 Note: Typical TBD TBD TBD Maximum 10 10 10 Unit mW mW mW Typical value is based on VDDPLLX = 1.0 V, TA = 70°C, TJ = 105°C. 2.6 2.6.1 Note: DC Electrical Characteristics DDR SDRAM DC Electrical Characteristics DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM uses VDDDDR(typ) = 1.8 V. This section describes the DC electrical characteristics for the MSC8144E. This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E. 2.6.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when VDDDDR(typ) = 1.8 V. Table 8. DDR2 SDRAM DC Electrical Characteristics for VDDDDR (typ) = 1.8 V Parameter/Condition I/O supply voltage1 I/O reference voltage2 I/O termination voltage3 Input high voltage Input low voltage Output leakage current4 Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Notes: 1. 2. 3. 4. Symbol VDDDDR MVREF VTT VIH VIL IOZ IOH IOL Min 1.7 0.49 × VDDDDR MVREF – 0.04 MVREF + 0.125 –0.3 –50 –13.4 13.4 Max 1.9 0.51 × VDDDDR MVREF + 0.04 VDDDDR + 0.3 Unit V V V V V μA mA mA MVREF – 0.125 50 — — VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of VDDDDR. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR. MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 29 Electrical Characteristics Table 9 provides the DDR capacitance when VDDDDR(typ) = 1.8 V. Table 9. DDR2 SDRAM Capacitance for VDDDDR(typ) = 1.8 V Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF This parameter is sampled. VDDDDR = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V. 2.6.1.2 DDR (2.5V) SDRAM DC Electrical Characteristics Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144E when VDDDDR(typ) = 2.5 V. Table 10. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V Parameter/Condition I/O supply voltage1 I/O reference voltage2 3 Symbol VDDDDR MVREF VTT VIH VIL Min 2.3 0.49 × VDDDDR MVREF – 0.04 MVREF + 0.15 –0.3 –50 –16.2 16.2 Max 2.7 0.51 × VDDDDR MVREF + 0.04 VDDDDR + 0.3 MVREF – 0.15 50 — — Unit V V V V V μA mA mA I/O termination voltage Input high voltage Input low voltage Output leakage current 4 IOZ IOH IOL Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Notes: 1. 2. 3. 4. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of VDDDDR. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR. Table 11 provides the DDR capacitance when VDDDDR (typ) = 2.5 V. Table 11. DDR SDRAM Capacitance for VDDDDR (typ) = 2.5 V Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF This parameter is sampled. VDDDDR = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V. Table 12 lists the current draw characteristics for MVREF. Table 12. Current Draw Characteristics for MVREF Parameter / Condition Current draw for MVREF Note: Symbol IMVREF Min — Max 500 Unit μA The voltage regulator for MVREF must be able to supply up to 500 μA current. MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 30 Freescale Semiconductor Electrical Characteristics 2.6.2 Serial RapidIO DC Electrical Characteristics DC receiver logic levels are not defined since the receiver is AC-coupled. 2.6.2.1 DC Requirements for SerDes Reference Clocks The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential clock input has an internal 50 Ω termination to GNDSXC. The reference clock must be able to drive this termination. The recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the maximum absolute voltage is 1.72 V. The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum common mode input level is GNDSXC. For example, a clock with a 50/50 duty cycle can be driven by a current source output that ranges from 0 mA to 16 mA (0–0.8 V). The input is AC-coupled internally, so, therefore, the exact common mode input voltage is not critical. Note: This internal AC-couple network does not function correctly with reference clock frequencies below 90 MHz. If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GNDSXC, or if it exceeds the maximum input current limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V (0.2 V peak-to-peak per phase). The maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see Figure 5. The termination to GNDSXC allows compatibility with HCSL type reference clocks specified for PCI-Express applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the limited common mode input range. LVPECL outputs can produce too large an amplitude and may need to be source terminated with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV differential peak-peak for single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible with AC-coupling. SRIO_REF_CLK 50 Ω GNDSXC 50 Ω SRIO_REF_CLK Figure 5. SerDes Reference Clocks Input Stage 2.6.2.2 Spread Spectrum Clock SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spreading at 3033 kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation. MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 31 Electrical Characteristics 2.6.3 PCI DC Electrical Characteristics Table 13. PCI DC Electrical Characteristics Characteristic Symbol VDDPCI VIH VIL VIPU IIN IOZ IL 2 Min 3.135 0.5 × VDDPCI –0.5 0.7 × VDDPCI –30 –30 –30 –30 0.9 × VDDPCI — Max 3.465 3.465 0.3 × VDDPCI 30 30 30 30 — 0.1 × VDDPCI 10 Unit V V V μA μA μA μA V V pF Supply voltage 3.3 V Input high voltage Input low voltage Input Pull-up voltage2 Input leakage current, 0