CSTCR6M00G15

FT2232L Dual USB UART / FIFO I.C. 1.0 The FT2232L is the lead free version of FTDI’s 3rd generation USB UART / FIFO I.C. family. This device features two Multi-Purpose UART / FIFO controllers which can be configured individually in several different modes. As well as a UART interface, FIFO interface and Bit-Bang IO modes of the 2nd generation FT232BM and FT245BM devices, the FT2232L offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine interface which is designed specifically for synchronous serial protocols such as JTAG and SPI bus. Introduction 1.1 • • • • • • • • HARDWARE FEATURES Features Summary Reset input and Reset Output pins • • • • • • • • • • • • • • • • • • • • • • • • 5V and 3.3V logic IO Interfacing with independent level conversion on each channel Integrated 3.3V LDO Regulator for USB IO Integrated 6MHz – 48Mhz clock multiplier PLL USB Bulk or Isochronous data transfer modes 4.35V to 5.25V single supply operating voltage range UHCI / OHCI / EHCI host controller compatible USB 2.0 Full Speed (12 Mbits / Second) compatible Compact 48-LD Lead Free LQFP package Windows 98 / 98 SE / 2000 / ME / XP Linux 2.40 and greater Windows CE MAC OS-8 and OS-9** MAC OS-X Windows 98 / 98 SE / 2000 / ME / XP Linux 2.4 and Greater USB Dual Port RS232 Converters USB  Dual Port RS422 / RS485 Converters Upgrading Legacy Peripheral Designs to USB USB Instrumentation USB JTAG Programming USB to SPI Bus Interfaces USB Industrial Control Field Upgradable USB Products Galvanically Isolated Products with USB Interface VIRTUAL COM PORT (VCP) DRIVERS for Single Chip USB  Dual Channel Serial / Parallel Ports with a variety of configurations Entire USB protocol handled on the chip...no USBspecific firmware programming required FT232BM-style UART interface option with full Handshaking & Modem interface signals UART Interface supports 7 / 8 bit data, 1 / 2 stop bits, and Odd / Even / Mark / Space / No Parity Transfer Data Rate 300 to 1 Mega Baud (RS232) Transfer Data Rate 300 to 3 Mega Baud (TTL and RS422 / RS485) Auto Transmit Enable control for RS485 serial applications using TXDEN pin FT245BM-style FIFO interface option with bidirectional data bus and simple 4 wire handshake interface • • • • • • • • • • • Transfer Data Rate up to 1 MegaByte / Second Enhanced Bit-Bang Mode interface option New Synchronous Bit-Bang Mode interface option New Multi-Protocol Synchronous Serial Engine (MPSSE) interface option New MCU Host Bus Emulation Mode option New Fast Opto-Isolated Serial Interface Mode option Interface mode and USB Description strings configurable in external EEPROM EEPROM Configurable on board via USB Support for USB Suspend and Resume conditions via PWREN#, and SI / WU pins Support for bus powered, self powered, and highpower bus powered USB configurations Integrated Power-On-Reset circuit, with optional DS2232L Version 1.4 D2XX (USB Direct Drivers + DLL S/W Interface) APPLICATION AREAS [ ** = In planning or under development ] © Future Technology Devices International Ltd. 2005 Page 1 of 51 FT2232L Dual USB UART / FIFO I.C. 1.2 General Description The FT2232L is a USB interface which incorporates the functionallity of two of FTDI’s second generation BM chips into a single device. A single downstream USB port is converted to two IO channels which can each be individually configured as a FT232BM-style UART interface, or a FT245BM-style FIFO interface, without the need to add a USB hub. There are also several new special modes which are either enabled in the external EEPROM, or by using driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface Mode. In addition a new high drive level option means that the device UART / FIFO IO pins will drive out at around three times the normal power level, meaning that the bus can be shared by several devices. Classic BM-style Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s internal RD# and WR# strobes. FTDI provide a royalty free Virtual Com Port (V.C.P) driver that makes the peripheral ports look like a standard COM port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by reconfiguring them to use the new ports created by the driver. Using the VCP drivers an application programmer would communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows VCOMM API calls or a COM port library. The FT2232L driver also incorporates the functions defined for FTDI’s D2XX drivers, allowing applications programmers to interface software directly to the device using a Windows DLL. Details of the driver and the programming interface can be found on FTDI’s website at www.ftdichip.com. DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 2 of 51 FT2232L Dual USB UART / FIFO I.C. 2.0 Features and Enhancements The FT2232L incorporates all of the enhancements introduced for the second generation FT232BM and FT245BM chips. These are summarised as follows :• Two Individually Configurable IO Channels Each of the FT2232L’s Channels (A and B) can be individually configured as a FT232BM-style UART interface, or as a FT245BM-style FIFO interface. In addition these channel can be configured in a number of special IO modes. • Integrated Power-On-Reset (POR) circuit The device incorporates an internal POR function. A RESET# pin is available to allow external logic to reset the device where required, however for most applications this pin can simply be hardwired to Vcc. A RSTOUT# pin is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices. • Integrated RCCLK circuit Used to ensure that the oscillator and clock multiplier PLL frequency are stable prior to USB enumeration. • Integrated level converter on UART / FIFO interface and control signals Each channel of the FT2232L has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each channel’s output voltage drive level to be individually configured. Thus allowing, for example 3.3V logic to be interfaced to the device without the need for external level converter I.C.’s. • Improved power management control for highpower USB Bus Powered devices The PWREN# pin will become active when the device is enumerated by USB, and be deactivated when the device is in USB suspend. This can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. The BM pull down enable feature (configured in the external EEPROM) DS2232L Version 1.4 • • • is also retained. This will make the device gently pull down on the FIFO / UART IO lines when the power is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. Support for Isochronous USB Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the FT2232L offers the option of USB Isochronous transfer via configuration of bit in the EEPROM. Send Immediate / Wake Up Signal Pin on each channel There is a Send Immediate / Wake Up (SI/WU) signal pins on each of the chips channels. These combine two functions on one pin. If USB is in suspend mode (and remote wakeup is enabled in the EEPROM), strobing this pin low will cause the device to request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the packet size. This can be used to optimise USB transfer speed for some applications. Low suspend current The suspend current of the FT2232L is typically under 100 μA (excluding the 1.5K pull up resistor on USBDP) in USB suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of 500uA. © Future Technology Devices International Ltd. 2005 Page 3 of 51 FT2232L Dual USB UART / FIFO I.C. • Programmable Receive Buffer Timeout The TX buffer timeout is programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets. • Relaxed VCC Decoupling The improved level of Vcc decoupling that was incorporated into BM devices has also been implemented in the FT2232L device. • Baud Rate Pre-Scaler Divisors The FT2232L (UART mode) baud rate pre-scaler supports division by (n+0), (n+0.125), (n+0.25), (n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875) where n is an integer between 2 and 16,384 (214). • • Extended EEPROM Support The FT2232L supports 93C46 (64 x 16 bit), 93C56 (128 x 16 bit), and 93C66 (256 x 16 bit) EEPROMs. The extra space is not used by the device, however it is available for use by other external MCU / logic whilst the FT2232L is being held in reset. There is now an adiitional 64 words of space available (128 bytes total) in the user area when a 93C56 or 93C66 is used. USB 2.0 (full speed option) An EEPROM based option allows the FT2232L to return a USB 2.0 device descriptor as opposed to USB 1.1. Note : The device would be a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 4 of 51 FT2232L Dual USB UART / FIFO I.C. In addition to the BM chip features, the FT2232L incorporates the following new features and interface modes :• Enhanced Asynchronous Bit-Bang Interface The FT2232L supports FTDI’s BM chip Bit Bang mode. In Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT2232L device this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the BitBang IO bus. • Synchronous Bit-Bang Interface Synchronous Bit-Bang Mode differs from Asynchronous Bit-Bang mode in that the device is only read when it is written to. Thus making it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. High Output Drive Level Capabillity The IO interface pins can be made to drive out at three times the standard drive level thus allowing multiple devices, or devices that require a greater drive strength to be interfaced to the FT2232L. This option is configured in the external EEPROM, ad can be set individually for each channel. Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.) The Multi-Protocol Synchronous Serial Engine (MPSSE) interface is a new option designed to interface efficiently with synchronous serial protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry standards, or proprietary bus protocols. For instance, it is possible to connect one of the FT2232L’s channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 5 of 51 normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use the MPSSE to download configuration data to the FPGA over USB. This data would define the hardware’s function on power up. The other FT2232 channel would be available for other devices. This approach would allow a customer to create a “generic” USB peripheral, who’s hardware function can be defined under control of the application software. The FPGA based hardware could be easily upgraded or totally changed simply by changing the FPGA configuration data file. (See FTDI’s MORPHIC development module for a practicle example, www.morph-ic.com) • MCU Host Bus Emulation This new mode combines the ‘A’ and ‘B’ bus interface to make the FT2232L interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU families to be directly attached to the FT2232L with IO being performed over USB with the help of MPSSE interface technology. Fast Opto-Isolated Serial Interface A new proprietary FTDI protocol is designed to allow galvanically isolated devices to communicate sychronously with the FT2232L using just 4 signal wires (over two dual opto-isolators), and two power lines. The peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. Maximum USB full speed data rates can be acheived. Both ‘A’ and ‘B’ channels can communicate over the same 4 wire interface if desired. • • • FT2232L Dual USB UART / FIFO I.C. 3.0 Simplified Block Diagram PWREN# 48MHz Baud Rate Generator Channel A ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 VCC PWRCTL Dual Port TX Buffer 128 bytes 3V3OUT 3.3 Volt LDO Regulator Dual Port RX Buffer 384 Bytes MultiPurpose UART / FIFO Controller ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 USBDP USB Transceiver USBDM Serial Interface Engine ( SIE ) USB Protocol Engine SI/WUA Channel B Dual Port TX Buffer 128 bytes BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 USB DPLL Dual Port RX Buffer 384 Bytes MultiPurpose UART / FIFO Controller XTOUT 6MHZ Oscillator x8 Clock Multiplier 48MHz 48MHz 12MHz Baud Rate Generator BCBUS3 SI/WUB XTIN 3V3OUT EECS TEST GND EEPROM Interface EESK EEDATA RESET# RESET GENERATOR RSTOUT# Figure 1 - FT2232L Simplified Block Diagram 3.1 • Functional Block Descriptions 3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power from the 3V3OUT pin if required. • USB Transceiver The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block. • DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 6 of 51 FT2232L Dual USB UART / FIFO I.C. • 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz crystal or ceramic resonator. x8 Clock Multiplier The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks. Serial Interface Engine (SIE) The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / unstuffing and CRC5 / CRC16 generation / checking on the USB data stream. USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the UART / FIFO controller blocks. Dual Port TX Buffers (128 bytes) Data from the USB data out endpoint is stored in the Dual Port TX buffer and removed from the buffer to the transmit register under control of the UART FIFO controller. Dual Port RX Buffers (384 bytes) Data from the UART / FIFO controller receive register is stored in the Dual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint. Multi-Purpose UART / FIFO Controllers The Multi-purpose UART / FIFO controllers handle the transfer of data between the Dual Port RX and TX buffers and the UART / FIFO transmit and receive registers. When configured as a UART it performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the data on the RS232 (RS422 and RS485) interface. Control signals supported by UART mode include RTS, CTS, DSR , DTR, DCD and RI. There are also transmitter enable control signal pins (TXDEN) provided to assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and Xon/Xoff handshaking options are also supported. Handshaking, where required, is handled in hardware to ensure fast response times. The UART’s also supports the RS232 BREAK setting and detection conditions. • Baud Rate Generator The Baud Rate Generator provides a x16 clock input to the UART’s from the 48MHz reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 3 million baud. RESET Generator The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT2232L, or the FT2232L to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1.5K pull-up on USBDP directly where delayed USB enumeration is required. It can also be used to reset other devices. RSTOUT# will stay highimpedance for approximately 5ms after VCC has risen above 3.5V AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device from external logic or an external reset generator I.C. • • • • • • • DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 7 of 51 FT2232L Dual USB UART / FIFO I.C. • EEPROM Interface When used without an external EEPROM the FT2232L be configured as a USB to dual serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows each of the chip’s channels to be independently configured as a serial UART (232 mode), or a parallel FIFO (245 mode). The external EEPROM is used to enable the Fast Opto-Isolated Serial interface mode. The external EEPROM can also be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT2232L for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The EEPROM should be a 16 bit wide configuration such as a MicroChip 93LC46B or equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility program available from FTDI’s web site (www.ftdichip.com). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT2232L will default to dual serial ports. The device use its built-in default VID, PID Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 8 of 51 FT2232L Dual USB UART / FIFO I.C. 4.0 Device Pin-Out 31 14 42 3 V C C 6 PW REN# BDBUS0 BDBUS1 BDBUS2 3V3OUT A V C C 46 V C C BDBUS3 AGND XTOU T EECS TEST AVCC V C C I O A V C C I O B ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 SI/WUA BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 24 23 22 21 20 19 17 16 15 13 12 11 10 40 39 38 37 36 35 33 32 30 29 28 27 X T IN VCC 8 USBDM 7 USBDP EESK EEDATA VCC RESET# RSTOUT# 3V3OUT USBDP USBDM GND SI/WUA ACBUS3 ACBUS2 1 48 37 36 BDBUS4 BDBUS5 GND BDBUS6 BDBUS7 VCCIOB BCBUS0 BCBUS1 BCBUS2 BCBUS3 SI/WUB GND 5 4 RSTOUT# RESET# FTDI FT2232L XXYY 12 13 25 24 43 XTIN 44 48 1 2 XTOUT EECS EESK EEDATA TEST A G N D 47 ACBUS1 V C C IO A ACBUS0 ADBUS7 ADBUS6 GND ADBUS5 ADBUS4 ADBUS3 ADBUS2 ADBUS1 ADBUS0 G GG G SI/WUB N NN N D D D D PWREN# 26 41 34 25 18 9 45 Figure 2 Pin-Out (Lead Free LQFP-48 Package ) Figure 3 Pin-Out (Schematic Symbol ) DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 9 of 51 FT2232L Dual USB UART / FIFO I.C. 5.0 Pin Definitions This section decribes the operation of the FT2232L pins. Common pins are defined in the first section, then the I/O pins are defined, by chip mode. More detailed descriptions of the operation of the I/O pins are provided in section 9. 5.1 Common Pins The operation of the following FT2232L pins stay the same, regardless of the chip mode :USB INTERFACE GROUP Pin# 7 8 Signal USBDP USBDM Type I/O I/O Description USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# ) USB Data Signal Minus EEPROM INTERFACE GROUP Pin# 48 1 2 Signal EECS EESK EEDATA Type I/O I/O Description EEPROM – Chip Select. Tri-State during device reset. **Note 1 EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. Tri-State during device reset. **Note 1 OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out. **Note 1 MISCELLANEOUS SIGNAL GROUP Pin# 4 5 Signal RESET# RSTOUT# Type INPUT Description Can be used by an external device to reset the FT2232L. If not required, tie to VCC. **Note 1 OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC > 3.5V and the internal clock starts up, then clamps it’s output to the 3.3V output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset. INPUT Puts device into I.C. test mode – must be tied to GND for normal operation. OUTPUT Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. INPUT Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external 6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if driving from an external source, the source must be driving at 5V CMOS level or a.c. coupled to centre around VCC/2. 47 41 TEST PWREN# 43 XTIN 44 XTOUT OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. **Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors. DS2232L Version 1.4 © Future Technology Devices International Ltd. 2005 Page 10 of 51 POWER AND GND GROUP Pin# 6 Signal 3V3OUT Type Description FT2232L Dual USB UART / FIFO I.C. OUTPUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled to GND using a 33nF ceramic capacitor in close proximity to the device pin. It’s prime purpose is to provide the internal 3.3V supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current (