FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Future Technology Devices
International Ltd.
FT220X
(USB 4-BIT SPI/FT1248 IC)
The FT220X is a USB to FTDI’s
proprietary FT1248 interface and the
following advanced features:
USB Battery Charger Detection. Allows for USB
peripheral devices to detect the presence of a
higher power source to enable improved
charging.
FT1248 serial parallel interface in 1, 2 or 4 bit
wide mode.
Device supplied pre-programmed with unique
USB serial number.
Similar to an SPI slave in 1 bit mode
Entire USB protocol handled on the chip. No
USB specific firmware programming required.
USB Power Configurations; supports buspowered, self-powered and bus-powered with
power switching.
Fully
integrated
2048
byte
multi-timeprogrammable (MTP) memory, storing device
descriptors and CBUS I/O configuration.
Integrated +3.3V level converter for USB I/O.
True 3.3V CMOS drive output and TTL input.
(operates down to 1V8 with external pull-ups)
Tolerant of 5V input.
Configurable I/O pin output drive strength; 4
mA(min) and 16 mA(max)
Integrated power-on-reset circuit.
Fully integrated AVCC supply filtering - no
external filtering required.
+ 5V Single Supply Operation.
Internal 3V3/1V8 LDO regulators
Low operating and USB suspend current; 8mA
(active-typ) and 125uA (suspend-typ).
Low USB bandwidth consumption.
UHCI/OHCI/EHCI host controller compatible.
USB 2.0 Full Speed compatible.
Extended operating temperature range; -40 to
85⁰C.
Available in compact Pb-free 16 Pin SSOP and
QFN packages (both RoHS compliant).
Fully integrated clock generation with no
external crystal required plus optional clock
output selection enabling a glue-less interface
to external MCU or FPGA.
Data transfer rates to 500kByte/s.
512 byte receive buffer and 512 byte transmit
buffer utilising buffer smoothing technology to
allow for high data throughput.
FTDI’s royalty-free Virtual Com Port (VCP) and
Direct
(D2XX)
drivers
eliminate
the
requirement for USB driver development in
most cases.
Configurable CBUS I/O pin.
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or fa ilure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow
G41 1HH United Kingdom. Scotland Registered Company Number: SC136640
Copyright © Future Technology Devices International Limited
1
FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
1 Typical Applications
USB to SPI interface in 1-bit mode
USB Industrial Control
Upgrading Legacy Peripherals to USB
Utilising USB to add system modularity
Detect USB dedicated charging ports, to allow
for high current battery charging in portable
devices.
Incorporate USB
transfers
for
communication
Interfacing MCU/PLD/FPGA based designs to
add USB connectivity
interface to enable PC
development
system
1.1 Driver Support
Royalty free VIRTUAL COM PORT
(VCP) DRIVERS for...
Royalty free D2XX Direct Drivers
(USB Drivers + DLL S/W Interface)
Windows 10 32,64-bit
Windows 10 32,64-bit
Windows 8 32,64-bit
Windows 8 32,64-bit
Windows 7 32,64-bit
Windows 7 32,64-bit
Server 2008 R2 and later
Server 2008 R2 and later
Windows CE 4.2 and later
Windows CE 4.2 and later
Mac OS-X
Mac OS-X
Linux 3.2 and greater
Linux 2.6 and greater
Android
Android
The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com).
Various 3rd party drivers are also available for other operating systems - see FTDI website
(www.ftdichip.com) for details.
For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm
1.2 Part Numbers
Part Number
Package
FT220XQ-x
16 Pin QFN
FT220XS-x
16 Pin SSOP
Note: Packing codes for x is:
- R: Taped and Reel, (SSOP is 3,000pcs per reel, QFN is 5,000pcs per reel).
- U: Tube packing, 100pcs per tube (SSOP only)
- T: Tray packing, 490pcs per tray (QFN only)
For example: FT220XQ-R is 5,000pcs taped and reel packing
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
1.3 USB Compliant
The FT220X is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID)
40001461 (Rev D).
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
2 FT220X Block Diagram
VCC
1V8 Internal
Core Supply
3V3OUT
USBDP
USBDM
3.3 Volt LDO
Regulator
USB
Transceiver
with
Integrated
1.5k pullups
and battery
charge
detection
1.8 Volt LDO
Regulator
FIFO RX Buffer
(512 bytes)
VCCIO
MIOSI[0]
MIOSI[1]
MIOSI[2]
MIOSI[3]
Serial Interface
Engine
(SIE)
USB
Protocol Engine
FT1248
Controller
CLK
CS#
MISO
CBUS3
Internal MTP
Memory
USB DPLL
FIFO TX Buffer
(512 bytes)
Internal
12MHz
Oscillator
3V3OUT
RESET#
X4 Clock
Multiplier
Reset
Generator
48MHz
To USB Transceiver Cell
GND
Figure 2.1 FT220X Block Diagram
For a description of each function please refer to Section 4.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Table of Contents
1
Typical Applications....................................................... 2
1.1
Driver Support ........................................................................... 2
1.2
Part Numbers ............................................................................. 2
1.3
USB Compliant ........................................................................... 3
2
FT220X Block Diagram .................................................. 4
3
Device Pin Out and Signal Description ........................... 7
3.1
16-LD QFN Package .................................................................. 7
3.1.1
3.2
16-LD SSOP Package ................................................................. 8
3.2.1
3.3
4
QFN Package Pinout Description .................................................................... 7
SSOP Package Pinout Description .................................................................. 8
CBUS Signal Options ................................................................ 10
Function Description ................................................... 11
4.1
Key Features ............................................................................ 11
4.2
Functional Block Descriptions .................................................. 11
5
FT1248 Interface Description ...................................... 13
5.1
Determining the Dynamic Bus Width ....................................... 13
5.2
Supported Commands on the FT1248 Interface ....................... 14
5.3
LSB or MSB Selection ............................................................... 15
5.4
Clock Phase/Polarity ............................................................... 15
5.4.1
5.5
6
CPHA = 1 ................................................................................................. 16
FT1248 Timing ......................................................................... 17
Devices Characteristics and Ratings ............................ 19
6.1
Absolute Maximum Ratings ...................................................... 19
6.2
ESD and Latch-up Specifications .............................................. 20
6.3
DC Characteristics .................................................................... 20
6.4
MTP Memory Reliability Characteristics ................................... 24
6.5
Internal Clock Characteristics .................................................. 24
7
USB Power Configurations ........................................... 25
7.1
USB Bus Powered Configuration ............................................. 25
7.2
Self Powered Configuration ..................................................... 26
7.3
USB Bus Powered with Power Switching Configuration ........... 27
7.4
USB Battery Charging Detection .............................................. 28
8
Application Examples .................................................. 30
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
8.1
9
USB to FT1248 Converter ......................................................... 30
Internal MTP Memory Configuration ............................ 32
9.1
Default Values ......................................................................... 32
9.2
Method of Programming the MTP Memory ............................... 33
9.2.1
Programming the MTP memory over USB ..................................................... 33
9.3
Memory Map ............................................................................ 33
9.4
Hardware Requirements .......................................................... 34
10 Package Parameters .................................................... 35
10.1
SSOP-16 Package Mechanical Dimensions ............................. 35
10.2
SSOP-16 Package Markings ................................................... 36
10.3
QFN-16 Package Mechanical Dimensions............................... 37
10.4
QFN-16 Package Markings ..................................................... 38
10.5
Solder Reflow Profile ............................................................. 38
11 Contact Information .................................................... 40
Appendix A – References ................................................... 41
Document References ...................................................................... 41
Acronyms and Abbreviations............................................................ 41
Appendix B - List of Figures and Tables ............................. 42
List of Figures .................................................................................. 42
List of Tables.................................................................................... 42
Appendix C - Revision History ............................................ 44
Copyright © Future Technology Devices International Limited
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
3 Device Pin Out and Signal Description
3V3OUT
7
6
1
VCCIO
8
VCC
10
3.1 16-LD QFN Package
9
CLK
CS#
MISO
CBUS3
15
2
16
4
12
11
5
14
3
13
17
RESET#
GND
GND
GND
USBDM
USBDP
MIOSI0
MIOSI1
MIOSI2
MIOSI3
Figure 3.1 QFN Schematic Symbol
3.1.1
QFN Package Pinout Description
Note: # denotes an active low signal.
Pin No.
10
1
8
3, 13
Name
**
VCC
VCCIO
**
3V3OUT
GND
Type
Description
POWER Input
POWER
5 V (or 3V3) supply to IC
1V8 - 3V3 supply for the IO cells
Input
3V3 output at 50mA. May be used to power VCCIO.
POWER Output
POWER
Input
When VCC is 3V3; pin 8 is an input pin. Connect to pin 10.
0V Ground input.
Table 3.1 Power and Ground
*Pin 17 is centre pad on base of chip package. Connect to GND.
** If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input
Pin No.
Name
Type
Description
7
USBDM
INPUT
USB Data Signal Minus.
6
USBDP
INPUT
USB Data Signal Plus.
9
RESET#
INPUT
Reset input (active low).
Table 3.2 Common Function pins
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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Document No.: FT_000629 Clearance No.: FTDI# 262
Pin
No.
Name
Type
15
MIOSI[0]
I/O
Bi-Directional data bit 0
2
MIOSI[1]
I/O
Bi-Directional data bit 1
16
MIOSI[2]
I/O
Bi-Directional data bit 2
4
MIOSI[3]
I/O
Bi-Directional data bit 3
12
CLK
Input
Clock input from FT1248 interface master
11
CS#
Input
Chip select input to enable the device interface. Active low logic.
5
MISO
Output
14
CBUS3
I/O
Description
Master In Slave Out. Used to provide status information to the FT1248
interface master.
Configurable CBUS I/O Pin. Function of this pin is configured in the device
MTP memory. See CBUS Signal Options, Table 3.7.
Table 3.3 FT1248 Interface and CBUS Group (see note 1)
Notes:
1. When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors.
These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an
option in the MTP memory.
3
VCCIO
GND
RESET#
5
11
USBDM
USBDP
1
4
2
6
MIOSI0
MIOSI1
MIOSI2
MIOSI3
15
14
7
16
CLK
CS#
MISO
CBUS3
13
9
8
3V3OUT
GND
10
VCC
12
3.2 16-LD SSOP Package
Figure 3.2 SSOP Schematic Symbol
3.2.1
SSOP Package Pinout Description
Note: # denotes an active low signal.
Pin No.
12
Name
**
VCC
Type
POWER Input
Description
5 V (or 3V3) supply to IC
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
3
POWER
VCCIO
3V3 output at 50mA. May be used to power VCCIO.
**
10
3V3OUT
5, 13
1V8 - 3V3 supply for the IO cells
Input
POWER Output
POWER
GND
Input
When VCC is 3V3; pin 10 is an input pin. Connect to pin 12.
0V Ground input.
Table 3.4 Power and Ground
** If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input
Pin No.
Name
Type
Description
9
USBDM
INPUT
USB Data Signal Minus.
8
USBDP
INPUT
USB Data Signal Plus.
11
RESET#
INPUT
Reset input (active low).
Table 3.5 Common Function pins
Pin
No.
Name
Type
1
MIOSI[0]
I/O
Bi-Directional data bit 0
4
MIOSI[1]
I/O
Bi-Directional data bit 1
2
MIOSI[2]
I/O
Bi-Directional data bit 2
6
MIOSI[3]
I/O
Bi-Directional data bit 3
15
CLK
Input
Clock input from FT1248 interface master
14
CS#
Input
Chip select input to enable the device interface. Active low logic.
7
MISO
Output
16
CBUS3
I/O
Description
Master In Slave Out. Used to provide status information to the FT1248
interface master.
Configurable CBUS I/O Pin. Function of this pin is configured in the device
MTP memory. See CBUS Signal Options, Table 3.7.
Table 3.6 FT1248 Interface and CBUS Group (see note 1)
Notes:
1. When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors.
These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an
option in the MTP memory.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
3.3 CBUS Signal Options
The following options can be configured on the CBUS I/O pin. CBUS signal options are common to both
package versions of the FT220X. These options can be configured in the internal MTP memory using the
software utility FT_PROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The
default configuration is described in Section 9.
CBUS Signal
Option
Available
On CBUS
Pin
TRI-STATE
CBUS3
IO Pad is tri-stated
DRIVE 1
CBUS3
Output a constant 1
DRIVE 0
CBUS3
Output a constant 0
PWREN#
CBUS3
Output is low after the device has been configured by USB, then high
during USB suspend mode. This output can be used to control power to
external logic P-Channel logic level MOSFET switch. Enable the interface
pull-down option when using the PWREN# in this way.
SLEEP#
CBUS3
Goes low during USB suspend mode. Typically used to power down an
external TTL to RS232 level converter IC in USB to RS232 converter
designs.
CLK24MHz
CBUS3
24 MHz Clock output.*
CLK12MHz
CBUS3
12 MHz Clock output.*
CLK6MHz
CBUS3
6 MHz Clock output.*
GPIO
CBUS3
CBUS bit bang mode option. Allows the CBUS pins to be used as
general purpose I/O. Configured in the internal MTP memory. A
separate application note, AN232R-01, available from FTDI website
(www.ftdichip.com) describes in more detail how to use CBUS bit bang
mode.
BCD Charger
CBUS3
Battery Charger Detect, indicates when the device is connected to a
dedicated battery charger port. Active high output.
BCD Charger#
CBUS3
Inverse of BCD Charger (open drain)
BitBang_WR#
CBUS3
Synchronous and asynchronous bit bang mode WR# strobe output.
BitBang_RD#
CBUS3
Synchronous and asynchronous bit bang mode RD# strobe output.
VBUS Sense
CBUS3
Input to detect when VBUS is present.
Time Stamp
CBUS3
Toggle signal which changes state each time a USB SOF is received
Keep_Awake#
CBUS3
Prevents the device from entering suspend state when unplugged.
Description
Table 3.7 CBUS Configuration Control
*When in USB suspend mode the outputs clocks are also suspended.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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Document No.: FT_000629 Clearance No.: FTDI# 262
4 Function Description
The FT220X is a USB to FTDI Proprietary FT1248 interface device which simplifies USB implementations
and reduces external component count by fully integrating an MTP memory and an integrated clock
circuit which requires no external crystal. It has been designed to operate efficiently with USB host
controllers by using as little bandwidth as possible when compared to the total USB bandwidth available.
4.1 Key Features
Functional Integration. Fully integrated MTP memory, clock generation, AVCC filtering, Power-OnReset and LDO regulator.
Configurable CBUS I/O Pin Options. The fully integrated MTP memory allows configuration of the
Control Bus (CBUS) functionality and drive strength selection. There is 1 configurable CBUS I/O pin. The
configurable options are defined in section 3.3.
The CBUS line can be configured with any one of these output options by setting bits in the internal MTP
memory. The device is supplied with the most commonly used pin definitions pre-programmed - see
Section 9 for details.
Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT220X supports FTDI’s previous
chip generation bit-bang mode. In bit-bang mode, the 4 MIOSI data lines can be switched from the
regular interface mode to a 4-bit general purpose I/O port. Data packets can be sent to the device and
they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the
baud rate pre-scalar).
Synchronous Bit Bang Mode. The FT220X supports synchronous bit bang mode. This mode differs from
asynchronous bit bang mode in that the interface pins are only read when the device is written to. This
makes it easier for the controlling program to measure the response to an output stimulus as the data
returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website
(www.ftdichip.com) describes this feature.
Source Power and Power Consumption. The FT220X is capable of operating at a voltage supply
between +3.3V and +5.25V with a nominal operational mode current of 8mA and a nominal USB suspend
mode current of 125µA. This allows greater margin for peripheral designs to meet the USB suspend mode
current limit of 2.5mA. An integrated level converter within the FT1248 interface allows the FT220X to
interface to logic running at +1.8V, 2.5V, +3.3V or +5V. (Note: External pull-ups are recommended for
IO ± 2kV
Machine mode (MM)
> ± 200V
Charged Device Mode (CDM)
> ± 500V
Latch-up
> ± 200mA
Table 6.2 ESD and Latch-Up Specifications
6.3 DC Characteristics
DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
VCC
VCC Operating
Supply Voltage
2.97
5
5.5
V
Normal Operation
VCC2
VCCIO
Operating
Supply Voltage
1.62
---
3.63
V
Icc1
Operating
Supply Current
9.7
10.5
12.3
mA
Normal Operation
Icc2
Operating
Supply Current
μA
USB Suspend
3V3
3.3v regulator
output
V
VCC must be greater than
3V3 otherwise 3V3OUT is an
input which must be driven
with 3.3V
125
2.97
3.3
3.63
Table 6.3 Operating Voltage and Current
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Ioh = +/-2mA
Voh
2.97
VCCIO
VCCIO
V
2.97
VCCIO
VCCIO
V
I/O Drive
strength* = 8mA
2.97
VCCIO
VCCIO
V
I/O Drive
strength* =
12mA
2.97
VCCIO
VCCIO
V
I/O Drive
strength* =
16mA
Output Voltage High
Copyright © Future Technology Devices International Limited
I/O Drive
strength* = 4mA
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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Document No.: FT_000629 Clearance No.: FTDI# 262
Iol = +/-2mA
Vol
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
Vt+
0.4
V
0
0.4
V
I/O Drive
strength* = 8mA
0
0.4
V
I/O Drive
strength* =
12mA
0
0.4
V
I/O Drive
strength* =
16mA
0.8
V
LVTTL
V
LVTTL
1.49
V
LVTTL
1.15
V
1.64
V
Output Voltage Low
Vil
Vt-
0
2.0
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive
going threshold voltage
I/O Drive
strength* = 4mA
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down resistance
40
75
190
KΩ
Vin =VCCIO
Iin
Input Leakage Current
-10
+/-1
10
μA
Vin = 0
Ioz
Tri-state output leakage
-10
+/-1
10
μA
Vin = 5.5V or 0
current
Table 6.4 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins)
* The I/O drive strength and slow slew-rate are configurable in the MTP memory.
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
2.25
VCCIO
VCCIO
V
2.25
VCCIO
VCCIO
V
I/O Drive
strength* = 8mA
2.25
VCCIO
VCCIO
V
I/O Drive
strength* =
12mA
2.25
VCCIO
VCCIO
V
I/O Drive
strength* =
16mA
0
0.4
V
Ioh = +/-2mA
Voh
Vol
Output Voltage High
Output Voltage Low
I/O Drive
strength* = 4mA
Iol = +/-2mA
I/O Drive
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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strength* = 4mA
Vil
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
VtVt+
0
0.4
V
I/O Drive
strength* = 8mA
0
0.4
V
I/O Drive
strength* =
12mA
0
0.4
V
I/O Drive
strength* =
16mA
0.8
V
LVTTL
V
LVTTL
1.1
V
LVTTL
0.8
V
1.2
V
0.8
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive
going threshold voltage
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down resistance
40
75
190
KΩ
Vin =VCCIO
Iin
Input Leakage Current
-10
+/-1
10
μA
Vin = 0
Ioz
Tri-state output leakage
-10
+/-1
10
μA
Vin = 5.5V or 0
current
Table 6.5 I/O Pin Characteristics VCCIO = +2.5V (except USB PHY pins)
* The I/O drive strength and slow slew-rate are configurable in the MTP memory.
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Ioh = +/-2mA
Voh
1.62
VCCIO
VCCIO
V
1.62
VCCIO
VCCIO
V
I/O Drive
strength* = 8mA
1.62
VCCIO
VCCIO
V
I/O Drive
strength* =
12mA
1.62
VCCIO
VCCIO
V
I/O Drive
strength* =
16mA
0
0.4
V
I/O Drive
strength* = 4mA
0
0.4
V
I/O Drive
Output Voltage High
I/O Drive
strength* = 4mA
Iol = +/-2mA
Vol
Output Voltage Low
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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strength* = 8mA
Vil
Input low Switching
Threshold
Vih
Input High Switching
Threshold
Vt
Switching Threshold
VtVt+
0
0.4
V
I/O Drive
strength* =
12mA
0
0.4
V
I/O Drive
strength* =
16mA
0.77
V
LVTTL
V
LVTTL
0.77
V
LVTTL
0.557
V
0.893
V
1.6
Schmitt trigger negative
going threshold voltage
Schmitt trigger positive
going threshold voltage
Rpu
Input pull-up resistance
40
75
190
KΩ
Vin = 0
Rpd
Input pull-down resistance
40
75
190
KΩ
Vin =VCCIO
Iin
Input Leakage Current
-10
+/-1
10
μA
Vin = 0
Ioz
Tri-state output leakage
-10
+/-1
10
μA
Vin = 5.5V or 0
current
Table 6.6 I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins)
* The I/O drive strength and slow slew-rate are configurable in the MTP memory.
Parameter
Description
Minimum
Voh
Output Voltage High
VCC-0.2
Vol
Output Voltage Low
Vil
Input low Switching Threshold
Vih
Input High Switching Threshold
Typical
Units
Conditions
V
2.0
Maximum
0.2
V
0.8
V
-
V
Table 6.7 USB I/O Pin (USBDP, USBDM) Characteristics
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6.4 MTP Memory Reliability Characteristics
The internal 2048 Bytes MTP memory has the following reliability characteristics:
Parameter
Value
Unit
Data Retention
10
Years
Write Cycle
2,000
Cycles
Read Cycle
Unlimited
Cycles
Table 6.8 MTP Memory Characteristics
6.5 Internal Clock Characteristics
The internal Clock Oscillator has the following characteristics:
Value
Parameter
Unit
Minimum
Typical
Maximum
Frequency of Operation (see Note 1)
11.98
12.00
12.02
MHz
Clock Period
83.19
83.33
83.47
ns
Duty Cycle
45
50
55
%
Table 6.9 Internal Clock Characteristics
Note 1: Equivalent to +/-1667ppm
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7 USB Power Configurations
The following sections illustrate possible USB power configurations for the FT220X. The illustrations have
omitted pin numbers for ease of understanding since the pins differ between the FT220XS and FT220XQ
package options.
All USB power configurations illustrated apply to both package options for the FT220X device. Please refer
to Section 3 for the package option pin-out and signal descriptions.
7.1 USB Bus Powered Configuration
VCC
Ferrite
Bead
1
VCC
27R
2
USBDM
3
27R
USBDP
4
5
47pF
FT220X
47pF
RESET#
SHIELD
VCCIO
GND
10nF
GND
VCC
GN
D
AG
ND
3V3OUT
100nF
+
4.7uF
100nF
GND
GND
Figure 7.1 Bus Powered Configuration
Figure 7.1 Illustrates the FT220X in a typical USB bus powered design configuration. A USB bus powered
device gets its power from the USB bus. Basic rules for USB bus power devices are as follows –
i)
ii)
iii)
iv)
v)
On plug-in to USB, the device should draw no more current than 100mA.
In USB Suspend mode the device should draw no more than 2.5mA.
A bus powered high power USB device (one that draws more than 100mA) should use one of
the CBUS pins configured as PWREN# and use it to keep the current below 100mA on plug-in
and 2.5mA on USB suspend.
A device that consumes more than 100mA cannot be plugged into a USB bus powered hub.
No device can draw more than 500mA from the USB bus.
The power descriptors in the internal MTP memory of the FT220X should be programmed to match the
current drawn by the device.
A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT220X and
associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead
depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from
Steward (www.steward.com), for example Steward Part # MI0805K400R-10.
Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ
resistor.
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7.2 Self Powered Configuration
VCC(3.3-5.25V)
1
VCC
27R
2
USBDM
27R
3
USBDP
4
47pF
47pF
4k7
FT220X
5
RESET#
SHIELD
VCCIO
GND
10k
GND
GND
GN
D
AG
ND
3V3OUT
VCC
100nF
100nF
100nF
+
4.7uF
GND
GND
Figure 7.2 Self Powered Configuration
Figure 7.2 illustrates the FT220X in a typical USB self-powered configuration. A USB self-powered device
gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic
rules for USB self-powered devices are as follows –
i)
ii)
iii)
A self-powered device should not force current down the USB bus when the USB host or hub
controller is powered down.
A self-powered device can use as much current as it needs during normal operation and USB
suspend as it has its own power supply.
A self-powered device can be used with any USB host, a bus powered USB hub or a selfpowered USB hub.
The power descriptor in the internal MTP memory of the FT220X should be programmed to a value of
zero (self-powered).
In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the
VBUS_Sense pin of the FT220X device. When the USB host or hub is powered up an internal 1.5kΩ
resistor on USBDP is pulled up to +3.3V, thus identifying the device as a full speed device to the USB
host or hub. When the USB host or hub is powered off, VBUS_Sense pin will be low and the FT220X is
held in a suspend state. In this state the internal 1.5kΩ resistor is not pulled up to any power supply
(hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to
do this may cause some USB host or hub controllers to power up erratically.
Figure 7.2 illustrates a self-powered design which has a +3.3V to +5.25V supply.
Note:
1. When the FT220X is in reset, the FT1248 interface I/O pins are tri-stated. Input pins have
internal 75kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some
external logic.
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7.3 USB Bus Powered with Power Switching Configuration
P Channel Power
MOSFET
Switched 5V Power to
External Logic
0.1uF
0.1uF
100k
1k
PWREN#
Ferrite
Bead
1
VCC
27R
2
USBDM
3
27R
USBDP
4
47pF
47pF
FT220X
5
SHIELD
RESET#
10nF
VCCIO
GND
VCC
CBUS3
GN
D
AG
ND
3V3OUT
GND
100nF
+
4.7uF
100nF
GND
Figure 7.3 Bus Powered with Power Switching Configuration
A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a
total current of less than 2.5mA. This requirement includes external logic. Some external logic has the
ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic
that cannot power itself down in this way, the FT220X provides a simple but effective method of turning
off power during the USB suspend mode.
Figure 7.3 shows an example of using a discrete P-Channel MOSFET to control the power to external
logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It
is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used
to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the
transient power surge, caused when the MOSFET switches on, will reset the FT220X or the USB host/hub
controller. The soft start circuit example shown in Figure 7.3 powers up with a slew rate of
approximaely12.5V/Ms. Thus supply voltage to external logic transitions from GND to +5V in
approximately 400 microseconds.
As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A
suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or
equivalent.
With power switching controlled designs the following should be noted:
i)
The external logic to which the power is being switched should have its own reset circuitry to
automatically reset the logic when power is re-applied when moving out of suspend mode.
ii) Set the Pull-down on Suspend option in the internal FT220X MTP memory.
iii) One of the CBUS Pins should be configured as PWREN# in the internal FT220X MTP memory, and
used to switch the power supply to the external circuitry.
iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up
to 500mA of current from the USB bus), the power consumption of the application must be set in
the Max Power field in the internal FT220X MTP memory. A high-power bus powered application
uses the descriptor in the internal FT220X MTP memory to inform the system of its power
requirements.
v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered
down using the external logic. In this case use the +3V3OUT.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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7.4 USB Battery Charging Detection
A
recent
addition
to
the
USB
specification
(http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip ) is to allow for additional charging
profiles to be used for charging batteries in portable devices. These charging profiles do not enumerate
the USB port of the peripheral. The FT220X device will detect that a USB compliant dedicated charging
port (DCP) is connected. Once detected while in suspend mode a battery charge detection signal is then
provided to allow external logic to switch to charging mode as opposed to operation mode.
VBUS
3V3OUT
VBUS
VBUS
DD+
ID
GND
1
2
3
4
5
VBUS
0.1uF
GND
DM
DP
27R
27R
3V3OUT
0.1uF
VCCIO
3V3OUT
VCC
600R/2A
CN USB
3V3OUT
GND
RESET#
10nF
N.F.
GND
GND
0.1uF
0R
BCD
CBUS3
FT220X
SLD
GND
GND
GND
VBUS VBUS
GND
VBUS
VBATT
4.7uF
0.1uF
GND
1
2
3
4
5
GND
CHRG
VCC
FAULT
TIMER
GND
ACPR
BAT
SHDN
PROG
NTC
GND
0.1uF
10
9
8
7
6
1
+
NCT
TB3.5mm
BCD
NTC
LTC4053EDD
11
2K2
1uF
1K5
1R
GND
GND
GND
GND
GND
EEPROM Setting
X-Chip Pin
CBUS3
Function
BCD
Battery Options
GND GND
1A when connected to a dedicated charger port
0A when enumerated
0A when not enumerated and not in sleep
0A when in sleep
VBUS
Battery Charger Enable X
Force Power Enable
NTC
JP1
NCT Available
4K32 1%
De-acticate Sleep
JUMPER-2mm
JP1
SIP-3
1-2
2-3
NCT Enabled
NCT Disabled (Default)
GND
Figure 7.4 USB Battery Charging Detection
To use the FT220X with battery charging detection the CBUS pin must be reprogrammed to allow for the
BCD Charger output to switch the external charger circuitry on. The CBUS pins are configured in the
internal MTP memory with the free utility FT_PROG. If the charging circuitry requires an active low signal
to enable it, the CBUS pin can be programmed to BCD Charger# as an alternative.
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When connected to a USB compliant dedicated charging port (DCP, as opposed to a standard USB host)
the device USB signals will be shorted together and the device suspended. The BCD charger signal will
bring the LTC4053 out of suspend and allow battery charging to start. The charge current in the example
above is 1A as defined by the resistance on the PROG pin.
To calculate the equivalent resistance on the LTC4053 PROG pin select a charge current, then Res =
1500V/Ichg
For more configuration options of the LTC4053 refer to:
AN_175_Battery Charging Over USB
Note: If the FT220X is connected to a standard host port such that the device is enumerated the battery
charge detection signal is inactive as the device will not be in suspend.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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8 Application Examples
The following sections illustrate possible applications of the FT220X. The illustrations have omitted pin
numbers for ease of understanding since the pins differ between the FT220XS and FT220XQ package
options.
8.1 USB to FT1248 Converter
VCCIO
10k
10k
FT220X
MIOSIO[0]
10k
10k
SCLK
FT1248 BUS
MASTER
SS_N
MISO
Figure 8.1 Application Example showing USB to FT1248 host
The FT1248 can be used with 1-bit. 2-bit, or 4-bit wide data. The Figure 8.1 is showing 1 bit mode. By
using 4 data bits you need fewer clock cycles to get the data across.
The FT220X is the slave device and the external FPGA/MCU is the bus master. The FT220X will auto
detect the bus width from the initial command byte sent by the controller. If not using all 4 data lines the
pins may be left unterminated as an internal pull-up ensures the device detects logic 1.
Timing diagrams for 1-bit accesses can be seen in figures 8.2 and 8.3.
For further information on the mode see AN_167 FT1248 Basics from the FTDI website.
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CLK
SS_n
COMMAND PHASE
WRITE DATA
BUS TURNAROUND
MIOSIO[0]
TXE#
CMD3
0
0
BUS TURNAROUND
CMD2
0
CMD1 CMD0
B6
B5
B4
B3
B2
B1
B0
TXE#
PULLED HIGH
MIOSIO[7:1]
MISO
B7
BUS TURNAROUND
RXF#
TXE#
RXF#
ACK
Figure 8.2 FT1248 1- bit write timing diagram
CLK
SS_n
COMMAND PHASE
READ DATA
BUS TURNAROUND
MIOSIO[0]
TXE#
0
0
CMD2
0
CMD1 CMD0
B7
B6
B5
B4
B3
B2
B1
B0
TXE#
PULLED HIGH
MIOSIO[7:1]
MISO
CMD3
BUS TURNAROUND
RXF#
RXF#
ACK
RXF#
Figure 8.3 FT1248 1- bit read timing diagram
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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9 Internal MTP Memory Configuration
The FT220X includes an internal MTP memory which holds the USB configuration descriptors, other
configuration data for the chip and also user data areas. Following a power-on reset or a USB reset the
FT220X will scan its internal MTP memory and read the USB configuration descriptors stored there.
In many cases, the default values programmed into the MTP memory will be suitable and no reprogramming will be necessary. The defaults can be found in Section 9.1.
The MTP memory in the FT220X can be programmed over USB if the values need to be changed for a
particular application. Further details of this are provided from section 9.2 onwards.
Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their
design can apply to FTDI for a free block of unique PIDs. See TN_100 – USB Vendor ID/Product ID
Guidelines for more details.
9.1 Default Values
The default factory programmed values of the internal MTP memory are shown in Table 9.1.
Parameter
Value
Notes
USB Vendor ID (VID)
0403h
FTDI default VID (hex)
USB Product UD (PID)
6015h
FTDI default PID (hex)
Serial Number
Enabled?
Yes
Serial Number
See Note
A unique serial number is generated and programmed into
the MTP memory during device final test.
Pull down I/O Pins in
USB Suspend
Disabled
Enabling this option will make the device pull down on the
UART interface lines when in USB suspend mode (PWREN# is
high).
Manufacturer Name
FTDI
Product Description
FT220X 4-BIT
FT1248
Max Bus Power
Current
90mA
Power Source
Bus Powered
Device Type
FT220X
Returns USB 2.0 device description to the host.
USB Version
0200
Remote Wake Up
Disabled
DBUS Drive Current
Strength
4mA
Options are 4mA, 8mA, 12mA, 16mA
DBUS slew rate
Slow
Options are slow or fast
Note: The device is a USB 2.0 Full Speed device (12Mb/s) as
opposed to a USB 2.0 High Speed device (480Mb/s).
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Parameter
Value
Notes
DBUS Schmitt Trigger
Enable
Normal
Options are normal or Schmitt
CBUS Drive Current
Strength
4mA
Options are 4mA, 8mA, 12mA, 16mA
CBUS slew rate
Slow
Options are slow or fast
CBUS Schmitt Trigger
Enable
Normal
Load VCP Driver
Disabled
CBUS3
Keep_Awake#
Options are normal or Schmitt
Enabling this will load the VCP driver interface for the device.
Prevents the device from entering suspend state when
unplugged.
Table 9.1 Default Internal MTP Memory Configuration
9.2 Method of Programming the MTP Memory
9.2.1
Programming the MTP memory over USB
The MTP memory on all FT-X devices can be programmed over USB. This method is the same as for the
EEPROM on other FTDI devices such as the FT232R. No additional hardware, connections or programming
voltages are required. The device is simply connected to the host computer in the same way that it would
be for normal applications, and the FT_Prog utility is used to set the required options and program the
device.
The FT_Prog utility is provided free-of-charge from the FTDI website, and can be found at the link below.
The user guide is also available at this link.
http://www.ftdichip.com/Support/Utilities.htm#FT_Prog
Additionally, D2XX commands can be used to program the MTP memory from within user applications.
For more information on the commands available, please see the D2XX Programmers Guide below.
9.3 Memory Map
The FT-X family MTP memory has various areas which come under three main categories:
User Memory Area
Configuration Memory Area (writable)
Configuration Memory Area (non-writable)
Memory Area Description
Word Address
User Memory Area 2
Accessible via USB, I2C and FT1248
0x3FF - 0x80
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Configuration Memory Area
Accessible via USB, I2C and FT1248
0x7E - 0x50
Configuration Memory Area
Cannot be written
0x4E - 0x40
User Memory Area 1
Accessible via USB, I2C and FT1248
0x3E - 0x12
Configuration Memory Area
Accessible via USB, I2C and FT1248
0x10 - 0x00
Figure 9.1: Simplified Memory Map for the FT-X
User Memory Area
The User Memory Areas are highlighted in Green on the memory map. They can be read and written via
both USB and FT1248 on the FT220X. All locations within this range are freely programmable; no areas
have special functions and there is no checksum for the user area.
Note: The application should take into account the specification for the number of write cycles in Section
6.4 if it will be writing to the MTP memory multiple times.
Configuration Memory Area (writable)
This area stores the configuration data for the device, including the data which is returned to the host in
the configuration descriptors (e.g. the VID, PID and string descriptions) and also values which set the
hardware configuration (the signal assigned to each CBUS pin for example).
These values can have a significant effect on the behaviour of the device. Steps must be taken to ensure
that these locations are not written to un-intentionally by an application which is intended to access only
the user area.
This area is included in a checksum which covers configuration areas of the memory, and so changing
any value can also cause this checksum to fail.
Configuration Memory Area (non-writable)
This is a reserved area and the application should not write to this area of memory. Any attempt to write
these locations will fail.
9.4 Hardware Requirements
The hardware is the same as for a typical USB-FT1248 application and no additional hardware or
programming voltages are required. For the USB connections, either a bus-powered configuration (see
Section 7.1and 7.3) or a self-powered configuration (see Section 7.2) could be used.
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
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10
Package Parameters
The FT220X is available in two different packages. The FT220XS is the SSOP-16 option and the FT220XQ
is the QFN-16 package option. The solder reflow profile for both packages is described in Section 10.5.
10.1 SSOP-16 Package Mechanical Dimensions
Figure 10.1 SSOP-16 Package Dimensions
The FT220XS is supplied in a RoHS compliant 16 pin SSOP package. The package is lead (Pb) free and
uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 4.90mm x 3.91mm body (4.90mm x 5.99mm including pins). The pins are on a
0.635 mm pitch. The above mechanical drawing shows the SSOP-16 package.
All dimensions are in inches.
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10.2 SSOP-16 Package Markings
-B
FT220XS
Figure 10.2 SSOP-16 Package Markings
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is
followed by the revision number.
The code XXXXXXXXXXXX is the manufacturing LOT code.
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10.3 QFN-16 Package Mechanical Dimensions
Figure 10.3 QFN-16 Package Dimensions
The FT220XQ is supplied in a RoHS compliant leadless QFN-16 package. The package is lead (Pb) free,
and uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 4.00mm x 4.00mm. The solder pads are on a 0.65mm pitch. The above
mechanical drawing shows the QFN-16 package. All dimensions are in millimetres.
The centre pad on the base of the FT220XQ is internally connected to GND and the PCB should not have
signal tracking on the top layer under this area. Connect to GND.
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10.4 QFN-16 Package Markings
1
FTDI
I
XXXXXXXXXX
12
FT220XQ
YYWW-B
5
8
Figure 10.4 QFN-16 Package Markings
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is
followed by the revision number.
The code XXXXXXX is the manufacturing LOT code
10.5 Solder Reflow Profile
The FT220X is supplied in Pb free 16 LD SSOP and QFN-16 packages. The recommended solder reflow
profile for both package options is shown in Figure 10.5.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 10.5 FT220X Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Table 10.1. Values are shown for
both a completely Pb free solder process (i.e. the FT220X is used with Pb free solder), and for a non-Pb
free solder process (i.e. the FT220X is used with non-Pb free solder).
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Pb Free Solder
Profile Feature
Process
Average Ramp Up Rate (Ts to Tp)
Non-Pb Free Solder Process
3°C / second Max.
3°C / Second Max.
- Temperature Min (Ts Min.)
150°C
100°C
- Temperature Max (Ts Max.)
200°C
150°C
- Time (ts Min to ts Max)
60 to 120 seconds
60 to 120 seconds
217°C
183°C
60 to 150 seconds
60 to 150 seconds
260°C
240°C
20 to 40 seconds
20 to 40 seconds
6°C / second Max.
6°C / second Max.
8 minutes Max.
6 minutes Max.
Preheat
Time Maintained Above Critical
Temperature TL:
- Temperature (TL)
- Time (tL)
Peak Temperature (Tp)
Time within 5°C of actual Peak
Temperature (tp)
Ramp Down Rate
Time for T= 25°C to Peak
Temperature, Tp
Table 10.1 Reflow Profile Parameter Values
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11
Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
sales1@ftdichip.com
support1@ftdichip.com
admin1@ftdichip.com
Branch Office – Tigard, Oregon, USA
Future Technology Devices International Limited
(USA)
7130 SW Fir Loop
Tigard, OR 97223
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
E-Mail (General Enquiries)
us.sales@ftdichip.com
us.support@ftdichip.com
us.admin@ftdichip.com
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited
(Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8791 3570
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System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology
Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level
performance requirements. All application-related information in this document (including application descriptions, suggested
FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this
information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications
assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, a nd the
user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from
such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is
implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product
described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent
of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640
Copyright © Future Technology Devices International Limited
40
FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Appendix A – References
Document References
AN232R-01 FT232RBitBangModes
AN_107 Advanced Driver Options
AN_121 FTDI Device EEPROM User Area Usage
AN_167 FT1248 Parallel Serial Interface Basics
http://www.ftdichip.com/Documents/InstallGuides.htm
TN_100 USB VID-PID Guidelines
AN_175 Battery Charging Over USB with FTEX Devices
http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip
Acronyms and Abbreviations
Terms
Description
DCP
Dedicated Charging Port
FIFO
First In First Out
LSB
Least Significant Bit First
MSB
Most Significant Bit First
MTP
Multi-time Programmable memory
QFN
Quad Flat Non-leaded package
SIE
Serial Interface Engine
USB
Universal Serial Bus
UART
Universal Asynchronous Receiver / Transmitter
Copyright © Future Technology Devices International Limited
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FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Appendix B - List of Figures and Tables
List of Figures
Figure 2.1 FT220X Block Diagram ................................................................................................... 4
Figure 3.1 QFN Schematic Symbol .................................................................................................. 7
Figure 3.2 SSOP Schematic Symbol ................................................................................................ 8
Figure 5.1: FT1248 Basic Waveform Protocol.................................................................................. 13
Figure 5.2: FT1248 Command Structure ........................................................................................ 14
Figure 5.3: FT1248 Clock Format CPHA = 1 ................................................................................... 16
Figure 5.4: FT1248 Clock Format CPHA = 1 ................................................................................... 17
Figure 7.1 Bus Powered Configuration ........................................................................................... 25
Figure 7.2 Self Powered Configuration ........................................................................................... 26
Figure 7.3 Bus Powered with Power Switching Configuration ............................................................ 27
Figure 7.4 USB Battery Charging Detection .................................................................................... 28
Figure 8.1 Application Example showing USB to FT1248 host ........................................................... 30
Figure 8.2 FT1248 1- bit write timing diagram ................................................................................ 31
Figure 8.3 FT1248 1- bit read timing diagram ................................................................................ 31
Figure 9.1: Simplified Memory Map for the FT-X ............................................................................. 34
Figure 10.1 SSOP-16 Package Dimensions ..................................................................................... 35
Figure 10.2 SSOP-16 Package Markings ......................................................................................... 36
Figure 10.3 QFN-16 Package Dimensions ....................................................................................... 37
Figure 10.4 QFN-16 Package Markings .......................................................................................... 38
Figure 10.5 FT220X Solder Reflow Profile ....................................................................................... 38
List of Tables
Table 3.1 Power and Ground .......................................................................................................... 7
Table 3.2 Common Function pins .................................................................................................... 7
Table 3.3 FT1248 Interface and CBUS Group (see note 1).................................................................. 8
Table 3.4 Power and Ground .......................................................................................................... 9
Table 3.5 Common Function pins .................................................................................................... 9
Table 3.6 FT1248 Interface and CBUS Group (see note 1).................................................................. 9
Table 3.7 CBUS Configuration Control ........................................................................................... 10
Table 5.1: FT1248 Commands ...................................................................................................... 15
Table 5.2: CPOL & CPHA Mode Numbers ........................................................................................ 15
Table 5.3: 1V8 VCCIO timings ...................................................................................................... 17
Table 5.4: 2V5 VCCIO timings ...................................................................................................... 18
Table 5.5: 3V3 VCCIO timings ...................................................................................................... 18
Table 6.1 Absolute Maximum Ratings ............................................................................................ 19
Table 6.2 ESD and Latch-Up Specifications .................................................................................... 20
Table 6.3 Operating Voltage and Current ....................................................................................... 20
Table 6.4 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins) ........................................... 21
Copyright © Future Technology Devices International Limited
42
FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Table 6.5 I/O Pin Characteristics VCCIO = +2.5V (except USB PHY pins) ........................................... 22
Table 6.6 I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins) ........................................... 23
Table 6.7 USB I/O Pin (USBDP, USBDM) Characteristics .................................................................. 23
Table 6.8 MTP Memory Characteristics........................................................................................... 24
Table 6.9 Internal Clock Characteristics ......................................................................................... 24
Table 9.1 Default Internal MTP Memory Configuration ..................................................................... 33
Table 10.1 Reflow Profile Parameter Values .................................................................................... 39
Copyright © Future Technology Devices International Limited
43
FT220X USB 4-BIT SPI/FT1248 IC Datasheet
Version 1.4
Document No.: FT_000629 Clearance No.: FTDI# 262
Appendix C - Revision History
Document Title:
USB 4-BIT SPI/FT1248 IC FT220X
Document Reference No.:
FT_000629
Clearance No.:
FTDI# 262
Product Page:
http://www.ftdichip.com/FT-X.htm
Document Feedback:
Send Feedback
Revision
Changes
Date
Version 1.0
Initial Release
2012-02-08
Version 1.1
Added USB compliance in section 1.3; Clarified MTP Reliability in table
6.8; Edited EEPROM Table 9.1 changed Load VCP; Driver to Disabled
and edited Product Description
2012-04-17
Version 1.2
Removed references to LED signals on the CBUS pins as these are not
available on the FT220X; Removed section 8.2 showing connection of
the Tx/Rx LEDs; Updated TID; Updated US address; Added clarification
on front page about 5V tolerant
2013-02-14
Version 1.3
Removed references to MTP programming over FT1248 and Clarified
package dimensions.
2014-02-10
Version 1.4
Remove the incorrect typical application items and update the driver
support list
2018-05-07
Copyright © Future Technology Devices International Limited
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