FT232BM

FT232BM USB UART ( USB - Serial) I.C. The FT232BM is the 2nd generation of FTDI’s popular USB UART I.C. This device not only adds extra functionality to its FT8U232AM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas. 1.0 Features VIRTUAL COM PORT (VCP) DRIVERS for Windows 98 and Windows 98 SE Windows 2000 / ME / Server 2003 / XP Windows XP 64 Bit Windows XP Embedded Windows CE 4.2 MAC OS-8 and OS-9 MAC OS-X Linux 2.40 and greater Windows 98 and Windows 98 SE Windows 2000 / ME / Server 2003 / XP Windows XP 64 Bit Windows XP Embedded Windows CE 4.2 Linux 2.40 and greater USB RS232 Converters USB  RS422 / RS485 Converters Upgrading RS232 Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer cables and interfaces Interfacing MCU based designs to USB USB Audio and Low Bandwidth Video data transfer PDA  USB data transfer USB Smart Card Readers Set Top Box (S.T.B.) PC - USB interface USB Hardware Modems USB Wireless Modems USB Instrumentation USB Bar Code Readers Transfer HARDWARE FEATURES • Single Chip USB Asynchronous Serial Data • • • • • • • • • • • • • • • • • • • • • • • Full Handshaking & Modem Interface Signals UART I/F Supports 7 / 8 Bit Data, 1 / 2 Stop Bits and Odd/Even/Mark/Space/No Parity Data rate 300 => 3M Baud (TTL) Data rate 300 => 1M Baud (RS232) Data rate 300 => 3M Baud (RS422/RS485) 384 Byte Receive Buffer / 128 Byte Transmit Buffer for high data throughput Adjustable RX buffer timeout Fully Assisted Hardware or X-On / X-Off Handshaking In-built support for event characters and line break condition Auto Transmit Buffer control for RS485 Support for USB Suspend / Resume through SLEEP# and RI# pins Support for high power USB Bus powered devices through PWREN# pin Integrated level converter on UART and control signals for interfacing to 5V and 3.3V logic Integrated 3.3V regulator for USB IO Integrated Power-On-Reset circuit Integrated 6MHz – 48Mhz clock multiplier PLL USB Bulk or Isochronous data transfer modes 4.35V to 5.25V single supply operation UHCI / OHCI / EHCI host controller compatible USB 1.1 and USB 2.0 compatible USB VID, PID, Serial Number and Product Description strings in external EEPROM EEPROM programmable on-board via USB Compact 32-LD LQFP package D2XX (USB Direct Drivers + DLL S/W Interface) APPLICATION AREAS DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 1 of 25 FT232BM USB UART ( USB - Serial) I.C. 2.0 Enhancements This section summarises the enhancements of the 2nd generation device compared to its FT8U232AM predecessor. For further details, consult the device pin-out description and functional descriptions. • Integrated Power-On-Reset (POR) Circuit The device now incorporates an internal POR function. The existing RESET# pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now simply be hard wired to VCC. In addition, a new reset output pin (RSTOUT#) is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices. RSTOUT# was the TEST pin on the previous generation of devices. This gating is now done on-chip - USBEN has now been replaced with the new PWREN# signal which can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. A new EEPROM based option makes the device pull gently down its UART interface lines when the power is shut off (PWREN# is High). In this mode, any residual voltage on external circuitry is bled to GND when power is removed thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. • Integrated RCCLK Circuit In the previous devices, an external RC circuit was required to ensure that the oscillator and clock multiplier PLL frequency was stable prior to enabling the clock internal to the device. This circuit is now embedded on-chip – the pin assigned to this function is now designated as the TEST pin and should be tied to GND for normal operation. • Lower Suspend Current Integration of RCCLK within the device and internal design improvements reduce the suspend current of the FT232BM to under 200uA (excluding the 1.5k pull-up on USBDP) in USB suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of 500uA. • Support for USB Isochronous Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the new device now offers an option of USB Isochronous transfer via an option bit in the EEPROM. • Integrated Level Converter on UART interface and control signals The previous devices would drive the UART and control signals at 5V CMOS logic levels. The new device has a separate VCC-IO pin allowing the device to directly interface to 3.3V and other logic families without the need for external level converter I.C.’s • Improved Power Management control for USB Bus Powered, high current devices The previous devices had a USBEN pin, which became active when the device was enumerated by USB. To provide power control, this signal had to be externally gated with SLEEP# and RESET#. DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 2 of 25 FT232BM USB UART ( USB - Serial) I.C. • Programmable Receive Buffer Timeout In the previous device, the receive buffer timeout used to flush remaining data from the receive buffer was fixed at 16ms timeout. This timeout is now programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets. • TXDEN Timing fix TXDEN timing has now been fixed to remove the external delay that was previously required for RS485 applications at high baud rates. TXDEN now works correctly during a transmit send-break condition. • Relaxed VCC Decoupling The 2 generation devices now incorporate a level nd to the device and they will be sequentially sent to the interface at a rate controlled by the prescaler setting. As well as allowing the device to be used stand-alone as a general purpose IO controller for example controlling lights, relays and switches, some other interesting possibilities exist. For instance, it may be possible to connect the device to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use Bit Bang Mode to download configuration data to the FPGA which would define its hardware function, then after the FPGA device is configured the FT232BM can switch back into UART interface mode to allow the programmed FPGA device to communicate with the PC over USB. This approach allows a customer to create a “generic” USB peripheral who’s hardware function can be defined under control of the application software. The FPGA based hardware can be easily upgraded or totally changed simply by changing the FPGA configuration data file. Application notes, software and development modules for this application area will be available from FTDI and other 3rd parties. • PreScaler Divide By 1 Fix The previous device had a problem when the integer part of the divisor was set to 1. In the 2nd generation device setting the prescaler value to 1 gives a baud rate of 2 million baud and setting it to zero gives a baud rate of 3 million baud. Noninteger division is not supported with divisor values of 0 and 1. of on-chip VCC decoupling. Though this does not eliminate the need for external decoupling capacitors, it significantly improves the ease of PCB design requirements to meet FCC, CE and other EMI related specifications. • Improved PreScaler Granularity The previous version of the Prescaler supported division by (n + 0), (n + 0.125), (n + 0.25) and (n + 0.5) where n is an integer between 2 and 16,384 (2 ). To this we have added (n + 0.375), (n + 0.625), (n + 0.75) and (n+ 0.875) which can be used to improve the accuracy of some baud rates and generate new baud rates which were previously impossible (especially with higher baud rates). • Bit Bang Mode The 2nd generation device has a new option referred to as “Bit Bang” mode. In Bit Bang mode, the eight UART interface control lines can be switched between UART interface mode and an 8-bit Parallel IO port. Data packets can be sent 14 DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 3 of 25 FT232BM USB UART ( USB - Serial) I.C. • Less External Support Components As well as eliminating the RCCLK RC network, and for most applications the need for an external reset circuit, we have also eliminated the requirement for a 100K pull-up on EECS to select 6MHz operation. When the FT232BM is being used without the configuration EEPROM, EECS, EESK and EEDATA can now be left n/c. For circuits requiring a long reset time (where the device is reset externally using a reset generator I.C., or reset is controlled by the IO port of a MCU, FPGA or ASIC device) an external transistor circuit is no longer required as the 1.5k pull-up resistor on USBDP can be wired to the RSTOUT# pin instead of to 3.3V. Note : RSTOUT# drives out at 3.3V level, not at 5V VCC level. This is the preferred configuration for new designs. • Extended EEPROM Support The previous generation of devices only supported EEPROM of type 93C46 (64 x 16 bit). The new devices will also work with EEPROM type 93C56 (128 x 16 bit) and 93C66 (256 x 16 bit). The extra space is not used by the device, however it is available for use by other external MCU / logic whilst the FT232BM is being held in reset. • USB 2.0 (full speed option) A new EEPROM based option allows the FT232BM to return a USB 2.0 device descriptor as opposed to USB 1.1. Note : The device would be a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). • Multiple Device Support without EEPROM When no EEPROM (or a blank or invalid EEPROM) is attached to the device, the FT232BM no longer gives a serial number as part of its USB descriptor. This allows multiple devices to be simultaneously connected to the same PC. However, we still highly recommend that EEPROM is used, as without serial numbers a device can only be identified by which hub port in the USB tree it is connected to which can change if the end user re-plugs the device into a different port. DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 4 of 25 FT232BM USB UART ( USB - Serial) I.C. 3.0 VCC Block Diagram (Simplified) PWRCTL SLEEP# PWREN# Dual Port TX Buffer 128 bytes 48MHz Baud Rate Generator 3V3OUT 3.3 Volt LDO Regulator USBDP USB Transceiver USBDM Serial Interface Engine ( SIE ) USB Protocol Engine UART FIFO Controller UART TXD RXD RTS# CTS# DTR# DSR# DCD# RI# TXDEN TXLED# RXLED# Dual Port RX Buffer 384 Bytes USB DPLL 3V3OUT EEPROM Interface EECS EESK EEDATA XTOUT 6MHZ Oscillator x8 Clock Multiplier 48MHz XTIN 12MHz RESET# RESET GENERATOR RSTOUT# TEST GND 3.1 • Functional Block Descriptions 3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power from the 3V3OUT pin if required. USB Transceiver The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. • USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block. 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz crystal or ceramic resonator. • • DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 5 of 25 FT232BM USB UART ( USB - Serial) I.C. • x8 Clock Multiplier The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks. Serial Interface Engine (SIE) The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / unstuffing and CRC5 / CRC16 generation / checking on the USB data stream. USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the UART. Dual Port TX Buffer (128 bytes) Data from the USB data out endpoint is stored in the Dual Port TX buffer and removed from the buffer to the UART transmit register under control of the UART FIFO controller. Dual Port RX Buffer (384 bytes) Data from the UART receive register is stored in the Dual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint. UART FIFO Controller The UART FIFO controller handles the transfer of data between the Dual Port RX and TX buffers and the UART transmit and receive registers. UART The UART performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the data on the RS232 (RS422 and RS485) interface. Control signals supported by the UART include RTS, CTS, DSR , DTR, DCD and RI. The UART provides a transmitter enable control signal (TXDEN) to assist with interfacing to RS485 transceivers. The UART supports RTS/ CTS, DSR/DTR and X-On/X-Off handshaking options. Handshaking, where required, is handled in hardware to ensure fast response times. The UART also supports the RS232 BREAK setting and detection conditions. • Baud Rate Generator The Baud Rate Generator provides a x16 clock input to the UART from the 48MHz reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 3 million baud. • RESET Generator The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT232BM or the FT232BM to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1.5k pull-up on USBDP directly where delayed USB enumeration is required. It can also be used to reset other devices. RSTOUT# will stay highimpedance for approximately 5ms after VCC has risen above 3.5V AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device from external logic or an external reset generator i.c. • • • • • • DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 6 of 25 FT232BM USB UART ( USB - Serial) I.C. • EEPROM Interface Though the FT232BM will work without the optional EEPROM, an external 93C46 (93C56 or 93C66) EEPROM can be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT232BM for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The EEPROM should be a 16 bit wide configuration such as a MicroChip 93LC46B or equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility available from FTDI’s web site (http://www.ftdichip.com). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT232BM will use its built-in default VID, PID Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. 4.0 Device Pin-Out 13 26 3 30 6 3V3OUT A V V C V C C V C C XTOUT V C C I O TXD RXD 25 EECS AVCC TEST AGND 24 XTIN VCC TXD 8 USBDM RTS# CTS# 23 22 7 USBDP DTR# DSR# 21 32 EESK EEDATA VCC RESET# RSTOUT# 3V3OUT USBDP USBDM 8 9 1 25 24 5 20 FTDI FT232BM XXYY 16 17 RXD RTS# CTS# DTR# DSR# DCD# RI# GND RSTOUT# RESET# DCD# RI# 19 4 18 27 XTIN TXDEN TXLED# 16 12 28 XTOUT EECS EESK EEDATA TEST A G N D 29 RXLED# 11 32 1 PWRCTL PWREN# SLEEP# G N D 9 G N D 17 14 2 31 15 10 RXLED# PWRCTL SLEEP# TXLED# PWREN# VCCIO Figure 1 Pin-Out (LQFP-32 Package ) DS232B Version 1.8 TXDEN GND Figure 2 Pin-Out (Schematic Symbol ) Page 7 of 25 © Future Technology Devices Intl. Ltd. 2005 FT232BM USB UART ( USB - Serial) I.C. 4.1 Signal Descriptions Table 1 - FT232BM - PINOUT DESCRIPTION UART INTERFACE GROUP Pin# 25 24 23 22 21 20 19 18 Signal TXD RXD RTS# CTS# DTR# DSR# DCD# RI# Type OUT IN OUT IN OUT IN IN IN Description Transmit Asynchronous Data Output Receive Asynchronous Data Input Request To Send Control Output / Handshake signal Clear To Send Control Input / Handshake signal Data Terminal Ready Control Output / Handshake signal Data Set Ready Control Input / Handshake signal Data Carrier Detect Control Input Ring Indicator Control Input. When the Remote Wakeup option is enabled in the EEPROM, taking RI# low can be used to resume the PC USB Host controller from suspend. Enable Transmit Data for RS485 16 TXDEN OUT USB INTERFACE GROUP Pin# 7 8 Signal USBDP USBDM Type I/O I/O Description USB Data Signal Plus ( Requires 1.5k pull-up to 3V3OUT or RSTOUT# ) USB Data Signal Minus EEPROM INTERFACE GROUP Pin# 32 Signal EECS Type I/O Description EEPROM – Chip Select. For 48MHz operation pull EECS to GND using a 10K resistor. For 6MHz operation no resistor is required. Tri-State during device reset. **Note 1 Clock signal to EEPROM. Tri-State during device reset, else drives out. Adding a 10K pull down resistor onto EESK will cause the FT232BM to use USB Product ID 6004 (hex) instead of 6001 (hex). All of the other USB device descriptors are unchanged.**Note 1 EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. Tri-State during device reset. **Note 1 1 EESK OUT 2 EEDATA I/O DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 8 of 25 FT232BM USB UART ( USB - Serial) I.C. POWER CONTROL GROUP Pin# 10 15 Signal SLEEP# PWREN# Type OUT OUT Description Goes Low during USB Suspend Mode. Typically used to power-down an external TTL to RS232 level converter i.c. in USB RS232 converter designs. Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. Bus Powered – Tie Low / Self Powered – Tie High (to VCCIO) 14 PWRCTL IN MISCELLANEOUS SIGNAL GROUP Pin# 4 5 Signal RESET# RSTOUT# Type IN OUT Description Can be used by an external device to reset the FT232BM. If not required, tie to VCC. Output of the internal Reset Generator. Stays high impedance for ~ 5ms after VCC > 3.5V and the internal clock starts up, then clamps its output to the 3.3v output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset. LED Drive - Pulses Low when Transmitting Data via USB LED Drive - Pulses Low when Receiving Data via USB Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external 6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if driving from an external source, the source must be driving at 5V CMOS level or a.c. coupled to centre around VCC/2. Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. Puts device in I.C. test mode – must be tied to GND for normal operation. 12 11 27 TXLED# RXLED# XTIN O.C. O.C. IN 28 31 XTOUT TEST OUT IN POWER AND GND GROUP Pin# 6 Signal 3V3OUT Type OUT Description 3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled to GND using a 33nF ceramic capacitor in close proximity to the device pin. Its prime purpose is to provide the internal 3.3V supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current ( RS485 converter. This example uses the Sipex SP481 device but there are similar parts available from Maxim and Analog Devices amongst others. The SP481 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN pin on the FT232BM is provided for exactly that purpose and so the transmitter enable is wired to TXDEN. The receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode. RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. A link is provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. In this example the data transmitted by the FT232BM is also received by the device that is transmitting. This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT232BM it is possible to do this entirely in hardware – simply modify the schematic so that RXD of the FT232BM is the logical OR of the SP481 receiver output with TXDEN using an HC32 or similar logic gate. DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 19 of 25 7.5 LED Interface Figure 12 Dual LED Configuration VCCIO FT232BM USB UART ( USB - Serial) I.C. Figure 13 Single LED Configuration VCCIO TX RX LED 220R 220R 220R FT232BM TXLED# RXLED# 12 11 FT232BM TXLED# RXLED# 12 11 The FT232BM has two IO pins dedicated to controlling LED status indicators, one for transmitted data the other for received data. When data is being transmitted / received the respective pins drive from tri-state to low in order to provide indication on the LEDs of data transfer. A digital one-shot timer is used so that even a small percentage of data transfer is visible to the end user. Figure 12 shows a configuration using two individual LED’s – one for transmitted data the other for received data. In Figure 13, the transmit and receive LED indicators are wire-OR’ed together to give a single LED indicator which indicates any transmit or receive data activity. Another possibility (not shown here) is to use a 3 pin common anode tri-color LED based on the circuit in Figure 13 to have a single LED that can display activity in a variety of colors depending on the ratio of transmit activity compared to receive activity. Note that the LED’s are connected to VCCIO. DS232B Version 1.8 © Future Technology Devices Intl. Ltd. 2005 Page 20 of 25 FT232BM USB UART ( USB - Serial) I.C. 7.6 Interfacing to 3.3v Logic Figure 14 Bus Powered Circuit with 3.3V logic drive / supply voltage 3.3v LDO Regulator In Gnd Out 3.3v Power to External Logic 0.1uF USB "B" Connector Ferrite Bead 1 2 3 4 10nF VCC 3 V C C 6 470R 27R 27R 26 V C C 13 V C C I O 30 A V C C 0.1uF 33nF 3v3OUT FT232BM 8 7 USB DM USB DP Figure 14 shows how to configure the FT232BM to interface with a 3.3V logic device. In this example, a discrete 3.3V regulator is used to supply the 3.3V logic from the USB supply. VCCIO is connected to the output of the 3.3V regulator, which in turn will cause the UART interface IO pins to drive out at 3.3V level. For USB bus powered circuits some considerations have to be taken into account when selecting the regulator – a) The regulator must be capable of sustaining its output voltage with an input voltage of 4.35 volts. A Low Drop Out (LDO) regulator must be selected. b) The quiescent current of the regulator must be low in order to meet the USB suspend total current requirement of