FT232HPQ-TRAY

FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Future Technology Devices International Ltd FT233HP/FT232HP (High Speed USB Bridge with Type-C/PD3.0 Controller) The FT233HP/FT232HP is a Hi-Speed USB device with Type-C/PD 3.0 controller IC that fully supports the latest USB Type-C and Power Delivery (PD) standards enabling support for power negotiation with the ability to sink or source current to a USB host device. The USB bridge function delivers 1 independent channel compatible with the FT232H – Single Hi-speed USB to multipurpose UART/FIFO solution. The FT233HP/FT232HP has the following advanced features:                  Supports PD Specification 3.0. 2 USB PD 3.0 Port Support. Port 1 supports Dual Role Swap Function while Port 2 supports sink mode with charging function through to Port 1 (FT233HPQ and FT233HPL only). Supports 5V3A, 9V3A, 12V3A, 15V3A, 20V3A and more PDOs as sink or source. Type-C/PD Physical Layer Protocol. PD policy engine using 32-bit RISC controller with 8kB data RAM and 48kB code ROM. PD mode configuration through external EEPROM. Options to use external MCU controlling PD policy through I2C interface. Up to 8 Configurable PD GPIO pins support. External MCU support through I2C bus. External EEPROM support for USB device configuration and PD profile. Single channel USB to serial / parallel ports with a variety of configurations. Entire USB protocol handled on the chip. No USB specific firmware programming required. USB 2.0 Hi-Speed (480Mbits/Second) and Full Speed (12Mbits/Second) compatible. Multi-Protocol Synchronous Serial Engine (MPSSE) to simplify synchronous serial protocol (USB to JTAG, I2C (MASTER), SPI (MASTER) or bit-bang) design. UART transfer data rate up to 12Mbaud. (RS232 Data Rate limited by external level shifter). USB to asynchronous 245 FIFO mode for transfer data rate up to 8 Mbyte/Sec. USB to synchronous 245 parallel FIFO mode for transfers up to 40 Mbytes/Sec                      Supports a proprietary half duplex FT1248 interface with a configurable width, bi-directional data bus (1, 2, 4 or 8 bits wide). CPU-style FIFO interface mode simplifies CPU interface design. Fast serial interface option. FTDI’s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases. Adjustable receive buffer timeout. Option for transmit and receive LED drive signals. Bit-bang Mode interface option with RD# and WR# strobes Highly integrated design includes 5V to 3.3/+1.8V LDO regulator for VCORE, integrated POR function Asynchronous serial UART interface option with full hardware handshaking and modem interface signals. Fully assisted hardware or X-On / X-Off software handshaking. UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity. Auto-transmit enable control for RS485 serial applications using the TXDEN pin. Operational mode configuration and USB Description strings configurable in external EEPROM over the USB interface. Configurable I/O drives strength (4, 8, 12 or 16mA) and slew rate. Low operating and USB suspend current. UHCI/OHCI/EHCI host controller compatible. USB Bulk data transfer mode (512 byte packets in HiSpeed mode). +1.2V (chip core) and +3.3V I/O interfacing (+5V Tolerant). Extended -40°C to 85°C industrial operating temperature range. 3 IC Package with RoHS compliant Support: FT233HPQ:Compact 64-pin Lead Free QFN package supports 2 PD 3.0 port FT233HPL:Compact 64-pin Lead Free LQFP package supports 2 PD 3.0 port FT232HPQ:Compact 56-pin Lead Free QFN package supports 1 PD 3.0 Port Configurable ACBUS I/O pins. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or r eproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentat ion are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Pa rk, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited 1 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 1 Typical Applications  USB Type-C/USB 3.0 Power Delivery Support  USB Instrumentation  High-power application via USB PD and/or Type-C port  USB Industrial Control Get power from USB device functions, e.g. portable USB host needs charging when USB is connected.  USB EPOS Control   USB MP3 Player Interface  USB FLASH Card Reader / Writers  Set Top Box - USB interface  USB Digital Camera Interface  USB Bar Code Readers  Single chip USB to UART (RS232, RS422 or RS485)  USB to FIFO  USB to FT1248  USB to JTAG  USB to SPI  USB to I2C  USB to Bit-Bang  USB to Fast Serial Interface  USB to CPU target interface (as memory) 1.1 Driver Support The FT233HP/FT232HP requires USB device drivers (listed below), available free from http://www.ftdichip.com, to operate. The VCP version of the driver creates a Virtual COM Port allowing legacy serial port applications to operate over USB e.g. serial emulator application TTY. Another FTDI USB driver, the D2XX driver, can also be used with application software to directly access the FT233HP/FT232HP through a DLL. Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface)  Windows 10 32,64-bit  Windows 10 32,64-bit  Windows 8/8.1 32,64-bit  Windows 8/8.1 32,64-bit  Windows 7 32,64-bit  Windows 7 32,64-bit  Windows Server 2008 and server 2012 R2  Windows Server 2008 and server 2012 R2  Mac OS-X  Linux 2.4 and greater  Linux 2.4 and greater  Android(J2xx)  Mac OS-X Copyright © Future Technology Devices International Limited 2 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 1.2 Part Numbers Part Number FT232HPQ –xxxx FT233HPQ-xxxx FT233HPL-xxxx Package 56 Pin QFN 64 Pin QFN 64 Pin LQFP Please refer to section 7 for all package mechanical parameters. 1.3 USB Compliant The FT233HP is fully compliant with the USB 2.0 specification and the USB Type-C & PD 3.0 specification. It has been given the USB-IF Test-ID (TID) 3425*. * for PD port1 The timing of the rise/fall time of the USB signals is not only dependant on the USB signal drivers, it is also dependant system and is affected by factors such as PCB layout, external components and any transient protection present on the USB signals. For USB compliance these may require a slight adjustment. Timing can also be changed by adding appropriate passive components to the USB signals. Copyright © Future Technology Devices International Limited 3 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 2 FT233HP/FT232HP Block Diagram ADBUS0 ADBUS1 ADBUS2 ADBUS3 120MHz Baud Rate VREGIN VREGOUT Generator LDO Regulator Tx Buffer 1K Bytes OSCI OSCO Oscillator Rx Buffer USBDP Type-C USBDM Protocol PHY Engine And FIFO Connector Control PD1_CC1 PD1_CC2 PD1_SVBUS UART/FIFO Controller ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ACBUS8 ACBUS9 USB UTMI ADBUS7 MultiPurpose 1K Bytes REF MPSSE/ ADBUS4 ADBUS5 ADBUS6 PD2 ( for FT233HP only ) PD2_CC1 Type-C PD2_CC2 Connector PD2_SVBUS PD1 PD1_VCONN RESET Port 1 Generator RESET# Port 2 TEST EECS EESK EEDATA EEPROM Interface GPIO ( 4~7 for FT233HP only ) GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Figure 1 - FT233HP/FT232HP Block Diagram *A full description of each function is available in section 4. Copyright © Future Technology Devices International Limited 4 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Table of Contents 1 Typical Applications....................................................... 2 1.1 Driver Support ........................................................................... 2 1.2 Part Numbers ............................................................................. 3 1.3 USB Compliant ........................................................................... 3 2 FT233HP/FT232HP Block Diagram ................................ 4 3 Device Pin Out and Signal Descriptions ......................... 8 3.1 FT233HPQ 64 Pin QFN Package Diagram ................................... 8 3.2 FT233HPL 64 Pin LQFP Package Diagram................................... 9 3.3 FT232HPQ 56 Pin QFN Package Diagram ................................. 10 3.4 FT233HP/FT232HP Pin Descriptions ....................................... 11 3.5 Signal Description .................................................................... 12 3.6 ACBUS Signal Option ................................................................ 16 3.7 Pin Configurations ................................................................... 16 3.7.1 FT233HP/232HP pins used in an UART interface ............................................ 16 3.7.2 FT233HP/FT232HP Pins used in an FT245 Synchronous FIFO Interface ............. 17 3.7.3 FT233HP/FT232HP Pins used in an FT245 Style asynchronous FIFO Interface ... 18 3.7.4 FT233HP/232HP Configured as Synchronous/ Asynchronous Bit-Bang Interface 19 3.7.5 FT233HP/FT232HP Pins used in an MPSSE .................................................... 19 3.7.6 FT233HP/FT232HP Pins used as a Fast Serial Interface .................................. 20 3.7.7 FT233HP/FT232HP Pins Configured as a CPU-style FIFO Interface ................... 21 3.7.8 FT233HP/FT232HP Pins Configured as a FT1248 Interface .............................. 22 4 Function Description ................................................... 23 4.1 Key Features ............................................................................ 23 4.2 Functional Block Descriptions .................................................. 24 4.3 FT233HP/FT232HP UART Interface Mode Description ............. 25 4.3.1 RS232 Configuration.................................................................................. 25 4.3.2 RS422 Configuration.................................................................................. 26 4.3.3 RS485 Configuration.................................................................................. 26 4.4 FT245 Synchronous FIFO Interface Mode Description .............. 27 4.4.1 FT245 Synchronous FIFO Read Operation ..................................................... 28 4.4.2 FT245 Synchronous FIFO Write Operation .................................................... 28 4.5 FT245 Style Asynchronous FIFO Interface Mode Description ... 28 4.6 FT1248 Interface Mode Description ......................................... 29 4.6.1 Bus Width Protocol Decode ......................................................................... 30 Copyright © Future Technology Devices International Limited 5 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4.6.2 4.7 FT1248: 1-bit interface .............................................................................. 31 Synchronous and Asynchronous Bit-Bang Interface Mode ....... 32 4.7.1 Asynchronous Bit-Bang Mode...................................................................... 32 4.7.2 Synchronous Bit-Bang Mode ....................................................................... 33 4.8 MPSSE Interface Mode Description .......................................... 34 4.8.1 4.9 MPSSE Adaptive Clocking ........................................................................... 35 Fast Serial Interface Mode Description .................................... 36 4.9.1 Outgoing Fast Serial Data .......................................................................... 37 4.9.2 Incoming Fast Serial Data .......................................................................... 37 4.9.3 Fast Serial Data Interface Example .............................................................. 37 4.10 CPU-style FIFO Interface Mode Description ............................. 38 4.11 RS232 UART Mode LED Interface Description .......................... 40 4.12 Send Immediate/Wake Up (SIWU#) ....................................... 40 4.13 FT233HP/FT232HP Mode Selection .......................................... 41 4.14 Modes Configuration ................................................................ 42 5 USB Type-C/Power Delivery 3.0 Controller.................. 43 5.1 PD Controller Description......................................................... 43 5.2 Features................................................................................... 43 5.3 AC timing on GPIO pins ............................................................ 43 5.4 GPIO Timing for PD Operation ................................................. 44 5.5 PD Voltage Parameter .............................................................. 44 6 Devices Characteristics and Ratings ............................ 46 6.1 Absolute Maximum Ratings ...................................................... 46 6.2 DC Characteristics .................................................................... 46 6.3 ESD Tolerance .......................................................................... 48 6.4 Thermal Characteristics ........................................................... 48 7 Package Parameters .................................................... 49 7.1 FT232HPQ, QFN-56 Package Dimensions ................................. 49 7.2 FT233HPQ, QFN-64 Package Dimensions ................................. 50 7.3 FT233HPL, LQFP-64 Package Dimensions ................................ 51 7.4 Solder Reflow Profile ............................................................... 52 8 Contact Information .................................................... 54 Appendix A – References ................................................... 55 Document References ...................................................................... 55 Acronyms and Abbreviations............................................................ 55 Copyright © Future Technology Devices International Limited 6 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Appendix B – List of Figures and Tables ............................. 56 List of Tables.................................................................................... 56 List of Figures .................................................................................. 57 Appendix C – Revision History ........................................... 58 Copyright © Future Technology Devices International Limited 7 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 3 Device Pin Out and Signal Descriptions There are three types of IC package for FT233HP IC: 64 pin QFN FT233HPQ, 64 pin LQFP FT233HPL and 56 pin QFN FT232HPQ. There pin numbering is illustrated in the schematic symbol shown in Figure 2, Figure 3 and Figure 4. VCORE PD2_CC2 PD2_SVBUS PD2_CC1 PD1_CC1 PD1_VCONN PD1_SVBUS PD1_CC2 VCC_PD REF DP DM VCC_USB VCORE NC ACBUS9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 3.1 FT233HPQ 64 Pin QFN Package Diagram EECS 1 48 ACBUS8 EECLK 2 47 ACBUS7 EEDATA 3 46 GND TEST 4 45 VCCIO VCCIO 5 44 ACBUS6 RESET# 6 43 ACBUS5 GPIO0 7 42 ACBUS4 GPIO1 8 41 VCORE GPIO2 9 40 ACBUS3 GPIO3 10 39 ACBUS2 GPIO4 11 38 ACBUS1 GPIO5 12 37 ACBUS0 VCORE 13 36 ADBUS7 GND 14 35 ADBUS6 VCCIO 15 34 ADBUS5 GPIO6 16 33 VCCIO XXXXXXXXXX 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCCIO OSCI OSCO GND VREGIN VREGOUT FSOURCE VPP VCORE NC ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 GPIO7 17 FT233HPQ YYWW-X Figure 2 - FT233HPQ-64 Pin Schematic Symbol Copyright © Future Technology Devices International Limited 8 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 VCORE PD2_CC2 PD2_SVBUS PD2_CC1 PD1_CC1 PD1_VCONN PD1_SVBUS PD1_CC2 VCC_PD REF DP DM VCC_USB VCORE NC ACBUS9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 3.2 FT233HPL 64 Pin LQFP Package Diagram EECS 1 48 ACBUS8 EECLK 2 47 ACBUS7 EEDATA 3 46 GND TEST 4 45 VCCIO VCCIO 5 44 ACBUS6 RESET# 6 43 ACBUS5 GPIO0 7 42 ACBUS4 GPIO1 8 41 VCORE GPIO2 9 40 ACBUS3 GPIO3 10 39 ACBUS2 GPIO4 11 38 ACBUS1 GPIO5 12 37 ACBUS0 VCORE 13 36 ADBUS7 GND 14 35 ADBUS6 VCCIO 15 34 ADBUS5 GPIO6 16 33 VCCIO XXXXXXXXXX 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCCIO OSCI OSCO GND VREGIN VREGOUT FSOURCE VPP VCORE NC ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 GPIO7 17 FT233HPL YYWW-X Figure 3 - FT233HPL-64 Pin Schematic Symbol Copyright © Future Technology Devices International Limited 9 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 VCORE PD1_CC1 PD1_VCONN PD1_SVBUS PD1_CC2 VCC_PD REF DP DM VCC_USB VCORE NC ACBUS9 ACBUS8 56 55 54 53 52 51 50 49 48 47 46 45 44 43 3.3 FT232HPQ 56 Pin QFN Package Diagram EECS 1 42 ACBUS7 EECLK 2 41 GND EEDATA 3 40 VCCIO TEST 4 39 ACBUS6 VCCIO 5 38 ACBUS5 RESET# 6 37 ACBUS4 GPIO0 7 36 VCORE GPIO1 8 35 ACBUS3 GPIO2 9 34 ACBUS2 GPIO3 10 33 ACBUS1 VCORE 11 32 ACBUS0 GND 12 31 ADBUS7 VCCIO 13 30 ADBUS6 VCCIO 14 29 ADBUS5 XXXXXXXXXX 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OSCI OSCO GND VREGIN VREGOUT FSOURCE VPP VCORE ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 VCCIO FT232HPQ YYWW-X Figure 4 - FT232HPQ-56 Pin Schematic Symbol Copyright © Future Technology Devices International Limited 10 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 3.4 FT233HP/FT232HP Pin Descriptions This section describes the operation of the FT233HP/FT232HP pins. Both the LQFP and the QFN packages have the same function on each pin. The function of many pins is determined by the configuration of the FT233HP/FT232HP. Table 1 provides details about the function of each pin dependent on the configuration of the interface. Each of the functions is described in the following table (Note: The convention used throughout this document for active low signals is the signal name followed by #). FT233HP / FT232HP Pin Pin functions (depends on configuration) 64 Pin # 28 56 Pin # 23 Pin Name ADBUS0 ASYNC Serial (RS232) TXD SYNC 245 FIFO D0 STYLE ASYNC 245 FIFO D0 ASYNC Bit-bang D0 SYNC Bit-bang D0 29 24 ADBUS1 RXD D1 D1 D1 D1 30 25 ADBUS2 RTS# D2 D2 D2 D2 31 26 ADBUS3 CTS# D3 D3 D3 D3 32 27 ADBUS4 DTR# D4 D4 D4 D4 GPIOL0 34 29 ADBUS5 DSR# D5 D5 D5 D5 GPIOL1 35 30 ADBUS6 DCD# D6 D6 D6 D6 GPIOL2 36 31 ADBUS7 RI# D7 D7 D7 D7 GPIOL3 RXF# RXF# ACBUS0 ACBUS0 GPIOH0 TXE# TXE# WRSTB# WRSTB# GPIOH1 RD# RD# RDSTB# RDSTB# GPIOH2 WR# WR# ACBUS3 ACBUS3 GPIOH3 SIWU# SIWU# SIWU# SIWU# GPIOH4 CLKOUT ACBUS5 ** ACBUS5 ** ACBUS5 GPIOH5 OE# ACBUS6 ACBUS6 ACBUS6 GPIOH6 37 32 ACBUS0 38 33 ACBUS1 39 34 ACBUS2 40 35 ACBUS3 42 37 ACBUS4 43 38 ACBUS5 44 39 ACBUS6 47 42 ACBUS7 48 43 ACBUS8 49 44 ACBUS9 * TXDEN ** ACBUS1 ** ACBUS2 * RXLED# * TXLED# ** ACBUS5 ** ACBUS6 WRSAV# ** ACBUS8 ** ACBUS9 PWRSAV # ** ACBUS8 ** ACBUS9 PWRSAV# ** ACBUS8 ** ACBUS9 PWRSAV # ** ACBUS8 ** ACBUS9 PWRSAV# ** ACBUS8 ** ACBUS9 MPSSE TCK/SK Fast Serial interface FSDI CPU Style FIFO D0 FT1248 MIOSI0 TDI/DO FSCLK D1 MIOSI1 TDO/DI FSDO D2 MIOSI2 TMS/CS FSCTS ** TriSt-UP ** TriSt-UP ** TriSt-UP ** TriSt-UP ** ACBUS0 ** ACBUS1 ** ACBUS2 ** ACBUS3 D3 MIOSI3 D4 MIOSI4 D5 MIOSI5 D6 MIOSI6 D7 MIOSI7 CS# SCLK A0 SS_n RD# MISO WR# ACBUS3 SIWU# SIWU# ACBUS4 ** ACBUS5 ** ACBUS6 ** ACBUS5 ** ACBUS6 PWRSAV # ** ACBUS8 ** ACBUS9 *** GPIOH7 ** ACBUS8 ** ACBUS9 PWRSAV# ** ACBUS8 ** ACBUS9 ACBUS5 ACBUS6 PWRSAV # ACBUS8 ACBUS9 Table 1 - FT233HP/FT232HP Pin Descriptions Pins marked * require an EEPROM for assignment to these functions. Default is Tristate, Pull-Up Pins marked ** default to tri-stated inputs with an internal 75KΩ (approx.) pull up resistor to VCCIO. Pin marked *** default to GPIO line with an internal 75KΩ pull down resistor to GND. Using the EEPROM this pin can be PWRSAV#(need to pull to VCC_USB) instead of GPIO mode. Note: Initial Pin States - The device will start up as a UART port if no EEPROM is fitted. This also applies if an EEPROM is fitted until the EEPROM is read by the device. Therefore pins which are output in UART mode will be driving out at start-up. If an application uses a mode other than UART, ensure that any external signals do not cause contention during this time. Copyright © Future Technology Devices International Limited 11 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 3.5 Signal Description The operation of the following FT233HP/FT232HP pins are the same regardless of the configured mode:64 Pin No. 13,26,41, 51, 64 56 Pin No. 11,22,36, 46, 56 5,15,18, 33,45 Name Type Description VCORE POWER Input 5,13,14, 28,40 VCCIO POWER Input 52 47 VCC_USB POWER Input +1.2V input. Core supply voltage input. Connect to pin 33 when using internal regulator. +3.3V input. I/O interface power supply input. Failure to connect all VCCIO pins will result in failure of the device. +3.3V Input. Internal USB PHY power supply input. Note that this cannot be connected directly to the USB supply. A +3.3V regulator must be used. It is recommended that this supply is filtered using an LC filter. *Note: When migrating designs from the FT232H – note that due to the Power Delivery capabilities of the FT233H, the application may negotiate the VCC_USB voltage to be significantly greater than 5V. The designer must ensure that any signals derived from circuits powered by VCC_USB which are applied to the FT233H pins do not exceed the maximum input voltage for the pins at any time. 56 51 VCC_PD 22 18 VREGIN 23 19 VREGOUT 24 20 FSOURCE 25 21 14,21,46 12,17,41 POWER Input POWER Input POWER Output +3.3V Input. Internal PD PHY power supply input. +3.3V Input. Integrated 1.2V voltage regulator input. +1.2V Output. Integrated voltage regulator output. Connect to VCORE with 3.3uF filter capacitor. This output should not be used to power other circuits apart from VCORE. FSOURCE input pin for EFUSE. Leave float for normal operation VPP input pin for EFUSE. Leave float for normal operation POWER Input POWER VPP Input POWER GND Ground. Input Table 2 - Power and Ground 64 Pin No. 19 56 Pin No. 15 OSCI INPUT 20 16 OSCO OUTPUT 55 50 REF INPUT 53 48 DM I/O 54 49 DP I/O 4 4 TEST INPUT 6 6 RESET# INPUT 47 42 PWRSAV# INPUT Name Type Description Oscillator input. Oscillator output. Current reference – connect via a 12KΩ resistor @ 1% to GND. USB Data Signal Minus. USB Data Signal Plus. IC test pin – for normal operation must be connected to GND. Reset input (active low). USB Power Save input. This is an EEPROM configurable option which is set using a ’Suspend on ACBus7 Low’ bit in FT_PROG. This option is available when the FT233HP/FT232HP is on a self-powered mode and is used to prevent forcing current down the USB lines when the host or hub is powered off. PWRSAV# = 1 : Normal Operation PWRSAV# = 0 : FT233HP/FT232HP forced into SUSPEND mode. PWRSAV# can be connected to VCC_USB (please see the note for VCC_USB usage in Table2) of the USB Copyright © Future Technology Devices International Limited 12 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 connector (via a 39KΩ resistor). When this input goes high, then it indicates to the FT233HP/FT232HP that it is connected to a host PC. When the host or hub is powered down then the FT233HP/FT232HP is held in SUSPEND mode. Table 3 - Common Function Pins 64 Pin No. 56 Pin No Name Type 1 1 EECS* I/O 2 2 EECLK* OUTPUT 3 3 EEDATA* Description EEPROM – Chip Select. Tri-State during device reset. Clock signal to EEPROM. Tri-State during device reset. When not in reset, this outputs the EEPROM clock. EEPROM – Data I/O. Connect directly to Data-in of the EEPROM and to Data-out of the EEPROM via a 2.2K resistor. I/O Also, pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. Tri-State during device reset. Table 4 - EEPROM Interface Group * Note: Pull each of pins via separate 10K resistor to VCCIO if no EEPROM uses. 64 Pin No. 56 Pin No 58 53 59 54 60 Name Type Description AI Power Input AI/O Analog input. Scaled down VBUS sensing input for PD1. VBUS is required to be divided by 10 before input to this pin. Power input for PD1 VCONN power source. Connect to 3.3V. 55 PD1_SVB US PD1_VCO NN PD1_CC1 57 52 PD1_CC2 AI/O 62 N/A AI 61 N/A PD2_SVB US PD2_CC1 AI/O Analog input. Scaled down VBUS sensing input for PD2. VBUS is required to be divided by 10 before input to this pin. Analog IO pin. PD2 CC1 pin N/A PD2_CC2 AI/O Analog IO pin. PD2 CC2 pin 63 Analog IO pin. PD1 CC1 pin Analog IO pin. PD1 CC2 pin Table 5 - Type-C/PD Port Pins 64 Pin No. 56 Pin No 7 7 8 8 9 9 10 11 Name Type Description GPIO0 I/O GPIO1 I/O GPIO2 I/O 10 GPIO3 I/O GPIO0 or I2C_SDA pin. Default function is GPIO0 input with weak pull-down. GPIO1 or I2C_SCL pin. Default function is GPIO1 input with weak pull-down. GPIO2 or I2C_INT# pin. Default function is GPIO2 input with weak pull-down. GPIO3 pin. Default function is GPIO3 input with weak pull-down. N/A GPIO4 I/O GPIO4 pin. Default function is GPIO4 input with weak pull-down. 12 N/A GPIO5 I/O GPIO5 pin. Default function is GPIO5 input with weak pull-down. 16 N/A 17 N/A GPIO6 GPIO7 I/O I/O GPIO6 pin. Default function is GPIO6 input with weak pull-down. GPIO7 pin. Default function is GPIO7 input with weak pull-down. Table 6 - GPIO Pins 64 Pin No. 56 Pin No Name Type 28 23 ADBUS0 Output 29 24 ADBUS1 Input 30 25 ADBUS2 Output 31 26 ADBUS3 Input Description Configurable Output Pin, the default configuration is Transmit Asynchronous Data Output. Configurable Input Pin, the default configuration is Receiving Asynchronous Data Input. Configurable Output Pin, the default configuration is Request to Send Control Output / Handshake Signal. Configurable Input Pin, the default configuration is Clear To Send Control Input / Handshake Signal. Copyright © Future Technology Devices International Limited 13 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 32 27 ADBUS4 Output 34 29 ADBUS5 Input 35 30 ADBUS6 Input 36 31 ADBUS7 Input 37 38 39 40 42 43 44 47 48 32 33 34 35 37 38 39 42 43 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ACBUS8 I/O I/O I/O I/O I/O I/O I/O I/O I/O Configurable Output Pin, the default configuration is Data Terminal Ready Control Output / Handshake Signal. Configurable Input Pin, the default configuration is Data Set Ready Control Input / Handshake Signal. Configurable Input Pin, the default configuration is Data Carrier Detect Control Input. Configurable Input Pin, the default configuration is Ring Indicator Control Input. When remote wake up is enabled in the EEPROM taking RI# low can be used to resume the PC USB host controller from suspend. (Also see note 1, 2, 3 in section 4.12) Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PD. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Copyright © Future Technology Devices International Limited 14 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 49 44 ACBUS9 I/O Configurable ACBUS I/O Pin. Function of this pin is configured in the device EEPROM. If the external EEPROM is not fitted the default configuration is TriSt-PU. See ACBUS Signal Options, Table 8 - ACBUS Configuration Control Table 7 - UART Interface and ACBUS Group (see note 1) Notes: When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the EEPROM. Copyright © Future Technology Devices International Limited 15 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 3.6 ACBUS Signal Option If the external EEPROM is fitted, the following options can be configured on the CBUS I/O pins using the software utility FT_PROG which can be downloaded from the FTDI utilities page. CBUS signal options are common to both package versions of the FT233HP/FT232HP. ACBUS Signal Option Available On ACBUS Pin Description TXDEN ACBUS0, ACBUS1, ACBUS2, ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 *PWREN# ACBUS0, ACBUS1, ACBUS2, ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 TXDEN = (TTL level). Used with RS485 level converters to enable the line driver during data transmit. TXDEN is active from one bit time before the start bit is transmitted on TXD until the end of the stop bit. Output is low after the device has been configured by USB, then high during USB suspend mode. This output can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way.* TXLED = Transmit signalling output. Pulses low when transmitting data (TXD) to the external device. This can be connected to an LED. RXLED = Receive signalling output. Pulses low when receiving data (RXD) from the external device. This can be connected to an LED. LED drive – pulses low when transmitting or receiving data from or to the external device. TXLED# RXLED# TX&RXLED# SLEEP# **CLK30 **CLK15 **CLK7.5 TriSt-PU DRIVE 1 DRIVE 0 I/O mode ACBUS0, ACBUS1, ACBUS2, ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 ACBUS0, ACBUS1, ACBUS2, ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 ACBUS0, ACBUS1, ACBUS2, ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 ACBUS0, ACBUS1, ACBUS2, Goes low during USB suspend mode. Typically used to ACBUS3, ACBUS4, ACBUS5, power down an external TTL to RS232 level converter IC ACBUS6, ACBUS8, ACBUS9 in USB to RS232 converter designs. ACBUS0, ACBUS5, 30MHz Clock output. ACBUS6,ACBUS8, ACBUS9 ACBUS0, ACBUS5, 15MHz Clock output. ACBUS6,ACBUS8, ACBUS9 ACBUS0, ACBUS5, 7.5MHz Clock output. ACBUS6,ACBUS8, ACBUS9 ACBUS0, ACBUS1, ACBUS2, Input Pull Up ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 ACBUS0, ACBUS5, Output High ACBUS6,ACBUS8, ACBUS9 ACBUS0, ACBUS1, ACBUS2, Output Low ACBUS3, ACBUS4, ACBUS5, ACBUS6, ACBUS8, ACBUS9 ACBUS5, ACBUS6,ACBUS8, ACBUS Bit Bang ACBUS9 Table 8 - ACBUS Configuration Control * Must be used with a 10kΩ resistor pull up. **When in USB suspend mode the outputs clocks are also suspended. 3.7 Pin Configurations The following section describes the function of the pins when the device is configured in different modes of operation. 3.7.1 FT233HP/232HP pins used in an UART interface The FT233HP/FT232HP can be configured as a UART interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 9. Copyright © Future Technology Devices International Limited 16 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 64 Pin No. 56 pin No Name Type 28 23 TXD OUTPUT 29 24 RXD INPUT 30 25 RTS# OUTPUT 31 26 CTS# INPUT 32 27 DTR# OUTPUT DTR# = Data Transmit Ready modem signalling line 34 29 DSR# INPUT DSR# = Data Set Ready modem signalling line 35 30 DCD# INPUT DCD# = Data Carrier Detect modem signalling line 36 31 RI# 37 32 ** TXDEN 40 35 ** RXLED 42 37 ** TXLED Table 9 UART Configuration Description TXD = transmitter output RXD = receiver input RTS# = Ready To send handshake output CTS# = Clear To Send handshake input RI# = Ring Indicator Control Input. When the Remote Wake up option is enabled in the EEPROM, INPUT taking RI# low can be used to resume the PC USB Host controller from suspend. TXDEN = (TTL level). Use to enable RS485 level OUTPUT converter RXLED = Receive signalling output. Pulses low when receiving data (RXD) from the external OUTPUT device (UART Interface). This should be connected to an LED. TXLED = Transmit signalling output. Pulses low when transmitting data (TXD) to the external OUTPUT device (UART Interface). This should be connected to an LED. - UART Configured Pin Descriptions ** ACBUS I/O pins For a functional description of this mode, please refer to section 4.3. Note: UART is the device default mode. 3.7.2 FT233HP/FT232HP Interface Pins used in an FT245 Synchronous FIFO The FT233HP/FT232HP can be configured as a FT245 synchronous FIFO interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 10. To set this mode the external EEPROM must be set to 245 mode. A software command (FT_SetBitMode) is then sent by the application to the FTDI D2XX driver to tell the chip to enter 245 synchronous FIFO mode. In this mode, data is written or read on the rising edge of the CLKOUT. Refer to Figure 8 for timing details. 64 Pin No. 28,29,30, 31,32,34, 35,36 56 Pin No 23,24,25, 26,27,29, 30,31 Name Type ADBUS[7:0] I/O 37 32 RXF# OUTPUT 38 33 TXE# OUTPUT 39 34 RD# INPUT FT245 Configuration Description D7 to D0 bidirectional FIFO data. This bus is normally input unless OE# is low. When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by driving RD# low. When in synchronous mode, data is transferred on every clock that RXF# and RD# are both low. Note that the OE# pin must be driven low at least 1 clock period before asserting RD# low. When high, do not write data into the FIFO. When low, data can be written into the FIFO by driving WR# low. When in synchronous mode, data is transferred on every clock that TXE# and WR# are both low. Enables the current FIFO data byte to be driven onto D0...D7 when RD# goes low. The next FIFO data byte (if available) is fetched from the receive Copyright © Future Technology Devices International Limited 17 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 40 42 43 44 FIFO buffer each CLKOUT cycle until RD# goes high. Enables the data byte on the D0...D7 pins to be written into the transmit FIFO buffer when WR# is 35 WR# INPUT low. The next FIFO data byte is written to the transmit FIFO buffer each CLKOUT cycle until WR# goes high. The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. 37 SIWU# INPUT During normal operation (PWREN# = 0), if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used. 60 MHz Clock driven from the chip. All signals 38 CLKOUT OUTPUT should be synchronized to this clock. Output enable when low to drive data onto D0-7. This should be driven low at least 1 clock period 39 OE# INPUT before driving RD# low to allow for data buffer turn-around. Table 10 - FT245 Synchronous FIFO Configured Pin Descriptions For functional description of this mode, please refer to section 4.5. Also refer to TN_167 FTDI FIFO Basics. 3.7.3 FT233HP/FT232HP Pins used in an FT245 Style asynchronous FIFO Interface The FT233HP/FT232HP can be configured as a FT245 style asynchronous FIFO interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 11. To enter this mode the external EEPROM must be set to 245 asynchronous FIFO mode. In this mode, data is written or read on the falling edge of the RD# or WR# signals. 64 Pin No. 28,29,30, 31,32,34, 35,36 56 pin No 23,24,25, 26,27,29, 30,31 Name Type ADBUS[7:0] I/O 37 32 RXF# OUTPUT 38 33 TXE# OUTPUT 39 34 RD# INPUT 40 35 WR# INPUT FT245 Configuration Description D7 to D0 bidirectional FIFO data. This bus is normally input unless RD# is low. When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by driving RD# low. When RD# goes high again RXF# will always go high and only become low again if there is another byte to read. During reset this signal pin is tristate, but pulled up to VCCIO via an internal 200kΩ resistor. When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR# high, then low. During reset this signal pin is tristate, but pulled up to VCCIO via an internal 200kΩ resistor. Enables the current FIFO data byte to be driven onto D0...D7 when RD# goes low. Fetches the next FIFO data byte (if available) from the receive FIFO buffer when RD# goes high. Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR# goes from high to Copyright © Future Technology Devices International Limited 18 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 low. The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. 37 SIWU# INPUT During normal operation (PWREN# = 0), if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used. Table 11 - FT245 Style Asynchronous FIFO Configured Pin Descriptions 42 For a functional description of this mode, please refer to section 4.6. Also refer to TN_167 FTDI FIFO Basics. 3.7.4 FT233HP/232HP Configured as Synchronous/ Asynchronous BitBang Interface Bit-bang mode is an FTDI FT233HP/FT232HP device mode that changes the 8 IO lines into an 8 bit bidirectional data bus. This mode is enabled by sending a software command (FT_SetBitMode) to the FTDI driver. When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in Table 12. 64 Pin No. 28,29,30, 31,32,34, 35,36 38 39 42 56 Pin No 23,24,25, 26,27,29, 30,31 Name Type ADBUS[7:0] I/O Configuration Description D7 to D0 bidirectional Bit-Bang parallel I/O data pins Write strobe, active low output indicates when new data has been written to the I/O pins from the Host PC (via the USB interface). Read strobe, this output rising edge indicates when 34 RDSTB# OUTPUT data has been read from the parallel I/O pins and sent to the Host PC (via the USB interface). The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. 37 SIWU# INPUT During normal operation (PWREN# = 0), if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used. Table 12 - Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions 33 WRSTB# OUTPUT For functional description of this mode, please refer to section 4.7. 3.7.5 FT233HP/FT232HP Pins used in an MPSSE The FT233HP/FT232HP has a Multi-Protocol Synchronous Serial Engine (MPSSE). This mode is enabled by sending a software command (FT_SetBitMode) to the FTDI D2xx driver. The MPSSE can be configured to a number of industry standard serial interface protocols such as JTAG, I2C (MASTER) or SPI (MASTER), or it can be used to implement a proprietary bus protocol. For example, it is possible to connect FT233HP/FT232HP’s to an SRAM configurable FPGA such as supplied by Altera or Xilinx. The FPGA device would normally not be configured (i.e. have no defined function) at power-up. Application software on the Copyright © Future Technology Devices International Limited 19 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 PC could use the MPSSE (and D2XX driver) to download configuration data to the FPGA over USB. This data would define the hardware function on power up. The MPSSE can be used to control a number of GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 13. 64 Pin No. 56 Pin No Name Type MPSSE Configuration Description Clock Signal Output. For example: JTAG – TCK, Test interface clock SPI (MASTER) – SK, Serial Clock I2C – SCK, Serial Clock Line Serial Data Output. For example: JTAG – TDI, Test Data Input SPI (MASTER) – DO I2C – SDA, Serial Data Line* Serial Data Input. For example: JTAG – TDO, Test Data output SPI (MASTER) – DI, Serial Data Input I2C – SDA, Serial Data Line* Output Signal Select. For example: JTAG – TMS, Test Mode Select SPI (MASTER) – CS, Serial Chip Select 28 23 TCK/SK OUTPUT 29 24 TDI/DO OUTPUT 30 25 TDO/DI INPUT 31 26 TMS/CS OUTPUT 32 27 GPIOL0 I/O General Purpose input/output 34 29 GPIOL1 I/O General Purpose input/output 35 30 GPIOL2 I/O General Purpose input/output 36 31 GPIOL3 I/O General Purpose input/output 37 32 GPIOH0 I/O General Purpose input/output 38 33 GPIOH1 I/O General Purpose input/output 39 34 GPIOH2 I/O General Purpose input/output 40 35 GPIOH3 I/O General Purpose input/output 42 37 GPIOH4 I/O General Purpose input/output 43 38 GPIOH5 I/O General Purpose input/output 44 39 GPIOH6 I/O General Purpose input/output 47 42 GPIOH7 I/O General Purpose input/output Table 13 - MPSSE Configured Pin Descriptions *: The DI and DO pins need connected together in order to create the full SDA signal for I2C. The DO pin requires configuration as an input except when transmitting in order to avoid driver contention during a slave transmission. For functional description of this mode, please refer to section 4.8. 3.7.6 FT233HP/FT232HP Pins used as a Fast Serial Interface The FT233HP/FT232HP can be configured for use with high-speed bi-directional isolated serial data. A proprietary FTDI protocol designed to allow galvanic isolated devices to communicate synchronously with the FT233HP/FT232HP using just 4 signal wires (over two dual opto-isolators), and two power lines. The peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. 12 Mbps (USB full speed) data rates can be achieved when using the proper high speed opto-isolators (see App Note AN-131). When configured in this mode, the pins used and the descriptions of the signals are shown in Table 14. 64 Pin No. Fast Serial Interface Configuration Description 56 Pin No Name Type 28 23 FSDI INPUT Fast serial data input. 29 24 FSCLK INPUT Fast serial clock input. Clock input to FT233H chip to clock data in or out. 30 25 FSDO OUTPUT Fast serial data output. Copyright © Future Technology Devices International Limited 20 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 31 42 Fast serial Clear To Send signal output. Driven low to indicate that the chip is ready to send data The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. 37 SIWU# INPUT During normal operation (PWREN# = 0), if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used. Table 14 - Fast Serial Interface Configured Pin Descriptions 26 FSCTS OUTPUT For a functional description of this mode, please refer to section 4. 3.7.7 FT233HP/FT232HP Pins Configured as a CPU-style FIFO Interface The FT233HP/FT232HP can be configured in a CPU-style FIFO interface mode which allows a CPU to interface to USB via the FT233HP/FT232HP. This mode is enabled in the external EEPROM. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 15. 64 Pin No. 28,29,30, 31,32,34, 35,36 56 Pin No 23,24,25, 26,27,29, 30,31 ADBUS[7:0] 37 32 CS# INPUT Active low chip select input 38 33 A0 INPUT Address bit A0 39 34 RD# INPUT Active Low FIFO Read input 40 35 WR# INPUT 42 Name Type I/O Fast Serial Interface Configuration Description D7 to D0 bidirectional data bus Active Low FIFO Write input Tie this pin to VCCIO if not used – otherwise, for normal operation The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB 37 SIWU# INPUT Bus. Normally, this can be used to wake up the Host PC. During normal operation (PWREN# = 0), if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Table 15 - CPU-style FIFO Interface Configured Pin Descriptions For a functional description of this mode, please refer to section 4.10. Copyright © Future Technology Devices International Limited 21 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 3.7.8 FT233HP/FT232HP Pins Configured as a FT1248 Interface The FT233HP/FT232HP can be configured as a proprietary FT1248 interface. This mode is enabled in the external EEPROM. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 16. 64 Pin No. 56 Pin No Name 28 23 MIOSIO0 29 24 MIOSIO1 30 25 MIOSIO2 31 26 MIOSIO3 32 27 MIOSIO4 34 29 MIOSIO5 35 30 MIOSIO6 36 31 MIOSIO7 37 32 SCLK INPUT 38 33 SS_n INPUT 39 34 Type UART Configuration Description INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T INPUT /OUTPU T Bi-directional synchronous command and data bus, bit 0 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 1 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 2 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 3 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 4 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 5 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 6 used to transmit and receive data from/to the master Bi-directional synchronous command and data bus, bit 7 used to transmit and receive data from/to the master Serial clock used to drive the slave device data Active low slave select 0 from master to slave Slave output used to transmit the status of the MISO OUTPUT transmit and receive buffers are empty and full respectively Table 16 - FT1248 Configured Pin Descriptions For functional description of this mode, please refer to section 4.6. Copyright © Future Technology Devices International Limited 22 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4 Function Description The FT233HP/FT232HP is a USB 2.0 Hi-Speed (480Mb/s) to UART/FIFO IC with USB Type-C/PD ports. It can be configured in a variety of industry standard serial or parallel interfaces, such as UART, FIFO, JTAG, SPI (MASTER) or I2C (MASTER) modes. In addition to these, the FT233HP/FT232HP introduces the FT1248 interface and supports a CPU-Style FIFO mode, bit-bang and a fast serial interface mode. The FT233HP has two Type-C/PD ports, with PD1 port supporting both power sink and source roles, and PD2 port (FT233HPQ and FT233HPL only) working as a power sink port. Both PD ports support 5V3A, 9V3A, 12V3A, 15V3A and 20V3A PDO profiles, and these profiles are configurable through the external EEPROM at power-up or reset. PD1 port shares the same Type-C connector with USB data, and the PD2 port is a power port only without USB data. 4.1 Key Features USB Type-C/PD Controller. The FT233HP/FT232HP supports USB Type-C specification version 1.3. The FT233HP/FT232HP integrates a USB PD 3.0 controller. USB PD port 1 is USB PD3.0 with the USB 2.0 function. The first USB PD power is initial power sink when local power source is presented, it can become power source via PD negotiation. The FT233HP has a second USB PD sink only port to connect to a PD power source. The FT233HP/FT232HP USB PD 3.0 function is backward compatible to the USB PD 2.0 standard. USB Hi-Speed to UART/FIFO Interface. The FT233HP/FT232HP provides USB 2.0 Hi-Speed (480Mbits/s) to flexible and configurable UART/FIFO Interfaces. Functional Integration. The FT233HP/FT232HP integrates a USB protocol engine which controls the physical Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 HiSpeed interface. The FT233HP/FT232HP includes an integrated +1.2V Low Drop-Out (LDO) regulator. It also includes 1Kbytes Tx and Rx data buffers. The FT233HP/FT232HP integrates the entire USB protocol on chip with no firmware required. MPSSE. Multi- Protocol Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides flexible synchronous interface configurations. FT1248 interface. The FT233HP/FT232HP supports a new proprietary half-duplex FT1248 interface with a variable bi-directional data bus interface that can be configured as 1, 2, 4, or 8-bits wide and this enables the flexibility to expand the size of the data bus to 8 pins. For details regarding 2-bit, 4-bit and 8-bit modes, please refer to application note AN_167 FT1248 Serial Parallel Interface Basics. Data Transfer rate. The FT233HP/FT232HP supports a data transfer rate up to 12 Mbaud when configured as an RS232/RS422/RS485 UART interface up to 40 Mbytes/second over a synchronous 245 parallel FIFO interface or up to 8 Mbyte/Sec over an asynchronous 245 FIFO interface. Please note the FT233HP/FT232HP does not support the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud. Latency Timer. A feature of the driver used as a timeout to transmit short packets of data back to the PC. The default is 16ms, but it can be altered between 1ms and 255ms. Bus (ACBUS) functionality, signal inversion and drive strength selection. There are 11 configurable ACBUS I/O pins. These configurable options are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. TXDEN – transmit enable for RS485 designs. PWREN# - Power control for high power, bus powered designs. TXLED# - for pulsing an LED upon transmission of data. RXLED# - for pulsing an LED upon receiving data. TX&RXLED# - which will pulse an LED upon transmission OR reception of data. SLEEP# - indicates that the device going into USB suspend mode. CLK30 / CLK15 / CLK7.5 – 30MHz, 15MHz and 7.5MHz clock output signal options. TriSt-PU – Input pulled up, not used DRIVE 1 – Output driving high DRIVE 0 – Output driving low I/O mode – ACBUS Bit Bang Copyright © Future Technology Devices International Limited 23 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 The ACBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose I/O pins (ACBUS 5, 6, 8 and 9) which are available during normal operation. The ACBUS lines can be configured with any one of these input/output options by setting bits in the external EEPROM. 4.2 Functional Block Descriptions Type-C/PD PHY and Controller. The FT233HP (FT233HPQ and FT233HPL only) has two Type-C/PD ports. Each port has Type-C/PD required Physical Layer (PHY) and controllers. PD1 port has built-in VCONN switches supporting up to 100mW VCONN power. PD Policy Engine. The PD policy engine is a 32bit RISC processor with 8kB data RAM and 48kB ROM. It manages both PD port 1 and port 2. Default PD configurations are stored in the ROM code. PD1 port can act as power sink or source role, supporting both normal power role swap. PD2 port (FT233HPQ and FT233HPL only) acts as power sink, which can be connected to a PD charger. By using an external EEPROM, it is possible to change the PD configuration based on specific use cases, such as port 1 sink, port 1 sink/source or PD charge through from port 2 to port 1. PDO voltage/current profiles can also be customised using EEPROM. I2C Slave Interface. The application can also choose to control the PD policy by external MCU through I2C interface. In this case the built-in PD policy engine is halted. The external MCU has full control to the two PD controller registers (FT233HPQ and FT233HPL only) through I2C access. An interrupt signal is also provided, so that an interrupt to an external MCU could be asserted when a PD event occurs. GPIO block. The GPIO block provides up to 8 GPIO pins which can be used as power switch controls based on the PD policy and profiles. Multi-Purpose UART/FIFO Controllers. The FT233HP/FT232HP has one independent UART/FIFO Controller. This controls the UART data, 245 FIFO data, Fast Serial (opto isolation) or Bit-Bang mode which can be selected by SETUP (FT_SetBitMode) command. Each Multi-Purpose UART/FIFO Controller also contains an MPSSE (Multi-Protocol Synchronous Serial Engine). Using this MPSSE, the Multi-Purpose UART/FIFO Controller can be configured under software command, to have one of the MPSSE (SPI (MASTER), I2C, and JTAG). USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol specification. Port FIFO TX Buffer (1Kbytes). Data from the Host PC is stored in these buffers to be used by the Multi-purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and FIFO control block. Port FIFO RX Buffer (1Kbytes). Data from the Multi-purpose UART/FIFO controllers is stored in these blocks to be sent back to the Host PC when requested. This is controlled by the USB Protocol Engine and FIFO control block. RESET Generator – The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input (with min pulse width 1.5 ms) pin allows an external device to reset the FT233HP/FT232HP. RESET# should be tied to VCCIO (+3.3V) if not being used. Baud Rate Generators – The Baud Rate Generators provides an x16 or an x10 clock input to the UART’s from a 120MHz reference clock and consists of a 14 bit pre-scaler and 4 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 12 Mbaud. See FTDI application note AN_120 Aliasing VCP Baud Rates for more details. EEPROM Interface. EEPROM is optional. When used without an external EEPROM the FT233HP/FT232HP defaults to a USB to an asynchronous serial port device with default profiles on 2 Type-C/PD ports. Adding an external 93LC66 EEPROM allows customization of USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT233HP/FT232HP for OEM applications, as well as PD port configurations and power profiles. Other parameters controlled by the EEPROM include Remote Wake Up, Soft Pull Down on Power-Off and I/O pin drive strength. Copyright © Future Technology Devices International Limited 24 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 The EEPROM must have a 16 bit wide configuration such as a Microchip 93LC66B or equivalent capable of a 1Mbit/s clock rate at VCC = 3.0V to 3.6V. The EEPROM is programmable in-circuit over USB using a utility program called FT_PROG available from FTDI’s web site – https://www.ftdichip.com/. This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT233HP/FT232HP will default to serial ports. The device uses its built-in default VID (0403), PID (6044), Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. LDO Regulator. The +1.2V LDO regulator generates the +1.2 volts for the core and the USB transceiver cell. Its input (VREGIN) must be connected to a +3.3V external power source. It is also recommended to add an external filtering capacitor to the VREGIN. There is no direct connection from the +1.2V output (VREGOUT) and the internal functions of the FT233HP/FT232HP. The PCB must be routed to connect VREGOUT to the pins that require the +1.2V including VREGIN. UTMI PHY. The Universal Transceiver Macrocell Interface (UTMI) physical interface cell. This block handles the Full speed / Hi-Speed SERDES (serialise – deserialise) function for the USB TX/RX data. It also provides the clocks for the rest of the chip. A 12 MHz crystal with ±30ppm must be connected to the OSCI and OSCO pins or 12 MHz Oscillator must be connected to the OSCI, and the OSCO is left unconnected. A 12K Ohm resistor should be connected between REF and GND on the PCB. The UTMI PHY functions include:       Supports 480 Mbit/s “Hi-Speed” (HS)/ 12 Mbit/s “Full Speed” (FS). SYNC/EOP generation and checking Data and clock recovery from serial stream on the USB. Bit-stuffing/unstuffing; bit stuff error detection. Manages USB Resume, Wake Up and Suspend functions. Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks. 4.3 FT233HP/FT232HP UART Interface Mode Description The FT233HP/FT232HP can be configured as a UART with external line drivers, similar to operation with the FTDI FT232R devices. The following examples illustrate how to configure the FT233HP/FT232HP with an RS232, RS422 or RS485 interface. 4.3.1 RS232 Configuration Figure 5 illustrates how the FT233HP/FT232HP can be configured with an RS232 UART interface. Figure 5 - RS232 Configuration Copyright © Future Technology Devices International Limited 25 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4.3.2 RS422 Configuration Figure 6 illustrates how the FT233HP/FT232HP can be configured as a RS422 interface. Figure 6 - RS422 Configuration In this case the FT233HP/FT232HP is configured as UART operating at TTL levels and a level converter device (full duplex RS485 transceiver) is used to convert the TTL level signals from the FT233HP/FT232HP to RS422 levels. The PWREN# signal is used to power down the level shifters such that they operate in a low quiescent current when the USB interface is in suspend mode. 4.3.3 RS485 Configuration Figure 7 illustrates how the FT233HP/FT232HP can be configured as a RS485 interface. Figure 7 - RS485 Configuration In this case the FT233HP/FT232HP is configured as a UART operating at TTL levels and a level converter device (half duplex RS485 transceiver) is used to convert the TTL level signals from the FT233HP/FT232HP to RS485 levels. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN pin on the FT233HP/FT232HP is provided for exactly that purpose, and so the transmitter enables are wired to the TXDEN. RS485 is a multi-drop network – i.e. Copyright © Future Technology Devices International Limited 26 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. 4.4 FT245 Synchronous FIFO Interface Mode Description When FT233HP/FT232HP is configured in an FT245 Synchronous FIFO interface mode the IO timing of the signals used are shown in Figure 8 which shows details for read and write accesses. The timings are shown in Figure 8. Note that only a read or a write cycle can be performed at any one time. Data is read or written on the rising edge of the CLKOUT clock. Figure 8 - FT245 Synchronous FIFO Interface Signal Waveforms Name Min t1 Nom Max 16.67 Units Comments ns CLKOUT period t2 7.5 8.33 9.17 ns CLKOUT high period t3 7.5 8.33 9.17 ns CLKOUT low period t4 0 9 ns CLKOUT to RXF# t5 0 9 ns CLKOUT to read DATA valid t6 0 9 ns OE# to read DATA valid t7 7.5 16.67 ns OE# setup time t8 0 ns OE# hold time t9 7.5 ns RD# setup time to CLKOUT (RD# low after OE# low) t10 0 ns RD# hold time t11 0 9 ns CLKOUT TO TXE# t12 7.5 16.67 ns Write DATA setup time t13 0 ns Write DATA hold time t14 7.5 ns WR# setup time to CLKOUT (WR# low after TXE# low) t15 0 16.67 16.67 WR# hold time Table 17 - FT245 Synchronous FIFO Interface Signal Timings Copyright © Future Technology Devices International Limited 27 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 This mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60 MHz CLKOUT clock for the external system to use. Note that Asynchronous FIFO mode must be selected in the EEPROM before selecting the Synchronous FIFO mode in software. 4.4.1 FT245 Synchronous FIFO Read Operation A read operation is started when the chip drives RXF# low. The external system can then drive OE# low to turn the data bus drivers around before acknowledging the data with the RD# signal going low. The first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored. 4.4.2 FT245 Synchronous FIFO Write Operation A write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst operation can be done on every clock providing TXE# is still low. The external system must monitor TXE# and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for each byte of data to be accepted. 4.5 FT245 Style Asynchronous FIFO Interface Mode Description The FT233HP/FT232HP can be configured as an asynchronous FIFO interface. This mode is similar to the synchronous FIFO interface with the exception that the data is written to or read from the FIFO on the falling edge of the WR# or RD# signals. This mode does not provide a CLKOUT signal and it does not expect an OE# input signal. The following diagrams illustrate the asynchronous FIFO mode timing. Figure 9 - FT245 Asynchronous FIFO Interface READ Signal Waveforms Figure 10 - FT245 Asynchronous FIFO Interface WRITE Signal Waveforms Copyright © Future Technology Devices International Limited 28 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Time T1 Description RD# inactive to RXF# Min 1 RXF# inactive after RD# cycle T3 RD# to DATA T4 RD# active pulse width 30 T5 RD# active after RXF# 0 T6 WR# active to TXE# inactive 1 T7 TXE# active to TXE# after WR# cycle T8 T9 T11 14 49 T2 T10 Max 1 Units Ns Ns 14 Ns Ns Ns 14 Ns 49 Ns DATA to WR# active setup time 5 Ns DATA hold time after WR# inactive 5 Ns WR# active pulse width 30 Ns WR# active after TXE# 0 Ns Table 18 - Asynchronous FIFO Timings (based on standard drive level outputs) 4.6 FT1248 Interface Mode Description The FT233HP/FT232HP supports a half-duplex FT1248 Interface that provides a flexible data communication and high performance interface between the FT233HP/FT232HP as a FT1248 slave and an external FT1248 master. The FT1248 protocol is a dynamic bi-directional data bus interface that can be configured as 1, 2, 4, or 8-bits wide. Figure 11 - FT1248 Bus with Single Master and Slave. In the FT1248 there are 3 distinct phases: While SS_n is inactive, the FT1248 reflects the status of the write buffer and read buffers on the MIOSIO[0] and MISO wires respectively. Additionally, the FT1248 slave block supports multiple slave devices where a master can communicate with multiple FT1248 slave devices. When the slave is sharing buses with other FT1248 slave devices, the write and read buffer status cannot be reflected on the MIOSIO[0] and MISO wires during SS_n inactivity as this would cause bus contention. Therefore, it is possible for the user to select whether they wish to have the buffer status switched on or off during inactivity. When SS_n is active a command/bus size phase occurs first. Following the command phase is the data phase, for each data byte transferred the FT1248 slave drives an ACK/NAK status onto the MISO wire. The master can send multiple data bytes so long as SS_n is active, if a unsuccessful data transfer occurs, i.e. a NAK happens on the MISO wire then the master should immediately abort the transfer by de-asserting SS_n. Copyright © Future Technology Devices International Limited 29 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 CLK SCLK WRITE READ SS_n WRITE DATA BUS TURNAROUND MIOSIO[0] MISO TXE# RXF# CMD RDATA0 STATUS RDATA1 RDATA2 TXE# STATUS STATUS RXF# CMD WDATA 0 STATUS WDATA 1 TXE# STATUS RXF# Figure 12 - FT1248 Basic Waveform Protocol Section 4.6.2 illustrates the FT1248 write and read protocol operating in 1-bit mode. For details regarding 2-bit, 4-bit and 8-bit modes, please refer to application note AN_167_FT1248 Parallel Serial Interface Basics. 4.6.1 Bus Width Protocol Decode In order for the FT1248 master to determine the bus width within the command phase the bus width is encoded along with the actual commands on the first active clock edge when SS_n is active and has a data width of 8-bits. If any of the MIOSIO [7:4] signals are low then the data transfer width equals 8-bits. If any of the MIOSIO [3:2] signals are low then the data transfer width equals 4-bits. If MIOSIO [1] signal is low then the data transfer width equals 2-bits. Else the bus width is defaulted to 1-bit. Please note that if both of the MIOSIO bit signals are low then the data transfer width is equal to the width of high priority MIOSIO bit signal. For example if both of the MIOSIO [7:3] signals are low then the data transfer width equals 8-bits or if both of the MIOSIO [3:1] signals are low then the data transfer width equals 4-bits. In order to successfully decode the bus width, all MIOSIO signals must have pull up resistors. By default, all MIOSIO signals shall be seen by the FT233HP/FT232HP in FT1248 mode as logic ‘1’. This means that when a FT1248 master does not wish to use certain MIOSIO signals the slave (FT233HP/FT232HP) is still capable of determining the requested bus width since any unused MIOSIO signals shall be pull up in the slave. The remaining bits used during the command phase are used to contain the command itself which means that it is possible to define up to 16 unique commands. Copyright © Future Technology Devices International Limited 30 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 LSB CMD[3] 1-bit Bus Width 2-bit Bus Width 4-bit Bus Width 8-bit Bus Width MSB BWID 2-bit BWID 4-bit CMD[2] BWID 8-bit CMD[1] CMD[0] X 0 1 2 3 4 5 6 7 CMD[3] X X CMD[2] X CMD[1] CMD[0] X 0 1 2 3 4 5 6 7 CMD[3] 0 X CMD[2] X CMD[1] CMD[0] X 0 1 2 3 4 5 6 7 CMD[3] X 0 CMD[2] X CMD[1] CMD[0] X 0 1 2 3 4 5 6 7 CMD[3] X X CMD[2] 0 CMD[1] CMD[0] X 1 2 3 4 5 6 7 0 Figure 13 - FT1248 Command Structure For more details about FT1248 Interface, please refer to application note AN_167_FT1248 Parallel Serial Interface Basics. 4.6.2 FT1248: 1-bit interface The FT1248 Interface transfers data over different bus widths (1-bit, 2-bit, 4-bit and 8-bit). Figure 14 and Figure 15 illustrates the waveform detailing the FT1248 write and read protocol operating in 1-bit mode with flow control. Please refer to the application notes AN_167_FT1248 Parallel Serial Interface Basics for more details regarding 1-bit without flow control, 2-bit, 4-bit and 8-bit modes. SCLK SS_n COMMAND PHASE WRITE DATA BUS TURNAROUND MIOSIO[0] TXE# 0 0 CMD2 0 CMD1 CMD0 B7 B6 B5 BUS TURNAROUND B4 B3 B2 B1 B0 TXE# PULLED HIGH MIOSIO[7:1] MISO CMD3 BUS TURNAROUND RXF# TXE# ACK RXF# Figure 14 - FT1248 1-bit Mode Protocol (WRITE) Copyright © Future Technology Devices International Limited 31 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 SCLK SS_n COMMAND PHASE READ DATA BUS TURNAROUND MIOSIO[0] TXE# CMD3 0 0 BUS TURNAROUND CMD2 0 CMD1 CMD0 B6 B5 B4 B3 B2 B1 B0 TXE# PULLED HIGH MIOSIO[7:1] MISO B7 RXF# RXF# ACK RXF# Figure 15 - FT1248 1-bit Mode Protocol (READ) When SS_n is inactive the write buffer and read buffer status is reflected on the MIOSIO[0] and MISO signals respectively. When the master wishes to initiate a data transfer, SS_n becomes active. As soon as SS_n becomes active the SPI slave immediately stops driving the MIOSIO[0] signal and SPI master is not allowed to begin driving the MIOSIO[0] signal until the first clock edge, this ensures that bus contention is avoided. On the first clock edge the command is shifted out for 7 clocks, on the 8 th clock cycle a bus turnaround is required. The bus turnaround is required as the slave may be required to drive the MIOSIO[0] bus with read data. The data phase occurs in response to the command and so long as SS_n remains active. The data phase in 1-bit mode requires 8 clock cycles where the MIOSIO[0] signal transfers the requested write or read data. The MISO signal indicates to the master the success of the transfer with an ACK or NAK. The status is reflected through the whole of the data phase and is valid from the first clock edge. If the master is writing data to the slave, then on the last clock edge before it de-asserts SS_n must tristate the MIOSIO[0] signal to enable the bus to be “turned” around as when SS_n becomes inactive the FT1248 slave shall begin to drive the write buffer status onto the MIOSIO[0] signal. When the SPI slave is driving the MIOSIO[0] (the master is reading data) no bus turnaround is required as when SS_n becomes inactive it is required to drive the write buffer status to the FT1248 master. 4.7 Synchronous and Asynchronous Bit-Bang Interface Mode The FT233HP/FT232HP can be configured as a bit-bang interface. There are two types of bit-bang modes: synchronous and asynchronous. See application note AN2232-02 Bit Mode Functions for the FT232 for more details and examples of using both Synchronous and Asynchronous bit-bang modes. 4.7.1 Asynchronous Bit-Bang Mode Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode, except that the internal RD# and WR# strobes (RDSTB# and WRSTB#) are now brought out of the device to allow external logic to be clocked by accesses to the bit-bang IO bus. Copyright © Future Technology Devices International Limited 32 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Any data written to the device in the normal manner will be self-clocked onto the data pins (those which have been configured as outputs). Each pin can be independently set as an input or an output. The rate that the data is clocked out at is controlled by the baud rate generator. New data must be written, and the baud rate clock should tick to change the data. If no new data is written to the chip, the pins configured for output will hold the last value written. Asynchronous Bit-Bang mode is enabled using the FT_SetBitMode D2xx driver command with a hex value of 0x01. 4.7.2 Synchronous Bit-Bang Mode The synchronous Bit-Bang mode will only update the output parallel port pins whenever data is sent from the USB interface to the parallel interface. When this is done, the WRSTB# will activate to indicate that the data has been read from the USB Rx FIFO buffer and written out on the pins. Data can only be received from the parallel pins (to the USB Tx FIFO interface) after the parallel interface has been written to. With Synchronous Bit-Bang mode data will only be sent out by the FT233HP/FT232HP if there is space in the FT233HP/FT232HP USB TXFIFO for data to be read from the parallel interface pins. This Synchronous Bit-Bang mode will read the data bus parallel I/O pins first, before it transmits data from the USB RxFIFO. It is therefore 1 byte behind the output, and so to read the inputs for the byte that you have just sent, another byte must be sent. For example: (1)Pins start at 0xFF Send 0x55, 0xAA Pins go to 0x55 and then to 0xAA Data read = 0xFF,0x55 (2) Pins start at 0xFF Send 0x55, 0xAA, 0xAA (repeat the last byte sent) Pins go to 0x55 and then to 0xAA Data read = 0xFF, 0x55, 0xAA Synchronous Bit-Bang Mode differs from Asynchronous Bit-Bang mode in that the device parallel output is only read when the parallel output is written to by the USB interface. This makes it easier for the controlling program to measure the response to a USB output stimulus as the data returned to the USB interface is synchronous to the output data. Synchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command with a hex value of 0x04. An example of the synchronous bit-bang mode timing is shown in Figure 16. WRSTB# RDSTB# Figure 16 - Synchronous Bit-Bang Mode Timing Interface Example WRSTB# = this output indicates when new data has been written to the I/O pins from the Host PC (via the USB interface). Copyright © Future Technology Devices International Limited 33 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Name t1 Description Current pin state is read t2 RDSTB# is set inactive and data on the parallel I/O pins is read and sent to the USB host. T3 RDSTB# is set active again, and any pins that are output will change to their new data t4 1 clock cycle to allow for data setup WRSTB# goes active. This indicates that the host PC has written new data to the I/O parallel data pins WRSTB# goes inactive Table 19 - Synchronous Bit-Bang Mode Timing Interface Example Timings t5 t6 RDSTB# = this output rising edge indicates when data has been read from the I/O pins and sent to the Host PC (via the USB interface). The WRSTB# goes active in t5. The WRSTB# goes active when data is read from the USB RXFIFO (i.e. sent from the PC). The RDSTB# goes inactive when data is sampled from the pins and written to the USB TXFIFO (i.e. sent to the PC). The SETUP command to the FT233HP/FT232HP is used to setup the bitmode. This command also contains a byte wide data mask to set the direction of each bit. The direction on each pin doesn’t change unless a new SETUP command is used to modify the direction. The WRSTB# and RDSTB# strobes are only a guide to what may be happening depending on the direction of the bus. For example if all pins are configured as inputs, it is still necessary to write to these pins in order to get the FT233HP/FT232HP to read those pins even though the data written will never appear on the pins. Signals and data-flow are illustrated in Figure 17. WRSTB# USB Rx FIFO/ Buffer USB Parallel I/O data Parallel I/O pins USB Tx FIFO/ Buffer RDSTB# Figure 17 - Bit-bang Mode Dataflow Illustration Diagram 4.8 MPSSE Interface Mode Description MPSSE Mode is designed to allow the FT233HP/FT232HP to interface efficiently with synchronous serial protocols such as JTAG, I2C (MASTER) and SPI (MASTER) Bus. It can also be used to program SRAM based FPGA’s over USB. The MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous serial protocol (industry standard or proprietary) to be implemented using the FT233HP/FT232HP. MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of 30 Mbits/s. When the FT233HP/FT232HP is configured in MPSSE mode, the IO timing and signals used are shown in Figure 18 and Table 20. These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to be provide a slower clock. Copyright © Future Technology Devices International Limited 34 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Figure 18 - MPSSE Signal Waveforms Name Min Typ Max Units Comments t1 32.66 33.33 33.99 Ns CLKOUT period t2 15 16.67 18.33 Ns CLKOUT high period t3 15 16.67 18.33 Ns CLKOUT low period t4 0 7.50 Ns CLKOUT to TDI/DO delay t5 0 Ns TDI/DO hold time t6 11 Ns TDI/DO setup time Table 20 - MPSSE Signal Timings MPSSE mode is enabled using the FT_SetBitMode D2XX driver command with a hex value of 0x02. A hex value of 0x00 will reset the device. See application note AN135 – MPSSE Basics for more details and examples. The MPSSE command set is fully described in application note AN108 – Command Processor For MPSSE and MCU Host Bus Emulation Modes. The following additional libraries and application notes are available for configuring the MPSSE for SPI Master, I2C Master and JTAG at the following link: https://www.ftdichip.com/Support/SoftwareExamples/MPSSE.htm 4.8.1 MPSSE Adaptive Clocking The Adaptive Clock mode correlates the CLK signal with a return clock RTCK. This is a technique used by ARM® processors. The FT233HP/FT232HP will assert the TCK line and wait for the RTCK to be returned from the target device to GPIOL3 line before changing the TDO (data out line). Figure 19 - Adaptive Clocking Interconnect Copyright © Future Technology Devices International Limited 35 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 TDO changes on falling edge of TCK TDO TCK RTCK Figure 20 - Adaptive Clocking Waveform Adaptive clocking is not enabled by default. For further details on MPSSE adaptive clocking please refer to AN_108 Command Processor For MPSSE and MCU Host Bus Emulation Modes. 4.9 Fast Serial Interface Mode Description Fast Serial Interface Mode provides a method of communicating with an external device over USB using 4 wires that can have opto-isolators in their path, thus providing galvanic isolation between systems. Fast serial mode is enabled by setting the appropriate bits in the external EEPROM. The fast serial mode can be held in reset by setting a bit value of 0x10 using the FT_SetBitMode D2XX driver command. While this bit is set the device is held reset – data can be sent to the device, but it will not be sent out by the device until the device is enabled again. This is done by sending a bit value of 0x00 using the Set Bit Mode command. When the FT233HP/FT232HP is configured in Fast Serial Interface mode the IO timing of the signals used are shown in Figure 21 and the timings are shown in Table 21. Figure 21 - Fast Serial Interface Signal Waveforms Name Minimum Typical Maximu Units Description t1 5 ns FSDO/FSC TS hold time t2 5 ns FSDO/FSC TS setup time t3 5 ns FSDI hold time t4 10 ns FSDI Setup Time t5 10 ns FSC LK low t6 10 ns FSC LK high t7 20 ns FSC LK Period Table 21 - Fast Serial Interface Signal Timings Copyright © Future Technology Devices International Limited 36 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4.9.1 Outgoing Fast Serial Data To send fast serial data out of the FT233HP/FT232HP, the external device must drive the FSCLK clock. If the FT233H has data ready to send, it will drive FSDO output low to indicate the start bit. It will not do this if it is currently receiving data from the external device. This is illustrated in Figure 22. FSCLK FSDO 0 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Data Bits - LSB first SRCE Source Bit Figure 22 - Fast Serial Interface Output Data Notes: 1. 2. 3. 4. The first bit output (Start bit) is always 0. FSDO is always sent LSB first. The last serial bit output is the source bit (SRCE) is always 0. If the target device is unable to accept the data when it detects the START bit, it should stop the FSCLK until it can accept the data. 4.9.2 Incoming Fast Serial Data An external device is allowed to send data into the FT233HP/FT232HP if FSCTS is high. On receipt of a zero START bit on FSDI, the FT233HP/FT232HP will drop FSCTS on the next positive clock edge. The data from bits 0 to 7 are then clocked in (LSB first). The last bit (DEST) determines where the data will be written to. This bit is always 0 with the FT233HP/FT232HP. This is illustrated in Figure 23. FSCTS FSCLK FSDI 0 Start Bit D0 D1 D2 D3 D4 D5 D6 Data Bits - LSB first D7 DEST Destination Bit Figure 23 - Fast Serial Interface Input Data Notes: 1. The first bit input (Start bit) is always 0. 2. FSDI is always received LSB first. 3. The last received serial bit is the destination bit (DEST) is always 0. 4. The target device should ensure that FSCTS is high before it sends data. FSCTS goes low after data bit 0 (D0) and stays low until the chip can accept more data. 4.9.3 Fast Serial Data Interface Example Figure 24 shows example of two Agilent HCPL-2430 (see the semiconductor section at https://www.broadcom.com) Hi-Speed opto-couplers used to optically isolate an external device which interfaced to USB using the FT233HP/FT232HP. In this example VCC5V is the USB VBUS supply and VCCE is the supply to the external device. Care must be taken with the voltage used to power the photo-LED. It must be the same voltage as that which the FT233HP/FT232HP I/Os are driving to, or the LED’s may be permanently on. Limiting resistors should be fitted in the lines that drive the diodes. The outputs of the opto-couplers are open-collector and require a pull-up resistor. Copyright © Future Technology Devices International Limited 37 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Figure 24 - Fast Serial Interface Example 4.10 CPU-style FIFO Interface Mode Description CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT233HP/FT232HP. This mode is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit (A0). When the FT233HP/FT232HP is in CPU-style Interface mode, the IO signal lines are configured as given in Table 22. This mode uses a combination of CS# and A0 to determine the operation to be carried out. The following Table 23 gives the decode values for particular operations. CS# 1 0 0 A0 X 0 1 Table 22 - CPU-Style FIFO RD# WR# X X Read Data Pipe Write Data Pipe Read Status Send Immediate Interface Operation Select The Status read is shown in Table 23 – Data Bit Data Status bit 0 1 Data available (=RXF) bit 1 1 Space available (=TXE) bit 2 1 Suspend bit 3 1 Configured bit 4 X X bit 5 X X bit 6 X X bit 7 X X Table 23 - CPU-Style FIFO Interface Operation Read Status Description Note that bits 7 to 4 can be arbitrary values and that X= not used. The timing of reading and writing in this mode is shown in Figure 25 and Table 24. Copyright © Future Technology Devices International Limited 38 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Figure 25 - CPU-Style FIFO Interface Operation Signal Waveforms Data Bit t1 t2 t3 t4 t5 t6 t7 t8 t9 Nom Max Units Comment 5 Ns A0/CS# setup time to WR# 5 Ns A0/CS# hold time after WR# inactive 5 Ns A0/CS# setup time to RD# 5 Ns A0/CS# hold time after RD# inactive 5 Ns D to WR# 36active setup time 5 Ns D hold time after WR# inactive 1 14 ns RD# to D 30 ns WR# active pulse width 30 ns RD# active pulse width Table 24 - CPU-Style FIFO Interface Operation Signal Timing An example of the CPU-style FIFO interface connection is shown in Figure 26. Figure 26 - CPU-Style FIFO Interface Example Copyright © Future Technology Devices International Limited 39 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4.11 RS232 UART Mode LED Interface Description When configured in UART mode the FT233HP/FT232HP has two IO pins dedicated to controlling LED status indicators, one for transmitted data the other for received data. When data is being transmitted or received the respective pins drive from tristate to low in order to provide indication on the LED’s of data transfer. A digital one-shot timer is used so that even a small percentage of data transfer is visible to the end user. Figure 27 - Dual LED UART Configuration Figure 27 shows a configuration using two individual LED’s – one for transmitted data the other for received data. Figure 28 - Single LED UART Configuration In Figure 28 transmit and receive LED indicators are wire-OR’ed together to give a single LED indicator which indicates any transmit or receive data activity. Note that the LED’s are connected to the same supply as VCCIO. 4.12 Send Immediate/Wake Up (SIWU#) The SIWU# pin is available in the FIFO modes and in bit-bang mode. The Send Immediate portion is used to flush data from the chip back to the PC. This can be used to force short packets of data back to the PC without waiting for the latency timer to expire. To avoid overrunning, this mechanism should only be used when a process of sending data to the chip has been stopped. The data transfer is flagged to the USB host by the falling edge of the SIWU# signal. The USB host will schedule the data transfer on the next USB packet. Copyright © Future Technology Devices International Limited 40 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 CLKOUT WR# D7-D0 SIWU# Figure 29 - Using SIWU# When the pin is being used for a Wake Up function to wake up a sleeping PC a 20ms negative pulse on this pin is required. When the pin is used to immediately flush the buffer (Send Immediate) a 250ns negative pulse on this pin is required. Notes: 1. When using remote wake-up, ensure the resistors are pulled-up in suspend. Also ensure peripheral designs do not allow any current sink paths that may partially power the peripheral. 2. If remote wake-up is enabled, a peripheral is allowed to draw up to 2.5mA in suspend. If remote wake-up is disabled, the peripheral must draw no more than 500uA in suspend. 3. If a Pull-down is enabled, the FT233HP/FT232HP will not wake up from suspend when using SIWU# 4. In UART mode the RI# pin acts as the wake up pin. 4.13 FT233HP/FT232HP Mode Selection The FT233HP/FT232HP defaults to asynchronous serial interface (UART) mode of operation. After a reset the required mode is determined by the contents of the external EEPROM which can be programmed using FT_Prog. The EEPROM contents determine if the FT233HP/FT232HP device is configured as FT233HP/FT232HP asynchronous serial interface, FT245 FIFO interface, CPU-style FIFO interface, FT1248 or Fast Serial Interface. Following a reset, the EEPROM is read and the FT233HP/FT232HP configured for the selected mode. After device enumeration, the FT_SetBitMode command (refer to D2XX_Programmers_Guide) can be sent to the USB driver to switch the selected interface into other modes – asynchronous bit-bang, synchronous bit-bang or MPSSE – if required. When in FT245 FIFO mode, the FT_SetBitMode command can be used to select Synchronous FIFO (FT_SetBitMode = 0x40). Note that FT245 FIFO mode must be configured in the EEPROM before selecting the Synchronous FIFO mode. The drive strength selection, slew rate and Schmitt input function can also be configured in the EEPROM. The MPSSE can be configured directly using the D2XX commands. The D2XX_Programmers_Guide is available from the FTDI website. The application note AN_108 – Command Processor for MPSSE and MCU Host Bus Emulation Modes gives further explanation and examples for the MPSSE. Copyright © Future Technology Devices International Limited 41 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 4.14 Modes Configuration This section summarises what modes are configurable using the external EEPROM or the application software. EEPROM configured Applicatio n Software configured ASYNC Serial UART STYLE ASYNC 245 FIFO SYNC 245 PARAL LEL FIFO FT1248 ASYNC BitBang SYNC BitBang MPSSE Fast Serial Interf ace CPUStyle FIFO YES YES YES YES NO NO NO YES YES NO NO YES NO YES YES YES RESET NO Table 25 - Configuration Using EEPROM and Application Software Note: 1. The Synchronous 245 FIFO mode requires both the EEPROM and application software mode settings 2. The application software can be used to reset the fast serial interface controller Copyright © Future Technology Devices International Limited 42 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 5 USB Type-C/Power Delivery 3.0 Controller 5.1 PD Controller Description The FT233HP/FT232HP has a Type-C/PD controller that fully supports the latest USB Type-C and Power Delivery (PD) 3.0 standards enabling support for power negotiation with the ability to sink or source current to a USB host device. There are two PD ports in the device (FT233HPQ and FT233HPL only), one port is with the legacy USB 2.0 port to form USB PD port as a power sink or source, and the other port is standalone PD port as a sink which is used to connect to PD power source. Power Delivery function is designed to meet PD2.0/3.0 specification. If the device is configured to be operated in legacy USB2.0 mode it will be backward compatible to FT232H in terms of USB2.0 and its peripheral IOs functions. Figure 30 – PD Working Diagram 5.2 Features                 PD 3.0 Compliant. Physical layer and Policy Engine. Initial Sink, with Dual Role Power (Power Role Swap) and vConn Swap support. Multiple Configurable Power Profiles. Supports up to 20V5A power profile. Charge through Support. Cable Attach and Orientation Detection. Supports 1.5A and 3A cables in Type-C legacy mode (NON-PD Mode). Profile Selection indication through GPIOs when operating In Sink Mode. Supports External MCU to take over the control. 8 bit register interface for a low speed processor, or optional I2C port Integrated Chapter 6 protocol reduces required MPU response time to 10mS. K code recognition/coding, preamble, CRC, etc offloaded from processor. VCONN 200mA protected driver switches Single 12MHz clock + 32KHz low power clock. Slew rate limited driving of CC cable lines drive to 1.1V and 300nS linear transition time. 5.3 AC timing on GPIO pins Best case transition time with 5pF load Rise(ns) Fall(ns) 1.2 1.1 Worst case transition time with 15pF load Rise(ns) Fall(ns) 6.0 6.5 Table 26 - AC timing on GPIO pins Copyright © Future Technology Devices International Limited 43 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 5.4 GPIO Timing for PD Operation GPIOs are used as a power profile indicator as well as power supply controllers. When operating as a Sink, GPIO pins are used for LOAD_EN* and ISET*. Depending on the kind of profile negotiated, the appropriate ISET* GPIO will go high followed by LOAD_EN* pin. The timing between this ISET* going high to LOAD_EN* can be as up to 12.5uS. When operating as a Source, GPIO pins are used as power supply controller. During Source operation, the initial voltage will be 5V and then depends on the profile setting; the PD controller can negotiate a higher voltage. Switching from 5V to higher Voltage or vice versa is controlled by switching GPIOs. 5V could be controlled by one Pin where as another higher Voltage is controlled by another pin. For example, below table shows a sample GPIO states for 3 different voltage cases. PS_EN* GPIO_9v* GPIO_20v* 5v HIGH LOW LOW 9V HIGH HIGH LOW 20V HIGH LOW HIGH Table 27 - Example GPIO states for power control In this case 5V to 9V or 5v to 20V is just an additional GPIO pin going high. In this case the timing does not matter. However in the scenario, when the profile changes from 9V to 20V there is one GPIO going low, and another one going high. In this case the delay between one pin going low to another pin going high can be up to 12.5uS. *: These five signals can be configured by software GPIOs setting but also corresponding to board design. 5.5 PD Voltage Parameter Based on USB Type-C specification, during initialization when Source connects to Sink, both are in the unattached state. Source firstly detects the Sink’s pull down on CC then enters attached state, Source turns on VBUS and VCONN. So USB Type-C specification requests voltage parameters shown below: Minimum Voltage Maximum Voltage Powered cable / 0.00V 0.15V adapter(vRa) Sink(vRd) 0.25V 1.50V No connect 1.65V (vOPEN) Table 28 - CC Voltage on Source Side - Default USB Threshold 0.20V Minimum Voltage Maximum Voltage Powered cable / 0.00V 0.35V adapter(vRa) Sink(vRd) 0.45V 1.50V No connect 1.65V (vOPEN) Table 29 - CC Voltage on Source Side - 1.5A @ 5V Threshold 0.40V Minimum Voltage Maximum Voltage Powered cable / 0.00V 0.75V adapter(vRa) Sink(vRd) 0.85V 2.45V No connect 2.75V (vOPEN) Table 30 - CC Voltage on Source Side - 3A @ 5V Threshold 0.80V Copyright © Future Technology Devices International Limited 1.60V 1.60V 2.60V 44 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 For better achieving USB Type-C specification request, we suggest to use P channel MOSFET to isolate DCDC power and FT233HP/FT232HP power in order to guarantee the expected voltage parameters. The equivalent circuit shown below: Figure 31 - P Channel MOSFET Equivalent Circuit Recommended MOSFET parameters: V(BR)DSS ID Gate Threshold Voltage -20V(typical) < -150mA < -0.6V Table 31 - P-Channel MOSFET Character Recommendation Copyright © Future Technology Devices International Limited 45 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 6 Devices Characteristics and Ratings 6.1 Absolute Maximum Ratings The absolute maximum ratings for the FT233HP/FT232HP devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these values may cause permanent damage to the device. Parameter Storage Temperature Floor Life (Out of Bag) At Factory Ambient (30°C / 60% Relative Humidity) Value -65°C to 150°C 168 Hours (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* Ambient Operating Temperature (Power -40°C to 85°C Applied) MTTF FT233HP/FT232HP TBD VCORE Supply Voltage -0.3 to +1.32 VCCIO IO Voltage -0.3 to +4.0 DC Input Voltage – USBDP and USBDM -0.5 to +3.63 DC Input Voltage – High Impedance Bi-directional (ACBUS and ADBUS powered from -0.3 to +5.8 VCCIO) DC Output Current – Outputs 16 Table 32 - Absolute Maximum Ratings Unit Degrees C Hours Degrees C Hours V V V V mA * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours. 6.2 DC Characteristics DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter VCORE VCCIO* VREGIN VREGOUT Description VCC Core Operating Supply Voltage VCCIO Operating Supply Voltage VREGIN Voltage regulator Input Voltage regulator Output Minimum Typical Maximum Units Conditions 1.08 1.20 1.32 V 2.97 3.30 3.63 V 3.00 3.30 3.60 V 1.08 1.20 1.32 V 150 mA VREGIN +3.3V and data transfer with 12Mbps Ireg Regulator Current 22.37 Icc1s VREGIN Suspend Supply Current 132.2 µA USB Suspend I_vcc_usb VCC_USB operating supply current 22.36 mA Data transfer with 12Mbps 1.72 mA I_vccio I_vcc_pd VCC_IO operating supply current Data transfer with 12Mbps VCC_PD suspend 23.5 uA supply current Table 33 - Operating Voltage and Current PD suspend Note: Failure to connect all VCCIO pins of the device will have unpredictable behaviour. Copyright © Future Technology Devices International Limited 46 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 The I/O pins are +3.3v cells, which are +5V tolerant (except the USB PHY pins). Parameter Description Voh Vih Vt VtVt+ Rpu Rpd Iin Typical Maximum Units 2.4 VCCIO VCCIO V 2.4 VCCIO VCCIO V 2.4 VCCIO VCCIO V 2.4 VCCIO VCCIO V 0 0.4 V 0 0.4 V 0 0.4 V 0 0.4 V Output Voltage High Vol Vil Minimum Output Voltage Low Conditions Ioh = +/-2mA I/O Drive strength* = 4mA I/O Drive strength* = 8mA I/O Drive strength* = 12mA I/O Drive strength* = 16mA Iol = +/-2mA I/O Drive strength* = 4mA I/O Drive strength* = 8mA I/O Drive strength* = 12mA I/O Drive strength* = 16mA Input low Switching 0.8 V LVTTL Threshold Input High Switching 2.0 V LVTTL Threshold Switching Threshold 1.5 V LVTTL Schmitt trigger negative 0.8 1.1 V going threshold voltage Schmitt trigger positive 1.6 2.0 V going threshold voltage Input pull-up resistance** 40 75 190 KΩ Vin = 0 Input pull-down resistance 40 75 190 KΩ Vin =VCCIO Input Leakage Current +/-1 μA Vin = 5V or 0V Table 34 - I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins) * The I/O drive strength and slow slew-rate are configurable in the EEPROM. ** The voltage pulled up to is VCCIO-0.9V in the worst case. DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter VCC_USB Iccphy Iccphy (susp) Parameter Voh Vol Vil Vih Description Minimum Typical Maximum Units PHY Operating Supply 3.0 3.3 3.6 V Voltage PHY Operating Supply ----60 mA Current PHY Suspend Supply ----2 mA Current Table 35 - PHY Operating Voltage and Current Description Minimum Typical Maximum Output Voltage High 2.8 3.6 Output Voltage Low 0 0.3 Input low Switching Threshold 0.8 Input High Switching Threshold 2.0 Table 36 - PHY I/O Pin Characteristics Copyright © Future Technology Devices International Limited Conditions 3.3V I/O Hi-speed operation at 480 MHz USB Suspend Units V V V V Conditions 47 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 6.3 ESD Tolerance ESD protection for FT233HP/FT232HP IO’s Parameter Human Body Model (HBM) Machine Mode (MM) Charge Device Model (CDM) Latch-up Reference Minimum JEDEC EIA/JESD22-A114-B, Class 2 JEDEC EIA/JESD22-A115-A, Class B JEDEC EIA/ JESD22-C101-D, Class-III JESD78, Trigger Class-II Table 37 - ESD Tolerance Typical Maximum Units ±2kV kV ±200V V ±500V V ±200mA mA 6.4 Thermal Characteristics Parameter ѲJA (FT233HPL) ѲJC (FT233HPL) ѲJA (FT233HPQ) ѲJC (FT233HPQ) ѲJA (FT232HPQ) ѲJC (FT232HPQ) Minimum Typical 54 12 29 1.0 23.65 9.35 Table 38 - Thermal Characteristics Copyright © Future Technology Devices International Limited Maximum Units °C/W °C/W °C/W °C/W °C/W °C/W 48 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 7 Package Parameters The FT233HP/FT232HP is available in three different packages. The FT232HPQ is the QFN-56 option, the FT233HPL is LQFP-64 package and the FT233HPQ is the QFN-64 package option. 7.1 FT232HPQ, QFN-56 Package Dimensions Figure 32 - 56 Pin QFN Package Details Copyright © Future Technology Devices International Limited 49 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 7.2 FT233HPQ, QFN-64 Package Dimensions Figure 33 - 64 Pin QFN Package Details Copyright © Future Technology Devices International Limited 50 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 7.3 FT233HPL, LQFP-64 Package Dimensions Figure 34 - 64 Pin LQFP Package Details Copyright © Future Technology Devices International Limited 51 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 7.4 Solder Reflow Profile Figure 35 - 64 Pin LQFP and QFN Reflow Solder Profile Copyright © Future Technology Devices International Limited 52 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Profile Feature Pb Free Solder Process (green material) SnPb Eutectic and Pb free (non green material) Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat - Temperature Min (Ts Min.) 150°C 100°C - Temperature Max (Ts Max.) 200°C 150°C - Time (ts Min to ts Max) 60 to 120 seconds 60 to 120 seconds Time Maintained Above Critical Temperature TL: 217°C 183°C - Temperature (TL) 60 to 150 seconds 60 to 150 seconds - Time (tL) Peak Temperature (Tp) 260°C Time within 5°C of actual Peak 30 to 40 seconds 20 to 40 seconds Temperature (tp) Ramp Down Rate 6°C / second Max. 6°C / second Max. Time for T= 25°C to Peak 8 minutes Max. 6 minutes Max. Temperature, Tp Table 39 - Reflow Profile Parameters Values SnPb Eutectic and Pb free (non green material) Package Thickness Volume mm3 < 350 Volume mm3 >=350 < 2.5 mm 235 +5/-0 deg C 220 +5/-0 deg C ≥ 2.5 mm 220 +5/-0 deg C 220 +5/-0 deg C Pb Free (green material) = 260 +5/-0 deg C Table 40 - Package Reflow Peak Temperature Copyright © Future Technology Devices International Limited 53 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 8 Contact Information Head Office – Glasgow, UK Branch Office – Tigard, Oregon, USA Future Technology Devices International Limited Unit 1, 2 Seaward Place, Centurion Business Park Glasgow G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 Future Technology Devices International Limited (USA) 7130 SW Fir Loop Tigard, OR 97223-8160 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) E-Mail (Sales) E-Mail (Support) E-Mail (General Enquiries) sales1@ftdichip.com support1@ftdichip.com admin1@ftdichip.com Branch Office – Taipei, Taiwan Future Technology Devices International Limited (Taiwan) 2F, No. 516, Sec. 1, NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8797 1330 Fax: +886 (0) 2 8751 9737 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) tw.sales1@ftdichip.com tw.support1@ftdichip.com tw.admin1@ftdichip.com us.sales@ftdichip.com us.support@ftdichip.com us.admin@ftdichip.com Branch Office – Shanghai, China Future Technology Devices International Limited (China) Room 1103, No. 666 West Huaihai Road, Shanghai, 200052 China Tel: +86 21 62351596 Fax: +86 21 62351595 E-mail (Sales) E-mail (Support) E-mail (General Enquiries) cn.sales@ftdichip.com cn.support@ftdichip.com cn.admin@ftdichip.com Web Site http://ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, a nd the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640 Copyright © Future Technology Devices International Limited . 54 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Appendix A – References Document References AN_108 – Command Processor for MPSSE and MCU Host Bus Emulation Modes AN_113 – Interfacing FT2232H Hi-Speed Devices to I2C Bus AN_114 – Interfacing FT2232H Hi-Speed Devices to SPI Bus AN_129 – Interfacing FT2232H Hi-Speed Devices to a JTAG TAP AN_135 – MPSSE Basics AN 411 - FTx232H MPSSE I2C Master Example in C# AN 355 - FT232H MPSSE Example - I2C Master Interface with Visual Basic AN_167_FT1248 Parallel Serial Interface Basics FT_PROG TN_167 FTDI FIFO Basics AN_120 Aliasing VCP Baud Rates MPSSE Example Projects (I2C Master, SPI Master, JTAG) Acronyms and Abbreviations Terms CPU EEPROM ESD FIFO I2C LDO LED LSB LQFP MPSSE PD QFN SPI TTL USB UART UTMI VCP Description Central Processing Unit Electrically Erasable Programmable Read Only Memory Electrostatic Discharge First In First Out Inter-Integrated Circuit Low Drop Out Light Emitting Diode Least Significant Bit First Low Profile Quad Flat Pack Multi- Protocol Synchronous Serial Engines Power Delivery Quad Flat Non-leaded package Serial Peripheral Interface Transistor-Transistor Logic Universal Serial Bus Universal Asynchronous Receiver / Transmitter Universal Transceiver Macrocell Interface Virtual COM Ports Copyright © Future Technology Devices International Limited 55 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Appendix B – List of Figures and Tables List of Tables Table 1 - FT233HP/FT232HP Pin Descriptions ................................................................................. 11 Table 2 - Power and Ground ......................................................................................................... 12 Table 3 - Common Function Pins ................................................................................................... 13 Table 4 - EEPROM Interface Group ................................................................................................ 13 Table 5 - Type-C/PD Port Pins ...................................................................................................... 13 Table 6 - GPIO Pins ..................................................................................................................... 13 Table 7 - UART Interface and ACBUS Group (see note 1) ................................................................. 15 Table 8 - ACBUS Configuration Control .......................................................................................... 16 Table 9 - UART Configured Pin Descriptions.................................................................................... 17 Table 10 - FT245 Synchronous FIFO Configured Pin Descriptions ...................................................... 18 Table 11 - FT245 Style Asynchronous FIFO Configured Pin Descriptions ............................................. 19 Table 12 - Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions .................................. 19 Table 13 - MPSSE Configured Pin Descriptions ................................................................................ 20 Table 14 - Fast Serial Interface Configured Pin Descriptions ............................................................. 21 Table 15 - CPU-style FIFO Interface Configured Pin Descriptions ....................................................... 21 Table 16 - FT1248 Configured Pin Descriptions ............................................................................... 22 Table 17 - FT245 Synchronous FIFO Interface Signal Timings ........................................................... 27 Table 18 - Asynchronous FIFO Timings (based on standard drive level outputs).................................. 29 Table 19 - Synchronous Bit-Bang Mode Timing Interface Example Timings......................................... 34 Table 20 - MPSSE Signal Timings .................................................................................................. 35 Table 21 - Fast Serial Interface Signal Timings ............................................................................... 36 Table 22 - CPU-Style FIFO Interface Operation Select...................................................................... 38 Table 23 - CPU-Style FIFO Interface Operation Read Status Description ............................................ 38 Table 24 - CPU-Style FIFO Interface Operation Signal Timing ........................................................... 39 Table 25 - Configuration Using EEPROM and Application Software ..................................................... 42 Table 26 - AC timing on GPIO pins ................................................................................................ 43 Table 27 - Example GPIO states for power control .......................................................................... 44 Table 28 - CC Voltage on Source Side - Default USB ....................................................................... 44 Table 29 - CC Voltage on Source Side - 1.5A @ 5V ......................................................................... 44 Table 30 - CC Voltage on Source Side - 3A @ 5V ............................................................................ 44 Table 31 - P-Channel MOSFET Character Recommendation .............................................................. 45 Table 32 - Absolute Maximum Ratings ........................................................................................... 46 Table 33 - Operating Voltage and Current ...................................................................................... 46 Table 34 - I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins) .......................................... 47 Table 35 - PHY Operating Voltage and Current ............................................................................... 47 Table 36 - PHY I/O Pin Characteristics ........................................................................................... 47 Table 37 - ESD Tolerance ............................................................................................................ 48 Table 38 - Thermal Characteristics ................................................................................................ 48 Table 39 - Reflow Profile Parameters Values ................................................................................... 53 Copyright © Future Technology Devices International Limited 56 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Table 40 - Package Reflow Peak Temperature ................................................................................ 53 List of Figures Figure 1 - FT233HP/FT232HP Block Diagram .................................................................................... 4 Figure 2 - FT233HPQ-64 Pin Schematic Symbol ................................................................................ 8 Figure 3 - FT233HPL-64 Pin Schematic Symbol ................................................................................. 9 Figure 4 - FT232HPQ-56 Pin Schematic Symbol .............................................................................. 10 Figure 5 - RS232 Configuration..................................................................................................... 25 Figure 6 - RS422 Configuration..................................................................................................... 26 Figure 7 - RS485 Configuration..................................................................................................... 26 Figure 8 - FT245 Synchronous FIFO Interface Signal Waveforms ...................................................... 27 Figure 9 - FT245 Asynchronous FIFO Interface READ Signal Waveforms ............................................ 28 Figure 10 - FT245 Asynchronous FIFO Interface WRITE Signal Waveforms ......................................... 28 Figure 11 - FT1248 Bus with Single Master and Slave. ..................................................................... 29 Figure 12 - FT1248 Basic Waveform Protocol .................................................................................. 30 Figure 13 - FT1248 Command Structure ........................................................................................ 31 Figure 14 - FT1248 1-bit Mode Protocol (WRITE) ............................................................................ 31 Figure 15 - FT1248 1-bit Mode Protocol (READ) .............................................................................. 32 Figure 16 - Synchronous Bit-Bang Mode Timing Interface Example ................................................... 33 Figure 17 - Bit-bang Mode Dataflow Illustration Diagram ................................................................. 34 Figure 18 - MPSSE Signal Waveforms ............................................................................................ 35 Figure 19 - Adaptive Clocking Interconnect .................................................................................... 35 Figure 20 - Adaptive Clocking Waveform ....................................................................................... 36 Figure 21 - Fast Serial Interface Signal Waveforms ......................................................................... 36 Figure 22 - Fast Serial Interface Output Data ................................................................................. 37 Figure 23 - Fast Serial Interface Input Data ................................................................................... 37 Figure 24 - Fast Serial Interface Example ...................................................................................... 38 Figure 25 - CPU-Style FIFO Interface Operation Signal Waveforms .................................................... 39 Figure 26 - CPU-Style FIFO Interface Example ................................................................................ 39 Figure 27 - Dual LED UART Configuration ....................................................................................... 40 Figure 28 - Single LED UART Configuration .................................................................................... 40 Figure 29 - Using SIWU# ............................................................................................................. 41 Figure 30 – PD Working Diagram .................................................................................................. 43 Figure 31 - P Channel MOSFET Equivalent Circuit ............................................................................ 45 Figure 32 - 56 Pin QFN Package Details ......................................................................................... 49 Figure 33 - 64 Pin QFN Package Details ......................................................................................... 50 Figure 34 - 64 Pin LQFP Package Details ........................................................................................ 51 Figure 35 - 64 Pin LQFP and QFN Reflow Solder Profile .................................................................... 52 Copyright © Future Technology Devices International Limited 57 FT233HP/FT232HP Datasheet Version 1.0 Document No.: FT_001484 Clearance No.: FTDI#558 Appendix C – Revision History Document Title: FT233HP/FT232HP Datasheet Document Reference No.: FT_001484 Clearance No.: FTDI#558 Product Page: https://www.ftdichip.com/Products/ICs.htm Document Feedback: Send Feedback Revision Version 1.0 Changes Initial Release Copyright © Future Technology Devices International Limited Date 26-06-2020 58