FT245BL

FT245BL USB FIFO ( USB - Parallel ) I.C. The FT245BL is the lead free version of the 2nd generation of FTDI’s popular USB FIFO I.C. This device not only adds extra functionality to its FT8U245AM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas. 1.0 • • • • • • HARDWARE FEATURES Single Chip USB  Parallel FIFO bi-directional Data Transfer Transfer Data rate to 1M Byte / Sec - D2XX Drivers Transfer Data rate to 300 Kilobyte / Sec - VCP Drivers Simple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface Entire USB protocol handled on-chip… no USBspecific firmware programming required FTDI’s royalty-free VCP and D2XX drivers eliminate the requirement for USB driver development in most cases. • • • • • • • • • • • • 384 Byte FIFO Tx buffer / 128 Byte FIFO Rx Buffer for high data throughput. New Send Immediate support via SI Pin for optimised data throughput. Support for USB Suspend / Resume through PWREN# and WAKEUP pins. Support for high power USB Bus powered devices through PWREN# pin Adjustable RX buffer timeout In-built support for event characters Integrated level converter on FIFO and control signals for interfacing to 5V and 3.3V logic Integrated 3.3V regulator for USB IO Integrated Power-On-Reset circuit Integrated 6MHz – 48Mhz clock multiplier PLL USB Bulk or Isochronous data transfer modes New Bit-Bang Mode allows the data bus to be used as an 8 bit general purpose IO Port without the need for MCU or other support logic. • • • 4.35V to 5.25V single supply operation UHCI / OHCI / EHCI host controller compatible USB 1.1 and USB 2.0 compatible Features • • • USB VID, PID , Serial Number and Product Description strings in external EEPROM EEPROM programmable on-board via USB Compact Lead free RoHS compliant 32-LD LQFP package VIRTUAL COM PORT (VCP) DRIVERS for Windows 98 and Windows 98 SE Windows 2000 / ME / Server 2003 / XP Windows XP 64 Bit Windows XP Embedded Windows CE 4.2 MAC OS-8 and OS-9 MAC OS-X Linux 2.40 and greater Windows 98 and Windows 98 SE Windows 2000 / ME / Server 2003 / XP Windows XP 64 Bit Windows XP Embedded Windows CE 4.2 Linux 2.4 and Greater Easy MCU / PLD / FPGA interface to USB Upgrading Legacy Peripheral Designs to USB USB Instrumentation USB Industrial Control USB Audio and Low Bandwidth Video data transfer PDA  USB data transfer USB MP3 Player Interface USB FLASH Card Reader / Writers Set Top Box (S.T.B.) PC - USB interface USB Digital Camera Interface USB Hardware Modems USB Wireless Modems D2XX (USB Direct Drivers + DLL S/W Interface) APPLICATION AREAS DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 1 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. 1.1 General Description The FT245BL provides an easy cost-effective method of transferring data to / from a peripheral and a host P.C. at up to 8 Million bits (1 Megabyte) per second. Its simple, FIFO-like design makes it easy to interface to any microcontroller or microprocessor via IO ports. To send data from the peripheral to the host computer, simply write the byte-wide data into the module when TXE# is low. If the (384-byte) transmit buffer fills up or is busy storing the previously written byte, the device keeps TXE# high in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host. TXE# goes high after every byte written. When the host sends data to the peripheral over USB, the device will take RXF# low to let the peripheral know that at least one byte of data is available. The peripheral can read a data byte every time RXF# goes low. RXF# goes high after every byte read. By using FTDI’s virtual COM port drivers, the peripheral looks like a standard COM port to the application software. Commands to set the baud rate are ignored - the device always transfers data at its fastest rate regardless of the application’s baud-rate setting. Alternatively, FTDI’s D2XX drivers allow application software to access the device “directly” through a published DLL based API. Details of the current VCP and D2XX driver can be found on FTDI’s web site ( http://www.ftdichip.com ) 2.0 Enhancements This section summarises the enhancements of the 2nd generation device compared to its FT8U245AM predecessor. For further details, consult the device pin-out description and functional descriptions. • Integrated Power-On-Reset (POR) Circuit The device now incorporates an internal POR function. The existing RESET# pin is maintained in order to allow external logic to reset the device where required, however for many applications this pin can now be either left N/C or hard wired to VCC. In addition, a new reset output pin (RSTOUT#) is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices. RSTOUT# was the TEST pin on the previous generation of devices. • • Integrated RCCLK Circuit In the previous devices, an external RC circuit was required to ensure that the oscillator and clock multiplier PLL frequency was stable prior to enabling the clock internal to the device. This circuit is now embedded on-chip – the pin assigned to this function is now designated as the TEST pin and should be tied to GND for normal operation. Power Management control for USB Bus Powered, high current devices A new PWREN# signal is provided which can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. A new EEPROM based option makes the device pull gently down its FIFO interface lines when the power is shut off (PWREN# is High). In this mode, any residual • Integrated Level Converter on FIFO interface and control signals The previous devices would drive the FIFO and control signals at 5V CMOS logic levels. The new device has a separate VCCIO pin allowing the device to directly interface to 3.3V and other logic families without the need for external level converter I.C.’s DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 2 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. voltage on external circuitry is bled to GND when power is removed thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. PWREN# can also be used by external circuitry to determine when USB is in suspend mode (PWREN# goes high). • • Send Immediate / WakeUp (SI / WU) signal The new Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (and remote wakeup is enabled in the EEPROM), strobing this pin low will cause the device to request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the packet size. This can be used to optimise USB transfer speed for some applications. • Lower Suspend Current Integration of RCCLK within the device and internal design improvements reduce the suspend current of the FT245BL to under 100uA typical (excluding the 1.5K pull-up on USBDP) in USB suspend mode. This allows greater margin for peripherals to meet the USB Suspend current limit of 500uA. • Support for USB Isochronous Transfers Whilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the new device now offers an option of USB Isochronous transfer via an option bit in the EEPROM. • Programmable FIFO TX Buffer Timeout In the previous device, the TX buffer timeout used to flush remaining data from the TX buffer • Bit Bang Mode The 2nd generation device has a new option referred to as “Bit Bang” mode. In Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the prescaler of the FT232BL device). As well as allowing the device to be used stand-alone as a general purpose IO controller for example controlling lights, relays and switches, some other interesting possibilities exist. For instance, it may be possible to connect the device to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use Bit Bang Mode to download configuration data to the FPGA which would define its hardware function, then after the FPGA device is configured the FT245BL can switch back into FIFO interface mode to allow the programmed FPGA device to communicate with the PC over USB. This approach allows a customer to create a “generic” USB peripheral who’s hardware function can be defined under control of the application software. Relaxed VCC Decoupling The 2nd generation devices now incorporate a level of on-chip VCC decoupling. Though this does not eliminate the need for external decoupling capacitors, it significantly improves the ease of PCB design requirements to meet FCC, CE and other EMI related specifications. was fixed at 16ms timeout. This timeout is now programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets. DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 3 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. The FPGA based hardware can be easily upgraded or totally changed simply by changing the FPGA configuration data file. Application notes, software and development modules for this application area will be available from FTDI and other 3 party rd • Multiple Device Support without EEPROM When no EEPROM (or a blank or invalid EEPROM) is attached to the device, the FT245BL no longer gives a serial number as part of its USB descriptor. This allows multiple devices to be simultaneously connected to the same PC. However, we still highly recommend that EEPROM is used, as without serial numbers a device can only be identified by which hub port in the USB tree it is connected to which can change if the end user re-plugs the device into a different USB port. developers. • Less External Support Components As well as eliminating the RCCLK RC network, and for most applications the need for an external reset circuit, we have also eliminated the requirement for a 100K pull-up on EECS to select 6MHz operation. When the FT245BL is being used without the configuration EEPROM, EECS, EESK and EEDATA can now be left n/c. For circuits requiring a long reset time (where the device is reset externally using a reset generator I.C., or reset is controlled by the IO port of a MCU, FPGA or ASIC device) an external transistor circuit is no longer required as the 1.5K pull-up resistor on USBDP can be wired to the RSTOUT# pin instead of to 3.3V. Note : RSTOUT# drives out at 3.3V level, not at 5V VCC level. This is the preferred configuration for new designs. • Extended EEPROM Support The previous generation of devices only supported EEPROM of type 93C46 (64 x 16 bit). The new devices will also work with EEPROM type 93C56 (128 x 16 bit) and 93C66 (256 x 16 bit). The extra space is not used by the device, however it is available for use by other external MCU / logic whilst the FT245BL is being held in reset. • USB 2.0 ( full speed option ) A new EEPROM based option allows the FT245BL to return a USB 2.0 device descriptor as opposed to USB 1.1. Note : The device would be a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). • EEREQ# / EEGNT# These (FT8U245AM) pins are no longer supported on the FT245BL device. They have been replaced with the new SI / WU and PWREN# signals respectively. DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 4 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. 3.0 Block Diagram ( simplified ) VCC Send Immediate / WakeUP PWREN# 3V3OUT 3.3 Volt LDO Regulator FIFO Receive Buffer 128 Bytes USBDP USBDM USB Transceiver Serial Interface Engine ( SIE ) USB Protocol Engine FIFO Controller D0 D1 D2 D3 D4 D5 D6 D7 RD# WR RXF# TXE# USB DPLL FIFO Transmit Buffer 384 Bytes XTOUT 3V3OUT 48MHz XTIN GND TEST 6MHZ Oscillator x8 Clock Multiplier 12MHz RESET# RESET GENERATOR EEPROM Interface EECS EESK EEDATA RSTOUT# 3.1 • 3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power from the 3V3OUT pin if required. USB Transceiver The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. Functional Block Descriptions • USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block. 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz crystal or ceramic resonator. x8 Clock Multiplier The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for the SIE, USB Protocol Engine and FIFO controller blocks. It also generates a 48MHz reference clock for the USB DPLL. • • • DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 5 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. • Serial Interface Engine (SIE) The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / unstuffing and CRC5 / CRC16 generation / checking on the USB data stream. • • USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO. FIFO Receive Buffer (128 bytes) Data sent from the USB Host to the FIFO via the USB data out endpoint is stored in the FIFO Receive Buffer and is removed from the buffer by reading the FIFO contents using RD#. FIFO Transmit Buffer (384 bytes) Data written into the FIFO using WR# is stored in the FIFO Transmit Buffer. The Host removes Data from the FIFO Transmit Data by sending a USB request for data from the device data in endpoint. FIFO Controller The FIFO Controller handles the transfer of data between the external FIFO interface pins and the FIFO Transmit and Receive buffers. RESET Generator The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT245BL, or the FT245BL to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1.5K pull-up on USBDP directly where delayed USB enumeration is required. RSTOUT# will be low for approximately 5ms after VCC has risen above 3.5V AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device from external logic or an external reset generator I.C. EEPROM Interface Though the FT245BL will work without the optional EEPROM, an external 93C46 (93C56 or 93C66) EEPROM can be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT245BL for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The EEPROM should be a 16 bit wide configuration such as a MicroChip 93LC46B or equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility available from FTDI’s web site ( http://www.ftdichip.com ). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT245BL will use its built-in default VID, PID Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. • • • • DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 6 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. 4.0 Device Pin-Out Figure 1 Pin-Out (Lead free LQFP-32 Package ) EECS TEST AVCC AGND XTOUT X T IN VCC D0 Figure 2 Pin-Out (Schematic Symbol ) 30 3 26 32 EESK EEDATA VCC RESET# RSTO# 3V3OUT USBDP USBDM 8 9 1 25 24 D1 D2 D3 D4 D5 D6 D7 17 16 GND 6 A V V 3V3OUT C USBDM V C C V C C V C C I O 13 D0 D1 D2 D3 25 24 FTDI FT245BL XXYY 8 23 22 7 USBDP D4 D5 21 20 5 4 27 RSTOUT# RESET# XTIN D6 D7 19 18 RD# WR 16 15 28 PW REN# V C C IO SI / W U GND RXF# TXE# RD# WR 32 XTOUT EECS EESK EEDATA TEST A G N D 29 TXE# RXF# SI / WU PWREN# G N D 9 G N D 17 14 12 1 2 31 11 10 DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 7 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. 4.1 Signal Descriptions Table 1 - FT245BL - PINOUT DESCRIPTION FIFO DATA BUS GROUP (*** Note 1) Pin# 25 24 23 22 21 20 19 18 Signal DO D1 D2 D3 D4 D5 D6 D7 Type I/O I/O I/O I/O I/O I/O I/O I/O Description FIFO Data Bus Bit 0 FIFO Data Bus Bit 1 FIFO Data Bus Bit 2 FIFO Data Bus Bit 3 FIFO Data Bus Bit 4 FIFO Data Bus Bit 5 FIFO Data Bus Bit 6 FIFO Data Bus Bit 7 FIFO CONTROL INTERFACE GROUP Pin# 16 Signal RD# Type IN Description Enables Current FIFO Data Byte on D0..D7 when low. Fetches the next FIFO Data Byte (if available) from the Receive FIFO Buffer when RD# goes from low to high. *** Note 1 Writes the Data Byte on the D0..D7 into the Transmit FIFO Buffer when WR goes from high to low. *** Note 1 When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high then low. *** Note 2 When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low then high again *** Note 2 15 14 12 WR TXE# RXF# IN OUT OUT USB INTERFACE GROUP Pin# 7 8 Signal USBDP USBDM Type I/O I/O Description USB Data Signal Plus (Requires 1.5K pull-up to 3V3OUT or RSTOUT#) USB Data Signal Minus EEPROM INTERFACE GROUP Pin# 32 1 Signal EECS EESK Type I/O OUT Description EEPROM – Chip Select. For 48MHz operation pull EECS to GND using a 10K resistor. For 6MHz operation no resistor is required. *** Note 3 Clock signal to EEPROM. Adding a 10K pull down resistor onto EESK will cause the FT245BL to use USB Product ID 6005 (hex) instead of 6001 (hex). All of the other USB device descriptors are unchanged. *** Note 3 EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2.2K resistor. Also pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. *** Note 3 2 EEDATA I/O DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 8 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. POWER CONTROL GROUP Pin# 10 Signal PWREN# Type OUT Description Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM , strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation (PWREN# = 0), if this pin is strobed low any data in the device TX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimise USB transfer speed for some applications. Tie this pin to VCCIO if not used. 11 SI / WU IN MISCELLANEOUS SIGNAL GROUP Pin# 4 5 Signal RESET# RSTOUT# Type IN OUT Description Can be used by an external device to reset the FT245BL. If not required, tie to VCC. Output of the internal Reset Generator. Stays high impedance for ~ 5ms after VCC > 3.5V and the internal clock starts up, then clamps its output to the 3.3V output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset. Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external 6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if driving from an external source, the source must be driving at 5V CMOS level or a.c. coupled to centre around VCC/2. Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. Puts device in I.C. test mode – must be tied to GND for normal operation. 27 XTIN IN 28 31 XTOUT TEST OUT IN DS245BL Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 9 of 24 FT245BL USB FIFO ( USB - Parallel ) I.C. POWER AND GND GROUP Pin# 6 Signal 3V3OUT Type OUT Description 3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled to GND using a 33nF ceramic capacitor in close proximity to the device pin. Its prime purpose is to provide the internal 3.3V supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current (