UM245R

™ Future Technology Devices International Ltd. UM245R USB-Parallel FIFO Development Module Incorporating FTDIChip-ID™ Security Dongle The UM245R is a development module which uses FTDI’s FT245RL, the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. The FT245R is a USB to parallel FIFO interface, with the new FTDIChip-ID™ security dongle feature. In addition, asynchronous and synchronous bit bang interface modes are available. USB to parallel designs using the FT245R have been further simplified by fully integrating the external EEPROM, clock circuit and USB resistors onto the device. The FT245R adds a new function compared with its predecessors, effectively making it a “2-in-1” chip for some application areas. A unique number (the FTDIChip-ID™) is burnt into the device during manufacture and is readable over USB, thus forming the basis of a security dongle which can be used to protect customer application software from being copied. The UM245R is supplied on a PCB which is designed to plug into a standard 15.0mm (0.6”) wide 24 pin DIP socket. All components used, including the FT232RL are Pb-free (RoHS compliant). Copyright © Future Technology Devices International Ltd. 2005 1. Features 1.1 Hardware Features • • • • • • • • • • Single chip USB to parallel FIFO bidirectional data transfer interface. Entire USB protocol handled on the chip - No USB-specific firmware programming required. Simple interface to MCU / PLD / FPGA logic with simple 4-wire handshake interface. Data transfer rate to 1 Megabyte / second - D2XX Direct Drivers. Data transfer rate to 300 kilobyte / second - VCP Drivers. FTDI’s royalty-free VCP and D2XX drivers eliminate the requirement for USB driver development in most cases. New USB FTDIChip-ID™ feature. FIFO receive and transmit buffers for high data throughput. Adjustable receive buffer timeout. Synchronous and asynchronous bit bang mode interface options with RD# and WR# strobes allow the data bus to be used as a general purpose I/O port. Integrated 1024 bit internal EEPROM for storing USB VID, PID, serial number and product description strings. Device supplied preprogrammed with unique USB serial number. Support for USB suspend / resume through PWREN# pin and Wake Up pin function. In-built support for event characters. • • • • • • • • • • • • • • • • • • Page 2 • • • • Support for bus powered, self powered, and highpower bus powered USB configurations. Integrated 3.3V level converter for USB I/O. Integrated level converter on FIFO interface and control pins for interfacing to 5V - 1.8V Logic. True 5V / 3.3V / 2.8V / 1.8V CMOS drive output and TTL input. High I/O pin output drive option. Integrated USB resistors. Integrated power-on-reset circuit. Fully integrated clock - no external crystal, oscillator, or resonator required. Fully integrated AVCC supply filtering - No separate AVCC pin and no external R-C filter required. USB bulk transfer mode. 3.3V to 5.25V Single Supply Operation. Low operating and USB suspend current. Low USB bandwidth consumption. UHCI / OHCI / EHCI host controller compatible USB 2.0 Full Speed compatible. -40°C to 85°C extended operating temperature range. Supplied in PCB designed to fit a standard 15.0mm (0.6”) wide 24 pin DIP socket. Pins are on a 26.0mm (0.1”) pitch. On board USB ‘B’ socket allows module to be connected to a PC via a standard A to B USB cable. Royalty-Free VIRTUAL COM PORT (VCP) DRIVERS for... • Windows 98, 98SE, ME, 2000, Server 2003, XP. • Windows Vista / Longhorn* • Windows XP 64-bit.* • Windows XP Embedded. • Windows CE.NET 4.2 & 5.0 • MAC OS 8 / 9, OS-X • Linux 2.4 and greater 1.2 Driver Support Royalty-Free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) • Windows 98, 98SE, ME, 2000, Server 2003, XP. • Windows Vista / Longhorn* • Windows XP 64-bit.* • Windows XP Embedded. • Windows CE.NET 4.2 & 5.0 • Linux 2.4 and greater The drivers listed above are all available to download for free from the FTDI website. Various 3rd Party Drivers are also available for various other operating systems - see the FTDI website for details. * Currently Under Development. Contact FTDI for availability. • • • • • • • • Upgrading Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer cables and interfaces Interfacing MCU / PLD / FPGA based designs to USB USB Audio and Low Bandwidth Video data transfer PDA to USB data transfer USB Smart Card Readers USB Instrumentation USB Industrial Control 1.3 Typical Applications • • • • • • • • USB MP3 Player Interface USB FLASH Card Reader / Writers Set Top Box PC - USB interface USB Digital Camera Interface USB Hardware Modems USB Wireless Modems USB Bar Code Readers USB Software / Hardware Encryption Dongles UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 2. FT232RL Features and Enhancements 2.1 Key Features Page 3 This section summarises the key features and enhancements of the FT245R IC device which is used in the UM245R Module. For further details, consult the FT245R datasheet, which is available from the FTDI website. Integrated Clock Circuit - Previous generations of FTDI’s USB to parallel FIFO interface devices required an external crystal or ceramic resonator. The clock circuit has now been integrated onto the device meaning that no crystal or ceramic resonator is required. However, if required, an external 12MHz crystal can be used as the clock source. Integrated EEPROM - Previous generations of FTDI’s USB to parallel FIFO interface devices required an external EEPROM if the device were to use USB Vendor ID (VID), Product ID (PID), serial number and product description strings other than the default values in the device itself. This external EEPROM has now been integrated onto the FT245R chip meaning that all designs have the option to change the product description strings. A user area of the internal EEPROM is available for storing additional data. The internal EEPROM is programmable in circuit, over USB without any additional voltage requirement. Preprogrammed EEPROM - The FT245R is supplied with its internal EEPROM preprogrammed with a serial number which is unique to each individual device. This, in most cases, will remove the need to program the device EEPROM. Integrated USB Resistors - Previous generations of FTDI’s USB to parallel FIFO interface devices required two external series resistors on the USBDP and USBDM lines, and a 1.5 kΩ pull up resistor on USBDP. These three resistors have now been integrated onto the device. Integrated AVCC Filtering - Previous generations of FTDI’s USB to parallel FIFO interface devices had a separate AVCC pin - the supply to the internal PLL. This pin required an external R-C filter. The separate AVCC pin is now connected internally to VCC, and the filter has now been integrated onto the chip. Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC filter will substantially reduce the bill of materials cost for USB interface designs using the FT245R compared to its FT245BM predecessor. Enhanced Asynchronous Bit Bang Mode with RD# and WR# Strobes - The FT245R supports FTDI’s BM chip bit bang mode. In bit bang mode, the eight parallel FIFO data bus lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT245R device this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the bit bang I/O bus. This option will be described more fully in a separate application note Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. Thus making it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. The feature was previously seen in FTDI’s FT2232C device. This option will be described more fully in a separate application note. Lower Supply Voltage - Previous generations of the chip required 5V supply on the VCC pin. The FT245R will work with a Vcc supply in the range 3.3V - 5V. Bus powered designs would still take their supply from the 5V on the USB bus, but for self powered designs where only 3.3V is available, and there is no 5V supply, there is no longer any need for an additional external regulator. Integrated Level Converter on FIFO Interface and Control Signals - VCCIO pin supply can be from 1.8V to 5V. Connecting the VCCIO pin to 1.8V, 2.8V, or 3.3V allows the device to directly interface to 1.8V, 2.8V or 3.3V and other logic families without the need for external level converter I.C.s 5V / 3.3V / 2.8V / 1.8V Logic Interface - The FT245R provides true CMOS Drive Outputs and TTL level Inputs. Integrated Power-On-Reset (POR) Circuit- The device incorporates an internal POR function. A RESET# pin is available in order to allow external logic to reset the FT245R where required. However, for many applications the RESET# pin can be left unconnected, or pulled up to VCCIO. UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 Page 4 Wake Up Function - If USB is in suspend mode, and remote wake up has been enabled in the internal EEPROM (it is enabled by default), the RXF# pin becomes an input. Strobing this pin low will cause the FT245R to request a resume from suspend on the USB bus. Normally this can be used to wake up the host PC from suspend Lower Operating and Suspend Current - The device operating supply current has been further reduced to 15mA, and the suspend current has been reduced to around 70μA. This allows a greater margin for peripherals to meet the USB suspend current limit of 500μA. Low USB Bandwidth Consumption - The operation of the USB interface to the FT245R has been designed to use as little as possible of the total USB bandwidth available from the USB host controller. High Output Drive Option - The parallel FIFO interface and the four FIFO handshake pins can be made to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive strength to be interfaced to the FT245R. This option is configured in the internal EEPROM. Power Management Control for USB Bus Powered, High Current Designs- The PWREN# signal can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. An option in the internal EEPROM makes the device gently pull down on its FIFO interface lines when the power is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. FTDIChip-ID™ - Each FT245R is assigned a unique number which is burnt into the device at manufacture. This ID number cannot be reprogrammed by product manufacturers or end-users. This allows the possibility of using FT245R based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area of the FT245R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note describing this feature is available separately from the FTDI website. Improved EMI Performance - The reduced operating current and improved on-chip VCC decoupling significantly improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related specifications. Programmable FIFO TX Buffer Timeout - The FIFO TX buffer timeout is used to flush remaining data from the receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be optimised for protocols that require fast response times from short data packets. Extended Operating Temperature Range - The FT232R operates over an extended temperature range of -40º to +85º C thus allowing the device to be used in automotive and industrial applications. New Package Options - The FT245R is available in two packages - a compact 28 pin SSOP ( FT245RL) and an ultra-compact 5mm x 5mm pinless QFN-32 package ( FT245RQ). Both packages are lead ( Pb ) free, and use a ‘green’ compound. Both packages are fully compliant with European Union directive 2002/95/EC. Figure 1 - UM245R Module UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 3. UM245R Pin Out and Signal Descriptions 3.1 UM245R Pin Out Page 5 DB0 1 DB4 DB2 VIO DB1 DB7 GND DB5 DB6 DB3 PWE# RD# 12 J1 123 24 J2 21 13 GND RXF# TXE# VCC RST# 3V 3 WR# PU1 PU2 VCC USB SLD Figure 2 - Module Pin Out and Jumper Locations UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 FTDI © Future Technology Devices International Ltd. 2005 3.2 UM245R Signal Descriptions Table 1 - Module Pin Out Description Pin No. Name 1 2 3 4 DB0 DB4 DB2 VIO Page 6 Type I/O I/O I/O PWR Description FIFO Data Bus Bit 0* FIFO Data Bus Bit 4* FIFO Data Bus Bit 2* +1.8V to +5.25V supply to the FIFO Interface and Control group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect to 3V3OUT to drive out at 3.3V levels (connect jumper J1 pins 1 and 2 together), or connect to VCC to drive out at 5V CMOS level (connect jumper J1 pins 2 and 3 together). This pin can also be supplied with an external 1.8V - 2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to Vcc. This means that in bus powered designs a regulator which is supplied by the 5V on the USB bus should be used. FIFO Data Bus Bit 1* FIFO Data Bus Bit 7* Module ground supply pins FIFO Data Bus Bit 5* FIFO Data Bus Bit 6* FIFO Data Bus Bit 3* Goes low after the device is configured by USB, then high during USB suspend. Can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# pin in this way. Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO data byte (if available) from the receive FIFO buffer when RD# goes from high to low. See Section 3.4 for timing diagram.* USB Cable shield. 5V Power output USB port. For a low power USB bus powered design, up to 100mA can be sourced from the 5V supply on the USB bus. A maximum of 500mA can be sourced from the USB bus in a high power USB bus powered design. These two pins are internally connected on the module pcb. To power the module from the 5V supply on USB bus connect jumper J2 pins 1 and 2 together (this is the module default configuration). In this case these pins would have the same description as pin 14. To use the UM245R module in a self powered configuration ensure that jumper J2 pins 1 and 2 are not connected together, and apply an external 3.3V to 5.25V supply to one or both of these pins. Pull up resistor pin connection 2. Conect to pin 17 (RST#) in a self powered configuration. Pull up resistor pin connection 1. Connect to pin 14 (USB) in a self powered configuration. 3.3V output from integrated L.D.O. regulator. This pin is decoupled to ground on the module pcb with a 10nF capacitor. The prime purpose of this pin is to provide the internal 3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the FT245RL’s VCCIO pin by connecting this pin to pin 4 (VIO), or by connecting together pins 1 and 2 on jumper J1. Can be used by an external device to reset the FT245R. If not required can be left unconnected, or pulled up to VCCIO. Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low. See Section 3.4 for timing diagram.* When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high, then low. During reset this signal pin is tri-state, but pulled up to VCCIO via an internal 200kΩ resistor. See Section 3.4 for timing diagram. When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low, then high again. During reset this signal pin is tri-state, but pulled up to VCCIO via an internal 200kΩ resistor. See Section 3.4 for timing diagram. If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode (PWREN# = 1) RXF# becomes an input which can be used to wake up the USB host from suspend mode. Strobing the pin low will cause the device to request a resume on the USB bus. 5 6 7, 24 8 9 10 11 DB5 DB7 GND DB5 DB6 DB3 PWE# I/O I/O PWR I/O I/O I/O I/O 12 13 14 RD# SLD USB I/O GND Output 15, 21 VCC PWR or Output 16 17 19 PU2 PU1 3V3 Control Control Output 20 18 22 RST# WR TXE# Input I/O I/O 23 RXF# I/O * When used in Input Mode, these pins are pulled to VCCIO via internal 200kΩ resistors. These can be programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the internal EEPROM. UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 Page 7 3.3 Jumper Configuration Options Table 2 - Jumper J1 Pin Description Pin No. Name 1 3V3 Type Output Description 3.3V output from integrated L.D.O. regulator. This pin is decoupled to ground on the module pcb with a 10nF capacitor. The prime purpose of this pin is to provide the internal 3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the FT245RL’s VCCIO pin by connecting this pin to pin 4 (VIO), or by connecting together pins 1 and 2 on jumper J1. +1.8V to +5.25V supply to the FIFO Interface and control pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect to 3V3 to drive out at 3.3V levels (connect jumper J1 pins 1 and 2 together), or connect to VCC to drive out at 5V CMOS level (connect jumper J1 pins 2 and 3 together). This pin can also be supplied with an external 1.8V - 2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to Vcc. This means that in bus powered designs a regulator which is supplied by the 5V on the USB bus should be used. VCC Output. This will be 5V from the USB bus if pins 1 and 2 on jumper J2 are connected. Alternativly, if the module is in a self powered configuration, the supply to the VCC module pins (15 and 21) will be brought out to this jumper pin. Connect this jumper J1 pin 2 in order to supply the device IO pins from the supply to VCCIO. 2 VIO PWR 3 VCC PWR Table 3 - Jumper J2 Pin Description Pin No. Name 1 USB Type PWR Description 5V Power output USB port. For a low power USB bus powered design, up to 100mA can be sourced from the 5V supply on the USB bus. A maximum of 500mA can be sourced from the USB bus in a high power USB bus powered design. Board supply input. Connect to jumper J2 pin 1 in order to supply the board from the USB bus. This pin is internally connected to the VCC DIP pins. Remove the jumper connector in a self powered design. 2 VCC PWR or Output UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 3.4 FT245R FIFO Control Interface Timing Diagrams Figure 3 - FIFO Read Cycle Page 8 T6 RXF# T5 RD# T3 T1 T2 T4 Valid Data D[7...0] Table 4 - FIFO Read Cycle Timings Time T1 T2 T3 T4 T5 T6 Description RD Active Pulse Width RD to RD Pre-Charge Time RD Active to Valid Data* Valid Data Hold Time from RD Inactive* RD Inactive to RXF# RXF Inactive After RD Cycle Min 50 50 + T6 20 0 0 80 Max Unit ns ns 50 25 ns ns ns ns * Load = 30pF Figure 4 - FIFO Write Cycle T11 T12 TXE# T7 T8 WR D[7...0] Table 5 - FIFO Write Cycle Timings Time T7 T8 T9 T10 T11 T12 T9 Valid Data T10 Description WR Active Pulse Width WR to RD Pre-Charge Time Data Setup Time before WR Inactive Data Hold Time from WR Inactive WR Inactive to TXE# TXE Inactive After WR Cycle Min 50 50 20 0 5 80 Max Unit ns ns ns ns 25 ns ns UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 4. UM245R Module Dimensions Figure 4 - UM245R Module Dimensions Page 9 I 7.50mm (0.30") 5.50mm (0.22") 21.30mm (0.85") 33.00mm (1.50") 10.50mm (0.42") 5.80mm (0.23") 5.0mm (0.2") 12.50mm (0.50") 15.00mm (0.60") All dimensions are shown in millimeters with inches shown in parenthesis. The FT245RL IC device used by the UM245R is supplied in a RoHS compliant 28 pin SSOP package. The package is lead ( Pb ) free and uses a ‘green’ compound. The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. The UM245R module uses exclusivly lead free components. Both the I.C. device and the module are fully compliant with European Union directive 2002/95/EC. UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 FT D 2.54mm (0.10") Diameter 0.50mm (0.02") 15.00mm (0.60") 12.00mm (0.48") 2.54mm (0.10") 18.10mm (0.72") 1.60mm (0.06") © Future Technology Devices International Ltd. 2005 Page 10 5. Device Characteristics and Ratings 5.1 Absolute Maximum Ratings The absolute maximum ratings for the FT245R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Table 6 - Absolute Maximum Ratings Parameter Storage Temperature Floor Life (Out of Bag) At Factory Ambient ( 30°C / 60% Relative Humidity) Ambient Temperature (Power Applied) Vcc Supply Voltage D.C. Input Voltage - USBDP and USBDM D.C. Input Voltage - High Impedance Bidirectionals D.C. Input Voltage - All other Inputs D.C. Output Current - Outputs DC Output Current - Low Impedance Bidirectionals Power Dissipation (Vcc = 5.25V) Value -65°C to 150°C 168 Hours (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* -40°C to 85°C -0.5 to +6.00 -0.5 to +3.8 -0.5 to +(Vcc +0.5) -0.5 to +(Vcc +0.5) 24 24 500 Unit Degrees C Hours Degrees C. V V V V mA mA mW * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of 125°C and baked for up to 17 hours. 5.2 DC Characteristics DC Characteristics ( Ambient Temperature = -40 to 85oC ) Table 7 - Operating Voltage and Current Parameter Vcc1 Vcc2 Icc1 Icc2 Description VCC Operating Supply Voltage VCCIO Operating Supply Voltage Operating Supply Current Operating Supply Current Min 3.3 1.8 50 Typ 15 70 Max 5.25 5.25 100 Units V V mA Conditions Normal Operation USB Suspend* μA Table 8 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 3.2 0.3 1.3 50 Typ 4.1 0.4 1.6 55 Max 4.9 0.6 1.9 60 Units V V V mV Conditions I source = 2mA I sink = 2mA ** ** Table 9 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 3.3V, Standard Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 2.2 0.3 1.0 20 Typ 2.7 0.4 1.2 25 Max 3.2 0.5 1.5 30 Units V V V mV Conditions I source = 1mA I sink = 2mA ** ** UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 Page 11 Table 10 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 2.8V, Standard Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 2.1 0.3 1.0 20 Typ 2.6 0.4 1.2 25 Max 3.1 0.5 1.5 30 Units V V V mV Conditions I source = 1mA I sink = 2 mA ** ** Table 11 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 5.0V, High Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 3.2 0.3 1.3 50 Typ 4.1 0.4 1.6 55 Max 4.9 0.6 1.9 60 Units V V V mV Conditions I source = 6mA I sink = 6mA ** ** Table 12 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 3.3V, High Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 2.2 0.3 1.0 20 Typ 2.8 0.4 1.2 25 Max 3.2 0.6 1.5 30 Units V V V mV Conditions I source = 3mA I sink = 8mA ** ** Table 13 - FIFO Interface and Control Bus Pin Characteristics (VCCIO = 2.8V, High Drive Level) Parameter Voh Vol Vin VHys Description Output Voltage High Output Voltage Low Input Switching Threshold Input Switching Hysteresis Min 2.1 0.3 1.0 20 Typ 2.8 0.4 1.2 25 Max 3.2 0.6 1.5 30 Units V V V mV Conditions I source = 3mA I sink = 8mA ** ** **Inputs have an internal 200kΩ pull-up resistor to VCCIO. Table 14 - RESET#, TEST Pin Characteristics Parameter Vin VHys Description Input Switching Threshold Input Switching Hysteresis Min 1.3 50 Typ 1.6 55 Max 1.9 60 Units V mV Conditions Table 15 - USB I/O Pin (USBDP, USBDM) Characteristics Parameter UVoh UVol UVse UCom UVDif UDrvZ Description I/O Pins Static Output ( High) I/O Pins Static Output ( Low ) Single Ended Rx Threshold Differential Common Mode Differential Input Sensitivity Driver Output Impedance Min 2.8 0 0.8 0.8 0.2 26 Typ Max 3.6 0.3 2.0 2.5 Units V V V V V Conditions RI = 1.5kΩ to 3V3OUT ( D+ ) RI = 15kΩ to GND ( D- ) RI = 1.5kΩ to 3V3OUT ( D+ ) RI = 15kΩ to GND ( D- ) 29 44 Ohms *** ***Driver Output Impedance includes the internal USB series resistors on USBDP and USBDM pins. UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 5.3 EEPROM Reliability Characteristics The internal 1024 bit EEPROM has the following reliability characteristicsTable 16 - EEPROM Characteristics Parameter Description Data Retention Read / Write Cycles Page 12 Value 15 100,000 Unit Years Cycles 5.4 Internal Clock Characteristics The internal Clock Oscillator has the following characteristics. Table 17 - Internal Clock Characteristics Parameter Min Frequency of Operation Clock Period Duty Cycle 11.98 83.19 45 Value Typical 12.00 83.33 50 Unit Max 12.02 83.47 55 MHz ns % UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 6. Module Configurations 6.1 Bus Powered Configuration Page 13 1 J1 24 FTDI J2 12 13 Figure 5 - Bus Powered Configuration Figure 5 illustrates the UM245R in a typical USB bus powered design configuration. This can easily be done by fitting the jumper link on J2, as shown above. The UM245R is supplied in this configuration by default. A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows – i) ii) On plug-in to USB, the device must draw no more than 100mA. On USB Suspend the device must draw no more than 500μA. iii) A Bus Powered High Power USB Device (one that draws more than 100mA) should use the PWREN# pin to keep the current below 100mA on plug-in and 500μA on USB suspend. iv) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub. v) No device can draw more that 500mA from the USB Bus. Interfacing the UM245R module to a microcontroller (MCU), or other logic for a bus powered design would be done in exactly the same way as for a self powered design (see Section 6.2), except that the MCU would take its power supply from the USB bus (either the 5V on the USB pin, or the 3.3V on the 3V3 pin). UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 6.2 Self Powered Configuration Vcc = 3.3V – 5V Vcc = 3.3V – 5V Page 14 WR RD# TXE# RXF# MCU DB0 1 DB4 2 J1 24 GND 23 RXF# 22 TXE# DB2 3 DB1 5 DB7 6 GND 7 DB5 8 DB6 9 21 VCC 20 RST# 18 WR FTDI DB0 DB1 DB2 DB3 17 PU1 16 PU2 15 VCC DB4 DB5 DB6 DB7 DB3 10 PWE# 11 J2 14 USB RD# 12 13 USB B Connector Figure 6 Self Powered Configuration Figure 6 illustrates the UM245R in a typical USB self powered configuration. In this case the link on jumper J2 is removed, and an external supply is connected to the module VCC pins. Figure 6 illustrates a design which has a 3.3V - 5V supply. A USB Self Powered device gets its power from its own power supply and does not draw current from the USB bus. The basic rules for USB Self power devices are as follows – i) ii) A Self Powered device should not force current down the USB bus when the USB Host or Hub Controller is powered down. A Self Powered Device can use as much current as it likes during normal operation and USB suspend as it has its own power supply. iii) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs The power descriptor in the internal EEPROM should be programmed to a value of zero (self powered). In order to meet requirement (i) the USB Bus Power is used to control the RESET# Pin of the FT245R device. When the USB Host or Hub is powered up the internal 1.5kΩ resistor on USBDP is pulled up to 3.3V, thus identifying the device as a full speed device to USB. When the USB Host or Hub power is off, RESET# will go low and the device will be held in reset. As RESET# is low, the internal 1.5kΩ resistor will not be pulled up to 3.3V, so no current will be forced down USBDP via the 1.5kΩ pull-up resistor when the host or hub is powered down. To do this pin 14 (USB) is connected to PU2 and PU1 is connected to RST#. Failure to do this may cause some USB host or hub controllers to power up erratically. Note : When the FT245R is in reset, the FIFO interface and control pins all go tri-state. These pins have internal 200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. Figure 5 also illustrates interfacing the UM245R and a Microcontroller (MCU) FIFO interface. This example uses two MCU I/O ports: one port (8 bits) to transfer data, and the other port (4 or 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes to the FT245R, as required. Using PWE# for this function is optional. If the Remote Wakeup option is enabled in the internal EEPROM, during USB suspend mode RXF# becomes an input which can be used to wake up the USB host controller by strobing the pin low. UM245R USB-Parallel FIFO Development Module Datasheet Version 1.02 © Future Technology Devices International Ltd. 2005 6.3 USB Bus Powered with Power Switching Configuration Switched 5V Power to External Logic Page 15 P-Channel Power MOSFET s d 0.1 uF 0.1 uF WR RD# DB0 1 DB4 2 DB2 3 DB1 5 J1 24 GND g 23 RXF# 22 TXE# TXE# RXF# Soft 1k Start Circuit FTDI MCU DB0 DB1 DB7 6 GND 7 DB5 8 18 WR DB2 DB3 DB4 DB5 DB6 9 DB3 10 PWE# 11 RD# 12 DB6 DB7 J2 14 USB 13 USB B Connector Figure 7 - Bus Powered with Power Switching Configuration USB Bus powered circuits need to be able to power down in USB suspend mode in order to meet the