Future Technology Devices International Ltd.
V2DIP1-32
VNC2-32Q Development Module
Datasheet
Document Reference No.: FT_000163
Version 1.01
Issue Date: 2010-05-25
Future Technology Devices International Ltd (FTDI)
Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow, G41 1HH, United Kingdom
Tel.: +44 (0) 141 429 2777
Fax: + 44 (0) 141 429 2758
E-Mail (Support): support1@ftdichip.com
Web: http://www.vinculum.com
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are
supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in
which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,
Glasgow, G41 1HH, United Kingdom. Scotland Registered Number: SC136640
Copyright © 2010 Future Technology Devices International Limited
Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
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1
Introduction
V2DIP1-32 module is designed to allow rapid development of designs using the VNC2-32Q IC. The
V2DIP1-32 is supplied as a PCB designed to fit into a 24 pin 0.6” wide / 0.1” pitch DIP socket. The
module provides access to the UART, parallel FIFO and SPI interface pins of the VNC2-32Q device via its
IO bus pins. The USB port is accessed via a type A USB connector.
Figure 1.1 - V2DIP1-32
The VNC2 is the second of FTDI’s Vinculum family of Embedded dual USB host controller devices. The
VNC2 device provides USB Host interfacing capability for a variety of different USB device classes
including support for BOMS (bulk only mass storage), Printer, HID (human interface devices). For mass
storage devices such as USB Flash drives, VNC2 also transparently handles the FAT file structure.
Communication with non USB devices such as a low cost microcontroller is accomplished via either UART,
SPI or parallel FIFO interfaces. The VNC2 provides a new cost effective solution for providing USB Host
capability into products that previously did not have the hardware resources available.
The VNC2 supports the capability to enable customers to develop custom firmware using the Vinculum II
development software tool suite. The development tools support compiler, linker and debugger tools
complete within an integrated development environment (IDE).
The Vinculum-II VNC2 family of devices are available in Pb-free (RoHS compliant) 32-lead LQFP, 32-lead
QFN, 48-lead LQFP, 48-lead QFN, 64-Lead lQFP and 64-lead QFN packages.
Copyright © 2010 Future Technology Devices International Limited
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Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
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Table of Contents
1
Introduction .................................................................... 1
2
Features .......................................................................... 3
3
Pin Out and Signal Description ........................................ 4
3.1
Module Pin Out.......................................................................... 4
3.2
Pin Signal Description ............................................................... 6
3.3
Default Interface I/O Pin Configuration .................................... 7
3.4
UART Interface ......................................................................... 8
3.4.1
3.5
Serial Peripheral Interface (SPI) .............................................. 9
3.5.1
Signal Description - SPI Slave ..................................................................... 9
3.5.2
Signal Description - SPI Master ................................................................... 9
3.6
Parallel FIFO Interface - Asynchronous Mode ......................... 10
3.6.1
Signal Description - Parallel FIFO Interface ................................................. 10
3.6.2
Timing Diagram – Asynchronous FIFO Mode Read and Write Cycle................ 11
3.7
Debugger Interface ................................................................. 12
3.7.1
4
5
Signal Description – UART Interface ............................................................. 8
Signal Description - Debugger Interface ..................................................... 12
Firmware....................................................................... 13
4.1
Firmware Support ................................................................... 13
4.2
Available Firmware ................................................................. 13
4.3
Firmware Upgrades ................................................................. 13
External circuit Configuration ....................................... 14
5.1
Adding a second USB Port ....................................................... 14
6
Mechanical Dimensions ................................................. 15
7
Schematic Diagram ....................................................... 16
8
Contact Information ...................................................... 17
Appendix A – References ................................................................. 18
Appendix B – List of Figures and Tables .......................................... 19
List of Figures ................................................................................. 19
List of Tables ................................................................................... 19
Appendix C – Revision History ......................................................... 20
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Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
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2
Features
The V2DIP1-32 incorporates the following features:
Uses FTDI’s VNC2-32Q embedded USB host
controller IC device.
All VNC2 signals available on 0.6” wide / 0.1”
pitch DIL male connectors.
USB ‘A’ type USB socket to interface with USB
peripheral devices.
Power and traffic indicator LED’s.
Second USB interface port accessible via
module pins if required.
UART, parallel FIFO and SPI interfaces can be
programmed to a choice of available I/O pins.
Single 5V supply input from DIL connectors or
5V supplied via USB VBUS slave interface or
debugger module.
Auxiliary 3.3 V / 200 mA power output to
external logic.
V2DIP1-32 is a Pb-free, RoHS compliant
development module.
Debugger interface pin available on DIL pins or
via 6 way male header which interfaces to
separate debugger module.
Firmware upgrades via UART or debugger
interface pin header
FOC software development suite of tools to
create customised firmware includes a
Compiler, Linker,Debugger and Assembler all
wrapped up in an easy to use Integrated
Design Environment GUI.
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3
Pin Out and Signal Description
3.1 Module Pin Out
Figure 3.1 - V2DIP1-32 Module Pin Out (Top View)
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V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
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Figure 3.2 - V2DIP1-32 Module Pin Out (Bottom View)
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3.2 Pin Signal Description
Name
Pin No.
J1-1
Pin Name on
PCB
Type
5V0
5V0
PWR Input
-
-
-
-
-
-
J1-4
USBD1P
U1P
I/O
J1-5
USBD1M
U1M
I/O
J1-6
J2-7
J1-8
J1-9
J1-10
J1-11
J1-12
J2-1
IOBUS4
GND
IOBUS5
IOBUS6
IOBUS7
IOBUS8
IOBUS9
3V3
IO4
GND
IO5
IO6
IO7
IO8
IO9
3V3
I/O
PWR
I/O
I/O
I/O
I/O
I/O
3.3V Output from
VDIP2’s on board
3.3V L.D.O.
J2-2
PROG#
PRG#
Input
J2-3
RESET#
RST#
Input
-
-
-
-
-
-
IOBUS3
GND
IOBUS2
IOBUS1
IOBUS0
IOBUS11
IOBUS10
IO3
GND
IO2
IO1
IO0
IO11
IO10
I/O
PWR
I/O
I/O
I/O
I/O
I/O
J1-2
J1-3
J1-4
J1-5
J2-6
J1-7
J2-8
J2-9
J2-10
J2-11
J2-12
Description
5.0V module supply pin. This pin can be used to
provide the 5.0V input to the V2DIP1-32 when the
V2DIP1-32 is not powered from the USB connector
(VBUS) or the debugger interface. Also connected to
DIL connector pins pin J3-6.
Not connected
Not connected
USB host / slave port 1 - USBData Signal Plus with
integrated pull up / pull down resistor. Module has on
board 27 Ω USB series resistor. This pin can be
brought out along with pin J1-5 to provide a second
USBport, if required.
USB host / slave port 1 - USBData Signal Minus with
integrated pull up / pull down resistor. Module has on
board 27 Ω USB series resistor. This pin can be
brought out along with pin 5 to provide a second USB
port,if required.
5V safe bidirectional data / control bus bit 4
Module ground supply pin
5V safe bidirectional data / control bus bit 5
5V safe bidirectional data / control bus bit 6
5V safe bidirectional data / control bus bit 7
5V safe bidirectional data / control bus bit 8
5V safe bidirectional data / control bus bit 9
3.3V output from V2DIP1’s on board 3.3V L.D.O.
This pin is used in combination with the RESET# pin
and the UART interface to program firmware into the
VNC2.
Can be used by an external device to reset the VNC2.
This pin is also used in combination with PROG# and
the UART interface to program firmware into the
VNC2
Not connected
Not connected
5V safe bidirectional data /
Module ground supply pin
5V safe bidirectional data /
5V safe bidirectional data /
5V safe bidirectional data /
5V safe bidirectional data /
5V safe bidirectional data /
control bus bit 3
control
control
control
control
control
bus
bus
bus
bus
bus
bit
bit
bit
bit
bit
2
1
0
11
10
Table 3.1 - Pin Signal Descriptions
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3.3 Default Interface I/O Pin Configuration
The 32 pin QFN VNC2-32Q device is delivered without any firmware pre-loaded. As such the IOMUX will
provide a default pinout as shown in the following table:
Data and Control Bus Configuration
Options
Pin
No.
Pin
Name
on PCB
Type
J2-10
IO0
I/O
J1-6
IO4
I/O
J1-8
IO5
I/O
J1-9
IO6
I/O
J1-10
IO7
I/O
J1-11
IO8
I/O
J1-12
IO9
I/O
J2-12
IO10
I/O
J2-11
IO11
I/O
UART
Interface
SPI Slave
Interface
SPI
Master
Interface
Parallel
FIFO
Interface
Debugger
Interface
NA
NA
NA
NA
Debug_if
uart_txd
NA
NA
NA
NA
uart_rxd
NA
NA
NA
NA
uart_rts#
NA
NA
NA
NA
uart_cts#
NA
NA
NA
NA
NA
spi_s0_clk
NA
NA
NA
NA
spi_s0_mosi
NA
NA
NA
NA
spi_s0_miso
NA
NA
NA
NA
spi_s0_ss#
NA
NA
NA
Table 3.2 - Default Interface I/O Pin Configuration
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3.4 UART Interface
When the data and control buses are configured in UART mode, the interface implements a standard
asynchronous serial UART port with flow control. The UART can support baud rates from 300 baud to
3Mbaud. The UART interface is described more fully in the VNC2 datasheet please refer to:- FTDI website
3.4.1 Signal Description – UART Interface
The UART signals can be programmed to a choice of available I/O pins. Table 3.3 explains the available
pins for each of the UART signals.
Available Pins
Name
Type
J2-10, J1-6, J1-11
uart_txd
Output
J2-9, J1-8, J1-12
uart_rxd
Input
Receive asynchronous data input
J2-8, J1-9, J2-12
uart_rts#
Output
Request To Send Control Output
J2-6, J1-10, J2-11
uart_cts#
Input
J2-10, J1-6, J1-11
uart_dtr#
Output
J2-9, J1-8, J1-12
uart_dsr#
Input
Data Request (Data Set Ready
Control) Input
J2-8, J1-9, J2-12
uart_dcd#
Input
Data Carrier Detect Control Input
uart_ri#
Input
Ring Indicator Control Input. RI# low
can be used to resume the PC USB
Host controller from suspend.
Output
Enable Transmit Data for RS485
designs. TXDEN may be used to
signal that a transmit operation is in
progress. The TXDEN signal will be
set high one bit-time before data is
transmitted and return low one bit
time after the last bit of a data frame
has been transmitted
J2-6, J1-10, J2-11
J2-10, J1-6, J1-11
uart_tx_active
Description
Transmit asynchronous data output
Clear To Send Control Input
Data Acknowledge (Data Terminal
Ready Control) Output
Table 3.3 - Data and Control Bus Signal Mode Options – UART
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3.5 Serial Peripheral Interface (SPI)
The VNC2-32Q has one SPI master module and two SPI slave modules. These modules are described
more fully in a VNC2 datasheet please refer to:- FTDI website
3.5.1 Signal Description - SPI Slave
The SPI Slave signals can be programmed to a choice of available I/O pins. Table 3.4 explains the
available pins for each of the SPI Slave signals.
Name
Type
Description
spi_s0_clk
Input
Slave clock input
Input/Output
Master Out Slave In
Available Pins
J2-10, J1-6, J1-11
spi_s1_clk
spi_s0_mosi
J2-9, J1-8, J1-12
spi_s1_mosi
spi_s0_miso
J2-8, J1-9, J2-12
Synchronous data from master to
slave
Output
spi_s1_miso
spi_s0_ss#
J2-6, J1-10, J2-11
Master In Slave Out
Synchronous data from slave to
master
Input
Slave chip select
spi_s1_ss#
Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave
3.5.2 Signal Description - SPI Master
The SPI Master signals can be programmed to a choice of available I/O pins. Table 3.5 shows the SPI
master signals and the available pins that they can be mapped.
Available Pins
J2-10, J1-6, J1-11
Name
Type
Description
spi_m_clk
Output
SPI master clock input
spi_m_mosi
Output
Master Out Slave In
Synchronous data from master to
slave
J2-9, J1-8, J1-12
spi_m_miso
Input
Master In Slave Out
Synchronous data from slave to
master
J2-8, J1-9, J2-12
spi_m_ss_0#
Output
J2-6, J1-10, J2-11
Active low slave select 0 from master
to
slave 0
J2-10, J1-6, J1-11
spi_m_ss_1#
Output
Active low slave select 1 from master
to
slave 1
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master
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3.6 Parallel FIFO Interface - Asynchronous Mode
The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface available in
VNC1L VDIP1 module and has an eight bit data bus, individual read and write strobes and two hardware
flow control signals.
3.6.1 Signal Description - Parallel FIFO Interface
The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins. Table 3.6
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
Available Pins
Name
Type
Description
J2-10, J1-6, J1-11
fifo_data[0]
I/O
FIFO data bus Bit 0
J2-9, J1-8, J1-12
fifo_data[1]
J2-8, J1-9, J2-12
fifo_data[2]
J2-6, J1-10, J2-11
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
fifo_data[3]
fifo_data[4]
fifo_data[5]
J2-8, J1-9, J2-12
fifo_data[6]
J2-6, J1-10, J2-11
fifo_data[7]
J2-10, J1-6, J1-11
fifo_rxf#
J2-9, J1-8, J1-12
fifo_txe#
J2-8, J1-9, J2-12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Output
fifo_rd#
Input
FIFO data bus Bit 1
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
FIFO data bus Bit 6
FIFO data bus Bit 7
When high, do not read data from
the FIFO. When low, there is data
available in the FIFO which can be
read by strobing RD# low, then high.
When high, do not write data into the
FIFO. When low, data can be written
into the FIFO by strobing WR high,
then low.
Enables the current FIFO data byte
on D0...D7 when low. Fetches the
next FIFO data byte (if available)
from the receive FIFO buffer when
RD# goes from high to low
Writes the data byte on the D0...D7
pins into the transmit FIFO buffer
Input
when WR goes from high to low.
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
J2-6, J1-10, J2-11
fifo_wr#
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3.6.2 Timing Diagram – Asynchronous FIFO Mode Read and Write Cycle
When in Asynchronous FIFO interface mode, the timing of a read and write operation on the FIFO
interface is shown in Table 3.7 and Figure 3.3
Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle.
Time
Description
Min
Max
Unit
1
14
ns
100
-
ns
1
14
ns
t1
RD# inactive to RXF#
t2
RXF# inactive after RD# cycle
t3
RD# to Data
t4
RD# active pulse width
30
-
ns
t5
RD# active after RXF#
0
-
ns
t6
WR# active to TXE# inactive
t7
TXE# inactive after WR# cycle
t8
t9
1
14
ns
100
-
ns
DATA to TXE# active setup time
5
-
ns
DATA hold time after WR# inactive
5
-
ns
30
-
ns
t11
WR# active after TXE#
0
Table 3.7 - Asynchronous FIFO Mode Read Cycle Timing
ns
t10
WR# active pulse width
In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#
inputs.
Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#
output will also go high. It will only become low again when there is another byte to read.
When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when
there is still space for data to be written in to the module.
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3.7 Debugger Interface
The purpose of the debugger interface is to provide access to the VNC2 silicon/firmware debugger. The
debug interface can be accessed via the J2-10 pin on the DIL connector or, more easily, it can be
accessed by connecting a VNC2_Debug_Module to the J3 connector. This debug module will give access
to the debugger through a USB connection to a PC via the Integrated Development Environment (IDE).
The IDE is a graphical interface to the VNC2 software development tool-chain and gives the following
debug capabilities through the debugger interface:
Flash Erase, Write and Program.
Application debug - application code can have breakpoints, be single stepped and can be halted.
Detailed internal debug - memory and register read/write access.
The Debugger Interface, and how to use it, is further described in the following applications Note
Vinculum-II Debug Interface Description
3.7.1 Signal Description - Debugger Interface
Table 3.8 shows the signals and pins description for the Debugger Interface pin header J3
Name
Pin No.
Name
On PCB
Type
Description
J3-1
IO0
DBG
I/O
Debugger Interface
-
[Key]
-
Not connected. Used to make sure that the debug
J3-2
J3-3
GND
GND
J3-4
RESET#
RST#
J3-5
PROG#
PRG#
J3-6
5V0
VCC
module is connected correctly.
PWR
Input
Input
Module ground supply pin
Can be used by an external device to reset the
VNCL2. This pin is also used in combination with
PROG# and the UART interface to program
firmware into the VNC2.
This pin is used in combination with the RESET#
pin and the UART interface to program firmware
into the VNC2.
PWR Input
5.0V module supply pin. This pin can be used to
provide the 5.0V input to the V2DIP1-32 from the
debugger interface when the V2DIP1-32 is not
powered from the USB connector (VBUS) or the
DIL connector pins J1-1 and J3-6.
Table 3.8 - Signal Name and Description – Debugger Interface
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4
Firmware
4.1 Firmware Support
The VNC2 on the V2DIP1-32 can be programmed with the customers own firmware created using the
Vinculum II firmware development tool chain or with various pre-compiled firmware profiles to allow a
designer to easily change the functionality of the chip. Please refer to:- FTDI website for full details on
available pre-compiled firmware
4.2 Available Firmware
V2DAP firmware is currently available: USB Host for single Flash Disk and general purpose USB
peripherals. Selectable UART, FIFO or SPI interface command monitor. please refer to:- FTDI website for
full details.
4.3 Firmware Upgrades
Refer to the debugger interface section which can be used to update the firmware.
.
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5
External circuit Configuration
5.1 Adding a second USB Port
The external circuit configuration for adding second USB host port, with the USB activity LED,
is shown below in Figure 5.1
Figure 5.1 Additional USB Port Configuration
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6
Mechanical Dimensions
16.51
9.90
7.90
3.02
13.97
3.90
1.27
J1
CN1
17.78
J3
X 1A
I
D XX Q
FT XX -32
W
X 2
XX NC YW
V Y
2.36
1
LED1
U
15.47
J2
53.22
16.51
41.91
44.25
46.00
8.65
4.90
1.60
17.85
7.00
Figure 6.1 - V2DIP1-32 Dimensions (Top View)
2.54
Figure 6.2 - V2DIP1-32 Dimensions (Side View)
±0.20mm Tolerance (except pitch)
All dimensions are in mm
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7
Schematic Diagram
Figure 7.1 - V2DIP1-32 Schematic
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8
Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place,
Centurion Business Park
Glasgow, G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
sales1@ftdichip.com
E-mail (Support) support1@ftdichip.com
E-mail (General Enquiries) admin1@ftdichip.com
Web Site URL
http://www.ftdichip.com
Web Shop URL
http://www.ftdichip.com
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)
2F, No 516, Sec. 1 NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8791 3570
Fax: +886 (0) 2 8791 3576
E-mail (Sales)
tw.sales1@ftdichip.com
E-mail (Support) tw.support1@ftdichip.com
E-mail (General Enquiries) tw.admin1@ftdichip.com
Web Site URL
http://www.ftdichip.com
Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)
7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
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Copyright © 2010 Future Technology Devices International Limited
17
Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
`
Appendix A – References
Application and Technical Notes
Vinculum-II IO Cell Description
Vinculum-II Debug Interface Description
Vinculum-II IO Mux Explained
Vinculum-II PWM Example
Migrating Vinculum Designs From VNC1L to VNC2-48L1A
Vinculum-II Errata Technical Note
Copyright © 2010 Future Technology Devices International Limited
18
Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
`
Appendix B – List of Figures and Tables
List of Figures
Figure 1.1 - V2DIP1-32 ................................................................................................................. 1
Figure 3.1 - V2DIP1-32 Module Pin Out (Top View) .......................................................................... 4
Figure 3.2 - V2DIP1-32 Module Pin Out (Bottom View) ..................................................................... 5
Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle. ........................................................... 11
Figure 5.1 Additional USB Port Configuration .................................................................................. 14
Figure 6.1 - V2DIP1-32 Dimensions (Top View) .............................................................................. 15
Figure 6.2 - V2DIP1-32 Dimensions (Side View) ............................................................................. 15
Figure 7.1 - V2DIP1-32 Schematic ................................................................................................ 16
List of Tables
Table 3.1 - Pin Signal Descriptions .................................................................................................. 6
Table 3.2 - Default Interface I/O Pin Configuration ........................................................................... 7
Table 3.3 - Data and Control Bus Signal Mode Options – UART ........................................................... 8
Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave ..................................................... 9
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master ................................................... 9
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface ................................. 10
Table 3.7 - Asynchronous FIFO Mode Read Cycle Timing .................................................................. 11
Table 3.8 - Signal Name and Description – Debugger Interface ........................................................ 12
Copyright © 2010 Future Technology Devices International Limited
19
Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
`
Appendix C – Revision History
Version 1.0
First Release
16th April 2010
Version 1.01
Updated module’s images, mechanical drawings and
25th May 2010
Figure 5.1
Copyright © 2010 Future Technology Devices International Limited
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