FA3687V

FA3687V Quality is our message FUJI Power Supply Control IC FA3687V Application Note May –2001 Fuji Electric Co., Ltd. Matsumoto Factory 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 1 FA3687V Quality is our message WARNING 1.This Data Book contains the product specifications, characteristics, data, materials, and structures as of May 2001. The contents are subject to change without notice for specification changes or other reasons. When using a product listed in this Data Book, be sure to obtain the latest specifications. 2. All applications described in this Data Book exemplify the use of Fuji's products for your reference only. No right or license, either express or implied, under any patent, copyright, trade secret or other intellectual property right owned by Fuji Electric Co., Ltd. is (or shall be deemed) granted. Fuji makes no representation or warranty, whether express or implied, relating to the infringement or alleged infringement of other's intellectual property rights, which may arise from the use of the applications, described herein. 3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of semiconductor products may become faulty. When using Fuji Electric semiconductor products in your equipment, you are requested to take adequate safety measures to prevent the equipment from causing a physical injury, fire, or other problem if any of the products become faulty. It is recommended to make your design fail-safe, flame retardant, and free of malfunction. 4.The products introduced in this Data Book are intended for use in the following electronic and electrical equipment, which has normal reliability requirements. • Computers • OA equipment • Communications equipment (pin devices) • Measurement equipment • Machine tools • audiovisual equipment • electrical home appliances • Personal equipment • Industrial robots etc. 5.If you need to use a product in this Data Book for equipment requiring higher reliability than normal, such as for the equipment listed below, it is imperative to contact Fuji Electric to obtain prior approval. When using these products for such equipment, take adequate measures such as a backup system to prevent the equipment from malfunctioning even if a Fuji's product incorporated in the equipment becomes faulty. • Transportation equipment (mounted on cars and ships) • Trunk communications equipment • Traffic-signal control equipment • Gas leakage detectors with an auto-shut-off feature • Emergency equipment for responding to disasters and anti-burglary devices • Safety devices 6. Do not use products in this Data Book for the equipment requiring strict reliability such as (without limitation) • Space equipment • Aeronautic equipment • Atomic control equipment • Submarine repeater equipment • Medical equipment 7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be reproduced in any form or by any means without the express permission of Fuji Electric. 8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales agents before using the product. Neither Fuji nor its agents shall be liable for any injury caused by any use of the products not in accordance with instructions set forth herein. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 2 FA3687V Quality is our message CONTENTS page 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Description Features Outline Block diagram Pin assignment Ratings and characteristics Characteristic curves Description of each circuit Design advice Application circuit ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ ･･･････････････････ 4 4 4 5 5 6 10 17 21 25 Note • Parts tolerance and characteristics are not defined in all application described in this Data book. When design an actual circuit for a product, you must determine parts tolerances and characteristics for safe and stable operation. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 3 FA3687V 1. Description Quality is our message FA3687V is a PWM type DC-to-DC converter control IC with 2ch outputs that can directly drive power MOSFETs. CMOS devices with high breakdown voltage are used in this IC and low power consumption is achieved. This IC is suitable for very small DC-to-DC converters because of their small and thin package (1.1mm max.), and high frequency operation (to 1.5MHz). You can select Pch or Nch of MOSFETs driven, and design any topology of DC-toDC converter circuit like a buck, a boost, a inverting, a fly-back, or a forward. 2. Features ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Wide range of supply voltage: VCC=2.5 to 20V MOSFET direct driving Selectable output stage for Pch/Nch MOSFET on each channel Low operating current by CMOS process: 2.5mA (typ.) 2ch PWM control IC High frequency operation: 300kHz to 1.5MHz Simple setting of operation frequency by timing resistor Soft start function at each channel Adjustable maximum duty cycle at each channel Built-in undervoltage lockout High accuracy reference voltage: VREF: 1.00V±1%, VREG: 2.20V±1% Adjustable built-in timer latch for short-circuit protection Thin and small package: TSSOP-16 3. Outline 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 4 FA3687V Quality is our message ⑬ ＶＲＥＧ ⑥ ＶCC ⑦ CS2 ⑩ CS1 4. Block diagram Reference voltage 2.20V Regulated voltage ＵＶＬＯ Soft start 1.00V ⑫ RT Oscillator ＋ ⑭ IN1⑮ FB1 ⑤ IN2+ ④ IN2③ FB2 ＋ − − Er.Amp.1 ＋ − Comp.1 N/P ch. drive ⑨ OUT1 Er.Amp.2 − ＋ Comp.2 N/P ch. drive ⑯ SEL1 ⑧ OUT2 ② SEL2 FB voltage detection Timer latch ① CP ⑪ GND 5. Pin assignment Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin symbol CP SEL2 FB2 IN2IN2+ VCC CS2 OUT2 OUT1 CS1 GND RT VREG IN1FB1 SEL1 Description Timer latched short circuit protection Selection of type of driven MOSFET (OUT2) Ch.2 output of error amplifier Ch.2 inverting input to error amplifier Ch.2 non-inverting input to error amplifier Power supply Soft start for Ch.2 Ch.2 output Ch.1 output Soft start for Ch.1 Ground Oscillator timing resistor Regulated voltage output Ch.1 inverting input to error amplifier Ch.1 output of error amplifier Selection of type of driven MOSFET (OUT1) 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 5 FA3687V Quality is our message 6. Ratings and characteristics (1) Absolute maximum ratings Item Power supply voltage SEL1・SEL2 pin voltage FB1・IN1-・FB2・IN2-・IN2+ pin voltage CS1･CS2･CP･RT･VREG pin voltage OUT1/2 OUT pin source current OUT pin sink current OUT1/2 OUT pin source current OUT pin sink current Power dissipation　　　　　　※1 Operating junction temperature Operating ambient temperature Storage temperature ※1　Derating factor Ta≧25℃ : 3mW/℃ Maximum power dissipation curve Symbol Test condition VCC VSEL VEA_IN VCTR_IN IOUTIOUT+ IOUTIOUT+ Pd TJ TOPR TSTG Ta≦25℃ rating 20 -0.3 to 5.0 -0.3 to 5.0 -0.3 to 5.0 -400(peak) 　150(peak) -50(continuous) 　50(continuous) 300 +125 -30 to +85 -40 to +125 Unit V V V V mA mA mA mA mW ℃ ℃ ℃ Maximun power dissipation [mW］ 350 300 250 200 150 100 50 0 -30 0 30 60 90 120 150 Ambient temperature [℃] (2) Recommended operating conditions Item Supply voltage CS1･CS2･CP pin voltage SEL1･SEL2 pin voltage IN1-･IN2-･IN2+ pin voltage Oscillation frequency VREG pin capacitance VREG pin current VCC pin capacitance CS1 pin capacitance CS2 pin capacitance CP pin capacitance Symbol VCC VCTR_IN VSEL_IN VEA_IN fOSC CREG IREG CVCC CCS1 CCS2 CCP Test condition MIN. 2.5 0.0 0.0 0.0 300 TYP. ‐ ‐ ‐ 500 1.0 1.0 ‐ ‐ ‐ ‐ ― MAX. 18 2.5 2.5 2.5 1500 4.7 4.7 1.0 ‐ ‐ ‐ ― Unit V V V V kHz μF μF mA μF μF μF μＦ Vcc＜10V 10V≦Vcc＜18V 0.1 0.47 ‐ 1.0 Between CS1 and GND Between CS2 and VREG 0.01 0.01 Between CP and VREG ※2 ０．０１ ※2. If the timer latched mode is not needed, connect the CP pin to GND. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 6 FA3687V Quality is our message (3) Electrical characteristics * The characteristics is based on the condition of VCC=3.3V, CREG=1.0μF, RT=12kΩ, Ta=+25℃, unless otherwise specified. (1) Regulated voltage for internal control blocks (VREG pin) Item Regulated voltage Line regulation Load regulation Variation with temperature Symbol VREG VREG_LINE VCC=2.5 to 18V VREG_LOAD IREG=0 to 1mA VREG_TC Ta=-30 to +85℃ Test condition MIN. 2.178 ― -5 TYP. 2.200 ±5 -1 ±0.5 MAX. 2.222 ±15 Unit V mV mV % (2) Oscillator section (RT pin) Item Oscillation frequency Line regulation Variation with temperature Symbol fOSC fOSC_LINE fOSC_TC1 VCC=2.5 to 18V Ta=-30 to +85℃ Test condition MIN. 435 ― TYP. 500 ±1 ±3 MAX. 565 ±5 Unit kHz % % (3) Error Amplifier section (IN1-・FB1・IN2-・IN2+・FB2 pin) Item Symbol VREF1 VREF_LINE VREF_TC1 VOFFSET VOFF_LINE IINVCOM AVO fT ISIFB ISOFB VFB1=0.5V,VIN1-=VREG VFB2=0.5V,VIN2-=VREG,VIN2+=1V VFB1=VREG-0.5V,VIN1-=0V VFB2=VREG-0.5V,VIN2-=0V,VIN2+=1V Test condition ※3 VCC=2.5 to 18V Ta=-30 to +85℃ VIN2+=1.0V，IN2+・IN2VCC=2.5～18V VINx-=0.0 to 2.5V IN2+・IN2- MIN. 0.99 ― TYP. 1.00 ±2 ±0.5 MAX. 1.01 ±5 Unit V mV % Reference voltage (ch.1) VREF1 Line regulation (ch.1) VREF1Variation with temperature (ch.1) Input offset voltage (ch.2) VOFFSET Line regulation (ch.2) Input bias current Common mode input voltage Open loop gain Unity gain bandwidth Output current (sink) Output current (source) ― ― 0 0.0 ±10 ｍＶ ｍＶ mA 0.7 70 1.5 2.3 -360 3.5 -270 1.5 Ｖ dB MHz 4.7 -180 mA μA * 3: The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 7 FA3687V Quality is our message (4) Soft start section (CS1・CS2 pin) Item Threshold voltage (CS1) (Driving Nch-MOSFET) Symbol VCS1D0N VCS1D20N VCS1D80N VCS1D0P Threshold voltage (CS1) (Driving Pch-MOSFET) VCS1D20P VCS1D80P VCS1D100P VCS2D0N Threshold voltage (CS2) (Driving Nch-MOSFET) VCS2D20N VCS2D80N VCS2D0P Threshold voltage (CS2) (Driving Pch-MOSFET) VCS2D20P VCS2D80P VCS2D100P Test condition Duty cycle=0%, VFB1=1.4V Duty cycle =20%, VFB1=1.4V Duty cycle =80%, VFB1=1.4V Duty cycle =0%, VFB1=1.4V Duty cycle =20%, VFB1=1.4V Duty cycle =80%, VFB1=1.4V Duty cycle =100%, VFB1=1.4V Duty cycle =0%, VFB2=0.7V Duty cycle =20%, VFB2=0.7V Duty cycle =80%, VFB2=0.7V Duty cycle =0%, VFB2=0.7V Duty cycle =20%, VFB2=0.7V Duty cycle =80%, VFB2=0.7V Duty cycle =100%, VFB2=0.7V 1.20 0.84 1.21 0.85 0.90 1.26 0.89 1.25 MIN. TYP. 0.82 0.925 1.285 1.38 0.82 0.935 1.295 1.38 1.33 1.245 0.885 0.80 1.33 1.235 0.875 0.80 1.27 0.91 1.28 0.92 0.97 1.33 0.96 1.32 MAX. Unit Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ VCS1D100N Duty cycle =100%, VFB1=1.4V VCS2D100N Duty cycle =100%, VFB2=0.7V (5) Pulse width modulation (PWM) section (FB1・FB2 pin) Item Threshold voltage (FB1) (Driving Nch-MOSFET) Symbol VFB1D0N VFB1D20N VFB1D80N VFB1D100N Threshold voltage (FB1) (Driving Pch-MOSFET) VFB1D0P VFB1D20P VFB1D80P VFB2D0N Threshold voltage (FB2) (Driving Nch-MOSFET) VFB2D20N VFB2D80N VFB2D0P Threshold voltage (FB2) (Driving Pch-MOSFET) VFB2D20P VFB2D80P VFB2D100P Test condition Duty cycle =0%, VCS1=VREG Duty cycle =20%, VCS1=VREG Duty cycle =80%, VCS1=VREG Duty cycle =100%, VCS1=VREG Duty cycle =0%, VCS1=VREG Duty cycle =20%, VCS1=VREG Duty cycle =80%, VCS1=VREG Duty cycle =0%, VCS2=0V Duty cycle =20%, VCS2=0V Duty cycle =80%, VCS2=0V Duty cycle =0%, VCS2=0V Duty cycle =20%, VCS2=0V Duty cycle =80%, VCS2=0V Duty cycle =100%, VCS2=0V MIN. TYP. 0.82 0.925 1.285 1.38 0.82 0.935 1.295 1.38 1.33 1.245 0.885 0.80 1.33 1.235 0.875 0.80 MAX. Unit Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ Ｖ VFB1D100P Duty cycle =100%, VCS1=VREG VFB2D100N Duty cycle =100%, VCS2=0V 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 8 FA3687V Quality is our message (6) Timer latch protection section (CP pin) Item Threshold voltage of FB1 Threshold voltage of FB2 Threshold voltage of CS1 Threshold voltage of CS2 Charge current of CP Threshold voltage of CP Symbol VTHFB1TL VTHFB2TL VTHFB3TL ICP VTHCPTL ※6-1 ※6-2 ※6-3 Test condition MIN. 1.5 0.2 0.2 1.5 -2.4 1.6 TYP. ― ― ― ― -2.0 ― MAX. 2.0 0.6 0.6 2.0 -1.5 2.1 Unit V V V V μA V VVTHCS1TL ※6-4 VCP=0.5V,VFB1=2.1V (7) Under voltage lockout circuit section (VCC pin) Item ON threshold voltage of VCC Hysteresis voltage Symbol VUVLO ΔVUVLO Test condition MIN. 2.0 TYP. 2.2 0.1 MAX. 2.35 Unit V V (8) Output section (OUT1・OUT2･SEL1･SEL2 pin) Item High side on resistance of OUT1/2 Low side on resistance of OUT1/2 Rise time of OUT1/2 Fall time of OUT1/2 SEL pin voltage for driving Nch-MOSFET SEL pin voltage for driving Pch-MOSFET Symbol RONHI Test condition IOUT2=-50mA IOUT1=-50mA,VCC=5V IOUT1=-50mA,VCC=15V IOUT1=50mA RONLO tRISE tFALL VSELN VSELP IOUT2=50mA,VCC=5V IOUT2=50mA,VCC=15V CL=1000pF CL=1000pF 0.0 VREG-0.2 MIN. TYP. 10 9 8 5 5 5 25 40 ― ― MAX. 20 Unit Ω Ω Ω 10 Ω Ω Ω ns ns 0.2 VREG Ｖ Ｖ (9) Overall section Item Operating mode supply current Symbol ICCA ICCA1 ICCA2 ICCA3 Test condition Ch.1, Ch.2 operating mode Ch.1, Ch.2 off mode Ch.1, Ch.2 operating mode, Vcc=18V MIN. TYP. 2.5 2.0 3.0 2.0 MAX. 3.5 Unit mA mA mA mA Latch mode *6-1: The current source of the CP pin operates when the voltage of FB1 exceeds the threshold voltage as shown in the table. *6-2: The current source of the CP pin operates when the voltage of FB2 falls below the threshold voltage as shown in the table. * 6-3: The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table. * 6-4: The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 9 FA3687V 7. Characteristic　curves Oscillation frequency vs.Timing resistor Vcc=3.3V,Ta=25 ℃ Quality is our message Oscillation frequency vs. Supply voltage Vcc Ta=25 ℃,RT= 1 2kΩ(fosc=500kHz) 1800 1600 Oscillation frequency [kHz] Oscillation frequency [kHz] 1400 1200 1000 800 600 400 200 0 1 10 Timing resistor R T[k Ω] 100 510 508 506 504 502 500 498 496 494 492 490 0 5 10 Vcc [V] 15 20 Oscillation frequency vs. ambient temperature Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) Regulated voltage vs. Supply voltage Vcc Ta=25 ℃,RT= 1 2kΩ(fosc=500kHz) 570 Oscillation frequency [kHz] Regulated voltage V REG[V] 550 530 510 490 470 450 430 -50 -25 0 25 50 75 100 Ambient temperature Ta [℃] 125 150 2.23 2.22 2.21 2.20 2.19 2.18 2.17 0 5 10 Vcc[V] 15 20 Load current IREG=0A Regulated voltage vs. ambient temperature Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) Regulated voltage vs. load current Vcc=3.3V,RT = 1 2kΩ(fosc=500kHz) 2.23 Regulated voltage V REG[V] Regulated voltage V REG[V] 2.22 2.21 2.20 2.19 2.18 2.17 -50 -25 0 25 50 75 100 Ambient temperature Ta[℃] 125 150 2.23 2.22 Ta=85℃ 2.21 2.20 Ta=25℃ 2.19 2.18 2.17 0.0 0.2 0.4 0.6 0.8 Load current IREG[mA] 1.0 1.2 Ta=-30℃ 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 10 FA3687V Quality is our message Reference voltage vs. ambient temperature Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) Reference voltage vs. Supply voltage Vcc 1.020 1.015 Reference voltage V REF [V] 1.010 1.005 1.000 0.995 0.990 0.985 0.980 0 5 10 Vcc[V] 15 20 25 Reference voltage V REF[V] Ta=25 ℃,RT= 1 2kΩ(fosc=500kHz) 1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -50 -25 0 25 50 75 100 Ambient temperature Ta[℃] 125 150 Error amp. Output current(sink) vs. ambient temperature 5.0 Output current (sink) ISIFB [mA] 4.5 4.0 3.5 3.0 2.5 2.0 -50 -25 0 25 50 75 100 Ambient temperature Ta[℃] 125 150 Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) Error amp. Output current(source) vs. ambient temperature -150 Output current (source) ISOFB[uA] Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) -200 -250 -300 -350 -50 -25 0 25 50 75 100 Ambient temperature Ta[℃] 125 150 charge current of CP vs. ambient temperature -1.0 Charge current of CP[uA] Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) Threshold voltage of CP vs. ambient temperature 2.3 2.2 Threshold voltage of CP [V] Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) -1.5 2.1 2.0 1.9 1.8 1.7 1.6 -2.0 -2.5 -3.0 -50 -25 0 25 50 75 100 125 150 Ambient temperature Ta[℃] 1.5 -50 -25 0 25 50 75 100 Ambient temperature Ｔａ[℃] 125 150 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 11 FA3687V Quality is our message Output duty cycle vs.CS voltage (ch.1) Output duty cycle vs. Oscillation frequency (ch.1) VCS1=1.35V 100 fosc=300kHz 90 80 Output duty cycle (ch.1) [％] 70 fosc=760kHz 60 50 40 30 20 10 Driving Nch MOSFET Vcc=3.3V ，Ta=25℃ fosc=1.5MHz fosc=500kHz 100 90 80 Output duty cycle (ch.1) [％] 70 60 50 40 30 20 10 VCS1=1.30V Driving Nch MOSFET Vcc=3.3V ，Ta=25℃ VCS1=1.25V VCS1=1.20V VCS1=1. 15V VCS1=1. 10V VCS1=1.05V VCS1=1.00V VCS1=0.95V VCS1=0.90V VCS1=0.85V 0 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0 300 500 700 900 1100 1300 oscillation frequency [ｋＨｚ] 1500 VCS1 [V] Output duty cycle vs.CS voltage (ch.1) 100 90 80 Output duty cycle (ch.1) [％] Output duty cycle (ch.1) [％] 70 60 50 40 30 20 10 10 0 0.80 0 300 500 fosc=1.5MHz fosc=760kHz fosc=300kHz fosc=500kHz 90 80 70 60 100 Output duty cycle vs. Oscillation frequency (ch.1) VCS1=1.35V Driving Pch MOSFET Vcc=3.3V ，Ta=25℃ VCS1=1.30V VCS1=1.25V VCS1=1.20V VCS1=1. 15V 50 40 30 20 VCS1=1. 10V VCS1=1.05V VCS1=1.00V VCS1=0.95V VCS1=0.90V Driving Pch MOSFET Vcc=3.3V ，Ta=25℃ VCS1=0.85V 0.90 1.00 1.10 1.20 1.30 1.40 1.50 VCS1 [V] 700 900 1100 1300 Oscillation frequency [kHz] 1500 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 12 FA3687V Quality is our message Output duty cycle vs.CS voltage (ch.2) 100 90 fosc=500kHz 80 Output duty cycle (ch.2) [％] 70 fosc=760kHz 60 50 40 30 20 10 0 0.70 fosc=1.5MHz Driving Nch MOSFET Vcc=3.3V ，Ta=25℃ Output duty cycle (ch.2) [％] 80 70 60 50 40 30 fosc=300kHz 100 90 Output duty cycle vs. Oscillation frequency (ch.2) VCS2=0.80V Driving Nch MOSFET Vcc=3.3V，Ta=25 ℃ VCS2=0.85V VCS2=0.90V VCS2=0.95V VCS2=1.00V VCS2=1.05V VCS2=1. 10V VCS2=1. 15V VCS2=1.20V 20 10 0 0.80 0.90 1.00 1.10 VCS2 [V] 1.20 1.30 1.40 300 VCS2=1.25V VCS2=1.30V 500 700 900 1100 1300 Oscillation frequency [kHz] 1500 Output duty cycle vs. CS voltage (ch.2) 100 90 80 Output duty cycle (ch.2) [％] 70 60 fosc=760kHz 50 40 fosc=1.5MHz 30 20 10 0 0.70 Driving Pch MOSFET Vcc=3.3V ，Ta=25℃ fosc=300kHz fosc=500kHz 1 00 90 80 Output duty cycle (ch.2) [％] 70 60 50 40 30 20 10 0 0.80 0.90 1.00 1.10 VCS2 [V] 1.20 1.30 1.40 Output duty cycle vs. Oscillation frequency (ch.2) VCS2=0.80V Driving Pch MOSFET Vcc=3.3V，Ta=25 ℃ VCS2=0.85V VCS2=0.90V VCS2=0.95V VCS2=1.00V VCS2=1.05V VCS2=1. 10V VCS2=1. 15V VCS2=1.20V VCS2=1.25V VCS2=1.30V 300 500 700 900 11 00 1 300 Oscillation frequency [kHz] 1 500 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 13 FA3687V Quality is our message OUT1 terminal source current vs. H level output voltage OUT2 terminal source current vs. H level output voltage 0 -50 Vcc=2.5V 0 -50 -100 -150 IOUT1[mA] -200 -250 -300 -350 -400 -450 -500 0.0 1.0 2.0 3.0 4.0 Vcc-VOUT1[V] Vcc= 1 2V Vcc= 3V Ta=25 ℃ Ta=25 ℃ -100 -150 IOUT2[mA] -200 -250 -300 -350 -400 -450 -500 5.0 6.0 0.0 1.0 Vcc=2.5V Vcc= 3V Vcc= 5V Vcc= 5V Vcc= 1 2V 2.0 3.0 Vcc-VOUT2[V] 4.0 5.0 0 -50 -100 IOUT1[mA] OUT1 terminal source current vs. H level output voltage Vcc=3.3V 0 -50 -100 OUT2 terminal source current vs. H level output voltage Vcc=3.3V Ta=85 ℃ IOUT2[mA] Ta=85 ℃ -150 Ta=25 ℃ -150 -200 Ta=-30 ℃ -200 -250 -300 0.0 0.5 Ta=-30 ℃ Ta=25 ℃ -250 -300 1.0 1.5 2.0 Vcc-VOUT1[V] 2.5 3.0 0.0 0.5 1.0 1.5 2.0 Vcc-VOUT2[V] 2.5 3.0 OUT1 terminal source currentvs. H level output voltage 0 -100 IOUT1[mA] Vcc= 1 2V OUT2 terminal source current vs. H level output voltage 0 -100 IOUT2[mA] Vcc= 1 2V -200 -200 -300 Ta=-30 ℃ Ta=85 ℃ -300 Ta=-30 ℃ Ta=85 ℃ -400 -400 Ta=25 ℃ Ta=25 ℃ -500 0.0 1.0 2.0 3.0 Vcc-VOUT1[V] 4.0 5.0 -500 0.0 1.0 2.0 3.0 Vcc-VOUT2[V] 4.0 5.0 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 14 FA3687V Quality is our message OUT2 terminal sink current vs. L level voltage 200 Ta=25 ℃ Ta=25 ℃ OUT1 terminal sink current vs. L level voltage 200 150 IOUT1[mA] Ta=-30 ℃ 150 IOUT2[mA] Ta=85 ℃ Ta=-30 ℃ Ta=85 ℃ 100 100 50 50 0 0.0 0.2 0.4 0.6 0.8 VOUT1[V] 1.0 1.2 1.4 0 0.0 0.2 0.4 0.6 0.8 VOUT2[V] 1.0 1.2 1.4 OUT1 terminal Rise time vs. Supply voltage Vcc 60 OUT1 terminal Rise time t RISE[ns] 50 Ta=85℃ 40 30 20 10 0 0 5 10 Vcc[V] 15 20 Ta=-30℃ Ta=25℃ CL= 1 000pF OUT2 terminal Rise time vs. Supply voltage Vcc 60 OUT2 terminal Rise time t RISE[ns] 50 40 30 20 Ta=-30℃ 10 0 0 5 10 Vcc[V] 15 20 Ta=85℃ Ta=25℃ CL= 1 000pF OUT1 terminal Fall time vs. Supply voltage Vcc 200 FALL [ns] OUT2 terminal Fall time vs. Supply voltage Vcc 200 FALL [ns] CL= 1 000pF CL= 1 000pF Ta=85℃ 150 Ta=25℃ Ta=85℃ 150 Ta=25℃ OUT1 terminal Fall time t OUT2 terminal Fall time t 100 Ta=-30℃ 50 100 Ta=-30℃ 50 0 0 5 10 Vcc[V] 15 20 0 0 5 10 Vcc[V] 15 20 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 15 FA3687V Quality is our message Operating mode supply current vs. Oscillation frequency UVLO ON threshold vs. ambient temperature Ta=25 ℃ 6.0 Operating mode supply current I CCA[mA] 2.5 UVLO ON threshold VUVLO[V] 2.4 2.3 2.2 2.1 2.0 1.9 1.8 5.0 Vcc=18V Vcc=12V 4.0 Vcc=5V 3.0 Vcc=3.3V Vcc=2.5V 2.0 300 500 700 900 1100 1300 Oscillation frequency [kHz] 1500 -50 -25 0 25 50 75 100 Ambient temperature Ta[℃] 125 150 CS1 i nternal discharge switch current vs. voltage Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) CS2 internal discharge switch current vs. voltage Vcc=3.3V,RT= 1 2kΩ(fosc=500kHz) 400 350 300 ICS1off[uA] 250 200 150 100 50 0 0.00 Ta=85℃ Ta=-30℃ 0 Ta=25℃ ICS2off[uA] -50 -100 Ta=85℃ -150 Ta=-30℃ -200 0.50 1.00 1.50 VCS1[V] 2.00 2.50 0.00 0.50 1.00 V REG-VCS2[V] Ta=25℃ 1.50 2.00 Error Amplifier Gain and Phase vs. frequency 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 16 FA3687V Quality is our message 8. Description of each circuit (1) Reference voltage circuit (VREF) This circuit generates the reference voltage of 1.00V±1% compensated in temperature from VCC voltage, and is connected to the non-inverting input of the error amplifier. The voltage cannot be observed directly because there is no external pin for this purpose. (2) Regulated Voltage circuit (VREG) This circuit generates 2.20V±1% based on the reference voltage VREF, and is used as the power supply of the internal IC circuits. The voltage is generated when the supply voltage, VCC, is input. The VREG voltage is also used as a regulated power supply for Soft Start, Maximum Duty cycle limitation, and others. The output current for external circuit should be within 1mA. A capacitor connected between VREG pin and GND pin is necessary to stabilize the VREG voltage (To determine capacitance, refer to Recommended operating conditions). The VREG voltage is regulated in VCC voltage of 2.4V or above. (3) Oscillator The oscillator generates a triangular waveform by charging and discharging the built-in capacitor. A desired oscillation frequency can be set by the value of the resistor connected to the RT pin (Fig. 1). The built-in capacitor voltage oscillates between approximately 0.82V and 1.38V at fosc=500kHz(that of ch1 and ch2 are slightly different) with almost the same charging and discharging gradients (Fig. 2). You can set the desired oscillation frequency by changing the gradients using the resistor connected to the RT pin. (Large RT: low frequency, Small RT: high frequency) The oscillator waveform cannot be 1.38V observed from the outside because a pin for this purpose is not provided. The RT pin voltage is approximately 1V DC in normal operation. The 0.82V oscillator output is connected to the PWM comparator. OSC 12 RT RT Fig.1 RT value: large RT value: small Fig.2 (4) Error Amplifier Circuit The error amplifier 1 has the inverting input of IN1(-) pin (Pin14). The non-Inverting input is internally connected to the reference voltage VREF (1.00V±1%; 25℃). The error amplifier 2 has the inverting input IN2(-) pin (Pin4) and non-inverting input IN2(+) pin (Pin5) externally. Since each input of error amplifier 2 is connected to the pins, CH2 is suitable for any circuit topology. The FB pins (Pin3, Pin15) are the output of the error amplifier. An external RC network is connected between FB pin and INpin for gain and phase compensation setting. (Fig. 3) For connecting of each topology, see Design Advice. Vout1 RNF1 R1 14 Er.Amp.1 FB1 15 IN1R2 + Vout2 VREF (1.0V) VREG 13 Comp R3 R5 IN2+ 5 Er.Amp.2 Comp FB2 3 IN2R4 R6 4 RNF2 Fig.3 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 17 FA3687V Quality is our message (5) PWM comparator The PWM output generates from the oscillator output, the error amplifier output (FB1, FB2) and CS voltage (CS1, CS2) (Fig. 4). The FB1 oscillator output is compared with the preferred lower voltage between FB1 and CS1 for ch1. While the preferred voltage is lower than Oscillato oscillator output, the PWM output is low. While r the preferred voltage is higher than oscillator output output, the PWM output is high. Since the phase of Ch2 is the opposite phase of Ch1, higher voltage between FB2 and CS2 is preferred and while the preferred voltage is FB2 lower than the oscillator output, the PWM output 2 is high. (Cannot be observed externally) The output polarity of OUT1, OUT2 changes according to the condition of SEL pin. (See Fig. 6) PWM Comp.1 PWM output1 N/P ch. drive OUT1 9 CS1 16 SEL1 UVLO CS2 PWM output2 N/P ch. drive PWM Comp.2 OUT2 8 2 Fig.4 SEL2 (6) Soft start function This IC has a soft start function to protect DC-to-DC converter circuits from damage when starting operation. CS1 pin (Pin10), and CS2 pin (Pin7) are used for soft start function of ch1 and ch2 respectively. (Fig. 5) When the supply voltage is applied to the VCC pin and UVLO is cancelled, VREG VREG capacitor CCS1 and CCS2 is charged by VREG through the R7 13 13 resistor R7 or R9. Therefore, CS1 voltage gradually CCS2 10 increases and CS2 voltage gradually decreases. Since CS1 7 CS2 CCS1 CS1 and CS2 pin are connected to the PWM comparator R9 internally, the pulses gradually widen and then the soft start Fig.5 function operates. (Fig. 6) The maximum duty cycle can be set by using the CS pins. (See Design Advice about the detail) Er.Amp.1 output Oscillator output CS1 pin voltage ＣＳ2 pin voltage Oscillator output Er.Amp.2 output PWM output 1 PWM output2 OUT1 Pch.drive (SEL1：VREG) OUT1 Nch.drive (SEL1：GND) OUT2 Pch.drive (SEL2：VREG) OUT2 Nch.drive (SEL2：GND) Fig.6 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 18 FA3687V Quality is our message (7) Timer latch short-circuit protection circuit This IC has the timer latch short-circuit protection circuit. This circuit cuts off the output of all channels when the output voltage of DC-to-DC converter drops due to short circuit or overload. To set delay time for timer latch operation, a capacitor CCP should be connected to the CP pin (Fig. 7). When one of the output voltage of the DC-to-DC converter drops due to short circuit or overload, the FB1 pin voltage increases up to around the VREG voltage for Icp Vcp CP CCP 1 Fig.7 ch 1, or the FB2 pin voltage drops down to momentary short around 0 V for ch 2.When FB1 pin voltage circuit short circuit exceeds 2.0V(max.) or FB2 pin voltage VREG pin voltag 2.1V(max) falls below 0.2V(min.), constant-current 2.0 source (2 μ A typ.) starts charging the Start-up capacitor CCP connected to the CP pin. If short circuit the voltage of the CP pin exceeds 2.1 V protection 1.0 (max.), the circuit regards the case as tp abnormal. Then the IC is set to off latch mode and the output of all channels is shut Time　t off, (Fig. 8) and the current consumption Fig.8 become 2mA(typ.) The period (tp) between the occurrence of short-circuit in the converter output and setting to off latch mode can be calculated by the following equation: tp[ s ] = CCP * VTHCPTL ICP VTHCPTL: CP pin latched mode threshold voltage [V] ICP: CP charge source current [μA] CCP: capacitance of CP pin capacitor You can reset off latched mode of the short-circuit protection by either of the following ways about 1) CP pin, or 2) VCC pin, or 3) CS1or CS2 pin: 1) CP voltage = 0V 2) VCC voltage UVLO voltage (2.2V, typ.) or below 3) Set the CS pin of the cause of OFF latched mode as follows CS1 pin voltage = 0V, CS2 pin voltage = VREG If the timer-latched mode is not necessary, connect the CP pin to GND. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 19 CP pin voltage [V] FA3687V Quality is our message (8) Output circuit The IC contains a push-pull output stage and can directly drive MOSFETs. The maximum peak current of the output stage is sink current of +150mA, and source current of - 400mA. The IC can also drive NPN and PNP transistors. The maximum current in such cases is ± 50mA. You must design the output current considering the rating of power dissipation. (See Design Advice) You can switch the types of external discrete MOSFETs by wiring of the SEL pins (Pin 2, Pin 16). For driving Nch MOS, connect the SEL pins to GND. For driving Pch MOS, connect the SEL pins to VREG. You can design buck converter or inverting converter by driving Pch MOS, and boost converter by driving Nch MOS. Connect them either to GND or to VREG surely. (9) Under voltage lockout circuit The IC contains a under voltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. When the supply voltage rises from 0V, the IC starts to operate at VCC of 2.2V(typ.) and outputs generate pulses. If a drop of the supply voltage occurs, it stops output at VCC of 2.1V(typ.). When it occurs, the CS1 pin is turned to low level and the CS2 pin to high level, and then these pins are reset. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 20 FA3687V Quality is our message 9. Design Advice (1) Setting the oscillation frequency As described at Section 8-(1), “Description of Each Circuit,” a desired oscillation frequency can be determined by the value of the resistor connected to the RT pin. When designing an oscillation frequency, you can set any frequency between 300kHz and 1.5MHz. You can obtain the oscillation frequency from the characteristic curve “Oscillation frequency (fosc) vs. timing resistor resistance (RT)” or the value can be approximately calculated by the following expression. fosc = 4050 * RT −0.86  4050  RT =   fosc     1.16 fosc: oscillation frequency [kHz] RT: timing resistor [kΩ] This expression, however, can be used for rough calculation, the obitained value is not guaranteed. The operation frequency varies due to the conditions such as tolerance of the characteristics of the ICs, influence of noises, or external discrete components. When determining the values, examine the effectiveness of the values in an actual circuit. The timing resistor RT should be wired to the GND pin as shortly as possible because the RT pin is a high impedance pin and is easy affected by noises. (2) Operation near the maximum or the minimum output duty cycle As described in “Output duty cycle vs. voltage”, the output duty cycle of this IC changes sharply near the minimum and the maximum output duty cycle. Note that these phenomena are conspicuous for high frequency operation (when the pulse width is narrow). (3) Determining soft start period The period from the start of charging the capacitor CCS to widening n% of output duty cycle can be roughly calculated by the following expression: (see Fig. 5 for symbols)  VCS1n  t[ms] = − R7 * CCS1 * ln1 −  　　for CS1 pin  VREG   VCS 2 n  t[ms] = − R9 * CCS 2 * ln   VREG  for CS2 pin CCS1, CCS2: Capacitance connected to CS1or CS2 pin [μF] R7, R9: Resistance connected to CS1 or CS2 pin [kΩ] VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in n% of output duty cycle, and vary in accordance with operating frequency. The value can be obtained from the characteristic curve “Output duty cycle vs. CS voltage” To reset the soft start function, the supply voltage VCC is lowered below the UVLO voltage (2.1V typ.) and then the internal switch discharges the CS capacitor. The characteristics of the internal switch for discharge are shown in following the characteristics curves of “Characteristics of CS1 internal discharge switch current vs. voltage” and “Characteristics of CS2 internal discharge switch current vs. voltage”. Therefore, when determining the period of soft start at restarting the power supply, consider the characteristics carefully. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 21 FA3687V Quality is our message (4) Setting Maximum Duty Cycle As described in the Fig. 9, you can limit maximum duty VREG VREG R7 CCS2 13 13 cycle by connecting a resistor divider "R7, R8 or R9, R10" between CS1, CS2 and VREG pin. Set the R10 10 7 maximum duty cycle considering that relation between CS2 CS1 the maximum output duty cycle and the CS pin R8 R9 CCS1 voltage changes with operation frequency as Fig.9 described in the characteristics curves of “Output duty cycle vs. Oscillation frequency” and “Output duty cycle vs. CS voltage”. When the maximum duty cycle is limited, CS pin voltage at start-up is described in Fig. 10, and the approximate value of soft start period can be obtained by the following expressions: VCC Threshold voltage VCC Threshold voltage R8 R7 + R8 VREG pin voltage ⋅ VREG VCS1n VCS2n R9 R9 + R10 ⋅ VREG ｔ0 ｔ ｔ0 ｔ t0: Time from power-on of VCC to reaching unlock voltage of UVLO Fig.10  VCS1n  t[ms] = − R 0 * CCS1 * ln1 −  VCS1   The divided CS1 voltage is obtained by: R0 = R7 * R8 R7 + R8 for CS1 VCS1 = R8 * VREG R7 + R8 R9 * R10 R9 + R10  VCS 2 n − VCS 2  t[ms] = − R 0 * CCS 2 * ln   VREG − VCS 2  The divided CS2 voltage is obtained by: R0 = for CS2 VCS 2 = R9 * VREG R9 + R10 CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [μF] R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [kΩ] VCS1n and VCS2n are the voltages of CS1 and CS2 under a certain output duty cycle and varies with operation frequencies. The values of VCS1n and VCS2n can be obtained from the characteristics curve of “Output duty cycle vs. CS voltage”. The charging of CCS1 and CCS2 after UVLO is unlocked. Therefore, the period from power-on of Vcc to widening n% of output duty cycle is the sum of t0 and t 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 22 FA3687V Quality is our message (5) Determining the output voltage of DC-DC converters The ways to determine the output voltage of the DCch1 DC converter of each channel is shown in Fig. 10 and the following equations. Vout1 9 OUT1 SEL1 VREG Vout1 14 15 For ch1: The positive output voltage of DC-to-DC converter (a buck, a boost) is determined by: R1 IN1- 16 FB1 + R2 R1 + R 2 Vout1 = * VREF R2 For ch2: The positive output voltage of DC-to-DC converter is determined by: Vout1 VREF (1.0V) buck OUT1 9 SEL1 R1 IN114 15 16 Vout1 R3 + R 4 Vout 2 = V 1 * R3 Here,V 1 = VREG * When R5=R6, GND FB1 R2 VREF (1.0V) boost + R6 R5 + R 6 ch2 OUT2 8 Vout2 VREG 13 2 SEL2 VREG Vout2  R3 + R 4  Vout 2 = VREG *    2 R3  The negative output voltage of DC-to-DC converter (inverting) is determined by: R4 R5 IN2+ 5 FB2 3 IN2V1 R3 R6 4 buck OUT2 8 Vout 2 = R3 + R 4 R4 *V1 − * VREG R3 R3 Vout2 VREG 13 2 Vout2 SEL2 GND R4 R5 IN2+ 5 The ratio of resistances is determined by: FB2 3 V1 R3 R6 IN2- 4 R3 VREG − V 1 = R 4 Vout 2 + V 1 (Use the absolute value of the Vout2 voltage.) boost OUT2 8 VREG When R5=R6, 13 2 SEL2 VREG Vout2 R3 R5 V1 IN2+ 5 3 4  R3 − R 4  Vout 2 = VREG *    2 R3  Connect the SEL1 and SEL2 pin to GND or VREG surely. FB2 R4 R6 IN2- inverting Fig.11 Vout2 (6) Restriction of external discrete components and Recommended operating conditions To achieve a stable operation of the IC, the value of external discrete components connected to VCC, VREG, CS, CP pins should be within the recommended operating conditions. And the voltage and the current applied to each pin should be also within the recommended operating conditions. If the pin voltage of OUT1, OUT2, or VREG becomes higher than the VCC pin voltage, the current flows from the pins to the VCC pin because parasitic three diode exist between the VCC pin and these pins. Be careful not to allow this current to flow. 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 23 FA3687V Quality is our message (5) Loss Calculation Since it is difficult to measure IC loss directly, the calculation to obtain the approximate loss of the IC connected directly to a MOSFET is described below. When the supply voltage is VCC, the current consumption of the IC is ICCA, the total input gate charge of the driven MOSFET is Qg and the switching frequency is fsw, the total loss Pd of the IC can be calculated by: Pd ≒ VCC*(ICCA+Qg*fsw). The value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperature, or the tolerance of parameter. Therefore, evaluate the appropriateness of IC loss sufficiently considering the range of values of above parameters under all conditions. Example) ICCA=2.5mA for VCC=3.3V in the case of a typical IC from the characteristics curve. Qg=6nC, fsw=500kHz, the IC loss ”Pd” is as follows. Pd≒3.3*(2.5mA+6nC*500kHz)≒18.2mW if two MOSFETs are driven under the same condition for 2 channels, Pd is as follows: Pd≒3.3*{2.5mA+2*(6nC*500kHz)}=28.1mW 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 24 FA3687V Quality is our message 10.Application circuit 7to18V 40kΩ 5V/500mA GND 10uF 10uF GND 10kΩ 0.1uF 100kΩ 3.3V/500mA 0.01uF 100Ω 10uF 22kΩ 11 10 9 GND CS1 OUT1 VCC CS2 OUT2 6 8 7 0.1uF 100kΩ FA3687V 0.47uF 11kΩ 10kΩ 1MΩ 10kΩ 10kΩ 1uF 13 14 IN1- VREG FB2 3 IN2- IN2+ 4 5 12 RT 6.2kΩ 0.01uF 10kΩ 0.01uF 16 15 SEL1 FB1 CP 1 SEL2 2 0.068uF 　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 25