FA5546

FA5546/47 Fuji Electric Switching Power Supply Control IC Green Mode PWM IC FA5546 / 47 (2 Stage OLP Type) Application Note April -2011 Fuji Electric Co., Ltd. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 1 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 Caution 1. The contents of this note (Product Specification, Characteristics, Data, Materials, and Structure etc.) were prepared in April 2011. The contents will subject to change without notice due to product specification change or some other reasons. In case of using the products stated in this document, the latest product specification shall be provided and the data shall be checked. 2. The application examples in this note show the typical examples of using Fuji products and this note shall neither assure to enforce the industrial property including some other rights nor grant the license. 3. Fuji Electric Co.,Ltd. is always enhancing the product quality and reliability. However, semiconductor products may get out of order in a certain probability. Measures for ensuring safety, such as redundant design, spreading fire protection design, malfunction protection design shall be taken, so that Fuji Electric semiconductor product may not cause physical injury, property damage by fire and social damage as a result. 4. Products described in this note are manufactured and intended to be used in the following electronic devices and electric devices in which ordinary reliability is required: - Computer - OA equipment - Communication equipment (Terminal) - Measuring equipment - Machine tool - Audio Visual equipment - Home appliance - Personal equipment - Industrial robot etc. 5. Customers who are going to use our products in the following high reliable equipments shall contact us surely and obtain our consent in advance. In case when our products are used in the following equipment, suitable measures for keeping safety such as a back-up-system for malfunction of the equipment shall be taken even if Fuji Electric semiconductor products break down: - Transportation equipment (in-vehicle, in-ship etc.) - Communication equipment for trunk line - Traffic signal equipment - Gas leak detector and gas shutoff equipment - Disaster prevention/Security equipment - Various equipment for the safety. 6. Products described in this note shall not be used in the following equipments that require extremely high reliability: - Space equipment - Aircraft equipment - Atomic energy control equipment - Undersea communication equipment - Medical equipment. 7. When reprinting or copying all or a part of this note, our company’s acceptance in writing shall be obtained. 8. If obscure parts are found in the contents of this note, contact Fuji Electric Co.,Ltd. or a sales agent before using our products. Fuji Electric Co.,Ltd. and its sales agents shall not be liable for any damage that is caused by a customer who does not follow the instructions in this cautionary statement. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 2 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Overview Features Outline drawing Block diagram Functional description of pins Rating & Characteristics Characteristic curve Operation of each block Advice for designing Application circuit example ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ ・ ・ ・・ ・・ ・・ ・・ ・・ ・・ ・ ・・ 4 4 4 5 6 6～ 9 10～ 13 14～ 21 22～ 25 26～ 27 Caution) ・ The contents of this note subject to change without notice due to improvement. ・ The application examples or the parts constants in this note are shown to help your design. Variation of parts and service condition are not fully taken into account. Before use, a design with due consideration for these variations and conditions shall be conducted. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 3 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 1. Overview FA5546/47 is a current mode type switching power supply control IC possible to drive a power MOSFET directly. Despite of a small package with 8 pins, it has a lot of functions and it is best suited for power saving at the light load and decreasing external parts. Moreover it enables to realize a reduced space and a high cost-performance power supply. 2. Features ・Excellent Power Saving by lowering the oscillation frequency depending on the load at light load. ・Low power consumption by a built-in 500V high voltage startup circuit. ・Current Minus detection. Power Saving of the revision of the input voltage of OLP. ・Overload protection function with a few number of external components. Auto Recovery type or Timer Latch type. ・Two-stages Over Load Protection suitable for Motor Driving. ・Brown-In/Out Function without additional external components. ・VCC Over Voltage Protection function(OVP) (Vcc=26V). ・VCC Under-Voltage Lock-Out function (UVLO). (Vcc=18V/9.8V) ・Minimum ON width is replaced and restrains transient leaping up of the drain voltage of the MOSFET. ・Latch pin for an external signal: Over Temperature Protection, Over Voltage Protection etc. ・External MOSFET driving suitable for Power Supply up to 200W: -1.0A(sink),/+0.5A(source) ・Soft Start function. Function list (2 Stage OLP type) Part Number FA5546 FA5547 Switching frequency 60kHz 60kHz Auto Recovery Latch 200ms 200ms 1400ms OLP Type OLP Delay time OLP restart time IS pin VthIS(Voltage for current detection) -0.95V -0.95V 3. Outline drawing DIP-8 8 5 SOP-8 1 9.4 4 4 .5 Ma x. 6 .5 3. 5 Max. 3. 4 2.54 0.25 ±0.1 0.5 ±0.1 7.6 2.54×3=7.62 0° ～ 15 ° Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 4 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 4. Block diagram FA5546 (Overload protection : Auto recovery type) VH Start up Current ON + UVLO 5V Reg. OFF Reset Reset OSC Freq control input 5V OFF(FB) + × VCC Internal Power Supply DBL OUTPUT 1shot CLR RSFF S Q R IS comp. + + VCC OFF (IS) + Start up Management Logic Monitor Ctrl ON 30V Dmax OUT FB IS INV. AMP Lv. Shift Brownout + VCC + OVP LAT Brown out BO Timer - OLP + Ctrl T1 Over Load T2 OLP Timer 5V T1:Delay time to OLP-stop T2:Time to OLP-stop BO Latch Latch Set Reset Latch LAT GND + UVLO FA5547 (Overload protection : Latch shutdown type) VH Start up Current ON + UVLO 5V Reg. OFF Reset Reset OSC Freq control input 5V OFF(FB) + × VCC Internal Power Supply DBL OUTPUT 1shot CLR RSFF S Q R IS comp. + + VCC OFF (IS) + Start up Management Logic Monitor Ctrl ON 30V Dmax OUT FB IS INV. AMP Lv. Shift Brownout + VCC + OVP LAT Brown out BO Timer - OLP + Ctrl T1 Over Load T2 OLP Timer T1:Delay time to OLP-Latch BO Latch Latch Set Reset Latch 5V LAT GND + UVLO Over Load Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 5 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 5. Functional description of pins Pin No. 1 2 3 4 5 6 7 8 Pin Name LAT FB IS GND OUT VCC (NC) VH Pin function External latch signal input. Soft start. Feed back input. Light load and OLP detect Current s ense (Input) Ground Driver Output Power supply (unused) High voltage input. Brown-out detect VH 8 （NC） VCC 7 6 OUT 5 1 LAT 2 FB 3 IS 4 GND 6. Rating & characteristics * “+” shows sink and “–“ shows source in current prescription. (1) Absolute maximum rating Item Power supply voltage OUT pin output peak current OUT pin voltage FB pin voltage IS pin voltage LAT pin voltage VH pin input voltage Total loss (Ta = 25℃) Junction temperature in operation Storage temperature Symbol VCC Ioh Iol VOUT VFB VIS VLAT VVH Pd Tj Tstg Rating 28 -0.5 +1.0 -0.3 to Vcc+0.3 -0.3 to 5.0 -2.0 to 5.0 -0.3 to 5.0 -0.3 to 500 800 (DIP-8) 400 (SOP-8) -30 to 125 -40 to 150 Unit V A A V V V V V mW mW ℃ ℃ ○Allowable loss reduction characteristics 800mW (DIP) 400mW (SOP) Allowable loss 0 -30 25 85 125 Ambient Temperature Ta [℃] Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 6 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (2) Recommended operating condition Item VCC Power supply voltage Direct voltage High input voltage Half-wave rectification Full-wave rectification VH pin Resistance LAT pin capacity VCC pin capacity Operating ambient temperature Symbol VCC VVH(DC) VVH(AC1) VVH(AC2) RVH CLAT CVCC Ta MIN 11 100 80 80 2 0.22 10 -30 --1.0 33 TYP 18 MAX 22 450 288 288 10 2.2 100 85 Unit V V(DC) V(AC) V(AC) k ohm uF uF ℃ (3) Electric characteristics (in case nothing specified : Tj=25℃, VCC=18V) Switching oscillator section (FB pin) Item Oscillation frequency Voltage stability Temperature stability *1 FB pin threshold voltage for light load mode Oscillation frequency reduction ratio Minimum oscillation frequency Symbol Fosc Fdv Fdt Vfbm kf Fmin Δf/ΔVfb Conditions VFB=3V VCC：11V to 24V Tj= -30 to 125℃ MIN 54 -2 -5 0.95 200 0.22 TYP 60 － － 1.15 240 0.34 MAX 66 +2 +5 1.35 280 0.50 Unit kHz % % V kHz/V kHz External latch shutdown signal (LAT pin) Item Source current of LAT pin Latch-off level Latch-off delay timer *1 Symbol Ilat VthLAT TdLAT Conditions LAT=1.1V Charge period MIN -80 1.00 50 TYP -70 1.05 65 MAX -60 1.10 80 Unit uA V us Pulse width modulation section (FB pin) Item Maximum duty cycle Minimum duty cycle Input threshold voltage FB pin source current Symbol Dmax Dmin VthFB0 Ifb0 Conditions FB=4.5V FB=0V DUTY=0% VFB=0V MIN 75 － 340 -300 TYP 80 － 400 -250 MAX 85 0 460 -200 Unit % % mV uA Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 7 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 Over load protection(OLP) circuit section (FB pin) Item Over load detection threshold voltage *1 Over load detection Delay time Waiting time of auto restart *1 Symbol VthOLP TdOLP TdOLP2 VFB=4V VFB=4V FA5546 Conditions MIN 2.4 170 1200 TYP 2.8 200 1400 MAX 3.2 230 1600 Unit V ms ms Current sense section (IS pin) Item Voltage gain Maximum threshold voltage Over load detection threshold voltage *1 Input bias current Minimum ON pulse width Delay to output *1 Symbol AvIS VthIS1 VthIS2 IIS Tmin TpdIS Conditions ΔVFB/ΔVIS VFB=3V VFB=VthOLP VIS=0V Steady Start/Restart Tj=25℃ MIN -3.5 -1.05 -0.70 -50 950 180 50 TYP -3.0 -0.95 -0.63 -40 1250 280 200 MAX -2.5 -0.85 -0.56 -30 1500 380 300 Unit V/V V V uA ns ns ns VCC circuit section (VCC pin) Item Start-up threshold voltage Shutdown threshold voltage Hysteresis width VCC over-voltage protection threshold voltage Symbol VCCon VCCoff Vhys Vthovp Tj=25℃ Conditions MIN 16 8.8 6.8 25 TYP 18 9.8 8.2 26 MAX 20 10.8 9.6 27 Unit V V V V Output circuit section (OUT pin) Item Low output voltage High output voltage *1 Rise time *1 Fall time *1 Symbol VOL VOH tr tf Conditions IOL=100mA, VCC=18V IOH= -100mA, VCC=18V CL=1000pF, Tj=25℃ CL=1000pF , Tj=25℃ MIN 0.5 (14.5) 30 20 TYP 1.0 (16) 60 40 MAX 2.0 17 100 70 Unit V V ns ns Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 8 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 High-voltage input section (VH pin、VCC pin) Item Symbol IHrun Input Current of VH pin IHstb Threshold voltage level at brown-out (VH pin) Threshold voltage level at Brown-in (VH pin) Brown-out Delay time VthBO VthBI TpdBO VCCBH VCC voltage at Brown‐out VCCBL VCCLH H VCC voltage at Latch VCCLH VCCLL Ipre1 Charge current for VCC pin Ipre2 VH=80V, Upper level VH=80V, Lower level VH =120V, 1 time clamp VH=120V, Upper level VH =120V, Lower level VCC =16V, VH =120V VCC =11V, VH =120V at Latch Conditions VH=450V, VCC > VCCon VH =120V, VCC =0V VH pin： Decreasing VH pin： Increasing MIN 90 3.5 92 97 45 17 14.5 13 12 11 -8 TYP 130 6.2 99 104 50 18 15.5 14.5 13 12 -4.9 MAX 170 9.0 106 111 55 19 16.5 16 14 13 -2 Unit uA mA V V ms V V V V V mA -8.2 -5.3 -2.8 mA Power supply current Item (VCC pin) Symbol ICCop1 ICCop2 Conditions Duty cycle=Dmax VFB=2V,OUT=No Load Duty cycle=0% VFB=0V VH=80V, FB=open VCC=14.5V FB=open, VCC=11V OUT：No Load Icc=2mA MIN 1.0 0.95 TYP 1.3 1.25 MAX 1.6 1.55 Unit mA mA Operating-state supply current Supply current at Brownout ICCbo 600 800 1100 uA Latch mode supply current VCC pin zenner clamp voltage ICClat VCCzd 600 28 800 30 1100 34 uA V *1:This parameter is not 100% tested in production but guaranteed by design. It doesn’t guarantee the column of ‘-’ to have been specified. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 9 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 7. Characteristics curve ・In case nothing is specified otherwise: Ta=25℃, VCC＝18V ・“+” shows sink and “–“ shows source in current prescription. ・Data written here show the typical characteristics of the IC and do not guarantee the characteristics. Oscillation Frequency (Fosc) vs. Junction temperature(Tj) Oscillation Frequency (kHz) 62 61 60 59 58 -50 0 50 Tj (℃) 100 150 Oscillation Frequency changing rate(%) Oscillation Frequency (FOSC) changing rate vs. Junction temperature(Tj) 6 4 2 0 -2 -4 -6 -50 0 50 Tj (℃) 100 150 Oscillation Frequency (Fosc) vs. Power supply voltage (VCC) Oscillation Frequency (kHz) 62 61 60 59 58 5 10 15 20 25 30 Voltage (V) Oscillation Frequency changing rate(%) Oscillation Frequency (Fosc) changing rate vs. Power supply voltage 0.2 0.1 0 -0.1 -0.2 5 10 15 20 25 30 Voltage (V) Voltage at frequency drop started (V) FB pin voltage at frequency drop started (Vfbm) vs. Junction temperature (Tj) 1.4 LAT pin source current (uA) -64 -66 -68 -70 -72 -74 -76 LAT pin source current (Ilat) vs. Junction temperature (Tj) 1.3 1.2 1.1 1.0 0.9 -50 0 50 Tj (℃) 100 150 VLAT=1.1V -50 0 50 Tj (℃) 100 150 Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 10 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 1.10 1.05 1.00 0.95 -50 0 50 Tj (℃) 100 150 FB pin pulse stop Voltage (V) Latch cutoff threshold voltage (VthLAT) vs. Junction temperature (Tj) 1.15 Latch cutoff voltage (V) Output shutdown threshold voltage (VthFB0) vs. Junction temperature 0.44 0.42 0.40 0.38 0.36 -50 0 50 Tj (℃) 100 150 FB pin input resistance (Rfb) vs. Junction temprature (Tj) 22 FB pin source current (uA) -220 -230 -240 -250 -260 -270 -280 FB pin source current (Ifb0) vs. Junction temperature (Tj) FB pin Resistance (kΩ) 21 20 19 18 -50 0 50 Tj (℃) 100 150 VFB=0V -50 0 50 Tj (℃) 100 150 3.2 OLP detection voltage (V) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 -50 0 50 Tj (℃) 100 150 VIS=0V IS pin maximum threshold voltage (V) OLP detection voltage (VthOLP) vs. Junction temperature (Tj) Current sense maximum input threshold voltage(VthIS) vs. Junction temperature (Tj) -0.90 -0.92 -0.94 -0.96 -0.98 -1.00 -50 0 50 Tj (℃) 100 150 Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 11 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 Minimum ON width (Tmin) vs. Junction tmperature (Tj) 1400 Minimum Pulse width (ns) 1350 1300 1250 1200 1150 1100 -50 0 50 Tj (℃) 100 150 UVLO release threshold voltage (VCCon) vs. Junction temperature (Tj) 19.0 UVLO release voltage (V) 18.5 18.0 17.5 17.0 -50 0 50 Tj (℃) 100 150 UVLO activate threshold voltage (VCCoff) vs. Junction temperature (Tj) 10.2 UVLO activate voltage (V) 10.0 9.8 9.6 9.4 -50 0 50 Tj (℃) 100 150 28 OVP voltage (V) 27 26 25 24 Overvoltage threshold voltage (VthOVP) vs. Junction tmperature (Tj) -50 0 50 Tj (℃) 100 150 Output voltage high level (VOH) vs. Junction tmperature (Tj) 18 2000 Output low level (mV) 1500 1000 500 Output voltage low level (VOL) vs. Junction temperature (Tj) Output high level (V) . 17 16 15 IL=-100mA IL=100mA 0 14 -50 0 50 Tj (℃) 100 150 -50 0 50 Tj (℃) 100 150 Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 12 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 VH pin input current (IHstb) vs. Junction temperature (Tj) VH=120V VCC pin capacitance charge current (Ipre2) vs. Junction temperature (Tj) VCC pin Charge current (mA) -3 -4 -5 -6 VH=120V 9 VH pin input current (mA) 8 7 6 5 4 -50 0 50 Tj (℃) 100 150 VCC=0V -7 -8 -50 0 50 Tj (℃) VCC=11V 100 150 Operation-state Supply currentr (mA) Operating-state Supply current (mA) Operational power supply current (ICCop1) vs. Junction tempearature (Tj) 1.6 VFB=2V 1.5 OUT : No Load 1.4 1.3 1.2 1.1 1.0 -50 0 50 Tj (℃) 100 150 Operational power supply current (ICCop2) vs. VCC pin voltage (VCC) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 5 10 15 20 25 30 VCC (V) VFB=0V Latch power supply current (ICClat) vs. Junction temperature (Tj) Latch mode Supply Current (uA) 1100 VFB=open 1000 900 800 700 600 -50 0 50 Tj (℃) 100 150 Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 13 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 8. Operation of each block (1) Startup circuit The IC integrates a startup circuit having withstand voltage of 500V to achieve low power consumption. Fig.1 to Fig.3 show connections. Turning on the power, capacitor C2 connected to the VCC terminal is charged and the voltage increases due to the current fed from the startup circuit to the VCC terminal. If the ON threshold voltage (Vcc = 18V typ) of the under-voltage lockout circuit (UVLO) is exceeded, the power for internal operation is turned on, and the IC starts operating. The current supplied from the VH terminal to the VCC terminal is approximately 6mA when VCC = 0V. As the VCC voltage increases, the supply current decreases and reaches 4.9mA at the startup voltage. After IC operation is started, the startup circuit is shut down to minimize power loss. The current flowing into the VH terminal is 130A (typ) at VH = 450Vdc. A resistor, RVH (2k to 10k), is connected in series to the VH terminal to prevent the IC from being damaged by the surge voltage of the AC line. Fig.1 shows a typical connection where the VH terminal is connected to the half-wave rectifier circuit of AC input voltage. The startup time of this connection is the longest in 3 types of connection. However, if AC input voltage is shut down after the IC enters the latch mode, the supply of current from the VH terminal is interrupted by overload or overvoltage protection, which allows the latch mode to be reset in a time as short as several seconds. Fig.2 shows the connection where the VH terminal is connected to the full-wave rectifier circuit of AC input voltage. The startup time of this connection is approximately half of the connection shown in Fig.1, and its latch mode reset time can be made as short as that of connection shown in Fig.1 by interrupting the AC input voltage. Fig.3 shows the connection where the VH terminal is connected to the back of rectification and smoothing of AC input voltage. The startup time of this connection is the shortest in 3 types. In this connection, however, even if the AC input voltage is shut down after the IC enters the latch mode, the voltage charged in C1 is kept impressed to the VH terminal, requiring much time for the latch mode to be reset. It takes approximately several minutes to reset the latch mode, although the time varies depending on conditions. After the startup, the IC goes into switching operation, and is operated with the power supplied from the auxiliary winding. While the brownout function is working in a state in which the AC input voltage is low, the VCC voltage is kept within the 15.5V to 18V (typ) range by the ON/OFF control of the startup circuit. If the overload or overvoltage protection is actuated, causing the IC to enter the latch mode, the one time clamp circuit discharges the VCC voltage immediately down to 14.5V (typ). This function interrupts the AC input voltage and shortens the latch mode reset (by the UVLO reset function) time. Then the startup circuit is subjected to ON/OFF control to maintain the VCC voltage within the 12V to 13V (typ) range. The VCC voltage of the auto recovery type is maintained within the 15.5V to 18V (typ) range by the ON/OFF control of the startup circuit during the auto reset wait time after the overload shutdown. C1 Startup circuit current Startup circuit control signal RVH VH 8 6 VCC C2 start Fig.1 Startup circuit 1 (Half-wave) Fig.2 Startup circuit 2 (Full-wave) Fig.3 Startup circuit 3 (Rectification) Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 14 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (2) Oscillator This oscillator is used to determine the switching frequency. The switching frequency in the normal operation mode is set to 60kHz (typ) or 100kHz (typ) within the IC. To minimize the loss of power in the standby state, this IC is equipped with a function of automatically decreasing the switching frequency under light load. When the FB terminal voltage decreases down to 1.15V (typ) or lower under light load, the frequency decreases almost linearly proportional to the FB terminal voltage.( See Fig.4) The minimum frequency, Fmin, has been set to 0.34kHz (typ). When the load further decreases and thus the FB terminal voltage decreases down to 0.4V (typ) or lower, the switching is stopped. (See one-shot circuit.) In addition to trigger signals for determining switching frequency, the oscillator generates pulse signals for determining the maximum duty cycle and ramp signals for performing slope compensation. (3) Current comparator & PWM latch circuit The IC performs current mode control. Fig.5 shows a circuit block for basic operations, and Fig.6 shows a timing chart. The polarity of the current detection voltage of the IS terminal is negative. The GND of the IC is connected between the current detection resistor Rs and the MOSFET. (See Fig.5) A trigger signal having the switching frequency that is output from the oscillator is input to the PWM latch (F.F.) through the one-shot circuit as a set signal. Then the output of the PWM latch as well as the OUT terminal voltage reaches the High state. On the other hand, the current comparator (IS comp.) monitors the MOSFET current, and if the threshold voltage is reached, a reset signal is output. When a reset signal is input, the output of PWM latch (F.F.) as well as the OUT terminal voltage reaches the Low state. The ON pulse width of the OUT terminal is thus controlled with the threshold voltage of the current comparator (IS comp.). The output is controlled by changing the threshold voltage of this IS comp. with feedback signals. As shown in Fig.7, the FB terminal voltage is level-shifted by a reverse amplifier and input into the current comparator (IS comp.) as the threshold voltage. In addition, -0.95V (typ) reference voltage is input inside the IC to regulate the maximum input threshold voltage of the IS terminal, VthIS1 (overcurrent control threshold). The reverse amplifier output or the maximum IS terminal input threshold voltage, VthIS1, whichever is higher, is given precedence as the IS terminal threshold voltage. (Example: When the output of the reverse amplifier is -0.5V in a product whose maximum threshold voltage of the IS terminal, VthIS1, is -0.95V, the output of the reverse amplifier is given precedence and thus the current comparator is reversed when the IS terminal voltage reaches -0.5V.) Fig.5 Current mode basic operation circuit block Fig.6 Current mode basic operation timing chart Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 15 http://www.fujielectric.co.jp/products/semiconductor/ Switching frequency Fig.4 Oscillation frequency FA5546/47 In normal operation, the output voltage of the power supply is maintained constant by changing the threshold voltage of the current comparator via the FB terminal voltage. When the output voltage decreases, the feedback circuit increases the FB voltage to allow the threshold voltage of the current comparator to scale out to Low, thus increasing the MOSFET current. The maximum input threshold voltage of the IS terminal, VthIS1 (-0.95V typ) controls the maximum current of the MOSFET. If the FB terminal voltage increases under overload, the output of the reverse amplifier scales out to Low, decreasing down to lower than VthIS1. The threshold voltage of the IS terminal is thus controlled not to exceed VthIS1. The oscillator outputs pulses for determining the maximum duty cycle. Using these pulses, the maximum duty cycle has been set to 80% (typ). Fig.7 Current comparator Minimum ON width 1shot output (set pulse) (4) One shot circuit (minimum ON width) When the MOSFET is turned on, a surge current is generated due to discharge corresponding to the capacitance of the main circuit and gate drive current. If this surge current reaches the IS terminal threshold voltage, the current comparator output is reversed, and consequently normal pulses may not be generated from the OUT terminal. To avoid this phenomenon, a minimum ON width of OUT terminal output is set within the one-shot circuit block of the IC. If a trigger signal having the switching frequency is input from the oscillator, a pulse having a specific width is output as a PWM latch (F.F.) set signal. Since the set signal has priority over the input signal of the PWM latch, the output of the PWM latch (F.F.) is not reversed while the set signal from the one-shot circuit is being input, even if a reset signal is input from the current comparator (IS comp.) (See Fig.5) As a result, the input to the IS terminal is kept invalid for the specified period of time immediately after the output pulse is generated from the OUT terminal (minimum ON width), and made not to respond to the surge current at turn-on. (See Fig.8) This minimum ON width function eliminates the need of a noise filter for the IS terminal in principle. The minimum ON width is usually set to 1250ns (typ) in normal operations, and to 280ns (typ) at startup or rebooting to prevent the transient MOSFET drain voltage from surging. In addition, an exclusive comparator is integrated to keep the output pulse at zero under no load. (See Fig.9) This comparator reverses its output when the FB terminal voltage decreases down to 400mV (typ), preventing a set pulse to be input to the PWM latch (F.F.). The output is thus maintained in Low state and switching is stopped. OUT pin voltage IS pin voltage IS pin threshold voltage Output pulse does not stop here because of this minimum ON width. Fig.8 Minimum ON width Fig.9 Output shutdown function of FB pin Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 16 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (5) Overload protection circuit (auto restart type) Detecting overload, the overload protection (OLP) circuit stops switching in case overload is continued for a specified period of time (200ms typ) to protect the circuit. Overload detection is performed based on the FB terminal voltage. The overload detection level has been set to lower than the maximum input threshold of the IS terminal (2-stage OLP). Consequently, overcurrent can be output while the output voltage is maintained within specified time (200ms typ), on condition that the overload current does not exceed the maximum power threshold determined by the IS terminal. It is therefore ideal for applications in which overcurrent is fed instantaneously such as motors. Fig.10 is a conceptual diagram of the operation. Fig.11 shows a circuit block, and Fig.12 shows the protection operation timing chart, of the auto reset type. The overload protection is actuated when FB terminal voltage processed into a signal is detected with the OLP comparator, based on the overload delay time TdOLP (200ms typ), which is the period from the overload detection with the built-in OLP timer to switching pulse stop, and the auto reset wait time TdOLP2 (1400ms typ), which is the period from switching stop to switching restart. These periods are specified within the IC. When the output current increases and the FB terminal voltage increases up to VthOLP (2.8V typ), overload is detected. In this case, since the IS terminal voltage is equivalent to VthIS2 (-0.63V typ), which is smaller than the maximum input threshold voltage, VthIS1 (-0.95V typ), the MOSFET current is not limited and the output voltage is maintained. If the output current is further increased and the IS terminal voltage increases to reach the maximum threshold voltage, VthIS1 (-0.95V typ), the MOSFET current is limited and the output voltage cannot be maintained any longer. As soon as the overload is detected, the OLP timer starts counting the delay time up to the stop of the switching pulse. When specified overload protection delay time TdOLP (200ms typ) has elapsed, the switching pulse output is stopped. If overload is reset and the FB voltage decreases down to VthOLP (2.8V typ) before the overload protection delay time expires, switching continues. When switching is stopped, the OLP timer counts the auto reset wait time TdOLP2 (1400ms typ). The startup circuit is kept under the ON/OFF control while switching is suspended, and the VCC voltage is kept within the 15.5V to 18V (typ) range. When auto reset wait time TdOLP2 has elapsed, the switching pulse is output for rebooting. Vo Output Voltage 0 Current limit Over load detection Output Current 0 VCC MOSFET Gate 0 OLP period over 200 ms Stop switching Fig. 10 Conceptual diagram of overload protection operation 8 VH Start up Current ON VCC Start up Management Logic Monitor Ctrl ON DBL 5 OUT OLP Ctrl T1 T2 5V Rfb 20kΩ Over Load OLP Timer INV. AMP A FB 2 IS comp. VthIS1 4 3 GND IS Fig.11 Overload protection circuit (auto recovery) Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 17 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 Fig. 12 Overload protection timing chart (auto reset type) Since the OLP timer for overload protection delay time uses an up/down counter, a period for counting down is required to clear the count. Note that switching frequency (Fosc) is counted to detect the overload protection delay time (TdOLP). Consequently, if overload is reset within the overload protection delay time (less than 200ms), and the switching frequency decreases (down to less than 60kHz or 100kHz) immediately after that, the time for resetting the count is prolonged. In the case of a pulse load with which another overload occurs before the counter is reset, the next overload delay time should be made shorter (200ms or shorter). Example: In the case of a load with which overload current period of 50ms and no-load period of 1s are repeated, overload protection occurs within the overload delay time (200ms or shorter) as shown in Fig.13. Pay attention to the above in the case of a load with which overload and light load are repeated. Fig. 13 Typical overload/light load repetition timing chart Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 18 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (6) Overload protection circuit (latch shutdown type) Fig.14 shows a latch shutdown type circuit block, and Fig.15 shows the protection operation timing chart. The latch shutdown type operates on the same principle as the auto reset type up to switching stop. After the overload protection delay time TdOLP (200ms typ) has elapsed, the switching pulse output is stopped and the latch mode is entered. After the latch mode is entered, the one-time clamp circuit discharges the VCC voltage rapidly down to 14.5V (typ) (as in the case of the overvoltage protection). To maintain the latched state in the latch mode, the startup circuit is subjected to the ON/OFF control, and the VCC voltage is maintained within the 12V or 13V (typ) range. By interrupting the input voltage to decrease the VCC voltage to the OFF threshold voltage (9.8V typ) or lower, the latch mode can be reset. As described in the section of the auto reset type, in the case of a load with which overload and light load are repeated, latch shutdown may occur within the period of 200ms or shorter. Fig.14 Overload protection circuit (timer latch) VthIS1 4 3 FB 2 Rfb 20kΩ 8 VH Start up Current ON VCC Start up Management Logic Monitor Ctrl ON DBL 5 OUT OLP Ctrl T1 T2 5V INV. AMP A Over Load OLP Timer UVLO Latch Set Reset IS comp. GND IS Fig. 15 Overload protection timing chart (timer latch type) Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 19 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (7) Soft start The LAT terminal is equipped with a soft start function. Fig.16 shows the LAT terminal voltage at soft start. The LAT terminal voltage increases to 2.1V at the time of startup, and then discharged by the constant current source (70uA typ) down to 1.25V. During this period when the LAT terminal voltage decreases from 2.1V to 1.5V, soft start operation is performed. By adjusting the capacity of the capacitor to be connected to the LAT terminal, the soft start time can be set. Approximate soft start time can be calculated using the following expression: Tss = (2.1  1.5)  CLAT/70A = 0.0086  CLAT[F] Tss[ms] = 8.6  CLAT[F] where, Tss is soft start time. The maximum recommended value (2.2uF) of the LAT terminal capacity CLAT listed in 6-(2) assumes that the power supply startup time is approximately 20ms. If longer soft start time is set, the value can be increased to approximately 10F. The soft start time is affected by a thermistor connected to the LAT terminal for overheat protection, if any. Even if soft start is not necessary, connect a capacitor to prevent the LAT terminal voltage from decreasing instantaneously down to 1.05V or lower due to constant current discharge for soft start, thus causing latch shutdown to occur. (See 8-(8) Latch shutdown circuit by an external signal.) Fig. 17 Overheat protection function using a thermistor (9) Overvoltage protection circuit (VCC terminal) The IC integrates an overvoltage protection circuit for monitoring the VCC terminal voltage. (See Fig.18) If the VCC voltage increases and exceeds 26V typ, which is the reference voltage of the comparator (OVP), the comparator output is reversed to High level, setting the latch circuit to perform latch shutdown. At this time, the startup circuit is subjected to ON/OFF control to maintain the latch mode, thus keeping the VCC voltage within the 12V or 13V (typ) range. To reset the latch mode, interrupt the input voltage to decrease the VCC voltage down to the OFF threshold voltage (9.8V typ) or lower. Since 65s (typ) delay time has been set to the set input of the latch circuit, the latch mode is not entered even if the VCC terminal exceeds the detection voltage temporarily. 6 VH 8 Start up Circut ON UVLO VCC VCC Start up Management Logic Monitor Ctrl ON DBL 5 5V LAT 1 LAT OVP Latch Set Reset Latch OUT Fig. 16 LAT terminal soft start operation CLAT UVLO (8) Latch shutdown circuit by an external signal The LAT terminal is equipped with a latch shutdown function. (See Fig.17) By decreasing the LAT terminal voltage to 1.05V or lower, the IC enters the latch mode. To reset the latch mode, interrupt the input voltage, thus decreasing the VCC voltage to the OFF threshold voltage (9.8V typ) or lower. If the external latch shutdown function by the LAT terminal is not to be used, connect a capacitor only. Connect an NTC thermistor to the LAT terminal to use the overheat protective function. (See Fig.17) Fig. 18 Overvoltage protection circuit (10) Undervoltage lockout circuit (VCC terminal) The IC integrates an undervoltage lockout (UVLO) function to prevent circuit malfunction that might occur when power supply voltage decreases. When the VCC voltage increases from 0V and reaches 18V (typ), the circuit starts operating. When the VCC decreases down to 9.8V (typ), the circuit stops operating. In a state in which the undervoltage lockout function is actuated to stop IC operation, the OUT terminal is forcibly made to enter the Low state. The latch mode of the protection circuit is also reset. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 20 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (11) Output circuit The push/pull structure output circuit drives the MOSFET directly. The peak output current of the OUT terminal is 0.5A (source) and 1.0A (sink) in the maximum absolute ratings. In a state in which the IC is stopped in the undervoltage lockout circuit or operation is suspended in the latch mode, or in an auto reset wait state by overload protection function, the OUT terminal is brought into the Low level, and the MOSFET is interrupted. (12) Brown out (low AC input voltage protection) This IC integrates a brown out function that stops the output pulse of the OUT terminal when the AC input voltage decreases to protect the circuit. Integration of a high withstand voltage resistor eliminates the need of external parts. Switching is started when the peak of the AC input voltage to the VH terminal reaches the brown in threshold voltage (104V typ). (See Fig.19) When the input voltage decreases down to brown out threshold voltage (99V typ) or lower, the output is stopped after 50ms (typ) of delay time. (See Fig.20) The brown out function is actuated after the UVLO is reset. While switching operation is suspended by the brown out function, the startup circuit is subjected to ON/OFF control to maintain the VCC voltage within the 15.5V to 18V (typ) range. Fig. 19 Brown in and brown out detection circuit Brown IN Brown-IN Vth Diod brige Half wave 0 Rating Vo Secondary Vo 0 MOS gate 0 Brown OUT Brown-OUT Vth Diod brige Half wave 50ms Delay time Secondary Vo 0 Rating Vo 0 MOS gate 0 Fig. 20 Conceptual diagram of brown in and brown out operations Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 21 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 9. Advice for designing (1) Startup To properly start or stop the power supply, a capacitor having appropriate capacitance must be selected. (See Fig.21) Fig.22 shows the VCC voltage at the time of startup when an appropriate capacitor is connected. When the power is turned on, the capacitor of the VCC is charged with the current supplied from the startup circuit, and the voltage increases. When the VCC reaches the ON threshold voltage, the IC starts operating. The IC is operated based on the voltage supplied from the auxiliary winding. Note that during the period immediately after startup until the voltage of the auxiliary winding starts up, the VCC decreases. Select a capacitor for the VCC that does not allow the VCC to decrease down to the OFF threshold voltage. Specifically, a VCC terminal capacitor whose OFF threshold voltage is 11V or higher is recommended. If the capacitance of the VCC terminal is too small, VCC decreases to lower than the OFF threshold voltage before the voltage of the auxiliary winding starts up as shown by Fig.23. In this case, the VCC repeats up/down operation between ON and OFF threshold voltages, and consequently the power supply cannot be turned on. To prevent the VCC terminal voltage from decreasing to lower than the UVLO OFF threshold voltage due to sudden load change and other reasons, it may be desirable that the capacitance of the capacitor to be connected to the VCC terminal be made larger. However, if the capacitance of the capacitor of the VCC terminal is increased, the startup time is made longer. In such cases, the circuit shown in Fig.24 can balance the capacitance and the startup time. By setting C2 to less than C3, the startup time can be kept short. Since current is supplied via C3 after startup, the VCC terminal voltage hold time can be kept long even under sudden change conditions. Time t Fig. 23 VCC terminal voltage at startup (when capacitance is too small) Fig. 21 VCC terminal circuit Select a capacitor whose capacitance does not allow VCC voltage to decrease down to VCCoff. Auxiliary winding voltage Time t Fig. 22 VCC terminal voltage at startup Fig. 24 VCC circuit (shortening of startup time) (2) VCC hold time When the load of the power circuit is short-circuited, power supply from the auxiliary winding is interrupted, causing VCC to decrease. In this case, by resetting the VCC terminal when it decreases to lower than the OFF threshold voltage, VCCoff (9.8V typ), before the overload protection delay time (TdOLP) elapses, startup and stop are repeated. By this operation, the latch type is not stopped by latch shutdown, but run and stop are repeated irrespective of the auto reset wait time TdOLP2 (1400ms typ). (See Fig.25) To avoid this phenomenon, connect a capacitor whose capacitance does not allow VCC voltage to decrease down to the OFF threshold voltage on occurrence of short circuit of the load of the power circuit. Fig. 25 VCC hold time (at output short circuit) Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 22 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (3) Gate drive circuit To adjust switching speed and prevent vibration of the gate terminal, a resistor is connected between the MOSFET gate terminal and the OUT terminal of the IC in general. In some cases, driving current for turning on the MOSFET and that for turning it off are required to be determined separately. In this case, connect a gate drive circuit shown in Fig.26 or 27 between the gate terminal of the MOSFET and the OUT terminal. Fig. 28 Latch shutdown function by an external signal (5) Feedback In Fig.26, the current is limited by R1 and R2 when the power is turned on, while the current is limited only by R2 when it is turned off. In Fig.27, the current is limited only by R1 when the power is turned on, while the current is limited by R1 and R2 connected in parallel when the power is turned off. This signal gives threshold voltage for the current comparator. Consequently, if noise is added to this signal, the output pulses are disturbed. Capacitor C4 is generally connected for protection against noise. Fig.29 shows the circuit configuration of the FB terminal. A photo-coupler PC is connected as a feedback circuit that monitors the output voltage and performs PWM control. Q1 5 OUT R1 R2 2 Fig. 26 Gate drive circuit (1) FB PC R2 5 OUT R1 Q1 C4 Fig. 29 FB terminal circuit configuration Fig. 27 Gate drive circuit (2) (4) LAT terminal • To perform overheat protection using an NTC thermistor As shown in Fig.17, thermistor TH1 is connected to the LAT terminal to perform overheat protection (latch shutdown). Since the LAT terminal source current is 60A (min.), select TH1 whose resistor Rth satisfies the following expression at the desired overheat protection temperature. If temperature setting for overheat protection is not feasible with TH1 only, connect an additional resistor in series for adjustment. Rth  1.00V / 60A  16.7k • To perform latch shutdown using an independent abnormality detection signal To perform latch shutdown with an external signal, connect a peripheral circuit, allowing the LAT terminal voltage to be kept below 1.0V. Fig.28 shows a typical circuit connection. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 23 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (6) Current sensing unit As described in 8-(4) One-shot circuit, the minimum ON width is set for this IC to minimize malfunction due to surge current that occurs when the power MOSFET is turned on. However, if the surge current that occurs at the time of power ON is large, or noise is applied externally at the time of power ON, malfunction might occur. In such cases, add RC filters C5 and R7 as shown in Fig.30. To ensure efficient operation of the capacitor C5, place it as close to the IC as possible, and lay wiring with extreme care. Fig. 30 IS terminal filter IS 3 C5 4 5 OUT GND R7 Rs (7) Protection against noise Since large current is fed to the VCC terminal when the MOSFET is started, relatively large noise is likely to occur. In addition, noise is also generated from the current supplied from the auxiliary winding. A large noise may cause IC malfunction. To minimize the noise generated at the VCC terminal, connect a bypass capacitor C6 (0.1 F or larger), as shown in Fig.31, adjacent to the VCC terminal of the IC, and between VCC and GND, in addition to the electrolytic capacitor C2. If the load is made larger, or due to surge voltage, the VCC voltage increases, actuating the overvoltage protection function. To prevent this phenomenon from occurring, connect resistor R10 (several  to several 10) in series with the diode as shown in Fig.31. Fig. 31 Noise malfunction prevention (VCC terminal) (8) Improvement of input power at light load The IC integrates the function of reducing standby power consumption by lowering oscillation frequency under light load. However, since load conditions vary depending on the power supply setting, the settings within the IC may be insufficient to reduce standby power consumption. In such cases, connect resistor R8 as shown in Fig.32 to reduce oscillation frequency. If R7 is 1k, the resistance of R8 should be approximately several k to 100k. The smaller the R8 value, the lower the switching frequency under light load (positive IS terminal correction). Also check overload characteristics, which are affected by the correction described above. By connecting R8 and C7 in series and connecting them between IS-OUT terminals as shown in Fig.33, the Rs resistance can be set small, allowing the loss to be minimized. Example: R8 = 4.7k, C7 = 100pF Fig. 32 Correction circuit for improvement of input power under light load Fig. 33 Correction circuit for improvement of input power under light load Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 24 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 (9) Reduction of dependency of overload detection level on input voltage Since the gradient of the inductor current of a transformer varies depending on the input voltage in the overload protection function, the current value determined to be overload also varies. The higher the input voltage, the higher the output current that causes overload shutdown to occur. As shown in Fig.34. resistor R9 can be connected between the auxiliary winding and the IS terminal to minimize the dependency of the overload detection level on input voltage (IS terminal line correction). If R7 is 1k, the resistance of R9 should be approximately several 10k to several 100k. Note that if the input voltage is made low by correction, the power output current for overload shutdown decreases. Also note that the correction described above affects the input power under light load. Since the polarity of the detection voltage of the IS terminal is negative, the loss of correction resistance can be lower than that of the positive-polarity system (correction made based on AC rectification voltage). (11) Loss calculation To use the IC within its ratings, the loss of the IC may have to be found. However, it is not feasible to measure loss directly. The following is an example of finding a rough value of loss by calculation. The rough value of the total loss of the IC, Pd, can be calculated using the following expression: Pd  VCC  (ICCop1  Qg  fsw)  VVH  IHrun where, VVH: voltage to be applied to the VH terminal, IHrun: current fed to the VH terminal during operation, VCC: power voltage, ICCop1: Consumption current of the IC Qg: electrical charge to be input to the MOSFET gate used, and Fsw: switching frequency. A rough value can be found using the above expression, and the total loss found by the calculation, Pd, is slightly larger than the actual value. Be sure to take into consideration that each characteristic value varies depending on temperatures and other factors. VCC 6 34 IS GND C2 R9 R7 Rs Example: When the VH terminal is connected to a half-wave rectifier circuit with 100VAC input, the average voltage to be applied to the VH terminal is calculated to be approximately 45V, and the average current to be fed to the VH terminal is approximately 130A;. Furthermore, assuming that Tj = 25C, VCC = 18V, and Qg = 80nC, and based on IHrun = 130A, ICCop1 = 1.3mA (typ), and fsw = 60kHz (typ) (product having Fosc = 60kHz), the loss of the IC having standard characteristics can be calculated as follows: Pd  18V  (1.3mA  80nC  60kHz)  45V  130A  112mW Fig. 34 Reduction of dependency of overload detection level on input voltage (10) Prevention of malfunction due to negative potential of the terminal If large negative voltage is applied to each terminal of the IC, the parasitic element within the IC may be actuated, thus causing malfunction to occur. Be sure to maintain the voltage to be applied to each terminal within the maximum absolute ratings. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 25 http://www.fujielectric.co.jp/products/semiconductor/ FA5546/47 10. Application circuit example ・Vout=19Vdc, Iout=3.6A (Po=68w) Input voltage=80Vac to 264Vac (DEMO Board) C32 C33 Caution VH Pin is connected to near by diode bridge(DS1) to avoid VH Pin’s surge voltage it happens by change of startup current when startup circuit repeats on-off operating. ・Part List Component IC1 IC2 TR1 DS1 DS2 D2 D3,6 D4 PC1 T1 L1 L3 F1 C1 C2 C5 C6,40 C9 C11 C12 C13,16 C14 C36,37,38 C29 C30 C31 C32,33,34,35 Ｉｔｅｍ IC IC FET diode diode diode diode diode PhotoCoupler transformer coil coil Fuse Film capacitor Film capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor capacitor Type or Value Qty FA5546/FA5547 (Fuji) 1 TA76431F 1 2SK3677-01MR (Fuji) 1 D5SBA60 1 YG868C15R (Fuji) 1 EG01C 1 ERA92-02 (Fuji) 2 D1N60 1 TLP421F 1 EER28 1 (Np : Ns : Nb = 63 : 11 : 9) 12mH 1 3.3uH 1 3.15A 1 0.47uF 1 0.22uF 1 220uF 1 0.01uF 2 1uF 1 0.01uF 1 220pF 1 0.1uF 2 22uF 1 0.1uF 3 2200pF 1 2200pF 1 1500pF 1 470uF 4 Component R1,2 R3 R5 R6 R7 R8 R11 R14 R16 R21 R22 R23 R24 R31 R33 R34 R35 R36 R37 R38 TH1 TH2 ZNR1 Ｉｔｅｍ Type or Value resistor 1M Ω resistor 47k Ω resistor 0.68 Ω resistor 10k Ω resistor 68 Ω resistor 10 Ω resistor 2.2k Ω resistor 13k Ω resistor 5.1k Ω resistor 2.2 Ω resistor 1.2k Ω resistor 360k Ω resistor 33k Ω resistor 10 Ω resistor 3.3k Ω resistor 1k Ω resistor 10k Ω resistor 15k Ω resistor 1k Ω resistor 2.4k Ω Power thermistor 10Ω thermistor 100k Ω Surge absorber 680V Qty 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note) This application circuit example shows typical directions for use of this IC for reference and does not guarantee the operation and characteristics. Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 26 http://www.fujielectric.co.jp/products/semiconductor/ C34 FA5546/47 ・DEMO Board Typical characteristic curves(FA5546/47) Input Power at NO-Load 0.30 0.25 In pu t Po we r [W ] 0.20 0.15 0.10 0.05 0.00 50 100 150 200 250 300 Input Voltage[Vac] Switching Frequency at NO-Load 1.0 Swit c h i n g Fr e qu e n c y[kHz] 0.8 0.6 0.4 0.2 0.0 50 100 150 200 250 300 Input Voltage[Vac] Efficiency vs. Output Power 92 Efficiency (Iout=3.6A) 92 115Vac 90 230Vac 90 Effic i e n c y[% ] 88 86 84 82 Effic ie n c y[% ] 88 86 84 82 0 25 50 75 100 Efficiency >= 87%(AVE) 50 100 150 200 250 300 Output Power[%] Input Voltage[Vac] Output Voltage (Iout=3.6A) 22 Ou t pu t Vol tage [Vdc ] 21 20 19 18 17 16 50 100 150 200 250 300 Input Voltage[Vac] Ou t pu t Cu r r e n t at OPC[A] 6.0 5.5 5.0 4.5 4.0 3.5 3.0 50 Over Current Protection vs. Input Voltage 100 150 200 250 300 Input Voltage[Vac] Fuji Electric Co., Ltd. AN-027E Rev.0.4 April -2011 27 http://www.fujielectric.co.jp/products/semiconductor/