29LV800BE

SPANSION Flash Memory Data Sheet TM September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20888-6E FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT MBM29LV800TE60/70/90/MBM29LV800BE60/70/90 s DESCRIPTION The MBM29LV800TE/BE are a 8 M-bit, 3.0 V-only Flash memory organized as 1 M bytes of 8 bits each or 512 Kwords of 16 bits each. The MBM29LV800TE/BE are offered in a 48-pin TSOP (1) , 48-pin CSOP and 48ball FBGA package. These devices are designed to be programmed in a system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. Ordering Part No. VCC = 3.3 V VCC = 3.0 V +0.3 V −0.3 V +0.6 V −0.3 V MBM29LV800TE/BE 60  60 60 30  70 70 70 30  90 90 90 35 Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) s PACKAGES 48-pin Plastic TSOP (1) 48-pin Plastic CSOP 48-ball Plastic FBGA (FPT-48P-M19) (LCC-48P-M03) (BGA-48P-M20) MBM29LV800TE/BE60/70/90 (Continued) The standard MBM29LV800TE/BE offer access times 60 ns, 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention, the devices have separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The MBM29LV800TE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV800TE/BE are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV800TE/BE are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally resets to the read mode. The MBM29LV800TE/BE also have hardware RESET pins. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV800TE/BE memory electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29LV800TE/BE60/70/90 s FEATURES • 0.23 µm Process Technology • Single 3.0 V Read, Program, and Erase Minimized system level power requirements • Compatible with JEDEC-standard Commands Use the same software commands as E2PROMs • Compatible with JEDEC-standard World-wide Pinouts 48-pin TSOP (1) (Package suffix : TN Normal Bend Type) 48-pin CSOP (Package suffix : PCV) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 70 ns maximum access time • Sector Erase Architecture One 8 Kwords, two 4 Kwords, one 16 Kwords, and fifteen 32 Kwords sectors in word mode One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64 Kbytes sectors in byte mode Any combination of sectors can be concurrently erased, and also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithm Automatically pre-programs and erases the chip or any sector. • Embedded ProgramTM* Algorithm Automatically writes and verifies data at specified address. • Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, MBM29LV800TE/BE automatically switch themselves to low power mode. • Low VCC Write Inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device. • Sector Protection Hardware method disables any combination of sectors from program or erase operations. • Sector Protection Set Function by Extended Sector Protection Command • Fast Programming Function by Extended Command • Temporary Sector Unprotection Temporary sector unprotection via the RESET pin * : Embedde EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29LV800TE/BE60/70/90 s PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 N.C. N.C. WE RESET N.C. N.C. RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 MBM29LV800TE/MBM29LV800BE Normal Bend 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (FPT-48P-M19) (Continued) 4 MBM29LV800TE/BE60/70/90 CSOP (TOP VIEW) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. N.C. A8 A9 A10 A11 A12 A13 A14 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (LCC-48P-M03) (Continued) 5 MBM29LV800TE/BE60/70/90 (Continued) FBGA (TOP VIEW) Marking side A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 (BGA-48P-M20) A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY N.C. A18 N.C. DQ2 DQ10 DQ11 DQ3 A4 B4 C4 D4 E4 F4 G4 H4 WE RESET N.C. N.C. DQ5 DQ12 VCC DQ4 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 BYTE DQ15/A-1 VSS 6 MBM29LV800TE/BE60/70/90 s PIN DESCRIPTION Pin name A18 to A0, A-1 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Unprotection Selects 8-bit or 16-bit mode No Internal Connection Device Ground Device Power Supply Function 7 MBM29LV800TE/BE60/70/90 s BLOCK DIAGRAM RY/BY Buffer VCC VSS Erase Voltage Generator RY/BY DQ15 to DQ0 Input/Output Buffers WE BYTE RESET State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE OE STB Y-Decoder Y-Gating Low VCC Detector Timer for Program/Erase Address X-Decoder Latch Cell Matrix A18 to A0 A-1 s LOGIC SYMBOL A-1 19 A18 to A0 DQ15 to DQ0 CE OE WE RESET BYTE RY/BY 16 or 8 8 MBM29LV800TE/BE60/70/90 s DEVICE BUS OPERATION MBM29LV800TE/BE User Bus Operations (BYTE = VIH) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read * 3 1 CE L L L H L L 2, 4 OE L L L X H H VID L X X WE H H H X H L H X X A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ15 to DQ0 Code Code DOUT High-Z High-Z DIN X Code X High-Z RESET H H H H H H H H VID L Standby Output Disable Write (Program/Erase) Enable Sector Protection * * Verify Sector Protection *2, *4 Temporary Sector Unprotection*5 Reset (Hardware) /Standby Legend : L = VIL, H = VIH, X = VIL or VIH, L L X X = Pulse input. See “s DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “Sector Address Tables (MBM29LV800BE) ” in “s FLEXIBLE SECTOR-ERASE ARCHITECTURE”. *2: Refer to Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.0 V to 3.6 V (MBM29LV800TE/BE 60) = 2.7 V to 3.6 V (MBM29LV800TE/BE 70/90) *5: Also used for the extended sector protection. 9 MBM29LV800TE/BE60/70/90 MBM29LV800TE/BE User Bus Operations (BYTE = VIL) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read * 3 1 CE L L L H L L 2, 4 OE L L L X H H VID L X X WE H H H X H L H X X DQ15/ A-1 L L A-1 X X A-1 L L X X A0 L H A0 X X A0 L L X X A1 L L A1 X X A1 H H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ7 to DQ0 RESET Code Code DOUT High-Z High-Z DIN X Code X High-Z H H H H H H H H VID L Standby Output Disable Write (Program/Erase) Enable Sector Protection * * Verify Sector Protection *2, *4 Temporary Sector Unprotection *5 Reset (Hardware) /Standby Legend : L = VIL, H = VIH, X = VIL or VIH, L L X X = Pulse input. See “s DC CHARACTERISTICS” for voltage levels. *1: Manufacturer and device codes may also be accessed via a command register write sequence. See “Sector Address Tables (MBM29LV800BE) ” in “s FLEXIBLE SECTOR-ERASE ARCHITECTURE”. *2: Refer to Sector Protection. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.0 V to 3.6 V (MBM29LV800TE/BE 60) = 2.7 V to 3.6 V (MBM29LV800TE/BE 70/90) *5: Also used for the extended sector protection. 10 MBM29LV800TE/BE60/70/90 MBM29LV800TE/BE Command Definitions Command Sequence Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Second Fourth Bus Bus First Bus Third Bus Fifth Bus Sixth Bus Bus Read/Write Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Cycles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 1 1 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh  2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h   2AAh 555h PA XXXh  55h 55h 55h 55h 55h   55h PD  555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh   555h AAAh    F0h 90h A0h 80h 80h   20h         2AAh 555h 2AAh 555h           55h 55h           555h AAAh SA           10h 30h       Read/Reset*1 Read/Reset*1 Autoselect Program Chip Erase Sector Erase RA*5 RD*5 IA*5 PA 555h AAAh 555h AAAh      ID*5 PD AAh AAh      Erase Suspend Erase Resume Set to Fast Mode Fast Program*2 Reset from Fast Mode*2 Extended Sector Protection*3 Word Byte Word Byte Word Byte Word Byte XXXh B0h XXXh 30h 555h AAAh XXXh XXXh XXXh XXXh AAh A0h 90h 3 2 2 *4 XXXh F0h SPA 60h 3 XXXh 60h SPA 40h SPA*5 SD*5 *1 : Both of these reset commands are equivalent. *2 : This command is valid during Fast Mode. *3 : This command is valid while RESET = VID (except during HiddenROM MODE) . *4 : The data “00h” is also acceptable. *5 : The fourth bus cycle is only for read. Notes : • Address bits A18 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA) . • Bus operations are defined in “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV800TE/BE User Bus Operations (BYTE = VIL)”. • RA = Address of the memory location to be read. IA = Autoselect read address that sets A6, A1, A0. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 11 MBM29LV800TE/BE60/70/90 • RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. • SPA = Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0) . SD = Sector protection verify data. Output 01h at protected sector addressed and output 00h at unprotected sector addresses. • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A-1 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. • The command combinations not described in Command Definitions are illegal. MBM29LV800TE/BE Sector Protection Verify Autoselect Codes Type Manufacture’s Code MBM29LV800TE Device Code MBM29LV800BE Sector Protection Byte Word Byte Word A18 to A12 X X X Sector Addresses A6 VIL VIL VIL VIL A1 VIL VIL VIL VIH A0 VIL VIH VIH VIL A-1*1 VIL VIL X VIL X VIL Code (HEX) 04h DAh 22DAh 5Bh 225Bh 01h*2 *1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. Expanded Autoselect Code Table Type Manufacturer’s Code MBM29 Device LV800TE Code MBM29 LV800BE Sector Protection* (B) (B) Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h A-1/0 DAh 5Bh 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 (W) 22DAh (W) 225Bh 01h A-1/0 * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. (B) : Byte mode (W) : Word mode HI-Z : High-Z 12 MBM29LV800TE/BE60/70/90 s FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Tables (MBM29LV800TE) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X Address Range (×8) 00000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to F7FFFh F8000h to F9FFFh FA000h to FBFFFh FC000h to FFFFFh Address Range (×16) 00000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7BFFFh 7C000h to 7CFFFh 7D000h to 7DFFFh 7E000h to 7FFFFh 13 MBM29LV800TE/BE60/70/90 Sector Address Tables (MBM29LV800BE) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Address Range (×8) 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh Address Range (×16) 00000h to 01FFFh 02000h to 02FFFh 03000h to 03FFFh 04000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh 14 MBM29LV800TE/BE60/70/90 • One 16 Kbytes, two 8 Kbytes, one 32 Kbytes, and fifteen 64 Kbytes • Individual-sector, multiple-sector, or bulk-erase capability • Individual or multiple-sector protection is user definable. (×8) FFFFFh 16 Kbyte FBFFFh 8 Kbyte F9FFFh 8 Kbyte F7FFFh 32 Kbyte EFFFFh 64 Kbyte DFFFFh 64 Kbyte CFFFFh 64 Kbyte BFFFFh 64 Kbyte AFFFFh 64 Kbyte 9FFFFh 64 Kbyte 8FFFFh 64 Kbyte 7FFFFh 64 Kbyte 6FFFFh 64 Kbyte 5FFFFh 64 Kbyte 4FFFFh 64 Kbyte 3FFFFh 64 Kbyte 2FFFFh 64 Kbyte 1FFFFh 64 Kbyte 0FFFFh 64 Kbyte 00000h 00000h 07FFFh 16 Kbyte 00000h 00000h 0FFFFh 8 Kbyte 03FFFh 01FFFh 17FFFh 8 Kbyte 05FFFh 02FFFh 1FFFFh 32 Kbyte 07FFFh 03FFFh 27FFFh 64 Kbyte 0FFFFh 07FFFh 2FFFFh 64 Kbyte 1FFFFh 0FFFFh 37FFFh 64 Kbyte 2FFFFh 17FFFh 3FFFFh 64 Kbyte 3FFFFh 1FFFFh 47FFFh 64 Kbyte 4FFFFh 27FFFh 4FFFFh 64 Kbyte 5FFFFh 2FFFFh 57FFFh 64 Kbyte 6FFFFh 37FFFh 5FFFFh 64 Kbyte 7FFFFh 3FFFFh 67FFFh 64 Kbyte 8FFFFh 47FFFh 6FFFFh 64 Kbyte 9FFFFh 4FFFFh 77FFFh 64 Kbyte AFFFFh 57FFFh 7BFFFh 64 Kbyte BFFFFh 5FFFFh 7CFFFh 64 Kbyte CFFFFh 67FFFh 7DFFFh 64 Kbyte DFFFFh 6FFFFh (×16) 7FFFFh 64 Kbyte EFFFFh 77FFFh (×8) FFFFFh (×16) 7FFFFh MBM29LV800TE Sector Architecture MBM29LV800BE Sector Architecture 15 MBM29LV800TE/BE60/70/90 s FUNCTIONAL DESCRIPTION Read Mode The MBM29LV800TE/BE have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (Assuming the addresses have been stable for at least tACC-tOE time) . When reading out data without changing addresses after power-up, it is necessary to input hardware reset or change CE pin from “H” or “L” Standby Mode There are two ways to implement the standby mode on the MBM29LV800TE/BE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition, the current consumed is less than 5 µA. The device can be read with standard access time (tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA. Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode, the outputs are in the high impedance state, independently of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV800TE/BE data. This mode can be useful in the application such as handy terminal which requires low power consumption. To activate this mode, MBM29LV800TE/BE automatically switches themselves to low power mode when MBM29LV800TE/BE addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) . Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and MBM29LV800TE/BE read-out the data for changed addresses. Output Disable With the OE input at a logic high level (VIH) , the output from the devices is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, A6, and A-1. (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” in “ DEVICE BUS OPERATION”.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV800TE/BE are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29LV800TE/BE Command Definitions” in “ DEVICE BUS OPERATION”. (Refer to Autoselect Command section.) 16 MBM29LV800TE/BE60/70/90 Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier code (MBM29LV800TE = DAh and MBM29LV800BE = 5Bh for × 8 mode; MBM29LV800TE = 22DAh and MBM29LV800BE = 225Bh for × 16 mode) . These two bytes/words are given in “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION”. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION”.) Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29LV800TE/BE feature hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18) . The sector protection feature is enabled using programming equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may program and protect sectors in the factory prior to shiping the device. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V) , CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29LV800TE)” and “Sector Address Tables (MBM29LV800BE) ” in “ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See “Sector Protection Timing Diagram” in “ TIMING DIAGRAM” and “Sector Protection Algorithm” in “ FLOW CHART” for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, A13, and A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “ DEVICE BUS OPERATION” for Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29LV800TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the VID is taken away from the RESET pin, all the previously protected sectors will be protected again. See “Temporary Sector Unprotection Timing Diagram” in “ TIMING DIAGRAM” and “Temporary Sector Unprotection Algorithm” in “ FLOW CHART”. 17 MBM29LV800TE/BE60/70/90 Extended Sector Protection In addition to normal sector protection, the MBM29LV800TE/BE have Extended Sector Protection as extended function. This function enables to protect sector by forcing VID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition the operation is initiated by writing the set-up command (60h) into the command register. Then the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to be protected (recommend to set VIL for the other addresses pins) , and write extended sector protect command (60h) . A sector is generally protected in 250 µs. To verify programming of the protection circuitry, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ0 produces for protected sector in the read operation. If the output is logical “0”, repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH (refer to “Extended Sector Protection Algorithm” in “s FLOW CHART”) . RESET Hardware Reset The MBM29LV800TE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET pin goes low. Furthermore once the RESET pin goes high, the devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If hardware reset occurs during program or erase operation, the data at that particular location is corrupted. Note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “s TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, the erasing sector (s) cannot be used. 18 MBM29LV800TE/BE60/70/90 s COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. “MBM29LV800TE/BE Command Definitions” in “s DEVICE BUS OPERATION” defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Furthermore both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29LV800TE = DAh and MBM29LV 800BE = 5Bh for ×8 mode; MBM29LV800TE = 22DAh and MBM29LV800BE = 225Bh for ×16 mode) . (See “MBM29LV800TE/BE Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in “s DEVICE BUS OPERATION”.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h for ×16 (XX04h for ×8). Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be performed margin mode on the protected sector. (See “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV 800TE/BE User Bus Operations (BYTE = VIL)” in “s DEVICE BUS OPERATION”.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. Byte/Word Programming The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags”.) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. 19 MBM29LV800TE/BE60/70/90 If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “Embedded ProgramTM Algorithm” in “s FLOW CHART” illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “Embedded EraseTM Algorithm” in “s FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30h) is latched on the rising edge of WE. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV800TE/BE Command Definitions” in “s DEVICE BUS OPERATION”. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reenabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of the last WE will initiate the execution of the Sector Erase command (s) . If another falling edge of the WE occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Once execution has begun resetting the devices will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18) . Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the “tTOW” time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the devices return to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase 20 MBM29LV800TE/BE60/70/90 “Embedded EraseTM Algorithm” in “s FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector will cause DQ2 to toggle while the device is in the erase-suspend-read mode (See the section on DQ2) . After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode MBM29LV800TE/BE have Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. In Fast Mode, do not write any command other than the fast program/fast mode reset command. The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register (Refer to “Embedded Programming Algorithm for Fast Mode” in “s FLOW CHART”) . The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (Refer to “Embedded Programming Algorithm for Fast Mode” in “s FLOW CHART”) . 21 MBM29LV800TE/BE60/70/90 Write Operation Status Hardware Sequence Flags Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle*1 Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle Toggle Data 1*2 1 N/A N/A In Progress *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes : • DQ1 and DQ0 are reserved pins for future use. • DQ4 is Fujitsu internal use only. DQ7 Data Polling The MBM29LV800TE/BE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “s FLOW CHART”. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to completion, MBM29LV800TE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that devices are driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “s TIMING DIAGRAM” for the Data Polling timing specifications and diagrams. 22 MBM29LV800TE/BE60/70/90 DQ6 Toggle Bit I The MBM29LV800TE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulses in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulses sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 2 µs and then stop toggling with data unchanged. In erase, devices will erase all selected sectors except for ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 200 µs and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See “Taggle Bit I during Embedded Algorithm Operation Timing Diagram” in “s TIMING DIAGRAM” for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions, DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of devices under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in “MBM29LV800TE/BE User Bus Operations (BYTE = VIH)” and “MBM29LV800TE/BE User Bus Operations (BYTE = VIL)” in “s DEVICE BUS OPERATION”. The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case, the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once devices have exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since devices were incorrectly used. If this occurs, reset device with command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun : If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags”. 23 MBM29LV800TE/BE60/70/90 DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “DQ2 vs. DQ6” in “s TIMING DIAGRAM”. Furthermore, DQ2 can also be used to determine which sector is being erased. When device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Toggle Bit Status Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) *1 Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle *1 DQ2 1 Toggle Toggle 1 *2 *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. RY/BY Ready/Busy MBM29LV800TE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or has been completed. If output is low, devices are busy with either a program or erase operation. If output is high, devices are ready to accept any read/write or erase operation. If MBM29LV800TE/BE are placed in an Erase Suspend mode, RY/BY output will be high. During programming, RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth WE pulse. RY/BY pin will indicate a busy condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operation Timing Diagram” and “RESET, RY/BY Timing Diagram” in “s TIMING DIAGRAM” for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. 24 MBM29LV800TE/BE60/70/90 Byte/Word Configuration BYTE pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/BE devices. When this pin is driven high, devices operate in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, devices operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to “Timing Diagram for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE Timing Diagram for Write Operations” in “s TIMING DIAGRAM” for the timing diagram. Data Protection MBM29LV800TE/BE are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up, devices automatically reset internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. Devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 25 MBM29LV800TE/BE60/70/90 s ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET *1, *2 Power Supply Voltage *1 A9, OE, and RESET *1, *3 *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, inputs or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC + 0.5 V. During voltage transitions, inputs or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE, and RESET pins is −0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN − VCC) does not exceed + 9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol Tstg TA VIN, VOUT VCC VIN Rating Min −55 −40 −0.5 −0.5 −0.5 Max +125 +85 VCC + 0.5 +5.5 +13.0 Unit °C °C V V V s RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature Power Supply Voltage* Symbol TA VCC Part No. MBM29LV800TE/BE 60 MBM29LV800TE/BE 70/90 MBM29LV800TE/BE 60 MBM29LV800TE/BE 70/90 Value Min −20 −40 +3.0 +2.7 Typ     Max +70 +85 +3.6 +3.6 Unit °C °C V V * : Voltage is defined on the basis of VSS = GND = 0 V. Note : Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 26 MBM29LV800TE/BE60/70/90 s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V −0.5 V −2.0 V 20 ns 20 ns 20 ns Maximum Undershoot Waveform VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns 20 ns Maximum Overshoot Waveform 1 +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns 20 ns Note : This wave form is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 27 MBM29LV800TE/BE60/70/90 s DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Test Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 10 MHz VCC Active Current * 1 Value Min −1.0 −1.0  Byte Word Byte Word       −0.5 2.0 11.5  2.4 VCC − 0.4 2.3 Max +1.0 +1.0 35 22 25 12 15 35 5 5 Unit µA µA µA mA mA mA µA µA µA V V V V V V V ICC1 CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *3 Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage ICC2 ICC3 ICC4 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V VCC = VCC Max, RESET = VSS ± 0.3 V VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V    IOL = 4.0 mA, VCC = VCC Min IOH = −2.0 mA, VCC = VCC Min IOH = −100 µA  ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO 5 0.6 VCC + 0.3 12.5 0.45   2.5 *1: ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz) . *2: ICC is active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: (VID − VCC) do not exceed 9 V. 28 MBM29LV800TE/BE60/70/90 s AC CHARACTERISTICS • Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High Symbols JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX   tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH  CE = VIL OE = VIL OE = VIL       Value* Test Setup 60      0   60  60 60 30 25 25  20 5 70      0   70  70 70 30 25 25  20 5 90      0   90  90 90 35 30 30  20 5 Unit ns ns ns ns ns ns ns µs ns Min Max Min Max Min Max * : Test Conditions : Output Load : 1 TTL gate and 30 pF (MBM29LV800TE60/BE60, MBM29LV800TE70/BE70) 1 TTL gate and 100 pF (MBM29LV800TE90/BE90) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 3.3 V Diode = 1N3064 or equivalent Device Under Test 6.2 kΩ CL Diode = 1N3064 or equivalent 2.7 kΩ Note : CL = 30 pF including jig capacitance (MBM29LV800TE60/BE60, MBM29LV800TE70/BE70) CL = 100 pF including jig capacitance (MBM29LV800TE90/BE90) Test Conditions 29 MBM29LV800TE/BE60/70/90 • Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling  tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word tWHWH1 tWHWH2     2 2 Symbol MBM29LV800TE/BE 60 60 0 45 30 0 0 0                   8 16 1                                        25 70 0 45 35 0 0 0 10 0 0 0 0 0 0 35 35 25 25    50 500 4 100 4 4 0 500 200  70                   8 16 1                                         25 90 0 45 45 0 0 0 10 0 0 0 0 0 0 45 45 25 25    50 500 4 100 4 4 0 500 200  90                   8 16 1                                         30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs s µs ns µs µs µs µs ns ns ns ns JEDEC Standard Min Typ Max Min Typ Max Min Typ Max tAVAV tAVWL tWLAX tDVWH tWHDX  tWC tAS tAH tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVLHT tWPP tOESP tCSP tRB tRP tRH tFLQZ 10 0 0 0 0 0 0 30 30 25 25   50 500 4 100 4 4 0 500 200  Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation *1 VCC Setup Time Rise Time to VID *2 Voltage Transition Time *2 Write Pulse Width * OE Setup Time to WE Active * Recover Time From RY/BY RESET Pulse Width RESET High Level Period Before Read BYTE Switching Low to Output High-Z       CE Setup Time to WE Active *2 (Continued) 30 MBM29LV800TE/BE60/70/90 (Continued) Parameter BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time Symbol MBM29LV800TE/BE 60 70 90 Unit JEDEC Standard Min Typ Max Min Typ Max Min Typ Max      tFHQV tBUSY tEOE tTOW tSPD    50    60 90 60    50      70 90 70  20    50       90 90 90  20 ns ns ns µs µs 20  *1: Does not include the preprogramming time. *2: For Sector Protection operation. 31 MBM29LV800TE/BE60/70/90 s ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle Limits Min     100,000 Typ 1 8 16 8.4  Max 10 300 360 25  Unit s µs s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead  s TSOP (1) , FBGA, CSOP PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 7.5 8.0 10.0 Max 9.5 10.0 13.0 Unit pF pF pF Notes : • Test conditions TA = +25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 32 MBM29LV800TE/BE60/70/90 s TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L": Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Change from H to L Will Change from L to H Changing, State Unknown Center Line is HighImpedance "Off" State tRC Address tACC Address Stable CE tOE tDF OE tOEH WE tCE High-Z tOH High-Z Outputs Outputs Valid Read Operation Timing Diagram 33 MBM29LV800TE/BE60/70/90 tRC Address tACC Address Stable CE tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid Hardware Reset/Read Operation Timing Diagram 34 MBM29LV800TE/BE60/70/90 3rd Bus Cycle Data Polling PA tAS tAH PA tRC Address 555h tWC CE tCS tCH tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS tDH tDF tOH Data A0h PD DQ7 DOUT DOUT Notes : • • • • • • PA is the address of the memory location to be programmed. PD is the data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates the last two bus cycles out of four bus cycles sequence. These waveforms are for the × 16 mode (the addresses differ from × 8 mode). Alternate WE Controlled Program Operation Timing Diagram 35 MBM29LV800TE/BE60/70/90 3rd Bus Cycle Data Polling PA tAS tAH PA Address 555h tWC WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH PD DQ7 DOUT Data A0h Notes : • • • • • • PA is the address of the memory location to be programmed. PD is the data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates the last two bus cycles out of four bus cycles sequence. These waveforms are for the × 16 mode (the addresses differ from × 8 mode) . Alternate CE Controlled Program Operation Timing Diagram 36 MBM29LV800TE/BE60/70/90 Address 555h tWC 2AAh tAS tAH 555h 555h 2AAh SA* CE tCS tCH OE tGHWL tWP tWPH WE tDS AAh tDH 55h 80h AAh 55h 10h for Chip Erase 10h/ 30h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Note : These waveforms are for the × 16 mode (the addresses differ from × 8 mode) . Chip/Sector Erase Operation Timing Diagram 37 MBM29LV800TE/BE60/70/90 CE tCH tOE tDF OE tOEH WE tCE * DQ7 = Valid Data DQ7 Data DQ7 High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 Data tBUSY DQ6 to DQ0 = Outputs Flag tEOE DQ6 to DQ0 Valid Data High-Z RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation) . Data Polling during Embedded Algorithm Operation Timing Diagram 38 MBM29LV800TE/BE60/70/90 CE tOEH WE tOES OE tDH Data DQ7 to DQ0 DQ6 Toggle DQ6 Toggle tOE * DQ6 Stop Toggling DQ7 to DQ0 Data Valid DQ6 * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) Toggle Bit I during Embedded Algorithm Operation Timing Diagram Enter Embedded Erasing Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE Erase Suspend Read DQ6 DQ2* Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 39 MBM29LV800TE/BE60/70/90 CE Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY RY/BY Timing Diagram during Program/Erase Operation Timing Diagram WE RESET tRP tRB RY/BY tREADY RESET, RY/BY Timing Diagram 40 MBM29LV800TE/BE60/70/90 CE tCE BYTE DQ14 to DQ0 tELFH Data Output (DQ7 to DQ0) tFHQV A-1 DQ15 Data Output (DQ14 to DQ0) DQ15/A-1 Timing Diagram for Word Mode Configuration CE BYTE DQ14 to DQ0 tELFL Data Outputs (DQ14 to DQ0) tACC Data Outputs (DQ7 to DQ0) DQ15/A-1 DQ15 tFLQZ A-1 Timing Diagram for Byte Mode Configuration Falling edge of last write signal CE or WE BYTE tAS Input Valid tAH BYTE Timing Diagram for Write Operations 41 MBM29LV800TE/BE60/70/90 A18, A17, A16 A15, A14, A13 A12 SPAX SPAY A6, A0 A1 VID VIH A9 VID VIH OE tVLHT tVLHT tWPP tVLHT tVLHT WE tOESP CE tCSP Data tVCS tOE 01h VCC SPAX : Sector Address to be protected. SPAY : Next Sector Address to be protected. Note : A-1 is VIL on byte mode. Sector Protection Timing Diagram 42 MBM29LV800TE/BE60/70/90 VCC tVCS tVIDR tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period Temporary Sector Unprotection Timing Diagram 43 MBM29LV800TE/BE60/70/90 VCC VID VIH RESET Address tVCS tVLHT tVIDR tWC tWC SPAX SPAX SPAY A6, A0 A1 CE OE tWP TIME-OUT WE Data 60h 60h 40h tOE 01h 60h SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 µs (Min) Extended Sector Protection Timing Diagram 44 MBM29LV800TE/BE60/70/90 s FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling Embedded Program Algorithm in progress No Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded ProgramTM Algorithm 45 MBM29LV800TE/BE60/70/90 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling Embedded Erase Algorithm in progress No Data = FFh ? Yes Erasure Completed Chip Erase Command Sequence (Address/Command): 555h/AAh Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h 555h/10h Additional sector erase commands are optional. Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded EraseTM Algorithm 46 MBM29LV800TE/BE60/70/90 Start Read Byte (DQ7 to DQ0) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Data Polling Algorithm 47 MBM29LV800TE/BE60/70/90 Start *1 Read DQ7 to DQ0 Addr. = VIH or VIL Read DQ7 to DQ0 Addr. = VIH or VIL DQ6 = Toggle? Yes No DQ5 = 1? Yes No *1, *2 Read DQ7 to DQ0 Addr. = VIH or VIL Read DQ7 to DQ0 Addr. = VIH or VIL DQ6 = Toggle? Yes Program/Erase Operation Not Complete.Write Reset Command No Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Toggle Bit Algorithm 48 MBM29LV800TE/BE60/70/90 Start ( Setup Sector Addr. A18, A17,A16, A15, A14, A13, A12 PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A0 = VIL, A1 = VIH ) Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Address Addr. = SPA, A1 = VIH * A6 = A0 = VIL ( ) No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector ? No Device Failed Remove VID from A9 Write Reset Command Yes Sector Protection Completed * : A-1 is VIL on byte mode. Sector Protection Algorithm 49 MBM29LV800TE/BE60/70/90 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. Temporary Sector Unprotection Algorithm 50 MBM29LV800TE/BE60/70/90 Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Unprotection Mode No Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Write 60h to Secter Address (A6 = A0 = VIL, A1 = VIH) Time out 150 µs Increment PLSCNT To Verify Sector Protection Write 40h to Secter Address (A6 = A0 = VIL, A1 = VIH) Read from Sector Address (Addr. = SPA, A0 = VIL, A1 = VIH, A6 = VIL) Setup Next Sector Address No Data = 01h? Yes Protect Other Group ? Yes No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command No Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed Extended Sector Protection Algorithm 51 MBM29LV800TE/BE60/70/90 FAST MODE ALGORITHM Start 555h/AAh 2AAh/55h Set Fast Mode 555h/20h XXXh/A0h Program Address/Program Data Data Polling In Fast Program Verify Data? Yes Increment Address No Last Address? Yes Programming Completed No XXXh/90h Reset Fast Mode XXXh/F0h Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded Programming Algorithm for Fast Mode 52 MBM29LV800TE/BE60/70/90 s ORDERING INFORMATION Part No. MBM29LV800TE60TN MBM29LV800TE70TN MBM29LV800TE90TN MBM29LV800TE60PCV MBM29LV800TE70PCV MBM29LV800TE90PCV MBM29LV800TE60PBT MBM29LV800TE70PBT MBM29LV800TE90PBT MBM29LV800BE60TN MBM29LV800BE70TN MBM29LV800BE90TN MBM29LV800BE60PCV MBM29LV800BE70PCV MBM29LV800BE90PCV MBM29LV800BE60PBT MBM29LV800BE70PBT MBM29LV800BE90PBT Package 48-pin plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 48-pin plastic CSOP (LCC-48P-M03) 48-ball plastic FBGA (BGA-48P-M20) 48-pin plastic TSOP (1) (FPT-48P-M19) (Normal Bend) 48-pin plastic CSOP (LCC-48P-M03) 48-ball plastic FBGA (BGA-48P-M20) Access Time (ns) 60 70 90 60 70 90 60 70 90 60 70 90 60 70 90 60 70 90 Bottom Sector Top Sector Remarks MBM29LV800 T E 60 PCV PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PCV = 48-Pin C-lead Small Outline Package (CSOP) PBT = 48-Ball Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide Device Revision BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV800 8 Mega-bit (1 M × 8-Bit or 512 K × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase 53 MBM29LV800TE/BE60/70/90 s PACKAGE DIMENSIONS 48-pin plastic TSOP (1) (FPT-48P-M19) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48 LEAD No. 1 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) * 12.00±0.20 (.472±.008) 1.10 –0.05 +0.10 +.004 .043 –.002 (Mounting height) 0.50(.020) "A" 0.10(.004) 0.17 –0.08 .007 –.003 C +0.03 +.001 0.10±0.05 (.004±.002) (Stand off height) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 54 MBM29LV800TE/BE60/70/90 48-pin plastic CSOP (LCC-48P-M03) Note 1) Note 2) Note 3) Note 4) 25 *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . *2 : These dimensions do not include resin protrusion. Pins width includes plating thickness. Pins width do not include tie bar cutting remainder. "A" 48 10.00±0.20 (.394±.008) *2 9.50±0.10 (.374±.004) INDEX INDEX 0.05 –0 +0.05 +.002 .002 –.0 (Stand off) LEAD No. 1 24 *1 10.00±0.10(.394±.004) 0.95±0.05(.037±.002) (Mounting height) 0.22±0.035 (.009±.001) Details of "A" part 0˚~10˚ 0.65(.026) 1.15(.045) 0.40(.016) 9.20(.362)REF 0.08(.003) C 2003 FUJITSU LIMITED C48056S-c-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 55 MBM29LV800TE/BE60/70/90 (Continued) 48-ball plastic FBGA (BGA-48P-M20) 8.00±0.20(.315±.008) 1.08 –0.13 .043 –.005 (Mounting height) 0.38±0.10(.015±.004) (Stand off) +0.12 +.003 5.60(.220) 0.80(.031)TYP 6 5 6.00±0.20 (.236±.008) 4 4.00(.157) 3 2 1 (INDEX AREA) H G F E D C B A M 48-ø0.45±0.05 (48-ø.018±.002) ø0.08(.003) 0.10(.004) C 2003 FUJITSU LIMITED B48020S-c-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 56 MBM29LV800TE/BE60/70/90 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 © FUJITSU LIMITED Printed in Japan