CE71T6

CE71 Series Embedded Array 0.25µm CMOS Technology Featur es • • • • • • • • 0.18µm Leff (0.24µm drawn) Propagation delay of 61 ps Separate core and I/O supply voltages Mixed-signal macros–A/D and D/A converters I/Os: 2.5V, 3.3V, 5V tolerant Core power supply voltage: 2.5V, 1.8V, 1.5V Junction temperature: -40ºC~125ºC High performance and special I/Os–PCML, LVDS, PCI, SSTL, GTL+, AGP, USB • Analog and digital PLLs • Packaging options: QFP, HQFP, BGA, TBGA • Support for major third-party EDA tools PCI Fixed Layout Soft Macro t Embedded Hard Macro Clk 5V Tol. 3V Clock Tree Fixed Layout Soft Macro PCML Description Fujitsu’s CE71 is a series of high-performance, 0.18µm Leff CMOS embedded arrays that include full support of diffused high-speed RAMs, ROMs, mixed-signal macros, and a variety of other embedded functions. The CE71 series offers density and performance similar to those of standard cells, yet provides the time-to-market advantage of gate arrays. The CE71 series devices include 44µm, 66µm, or 88µm pad pitch for a cost-effective solution for both pad-limited and core-limited designs. With a nominal 1.5V to 2.5V core operation and with 2.5V and 3.3V/5V tolerant I/Os, the CE71 series features a very low-power consumption of 0.06µW/gate/MHz. Potential applications for the CE71 series include computing, graphics, communications, networking, wireless, and consumer designs. J-Series with 66µm Stagger Pad Pitch and Wire Bonding t Frame CE71J1 CE71J2 CE71J3 CE71J4 CE71J5 CE71J6 CE71J7 CE71J8 CE71J9 CE71JA CE71JB CE71JC CE71JD CE71JE CE71JF CE71JG Total Gates 216K 312K 488K 703K 911K 1,098K 1,302K 1,524K 2.020K 2,586K 3,055K 3,564K 4,113K 5,114K 6,698K 8,096K Total Pads 192 224 272 320 360 392 424 456 520 584 632 680 728 808 920 1,008 Signals 152 152 178 206 264 304 360 360 360 472 472 506 506 506 506 506 K-Series with 88µm Inline Pad Pitch and Wire Bonding Frame CE71K1 CE71K2 CE71K3 CE71K4 CE71K5 CE71K6 CE71K7 CE71K8 Total Gates 167K 237K 348K 524K 734K 963K 1,110K 1,559K Total Pads 100 120 144 176 208 240 256 304 Signals 88 102 126 152 178 206 220 264 CE71 Series Embedded Array L-Series with 44µm Inline Pad Pitch and Au Bump Frame CE71L4 CE71L5 CE71L6 CE71L7 CE71L8 CE71L9 CE71LA CE71LB CE71LC CE71LD CE71LE Total Gates 356K 476K 677K 1,034K 1,469K 1,976K 2,513K 3,001K 3,506K 4,050K 5,043K Total Pads 304 352 420 520 620 720 812 888 960 1,032 1,152 Signals 264 304 360 428 504 504 504 504 504 504 504 Memory Macros • SRAM Compiler: single and dual port (1 R/W, 1R), up to 72K bits per block, both BUS and Partial Write • ROM Compiler: up to 512K bits per block • High-density single-port RAM 288K bits • Register file (2R/W, 2R/2W), up to 4,608 bits Phase-Locked Loops • Analog: up to 250 MHz (622 MHz under development) I/Os • 2.5V, 3.3V, and 5V tolerant • Slew-rate controlled • CMOS, TTL, PCML, T-LVTTL, LVDS, PCI, SSTL, GTL+, AGP, USB SOC IP Cores ARM 7TDMI Hard Macro ARC 32-bit RISC 834/836 SPARClite Hard Macros Oak DSP Hard Macro 10/100 MAC 64/256 QAM MPEG2 Decoder/Demultiplexer 8VSB TV Demodulator AC-3 Dolby Voice Decoder JPEG Encoder and Decoder PCI–33/66 MHz, 32/64-bit cores USB Host Controller/Device I2C IDE (ATA3) Host Controller Smart Card I/F IRDA I/R Interface More IPs are being added ASIC Design Kit and EDA Support Verilog Logic Simulators from Cadence, Synopsys, and Mentor VHDL/VITAL Logic Simulators from Synopsys, Cadence, and Mentor Synthesis, power, DFT, and STA tools from Synopsys Other EDA tools Verilog-XL, NC-Verilog, VCS, Model-sim (Verilog) VSS, Model-sim (VHDL), V-System, Leapfrog Design Compiler, Design Power, Test Compiler, PrimeTime, MOTIVE, and Sunrise TestGen Chrysalis Design Verifyer and Sente Watt Watcher T-Series with 88µm Inline Pad Pitch and Wire Bonding Frame CE71T2 CE71T3 CE71T4 CE71T5 CE71T6 CE71T7 CE71T8 CE71T9 CE71TA CE71TB CE71TC CE71TD CE71TE CE71TG Total Gates 347K 524K 734K 845K 963K 1.110K 1.407K 1.559K 1.827K 2.088K 2.398K 3.040K 3.645K 5.152K Total Pads 144 176 208 224 240 256 288 304 328 352 376 424 464 552 Signals 128 156 178 192 206 220 248 264 264 312 312 360 360 264 Mixed-Signal Macros D/A Converters • 10-bit: 1 MS/s, 1.5 MS/s, 30 MS/s, 50 MS/s, 100 MS/s, 220 MS/s • 8-bit: 200 KS/s, 1 MS/s, 50 MS/s A/D Converters • 12-bit: 1 MS/s • 10-bit: 1 MS/s, 20 MS/s, 40 MS/s • 8-bit: 1 MS/s, 30 MS/s, 50 MS/s • 6-bit: 100 MS/s, 500 MS/s Multiplier Compiler • Multiplicand (m): 4 ≤ m ≤ 32 • Multiplier (n): 4 ≤ n ≤ 32 (even number only) Fujitsu Microelectronics, Inc. 0.25µm CMOS Technology PACKAGE AVAILABILITY No. of Pins 100 120 144 176 208 256 176 208 240 208 240 256 304 256 352 420 576 672 144 176 224 288 304 352 480 560 660 720 K1, K2 K2, K3 K3, K4, K8, T2, T3 K4, K5, T3, T4 T4, T5, T6, T7, T8, T9 T8, T9, TA, TB, TC J1, J2, K4, K5 J3, J4, J5, K5, K6, K7, K8 J4, J5, J6, K6, K7, K8 J3, J4, J5, J6, J7, J8, J9, K5, K6, K7, K8 T4, T5, T6, T7, T8, T9 J4, J5, J6, J7, J8, J9, JA, K6, K7, K8, T6, T7, T8, T9, TA J5, J6, J7, J8, J9, T7, T8, T9, TA, TB, TC J7, J8, J9, JA, JB, JC, JD, JE, JF, JG, TB, TC, TD, TE, TG J3, J4, T7, T8, T9, TA, TB J6, J7, J8, TB, TC, TD J8, J9, TD, TE JA, JB JC, JD T3 T3, T4 T5, T6, T7, T8, T9 T8, T9, TA, TB, TC L4, L5 L5, L6, L7 L6, L7 L7, L8, LB, LC L8, L9 L9, LA, LB, LC, LD, LE Frame Size Thin and Low Profile QFP Packages (0.4, 0.5 mm lead pitch) Shrink QFP Package (0.5 mm lead pitch) Heatspreader QFP Package (0.4, 0.5 mm lead pitch) Ball Grid Array (1.27 mm ball pitch) Fine-Pitch Ball Grid Array (0.75, 0.8 mm ball pitch) Tab Ball Grid Array (0.8, 1.0 mm ball pitch) Fujitsu Microelectronics, Inc. FUJITSU MICROELECTRONICS AMERICA, INC. Corporate Headquarters 1250 East Arques Avenue, Sunnyvale, California 94088-3470 Tel: (800) 866-8608 Fax: (408) 737-5999 E-mail: inquiry@fma.fujitsu.com Web Site: http://www.fma.fujitsu.com © 1999 Fujitsu Microelectronics, Inc. All company and product names are trademarks or registered trademarks of their respective owners. Printed in the U.S.A. ASIC-FS-20655-11/99