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FCU-022M101

FCU-022M101

  • 厂商:

    FUJITSU(富士通)

  • 封装:

  • 描述:

    FCU-022M101 - x-mGC, Electrical Transceiver for 10GBASE-CX4 - Fujitsu Component Limited.

  • 数据手册
  • 价格&库存
FCU-022M101 数据手册
x-mGC, Electrical Transceiver for 10GBASE-CX4 x-mGC Part Number: FCU-022M101 Features Compliant with IEEE802.3ak (10GBASE-CX4) X2 MSA Rev 1.0b Compatible module Industry standard electrical connector, microGiGaCNTM (I/O interface) XAUI Four channel electrical interface (Host side card edge) XAUI Standard 70 pin connector for host connection Front panel hot swap ability. X2 MSA Rev 1.0b compliant MDIO Link Alarm Status Interrupt (LASI) support Total Power consumption under 3.0 watt 20 meters over standard InfiniBand copper cable (24AWG) With media detect converter (o-mGC), up to 300 meters over standard multi mode fiber. No external clocks requirement – oscillator on board Description The x-mGC is a 10Gigabit Ethernet CX4 Module that designed to ease X2 MSA Rev 1.0b and it is an electrical module that incorporates the complete physical layer functionality from XAUI compliant 4 lanes x 3.125 Gb/s four differential electrical interface to the microGiGaCN™ CX4 compliant electrical interface. The x-mGC is plugged into a X2 hosting system and connects to a 4X InfiniBand cable. The control interface (MDIO)is also integrated. The x-mGC module includes 10Gb/s Ethernet transmitter and receiver ports. The host may control the x-mGC registers using XAUI interface as defined in the X2 MSA. The MUX/DEMUX, XAUI interface and MDIO management functions are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock. Fujitsu Component Limited Page 1 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 x-mGC Block Diagram XAUI IN Tx Re-timer XAUI IN CX4 Interface (MIDRO GiGaCN™ connector) Normalization XAUI Interface (70pin connector) XAUI OUT XAUI OUT Transceiver Management MDIO, MDC, Other signal Power (*1) Reference Clock Vcc Hot Swap Control Media Detect Figure 1: Functional Brock Diagram of x-mGC module (*1) In case of InfiniBand cable is connected, the power does not supply to cable, and if o-mGC is connected, a ground contact is changed Vcc for power supply to o-mGC by Media detect function. General Electrical Specification Interface: XAUI side; 70 pin SMT connector (See X2 MSA Rev1.0b, chapter 6.7) CX4 side; InfiniBand 4X connector (microGiGaCN™ , Fujitsu Component LTD. Patent) Differential signal rate: Tx and Rx each 3.125 Gb/s x 4 pair Impedance: 100 ohms differential, AC-coupled I/O Adaptable Cable and Link Length: ; InfiniBand 4X cable 20m over Supply Voltage: 3.3V and 1.5V Supports standard LVCMOS 1.2V host interface. Environmental Specification Operating case temperature: 0 - 70 degree (In an uniform air flow of 0.5 m/s.) Power consumption: 2.1 Watt Max Fujitsu Component Limited Page 2 of 12 InfiniBand Cable (< 20m) o-mGC + Optical fiber (< 300m (*1) ) 7 XGXS Rx x-mGC, Electrical Transceiver for 10GBASE-CX4 Figure 2: Top Level Brock Diagram of x-mGC Driver Fujitsu Component Limited Page 3 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 Technical specification Table 1: Transmitter characteristics Parameter Typical Units Notes Signal data rate Unit interval (UI) nominal Differential peak to peak output voltage Maximum Minimum Differential peak to peak output voltage difference Differential output return loss Differential output template Transition time (20-80%) Maximum Minimum Output jitter Random jitter Deterministic jitter Total jitter 3.125 320 1200 800 150 See figure 3 See figure 4 130 60 0.27 0.17 0.35 Gb/s ps mVp-p mVp-p mVp-p dB V ps ps UIpp UIpp UIpp +/-100ppm Maximum Minimum Frequency (MHz) 0 100 1,000 10,000 5 Loss (dB) 10 15 Figure 3: Transmit differential output return loss Fujitsu Component Limited Page 4 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 1.500 1.000 Normalized Amplitude (V) 0.500 0.000 -1.500 -1.000 -1.500 0.000 5.000 Time (UI) Figure 4: Normalized transmit template 10.000 Table 2: Receiver characteristics Parameter Typical 10-12 3.125 320 1200 See figure 3 Gb/s ps mVp-p dB Maximum 100ohm +/-100ppm Units Notes Bit error ratio Signal data rate Unit interval (UI) nominal Differential input amplitude Return loss differential (minimum) Fujitsu Component Limited Page 5 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 XAUI Interface Table 3: Driver characteristics Parameter Typical Units Notes Transmit data rate Unit interval nominal Differential amplitude Absolute output voltage limits Maximum Minimum Differential skew Differential output return loss Common mode output return loss Eye mask 3.125 320 1600 Gb/s ps mVp-p +/-100ppm Maximum 2.3 -0.4 15 10 6 See figure 5 V V ps dB dB Maximum Minimum Minimum Differential Amplitude mV) A2 A1 0 -A1 -A2 X1 X2 1-X2 1-X1 Time (UI) Figure 5: Table 4: Symbol X1 X2 Driver Template Driver Template Near-End Value 0.175 0.390 Far-End Value 0.275 0.4 Units UI UI A1 A2 400 800 100 800 mV mV Fujitsu Component Limited Page 6 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 Table 5: Receive Input parameters Parameter Typical Units Notes Transmit data rate Unit interval nominal Differential input amplitude Maximum Minimum Return loss Differential Common Input differential skew Jitter amplitude tolerance Peak-to-peak total jitter Peak-to-peak deterministic jitter 3.125 320 1600 200 10 6 75 0.65 0.47 Gb/s ps mVp-p mVp-p dB dB ps UIpp UIpp +/-100ppm Maximum Fujitsu Component Limited Page 7 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 x-mGC XAUI Pin out 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 GND GND RESERVED RESERVED GND TX LANE3TX LANE3+ GND TX LANE2TX LANE2+ GND TX LANE1TX LANE1+ GND TX LANE0TX LANE0+ GND GND GND RX LANE3RX LANE3+ GND RX LANE2RX LANE2+ GND RX LANE1RX LANE1+ GND RX LANE0RX LANE0+ GND RESERVED RESERVED GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 23 24 25 26 27 28 29 30 31 32 33 34 35 GND GND GND 5.0V 3.3V 3.3V APS (1.5V) APS (1.5V) LASI RESET VEND SPECIFIC TX ON/OFF RESERVED MOD DETECT VEND SPECIFIC VEND SPECIFIC MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 VEND SPECIFIC APS SET RESERVED APS SENSE APS (1.5V) APS (1.5V) 3.3V 3.3V 5.0V GND GND GND Top of Transceiver PCB Bottom of Transceiver PCB (as viewed through top) Toward Bezel Figure 6: x-mGC transceiver Electrical pad layout Fujitsu Component Limited Page 8 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 23 24 25 26 27 28 29 30 31 32 33 34 35 GND GND GND 5.0V 3.3V 3.3V APS (1.5V) APS (1.5V) LASI RESET VEND SPECIFIC TX ON/OFF RESERVED MOD DETECT VEND SPECIFIC VEND SPECIFIC MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 VEND SPECIFIC APS SET RESERVED APS SENSE APS (1.5V) APS (1.5V) 3.3V 3.3V 5.0V GND GND GND 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 GND GND RESERVED RESERVED GND TX LANE3TX LANE3+ GND TX LANE2TX LANE2+ GND TX LANE1TX LANE1+ GND TX LANE0TX LANE0+ GND GND GND RX LANE3RX LANE3+ GND RX LANE2RX LANE2+ GND RX LANE1RX LANE1+ GND RX LANE0RX LANE0+ GND RESERVED RESERVED GND GND Lower Row Upper Row Toward Bezel Figure 7: 10Gb host board pad layout Fujitsu Component Limited Page 9 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 Pin function definitions Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name GND GND GND 5.0V 3.3V 3.3V APS (1.5V) APS (1.5V) LASI RESET VEND SPECIFIC-signal detect TX ON/OFF RESERVED MOD DETECT VEND SPECIFIC-spare VEND SPECIFIC-spare MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 VEND SPECIFIC-not connected APS SET (1.5V) RESERVED APS SENSE APS (1.5V) APS (1.5V) 3.3V 3.3V 5.0V GND GND GND Dir Function Electrical Ground Electrical Ground Electrical Ground Power Power Power Adaptive Power Supply Adaptive Power Supply LVCMOS 1.2V Open Drain I LVCMOS 1.2V Open Drain Notes 1 1 1 2 2 2 2 2 3 3 Passive Reserved Passive Passive Passive Management Data IO LVCMOS 1.2V Open Drain 4 O I/O I I I I I I 3,4 3,4 3 3 3 3 3 Management Data Clock Port Address Bit 4 (Low = 0) Port Address Bit 3 (Low = 0) Port Address Bit 2 (Low = 0) Port Address Bit 1 (Low = 0) Port Address Bit 0 (Low = 0) Passive Passive Reserved Passive Connector to a 348 ohm resistor Adaptive Power Supply Adaptive Power Supply Power Power Power Electrical Ground Electrical Ground Electrical Ground 4 2 2 2 2 2 1 1 1 Table 6: XAUI Pin function 1 Fujitsu Component Limited Page 10 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 Pin No 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Name GND GND RESERVED RESERVED GND RX LANE0+ RX LANE0- Dir Function Electrical Ground Electrical Ground Reserved Reserved Electrical Ground Module XAUI Output Lane 0+ Module XAUI Output Lane 0Electrical Ground Module XAUI Output Lane 1+ Module XAUI Output Lane 1Electrical Ground Module XAUI Output Lane 2+ Module XAUI Output Lane 2Electrical Ground Module XAUI Output Lane 3+ Module XAUI Output Lane 3Electrical Ground Electrical Ground Electrical Ground Module XAUI Input Lane 0+ Module XAUI Input Lane 0Electrical Ground Module XAUI Input Lane 1+ Module XAUI Input Lane 1Electrical Ground Module XAUI Input Lane 2+ Module XAUI Input Lane 2Electrical Ground Module XAUI Input Lane 3+ Module XAUI Input Lane 3Electrical Ground Reserved Reserved Electrical Ground Electrical Ground Notes 1 1 GND RX LANE1+ RX LANE1- GND RX LANE2+ RX LANE2- GND RX LANE3+ RX LANE3- GND GND GND TX LANE0+ TX LANE0- GND TX LANE1+ TX LANE1- GND TX LANE2+ TX LANE2- GND TX LANE3+ TX LANE3- GND RESERVED RESERVED GND GND 1 5 5 1 5 5 1 5 5 1 5 5 1 1 1 5 5 1 5 5 1 5 5 1 5 5 1 1 1 Table 7: XAUI Pin function 2 Notes: 1) Ground connections are common for TX and RX. 2) All contacts of XAUI 70 pin connector are rated at 0.5A nominal. 3) 1.2V CMOS compatible. 4) MDIO and MDC timing must comply with IEEE802.3ae, Clause 45.3 5) XAUI output characteristics should comply with IEEE802.3ae Clause 47. Fujitsu Component Limited Page 11 of 12 x-mGC, Electrical Transceiver for 10GBASE-CX4 Package Design Mechanical design of x-mGC is shown as in following figure8. It is preliminary design and subject to change without notice, please check with us for the latest design. Datum B is physical hard stop for transceiver. (Part inside edge of slot on transceiver. Datum C is Number:FCU-022M101-0) Datum D is vertical center of transceiver PCB. Datum E is top surface of slot on transceiver. Note3) Lot code, the product part number, serial number and Fujitsu Component Limited logo are indicated. Note2) Unless otherwise specified, tolerance shall be +/-0.5mm. Note1) This module is X2-CX4 transceiver. (MID/Panel-mount type) Figure 8: x-mGC schematic drawing Fujitsu Component Limited Page 12 of 12
FCU-022M101 价格&库存

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