MB1507

September 1995 Edition 4.0a DATA SHEET MB1507 SERIAL INPUT PLL FREQUENCY SYNTHESIZER SERIAL INPUT PLL FREQUENCY SYNTHESIZER WITH 2.0GHZ PRESCALER The Fujitsu MB1507 is a single chip serial input PLL frequency synthesizer designed for Broadcast Satelite tuner and cellular telephone applications. It contains a 2.0 GHZ dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time. It operates supply voltage of 5.0V typ. and dissipates 18mA typ. of current realized through the use of Fujitsu’s unique U-ESBIC Bi-CMOS technology. • • • • • • • • • High operating frequency: fIN MAX=2.0GHZ (PIN MIN=–4dBm) Pulse swallow function: 128/129 or 256/257 Low supply current: ICC=18mA typ. Serial input 19-bit programmable divider consisting of: Binary 8-bit swallow counter: 0 to 255 Binary 11-bit programmable counter: 16 to 2047 Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter: 8 to 16383 1-bit switch counter (SW) Sets divide ratio of prescaler On-chip analog switch achieves fast lock up time 2types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump Wide operating temperature: –40°C to +85°C 16-pin Plastic Flat Package (Suffix: –PF) OSCIN OSCOUT VP VCC 1 2 3 4 TOP VIEW DO 5 6 7 8 12 11 10 9 FC LE Data Clock 16 15 14 13 ØR ØP fOUT BISW PLASTIC PACKAGE FPT-16P-M06 PIN ASSIGNMENT ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Power Supply Voltage Output Voltage Open-drain Voltage Output Current Storage Temperature NOTE: Symbol VCC VP VOUT VOOP IOUT TSTG Value –0.5 to +7.0 VCC to 10.0 –0.5 to VCC +0.5 –0.5 to 8.0 +10 –55 to +125 Unit V V V V mA GND LD fIN °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright © 1995 FUJITSU LIMITED and FUJITJU MICROELECTRONICS, INC. 1 MB1507 MB1507 BLOCK DIAGRAM OSCIN 1 CRYSTAL OSCILLATOR 16-BIT SHIFT REGISTER 16-BIT SHIFT REGISTER PHASE COMPARATOR 16 OR OSCOUT 2 15-BIT LATCH MONITOR FREQUENCY CHANGING CIRCUIT ANALOG SWITCH 15 OP VP 3 15-BIT LATCH 14 fOUT VCC 4 PROGRAMMABLE REFERENCE DIVIDER BINARY 14-BIT REFERENCE COUNTER S W CHARGE PUMP fr 13 BISW DO LE 12 FC DO 5 GND 6 11 LE LD 7 20-BIT SHIFT REGISTER 20-BIT SHIFT REGISTER CONTROL 1-BIT LATCH 10 Data 9 19-BIT LATCH 8-BIT LATCH 11-BIT LATCH Clock fIN 8 PRESCALER PROGRAMMABLE DIVIDER BINARY 8-BIT SWALLOW COUNTER BINARY 11-BIT PROGRAMMABLE COUNTER fp CONTROL CIRCUIT 2 MB1507 PIN DESCRIPTION Pin No. 1 2 Pin Name OSCIN OSCOUT I/O I O Description Oscillator input. Oscillator output. A crystal is placed between OSCIN and OSCOUT. Power supply input for charge pump and analog switch. Power supply voltage input. Charge pump output. The characteristics of charge pump is reversed depending upon FC input. Ground. Phase comparator output. Normally the output level is high level. While the phase difference of fr and fp exists, the output becomes low level. Prescaler input. The connection with VCO should be AC connection. Clock input for 20-bit shift register and 16-bit shift register. On rising edge of the clock shifts one bit of data into the shift registers. Binary serial data input. The last bit of the data is a control bit which specified destination of shift registers. When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 19-bit latch. Load enable input (with pull up resistor). When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch becomes ON state. Phase select input of phase comparator (with pull up resistor). When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC pin input signal controls fout pin (test pin) output level, fr or fp. Analog switch output. Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump output. Monitor pin of phase comparator input. fout pin outputs programmable reference divider output (fr) or programmable divider output (fp) depending upon FC pin input level. FC=H: It is the same as fr output level. FC=L: It is the same as fp output level. Outputs for external charge pump. The characteristics are reversed according to FC input. ∅P pin is N-channel open drain output. 3 4 5 6 VP VCC DO GND – – O – 7 LD O 8 fIN I 9 Clock I 10 Data I 11 LE I 12 FC I 13 BISW O 14 fOUT O 15 16 ØP ØR O O 3 MB1507 FUNCTIONAL DESCRIPTIONS SERIAL DATA INPUT Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15–bit programmable reference divider and 19–bit programmable divider, respectively. Binary serial data is input to Data pin. On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. Control data ”H” data is transferred into 15–bit latch. Control data ”L” data is transferred into 19–bit latch. THE DIVIDE RATIO SETTING fVCO=[(MxN)+A]xfOSC÷R fVCO: Output frequency of external voltage controlled oscillator (VCO) M: Preset modulus of external dual modulus prescaler (128 or 256) N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047) A: Preset divide ratio of binary 8-bit swallow counter (0≤A≤255, Afp fr=fp frfp fr=fp Z L fr