MB15F02PFV

FUJITSU SEMICONDUCTOR DATA SHEET DS04-21341-2E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F02 s DESCRIPTION The Fujitsu MB15F02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.0 GHz and a 500 MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 500 MHz prescaler can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 6.0 mA typ. at a supply voltage of 3.0 V. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result of this, MB15F02 is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile Communications). s FEATURES • High frequency operation • • • • • RF synthesizer : 1.2 GHz max. IF synthesizer : 500 MHz max. Low power supply voltage: VCC = 2.7 to 3.6V Very Low power supply current : ICC = 6.0 mA typ. (VCC = 3 V) Power saving function : IPS1 = IPS2 = 0.1 µA typ. Serial input 14–bit programmable reference divider: R = 5 to 16,383 Serial input 18–bit programmable divider consisting of: - Binary 7–bit swallow counter: 0 to 127 - Binary 11–bit programmable counter: 5 to 2,047 On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and low phase noise Wide operating temperature: Ta = −40 to 85°C Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pin BCC package (LCC-16P-M03) • • • s PACKAGES 16-pin, Plastic SSOP 16-pin, Plastic BCC (FPT-16P-M05) (LCC-16P-M03) MB15F02 s PIN ASSIGNMENTS SSOP-16 pin GNDRF OSCin GNDIF finIF VccIF LD/fout PSIF DoIF 1 2 3 4 16 15 14 Clock Data LE finRF VccRF XfinRF PSRF DoRF TOP 13 VIEW 5 12 6 7 8 11 10 9 (FPT-16P-M05) BCC-16 pin GNDRF OSCin GNDIF finIF VCCIF LD/fout PSIF 1 2 3 4 5 6 7 DoIF 16 Clock 15 14 13 Data LE finRF VCCRF XfinRF PSRF TOP VIEW 12 11 10 8 DoRF 9 (LCC-16P-M03) 2 MB15F02 s PIN DESCRIPTIONS Pin No. SSOP 1 2 3 4 5 BCC 16 1 2 3 4 Pin name GNDRF OSCin GNDIF finIF VccIF I/O – I – I – Ground for RF–PLL section. The programmable reference divider input. TCXO should be connected with a coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. The connection with VCO should be AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = ”H” ; outputs fout signal LDS bit = ”L” ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. Prescaler input pin for the RF-PLL. The connection with VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is ”H”, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-Prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a riging edge of the clock. Descriptions 6 5 LD/fout O 7 6 PSIF I 8 9 7 8 DoIF DoRF O O 10 9 PSRF I 11 12 13 10 11 12 XfinRF VccRF finRF I – I 14 13 LE I 15 14 Data I 16 15 Clock I 3 MB15F02 s BLOCK DIAGRAM VccIF 5 GNDIF 3 7 PSIF Intermittent mode control (IF–PLL) 3-bit latch LDS SWIF FCIF 7-bit latch 11-bit latch fpIF Binary 11-bit Binary 7-bit swallow counter programmable (IF–PLL) counter(IF–PLL) (IF–PLL) Phase comp. Charge Super pump charger (IF–PLL) 8 DoIF Prescaler finIF 4 16/17,32/33 2-bit latch T1 T2 14-bit latch Binary 14–bit programmable ref. counter(IF–PLL) frIF (IF–PLL) Lock Det. (IF–PLL) LDIF 2 OSCin AND OR frRF Selector LD frIF frRF fpIF fpRF T1 T2 Binary 14-bit programmable ref. counter(RF–PLL) LDRF 6 LD/fout 2-bit latch finRF 13 11 14-bit latch Prescaler 64/65, 128/129 LDS SWRF FCRF Binary 7-bit swallow counter (RF–PLL) (RF–PLL) (RF–PLL) Lock Det. XfinRF PSRF 10 Intermittent mode control (RF–PLL) Binary 11-bit programmable counter(RF–PLL) fpRF (RF–PLL) Phase comp. Charge Super pump (RF–PLL) charger 9 DoRF 3-bit latch 7-bit latch 11-bit latch LE 14 Schmitt circuit Latch selector Data 15 Clock 16 Schmitt circuit Schmitt circuit C N 1 C N 2 23-bit shift register 12 1 VCCRF GNDRF Note: SSOP-16 pin 4 MB15F02 s ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VI VO TSTG Rating –0.5 to +4.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 –55 to +125 Unit V V V °C Remark WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Input voltage Operating temperature Symbol VCC Vi Ta Value Min. 2.7 GND –40 Typ. 3.0 – – Max. 3.6 VCC +85 Unit V V °C Note WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always yse semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 5 MB15F02 s ELECTRICAL CHARACTERISTICS Parameter Symbol ICCIF*1 Power supply current ICCRF*2 Power saving current finIF Operating frequency finRF OSCin finIF Input sensitivity finRF OSCin Data, Clock, LE PSIF, PSRF Data, Clock, LE, PSIF, PSRF OSCin LD/fout Output voltage DoIF, DoRF High impedance cutoff current DoIF, DoRF LD/fout Output current DoIF, DoRF *1: *2: *3: *4: *5: 6 IpsIF IpsRF finIF*4 fin fOSC RF*4 Condition finIF = 500 MHz, fosc = 12 MHz finRF = 1200 MHz, fosc = 12 MHz VccIF current at PSIF =”L” VccRF current at PSIF/RF =”L” IF–PLL RF–PLL IF–PLL, 50 Ω load system (Refer to the TEST CIRCUIT) RF–PLL, 50 Ω load system (Refer to the TEST CIRCUIT) Schmitt trigger input Schmitt trigger input (VCC = 2.7 to 3.6 V, Ta = –40 to +85°C) Value Unit Min. Typ. Max. – – – – 50 100 3 –10 –10 0.5 VCC×0.7+0.4 – VCC×0.7 – –1.0 –1.0 0 –100 – – – – – – – – – – – – 2.5 3.5 0.1*3 0.1 – – – – – – – – – – *3 – mA – 10 10 500 1200 40 +2 +2 VCC VCC×0.3–0.4 VCC×0.3 +1.0 +1.0 +100 0 0.4 0.4 1.1 –1.0 – –6 mA 15 µA dBm dBm Vp-p V V MHz µA VfinIF VfinRF VOSC VIH VIL VIH VIL IIH*5 IIL*5 IIH IIL*5 VOH VOL Input voltage Input current µA V V µA mA VDOH VDOL IOFF IOH*5 IOL IDOH*5 IDOL Vcc = 3.0 V, IOH = –1 mA Vcc = 3.0 V, IOL = 1 mA Vcc = 3.0 V, IOH = –1 mA Vcc = 3.0 V, IOL = 1 mA Vcc = 3.0 V VOFF = GND to Vcc Vcc = 3.0 V Vcc = 3.0 V Vcc = 3.0 V, VDOH = 2.0 V, Ta = 25°C Vcc = 3.0 V, VDOL = 1.0 V, Ta = 25°C VCC–0.4 – VCC–0.4 – – – 1.0 –11 8 Conditions ; VccIF = 3.0 V, Ta = 25°C, in locking state. Conditions; VccRF = 3.0 V, Ta = 25°C, in locking state. Conditions ; Vcc = 3.0 V, fosc = 12.8 MHz (–2 dB), Ta = 25°C AC coupling. The minimum frequency is specified with a connecting coupling capacitor of 1000 pF. The symbol “–” means direction of current flow. MB15F02 s FUNCTIONAL DESCRIPTIONS The divide ratio can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC ÷ R fVCO: M: N: A: fOSC: R: (A < N) Output frequency of external voltage controlled ocillator (VCO) Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL) Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) Serial Data Input Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL sections, programmable reference dividers of IF/RF PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. Table1. Control Bit Control bit CN1 L H L H CN2 L L H H Destination of serial data The programmable reference counter for the IF-PLL. The programmable reference counter for the RF-PLL. The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL Shift Register Configuration Programmable Reference Counter LS 1 C N 1 2 C N 2 3 T 1 4 T 2 5 R 1 6 R 2 7 R 3 8 R 4 9 R 5 Data 10 R 6 11 R 7 12 R 8 13 R 9 14 R 10 15 R 11 16 R 12 17 R 13 MS 18 R 14 CNT1, 2 : Control bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) T1, 2 : Test purpose bit NOTE: Start data input with MSB first. [Table. 1] [Table. 2] [Table. 3] 7 MB15F02 Programmable Counter LS 1 C N 1 2 C N 2 3 L D S 4 S W 5 F C 6 A 1 7 A 2 8 A 3 9 A 4 Data 10 A 5 11 A 6 12 A 7 13 N 1 14 N 2 15 N 3 16 N 4 17 N 5 18 N 6 19 N 7 20 N 8 21 N 9 22 N 10 MS 23 N 11 CNT1, 2 N1 to N14 A1 to A7 SW : Control bit : Divide ratio setting bits for the programmable counter (5 to 2,047) : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bit for the prescaler (16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL) FC : Phase control bit for the phase detector LDS : LD/fout signal select bit NOTE: Start data input with MSB first. [Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 8] Table2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio (R) 5 6 ⋅ 16383 R 14 0 0 ⋅ 1 R 13 0 0 ⋅ 1 R 12 0 0 ⋅ 1 R 11 0 0 ⋅ 1 R 10 0 0 ⋅ 1 R 9 0 0 ⋅ 1 R 8 0 0 ⋅ 1 R 7 0 0 ⋅ 1 R 6 0 0 ⋅ 1 R 5 0 0 ⋅ 1 R 4 0 0 ⋅ 1 R 3 1 1 ⋅ 1 R 2 0 1 ⋅ 1 R 1 1 0 ⋅ 1 Note: • Divide ratio less than 5 is prohibited. Table.3 Test Purpose Bit Setting T 1 L H L H T 2 L L H H LD/fout pin state Outputs frIF. Outputs frRF. Outputs fpIF. Outputs fpRF. 8 MB15F02 Table.4 Binary 11-bit Programmable Counter Data Setting Divide ratio (N) 5 6 ⋅ 2047 N 11 0 0 ⋅ 1 N 10 0 0 ⋅ 1 N 9 0 0 ⋅ 1 N 8 0 0 ⋅ 1 N 7 0 0 ⋅ 1 N 6 0 0 ⋅ 1 N 5 0 0 ⋅ 1 N 4 0 0 ⋅ 1 N 3 1 1 ⋅ 1 N 2 0 1 ⋅ 1 N 1 1 0 ⋅ 1 Note: • Divide ratio less than 5 is prohibited. Table.5 Binary 7-bit Swallow Counter Data Setting Divide ratio (A) 0 1 ⋅ 127 A 7 0 0 ⋅ 1 A 6 0 0 ⋅ 1 A 5 0 0 ⋅ 1 A 4 0 0 ⋅ 1 A 3 0 0 ⋅ 1 A 2 0 0 ⋅ 1 A 1 0 1 ⋅ 1 Note: • Divide ratio (A) range = 0 to 127 Table. 6 Prescaler Data Setting SW = ”H” Prescaler divide ratio IF-PLL RF-PLL 16/17 64/65 SW = ”L” 32/33 128/129 9 MB15F02 Table. 7 Phase Comparator Phase Switching Data Setting FCIF/RF = H fr > fp fr = fp fr < fp VCO polarity H Z L (1) FCIF/RF = L DoIF/RF L Z H (2) VCO Output Frequency (1) Note: • Z = High–impedance • Depending upon the VCO and LPF polarity, FC bit should be set. VCO Input Voltage (2) Table. 8 LD/fout Output Select Data Setting LDS H L LD/fout output signal fout (frIF/RF, fpIF/RF) signals LD signal Serial Data Input Timing Data MSB LSB Clock LE t1 t7 t2 t3 t4 t5 t6 On rising edge of the clock, one bit of the data is transferred into the shift register. Parameter t1 t2 t3 t4 Min. 20 20 30 30 Typ. – – – – Max. – – – – Unit ns ns ns ns Parameter t5 t6 t7 Min. 100 20 100 Typ. – – – Max. – – – Unit ns ns ns 10 MB15F02 s PHASE DETECTOR OUTPUT WAVEFORM frIF/RF fpIF/RF tWU LD (FC bit = High) DoIF/RF Z tWL H L (FC bit = Low) DoIF/RF Z LD Output Logic Table IF–PLL section RF–PLL section LD output H L L L Locking state / Power saving state Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state Unlocking state Locking state / Power saving state Unlocking state Note: • Phase error detection range = −2π to +2π • Pulses on DoIF/RF signals are output to prevent dead zone. • LD output becomes low when phase error is tWU or more. • LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCin input frequency as follows. tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz 11 MB15F02 s POWER SAVING MODE (INTERMITTENT MODE CONTROL CIRCUIT) Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can be limited to 10µA (typ.). Setting PS pin to High, power saving mode is released so that the device works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. Thus keeping the loop locked. Allow 1 µs after frequency stabilization on power-up for exiting the power saving mode (PS: L to H) Serial data can be entered during the power saving mode. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10µA per one PLL section. At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF’s time constant. As a result of this, VCO’s frequency is kept at the locking frequency. Note: PS pin must be set “L” at Power-ON. The power saving mode should be released at 1 µs after the power supply becomes stable. PSIF L H L H PSRF L L H H IF-PLL counters OFF ON OFF ON RF-PLL counters OFF OFF ON ON OSC input buffer OFF ON ON ON ON V CC Clock Data LE PS i1j i2j i3j (1) PS = L (power saving mode) at Power-ON. (2) Set serial data after power supply remains stable. (3) Release saving mode (PS: LfiH) after setting serial data. 12 MB15F02 s TYPICAL CHARACTERISTICS Input sensivity of FIN (IF) vs. Input frequency [Ta = +25°C] +10 0 Vfin (dBm) x x Main. counter div. ratio=1032 Swallow=“ON”, RF: Active fosc=19.8 MHz (–2dB) SPEC x x x x x x x x –10 –20 –30 –40 0 500 x x VCC=2.7 V VCC=3.0 V VCC=3.6 V 1000 fin (MHz) 1500 2000 Input sensivity of FIN (RF) vs. Input frequency [Ta = +25°C] +10 0 Main. counter div. ratio=4104 Swallow=“ON”, IF: Active fosc=19.8 MHz (–2dB) x SPEC Vfin (dBm) –10 x x x x x x x x x –20 –30 –40 0 1000 x VCC=2.7 V VCC=3.0 V VCC=3.6 V 2000 fin (MHz) 3000 (Continued) 13 MB15F02 (Continued) Input sensivity of OSC (IF) vs. Input frequency [Ta = +25°C] +10 0 Vosc (dBm) –10 –20 –30 –40 x x x x x x x x Ref. counter div. ratio=2048 RF: fin = 1005 MHz (VCO) IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN SPEC x x x VCC=2.7 V VCC=3.0 V VCC=3.6 V –50 –60 0 50 100 fosc (MHz) 150 200 Input sensivity of OSC (RF) vs. Input frequency [Ta = +25°C] +10 0 Vosc (dBm) –10 –20 –30 –40 –50 –60 0 50 100 fosc (MHz) 150 200 x x x x x x x Ref. counter div. ratio=2048 RF: fin = 1005 MHz (VCO) IF: fin = 270 MHz (VCO), Xfin = 1000 PF Pull DOWN x x x SPEC x x x VCC=2.7 V VCC=3.0 V VCC=3.6 V 14 MB15F02 (Continued) Do output Current (IF) Conditions: Ta = +25°C VCC= 2.7, 3.0, 3.6 V 5.000 VOH (V) .5000 /div 3.6 V 3.0 V VCC = 2.7 V • DO = VCC = 1 V • OSCin = 12.8 MHz (+10 dB) • fin [IF/RF] = “H” (= VCC) .0000 .0000 2.500/div IOH (mA) (mA) –25.00 5.000 VOL(V) .5000 /div VCC = 2.7 V 3.0 V 3.6 V • DO = 1 V • fin [IF] = 500 MHz (–10 dB) • OSCin, fin [RF] = “H” (= VCC) .0000 .0000 2.500/div IOL (mA) (mA) 25.00 (Continued) 15 MB15F02 (Continued) Do output Current (RF) Conditions: Ta = +25°C VCC= 2.7, 3.0, 3.6 V 5.000 VOH (V) .5000 /div 3.6 V 3.0 V VCC = 2.7 V • DO = VCC = 1 V • OSCin = 12.8 MHz (+10 dB) • fin [IF/RF] = “H” (= VCC) .0000 .0000 2.500/div IOH (mA) (mA) –25.00 5.000 VOL(V) .5000 /div VCC = 2.7 V 3.0 V 3.6 V • DO = 1 V • fin [RF] = 1.2 GHz (–10 dB) • OSCin, fin [IF] = “H” (= VCC) .0000 .0000 2.500/div IOL (mA) (mA) 25.00 16 MB15F02 (Continued) Input Impedance 3: 26.805 Ω –178.48 Ω 2.2294 pF 400.000 000 MHz 1: 778.28 Ω –824.12 Ω 50 MHz 87.25 Ω –357.03 Ω 200 MHz 19.305 Ω –138.94 Ω 500 MHz 2: finIF Pin 1 3 4 2 4: 4: 11.686 Ω –40.426 Ω 3.2808 pF 1 200.000 000 MHz 1: 312.84 Ω –627.28 Ω 100 MHz 30.344 Ω –183.38 Ω 400 MHz 12.746 Ω –81 Ω 800 MHz 2: finRF Pin 1 3: 2 4 3 2: 316.75 Ω –5.9348 kΩ 2.6817 pF 10.000 000 MHz 1: 7.401 kΩ –20.347 kΩ 3 MHz 116.75 Ω –3.0649 kΩ 20 MHz 083.88 Ω –1.5473 kΩ 40 MHz 3: OSCin Pin 2 1 34 4: 17 MB15F02 s REFERENCE INFORMATION Typical plots measured with the test circuit are shown below. Each plot shows lock up time, phase noise and reference leakage. Test Circuit S.G OSCin Do fin LPF • • • • • fvco = 1018 MHz Kv = 20 MHz/v fr = 200 kHz fosc = 13 MHz LPF: 15 kΩ 2.2 kΩ Spectrum Analyzer VCO 2000 pF 330 pF 20000 pF PLL Lock Up Time = 440 µs (1005.000 MHz → 1031.000 MHz, within ± 1kHz) ∆ MKr x : 439.90929 µs y : 25.99986 MHz 30.00300 MHz RBW 300 Hz SAMPLE VBW 300 Hz A evts N/A PLL Phase Noise @ within loop band = 75.5 dBc/Hz REF –10.0 dBm 10dB/ ATT 10 dB 1.000 kHz/div 29.99800 MHz 10.2449 µs 1.9902449 ms SPAN 50.0 kHz CENTER 1.0180000 GH z PLL Lock Up Time = 440 µs (1031.000 MHz → 1005.000 MHz, within ± 1kHz) ∆ MKr x : 440.02236 µs y : –26.00006 MHz 30.00300 MHz RBW 10 kHz SAMPLE VBW 10 kHz REF 10dB/ PLL Reference Leakage @ 200 kHz offset = 71.4 dBc –10.0 dBm ATT 10 dB 1.00 kHz/div 29.99800 MHz 10.1378 µs 1.9901378 ms SPAN 1.00 MHz CENTER 1.01800 GHz 18 MB15F02 s TEST CIRCUIT (PRESCALER INPUT/PROGRAMMABLE REFERENCE DIVIDER INPUT SENSITIVITY TEST) fout Oscilloscope VccIF 0.1µF 1000pF P.G 50Ω 1000pF P.G 50Ω 8 7 6 5 4 3 2 1 GND MB15F02 9 10 11 12 13 14 15 16 P.G 1000pF 50Ω VccRF 1000pF 0.1µF Controller (divide ratio setting) Note: SSOP-16 pin 19 MB15F02 s APPLICATION EXAMPLE OUTPUT VCO 3V from controller 1000 pF 0.1µF 1000 pF LPF Clock Data 16 15 LE 14 finRF 13 VccRF 12 XfinRF 11 PSRF 10 DoRF 9 MB15F02 1 2 3 4 5 6 7 8 GNDRF OSCIN GNDIF finIF VccIF LD/fout PSIF DoIF 3V 1000 pF 1000 pF 0.1µF TCXO Lock Det. OUTPUT VCO LPF Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). Note: SSOP-16 pin 20 MB15F02 s ORDERING INFORMATION Part number MB15F02 PFV MB15F02 PV Package 16 pin, Plastic SSOP (FPT-16P-M05) 16 pin, Plastic BCC (LCC-16P-M03) Remarks 21 MB15F02 s PACKAGE DIMENSIONS 16 pins, Plastic SSOP (FPT-16P-M05) * 5.00±0.10(.197±.004) * : These dimensions do not include resin protrusion. 1.25 –0.10 +.008 .049 –.004 +0.20 0.10(.004) INDEX *4.40±0.10 (.173±.004) 6.40±0.20 (.252±.008) 5.40(.213) NOM 0.65±0.12 (.0256±.0047) 0.22 –0.05 +.004 .009 –.002 +0.10 "A" 0.15 –0.02 +.002 .006 –.001 +0.05 Details of "A" part 0.10±0.10(.004±.004) (STAND OFF) 4.55(.179)REF 0 10° 0.50±0.20 (.020±.008) C 1994 FUJITSU LIMITED F16013S-2C-4 Dimensions in mm (inches) (Continued) 22 MB15F02 16-pin, Plastic BCC (LCC-16P-M03) 14 4.55±0.10 (.179±.004) 0.80(.032)MAX 9 3.40(.134)TYP 9 (Mounting height) 0.65(.026)TYP 14 0.40±0.10 (.016±.004) 4.20±0.10 (.165±.004) 45˚ 3.25(.128) TYP "A" "B" 1.55(.061)TYP 0.80(.032) TYP 1 E-MARK 6 0.40(.016) 0.085±0.040 (.003±.002) (STAND OFF) 6 0.325±0.10 (.013±.004) 1.725(.068) TYP 1 Details of "A" part 0.75±0.10 (.030±.004) 0.05(.002) Details of "B" part 0.60±0.10 (.024±.004) 0.40±0.10 (.016±.004) 0.60±0.10 (.024±.004) C 1996 FUJITSU LIMITED C16014S-1C-1 Dimensions in mm (inches) 23 MB15F02 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9704 © FUJITSU LIMITED Printed in Japan 24