MB15U10PFV

FUJITSU SEMICONDUCTOR DATA SHEET DS04-21339-2E ASSP Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler MB15U10 s DESCRIPTION The Fujitsu MB15U10 is a dual serial input phase-locked loop (PLL) frequency synthesizer and is ideally suitable for mobile communications such as cellular phones. The MB15U10 has two PLL frequency synthesizer circuits on a single chip: one for transmission and the other for reception (PLL1 and PLL2). It can operate from a +2.6V to 5.5V supply. Fujitsu’s advanced technology achieves an Icc of 7 mA (typical) as well as 10 µA (max.) at power saving mode. s FEATURES • • • • Two PLLs’ for transmission/reception Low current consumption : ICC = 7 mA typ. at 3 V Power saving function : IPS = 10 µA max. Divide ratio setting with serial data input : Binary 12-bit reference counter:6 to 4,095 Binary 17-bit main counter: 1,024 to 131,071 *Main counters can be programmed individually each other. On-chip constant current source charge pumps Adjustable charge pump output current with an external resistor Lock detection function Phase matching circuit helps fast intermittent operation Plastic 20-pin SSOP (shrink small outline) package • • • • • s PACKAGE 20-pin, Plastic SSOP (FPT-20P-M03) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1 MB15U10 s PIN ASSIGNMENT (Top View) P1/fp1 P2/fp2 Do1 VDD1 PS fin1 DGND OSCin P3/fr2 OSCout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ISET P0/LD VP Do2 AGND fin2 VDD2 LE Data Clock (FPT-20P-M03) 2 MB15U10 s PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin name P1/fp1 P2/fp2 Do1 VDD1 PS fin1 DGND OSCin P3/fr2 OSCout Clock Data LE VDD2 fin2 AGND Do2 VP P0/LD ISET Descriptions Data output / fp1 monitoring output (Open drain output) Data output / fp2 monitoring output (Open drain output) Charge pump output (PLL1) Power supply for digital blocks (PLL1) Power saving mode control (input ”L” : power saving mode) RF input (PLL1) Ground for digital blocks Crystal oscillator or TCXO input Data output / fr2 monitoring output (Open drain output) Crystal oscillator output (CMOS output) Clock input Data input Load enable of serial input data (input ”H” : Data is shifted into a latch.) Power supply for digital blocks (PLL2) RF input (PLL2) Ground for the charge pumps Charge pump output (PLL2) Power supply for charge pump Data output / lock detector output (Open drain output) Output is selected by ”OLA” and ”OLB” bits in a serial data Charge pump output current adjustment (A resistor is connected.) 3 MB15U10 s BLOCK DIAGRAM VDD1 4 18 VP Power saving circuit PS1 17-bit latch (comparisonal division) Phase comparator Charge pump ISET 3 Do1 fin1 6 Main counter (binary 17-bit) fp1 CR1 PS 5 LD1 PLL1 OSCin 8 Crystal oscillator OSCout 10 fr1 Reference counter SR +1/+2 TS fr2 P0 LD2 OLA, B Selector 19 P0/LD 14-bit latch (referencial division) fr2 9 P3/fr2 Selector fp1 1 P1/fp1 2 P2/fp2 Power saving circuit PS2 17-bit latch (comparisonal division) fp2 fin2 15 Main counter (binary 17-bit) fp2 Phase comparator Charge pump 17 Do2 PLL2 P0 P1, 2, 3 CR2 OLA, B CR1, 2 20 ISET 10-bit latch LE 13 Data 12 Shift register (21-bit) Clock 11 14 7 Latch selector 16 VDD2 DGND AGND 4 MB15U10 s ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Output voltage Output current Open drain withstand voltage Storage temperature Symbol VDD1, 2 VP VO IO VOOP Tstg Rating –0.3 to +6.0 VDD to 6.0 –0.3 to VDD +0.3 ±10 –0.5 to 7.0 –55 to +125 Unit V V V mA V °C Remark Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. s RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD1, VDD2 VP VI Ta Value Min 2.6 VDD GND –30 Typ – – – – Max 5.5 6.0 VDD +85 Unit V V V °C Remark Power supply voltage Input voltage Operating temperature Notes: To protect against damage by electrostatic discharge, note the following handling precautions: – Store and transport devices in conductive containers. – Use properly grounded workstations, tools, and equipment. – Turn off power before inserting or removing this device into or from a socket. – Protect leads with conductive sheet, when transporting a board mounted device. 5 MB15U10 s ELECTRICAL CHARACTERISTICS Ta = 25°C Parameter Power supply current (IDD1 + IDD2) Stand by current Operating frequency VDD1, 2 fin1, 2 OSCin fin1, 2 Input sensitivity fin1, 2 OSCin High-level input voltage Low-level input voltage High-level input current Low-level input current Input current Low-level output voltage Set output voltage High-impedance cut off current Data, Clock, LE, PS Data, Clock, LE, PS OSCin P0 to P3 ISET DO, P0 to P3 DO1, 2 Output current DO1, 2 P0 to P3 Symbol Value Min – – – 3 Typ 7.0 11.0 – – 12.8 – – – – – – – – – 1.2 – 1.9 1.9 0.96 0.96 – Max 9.0 13.5 10 1100 35 +1 +1 – – VDD × 0.3 1.0 – 100 0.4 – 1.1 2.4 2.4 1.2 1.2 – Unit mA mA µA MHz MHz dBm dBm Vp-p V V µA µA µA V V µA mA mA mA mA mA *1 *2 Condition IDD IPS fin* 90 3 –13 –7 0.5 VDD × 0.7 – – –1.0 –100 – – – 1.4 1.4 0.7 0.7 1.0 fOSC Vfin Vfin VOSC VIH VIL IIH IIL IOSC VOL VSET IOFF IDOH1*4 IDOL1*4 IDOH0 IDOL0 IOL 50Ω, Vcc = 2.6 to 3.5V 50Ω, Vcc = 3.5 to 5.5V Open drain output RSET = 5kΩ to 60kΩ RSET = 7kΩ connected. CR1, 2 bits = ”1” VDD = 3.0V, VP = 5.0V RSET = 7kΩ connected. CR1, 2 bits = ”0” VDD = 3.0V, VP = 5.0V Open drain Note: *1 ; fIN = 1.1 GHz, OSCIN = 12.8 MHz, VDD = 3.0 V. In locked state. *2 ; fIN = 1.1 GHz, OSCIN = 12.8 MHz, VDD = 5.0 V. In locked state. *3 ; AC coupling with a 1000 pF capacitor connected. *4 ; The symbol “–” (minus) means direction of current flow. 6 MB15U10 s FUNCTIONAL DESCRIPTIONS Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider, programmable divider (PLL1) and programmable divider (PLL2) separately by means of address setting. Binary serial data is entered via the Data pin. One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched. a) Serial data input format (MSB) 1 X 2 X 3 X 4 P 0 5 O L A M A 12 S R M B 12 6 O L B M A 11 R 11 M B 11 7 C R 1 M A 10 R 10 M B 10 8 C R 2 M A 9 R 9 M B 9 9 X 10 X 11 P S 1 M A 6 R 6 M B 6 Direction of data input (LSB) 16 X 17 X 18 0 19 0 20 0 21 1 12 P S 2 M A 5 R 5 M B 5 13 P 3 14 P 2 15 P 1 M A 16 0 M A 15 0 M A 14 0 M A 13 T S M B 13 M A 8 R 8 M B 8 M A 7 R 7 M B 7 M A 4 R 4 M B 4 M A 3 R 3 M B 3 M A 2 R 2 M B 2 M A 1 R 1 M B 1 M A 0 R 0 M B 0 0 1 0 0 0 1 0 1 M B 16 M B 15 M B 14 0 1 1 0 0 Auxiliary bit for test (no need at ordinary use) 0 0 0 Data setting MA0 to 16 MB0 to 16 R0 to 11 SR P0 to 3 OLA, B CR1, 2 PS1, 2 TS X 0 : : : : : : : : : : : Divide ratio setting bits of the main counter (PLL1) Divide ratio setting bits of the main counter (PLL2) Divide ratio setting bits of the reference counter Divide ratio select bit of reference frequency (PLL1 and PLL2) Setting bits of P0 to P3 output pins Select bits of P0/LD pin output Select bits of charge pump output current Power saving mode control bits Test bits (Set ”0” at ordinary use.) Dummy bits (Set ”0” or ”1”.) Set ”0” Address [ See Table 1 ] [ See Table 2 ] [ See Table 3 ] [ See Table 4 ] [ See Table 5 ] [ See Table 6 ] [ See Table 7 ] [ See Table 8 ] [ See Table 9 ] Note: Start data input with MSB first. 7 MB15U10 b) Data setting description • Table 1 : MA0 to MA16 : Divide ratio of the binary 17-bit main counter (PLL1) Divide Ratio (MA) 1024 1025 • M A 16 0 0 • M A 15 0 0 • M A 14 0 0 • M A 13 0 0 • M A 12 0 0 • M A 11 0 0 • M A 10 1 1 • M A 9 0 0 • M A 8 0 0 • M A 7 0 0 • M A 6 0 0 • M A 5 0 0 • M A 4 0 0 • M A 3 0 0 • M A 2 0 0 • M A 1 0 0 • M A 0 0 1 • Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071) • Table 2 : MB0 to MB16 : Divide ratio of the binary 17-bit main counter (PLL2) Divide Ratio (MB) 1024 1025 • M B 16 0 0 • M B 15 0 0 • M B 14 0 0 • M B 13 0 0 • M B 12 0 0 • M B 11 0 0 • M B 10 1 1 • M B 9 0 0 • M B 8 0 0 • M B 7 0 0 • M B 6 0 0 • M B 5 0 0 • M B 4 0 0 • M B 3 0 0 • M B 2 0 0 • M B 1 0 0 • M B 0 0 1 • Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071) • Table 3 : R0 to R11 : Divide ratio of the binary 12-bit reference counter Divide Ratio (R) 6 7 • R 11 0 0 • R 10 0 0 • R 9 0 0 • R 8 0 0 • R 7 0 0 • R 6 0 0 • R 5 0 0 • R 4 0 0 • R 3 0 0 • R 2 1 1 • R 1 1 1 • R 0 0 1 • Note: • Divide ratios less than 6 are prohibited. (Divide ratio = 6 to 4,095) • Table 4 : Divide ratio select bit of reference frequency (PLL1 and PLL2) SR 0 1 Divide ratio of reference frequency (PLL1) R R Divide ratio of reference frequency (PLL2) R 2R Note: R = Programmed value with R0 to R11 bits 8 MB15U10 • Table 5 : P0 to P3 ; P0 to P3 outputs control PX bit 0 1 Notes: X = 0 to 3 • Table 6 : OLA, OLB ; 19-pin output selection OLA 0 0 1 1 OLB 0 1 0 1 19-pin output P0 signal Lock detect signal (PLL2) Lock detect signal (PLL1) Lock detect signal (PLL1 and PLL2) PX output (19, 1, 2, 9 pins) ON (”L”) OFF (”Z”) • Table 7 : CR1, CR2 ; Charge pump output current selection CR1, 2 0 1 Charge pump output current IDO 2IDO Notes: PLL1 and PL2 can be controlled individually. • Table 8 : PS ; Power saving control PS1, 2 0 1 Operating mode Power saving mode Operation Notes: PLL1 and PL2 can be controlled individually. • Table 9 : TS ; Test bit (Set to "0" at ordinary use.) TS 0 1 1-pin Output P1 signal Outputs fp1 2-pin Output P2 signal Outputs fp2 9-pin Output P3 signal Outputs fp3 Notes: Reference frequency and comparison frequency can be monitored via P1 to P3 pins. 9 MB15U10 Serial Data Input Timing • t1 (≥ 20 ns), t2 (≥ 20 ns), t3 (≥ 50 ns), t4 (≥ 50 ns), t5 (≥ 20 ns), t6 (≥ 1000 ns) Data MSB LSB Clock LE t1 t2 t3 t4 t5 t6 Note: One bit of data is shifted into the shift register on the rising edge of the clock. 10 MB15U10 s TEST CIRCUIT (for Measuring fin Input Sensitivity) VDD2 7kΩ 1000pF S.G 50Ω 20 19 18 17 16 15 14 0.1µF Controller 13 12 11 50Ω S.G 1000pF Oscilloscope Oscilloscope VDD 1 2 3 VDD1 0.1µF 4 5 6 7 8 9 X’tal 10 2kΩ 2kΩ 0.1µF 11 MB15U10 s TYPICAL CHARACTERISTICS Do Output Current Conditions : Ta = +25°C VDD = 3 V Vp = 5 V ISETR = 5 k, 7 k, 15 k, 60 k 7 k Ω 5 k Ω 60 60 15 kkk ΩΩΩ 7 5 15 k kk Ω ΩΩ CR = “H” CR = “L” 7 k Ω 5 k Ω 60 60 15 7 5 15 k k kkk k Ω Ω Ω ΩΩ Ω 5.0 4.0 VOH (V) VOL (V) 0 –1.0 –2.0 IOH (mA) fin Input Sensitivity +10 0 Vfin (dBm) –10 –20 × × 5.0 4.0 3.0 2.0 1.0 0 –3.0 –4.0 0 1.0 2.0 IOL (mA) [Ta = +25°C] × × × 3.0 2.0 1.0 0 3.0 4.0 SPEC × × × × × × × × –30 × × × × × × × :VDD = 2.6 V • :VDD = 3.0 V :VDD = 3.6 V 1500 2000 [Ta = +25°C] 0 500 1000 fin (MHz) +10 0 –10 –20 –30 –40 0 500 1000 fin (MHz) 1500 2000 :VDD = 4.5 V :VDD = 5.0 V :VDD = 5.5 V SPEC Vfin (dBm) (Continued) 12 MB15U10 (Continued) OSCin Input Sensitivity [Ta = +25°C] +10 0 VOSC(dBm) –10 –20 –30 –40 0 50 100 fOSC (MHz) 150 200 × :VDD = 2.6 V • :VDD = 3.0 V :VDD = 3.6 V :VDD = 4.5 V :VDD = 5.0 V :VDD = 5.5 V SPEC 13 MB15U10 s APPLICATION EXAMPLE Output LPF VCO VDD2 VP 1000pF R1 Lock Det ISET 20 P0/LD 19 VP 18 Do2 17 AGND 16 fin2 15 14 VDD2 LE 13 Data 12 0.1µF 0.1µF Controller Clock 11 MB15U10 1 P1/fp1 2 P2/fp2 3 Do1 VDD1 4 VDD1 5 PS 6 fin1 7 DGNG 8 OSCIN 9 P3/fr2 10 OSCOUT X’tal 1000pF 0.1µF C1 C2 Controller Output LPF VCO R1 C1, C2 Clock, Data, LE PS : Values(5 to 60 kΩ) are used to determine the output current for charge pump. : Determined by the crystal oscillator : Insert pull down/pull up resistors to prevent oscillation when the terminals are left open. : When not in use, insert a pull up resistor with respect to the power supply. 14 MB15U10 s REFERENCE INFORMATION Typical plots measured with the test circuit are shown below. Each plots shows lock up time, phase noise, and reference leakage. • fVCO • KV • fr • fOSC • LPF = 836.490 MHz = 12 MHz/V = 30 kHz = 15.36 MHz 9.1 kΩ fin 5.1 kΩ 0.033 µF Spectrum Analyzer VCO 0.33 µF 0.01 µF Test Circuit S.G. OSCin Do LPF PLL Lock Up Time = 11.0 ms (824.01 MHz → 848.97 MHz, within ±800 Hz) ∆ Mkr x: y: 10.99990891 ms 24.961502 MHz A evts N/A ∆ Mkr PLL Lock Up Time = 10.6 ms (848.97 MHz → 824.01 MHz, within ±800 Hz) x: y: 10.59999719 ms –24.960989 MHz A evts N/A 30.00150 MHz 30.00150 MHz 500.0 Hz/div 500.0 Hz/div 29.99900 MHz 100.2131 µs 59.9002131 ms 29.99900 MHz 100.1353 µs 59.9003853 ms ∆ Mkr x: y: 10.99990891 ms 24.961502 MHz A evts N/A ∆ Mkr x: y: 10.59999719 ms –24.960989 MHz A evts N/A 50.00000 MHz 60.00000 MHz 10.00000 MHz/div 10.00000 MHz/div 0 Hz 100.2131 µs 59.9002131 ms 10.00000 MHz 100.1353 µs 59.9003853 ms (Continued) 15 MB15U10 (Continued) PLL Phase Noise (TX mode) @±1 kHz offset at 836.49 MHz = 75 dBc/Hz REF 0.0 dBm 10 dB/ ATT 10 dB MKR 10 dB/ REF 0.0 dBm PLL Reference Leakage (TX mode) @±30 kHz offset at 836.49 MHz = 82 dBc ATT 10 dB MKR RBW 100 Hz VBW 100 Hz RBW 1kHz VBW 1kHz SWP 3 s SPAN 5.00 kHz CENTER 836.49000 MHz SWP 800 ms SPAN 150 kHz CENTER 836.490 MHz fin Input Impedance 1: 20.93 Ω –130.75 Ω 500 MHz 2: 11.281 Ω –71.824 Ω 800 MHz 3: 11.871 Ω –51.166 Ω 1 GHz 4: 11.627 Ω –42.119 Ω 3.4352 pF 1.1 GHz 1 3 2 4 OSCin Input Impedance 1: 1.5699 kΩ –2.6509 kΩ 10 MHz 2: 889.63 Ω –2.0951 kΩ 15 MHz 4 1 3 2 3: 537.31 Ω –1.6434 kΩ 20 MHz 4: 342.19 Ω –1.3733 kΩ 4.6357 pF 25 MHz 16 MB15U10 s ORDERING INFORMATION Part number MB15U10PFV Package 20pin, Plastic SSOP (FPT-20P-M03) Remarks 17 MB15U10 s PACKAGE DIMENSION 20 pin, Plastic SSOP (FPT-20P-M03) *: These dimensions do not include resin protrusion. * 6.50±0.10(.256±.004) 1.25 –0.10 +.008 .049 –.004 +0.20 (Mounting height) 0.10(.004) INDEX *4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) 5.40(.213) NOM 0.65±0.12 (.0256±.0047) 0.22 –0.05 +.004 .009 –.002 +0.10 "A" 0.15 –0.02 +.002 .006 –.001 +0.05 Details of "A" part 0.10±0.10(.004±.004) (STAND OFF) 5.85(.230)REF 0 10° 0.50±0.20 (.020±.008) C 1994 FUJITSU LIMITED F20012S-2C-4 Dimensions in mm (inches). 18 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 © FUJITSU LIMITED Printed in Japan 24