Fujitsu semiconductor
Rev5.0
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15U36
ØDESCRIPTION
The Fujitsu MB15U36 is a serial input Phase Locked Loop (PLL) frequency synthesizer with 2.0GHz and 1.2GHz
prescalers. A 64/65 or a 128/129 for the 2.0GHz prescaler, and a 64/65 or a 128/129 for the 1.2GHz prescaler can
be selected that enables pulse swallow operation.
The latest BiCMOS process technology is used, resultantly a supply current is limited as low as 9.0mA typ. at a
supply voltage of 5.0V. MB15U36 utilizes a refined charge pump design (Fujitsu’s Super Charger) that provides
fast tuning along with low noise performance.
MB15U36 is ideally suitable for digital mobile communications, such as CATV, PHS(Personal Handy Phone
System), and PCS( Personal Communication Service).
Ø FEATURE
-High frequency operation : RF synthesizer: 2.0GHz max.
IF synthesizer: 1.2GHz max.
-Power supply voltage : Vcc=3.0 V to 5.5V
-Very low power supply current : Icc=9.0mA typ. (Vcc=5.0V)
-Power saving function : Ips1=Ips2=10uA max.
-Serial input 15 bit programmable reference divider : R=3 to 32,767
-Serial input 18 bit programmable divider consisting of
Binary 7 bit swallow counter : 0 to 127
Binary 11 bit programmable counter : 3 to 2,047
-On-chip high performance charge pump circuit and phase comparator achieved high speed settling
time and low phase noise.
-Wide operating temperature : Ta = -40 to +85 °C
-Plastic 20 pin TSSOP package
ØPACKAGE
20-pinPlastic SSOP
FPT-20P-M03
(FPT-20P-M06)
Rev5.0
MB15U36
ØPIN ASSIGNMENT
Vcc1
1
20
Vcc2
Vp1
2
19
Vp2
Do1
3
18
Do2
GND 1
4
17
GND 2
fin1
5
16
fin2
Xfin1
6
15
Xfin2
GND 1
7
14
GND 2
OSCin
8
13
LE
OSCout
9
12
Data
LD/fout
10
11
Clock
TOP
VIEW
-2 -
Rev5.0
MB15U36
ØPIN DESCRIPTIONS
Pin No Pin name I/O
Descriptions
1
Vcc1
−
Power supply voltage input pin for the RF1-PLL section, the shift register and the
oscillator input buffer. When power is OFF, latched data of RF1-PLL is cancelled.
2
Vp1
−
Power supply for RF1 charge pump.(Independent of 19 pin)
3
Do1
O
Charge pump output for the RF1-PLL section. Phase detector characteristics can
be reversed using the FC bit.
4
GND1
−
Ground for the RF1-PLL section.
5
fin1
I
Prescaler input pin for the RF1-PLL section.
Connection to an external VCO should be via AC coupling.
6
Xfin 1
I
Prescaler complimentary input for the RF1-PLL. Section.
This pin should be grounded via a capacitor.
7
GND1
−
Ground for the RF1-PLL section.
8
OSCin
I
The programmable reference divider input. External TCXO reference oscillator
input or connection to crystal. TCXO should be connected with via AC coupling.
9
OSCout
−
Oscillator output or connection to crystal.
10
LD/fout
O
Lock detect signal output (LD) / phase comparator monitoring output (fout).
The output signal is selected by the LDS and FDS bits in the serial data.
11
Clock
I
12
Data
I
13
LE
I
14
GND2
−
Ground for the RF2-PLL section.
15
Xfin 2
I
Prescaler complimentary input for the RF2-PLL section.
This pin should be grounded via a capacitor.
16
fin2
I
Prescaler input pin for the RF2-PLL section.
Connection to an external VCO should be via AC coupling.
17
GND2
−
Ground for the RF2-PLL section.
18
Do2
O
Charge pump output for the RF2-PLL section. Phase detector characteristics can
be reserved using FC bit.
19
Vp2
−
Power supply voltage for the RF2 charge pump.(Independent of 2 pin)
20
Vcc2
−
Power supply voltage input pin for the RF2-PLL section. When power is OFF,
latched data of IF-PLL is cancelled.
Clock input for the 22 bit shift register.
One bit data is shifted into the shift register on a rising edge of the clock.
Serial data input. Data is transferred to the corresponding latch (RF1-ref counter,
RF1-prog counter, RF2-ref counter, RF2-prog counter according to the control
bits setting in the serial programming data.
Load enable signal input.
When LE is “H”, data in the shift register is transferred to the corresponding latch
according to the control bits in the serial programming data.
-3 -
Rev5.0
MB15U36
ØBLOCK DIAGRAM
PKG:TSSOP-20(FPT-20-M03)
Vcc 2
GND2
20
2bit latch
7-bit latch
11-bit latch
Binary 11-bit
Binary 7-bit
swallow counter Programmable counter
(RF2-PLL)
(RF2-PLL)
SWRF2 PSRF2
fin 1 16
Xfin2 15
fpRF2
Prescaler
(RF2-PLL)
14 17
Phase comp
(RF2-PLL)
Vp 2
19
Charge comp
(RF2-PLL)
18 DO
2
Lock det.
(RF2-PLL)
64/65,128/129
5-bit latch
FC
CMC
RF2
RF2
ZC
LDS FDS
RF2
RF2
RF2
15-bit latch
Binary 15-bit
fr
Programmable ref. RF2
counter (RF2-PLL)
LDRF2
OSCout 9
OSCin 8
Selector
FC
CMC
RF1
OR
fin1
Xfin1
5
6
LE 13
Dat a 12
Cloc k 11
RF1
ZC
LDS FDS
RF1
RF1
RF1
5-bit latch
LDRF2
LDRF1
f rRF2
f rRF1
fpRF2
fpRF1
10
Phase comp Charge pump
(RF1-PLL)
(RF1-PLL)
3
Binary 15-bit
Programmable ref.
counter (RF1-PLL) frRF1
15-bit latch
Rrescaler
(RF-PLL)
LD/fout
LDRF1
64/65,128/129
Lock det.
(RF1-PLL)
SWRF1 PSRF1
Binary 7-bit
swallow counter
(RF1-PLL)
2bit latch
7-bit latch
Binary 11-bit
fpRF1
Programmable counter
(RF1-PLL)
11-bit latch
Latch selector
CN1 CN2
22-bit shift register
1
Vcc1
-4 -
4 7
2
GND1
Vp 1
Do1
Rev5.0
MB15U36
ØABSOLUTE MAXIMUM
Parameter
Symbol
Rating
Unit
Vcc
-0.5 to 6.5
V
Vp
-0.5 to 6.5
V
Input voltage
Vi
-0.5 to 6.5
V
Output voltage
Vo
-0.5 to 6.5
V
TSTG
-55 to +125
°C
Power supply voltage
Storage temperature
Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in
the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ØRECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
Typ.
Max.
4.5
5.0
5.5
V
Vcc1=Vcc2
3.0
5.5
5.5
V
Vcc1=Vcc2 *1
Vp
Vcc
-
5.5
V
Input voltage
Vi
GND
-
Vcc
V
Operating temperature
Ta
-40
-
+85
°C
Vcc
Power supply voltage
*1:Prescaler divide ratio is only 64/65 (SW=”L”) at RF1
Handling Precautions
-This device should be transported and stored in anti-static containers.
-This is a static-sensitive device ; take proper anti-ESD precautions. Ensure that personnel
and equipment are properly grounded. Cover workbenches with grounded conductive mats.
-Always turn the power supply off before inserting or removing the device from its socket.
-Protect leads with a conductive sheet when handling or transporting PC boards with devices
-5 -
Rev5.0
MB15U36
ØELECTRICAL CHARACTERISITCS
Parameter
Condition
Symbol
Icc1*1
Power saving current
Operating frequency
Vcc=5.0V
−
6.0
−
mA
Vcc=3.0V
−
3.5
−
mA
fin2=1200MHz
fosc=12MHz
Vcc=5.0V
−
3.0
−
mA
Vcc=3.0V
−
2.5
−
mA
Ips1
Vcc1 current at PsbitRF1/RF2=”H”
−
0.1*3
10
uA
Ips2
Vcc2 current at PsbitRF2=”H”
−
0.1*3
10
uA
fin1*4
RF1-PLL
100
−
2000
MHz
fin2*4
RF2-PLL
50
−
1200
MHz
fosc
Min. 500mVpp
3
−
40
MHz
RF1-PLL, 50Ω termination
-10
−
+2
dBm
RF1-PLL, Vcc=3.5V
300MHz
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