MB3769A

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27202-6E ASSP BIPOLAR SWITCHING REGULATOR CONTROLLER MB3769A ■ DESCRIPTION The Fujitsu MB3769A is a pulse-width-modulation controller which is applied to fixed frequency pulse modulation technique. The MB3769A contains wide band width Op-Amp and high speed comparator to construct very high speed switching regulator system up to 700 kHz. Output is suitable for power MOS FET drive owing to adoption of totem pole output. The MB3769A provides stand-by mode at low voltage power supply when it is applied in primary control system. ■ FEATURES • • • • • • • • • • • • • • High frequency oscillator (f = 1 kHz to 700 kHz) On-chip wide band frequency operation amplifier (BW = 8 MHz Typ) On-chip high speed comparator (td = 120 ns Typ) Internal reference voltage generator provides a stable reference supply (5 V ± 2%) Low power dissipation (1.5 mA Typ at standby mode, 8 mA Typ at operating mode) Output current ± 100 mA (± 600 mA at peak) High speed switching operation (tr = 60 ns, tf = 30 ns, CL = 1000 pF Typ) Adjustable Dead-time On-chip soft start and quick shut down functions Internal circuitry prohibits double pulse at dynamic current limit operation Under voltage lock out function (OFF to ON: 10 V Typ, ON to OFF: 8 V Typ) On-chip output shut down circuit with latch function at over voltage On-chip Zener diode (15 V) One type of package (SOP-16pin : 1 type) ■ APPLICATIONS • Power supply module • Industrial Equipment • AC/DC Converter etc. Copyright©1994-2006 FUJITSU LIMITED All rights reserved MB3769A ■ PIN ASSIGNMENT (TOP VIEW) +IN (OP) -IN (OP) FB DTC CT RT GND VL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +IN (C) -IN (C) VREF OVP VCC VZ VH OUT (FPT-16P-M06) 2 MB3769A ■ BLOCK DIAGRAM Fig. 1 - MB3769A Block Diagram Over Current Detection Comparator -IN (C) 15 S +IN (C) 16 + R 1.85 V VREF + + + PWM + Comp. + STB STB FB +IN (OP) 3 1 8 VL Q 10 VH + 1.8 V DTC 4 9 OUT -IN (OP) 2 13 + Error Amp Over Voltage Detector S 2.5 V Power off 1.5 V to 3.5 V Triangle Wave Oscillator R Q OVP + CT RT V CC 5 6 12 + 8/10 V STB - (2.5 V) 15.4 V VZ 11 30 kΩ GND 7 Reference Regulator 5.0 + 0.1 V + 14 VREF 3 MB3769A ■ ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Output Current Operation Amp Input Voltage Power Dissipation : SOP Storage Temperature *1 : Duty ≤ 5% *2 : Ta = + 25 °C, SOP package is mounted on the epoxy board. (4 cm x 4 cm x 0.15 cm) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC IOUT Vin (OP) PD TSTG Rating Min ⎯ ⎯ ⎯ ⎯ -55 Max 20 120 (660* ) VCC + 0.3 (≤ 20) 620*2 +125 1 Unit V mA V mW °C 4 MB3769A ■ RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Output Current (DC) Output Current (Peak) Operation Amp Input voltage FB Sink Current FB Source Current Comparator Input Voltage Reference Section Output Current Timing Resistor Timing Capacitor Oscillator Frequency Zener Current Operating Ambient Temperature: SOP Symbol VCC IOUT IOUT PEAK VINOP ISINK ISOURCE VINC+ VINCIREF RT CT fOSC IZ Ta SOP package Min 12 -100 -600 -0.2 -0.3 -0.3 9 100 1 -30 Typ 15 0 to VREF 0 to 3 0 to 2 2 18 680 100 +25 Max 18 +100 +600 VCC-3 0.3 2 VCC 2.5 10 50 10 5 +75 6 Unit V mA mA V mA mA V V mA kΩ pF kHz mA °C 700 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB3769A ■ ELECTRICAL CHARACTERISTICS (VCC=15V, Ta=+25°C) Parameter Output Voltage Input Regulation Reference Load Regulation Section Temp. Stability Short Circuit Output Current Oscillator Frequency Oscillator Section Voltage Stability Temp. Stability Input Bias Current Max. Duty Cycle Duty Cycle Set Dead -time Control Input Section Threshold Voltage 0% Duty Cycle Max. Duty Cycle Symbol VREF ∆VRIN ∆VRLD ∆VRTEMP ISC fOSC ∆fOSCIN ∆fOSC /∆T ID Dmax Dset VDO VDM VDH VIO (OP) IIO (OP) IIR (OP) VCM (OP) Av (OP) BW SR CMR VOH VOL Condition IREF = 1 mA 12 V ≤ VCC ≤ 18 V 1 mA ≤ IREF ≤10 mA -30 °C ≤ Ta ≤ +85 °C VREF = 0 V RT = 18 kΩ CT = 680 pF 12 V ≤ VCC ≤ 18 V -30 °C ≤ Ta ≤ +85 °C Value Min 4.9 15 90 75 45 1.55 4.5 -1 -0.2 70 65 4.0 - Typ 5.0 2 -1 ±200 40 100 ±0.03 ±2 2 80 50 3.5 1.85 ±2 ±30 -0.3 90 8 6 80 4.6 0.1 Max 5.1 15 -15 ±750 110 10 85 55 3.8 ±10 ±300 VCC -3 0.5 Unit V mV mV µV/ °C mA kHz % % µA % % V V V mV nA µA V dB MHz V/µs dB V V Vd = 1.5 V Vd = 0.5 VREF VCC = 7 V, IDTC = -0.3 mA V3 = 2.5 V V3 = 2.5 V V3 = 2.5 V 12 V ≤ VCC ≤ 18 V 0.5 V ≤ V3 ≤ 4 V Av = 0 dB RL = 10 kΩ, Av = 0 dB VIN = 0 V to 10 V I3 = -2 mA I3 = 0.3 mA Discharge Voltage Input Offset Voltage Input Offset Current Input Bias Current Common-Mode Input Voltage Error Amplifier Section Voltage Gain Band Width Slew Rate Common-Mode Rejection Rate “H” Level Output Voltage “L” Level Output Voltage (Continued) 6 MB3769A (Continued) (VCC=15V, Ta=+25°C) Parameter Input Offset Voltage Input Bias Current Current Comparator Common-Mode Input Voltage Voltage Gain Response Time PWM Comparator Section 0% Duty Cycle Max Duty Cycle “H” Level Output Voltage “L” Level Output Voltage Output Section Rise Time Fall Time Over Voltage Detector Under Voltage Out Stop Threshold Voltage Input Current VCC Reset Off to On On to Off Standby * Supply Current Operating Zener Voltage Zener Current Symbol VIO (C) IIB (C) VCM (C) AV (C) td VOPO VOPM VH VL tr tf VOVP IIOVP VCC RST VTHH VTHL ISTB ICC VZ IZ Condition VIN = 1 V VIN = 1 V 50 mV over drive RT = 18 kΩ CT = 680 pF IOUT = -100 mA IOUT = 100 mA CL = 1000 pF, RL = ∞ CL = 1000 pF, RL = ∞ VIN = 0 V RT = 18 kΩ 4 pin Open RT = 18 kΩ IZ = 1 mA V11-7 = 1 V Value Min -5 0 1.55 12.5 2.4 -1.0 2.0 9.2 7.2 - Typ ±5 -1 200 120 3.5 1.85 13.5 1.1 60 30 2.5 -0.2 3.0 10.0 8.0 1.5 8.0 15.4 0.03 Max ±15 2.5 250 3.8 1.3 120 80 2.6 4.5 10.8 8.8 2.0 12.0 - Unit mV µA V V/V ns V V V V ns ns V µA V V V mA mA V mA * : VCC = 8V 7 MB3769A Fig. 2 - MB3769A Test Circuit 1.0 V 10 kΩ 16 +IN (C) COMP in +IN (OP) 1 -IN (OP) 2 FB 3 DTC 4 680 pF VFB VDTC 15 -IN (C) 14 VREF 13 OVP 12 VCC MB3769A CT 5 18 kΩ RT 6 GND 7 VL 8 11 VZ 10 VH 9 OUT 1000 pF 15.0 V OUTPUT TEST INPUT 3.5 V Typ Voltage at CT 1.5 V Typ 1.05 V 1.0 V COMP in 0.95 V 90% tr of COMP-in should be within 20 ns. 50% OUTPUT 10% tr tf td 8 MB3769A Fig. 3 - MB3769A Operating Timing Soft Start Operation Dead-Time Input Voltage Triangle Wave Form Error Amp Output 1.85V Quick Shutdown Operation 3.5 V 1.5 V PWM Comparator Output Output Wave Form Comp. Current -in Wave Form Comp. Current +in Wave Form Comp. Current Latch Output Voltage at OVP OVP Latch Power Supply Voltage 0V Standby Mode Over Voltage Detector Latch OFF (15 V) 10 V (Typ) Over Current Detector 2.5 V (1 V) 8V (Typ) Over Voltage Detector 3V Standby Mode 9 MB3769A ■ FUNCTIONS 1. Error Amplifier The error amplifier detects the output voltage of the switching regulator. The error amplifier uses a high-speed operational amplifier with an 8 MHz bandwidth (typical) and 6 V/µs slew rate (typical). For ease of use, the common mode input voltage ranges from -0.2 V to VCC-3 V. Figure 4 shows the equivalent circuit. Fig. 4 - MB3769A Equivalent Circuit Differential Amp VCC VREF -IN (OP) 150 Ω +IN (OP) 700 µA To PWM Comp. GND Protection element 2. Overcurrent Detection Comparator There are two methods for protection of the output transistor of this device from overcurrents; one restricts the transistor’s ontime if an overcurrent that flows through the output transistor is detected from an average output current, and the other detects an overcurrent in the external transistor (FET) and shuts the output down instantaneously. Using average output currents, the peak current of the external transistor (FET) cannot be detected, so an output transistor with a large safe operation area (SOA) margin is required. For the method of detecting overcurrents in the external transistor (FET), the output transistor can be protected against a shorted filter capacitor or power-on surge current. The MB3769A uses dynamic current limiting to detect overcurrents in the output transistor (FET). A high-speed comparator and flip-flop are built-in. To detect overcurrents, compare the voltage at +IN(C) of current detection resistor connected the source of the output transistor (FET), with the reference voltage (connected to -IN(C)) using a comparator. To prevent output oscillation during overcurrent, flipflop circuit protects against double pulses occurring within a cycle. The output of overcurrent detector is ORed with other signals at the PWM comparator. See the example “■ Application Example” for details on use. Figure 5 shows the equivalent circuit of the over-current detection comparator. 10 MB3769A Fig. 5 - MB3769A Equivalent Circuit Over Current Detection Comparator VREF To PWM Comp. +IN (C) -IN (C) Protection element 3. DTC: Dead Time Control (Soft-Start and Quick Shutdown) The dead time control terminal and the error amplifier output are connected to the PWM comparator. The maximum duty cycle for VDTC (voltage applied to pin 4) is obtained from the following formula (approximate value at low frequency): Duty Cycle = (3.5 - VDTC) x 50 (%) [0% ≤ duty cycle ≤ DMAX (80%)] The dead time control terminal is used to provide soft start. In Figure 6, the DTC terminal is connected to the VREF terminal through R and C. Because capacitor C does not charge instantaneously when the power is turned on, the output transistor is kept turned off. The DTC input voltage and the output pulse width increase gradually according to the RC time constant so that the control system operates safely. Fig. 6 - MB3769A Soft Start Function VREF C DTC R Soft Start R2 Soft Start + DTC C R1 DTC VREF The quick shutdown function prevents soft start malfunction when the power is turned off and on quickly. After the power is shut down, soft start is disabled because the DTC terminal has low electric potential from the beginning if the power is turned on again before the capacitor is discharged. The MB3769A prevents this by turning on the discharge transistor to quickly discharge the capacitor in the stand-by mode. 11 MB3769A 4. Triangular Wave Oscillator The oscillation frequency is expressed by the following formula: 1 0.8 x CT x RT + 0.0002 ms [kHz] CT :µF RT :kΩ fOSC ~ For master/slave synchronized operation of several MB3769As, the CT and RT terminals of the master MB3769A are connected in the usual way and the CT terminals of the master and slave device (s) are connected together. The slave MB3769A’s RT terminal is connected to it’s VREF terminal to disable the slave’s oscillator. In this case, set 50/n kΩ (n is the number of master and slave ICs) to the upper limit of RT so that internal bias currents do not stop the master oscillation. Fig. 7 - MB3769A Synchronized Operation master RT CT VREF slave RT CT 5. Overvoltage Detector The overvoltage detection circuit shuts the system power down if the switching regulator’s output voltage is abnormal or if abnormal voltage is appeared. The reference voltage is 2.5 V (VREF /2). The system power is shut down if the voltage at pin 13 rises above 2.5 V. The output is kept shut down by the latching circuit until the power supply is turned off (see Figure 3). 6. Stand-by Mode and Under-Voltage Lockout (UVLO) Generally, VGS > 6 to 8 V is required to use power MOSFET for switching. UVLO is set so that output is on at VCC ≥ 10 V (standard) when the power is turned on and is off at VCC ≤ 8 V (standard) when the power is turned off. In the stand-by mode, the power supply current is limited to 2 mA or less when the output is inhibited by the UVLO circuit. When the MB3769A is operated from the 100 VAC line, the power supply current is supplied through resistor R (Figure 8). That is, the IC power supply current is supplied by the AC line through resistor R until operation starts. Current is then supplied from the transformer tertiary winding, eliminating the need for a second power supply. Two volts (typical) of hysteresis are provided for return from operation mode to stand-by mode not to return to stand-by mode until output power is turned on or to avoid malfunction due to noise. 12 MB3769A Fig. 8 - MB3769A Primary Control R C MB3769A 7. Output Section Because the OUT terminal (pin 9) carries a large current, the collector and emitter of the output transistor are brought out to the VH and VL terminals. In principle, VH is connected to VCC and VL is connected to GND, but VH can be supplied from another power supply (4 V to 18 V). Note that VL and GND should be connected as close to the IC package as possible. A capacitor of 0.1 µF or more is inserted between VH and VL (see Figure 9). Fig. 9 - MB3769A Typical Connection Circuit Of Output 12 10 9 7 8 ≥ 0.1 µF 13 MB3769A ■ APPLICATION EXAMPLE Fig. 10 - MB3769A DC - DC Convertor 12 to 18 V 3.6 kΩ 1+IN (OP) 2-IN (OP) 330 pF 100 kΩ 3FB 4DTC 5CT 6RT 7GND 8VL +IN (C) 16 IN (C) 15 VREF 14 OVP 13 MB3769A VCC 12 VZ 11 VH 10 OUT 9 R S 220 pF C 51 kΩ 18 kΩ 10 kΩ 5.1 kΩ 1Ω 20 kΩ 2.4 kΩ 5V 1A 3.3 kΩ 0.1 µF 10 kΩ Overcurrent Protection Circuit The waveform at the output FET source terminal is shown in Figure 11. The RC time constant must be chosen so that the voltage glitch in the waveform does not cause erroneous overcurrent detection. This time constant is should be from 5 ns to 100 ns. A detection current value depends on R or C because a waveform is weakened. To keep this glitch as small as possible, the rectifiers on the transformer secondary winding must be the fast-recovery type. Fig. 11 - MB3769A Output FET Source Point Glitch Point S waveform 14 MB3769A Fig. 12 -Primary Control 100 VAC R 1 +IN(OP) +IN(C) 16 2 -IN(OP) 22 kΩ 3 FB 4.7 µF 4 DTC 5 CT 6 RT 7 GND 22 kΩ 680 18 pF kΩ 8 VL -IN(C) 15 VREF 14 OVP 13 VCC 12 VZ 11 VH 10 OUT 9 * 22 Ω 15 kΩ 47 kΩ + + 10 kΩ *: The resistance (22 Ω) as an output current limiter at pin 9 is required when driving the FET which is more than 1000 pF (CGS). 15 V 0V Secondly power supply Fig. 13 -Secondly Control 12 V 43 kΩ 10 kΩ 39 kΩ 1000 27 pF kΩ 5.1 kΩ 1 +IN(OP) +IN(C) 16 51 kΩ 2 -IN(OP) 3 FB 4 DTC 5 CT 6 RT 7 GND 8 VL -IN(C) 15 VREF 14 OVP 13 VCC 12 VZ 11 VH 10 OUT 9 10 kΩ 680 pF 18 kΩ 15 MB3769A ■ SHORT PROTECTION CIRCUIT The system power can be shut down to protect the output against intermittent short-circuits or continuous overloads. This protection circuit can be configured using the OVP input as shown in Figure 14. Fig. 14 -Case I. (Over Protection Input) Primary Mode V0 (5V output) PC2 15 kΩ IN-B 8.2 kΩ IN-A 8 3 1 4 MB3761 6 5 PC1 OUT-B 500 Ω HYS-A 9 6.8 kΩ 500 Ω MB3769A 14 20 kΩ 13 PC2 7 1 µF PC1 100 kΩ 10 kΩ Fig. 15 -Case II. (Over Protection Input) Secondly Mode V0 (5V output) 14 VREF MB3769A 13 OVP 15 kΩ IN-B 8.2 kΩ 6.8 kΩ IN-A 3 1 20 kΩ 8 6 OUT-B MB3761 2 5 HYS-A 1 µF 200 kΩ 16 MB3769A ■ HOW TO SYNCHRONIZE WITH OUTSIDE CLOCK The MB3769A oscillator circuit is shown in Figure 16. CT charge and discharge currents are expressed by the following formula: 5V ICT = ±2 x I1 = ± RT Fig. 16 -Oscillator Circuit VREF 1 kΩ I1 2 x I1 RT + 2.5 V 300 Ω 6 5 (4 x I1) 150Ω CT 1.5 V 2 x I1 ICT + 500 Ω 500 Ω + 3.5 V R Q S This circuit shows that if the voltage at the CT terminal is set to 1.5 V or less, one oscillation cycle ends and the next cycle starts. An example of an external synchronous clock circuit is shown in Figure 17. Fig. 17 -Typical Connection of Synchronized Outside Clock Circuit tcycle 5 MB3769A 6 RT CT ex. MB74HC04 VP R(5.1 k Ω) clamp circuit (VL) VP tP tcycle = 2.5 µs (fEXT = 400 kHz) tP = 0.5 µs RT = 11 k Ω The Figure 18 shows the CT terminal waveform. VTH may be near 2.5 V. In this case, the maximum duty cycle is restricted as shown in the formula below if tP’ = 0. Fig. 18 -Voltage Waveform at CT 3.5 V VTH ( .. 2.5 V) 1.85 V VCT Dmax= (3.5 - 1.85) + (3.5 - VTH) (3.5 - VL) + (3.5 - VTH) ≤ 59% (VL = 0 V: No clamp circuit) VL When VTH = 2.5 V, CT can be provided by followings. tcycle - tP = 1 fOSC x (3.5 - VL) + (3.5 - VTH) fOSC(3.5 - 1.5) x 2 tP’ 17 MB3769A 1 0.8 x CT x RT 1 x 0.8 x RT 4 4.5 - VL (tcycle - tP) [pF] (RT: kΩ, tcycle, tP: ns) fOSC ~ CT ~ Make VL high for a large duty cycle for the clamp circuit. The circuits below can be used because the clamp voltage must be much lower than 1.5 V. Fig. 19 -Clamp Circuit VREF R1 (4.7 kΩ) (1.2 V) 0.1 µF A R2 (1.2 kΩ) 820 Ω 0.1 µF (1.2 V) 3 4 5 VREF 8 MB3761 B In circuit A, R1 and R2 must be determined considering the effects of tP R, or RT. , The transistor saturation voltage must be very small (