MB3775_07

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27204-5E ASSP BIPOLAR SWITCHING REGULATOR CONTROLLER MB3775 ■ LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM control circuits. Complete synchronization is obtained by using the same oscillator output waveform. This IC can provide following types of output voltage: step down, step up, and inverter. Power consumption is low, thus the MB3775 is ideal for use in high-efficiency portable equipment. ■ FEATURES • • • • • • • • Wide supply voltage range: 3.6 V to 18 V Low current consumption: 1.3 mA typical Wide oscillation frequency range: 1 kHz to 500 kHz On-chip timer latch short protection circuit On-chip under voltage lockout protection On-chip reference voltage: 1.28 V Variable dead time provides control over total operating range. Two types of packages (SOP-16pin : 1 type, SSOP-16pin : 1 type) ■ APPLICATIONS • LCD monitor/panel • Surveillance camera etc. Copyright©1994-2006 FUJITSU LIMITED All rights reserved MB3775 ■ PIN ASSIGNMENT (TOP VIEW) CT RT +IN1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF SCP +IN2 -IN1 FB1 D.T.C.1 OUT1 E/GND -IN2 FB2 D.T.C.2 OUT2 VCC (FPT-16P-M06) (FPT-16P-M05) ■ BLOCK DIAGRAM 9 V REF = 1.28 V V CC 1.9 V 1.3 V + − − 1 2 16 Reference Voltage 2.5 V Triangular Waveform OUT 1 7 Error Amp 1 3 4 5 12 14 13 + − PWM Comp.1 S.C.P.Comp. + + − + − − OUT 2 PWM Comp.2 10 1.1 V Error Amp 2 + − 2.5 V 15 1 µA S R R 1.28 V 0.9 V 0.9 V Latch U.V.L.O. + + − D.T.C.Comp. GND 1.8 V 6 11 8 2 MB3775 ■ OPERATION DESCRIPTION 1. Reference voltage The reference voltage circuit generates a stable, temperature-compensated 2.5 V reference from Vcc terminals (pin 9) for use by internal circuits. A reference voltage of temperature compensated 1/2 VREF can be obtained to external circuit by VREF terminal (pin 16). 2. Oscillator A triangular waveform of any frequency is obtained by connecting an external capacitor and resistor to the CT terminal (pin 1) and RT terminals (pin 2). The amplitude of this waveform is from 1.3 V to 1.9 V. The oscillator is internally connected to the non-inverting inputs of the PWM comparators. The oscillator waveform is available at the CT terminal (pin 1). 3. Error amplifiers The error amplifier detects the output voltage of the switching regulator. The common-mode input voltage range is −0.2 V to 1.45 V, so the input reference voltage can be set the VREF terminal (pin 16) and GND terminal levels. Error amplifiers can be used as either inverting and non-inverting amplifiers. The voltage gain is fixed. Phase compensation is possible by connecting a capacitor to the FB terminals (pins 5 and 12) of the error amplifiers. The error amplifier output are internally connected to the inverting inputs of the PWM comparators and also to the short protection circuit. 4. Timer latch short protection circuit The timer latch short protection circuit detects the output levels of the error amplifiers. If one or both error amplifier outputs are 1.1 V or lower, the timer circuit begins charging the externally connected protection enable capacitor. If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage reaches the transistor base-emitter voltage VBE ( 0.65 V), the latch circuit turns the output drive transistor off and sets the dead time to 100 %. 5. Under voltage lockout protection circuit An ambiguous transition state at power-on or a momentary fluctuation in the supply line may result in loss of control and may adversely affect or even destroy the system. The under voltage lockout protection circuit compares the internal reference voltage level with the supply voltage level. If the supply voltage level falls below the reference level the latch circuit is reset the output drive transistor is turned off and the dead time is set to 100%. The protection enable terminal (pin 15) is pulled “Low”. 6. PWM comparator Each PWM comparator has two inverting inputs and one non-inverting input. This voltage-to-pulse-width converter controls the output pulse width according to the input voltage. The PWM comparator turns the output drive transistor on when the oscillator triangular waveform is higher than the error amplifier output and the dead time control terminal voltage. 7. Output drive transistor The open-collector output-drive transistors provide common-emitter output of 18 V dielectric capability. The output drive transistors can source up to 50 mA of drive current to the switching power transistor. 3 MB3775 ■ ABSOLUTE MAXIMUM RATING Parameter Power Supply Voltage Error Amp Input Voltage Collector Output Voltage Collector Output Current Power Dissipation Operating Ambient Temperature Storage temperature Symbol VCC VI VO IO PD Ta Tstg Condition ⎯ ⎯ ⎯ ⎯ Ta ≤ +25 °C(SOP) Ta ≤ +25 °C(SSOP) ⎯ ⎯ Rating Min ⎯ −0.3 ⎯ ⎯ ⎯ ⎯ −30 −55 Max 20 +10 20 75 *620 *430 +85 +125 Unit V V V mA mW mW °C °C *: The packages are mounted on the epoxy board (4 cm x 4 cm x 1.5 mm). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Error Amp Input Voltage Collector Output Voltage Collector Output Current Phase Compensation Capacitor Timing Capacitor Timing Resistor Oscillator Frequency Reference Voltage Output Current Operating Ambient Temperature Symbol VCC VI VO IO CP CT RT fOSC IREF Ta Value Min 3.6 −0.2 ⎯ 0.3 ⎯ 150 5.1 1 −3 −30 Typ 6.0 ⎯ ⎯ ⎯ 0.1 ⎯ ⎯ ⎯ −1 +25 Max 18 +1.45 18 50 ⎯ 15000 100 500 ⎯ +85 Unit V V V mA µF pF kΩ kHz mA °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 4 MB3775 ■ ELECTRICAL CHARACTERISTICS (Ta = +25 °C, VCC = 6 V) Parameter Output Voltage Output Temp. Stability Reference Section Input Stability Load Stability Condition IOR = −1 mA Ta = −30 °C to +85 °C VCC = 3.6 V to 18 V IOR = −0.1 mA to −1 mA Symbol VREF VRTC Line Load IOS VtH VtL VHYS VR VtPC VSTB VI ⎯ Pin 5, Pin 12 CT = 330 pF, RT = 15 kΩ CT = 330 pF, RT = 15 kΩ Ta = −30 °C to +85 °C Duty Cycle = 0 % Duty Cycle = 100 % ⎯ Vdt = 0.7 V Idt = −40 µA Ibpc VtC fOSC fdev fdV fdT Vt0 Vt100 Ibdt Idt Vdt Value Min 1.26 −2 ⎯ ⎯ ⎯ ⎯ ⎯ 80 1.5 0.60 ⎯ ⎯ −1.4 ⎯ ⎯ ⎯ ⎯ −4 ⎯ 0.2 ⎯ ⎯ VREF −0.1 Typ 1.28 ±0.2 2 1 –30 2.72 2.60 120 1.9 0.65 50 50 −1.0 1.1 200 10 1 – 1.0 0.4 −0.2 −150 ⎯ Max 1.30 +2 10 7.5 –10 ⎯ ⎯ ⎯ ⎯ 0.7 100 100 −0.6 ⎯ ⎯ ⎯ ⎯ +4 VREF −0.15 ⎯ –1 −80 ⎯ Unit V % mV mV mA V V mV V V mV mV µA V kHz % % % V V µA µA V Short Circuit Output CurVREF = 0 V rent Under Voltage Lockout Protection Section Threshold Voltage Hysteresis Width Reset Voltage (VCC) Input Threshold Voltage Input Stand by Voltage Protection Circuit Section Input Latch Voltage Input Source Current Comparator Threshold Voltage Triangular Waveform Oscillator Section Oscillator Frequency Frequency Deviation Frequency Stability (Ta) Input Threshold Voltage (fOSC = 10 kHz) Dead-Time Control Section Input Bias Current Latch Mode Source Current Latch Input Voltage No pull up No pull up IOR = −0.1 mA IOR = −0.1 mA IOR = −0.1 mA ⎯ ⎯ Frequency Stability (VCC) VCC = 3.6 V to 18 V (Continued) 5 MB3775 (Continued) (Ta = +25 °C, VCC = 6 V) Parameter Input Offset Voltage Input Offset Current Input Bias Current Common Mode Input Voltage Range Voltage Gain Error Amp Section Frequency Band Width Common Mode Rejection Ratio Max Output Voltage Width Output Sink Current Output Source Current PWM Comparator Section Input Threshold Voltage (fOSC=10 kHz) Input Sink Current Input Source Current Output Section Output Leak Current Output Saturation Voltage VO = 1.6 V VO = 1.6 V Duty Cycle = 0 % Duty Cycle = 100 % Pin 5, Pin 12 = 1.6 V Pin 5, Pin 12 = 1.6 V VO = 18 V IO = 50 mA Output “OFF” RT = 15 kΩ AV = −3 dB Condition VO = 1.6 V VO = 1.6 V VO = 1.6 V VCC = 3.6 V to 18 V Symbol VIO IIO IB VICR AV BW CMRR VOM+ VOMIOM+ IOMVt0 Vt100 IIN+ IINLeak VSAT ICCS ICCa Value Min −10 −100 −500 −0.2 84 ⎯ 60 2.2 – 24 ⎯ ⎯ 1.05 24 ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ −100 ⎯ 120 3 80 2.4 0.7 50 −1.2 1.9 1.3 50 −1.2 ⎯ 1.1 1.3 1.7 Max +10 +100 ⎯ +1.45 ⎯ ⎯ ⎯ ⎯ 0.9 ⎯ −0.7 2.1 ⎯ ⎯ −0.7 10 1.4 1.8 2.4 Unit mV nA nA V V/V MHz dB V V µA mA V V µA mA µA V mA mA Stand by Current Average Supply Current 6 MB3775 ■ TEST CIRCUIT INPUT TEST SW CPE 4.7 kΩ VCC=6 V OUTPUT 1 4.7 kΩ OUTPUT 2 16 15 14 13 12 11 10 9 MB3775 1 0.1 µF 330 pF 15 kΩ 2 3 4 5 6 7 8 TEST INPUT ■ TIMING CHART (Internal Waveform) Error Amp output Triangular waveform oscillator output 1.9 V Dead Time PWM 1.5 V input voltage 1.3 V Short circuit protection 1.1 V comparator Reference input “High” PWM comparator output “Low” Output Transistor collector waveform SCP Terminal waveform “High” “Low” 0.6 V 0V tPE LOCK-OUT DEAD TIME 100% Short circuit protection “High” comparator output “Low” LOCK-OUT CANCEL Power supply voltage 3.6 V (VCC : Min Value) 0V Protection Enable Time tPE = 0.6 x 106 x CPE (s) : 2.8 V (Typ Value) 7 MB3775 ■ APPLICATION CIRCUIT Fig. 1 - Chopper Type Step Down/Inverting VIN (10 V) 820 pF 1 10 kΩ 2 3 4 33 kΩ +− 1 µF 33 kΩ +− 1 µF 330 Ω 330 Ω 120 µH − 16 15 14 0.1 µF 2.3 kΩ MB3775 13 12 11 10 9 5 0.1 µF 33 kΩ 6 7 8 1.9 kΩ 0.1 µF 33 kΩ − 56 µH + 220 µF 5.6 kΩ 470 Ω 470 Ω + − + 120 µH 9.1 kΩ V0- (−5 V) 220 µF GND Fig. 2 - Chopper Type Step Up/Inverting 220 µF V0+ (+5 V) VIN (5 V) 820 pF 1 10 kΩ 2 3 4 5 33 kΩ +− 1 µF 33 kΩ +− 1 µF 330 Ω 330 Ω 16 15 14 0.1 µF 2.3 kΩ MB3775 13 12 11 10 9 1.9 kΩ 0.1 µF 33 kΩ − 56 µH 0.1 µF 33 kΩ 6 7 8 + 220 µF 16 kΩ 3.9 kΩ 120 µH − 120 µH 100 Ω − + + 9.1 kΩ V0- (−5 V) 220 µF GND 220 µF V0+ (+12 V) (Continued) 8 MB3775 (Continued) Fig. 3 - Chopper Type Step Up/Inverting (For High Speed) 820 pF 1 10 kΩ 2 2.3 kΩ 3 4 33 kΩ +− 1 µF 33 kΩ +− 1 µF 220 Ω 470 Ω 470 Ω 120 µH − − 1 µF VIN (5 V) 16 15 14 56 µH 1.9 kΩ 0.1 µF 33 kΩ − 0.1 µF MB3775 13 12 11 10 9 0.1 µF 33 kΩ 5 6 7 + 220 µF 16 kΩ 470 Ω 8 470 Ω 33 kΩ 33 kΩ 330 pF + 150 Ω 120 µH + GND − + V0+ (+12 V) 9.1 kΩ V0- (−5 V) 220 µF 220 µF Fig. 4 - Multi Output Type (Apply Transformer) 820 pF 1 10 kΩ 2 3 4 5 6 7 8 15 14 1.9 kΩ VIN (10 V) 16 0.1 µF 5.6 kΩ 0.1 µF − 56 µH MB3775 13 12 33 kΩ 0.1 µF + 1.8 kΩ 1 nF 11 33 kΩ 10 9 220 µF 220 Ω − + − + − + − + 220 µF 220 µF 220 µF 220 µF V02(−12 V) V01(−5 V) GND V02+ (+5 V) V01+ (+12 V) 9 MB3775 ■ HOW TO SET OUTPUT VOLTAGE The output voltage is set using the connection shown in Fig. 5 and 6. The error amplifiers are supplied to the internal reference voltage circuit as are the other internal circuits. The common-mode input voltage range is from −0.2 V to +1.45 V. When the amplifiers are operated non-inverting, tie the inverting terminal to VREF ( 1.28 V). When the amplifiers are operated inverting, tie the non-inverting terminal to ground. Fig. 5 -Connection of Error Amp Output Voltage V0 is plus R2 V0+ [V0+ = VREF X (1 + R2/R1)] + PIN 5 or PIN 12 R1 − VREF Fig. 6 -Connection of Error Amp Output Voltage V0 is minus R2 V0- [V0- = −VREF X (R2/R1)] − PIN 5 or PIN 12 R1 + VREF 10 MB3775 ■ HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT TIMING CHART shows the configuration of the protection latch circuit. Error amplifier outputs, are internally connected to the non-inverting inputs of the short-circuit protection comparator and are compared with the reference voltage (1.1 V) connected to the inverting input. When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus, short-circuit protection control is also kept in balance, and the protection enable terminal (pin 15) voltage is kept at about 50 mV. If the load condition drastically changes due to a load short-circuit and if low-level signals (1.1 V or lower) are input to the non-inverting inputs of the short-circuit protection comparator from the error amplifiers, the shortcircuit protection comparator outputs a “Low” level to turn transistor Q1 off. The protection enable terminal voltage is discharged, and then the short-circuit protection comparator charges the externally connected protection enable capacitor CPE according to the following formula: VPE = 50 mV + tPE x 10-6/CPE 0.65 = 50 mV + tPE x 10-6/CPE CPE = tPE/0.6 (µF) When the protection enable capacitor charges to about 0.65 V, the protection latch is set to enable the under voltage lockout protection circuit and to turn the output drive transistor off. The dead time is set to 100 %. Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the protection latch is not reset if the power is not turned off. The non-inverting inputs of the D.T.C. comparator are connected to the D.T.C. terminals (pins 6 and 11) through the power supply (about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the inverting input. To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. terminals), the D.T.C. comparator outputs a “High” level to turn Q2 on until the D.T.C. terminals (pins 6 and 11) voltage drops to about 0.9 V. Fig. 7 - Protection Latch Circuit 2.5 V 1 µA S.C.P.Comp. R1 Error Amp1 Error Amp2 1.1 V + + − SCP 15 CPE S R U.V.L.O. Q1 Q2 Q3 Latch + + − 0.9 V 0.9 V 1.8 V 6 11 D.T.C.1 D.T.C.2 D.T.C.Comp. 11 MB3775 ■ SYNCHRONIZATION OF ICs To synchronize MB3775 ICs, first, the specified capacitor and resistor are connected to the CT and RT terminals (pins 1 and 2) of the master IC to start self oscillation. Next, 2 V is applied to the RT terminals (pin 2) of the slave ICs to disable the charge/discharge circuit for triangular wave oscillation. Finally, the CT terminals (pin 1) of the master and slave ICs are connected. Instead of applying VRT to the RT terminals (pin 2), these terminals can be pulled up by a resistor (see resistance indicated by the dashed line in Fig. 8). Select the pull-up resistance Rpull from the formula given below. VCC ≤ Rpull 0.5 x N Rpull: Pull up Resistor (kΩ) VCC: Power Supply Voltage (V) N: Number of Slave ICs Fig. 8 - Connection of Master, Slave MB3775 (MASTER) VCC Rpull CT RT MB3775 (SLAVE) VRT 2V MB3775 (SLAVE) 12 MB3775 ■ TYPICAL PERFORMANCE CHARACTERISTICS Fig. 9 - Reference voltage vs. Power supply voltage 2.0 Fig. 10 - Average supply current vs. Power supply voltage 2.0 Average supply current I CCa (mA) 5 10 15 Power supply voltage VCC (V) 20 Reference voltage VREF(V) 1.5 1.5 1.0 1.0 0.5 0.5 0 0 5 10 15 Power supply voltage VCC (V) 20 Fig. 11 - Stand by current vs. Power supply voltage 2.0 Fig. 12 - Reference voltage vs. Operating ambient temperature 1.29 Reference voltage VREF (V) Stand by current ICCS (mA) 1.5 1.28 1.0 1.27 0.5 1.26 0 1.25 5 10 15 Power supply voltage VCC (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 Error Amp Max output voltage VOM (V) 20 −30 +0 +30 +60 +90 Operating ambient temperature Ta ( °C) Fig. 13 - Collectorsaturation saturation voltage vs. Sink current Fig. 14 - Error Amp Max output voltage vs. Frequency 3.0 Collectorsaturation voltage VSAT (V) 2.0 1.0 50 100 150 200 250 300 Sink current lO (mA) 350 0 100 1k 10k 100k Frequency f (Hz) 1M (Continued) 13 MB3775 Fig. 15 - Oscillation Frequency vs. Timing resistor 1M Fig. 16 - Triangular waveform cycle vs. Timing capacitor 103 Triangular waveform cycle ( µs) Oscillation Frequency fOSC (Hz) 100k 102 10k CT = 150 pF 101 Timing resistance = 15 kΩ VCC = 6 V 1k CT = 1500 pF 100 CT = 15000 pF 100 1k 10k 100k 1M Timing resistor RT (Ω) Timing resistance=15 kΩ VCC = 6 V 10M 10-1 101 102 103 104 Timing capacitor CT (pF) 105 Fig. 17 - Triangular waveform Max Amplitude voltage vs. Timing capacitor Fig. 18 - Gain/Phase vs. Frequency 60 40 Gain AV 180 Phase φ (deg) Triangular waveform Max Amplitude voltage (V) 2.2 2.0 Gain AV(dB) 1.8 20 90 1.6 0 −20 0 Phase φ −90 1.4 1.2 1.0 −40 −180 101 102 103 104 Timing capacitor CT (pF) CFB = 1 µF 105 −60 1k 10k 100k Frequency f (Hz) 1M 90 10M Fig. 19 - Gain/Phase vs. Frequency (Actual Data) 60 Fig. 20 - Gain/Phase vs. Frequency (Actual Data) 60 CFB = 0.1 µF 180 40 180 40 Gain A V(dB) Phase φ (deg) Gain AV(dB) Gain AV 0 Phase φ Gain AV 0 Phase φ 0 −20 0 −90 −20 −90 −40 −60 −180 −40 −60 −180 100 101 102 103 104 105 Frequency f (Hz) 106 107 100 101 102 103 104 105 Frequency f (Hz) 106 107 (Continued) 14 Phase φ (deg) 20 90 20 90 MB3775 (Continued) Fig. 21 - Gain/Phase vs. Frequency (Actual Data) 60 CFB=0.01 µF 40 180 Gain AV (dB) 20 Gain AV 0 Phase φ −20 0 −90 −40 −60 −180 100 101 102 103 104 105 Frequency f (Hz) 106 107 Phase φ (deg) 90 15 MB3775 ■ HOW TO SET THE ERROR AMPLIFIER FREQUENCY CHARACTERISTIC Figure 22 shows the equivalent circuit of the error amplifier. The frequency characteristic of the error amplifier is set by R1, R2, and CP The high-frequency gain is set by the . ratio of resistors R1 and R2 in the IC (set value 0 dB). When CP = 0.1 µF, the gain at 20 kHz ≤ f ≤ 5 MHz is about 0 dB. The roll-off frequency is adjusted by changing external phase compensating capacitor CP (see Fig. 24). When high frequency gain is needed or the phase must be advanced at a low frequency, connect a resistor RP between the FB terminals (pins 5 and 12) and CP as shown in Figure 23 (see Fig. 25). Fig. 22 - Error Amp Equivalent Circuit Error Amp [− IN] − x 120 [+ IN] + R1 38 kΩ PWM COMP R2 470 Ω [FB] CP Fig. 23 - Error Amp Equivalent Circuit (Insert RP) Error Amp [− IN] − x 120 [+ IN] + R1 38 kΩ PWM COMP R2 470 Ω [FB] RP CP Note: As shown above, the frequency characteristic of the error amplifier is set by the external phase compensating capacitor CP . When a ceramic chip capacitor must be used to meet the requirements of a small system, be careful of its . . . . temperature characteristic. (−30 °C = 1/5 and +80 °C = 1/3 for the frequency characteristic, so a sufficient phase margin must be allowed for at room temperature.) Ceramic chip capacitors with a low temperature characteristic (B characteristic) or film capacitors are recommended (see Fig. 26 to 28). 16 MB3775 Fig. 24 - Error Amp Frequency characteristics 60 AV 40 (Large) 20 Gain AV (dB) ϕ 0 (Small) 0 (Small) 90 Phase φ (deg) Phase φ (deg) CP = 0.1 µF 180 −20 (Large) −90 CP = 0.1 µF −180 −40 −60 10 100 1k 10k 100k 1M 10M 100M Frequency f (Hz) Fig. 25 - Error Amp Frequency characteristics 60 CP = 0.1 µF AV 40 180 20 Gain AV (dB) ϕ 0 RP=0 Ω (Large) (Large) 90 0 −20 −90 RP=0 Ω −40 −180 −60 10 100 1k 10k 100k 1M 10M 100M Frequency f (Hz) 17 MB3775 Fig. 26 - Ceramic Chip Capacitor (0.1 µF) 20 Temp. characteristic Temp. : Ratio −30°C : 0.19 +25°C : 1.0 +80°C : 0.32 −30°C 90 Phase φ (deg) −30°C +25°C +80°C 10 Gain AV (dB) 0 AV −10 0 φ +80°C +25°C −90 −20 1k 10k Frequency f (Hz) 100k 1M Fig. 27 - Tantal Capacitor (0.33 µF) 20 Temp. characteristic Temp. : Ratio −30°C : 0.95 to 1.05 +25°C : 1.0 +80°C : 0.95 to 1.05 AV −30°C 90 10 Gain AV (dB) 0 0 +25°C −10 φ +80°C −30°C −90 −20 +80°C 10k Frequency f (Hz) 100k +25°C 1M 1k Fig. 28 - Film Capacitor (0.1 µF) 20 AV Temp. characteristic −30°C : 0.9 to 1.1 +25°C : 1.0 +80°C : 0.9 to 1.1 90 Phase φ (deg) 10 Gain AV (dB) 0 −30°C, +25°C, +80°C −10 0 φ −30°C, −90 −20 +25°C +80°C 1k 10k Frequency f (Hz) 100k 1M 18 Phase φ (deg) MB3775 ■ EFFECT OF EQUIVALENT SERIES RESISTANCE OF SMOOTHING CAPACITOR The equivalent series resistance (ESR) of the smoothing capacitor in the DC/DC converter greatly affects the loop phase characteristic. A smoothing capacitor with a low ESR reduces system stability by increasing the phase shift in the high-frequency region (see Fig. 30). Therefore, a smoothing capacitor with a high ESR will improve system stability. Be careful when using low ESR semiconductor electrolytic capacitors (OS-CONTM) and tantalum capacitors. Note: OS-CON is the trademark of Sanyo Electric Co., Ltd. Fig. 29 - Step Down DC/DC Converter Basic Circuit L Tr RC VIN D C RL Fig. 30 - Gain vs. Frequency Fig. 31 - Phase vs. Frequency 20 0 Gain A V (dB) Phase φ (deg) 0 (2) −90 −20 (2) −40 −60 (1) : RC = 0 Ω (2) : RC = 31 mΩ 100 1k (1) 10k 100k −180 (1) : RC = 0 Ω (2) : RC = 31 mΩ (1) 10 10 100 1k Frequency f (Hz) 10k 100k Frequency f (Hz) 19 MB3775 Reference data If an aluminum electrolytic smoothing capacitor (RC 1.0 Ω) is replaced with a low ESR semiconductor electrolytic capacitor (OS-CONTM: RC 0.2 Ω), the phase shift is reduced by half (see Fig. 33 and 34). Fig. 32 - DC/DC Converter AV vs. φ characteristic Test Circuit VOUT V0+ AV vs. φ characteristic Between this point. + IN FB + VIN R2 − 0.1 µF − IN R1 ~ VREF Error Amp Fig. 33 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 40 AV Gain A V (dB) 20 0 +62° VCC=10 V RL=25 Ω CP=0.1 µF φ 180 V0+ 90 0 Phase φ (deg) + AI Capacitor 220 µF(16 V) − 1.0 Ω : fosc=1 kHz RC GND −20 −40 10 100 1k Frequency f (Hz) 10k 100k −90 −180 Fig. 34 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 40 Gain A V (dB) 20 0 AV VCC=10 V RL=25 Ω CP=0.1 µF φ +27° 180 Phase φ (deg) 90 0 + V0+ OS-CONTM 22 µF(16V) − RC 0.2 Ω : fosc=1 kHz −20 −40 10 100 1k Frequency f (Hz) 10k 100k −90 −180 GND 20 MB3775 ■ MEASURES FOR ENSURING SYSTEM STABILITY WHEN A LOW ESR SMOOTHING CAPACITOR IS USED When a low ESR smoothing capacitor is used in the DC/DC converter, only the L and C are apparent even in the high-frequency region, and the phase is delayed by almost 180°. Consequently, the system phase margin and stability are reduced. On the other hand, a low ESR capacitor is needed to reduce the amount of output ripple. This is contrary to the system stability explained above. To solve this problem, phase compensation can be used. This method increases the phase margin by advancing the phase when the phase margin is reduced by a low ESR capacitor. The three suggestions listed below are recommended for DC/DC converters using the MB3775. (1) As shown in Fig. 35, a capacitor is connected in parallel with the output feedback resistor to advance the phase. Use the formula below as a guideline for the capacitance. C1 1 2πfR2 Unstable Frequency (See Fig. 32) Fig. 35 - External circuit example1 to advance the phase C1 V0+ R2 + IN + FB − IN R1 − CP VREF Fig. 36 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 40 AV φ +66° 180 Phase φ (deg) Gain AV (dB) 20 VCC = 10 V RL = 25 Ω CP = 0.1 µF Smoothing Capacitor 22 µF OS-CON C1 = 4700 pF R1 = 1.8 kΩ R2 = 5.6 Ω 100 1k Frequency f (Hz) 90 0 0 −20 −40 −90 −180 10 10k 100k 21 MB3775 (2) As shown in Figure 37, a resistor (RP) is connected between the FB terminal (pins 5 and 12) and CP of the error amplifier to advance the phase. The more RP is increased, the more the phase is advanced. However, the gain in the high-frequency range is also increased, which causes instability. Therefore, select the optimum resistance (see Fig. 38). Fig. 37 - External circuit example 2 to advance the phase V0+ R2 + IN + FB − IN R1 − RP CP VREF Fig. 38 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 40 AV Gain A V (dB) 20 VCC = 10 V RL = 25 Ω CP = 0.1 µF Smoothing Capacitor 22 µF OS-CON RP = 470 Ω R1 = 1.8 kΩ R2 = 5.6 Ω 100 1k Frequency f (Hz) 10k 180 Phase φ (deg) φ +45° 90 0 0 −20 −40 −90 −180 100k 10 22 MB3775 (3) As shown in Fig. 39, the phase is advanced by using both example 1 and 2 (Fig. 35 and 37). Fig. 39 - External circuit example 3 to advance the phase C1 V0+ R2 + IN + − IN − FB R1 RP CP VREF ■ ERROR AMPLIFIER INPUT RIPPLE VOLTAGE The boost circuit for charging the phase compensating capacitor CP is connected to the error amplifier as shown in Figure 40 to protect against output voltage overload at power-on. A =15 mV offset voltage is provided for the negative input side so that the boost circuit only operates at power: on. When a capacitor is connected in parallel with the output feedback resistor, because the output ripple is too large or for advanced phase compensation, the boost circuit starts operating, which may degrade regulation if the differential input voltage of the error amplifier exceeds =15 mV. Be careful with the differential input voltage : of the error amplifier. Fig. 40 - Error Amp /Boost Equivalent circuit V0 + VCC + Advanced phase compensation capacitor R4 − 15 mV [+ IN] + [− IN] × 120 R1 38 kΩ Boost circuit − R2 Error Amp 470 Ω R3 [FB] CP VREF 23 MB3775 ■ NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage - Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. ■ ORDERING INFORMATION Part number MB3775PF-❏❏❏ MB3775PFV-❏❏❏ MB3775PF-❏❏❏E1 MB3775PFV-❏❏❏E1 Package 16-pin plastic SOP (FPT-16P-M06) 16-pin plastic SSOP (FPT-16P-M05) 16-pin plastic SOP (FPT-16P-M06) 16-pin plastic SSOP (FPT-16P-M05) Remarks Conventional version Conventional version Lead Free version Lead Free version ■ RoHS Compliance Information of Lead (Pb) Free version The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added “E1” at the end of the part number. 24 MB3775 ■ MARKING FORMAT (Lead Free version) MB3775 XXXX XXX E1 INDEX SOP-16 Lead Free version Lead Free version 3 775 E1XXXX XXX INDEX SSOP-16 25 MB3775 ■ LABELING SAMPLE (Lead free version) lead-free mark JEITA logo JEDEC logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 G Pb (3N)2 1561190005 107210 QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN 1/1 MB123456P - 789 - GE1 0605 - Z01A 1000 1561190005 Lead Free version 26 MB3775 ■ MB3775PF-❏❏❏E1, MB3775PFV-❏❏❏E1 RECOMMENDED CONDITIONS of MOISTURE SENSITIVITY LEVEL Item Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions Condition IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 8 days Please processes within 8 days after baking (125 °C, 24H) 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) [Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) H rank : 260 °C Max 260 °C 255 °C 170 °C to 190 °C RT (b) (c) (d) (e) (a) (d') (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60s to 180s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10s or less : Temperature 230 °C or more, 40s or less or Temperature 225 °C or more, 60s or less or Temperature 220 °C or more, 80s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 °C Max Times : 5 s max/pin 27 MB3775 ■ PACKAGE DIMENSION 16-pin plastic SOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 1.27 mm 5.3 × 10.15 mm Gullwing Plastic mold 2.25 mm MAX 0.20 g P-SOP16-5.3×10.15-1.27 (FPT-16P-M06) Code (Reference) 16-pin plastic SOP (FPT-16P-M06) *110.15 –0.20 .400 –.008 16 +0.25 +.010 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17 –0.04 9 +0.03 +.001 .007 –.002 INDEX *2 5.30±0.30 7.80±0.40 (.209±.012) (.307±.016) Details of "A" part 2.00 –0.15 .079 –.006 +0.25 +.010 (Mounting height) 1 8 "A" 0.13(.005) 0.25(.010) 0~8˚ 1.27(.050) 0.47±0.08 (.019±.003) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10 –0.05 +0.10 +.004 .004 –.002 (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F16015S-c-4-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued) 28 MB3775 (Continued) 16-pin plastic SSOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.65 mm 4.40 × 5.00 mm Gullwing Plastic mold 1.45mm MAX 0.07g P-SSOP16-4.4×5.0-0.65 (FPT-16P-M05) Code (Reference) 16-pin plastic SSOP (FPT-16P-M05) *1 5.00±0.10(.197±.004) 16 9 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.03 (.007±.001) INDEX *2 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) Details of "A" part 1.25 –0.10 .049 –.004 LEAD No. 1 8 +0.20 +.008 (Mounting height) 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.13(.005) M 0~8˚ 0.10±0.10 (Stand off) (.004±.004) 0.25(.010) 0.10(.004) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F16013S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. 29 MB3775 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0605