MB3782P

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27205-5E ASSP Power Supplies BIPOLAR Switching Regulator Controller MB3782 s DESCRIPTION The FUJITSU MB3782 is a PWM-type switching regulator controller, designed with open-collector output for connection to external drive transistors and coils, providing a selection of three types of output voltage: step-up, step-down or inverting (inverting output is available on one circuit only). The MB3782 features identical oscillator output waveforms to enable completely synchronous operation and prevent the occurrence of low-frequency beat between channels. Also, the MB3782 features low power dissipation (2.1 mA Typ) and a built-in standby mode (10 µA), making possible the configuration of a wide variety of high-efficiency, stable power supplies, even with the use of battery power. The MB3782 is an ideal power supply for high-performance portable devices such as video camcorders and cameras. s FEATURES • • • • • • • • Wide voltage range (3.6 V to 18 V) Low power dissipation (operating mode: 2.1 mA (Typ), standby mode: 10 µA (Max) Wide range of oscillator frequencies, high-frequency capability (1 to 500 kHz) On-chip timer-latch type short detection circuit On-chip undervoltage lockout circuit On-chip 2.50 V reference voltage circuit (1.25 V output available at RT pin) Dead time adjustment over full duty cycle range On-chip standby mode (power on/off function) s PACKAGE Plastic DIP 20 pin , Plastic SOP 20 pin , (DIP-20P-M01) (FPT-20P-M01) MB3782 s PIN ASSIGNMENT TOP VIEW VREF CT RT + IN1 – IN1 FB1 DTC1 PUT1 GND OUT2 1 2 3 4 5 6 7 8 9 10 VCC CTL – IN3 FB3 DTC3 OUT3 SCP – IN2 FB2 DTC2 20 19 18 17 16 15 14 13 12 11 (DIP-20P-M01) (FPT-20P-M01) s PIN DESCRIPTION Pin No. 1 2 Pin Name VREF CT I/O O — Description 2.50 V (typ) voltage output: provides load current up to 3 mA, for use as error amplifier reference input and for dead time setting. Oscillator timing capacity connection: should be used in the capacity range 150 to 15000 pF. Oscillator timing resistor connection: should be used in the resistance range 5.1 to 100 kΩ. This pin can also provide output at voltage level VREF/2, for use as error amplifier reference input. Error amplifier 1 non-inverting input pin. Error amplifier 1 inverting input pin. Error amplifier 1 output pin: connect resistor and capacitor between this pin and the –IN1 pin to set gain and adjust frequency characteristics. OUT1 dead time setting pin: VREF voltage is divided by an external resistor and applied to set dead time. Also, a capacitor may be connected between this pin and the GND pin to perform soft start operations. 3 4 5 6 RT +IN1 –IN1 FB1 — I I O 7 DTC1*1 I (Continued) 2 MB3782 (Continued) Pin No. 8 9 10 Pin Name VOUT1 GND OUT2 I/O O — O Description Open collector type output pin with an emitter connected to GND. Output current may be up to 50 mA. Ground pin Open collector type output pin with an emitter connected to GND. Output current may be up to 50 mA. Used to set OUT2 pin dead time. VREF voltage is divided by an external resistor and applied to set dead time. Also, a capacitor may be connected between this pin and the GND pin to perform soft start operations. Error amplifier 2 output pin: connect resistor and capacitor between this pin and the –IN2 pin to set gain and adjust frequency characteristics. Error amplifier 2 inverting input pin. Time constant setting capacitor connection for timer-latch type short prevention circuit: a capacitor should be connected between this pin and the GND pin. For details, see “s Setting the Time Constant for the Timer-Latch Type Short Prevention Circuit.” Open collector type output pin for emitter connected to GND. Output current may be up to 50 mA. Used to set OUT3 pin dead time. VREF voltage is divided by an external resistor and applied to set dead time. Also, a capacitor may be connected between this pin and the GND pin to perform soft start operations. Error amplifier 3 output pin: connect resistor and capacitor between this pin and the –IN3 pin to set gain and adjust frequency characteristics. Error amplifier 3 inverting input pin. Power supply control pin: low level places the IC in standby mode and reduces power consumption to 10 µA or lower. Input level may be driven by TTL or CMOS. Power supply pin: voltage range is 3.6 to 18 V. 11 DTC2* 1 I 12 13 FB2 –IN2 O I 14 SCP*2 — 15 OUT3 O 16 DTC3* 1 I 17 18 19 20 FB3 –IN3 CTL VCC O I I — *1: DTC = Dead Time Control *2: SCP = Short Circuit Protection 3 MB3782 s BLOCK DIAGRAM RT 3 CT 2 VREF 1 VCC 20 CLT 19 1.25 V 2.5 V Triangular wave oscillator Reference voltage source Power on/off control circuit 9 GND Error Amp.1 + IN1 – IN1 FB1 DTC1 4 PWM Comp. Ch.1 + + – 8 + – OUT1 5 6 7 Error Amp.2 – IN2 13 PWM Comp. + + – – + 1.25 V Ch.2 10 OUT2 FB2 DTC2 12 11 Error Amp.3 – IN3 18 PWM Comp. + + – – + 1.25 V Ch.3 15 OUT3 FB3 DTC3 17 16 SCP Comp. – – – + 2.1 V VREF 1 µA SCP 14 S Latch R U.V.L.O. 4 MB3782 s FUNCTIONAL DESCRIPTIONS 1. Reference Voltage Source The reference voltage source uses the voltage provided at the power supply pin (pin 20) to generate a temperature-compensated reference voltage (≅ 2.50 V), which is used as the operating power supply for the internal circuits of the IC. The reference voltage source can be output through the VREF pin (pin 1). 2. Triangular Wave Oscillator By connecting a timing capacitor and resistor respectively to the CT pin (pin 2) and RT pin (pin 3), the oscillator can provide a triangular waveform at any desired frequency. The waveform has an amplitude of 1.3 V to 1.9 V, and can be connected to the non-inverting input of the onchip PWM comparator and also output through the CT pin. 3. Error Amps The error amps are amplifiers that detect the output voltage of the switching regulator and send the PWM control signal. The common-mode input voltage range is 1.05 V to 1.45 V, so that the voltage applied to the non-inverting input pin as a reference voltage should be either the voltage obtained by dividing the IC reference voltage output (recommended value: VREF/2) or the voltage obtained from the RT pin (1.25 V). The non-inverting input for the error amps 1 and 2 is internally connected to VREF/2 voltage. Also, a feedback transistor and capacitor can be connected between the error amp output pin and inverting input pin to provide any desired level of loop gain, enabling stable phase compensation. 4. Timer Latch (S-R Latch) Type Short Prevention Circuit The timer-latch type short prevention circuit detects the output levels from each of the error amps. Whenever one or more error amps produces an output level of 2.1 V or higher, the timer circuit is activated starting the charging of the external protection enabler capacitor. If the error amp output voltage does not return to normal range before the voltage in this capacitor reaches the transistor’s base-emitter junction voltage (VBE (≅ 0.65 V)), the latch circuit will operate to turn the output transistor off and at the same time set the dead time to 100%. Once the prevention circuit is activated, the power must be switched on again to resume normal operation. 5. Low Input Voltage Fault Prevention Circuit (Under Voltage Lock-Out (UVLO) function) When power is switched on, excess power or momentary drops in power line current can cause operating faults in the controller IC, which can in turn lead to damage or deterioration in systems. The low input voltage fault prevention circuit detects the internal reference voltage level with respect to the power supply voltage level and acts to reset the latch circuit, thereby turning the output transistor off and at the same time setting the dead time to 100% and holding the SCP pin (pin 14) at “low.” Operation returns to normal when the power supply voltage reaches or exceeds the UVLO threshold voltage level. 6. PWM Comparator The PWM comparator is a voltage comparator with one inverting and two non-inverting inputs, which acts as a voltage to pulse width converter controlling the on-time of the output pulse according to the input voltage level. When the triangular waveform produced by the oscillator is lower than either the error amp output or the DTC pin voltage, the output transistor is switched on. It is also possible to use the DTC terminal to provide a soft start function. 7. Output Transistor The output is open-collector type, with the emitter of the output transistor connected to the GND pin. The power transistor for external switching can carry a base current of up to 50 mA. 8. Power Supply Control Power supply on/off control is enabled through the CTL pin (pin 19). (In standby mode, power supply current is 10 µA or less.) 5 MB3782 s SETTING THE TIME CONSTANT FOR THE TIMER-LATCH TYPE SHORT PREVENTION CIRCUIT Figure 1 shows the configuration of the protection latch circuit. The output lines from the error amps are each connected to the inverting input lines of the short protection comparator, which constantly compares them with the reference voltage of approximately 2.1 V connected to the non-inverting input. When load conditions in the switching regulator are stabilized, there is no variation in the output from the error amps, and therefore the short prevention controls are held in equilibrium. In this situation, voltage at the SCP pin (pin 14) is held at approximately 50 mV. When load conditions change rapidly, as in the case of a load short, high potential signal (greater than 2.1V) from the error amps is input to the inverting signal input of the short protection comparator, and the short protection comparator outputs a “low” level signal. The transistor Q1 is consequently switched off, so that short protection capacitor CPE externally connected to the SCP pin voltage is then charged according to the following formulas. VPE = 50 mV + tPE × 10–6/CPE 0.65 = 50 mV + tPE × 10–6/CPE CPE = tPE/0.6 (µF) When the short protection capacitor is charged to a level of approximately 0.65 V, the SR latch is set and the low input voltage fault prevention circuit is enabled, turning the output drive transistor off. At the same time, the dead time is set to 100% and the SCP pin (pin 14) is held “low.” This closes the S-R latch input and then discharges the capacitor CPE 2.50 V 1 µA S.C.P.Comp. Error Amp.1 Error Amp.2 Error Amp.3 2.1 V – – – + 14 CPE Q1 Q3 S R U.V.L.O. PWM Comp. Out Latch Figure 1 Protection Latch Circuit 6 MB3782 s SETTING OUTPUT VOLTAGE The following diagrams show the connections used to set the output voltage. Because the power supply to the error amps is provided by the same reference voltage circuit used for the other internal circuits, the common-mode input voltage range is set at 1.05 V to 1.45 V. The reference voltage input to the +IN and -IN pins should be set at 1.25 V (VREF/2). The method of connection for channel 1 is different from channel 2 and channel 3. In addition, channel 1 is capable of picking up both positive and negative voltages, while channel 2 and channel 3 can pick up only positive output voltages. VREF V0 + R R1 V0 + = VREF · (R1 + R2) 2·R2 + – pin 6 R R2 RNF Figure 2 Error amp (channel 1) connection: Output voltage VO positive VREF V0 – = – R R1 VREF · (R1 + R2) + VREF 2·R2 + – pin 6 R R2 RNF V0 – Figure 3 Error amp (channel 1) connection: Output voltage VO positive 7 MB3782 V0 + R1 V0 + = 1.25 · (R1 + R2) R2 + – pin 12,17 R2 RNF 1.25 V Figure 4 Error amp (channel 2, channel 3) connection The non-inverting input to the error amps on channel 2 and channel 3 is internally connected to VREF/2, and therefore cannot be configured for inverting output. ch-1 ch-2 ch-3 Step up Step down Inverting q q q q q × q q × 8 MB3782 s USING THE RT PIN The triangular waves, as shown in Figure 5, act to set the oscillator frequency by charging and discharging the capacitor connected to the CT pin using the current value of the resistor connected to the RT pin. In addition, when voltage level VREF/2 is output to external circuits from the RT pin, care must be taken in making the external circuit connections to adjust for the fact that I1 is increased by the value of the current I2 to the external circuits in determining the oscillator frequency (see Figure 6). ICT = IRT Triangular wave oscillator = VREF 2RT VREF 2 2 IRT RT CT 1 ICT Figure 5 No VREF/2 connection to external circuits from RT pin ICT = IRT Triangular wave generator = I1 + I2 VREF 2 2 IRT To external circuits IRT I1 RT CT 1 ICT = VREF + I2 2RT Figure 6 VREF/2 connection to external circuits from RT pin 9 MB3782 s TREATMENT OF UNUSED ERROR AMPS Any error amps that are not used should be handled as follows. Note that failure to apply proper treatment to error amps will cause the SCP circuit to activate and disable the switching regulator output. 1. Error Amp (channel 1) Not In Use 1 3 4 5 7 9 VREF RT + IN1 – IN1 DTC1 GND Note: Pin 6 and pin 8 shoud be left open. 2. Error Amp (channel 2) Not In Use VREF 1 9 – IN2 GND DTC2 13 11 Note: Pin 10 and pin 12 shoud be left open. 3. Error Amp (channel 3) Not In Use VREF – IN3 18 DTC3 16 1 9 GND Note: Pin 15 and pin 17 shoud be left open. 10 MB3782 s TREATMENT OF UNUSED SCP PIN When the timer latch short protection circuit is not used, the SCP pin should be connected to the GND by the shortest possible path. SCP 14 11 MB3782 s ABSOLUTE MAXIMUM RATINGS (Ta = +25°C) Parameter Power supply voltage Error amp input voltage Dead time control input voltage Control input voltage Collector output voltage Collector output current Allowable loss Operating temperature Storage temperature Symbol VCC VIN Vdt VCTL VOUT IOUT PD*1 Top Tstg Ta ≤ +25°C Condition — — — — — — SOP Version DIP Version — — Rating Min — –0.3 –0.3 –0.3 — — — — –30 –55 Max 20 +10 +2.8 +20 20 75 740*2 1110 +85 +125 Unit V V V V V mA mW °C °C *1: For operation in conditions where Ta > +25°C, the SOP version should be derated by 7.4 mW/°C, and the DIP version should be derated by 11.1 mW/°C. *2: When mounted on a 4 cm-square dual-sided epoxy board. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Error amp input voltage Control input voltage Collector output voltage Collector output current Reference voltage output current Timing capacitance Timing resistance Oscillator frequency Operating temperature Symbol VCC VIN VCTL VOUT IOUT IREF CT RT fOSC Top Condition — — — — — — — — — — Value Min 3.6 1.05 0 — 0.3 –3 150 5.1 1 –30 Typ 6.0 — — — — –1 — — — +25 Max 18.0 1.45 18 18 50 0 15000 100 500 85 Unit V V V V mA mA pF kΩ kHz °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 12 MB3782 s ELECTRICAL CHARACTERISTICS (VCC = 6 V, Ta = +25°C) Value Unit Typ Max 2.50 ±0.2 2 1 –10 2.72 2.60 120 1.9 0.65 50 50 –1.0 2.1 200 ±5 ±1 — 1.3 1.9 65 0.2 500 — 2.55 2 10 7.5 –3 — — — — 0.70 100 100 –0.6 — 240 — — +4 — 2.25 75 1 — 0.3 V % mV mV mA V V mV V V mV mV µA V kHz % % % V V % µA µA V Parameter Reference voltage Output voltage Output voltage temperature variation Input stability Load stability Short output current Threshold voltage Hysteresis width Reset voltage (VCC) Input threshold voltage Input standby voltage Input latch voltage Input source current Comparator threshold voltage Oscillator frequency Frequency deviation Frequency deviation (VCC) Frequency deviation (Ta) Input threshold voltage ON duty cycle Input bias current Latch mode sink current Latch input voltage Symbol VREF VRTC Line Load IOS VtH VtL VHYS VR VtPC VSTB VIN Ibpc VtC fOSC fdev fdV fdT Vt0 Vt100 Dtr Ibdt Idt Vdt Conditions IOR = –1 mA Ta = –30°C to +85°C VCC = 3.6 V to 18 V IOR = –0.1 mA to –1 mA VREF = 2 V IOR = –0.1 mA IOR = –0.1 mA IOR = –0.1 mA — — No pull-up No pull-up — Pin 6, pin 12, pin 17 CT = 330 pF, RT = 15 kΩ CT = 330 pF, RT = 15 kΩ VCC = 3.6 V to 18 V Ta = –30°C to +85°C Duty cycle = 0 % Duty cycle = 100 % Vdt = VR/1.45 V — Vdt = 2.5 V Idt = 100 µA Min 2.45 –2 — — –30 — — 80 1.5 0.60 — — –1.4 — 160 — — –4 1.05 — 55 — 150 — Dead time controller Triangular wave Short circuit protection Undervoltage lock oscillator (DTC) (SCP) out circuit (UVLO) (Continued) 13 MB3782 (Continued) Parameter Input offset voltage Input offset current Input bias current Common mode input voltage range Error amps Voltage gain Frequency bandwidth Common mode rejection ratio Maximum output voltage range Output sink current Output source current PWM comparator Input threshold voltage Input sink current Input source current Input OFF conditions Input ON conditions Control pin current Output leak current Output saturation voltage Standby current Average feed current Symbol VIO IIO IB VICR Av BW CMRR VOM+ VOMIOM+ IOMVt0 Vt100 IIN+ IINVOFF VON ICTL Leak VSAT ICCS ICCa VCTL = 10 V VOUT = 18 V IOUT = 50 mA VCTL = 0 V VCTL = VCC, no output load VOUT = 1.6 V VOUT = 1.6 V Duty cycle = 0 % Duty cycle = 100 % Pin 6, pin 12, pin 17 Pin 6, pin 12, pin 17 — — Av = 0 dB — — — Conditions VOUT = 1.6 V VOUT = 1.6 V VOUT = 1.6 V VCC = 3.6 V to 18 V — (VCC = 6 V, Ta = +25°C) Value Unit Typ Max — — –100 — 80 0.8 80 — 0.7 1.0 –60 1.3 1.9 1.0 –60 — — 200 — 1.1 — 2.1 6 100 — 1.45 — — — — 0.9 — — — 2.25 — — 0.7 — 400 10 1.4 10 3.2 mV nA nA V dB MHz dB V V mA µA V V mA µA V V µA µA V µA mA Min –6 –100 –500 1.05 70 — 60 VREF –0.3 — — — 1.05 — — — — 2.1 — — — — — Notes : • Voltage control on channel 1 may be positive or negative. • The non-inverting input to the error amps on channel 2 and channel 3 is internally connected to VREF/2, and therefore voltage control is positive only. • VREF/2 output can be obtained from the RT pin. 14 Entire Output device block Control block MB3782 s TEST CIRCUIT OUTPUT OUTPUT 4.7 kΩ 4.7 kΩ VCC CTL 1 330 pF 2 150 kΩ 3 4 5 TEST INPUT 7 8 9 10 6 20 19 18 17 16 15 14 4.7 kΩ TEST INPUT OUTPUT CPF 13 12 11 TEST INPUT 15 16 MB3782 CT pin wavefoms Short protection comparator reference input 2.1 V 1.9 V 1.6 V 1.3 V Dead time,PWM input voltage Error amp output PWM comparator output “Low” “High” “Low” 0.6 V SCP pin waveforms 0V “High” “Low” Power ON 2.1 V Control pin voltage (VCTL: minimum value) 0V 3.6 V 0V “High” Dead time 100 % s TIMING CHART (INTERMAL WAVEFORMS) Output transistor-collector waveforms tPE Short protection comparator output Power OFF Power supply voltage (VCC: minimum) Protection enable time tPE ≅ 0.6 × 106 × CPE (µs) 16 kΩ 5.6 kΩ 9.1 kΩ 1.8 kΩ 1 µF 1 µF 1 µF 4.7 kΩ 2.4 kΩ 10 kΩ 4.7 kΩ 10 kΩ 10 kΩ s EXAMPLE OF APPLICATION 56 µH VIN (6 V) CTL 1 7 11 16 20 19 VREF 4 DTC1 330 Ω DTC2 DTC3 VCC CTL 120 µH 330 Ω 330 Ω 120 µH + 220 µF – 10 + IN1 – IN1 OUT1 8 4.7 kΩ 5 V0 – (–5V) 0.033 µF 6 150 kΩ FB1 1.8 kΩ 13 – IN2 FB2 MB 3782 V0 + (+5V) OUT2 0.033 µF 12 150 kΩ 1.8 kΩ 18 330 Ω 120 µH 220 µF + – 3.9 kΩ OUT3 15 – IN3 FB3 CT RT SCP GND 9 V0 + ( + 12 V ) 0.033 µF 17 2 3 14 150 kΩ 820 PF 100 Ω 8.2 kΩ 0.1 µF MB3782 17 MB3782 s TYPICAL CHARACTERISTICS CURVES Power supply voltage vs.reference voltage 5.0 3.0 Power supply voltage vs.average feed current Ta = +25˚C Reference voltage VREF (V) Average feed current (mA) Ta = +25˚C 2.5 1.5 0 0 4 8 12 16 20 Power supply voltage VCC (V) Ambient temperature vs.reference voltage 2.51 2.50 2.49 2.48 2.47 2.46 2.45 VCC = VCTL = 6 V IOR = -1 mA 0 0 4 8 12 16 20 Power supply voltage VCC (V) Timing capacity vs.triangular wave maximum amplitude voltage 2.2 VCC = 6 V RT = 15 kΩ Ta = +25˚C Reference voltage VREF (V) Triangular wave maximum amplitude voltage (V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 - 40 - 20 0 20 40 60 80 Ambient temperature Ta (˚C) 100 102 103 Timihg capacitance CT (pF) 104 Sink current vs.collector saturation voltage Collector saturation voltagre VOL (V) 2.0 Error amp maximum output voltage amplitude (V) VCC = 6 V Ta = +25˚C 1.5 Frequency vs.error amp maximum output voltage amplitude 3.0 VCC = 6 V Ta = +25˚C 2.0 1.0 1.0 0.5 0 0 10 20 30 40 50 Sink current IOL (mA) 0 100 500 1 k 5 k 10 k Fequency f (Hz) 50 k 100 k 500 k (Continued) 18 MB3782 Timing resistance vs.oscillator frequency VCC = 6 V Ta = +25˚C 100 1M VCC = 6 V RT = 15 kΩ Ta = +25˚C Power supply voltage vs. triangular wave period Oscillator frequency fOSC (Hz) Triangular wave period(µs) 10 100 k CT = 150 pF 10 k CT = 15000 pF CT = 1500 pF 1 102 103 104 105 Timing capacitance CT (pF) 1k 1k 5 k 10 k 50 k 100 k 500 k Timing resistance RT (Ω) Ambient temperature vs.oscillator frequency 10 100 Oscillator frequency vs.duty cycle VCC = 6 V CT = 1330 pF RT = 15 kΩ Ta = +25˚C Frequency variation fDT (%) Duty Cycle Dtr (%) VCC = 6 V CT = 330 pF RT = 15 kΩ 80 60 40 20 0 0 Ð 10 - 40 - 20 0 20 40 60 80 100 120 5k 10 k 50 k 100 k 500 k 1 M Oscillator frequency (Hz) Ambient temperature Ta (˚C) Control voltage vs.reference voltage 5.0 VCC = 6 V CT = +25˚C 500 Control input current VCC = 6 V CT = +25˚C Reference voltage VREF (V) Control current ICTL (µA) 2.5 250 0 0 1 2 3 4 5 Control voltage VCTL (V) 0 0 4 8 12 16 20 Control voltage VCTL (V) (Continued) 19 MB3782 Frequenncy vs.gain and phase 40 20 Gain AV (dB) 0 CNF = open AV 180 90 0 40 20 Gain AV (dB) 0 Frequenncy vs.gain and phase CNF = 0.047 pF 180 AV 90 0 φ φ -20 -40 10 100 1k 10 k 100 k -90 -180 1M Phase ϕ (deg) -20 -40 10 100 -90 -180 1k 10 k 100 k 1M Frequenncy f (Hz) Frequenncy vs.gain and phase 40 20 Gain AV (dB) 0 CNF = 470 pF 180 90 0 φ 40 20 Gain AV (dB) 0 Frequenncy f (Hz) Frequenncy vs.gain and phase CNF = 4700 pF AV 180 90 0 φ Phase ϕ (deg) -20 -40 10 100 1k -90 -180 10 k 100 k 1M -20 -40 10 100 -90 -180 1k 10 k 100 k 1M Frequenncy f (Hz) Test Circuit VREF VREF CNF 4.7 kΩ 4.7 kΩ 240 kΩ 4 10 µF -+ 4.7 kΩ 4.7 kΩ Frequenncy f (Hz) 6 OUT IN 5+ Error amp (Continued) 20 Phase ϕ (deg) AV Phase ϕ (deg) MB3782 (Continued) Ambient temperature vs.allowable loss Allowable loss PD (mW) 1200 1110 1000 800 740 600 400 200 DIP version SOP version -30 -20 -10 0 0 10 20 30 40 50 60 70 80 85 Ambient temperature Ta (˚C) 21 MB3782 s APPLICATIONS • Concerning Equivalent Series Resistance and Stability of Smoothing Capacitors In DC/DC converters, the equivalent series resistance value (ESR) of smoothing capacitors has a major influence on loop phase characteristics. The ESR is a means by which phase characteristics approximate phase relationships to ideal capacitors in highfrequency bands (see Graph 1), thus improving system stability. At the same time, the use of smoothing capacitors with low ESR reduces system stability, so that care must be taken when using semiconductor electrolytic capacitors (OS capacitors) or tantalum capacitors with low ESR. L Tr Rc VIN D C RL Figure 7 Basic circuit for step-down voltage DC/DC converter Frequency vs.Gain Frequency vs.phase 20 0 0 Phase (deg) Gain (dB) 2 – 90 – 20 2 – 40 1 : Rc = 0 Ω – 60 10 2 : Rc = 31 mΩ 100 1k Frequency f (Hz) 10 k 1 – 180 1 : Rc = 0 Ω 2 : Rc = 31 mΩ 1 100 k 10 100 1k Frequency f (Hz) 10 k 100 k Graph 1 Frequency vs. gain and phase 22 MB3782 • Reference data Changing the smoothing capacitor from an aluminum electrolytic capacitor (RC ≅ 1.0Ω) to a lower-ESR semiconductor electrolytic capacitor (OS capacitor: RC ≅ 0.2 Ω) decreases the phase margin (see Graphs 2, 3). V out V0 + CNF AV and phase characteristics measured between these points – IN FB – + + IN R1 R2 VIN VREF/2 Error amp Figure 8 Measurement of DC/DC Capacitor AV and Phase (Ψ) Characteristics Graph 2 60 40 DC/DC converter + 5 V output frequency vs.gain and phase Vcc = 10 v RL = 25 Ω Cp = 0.1 µF φ 62° 180 V0 + Phase (deg) 90 0 – 90 + – Aluminum electrolytic capacitor 220 µF (16 V) RC ≅ 1.0 Ω : fosc = 1 kHz Av Gain (dB) 20 0 – 20 – 40 10 100 1k Frequency f (Hz) 10 k – 180 100 k Graph 3 DC/DC converter + 5 V output frequency vs.gain and phase 60 40 Gain (dB) 20 φ 0 – 20 – 40 10 27° 0 – 90 – 180 100 k Av Vcc = 10 v RL = 25 Ω Cp = 0.1 µF 180 90 Phase (deg) + – OS capacitor 22 µF (16 V) RC ≅ 0.2 Ω : fosc = 1 kHz 100 1k Frequency f (Hz) 10 k 23 MB3782 s NOTES ON USE • Take account of common impedance when designing the earth line on a printed wiring board. • Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series. • Do not apply a negative voltage - Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. s ORDERING INFORMATION Part number MB3782P MB3782PF Package Plastic DIP, 20 pin (DIP-20P-M01) Plastic SOP, 20 pin (FPT-20P-M01) Remarks 24 MB3782 s PACKAGE DIMENSIONS Plastic DIP 20 pin , (DIP-20P-M01) 24.64 –0.30 .970 –.012 +.008 +0.20 INDEX-1 INDEX-2 6.60±0.25 (.260±.010) 4.36(.172)MAX 0.51(.020)MIN 0.25±0.05 (.010±.002) 3.00(.118)MIN 0.46±0.08 (.018±.003) 15°MAX 0.86 –0 1.27(.050) MAX +0.30 +.012 1.27 –0 +0.30 +.012 .034 –0 .050 –0 2.54(.100) TYP 7.62(.300) TYP C 1994 FUJITSU LIMITED D20005S-3C-3 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 25 MB3782 (Continued) Plastic SOP 20 pin (FPT-20P-M01) Note 1) Note 2) Note 3) Note 4) +0.25 +.010 *1 : These dimensions include resin protrusion. *2 : These dimensions do not include resin protrusion. Pins width and pins thickness include plating thickness. Pins width do not include tie bar cutting remainder. 0.17 –0.04 +0.03 +.001 *112.70 –0.20 .500 –.008 20 11 .007 –.002 INDEX *2 5.30±0.30 7.80±0.40 (.209±.012) (.307±.016) Details of "A" part 2.00 –0.15 .079 –.006 +0.25 +.010 (Mounting height) 1 10 "A" 0.25(.010) 0~8˚ 1.27(.050) 0.47±0.08 (.019±.003) 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10 –0.05 +0.10 +.004 .004 –.002 (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F20003S-c-7-7 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 26 MB3782 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0309 © FUJITSU LIMITED Printed in Japan