MB39A104

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27231-5E ASSP For Power Management Applications (General Purpose DC/DC Converter) 2-ch DC/DC Converter IC with Overcurrent Protection MB39A104 ■ DESCRIPTION The MB39A104 is a 2-channel DC/DC converter IC using pulse width modulation (PWM), incorporating an overcurrent protection circuit (requiring no current sense resistor). This IC is ideal for down conversion. Operating at high frequency reduces the value of coil. This is ideal for built-in power supply such as LCD monitors and ADSL. This product is covered by US Patent Number 6,147,477. ■ FEATURES • • • • • • • • • Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor) Power supply voltage range : 7 V to 19 V Reference voltage : 5.0 V ± 1 % Error amplifier threshold voltage : 1.24 V ± 1 % High-frequency operation capability : 1.5 MHz (Max) Built-in standby function: 0 µA (Typ) Built-in soft-start circuit independent of loads Built-in totem-pole type output for P-ch MOS FET One type of package (SSOP-24 pin : 1 type) ■ APPLICATION • • • • LCD monitor/panel IP phone Printer Video capture etc. Copyright©2002-2006 FUJITSU LIMITED All rights reserved MB39A104 ■ PIN ASSIGNMENTS (TOP VIEW) VCCO : 1 VH : 2 OUT1 : 3 VS1 : 4 ILIM1 : 5 DTC1 : 6 VCC : 7 CSCP : 8 FB1 : 9 −INE1 : 10 CS1 : 11 RT : 12 24 : CTL 23 : GNDO 22 : OUT2 21 : VS2 20 : ILIM2 19 : DTC2 18 : GND 17 : VREF 16 : FB2 15 : −INE2 14 : CS2 13 : CT (FPT-24P-M03) 2 MB39A104 ■ PIN DESCRIPTION Pin No. 1 2 3 4 5 Symbol VCCO VH OUT1 VS1 ILIM1 I/O ⎯ O O I I Descriptions Output circuit power supply terminal (Connect to same potential as VCC pin) Power supply terminal for FET drive circuit (VH = VCC − 5 V) External P-ch MOS FET gate drive terminal Overcurrent protection circuit input terminal Overcurrent protection circuit detection resistor connection terminal. Set overcurrent detection reference voltage depending on external resistor and internal current resource (110 µA at RT = 24 kΩ) PWM comparator block (PWM) input terminal. Compares the lowest voltage among FB1 and DTC1 terminals with triangular wave and controls output. Power supply terminal for reference power supply and control circuit (Connect to same potential as the VCCO terminal) Timer-latch short-circuit protection capacitor connection terminal Error amplifier (Error Amp 1) output terminal Error amplifier (Error Amp 1) inverted input terminal Soft-start capacitor connection terminal Triangular wave oscillation frequency setting resistor connection terminal Triangular wave oscillation frequency setting capacitor connection terminal Soft-start capacitor connection terminal Error amplifier (Error Amp 2) inverted input terminal Error amplifier (Error Amp 2) output terminal Reference voltage output terminal Output circuit ground terminal (Connect to same potential as GNDO terminal.) PWM comparator block (PWM) input terminal. Compares the lowest voltage among FB2 and DTC2 terminals with triangular wave and controls output. Overcurrent protection circuit detection resistor connection terminal. Set overcurrent detection reference voltage depending on external resistor and internal current resource (110 µA at RT = 24 kΩ) Overcurrent protection circuit input terminal External P-ch MOS FET gate drive terminal Output circuit ground terminal (Connect to same potential as GND terminal) Power supply control terminal. Setting the CTL terminal at “L” level places IC in the standby mode. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DTC1 VCC CSCP FB1 −INE1 CS1 RT CT CS2 −INE2 FB2 VREF GND DTC2 I ⎯ ⎯ O I ⎯ ⎯ ⎯ ⎯ I O O ⎯ I 20 21 22 23 24 ILIM2 VS2 OUT2 GNDO CTL I I O ⎯ I 3 MB39A104 ■ BLOCK DIAGRAM −INE1 10 VREF + + 10 µA CS1 11 1.24 V FB1 9 Error Amp1 L priority CH1 Drive1 P-ch 1 VCCO PWM + Comp.1 + 3 OUT1 L priority IO = 200 mA at VCCO = 12 V Current Protection Logic 4 VS1 + 5 ILIM1 DTC1 6 −INE2 15 L priority VREF + + 10 µA CS2 14 1.24 V FB2 16 DTC2 19 Error Amp2 CH2 Drive2 P-ch IO = 200 mA at VCCO = 12 V PWM + Comp.2 + 22 OUT2 L priority H: at SCP H priority SCP Comp. + + (3.1 V) Current Protection Logic 21 VS2 + 20 ILIM2 H: at OCP SCP Logic CSCP 8 UVLO H:UVLO release VCC − 5 V VH Bias Voltage 2 VH 2.5 V 1.5 V 23 GNDO Error Amp Power Supply Error Amp Referennce 7 VCC bias OSC Accuracy ±1% 1.24 V VREF Power VR1 ON/OFF CTL 24 CTL 5.0 V 12 13 RT CT 17 VREF 18 GND 4 MB39A104 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Output current Output peak current Power dissipation Storage temperature Symbol VCC IO IOP PD TSTG Condition VCC, VCCO terminal OUT1, OUT2 terminal Duty ≤ 5% (t = 1/fOSC×Duty) Ta ≤ +25 °C ⎯ Rating Min ⎯ ⎯ ⎯ ⎯ −55 Max 20 60 700 740* +125 Unit V mA mA mW °C * : The packages are mounted on the epoxy board (10 cm × 10 cm). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Reference voltage output current VH output current Input voltage Control input voltage Output current Output Peak current Oscillation frequency Timing capacitor Timing resistor VH terminal capacitor Soft-start capacitor Short-circuit detection capacitor Reference voltage output capacitor Operating ambient temperature Symbol VCC IREF IVH VINE VDTC VCTL IO IOP fOSC CT RT CVH CS CSCP CREF Ta Condition VCC, VCCO terminal VREF terminal VH terminal −INE1, −INE2 terminal DTC1, DTC2 terminal CTL terminal OUT1, OUT2 terminal Duty ≤ 5% (t = 1/fOSC×Duty) Value Min 7 −1 0 0 0 0 −45 −450 100 100 Typ 12 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 500 500 100 24 0.1 0.1 0.1 0.1 +25 Max 19 0 30 VCC − 0.9 VCC − 0.9 19 +45 +450 1000 1500 560 130 1.0 1.0 1.0 1.0 +85 Unit V mA mA V V V mA mA kHz kHz pF kΩ µF µF µF µF °C Overcurrent detection by ON resistance of FET * ⎯ ⎯ VH terminal CS1, CS2 terminal CSCP terminal VREF terminal ⎯ 39 11 ⎯ ⎯ ⎯ ⎯ −30 * : Refer to“ ■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY”. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB39A104 ■ ELECTRICAL CHARACTERISTICS (VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C) Parameter Output voltage 1.Reference voltage block [REF] Output voltage temperature variation Input stability Load stability Short-circuit output current 7.Error amplifier 6.Soft2.Under 5.Triangular 4.Short-circuit 3.Short-circuit block start voltage lockout wave oscillator detection block detection block [Error Amp1, block protection circuit block [OSC] [SCP Comp.] [SCP Logic] Error Amp2] [CS1, CS2] block [UVLO] Threshold voltage Hysteresis width Threshold voltage Input source current Reset voltage Symbol Pin No 17 17 17 17 17 17 17 17 8 8 17 Conditions Ta = +25 °C Ta = 0 °C to +85 °C VCC = 7 V to 19 V VREF = 0 mA to −1 mA VREF = 1 V VREF = VREF = ⎯ ⎯ ⎯ VREF = Value Min 4.95 ⎯ ⎯ ⎯ −50 2.6 2.4 ⎯ 0.68 −1.4 2.4 Typ 5.00 0.5* 3 1 −25 2.8 2.6 0.2* 0.73 −1.0 2.6 Max 5.05 ⎯ 10 10 −12 3.0 2.8 ⎯ 0.78 −0.6 2.8 Unit V % mV mV mA V V V V µA V VREF ∆VREF/ VREF Line Load IOS VTLH VTHL VH VTH ICSCP VRST Threshold voltage VTH 8 ⎯ 2.8 3.1 3.4 V Oscillation frequency Frequency temperature variation fOSC ∆fOSC/ fOSC 13 CT = 100 pF, RT = 24 kΩ Ta = 0 °C to +85 °C 450 500 550 kHz 13 ⎯ 1* ⎯ % Charge current ICS 11, 14 CS1 = CS2 = 0 V −14 −10 −6 µA Threshold voltage Input bias current Voltage gain VTH IB AV 9, 16 10, 15 9, 16 FB1 = FB2 = 2 V −INE1 = −INE2 = 0 V DC 1.227 1.240 1.253 −120 ⎯ −30 100* ⎯ ⎯ V nA dB (Continued) 6 MB39A104 (Continued) (VCC = VCCO = 12 V, VREF = 0 mA, Ta = +25 °C) Symbol BW VOH VOL ISOURCE ISINK VT0 Threshold voltage VT100 Input current ILIM terminal input current Offset voltage IDTC ILIM 6, 19 6, 19 5, 20 Duty cycle = Dtr DTC1 = DTC2 = 0.4 V RT = 24 kΩ, CT = 100 pF ⎯ −2.0 99 2.5 −0.6 110 2.6 ⎯ 121 V µA µA Pin No. 9, 16 9, 16 9, 16 9, 16 9, 16 6, 19 Conditions AV = 0 dB ⎯ ⎯ FB1 = FB2 = 2 V FB1 = FB2 = 2 V Duty cycle = 0 % Value Min ⎯ 4.7 ⎯ ⎯ 150 1.4 Typ 1.6* 4.9 40 −2 200 1.5 Max ⎯ ⎯ 200 −1 ⎯ ⎯ Unit MHz V mV mA µA V Parameter 10.Bias 9.Overcurrent 8.PWM comparator 7.Error amplifier block voltage protection circuit block [Error Amp1, block block [PWM Comp.1, Error Amp2] [VH] [OCP1, OCP2] PWM Comp.2] Frequency bandwidth Output voltage Output source current Output sink current VIO 5, 20 ⎯ ⎯ 1* ⎯ mV Output voltage VH 2 VCC = VCCO = 7 V to 19 V VCC− VCC− VCC− VH = 0 mA to 30 mA 5.5 5.0 4.5 V 11.Output block [Drive1, Drive2] Output source current ISOURCE 3, 22 OUT1 to OUT4 = 7 V, Duty ≤ 5 % (t = 1/fOSC×Duty) OUT1 to OUT4 = 12 V, Duty ≤ 5 % (t = 1/fOSC×Duty) OUT1 = OUT2 = −45 mA OUT1 = OUT2 = 45 mA IC Active mode IC Standby mode CTL = 5 V CTL = 0 V CTL = 0 V CTL = 5 V ⎯ −300 ⎯ mA Output sink current Output ON resistor CTL input voltage ISINK ROH ROL VIH VIL ICTLH 3, 22 3, 22 3, 22 24 24 24 24 1, 17 1, 17 ⎯ ⎯ ⎯ 2 0 ⎯ ⎯ ⎯ ⎯ 350 8.0 6.5 ⎯ ⎯ 50 ⎯ 0 4.0 ⎯ 12.0 9.7 19 0.8 100 1 10 6.0 mA Ω Ω V V µA µA µA mA 12.Control block 13.General [CTL] Input current Standby current Power supply current ICTLL ICCS ICC *: Standard design value. 7 MB39A104 ■ TYPICAL CHARACTERISTICS Power Supply Current vs. Power Supply Voltage 10 Reference Voltage vs. Power Supply Voltage 10 Power supply current ICC (mA) Reference voltage VREF (V) Ta = +25 °C CTL = 5 V 8 8 Ta = +25 °C CTL = 5 V VREF = 0 mA 6 6 4 4 2 2 0 0 5 10 15 20 0 0 5 10 15 20 Power supply voltage VCC (V) Power supply voltage VCC (V) Reference Voltage vs. Load current 10 Reference Voltage vs. Ambient Temperature 2.0 Reference voltage ∆VREF (%) Reference voltage VREF (V) 8 Ta = +25 °C VCC = 12 V CTL = 5 V 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −40 −20 0 +20 +40 VCC = 12 V CTL = 5 V VREF = 0 mA 6 4 2 0 0 5 10 15 20 25 30 35 Load current IREF (mA) Ambient temperature Ta (°C) +60 +80 +100 CTL terminal Current vs. CTL terminal Voltage 500 CTL terminal current ICTL (µA) 400 7 300 VREF 200 ICTL 100 6 5 4 3 2 1 0 0 5 10 15 0 20 CTL terminal voltage VCTL (V) (Continued) 8 Reference voltage VREF (V) 10 Ta = +25 °C 9 VCC = 12 V VREF = 0 mA 8 MB39A104 Triangular Wave Oscillation Frequency vs. Timing Resistor Triangular wave oscillation frequency fOSC (kHz) 10000 Triangular Wave Oscillation Frequency vs. Timing Capacitor 10000 Triangular wave oscillation frequency fOSC (kHz) Ta = +25 °C VCC = 12 V CTL = 5 V Ta = +25 °C VCC = 12 V CTL = 5 V 1000 1000 RT = 11 kΩ 100 RT = 130 kΩ RT = 24 kΩ RT = 68 kΩ CT = 39 pF 100 CT = 560 pF CT = 220 pF CT = 100 pF 10 1 10 100 1000 10 10 100 1000 10000 Timing resistor RT (kΩ) Timing capacitor CT (pF) Triangular Wave Upper and Lower Limit Voltage vs. Triangular Wave Oscillation Frequency 3.2 Triangular Wave Upper and Lower Limit Voltage vs. Ambient Temperature 3.2 Triangular wave upper and lower limit voltage VCT (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 0 Triangular wave upper and lower limit voltage VCT (V) Ta = +25 °C VCC = 12 V CTL = 5 V RT = 47 kΩ Upper VCC = 12 V 3.0 CTL = 5 V 2.8 RT = 24 kΩ CT = 100 pF 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 −40 −20 0 +20 +40 +60 Upper Lower Lower +80 +100 200 400 600 800 1000 1200 1400 1600 Triangular wave oscillation frequency fOSC (kHz) Ambient temperature Ta ( °C) Triangular Wave Oscillation Frequency vs. Ambient Temperature Triangular wave oscillation frequency fOSC (kHz) Triangular wave oscillation frequency fOSC (kHz) 560 540 520 500 480 460 440 −40 VCC = 12 V CTL = 5 V RT = 24 kΩ CT = 100 pF Triangular Wave Oscillation Frequency vs. Power supply voltage 560 540 520 500 480 460 440 0 5 10 15 20 Ta = +25 °C CTL = 5 V RT = 24 kΩ CT = 100 pF −20 0 +20 +40 +60 +80 +100 Ambient temperature Ta ( °C) Power supply voltage VCC (V) (Continued) 9 MB39A104 (Continued) Error Amplifier, Gain, Phase vs. Frequency 40 30 AV ϕ Ta = +25 °C VCC = 12 V 180 240 kΩ Phase φ (deg) Gain AV (dB) 20 10 0 −10 −20 −30 −40 100 1k 90 10 kΩ 1 µF + 0 IN 10 kΩ 2.4 kΩ (15) 10 11 (14) − + + 1.24 V OUT Error Amp1 (Error Amp2) 9 (16) −90 −180 10 k 100 k 1M 10 M Frequency f (Hz) Power Dissipation vs. Ambient Temperature 1000 Power dissipation PD (mW) 800 740 600 400 200 0 −40 −20 Ambient temperature Ta ( °C) 0 +20 +40 +60 +80 +100 10 MB39A104 ■ FUNCTIONS 1. DC/DC Converter Functions (1) Reference voltage block (REF) The reference voltage circuit generates a temperature-compensated reference voltage (5.0 V Typ) from the voltage supplied from the VCC terminal (pin 7). The voltage is used as the reference voltage for the IC’s internal circuitry. The reference voltage can supply a load current of up to 1 mA to an external device through the VREF terminal (pin 17). (2) Triangular-wave oscillator block (OSC) The triangular wave oscillator incorporates a timing capacitor and a timing resistor connected respectively to the CT terminal (pin 13) and RT terminal (pin 12) to generate triangular oscillation waveform amplitude of 1.5 V to 2.5 V. The triangular waveforms are input to the PWM comparator in the IC. (3) Error amplifier block (Error Amp1, Error Amp2) The error amplifier detects the DC/DC converter output voltage and outputs PWM control signals. In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input terminal of the error amplifier, enabling stable phase compensation to the system. Also, it is possible to prevent rush current at power supply start-up by connecting a soft-start capacitor with the CS1 terminal (pin 11) and CS2 terminal (pin 14) which are the non-inverted input terminal for Error Amp. The use of Error Amp for soft-start detection makes it possible for a system to operate on a fixed soft-start time that is independent of the output load on the DC/DC converter. (4) PWM comparator block (PWM Comp.1, PWM Comp.2) The PWM comparator is a voltage-to-pulse width modulator that controls the output duty depending on the input/ output voltage. The comparator keeps output transistor on while the error amplifier output voltage remain higher than the triangular wave voltage. (5) Output block (Drive1, Drive2) The output block is in the totem pole configuration, capable of driving an external P-channel MOS FET. (6) Bias voltage block (VH) This bias voltage circuit outputs VCC − 5 V(Typ) as minimum potential of the output circuit. In standby mode, this circuit outputs the potential equal to VCC. 11 MB39A104 2. Control Function When CTL terminal (pin 24) is “L” level, IC becomes the standby mode. The power supply current is 10 µA (Max) at the standby mode. On/Off Setting Conditions CTL Power L H OFF (Standby) ON (Operating) 3. Protective Functions (1) Timer-latch overcurrent protection circuit block (OCP) The timer-latch overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET ON resistor, actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, latch is set and OUT terminals (pin 3,22) of each channel are fixed at “H” level. And the circuit sets the latch to turn off the external FET. The detection current value can be set by resistor RLIM1 connected between the FET’s drain and the ILIM1 terminal (pin 5) and resistor RLIM2 connected between the drain and the ILIM2 terminal (pin 20). Changing connection enables to detect overcurrent at current sense resistor. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 6) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (Refer to “1. Setting Timer-Latch Overcurrent Protection Detection Current” in “■ABOUT TIMER-LATCH PROTECTION CIRCUIT”.) (2) Timer-latch short-circuit protection circuit (SCP Logic, SCP Comp.) The short-circuit detection comparator (SCP Comp.) detects the output voltage level of Error Amp, and if the error amp output voltage of any channel falls below the short-circuit detection voltage (3.1 V Typ), the timer circuits are actuated to start charging the external capacitor CSCP connected to the CSCP terminal (pin 8). When the capacitor voltage reaches about 0.73 V, the circuit is turned off the output transistor and sets the dead time to 100 %. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the “L” level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. (Refer to “2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit” in “■ABOUT TIMER-LATCH PROTECTION CIRCUIT”.) (3) Under voltage lockout protection circuit (UVLO) The transient state or a momentary decrease in supply voltage, which occurs when the power supply is turned on, may cause the IC to malfunction, resulting in breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage with respect to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the CSCP terminal (pin 8) at the “L” level. The circuit restores the output transistor to normal when the supply voltage reaches the threshold voltage of the undervoltage lockout protection circuit. (4) Protection circuit operating function table This table refers to output condition when protection circuit is operating. Operating circuit CS1 CS2 Overcurrent protection circuit Short-circuit protection circuit Under-voltage lockout 12 L L L L L L OUT1 H H H OUT2 H H H MB39A104 ■ SETTING THE OUTPUT VOLTAGE • Output Voltage Setting Circuit VO R1 (−INE2) 15 −INE1 R2 (CS2) 14 CS1 11 10 − + + 1.24 V Error Amp VO (V) = 1.24 R2 (R1 + R2) ■ SETTING THE TRIANGULAR OSCILLATION FREQUENCY The triangular oscillation frequency is determined by the timing capacitor (CT) connected to the CT terminal (pin 13), and the timing resistor (RT) connected to the RT terminal (pin 12). Moreover, it shifts more greatly than the calculated values according to the constant of timing resistor (RT) when the triangular wave oscillation frequency exceeds 1 MHz. Therefore, set it referring to “Triangular Wave Oscillation Frequency vs. Timing Resistor” and “Triangular Wave Oscillation Frequency vs. Timing Capacitor” in “■ TYPICAL CHARACTERISTICS”. Triangular oscillation frequency : fOSC fOSC (kHz) = : 1200000 CT (pF) × RT (kΩ) 13 MB39A104 ■ SETTING THE SOFT-START AND DISCHARGE TIMES To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 and CS2) to the CS1 terminal (pin 11) for channel 1 and the CS2 terminal (pin 14) for channel 2, respectively. When CTL terminal (pin 24) goes to “H” level and IC starts (VCC ≥ UVLO threshold voltage), the external softstart capacitors (CS1 and CS2) connected to CS1 and CS2 terminals are charged at 10 µA. The error amplifier output (FB1 (pin 9) , FB2 (pin 16) ) is determined by comparison between the lower one of the potentials at two non-inverted input terminals (1.24 V, CS1 terminal voltages) and the inverted input terminal voltage (−INE1 (pin 10) voltage, −INE2 (pin 15) voltage). The FB1 (FB2) terminal voltage is decided for the soft-start period by the comparison between 1.24 V in an internal reference voltage and the voltages of the CS1 (CS2) terminal. The DC/DC converter output voltage rises in proportion to the CS1 (CS2) terminal voltage as the soft-start capacitor connected to the CS1 (CS2) terminal is charged. The soft-start time is obtained from the following formula: Soft-start time: ts (time to output 100%) ts (s) = 0.124 × CS (µF) : CS1 (CS2) terminal voltage =5V : Error Amp block −INE1 (−INE2) voltage = 1.24 V : =0V : t Soft-start time (ts) 14 MB39A104 • Soft-Start Circuit VREF VO R1 −INE1 10 (−INE2) 15 10 µA R2 L priority Error Amp − CH ON/OFF signal L : ON, H : OFF 11 CS1 (CS2) CS1 (CS2) FB1 14 + + 1.24 V 9 UVLO (FB2) 16 15 MB39A104 ■ TREATMENT WITHOUT USING CS TERMINAL When not using the soft-start function, open the CS1 terminal (pin 11) and the CS2 terminal (pin 14) . • Without Setting Soft-Start Time “OPEN” 11 CS1 CS2 14 “OPEN” 16 MB39A104 ■ ABOUT TIMER-LATCH PROTECTION CIRCUIT 1. Setting Timer-Latch Overcurrent Protection Detection Current The overcurrent protection circuit is actuated upon completion of the soft-start period. When an overcurrent flows, the circuit detects the increase in the voltage between the FET’s drain and source using the external FET ON resistor (RON), actuates the timer circuit, and starts charging the capacitor CSCP connected to the CSCP terminal (pin 8). If the overcurrent remains flowing beyond the predetermined period of time, the circuit sets the latch to fix OUT terminals (pin 3, 22) at “H” level and turn off the external FET. The detection current value can be set by the resistors (RLIM1 and RLIM2) connected between the FET’s drain and the ILIM1 terminal (pin 5) and between the drain and the ILIM2 terminal (pin 20), respectively. The internal current (ILIM) can be set by the timing resistor (RT) connected to the RT terminal (pin 12). Time until activating timer circuit and setting latch is equal to short-circuit detection time in "2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit". Internal current value: ILIM ILIM (µA) = : 2700 RT (kΩ) Detection current value: IOCP IOCP (A) = : RLIM : RON : VIN : VO : fOSC : L: ILIM(A) × RLIM(Ω) RON (Ω) − (VIN(V) − VO(V)) × VO(V) 2 × VIN(V) × fOSC(Hz) × L(H) Overcurrent detection resistor External FET ON resistor Input voltage DC/DC converter output voltage Oscillation frequency Coil inductance To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. • Overcurrent detection circuit VIN Q1 L (VS2) 21 VS1 4 VO Current Protection Logic − + (ILIM2) 20 ILIM1 5 (RLIM) (1 µA) CSCP 8 SR Latch VREF Each Channel Drive UVLO 17 MB39A104 Overcurrent Protection Circuit: Range of Operation When an overcurrent flow occurs, if the increased voltage between the drain and source of the FET is detected by means of the external FET (Q1) resistor, operational stability is lost when the external FET (Q1) ON interval determined by the oscillation frequency, input voltage, and output voltage falls below 450 ns. Therefore, the circuit should be used within a range that ensures that the ON interval does not fall below 450ns, according to the following formula. ON interval 450 (ns) ≤ VO (V) VIN (V) × fOSC (Hz) If the ON interval of the external FET (Q1) is below 450ns, we recommend the use of an overcurrent detection resistor RS to detect overcurrent, as shown below. This example shows the range of operation of the overcurrent detection function with a setting of Vo = 3.3V. • Method to detect by current when external FET(Q1) is turned on VIN Overcurrent Detection Function Operating Range (Rs) Q1 1400 Error Amp 1600 fOSC (kHz) 21 4 VS1 (VS2) VO = set to 3.3 V 1200 1000 800 400 − + (ILIM2) 20 ILIM1 5 Operation Range Connect to RS when using RS 200 0 6 8 10 12 14 VCC (V) 16 18 20 • Method to detect by mean current (Possible to detect at 2 V or more of output voltage) VIN Q1 21 (VS2) 4 VS1 Error Amp RS Overcurrent Detection Function Operating Range 1600 1400 1200 fOSC (kHz) 1000 800 600 VO = set to 3.3 V Operation Range − + (ILIM2) 20 ILIM1 5 400 200 0 6 8 10 12 14 VCC (V) 16 18 20 18 MB39A104 2. Setting Time Constant for Timer-Latch Short-Circuit Protection Circuit Each channel uses the short-circuit detection comparator (SCP Comp.) to always compare the error amplifier′s output level to the reference voltage (3.1 V Typ). While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output remains at “L” level, and the CSCP terminal (pin 8) is held at “L” level. If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the output of the short-circuit detection comparator goes to “H” level. This causes the external shortcircuit protection capacitor CSCP connected to the CSCP terminal to be charged at 1 µA. Short-circuit detection time (tSCP) tSCP (s) = 0.73 × CSCP (µF) : When the capacitor CSCP is charged to the threshold voltage (VTH = 0.73 V), the latch is set and the external : FET is turned off (dead time is set to 100%). At this time, the latch input is closed and the CSCP terminal (pin 8) is held at “L” level. If a short-circuit is detected on either of the two channels, both channels are shut off. When the power supply is turned on back or VREF terminal (pin 17) voltage is less than 2.4 V (Min) by setting CTL terminal (pin 24) to “L” level, the latch is released. • Timer-latch short-circuit protection circuit (FB2) VO FB1 16 9 R1 (−INE2) 15 −INE1 10 − + Error Amp R2 (1.24 V) SCP Comp. + + − (3.1 V) (1 µA) To each channel Drive CSCP 8 VREF S R UVLO Latch 19 MB39A104 ■ TREATMENT WITHOUT USING CSCP TERMINAL When not using the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 8) to GND with the shortest distance. • Treatment without using CSCP GND 18 8 CSCP ■ RESETTING THE LATCH OF EACH PROTECTION CIRCUIT When the overcurrent, or short-circuit protection circuit detects each abnormality, it sets the latch to fix the output at the "L" level. To reset the actuated protection circuit, either the power supply turn off and on again or set the CTL terminal (pin 24) to the "L" level to lower the VREF terminal (pin 17) voltage to 2.4 V (Min) or less. 20 MB39A104 ■ I/O EQUIVALENT CIRCUIT 〈〈Reference voltage block〉〉 VCC 7 1.24 V ESD protection element + − 77.8 kΩ 24.8 kΩ GND 18 ESD protection element 17 VREF ESD protection element 104 kΩ GND GND 〈〈Control block〉〉 CTL 24 72 kΩ 〈〈Soft-start block〉〉 VREF (5.0 V) VCC CSX 〈〈Short-circuit detection block〉〉 VREF (5.0 V) 2 kΩ 〈〈Triangular wave oscillator block (RT) 〉〉 VCC (3.1 V) 1.35 V + − 12 RT 〈〈Triangular wave oscillator (CT) block〉〉 (3.1 V) 8 CSCP CT 13 GND GND GND 〈〈Error amplifier block (CH1, CH2) 〉〉 VCC VREF (5.0 V) −INEX 〈〈Overcurrent protection circuit block〉〉 VCC ILIMX VCCO VSX CSX 1.24 V FBX GND GND GNDO 〈〈PWM comparator block (CH1, CH2) 〉〉 VCC 〈〈Bias voltage block〉〉 VCC VCCO 〈〈Output block (CH1, CH2) 〉〉 VCCO 1 FBX DTCX CT 2 VH VH GNDO 23 O GND GND GNDO X : Each channel No. 21 22 Stepdown R10R11 A VREF Error Amp1 L priority 10 CH1 1 Q1 OUT1 3 + + VCCO L1 VO1 (5.0 V) A MB39A104 CH1 ON/OFF signal (Hiz : ON, L : OFF) 1.24 V L priority CS1 11 R8 + + D1 IO = 200 mA at VCCO = 12 V VS1 4 + 5 ILIM1 CH2 Drive2 P-ch IO = 200 mA at VCCO = 12 V H priority H: at SCP PWM + Comp.1 + Drive1 P-ch C12 9 1000 pF FB1 Current Protection Logic R4 6 R15R16 B VREF Error Amp2 + + 1.24 V L priority L priority ■ APPLICATION EXAMPLE DTC1 15 PWM + Comp.2 + OUT2 22 Stepdown B Q2 + L2 VO2 (3.3 V) CH2 ON/OFF signal (Hiz : ON, L : OFF) C14 16 1000 pF FB2 19 DTC2 SCP Comp. + + 3.1 V SCP Logic 8 C21 1000 pF UVLO H: UVLO release H: at OCP CS2 14 R13 D2 + VIN (7 V to 19 V) VS2 21 + 20 ILIM2 VH R5 Current Protection Logic CSCP 2.5 V 1.5 V VH Bias Voltage Error Amp Power Supply 2 GNDO 23 VCC 7 Error Amp Reference bias accuracy ± 1% 1.24 V VREF 5.0 V VR1 ON/OFF CTL Power OSC CTL 24 12 13 RT CT C1 100 pF 17 VREF 18 GND H : ON (Power ON) L : OFF (Standby mode) VTH = 1.4 V MB39A104 ■ PARTS LIST COMPONENT Q1, Q2 D1, D2 L1, L2 C1 C2, C6 C3, C7 C4, C8 C10, C11, C20 C12, C14, C21 C16, C17 R1 R4, R5 R8, R13 R9, R14 R10 R11 R15 R16 ITEM P-ch FET Diode Inductor Ceramics Condenser OS-CONTM Ceramics Condenser OS-CONTM Ceramics Condenser Ceramics Condenser Ceramics Condenser Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor SPECIFICATION VDS = −30 V, ID = −6 A VF = 0.42 V (Max) , at IF = 3 A 15 µH 100 pF 10 µF 10 µF 82 µF 0.1 µF 1000 pF 0.1 µF 24 kΩ 2.7 kΩ 220 kΩ 68 kΩ 150 kΩ 56 kΩ 100 kΩ 13 kΩ 3.6 A, 50 mΩ 50 V 20 V 25 V 6.3 V 50 V 50 V 50 V 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % VENDOR TOSHIBA ROHM SUMIDA TDK SANYO TDK SANYO TDK TDK TDK ssm ssm ssm ssm ssm ssm ssm ssm PARTS No. TPC8102 RB0530L-30 CDRH104R-150 C1608CH1H101J 20SVP10M C3225JF1E106Z 6SVP82M C1608JB1H104K C1608JB1H102K C1608JB1H104K RR0816P-243-D RR0816P-272-D RR0816P-224-D RR0816P-683-D RR0816P-154-D RR0816P-563-D RR0816P-104-D RR0816P-133-D Note : TOSHIBA ROHM SANYO TDK SUMIDA ssm : TOSHIBA Corporation : ROHM Co., Ltd : SANYO Electric Co., Ltd. : TDK Corporation : SUMIDA Electric Co., Ltd. : SUSUMU Co., Ltd. 23 MB39A104 ■ SELECTION OF COMPONENTS • P-ch MOS FET The P-ch MOSFET for switching use should be rated for at least 20% more than the maximum input voltage. To minimize continuity loss, use a FET with low RDS(ON) between the drain and source. For high input voltage and high frequency operation, on/off-cycle switching loss will be higher so that power dissipation must be considered. In this application, the Toshiba TPC8102 is used. Continuity loss, on/off switching loss, and total loss are determined by the following formulas. The selection must ensure that peak drain current does not exceed rated values, and also must be in accordance with overcurrent detection levels. Continuity loss : PC PC = ID 2 × RDS (ON) × Duty On-cycle switching loss : PS (ON) VD (Max) × ID × tr × fOSC PS (ON) = 6 Off-cycle switching loss : PS (OFF) VD (Max) × ID (Max) × tf × fOSC PS (OFF) = 6 Total loss : PT PT = PC + PS (ON) + PS (OFF) Example: Using the Toshiba TPC8102 CH1 Input voltage VIN (Max) = 19 V, output voltage VO = 5 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz, L = 15 µH, drain-source on resistance RDS (ON) = 50 mΩ, tr = tf = 100 ns. : : Drain current (Max) : ID (Max) VIN − VO ID (Max) = IO + ton 2L =3+ 19 − 5 2 × 15 × 10−6 × 1 × 0.263 500 × 103 = 3.25 (A) : Drain current (Min) : ID (Min) VIN − VO ID (Min) = IO − ton 2L =3− 19 − 5 2 × 15 × 10−6 × 1 × 0.263 500 × 103 = 2.75 (A) : 24 MB39A104 = ID 2 × RDS (ON) × Duty = 3 2 × 0.05 × 0.263 = 0.118 W : PS (ON) = = VD (Max) × ID × tr × fOSC 6 19 × 3 × 100 × 10−9 × 500 × 103 6 PC = 0.475 W : = = PS (OFF) VD (Max) × ID (Max) × tf × fOSC 6 19 × 3.25 × 100 × 10−9 × 500 × 103 6 = 0.515 W : PT = PC + PS (ON) + PS (OFF) = 0.118 + 0.475 + 0.515 : = 1.108 W : The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) . CH2 Input voltage VIN (Max) = 19 V output voltage VO = 3.3 V, drain current ID = 3 A, Oscillation frequency fOSC = 500 kHz, L = 15 µH, drain-source on resistance RDS (ON) = 50 mΩ, tr = tf = 100 ns. : : Drain current (Max) : ID (Max) VIN − VO ID (Max) = IO + ton 2L =3+ 19 − 3.3 2 × 15 × 10−6 × 1 × 0.174 500 × 103 = 3.18 (A) : Drain current (Min) : ID (Min) VIN − VO ton ID (Min) = IO − 2L =3− 19 − 3.3 2 × 15 × 10−6 × 1 × 0.174 500 × 103 = 2.82 (A) : 25 MB39A104 PC = ID 2 × RDS (ON) × Duty = 3 2 × 0.05 × 0.174 VD (Max) × ID × tr × fOSC 6 19 × 3 × 100 × 10−9 × 500 × 103 6 = 0.078 W : PS (ON) = = = 0.475 W : PS (OFF) = = VD (Max) × ID (Max) × tf × fOSC 6 19 × 3.18 × 100 × 10−9 × 500 × 103 6 = 0.504 W : PT = PC + PS (ON) + PS (OFF) = 0.078 + 0.475 + 0.504 : = 1.057 W : The above power dissipation figures for the TPC8102 are satisfied with ample margin at 2.4 W (Ta = +25 °C) . • Inductors In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor, but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value, which will enable continuous operation under light loads. Note that if the inductance value is too high, however, direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at the point where efficiency is greatest. Note also that the DC superimposition characteristics become worse as the load current value approaches the rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing loss of efficiency. The selection of rated current value and inductance value will vary depending on where the point of peak efficiency lies with respect to load current. Inductance values are determined by the following formulas. The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the load current or less. Inductance value : L 2 (VIN − VO) ton L≥ IO 26 MB39A104 Example: CH1 L≥ ≥ 2 (VIN − VO) ton IO 2 × (19 − 5) 1 × × 0.263 IO 500 × 103 ≥ 4.91 µH CH2 L≥ ≥ 2 (VIN − VO) ton IO 2 × (19 − 3.3) 1 × × 0.174 IO 500 × 103 ≥ 3.64 µH Inductance values derived from the above formulas are values that provide sufficient margin for continuous operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore necessary to determine the load level at which continuous operation becomes possible. In this application, the Sumida CDRH104R-150 is used. At 15 µH, the load current value under continuous operating conditions is determined by the following formula. Load current value under continuous operating conditions : IO VO IO ≥ toff 2L Example: Using the CDRH104R-150 15 µH (allowable tolerance ±30%) , rated current = 3.6 A CH1 IO ≥ ≥ VO 2L toff × 1 × (1 − 0.263) 500 × 103 5 2 × 15 × 10−6 ≥ 245.7 mA CH2 IO ≥ ≥ VO 2L toff × 1 × (1 − 0.174) 500 × 103 3.3 2 × 15 × 10−6 ≥ 181.7 mA 27 MB39A104 To determine whether the current through the inductor is within rated values, it is necessary to determine the peak value of the ripple current as well as the peak-to-peak values of the ripple current that affect the output ripple voltage. The peak value and peak-to-peak value of the ripple current can be determined by the following formulas. Peak value : IL VIN − VO IL ≥ IO + 2L ton Peak-to-peak value : ∆IL VIN − VO ∆IL = ton L Example: Using the CDRH104R-150 15 µH (allowable tolerance ±30%) , rated current = 3.6 A Peak value: CH1 IL ≥ IO + ≥3+ VIN − VO 2L ton 19 − 5 1 × 0.263 × 2 × 15 × 10−6 500 × 103 ≥ 3.25 A CH2 IL ≥ IO + ≥3+ VIN − VO 2L ton × 1 × 0.174 500 × 103 19 − 3.3 2 × 15 × 10−6 ≥ 3.18 A Peak-to-peak value: CH1 ∆IL = = VIN − VO L ton 19 − 5 1 × × 0.263 15 × 10−6 500 × 103 = 0.491 A CH2 ∆IL = = VIN − VO L ton 19 − 3.3 1 × × 0.174 15 × 10−6 500 × 103 = 0.364 A 28 MB39A104 • Flyback diode The flyback diode is generally used as a Shottky barrier diode (SBD) when the reverse voltage to the diode is less than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recovery time, and lower forward voltage, and is ideal for achieving high efficiency. As long as the DC reverse voltage is sufficiently higher than the input voltage, the average current flowing through the diode is within the average output current level, and peak current is within peak surge current limits, there is no problem. In this application the Rohm RB053L-30 is used. The diode average current and diode peak current can be calculated by the following formulas. Diode mean current : IDi VO ) IDi ≥ IO × (1 − VIN Diode peak current : IDip VO IDip ≥ (IO + toff) 2L Example: Using the Rohm RB053L-30 VR (DC reverse voltage) = 30 V, average output voltage = 3.0 A, peak surge current = 70 A, VF (forward voltage) = 0.42 V, IF = 3.0 A CH1 IDi ≥ IO × (1 − VO ) VIN ≥ 3 × (1 − 0.263) ≥ 2.21 A CH2 IDi ≥ IO × (1 − VO ) VIN ≥ 3 × (1 − 0.174) ≥ 2.48 A CH1 IDip ≥ (IO + ≥ 3.24 A CH2 IDip ≥ (IO + ≥ 3.18 A VO toff) 2L VO toff) 2L 29 MB39A104 • Smoothing Capacitor The smoothing capacitor is an indispensable element for reducing ripple voltage in output. In selecting a smoothing capacitor it is essential to consider equivalent series resistance (ESR) and allowable ripple current. Higher ESR means higher ripple voltage, so that to reduce ripple voltage it is necessary to select a capacitor with low ESR. However, the use of a capacitor with low ESR can have substantial effects on loop phase characteristics, and therefore requires attention to system stability. Care should also be taken to use a capacity with sufficient margin for allowable ripple current. This application uses the (OS-CON TM) 6SVP82M made by SANYO. The ESR, capacitance value, and ripple current can be calculated from the following formulas. Equivalent Series Resistance : ESR 1 ∆VO − ESR ≤ ∆IL 2πfCL Capacitance value : CL ∆I L CL ≥ 2πf (∆VO − ∆IL × ESR) Ripple current : ICLrms (VIN − VO) ton ICLrms ≥ 2√3L Example: Using the 6SVP82M Rated voltage = 6.3 V, ESR = 50 mΩ, maximum allowable ripple current = 1570 mArms Equivalent series resistance CH1 ESR ≤ ≤ ∆V O ∆I L 0.050 0.491 − − 1 2πfCL 1 2π × 500 × 103 × 82 × 10−6 ≤ 98.0 mΩ 30 MB39A104 CH2 ESR ≤ ≤ ∆VO ∆IL 0.033 0.364 − 1 2πfCL − 1 2π × 500 × 103 × 82 × 10−6 ≤ 86.8 mΩ Capacitance value CH1 CL ≥ ≥ ∆I L 2πf (∆VO − ∆IL × ESR) 0.491 2π × 500 × 103 × (0.050 − 0.491 × 0.05) ≥ 6.14 µF CH2 CL ≥ ≥ ∆I L 2πf (∆VO − ∆IL × ESR) 0.364 2π × 500 × 103 × (0.033 − 0.364 × 0.05) ≥ 7.83 µF Ripple current CH1 ICLrms ≥ ≥ (VIN − VO) ton 2√3L (19 − 5) × 0.263 2√3 × 15 × 10−6 × 500 × 103 ≥ 141.7 mArms CH2 ICLrms ≥ ≥ (VIN − VO) ton 2√3L (19 − 3.3) × 0.174 2√3 × 15 × 10−6 × 500 × 103 ≥ 105.1 mArms 31 MB39A104 ■ REFERENCE DATA Conversion Efficiency vs. Load Current (CH1) 100 90 Conversion efficiency η (%) 80 70 VIN = 7 V VIN = 10 V VIN = 12 V VIN = 19 V 60 50 40 Ta = +25 °C 5 V Output SW1 = OFF SW2 = ON 100 m 1 10 30 10 m Load current IL (A) Conversion Efficiency vs. Load Current (CH2) 100 Conversion efficiency η (%) 90 80 70 VIN = 7 V VIN = 10 V VIN = 12 V VIN = 19 V 60 50 40 Ta = +25 °C 3.3 V Output SW1 = ON SW2 = OFF 100 m 1 10 30 10 m Load current IL (A) (Continued) 32 MB39A104 (Continued) Switching Wave Form (CH1) VG (V) 15 10 5 VS (V) 0 15 10 5 0 Ta = +25 °C VIN = 12 V CTL = 5 V VO = 5 V RL = 1.67 Ω 0 1 2 3 4 5 6 7 8 9 10 t (µs) Switching Wave Form (CH2) VG (V) 15 10 5 VS (V) 0 15 10 5 0 Ta = +25 °C VIN = 12 V CTL = 5 V VO = 3.3 V RL = 1.1 Ω 0 1 2 3 4 5 6 7 8 9 10 t (µs) 33 MB39A104 ■ USAGE PRECAUTIONS • Printed circuit board ground lines should be set up with consideration for common impedance. • Take appropriate static electricity measures. • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. • Do not apply negative voltages. • The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause malfunction. ■ ORDERING INFORMATION Part number MB39A104PFV-❏❏❏E1 Package 24-pin plastic SSOP (FPT-24P-M03) Remarks Lead Free version ■ EV BOARD ORDERING INFORMATION EV board part No. MB39A104EVB EV board version No. Board Rev. 1.0 Remarks SSOP-24P ■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added “E1” at the end of the part number. ■ MARKING FORMAT (Lead Free version) 3 9A1 04 XXXX XXX E1 INDEX Lead Free version 34 MB39A104 ■ LABELING SAMPLE (LEAD FREE VERSION) lead-free mark JEITA logo JEDEC logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 G Pb (3N)2 1561190005 107210 QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN 1/1 MB123456P - 789 - GE1 0605 - Z01A 1000 1561190005 Lead Free version 35 MB39A104 ■ MB39A104PFV-❏❏❏E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL Item Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions Condition IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 8 days Please processes within 8 days after baking (125 °C, 24H) 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) [Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) H rank : 260 °C Max 260 °C 255 °C 170 °C to 190 °C RT (b) (c) (d) (e) (a) (d') (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60 s to 180 s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10 s or less : Temperature 230 °C or more, 40 s or less or Temperature 225 °C or more, 60 s or less or Temperature 220 °C or more, 80 s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 °C Max Times : 5 s max/pin 36 MB39A104 ■ PACKAGE DIMENSION 24-pin plastic SSOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.65 mm 5.6 × 7.75 mm Gullwing Plastic mold 1.45 mm MAX 0.12 g P-SSOP24-5.6×7.75-0.65 (FPT-24P-M03) Code (Reference) 24-pin plastic SSOP (FPT-24P-M03) *17.75±0.10(.305±.004) 24 13 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.03 (.007±.001) *2 5.60±0.10 INDEX 7.60±0.20 (.220±.004) (.299±.008) Details of "A" part 1.25 –0.10 .049 –.004 +0.20 +.008 (Mounting height) 0.25(.010) 0~8˚ 1 12 "A" M 0.65(.026) 0.24 .009 +0.08 –0.07 +.003 –.003 0.13(.005) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F24018S-c-4-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. 37 MB39A104 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0608