MB39A123

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27257-1E ASSP For Power Supply Applications 6 ch DC/DC Converter IC with Synchronous Rectification MB39A123 ■ DESCRIPTION MB39A123 is a 6-channel DC/DC converter IC using pulse width modulation (PWM) , and it is suitable for up conversion, down conversion, and up/down conversion. MB39A123 is built in 6 channels into BCC-48++/LQFP48P package and this IC can control and soft-start at each channel. MB39A123 is suitable for power supply of high performance potable instruments such as a digital still camera (DSC). ■ FEATURES • • • • • • • • • • • • • • Supports for step-down with synchronous rectification (ch.1) Supports for step-down and up/down Zeta conversion (ch.2 to ch.4) Supports for step-up and up/down Sepic conversion (ch.5, ch.6) Negative voltage output (Inverting amplifier) (ch.4) Low voltage start-up (ch.5, ch.6) : 1.7 V Power supply voltage range : 2.5 V to 11 V Reference voltage : 2.0 V ± 1% Error amplifier reference voltage : 1.0 V ± 1% (ch.1) , 1.23 V ± 1% (ch.2 to ch.6) Oscillation frequency range : 200 kHz to 2.0 MHz Standby current : 0 µA (Typ) Built-in soft-start circuit independent of loads Built-in totem-pole type output for MOS FET Short-circuit detection capability by external signal (−INS terminal) Two types of packages (BCC-48 pin : 1 type, LQFP-48 pin : 1 type) ■ APPLICATIONS • Digital still camera(DSC) • Digital video camera(DVC) • Surveillance camera etc. Copyright©2006 FUJITSU LIMITED All rights reserved MB39A123 ■ PIN ASSIGNMENTS (TOP VIEW) −INE3 −INE2 −INE1 DTC3 DTC2 VCC CS2 CS1 CS3 FB3 FB2 CTL 1 48 47 46 45 44 43 42 41 40 39 38 37 CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 −INS VREF GND RT CT 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 FB1 VCCO OUT1-1 OUT1-2 OUT2 OUT3 OUT4 OUT5 OUT6 GNDO CS6 −INE6 FB6 13 14 15 16 17 18 19 20 21 22 23 24 25 OUTA −INE4 −INA CSCP −INE5 FB4 CS4 CS5 DTC4 FB5 DTC5 (LCC-48P-M08) DTC6 (Continued) 2 MB39A123 (Continued) (TOP VIEW) −INE3 −INE2 −INE1 38 DTC3 DTC2 VCC CS3 CS2 CS1 FB3 FB2 48 47 46 45 44 43 42 41 40 39 37 CTL CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 −INS VREF GND RT CT 1 2 3 4 5 6 7 8 9 10 11 12 FB1 36 35 34 33 32 31 30 29 28 27 26 25 VCCO OUT1-1 OUT1-2 OUT2 OUT3 OUT4 OUT5 OUT6 GNDO CS6 −INE6 FB6 13 14 15 16 17 18 19 20 21 22 23 24 CSCP DTC4 FB4 −INE4 CS4 OUTA −INA CS5 −INE5 FB5 DTC5 (FPT-48P-M26) DTC6 3 MB39A123 ■ PIN DESCRIPTIONS Block name Pin No. Pin name 37 38 39 ch.1 35 34 43 42 ch.2 41 40 33 44 45 ch.3 46 47 32 14 15 16 ch.4 17 31 19 18 23 22 ch.5 21 20 30 24 25 ch.6 26 27 29 OUT1-1 OUT1-2 DTC2 FB2 −INE2 CS2 OUT2 DTC3 FB3 −INE3 CS3 OUT3 DTC4 FB4 −INE4 CS4 OUT4 −INA OUTA DTC5 FB5 −INE5 CS5 OUT5 DTC6 FB6 −INE6 CS6 OUT6 O O I O I ⎯ O I O I ⎯ O I O I ⎯ O I O I O I ⎯ O I O I ⎯ O FB1 −INE1 CS1 I/O O I ⎯ Description ch.1• Error amplifier output terminal ch.1• Error amplifier inverted input terminal ch.1• Soft-start setting capacitor connection terminal ch.1• P-ch drive output terminal (External main side FET gate driving) ch.1• N-ch drive output terminal (External synchronous rectification side FET gate driving) ch.2 • Dead time control terminal ch.2 • Error amplifier output terminal ch.2 • Error amplifier inverted input terminal ch.2 • Soft-start setting capacitor connection terminal ch.2 • P-ch drive output terminal ch.3 • Dead time control terminal ch.3 • Error amplifier output terminal ch.3 • Error amplifier inverted input terminal ch.3 • Soft-start setting capacitor connection terminal ch.3 • P-ch drive output terminal ch.4 • Dead time control terminal ch.4 • Error amplifier output terminal ch.4 • Error amplifier inverted input terminal ch.4 • Soft-start setting capacitor connection terminal ch.4 • P-ch drive output terminal Inverting amplifier input terminal Inverting amplifier output terminal ch.5 • Dead time control terminal ch.5 • Error amplifier output terminal ch.5 • Error amplifier inverted input terminal ch.5 • Soft-start setting capacitor connection terminal ch.5 • N-ch drive output terminal ch.6 • Dead time control terminal ch.6 • Error amplifier output terminal ch.6 • Error amplifier inverted input terminal ch.6 • Soft-start setting capacitor connection terminal ch.6 • N-ch drive output terminal (Continued) 4 MB39A123 (Continued) Block name OSC Pin No. 12 11 1 2 3 4 Control 5 6 7 13 8 36 48 Power 9 28 10 Pin name CT RT CTL CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 CSCP −INS VCCO VCC VREF GNDO GND I/O ⎯ ⎯ I I I I I I I ⎯ I ⎯ ⎯ O ⎯ ⎯ Description Triangular wave frequency setting capacitor connection terminal Triangular wave frequency setting resistor connection terminal Power supply control terminal ch.1 control terminal ch.2 control terminal ch.3 control terminal ch.4 control terminal ch.5 control terminal ch.6 control terminal Short-circuit detection circuit capacitor connection terminal Short-circuit detection comparator inverted input terminal Drive output block power supply terminal Power supply terminal Reference voltage output terminal Drive output block ground terminal Ground terminal 5 MB39A123 ■ BLOCK DIAGRAM Step-down (Synchronous Rectification) A A −INE1 38 L priority VREF 1.1 µA − + + Error Amp1 + − 36 VCCO CS1 39 PWM Comp.1 (1.0 V) FB1 37 Reference voltage 1.0 V ± 1 % Dead Time Io = 300 mA at VCCO = 7 V Drive1-1 P-ch Vo1 (1.2 V) 35 OUT1-1 Drive1-2 N-ch 34 OUT1-2 Step-down Dead Time (td = 50 ns) Io = 300 mA at VCCO = 7 V B Vo2 (2.5 V) B −INE2 L priority 41 VREF 1.1 µA − + + Error Amp2 Max Duty VREF L priority 92 % ± 5 % PWM + + − CS2 Comp.2 40 Drive2 P-ch 33 OUT2 1.23 V FB2 DTC2 −INE3 42 43 Reference voltage 1.23 V ± 1 % L priority VREF 1.1 µA − + + Io = 300 mA at VCCO = 7 V Step-down C Vo3 (3.3 V) C 46 Error Amp3 Max Duty VREF 92 % ± 5 % L priority + + − CS3 47 PWM Comp.3 Drive3 P-ch 32 OUT3 1.23 V FB3 DTC3 −INA 45 44 Reference voltage 1.23 V ± 1 % − + Io = 300 mA at VCCO = 7 V D 19 OUTA 18 INVAmp Inverting D Vo4 (−7.5 V) −INE4 L priority 16 VIN (5 V-11 V) VREF 1.1 µA − + + Error Amp4 L priority Max Duty VREF PWM 92 % ± 5 % + + − CS4 Comp.4 17 Drive4 P-ch 31 OUT4 1.23 V FB4 DTC4 15 14 Reference voltage 1.23 V ± 1 % L priority VREF 1.1 µA − + + Io = 300 mA at VCCO = 7 V Step-up E −INE5 CS5 21 Error Amp5 Max Duty VREF L priority 92 % ± 5 % PWM + + − E Vo5 (15 V) Comp.5 20 Drive5 N-ch 30 OUT5 1.23 V FB5 22 DTC5 23 −INE6 Reference voltage 1.23 V ± 1 % L priority VREF 1.1 µA − + + Io = 300 mA at VCCO = 7 V Transformer Max Duty VREF L priority 92 % ± 5 % PWM + + − F Vo6-1 (15 V) Vo6-2 (5.0 V) F 26 Error Amp6 CS6 Comp.6 27 Drive6 N-ch 29 28 OUT6 GNDO 1.23 V FB6 DTC6 25 24 Reference voltage 1.23 V ± 1 % VREF Io = 300 mA at VCCO = 7 V Short-circuit detection signal (L: at short-circuit) Charge current 1 µA −INS 8 − SCP Comp. SCP H:at SCP 1V CSCP 13 + Error Amp power supply SCP Comp. power supply 0.9 V H:UVLO release H:ON L:OFF VTH = 1.0 V CTL1 CTL2 CTL4 CTL5 CTL6 2 3 0.4 V OSC UVLO1 UVLO2 Error Amp reference 48 VCC bias 1.0 V/1.23 V VREF Precision ± 0.8 % 10 CTL3 4 5 6 7 CHCTL VR Power ON/OFF CTL CTL 1 H:ON (Power ON) L:OFF(Standby mode) VTH = 1.0 V 2.0 V 11 12 9 RT CT Precision ± 0.5 % (2.0 MHz) VREF Precision ±1% GND > PKG:BCC-48++ :LQFP-48P 6 MB39A123 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Output current Symbol VCC IO Conditions VCC, VCCO terminals OUT1-1, OUT1-2, OUT2 to OUT6 terminals OUT1-1, OUT1-2, OUT2 to OUT6 terminals Duty ≤ 5% Ta ≤ +25 °C (BCC-48++) Ta ≤ +25 °C (LQFP-48P) ⎯ Rating Min ⎯ ⎯ ⎯ ⎯ ⎯ −55 Max 12 20 Unit V mA Peak output current IOP 400 1670* 2000* +125 mA mW mW °C Power dissipation Storage temperature PD TSTG * : When mounted on a 117 mm × 84 mm × 0.8 mm FR-4 boards. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 7 MB39A123 ■ RECOMMENDED OPERATING CONDITIONS Parameter Start power supply voltage Power supply voltage Reference voltage output current Symbol VCC VCC IREF VINE VDTC Control input voltage Output current VCTL IO Conditions ch.5, ch.6, VCC, VCCO terminals VCC, VCCO terminals VREF terminal −INE1 to −INE6 terminals Input voltage −INA terminal −INS terminal DTC2 to DTC6 terminals CTL, CTL1 to CTL6 terminals OUT1-1, OUT1-2, OUT2 to OUT6 terminals OUT1-1, OUT1-2, OUT2 to OUT6 terminals connection FET fosc = 2 MHz ⎯ ⎯ ⎯ CS1 to CS6 terminals ⎯ ⎯ ⎯ Value Min 1.7 2.5 −1 0 − 0.2 0 0 0 −15 Typ ⎯ 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max 11 11 0 VCC − 0.9 VCC − 1.8 VREF VREF 11 +15 Unit V V mA V V V V V mA Total gate charge of external FET Qg ⎯ 0.2 27 3.0 ⎯ ⎯ ⎯ −30 2.6 7.5 nC Oscillation frequency Timing capacitor Timing resistor Soft-start capacitor Short-circuit detection capacitor Reference voltage output capacitor Operating ambient temperature fOSC CT RT CS CSCP CREF Ta 1.0 100 6.8 0.1 0.1 0.1 +25 2.0 680 39 1.0 1.0 1.0 +85 MHz pF kΩ µF µF µF °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 8 MB39A123 ■ ELECTRICAL CHARACTERISTICS (VCC = VCCO = 4 V, Ta = +25 °C) Parameter Symbol VREF1 Output voltage Reference Voltage Block [VREF] Input stability Load stability Temperature stability Short-circuit output current Under voltage lockout protection circuit Block (ch.1 to ch.4) [UVLO1] Under voltage lockout protection circuit Block (ch.5, ch.6) [UVLO2] Threshold voltage Hysteresis width Reset voltage Threshold voltage Hysteresis width Reset voltage VREF2 VREF3 Line Load ∆VREF/ VREF IOS VTH1 VH1 VRST1 VTH2 VH2 VRST2 VTH ICSCP fosc1 fosc2 ∆fOSC/ fOSC ∆fOSC/ fOSC Pin No. 9 9 9 9 9 9 9 35 35 35 30 30 30 13 13 29 to 35 29 to 35 29 to 35 VCC = ⎯ ⎯ CT = 100 pF, RT = 6.8 kΩ CT = 100 pF, RT = 6.8 kΩ VCC = 2.5 V to 11 V CT = 100 pF, RT = 6.8 kΩ VCC = 2.5 V to 11 V* CT = 100 pF, RT = 6.8 kΩ Ta = 0 °C to +85 °C* VCC = VCC = ⎯ Conditions VREF = 0 mA VCC = 2.5 V to 11 V VREF = 0 mA to −1 mA VCC = 2.5 V to 11 V* VREF = 0 mA to −1 mA* Ta = 0 °C to +85 °C* VREF = 0 V* VCC = ⎯ Value Min 1.98 Typ 2.00 Max 2.02 Unit V V V mV mV % mA V V V V V V V µA MHz 1.975 2.000 2.025 1.975 2.000 2.025 ⎯ ⎯ ⎯ ⎯ 1.7 0.05 1.55 1.35 0.02 1.27 0.65 −1.4 0.95 0.945 ⎯ ⎯ 2 2 0.20 −130 1.8 0.1 1.7 1.5 0.05 1.45 0.70 −1.0 1.0 1.0 1.0 ⎯ ⎯ ⎯ ⎯ 1.9 0.2 1.85 1.65 0.1 1.63 0.75 −0.6 1.05 Threshold Short-circuit voltage detection Block Input source [SCP] current Oscillation frequency Triangular Wave Oscillator Block [OSC] Frequency Input stability Frequency temperature stability Soft-Start Block Charge (ch.1 to ch.6) current [CS1 to CS6] 1.055 MHz ⎯ ⎯ % % 29 to 35 1.0 ICS 17,20,27, CS1 to CS6 = 0 V 39,40,47 −1.45 −1.1 −0.75 µA (Continued) 9 MB39A123 (VCC = VCCO = 4 V, Ta = +25 °C) Parameter Symbol Pin No. VTH1 VTH2 ∆VTH/ VTH IB AV BW VOH VOL ISOURCE ISINK 38 38 38 38 37 37 37 37 37 37 16, 21, 26, 41, 46 16, 21, 26, 41, 46 16, 21, 26, 41, 46 16, 21, 26, 41, 46 15, 22, 25, 42, 45 15, 22, 25, 42, 45 15, 22, 25, 42, 45 15, 22, 25, 42, 45 FB1 = 0.65 V FB1 = 0.65 V VCC = 2.5 V to 11 V Ta = +25 °C VCC = 2.5 V to 11 V Ta = 0 °C to +85 °C* Ta = 0 °C to +85 °C* Conditions VCC = 2.5 V to 11 V Ta = +25 °C VCC = 2.5 V to 11 V Ta = 0 °C to +85 °C* Ta = 0 °C to +85 °C* −INE1 = 0 V DC* AV = 0 dB* ⎯ ⎯ Value Min Typ Max Unit V V % nA dB MHz V mV mA µA V Reference voltage Temperature stability Input bias current 0.990 1.000 1.010 0.988 1.000 1.012 ⎯ −120 ⎯ ⎯ 1.7 ⎯ ⎯ 150 0.1 −30 100 1.4 1.9 40 −2 200 ⎯ ⎯ ⎯ ⎯ ⎯ 200 −1 ⎯ Error Amp Block Voltage gain (ch.1) [Error Amp1] Frequency bandwidth Output voltage Output source current Output sink current VTH3 Reference voltage VTH4 ∆VTH/ VTH 1.217 1.230 1.243 1.215 1.230 1.245 V Temperature stability Input bias Error Amp Block current (ch.2 to ch.6) [Error Amp2 to Error Amp6] Voltage gain ⎯ 0.1 ⎯ % IB −INE2 to −INE6 = 0 V −120 −30 ⎯ nA AV DC* ⎯ 100 ⎯ dB Frequency bandwidth BW AV = 0 dB* ⎯ 1.4 ⎯ MHz VOH Output voltage VOL ⎯ 1.7 1.9 ⎯ V ⎯ ⎯ 40 200 mV (Continued) 10 MB39A123 (VCC = VCCO = 4 V, Ta = +25 °C) Parameter Output source Error Amp Block current (ch.2 to ch.6) [Error Amp2 to Output sink Error Amp6] current Input offset voltage Input bias current Voltage gain Inverting Amp Block (ch.4) [Inv Amp] Frequency bandwidth Output voltage Output source current Output sink current PWM Comparator Block (ch.1) [PWM Comp.1] PWM Comparator Block (ch.2 to ch.6) [PWM Comp.2 to PWM Comp.6] Symbol Pin No. 15, 22, 25, 42, 45 15, 22, 25, 42, 45 18 19 18 18 18 18 18 18 34, 35 34, 35 Conditions Value Min ⎯ Typ −2 Max −1 Unit ISOURCE FB2 to FB6 = 0.65 V mA ISINK FB2 to FB6 = 0.65 V OUTA = 1.23V − INA = 0V DC* AV = 0 dB* ⎯ ⎯ OUTA = 1.23V OUTA = 1.23V Duty cycle = 0% Duty cycle = 100% 150 −10 −120 ⎯ ⎯ 1.7 ⎯ ⎯ 150 0.35 0.85 0.35 0.85 87 ⎯ 75 ⎯ ⎯ * * ⎯ ⎯ 200 ⎯ + 10 ⎯ ⎯ ⎯ ⎯ 200 −1 ⎯ 0.45 0.95 0.45 0.95 97 −75 ⎯ 27 27 ⎯ ⎯ µA mV nA dB MHz V mV mA µA V V V V % VIO IB AV BW VOH VOL ISOURCE ISINK VT0 0 −30 100 1.0 1.9 40 −2 200 0.4 0.9 0.4 0.9 92 −130 130 18 18 50 50 Threshold voltage VT100 VT0 VT100 Dtr Threshold voltage Maximum duty cycle Output source current 29 to 33 Duty cycle = 0% 29 to 33 Duty cycle = 100% 29 to 33 CT = 100 pF, RT = 6.8 kΩ Duty ≤ 5% OUT = 0 V Duty ≤ 5% OUT = 4 V ISOURCE ISINK ROH ROL tD1 tD2 29 to 35 29 to 35 mA mA Ω Ω ns ns Output Block (ch.1 to ch.6) Output on [Drive1 to Drive6] resistor Output sink current 29 to 35 OUT = − 15 mA 29 to 35 OUT = 15 mA 34, 35 34, 35 OUT2 OUT1 − OUT1 − OUT2 Dead time (Continued) 11 MB39A123 (Continued) (VCC = VCCO = 4 V, Ta = +25 °C) Parameter Short-Circuit Detection Comparator Block [SCP Comp.] Threshold voltage Input bias current Output on condition Output off condition Input current Standby current Power supply current * : Standard design value Symbol Pin No. VTH IB VIH VIL ICTLH ICTLL ICCS ICCSO ICC 35 8 1 to 7 1 to 7 1 to 7 1 to 7 48 36 48 −INS = 0 V CTL, CTL1 to CTL6 CTL, CTL1 to CTL6 CTL, CTL1 to CTL6 = 3 V CTL, CTL1 to CTL6 = 0 V CTL, CTL1 to CTL6 = 0 V CTL = 0 V CTL = 3 V Conditions ⎯ Value Min 0.97 −25 1.5 0 5 ⎯ ⎯ ⎯ ⎯ Typ 1.00 −20 ⎯ ⎯ 30 ⎯ 0 0 4.5 Max 1.03 −17 11 0.5 60 1 2 1 6.8 Unit V µA V V µA µA µA µA mA Control Block (CTL, CTL1 to CTL6) [CTL, CHCTL] General 12 MB39A123 ■ TYPICAL CHARACTERISTICS Power Supply Current vs. Power Supply Voltage 5 Reference Voltage vs. Power Supply Voltage 5 Power Supply Current ICC (mA) Reference Voltage VREF (V) Ta = + 25 °C CTL = 3 V 4 4 Ta = + 25 °C CTL = 3 V VREF = 0 mA 3 3 2 2 1 1 0 0 2 4 6 8 10 12 0 0 2 4 6 8 10 12 Power Supply Voltage VCC (V) Reference Voltage vs. Operating Ambient Temperature 2.05 Power Supply Voltage VCC (V) Reference Voltage VREF (V) 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 −40 −20 0 +20 +40 +60 VCC = 4 V CTL = 3 V VREF = 0 mA Operating Ambient Temperature Ta ( °C) Reference Voltage vs. CTL Terminal Voltage +80 +100 CTL Terminal Current vs. CTL Terminal Voltage 200 5.0 CTL Terminal Current ICTL (µA) Reference Voltage VREF (V) 4.0 Ta = + 25 °C VCC = 4 V VREF = 0 mA Ta = + 25 °C VCC = 4 V 150 3.0 100 2.0 50 1.0 0.0 0 2 4 6 8 10 12 0 0 2 4 6 8 10 12 CTL Terminal Voltage VCTL (V) CTL Terminal Voltage VCTL (V) (Continued) 13 MB39A123 Triangular Wave Oscillation Frequency vs. Timing Resistor 10000 Triangular Wave Oscillation Frequency vs. Timing Capacity 10000 Triangular Wave Oscillation Frequency fOSC (kHz) 1000 CT = 27 pF CT = 100 pF CT = 680 pF CT = 220 pF 100 Triangular Wave Oscillation Frequency fOSC (kHz) Ta = + 25 °C VCC = 4 V CTL = 3 V Ta = + 25 °C VCC = 4 V CTL = 3 V 1000 RT = 3 kΩ RT = 6.8 kΩ 100 RT = 39 kΩ RT = 13 kΩ 10 1 Timing Resistor RT (kΩ) 10 100 1000 10 10 100 1000 10000 Timing Capacity CT (pF) Triangular Wave Upper and Lower Limit Voltage vs. Operating Ambient Temperature Triangular Wave Upper and Lower Limit Voltage VCT (V) 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 Lower limit 0.30 0.20 −40 −20 0 +20 +40 +60 +80 +100 VCC = 4 V CTL = 3 V RT = 6.8 kΩ CT = 100 pF Triangular Wave Upper and Lower Limit Voltage vs. Triangular Wave Oscillation Frequency Triangular Wave Upper and Lower Limit Voltage VCT (V) 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 Lower limit 0.30 0.20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 Ta = + 25 °C VCC = 4 V CTL = 3 V RT = 6.8 kΩ Upper limit Upper limit Triangular Wave Oscillation Frequency fOSC (kHz) Triangular Wave Oscillation Frequency vs. Operating Ambient Temperature 1100 Operating Ambient Temperature Ta ( °C) Triangular Wave Oscillation Frequency fOSC (kHz) 1080 1060 1040 1020 1000 980 960 940 920 900 −40 VCC = 4 V CTL = 3 V RT = 6.8 kΩ CT = 100 pF −20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature Ta ( °C) (Continued) 14 MB39A123 ON Duty Cycle vs. DTC Terminal Voltage 100 95 fosc = 200 kHz Maximum Duty Cycle vs. Oscillation Frequency 100 Maximum Duty Cycle Dtr (%) ON Duty Cycle Dtr (%) 90 85 80 75 70 65 60 55 50 0.6 Ta = + 25 °C VCC = CTL = 4 V FB = 2 V CT = 100 pF 95 Ta = + 25 °C VCC = 4 V CTL = 4 V FB = 2 V DTC = Open RT = 3 kΩ RT = 39 kΩ RT = 13 kΩ RT = 6.8 kΩ fosc = 1 MHz 90 fosc = 2 MHz 85 80 75 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 0.65 0.7 0.75 0.8 0.85 0.9 DTC Terminal Voltage VDTC (V) Maximum Duty Cycle vs. Power Supply Voltage 100 100 Oscillation Frequency fOSC (kHz) Maximum Duty Cycle vs. Operating Ambient Temperature Maximum Duty Cycle Dtr (%) fosc = 200 kHz Maximum Duty Cycle Dtr (%) fosc = 200 kHz 95 fosc = 1 MHz 95 90 Ta = + 25 °C VCC = CTL DTC pin open FB = 2 V CT = 100 pF 90 fosc = 1 MHz 85 fosc = 2 MHz 85 fosc = 2 MHz 80 80 Ta = + 25 °C VCC = CTL = 4 V DTC pin open FB = 2 V CT = 100 pF −20 0 +20 +40 +60 +80 +100 75 75 70 0 2 4 6 8 10 12 70 −40 Power Supply Voltage VCC (V) Start Power Supply Voltage vs. Timing Resistor 2 Operating Ambient Temperature Ta ( °C) Start Power Supply Voltage VCC (V) At evaluating Fujitsu EV board system 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1 10 100 VCTL = VCC CT = 100 pF Ta = + 25 °C Ta = −30 °C Timing Resistor RT (kΩ) (Continued) 15 MB39A123 (Continued) Error Amp Voltage Gain, Phase vs. Frequency Error Amp Voltage Gain AV (dB) 50 40 30 20 10 0 −10 −20 −30 −40 −50 1k 10 k 100 k 1M φ Av Ta = +25 °C VCC = 7 V 225 180 135 90 45 0 −45 −90 2.0 V 240 kΩ Phase φ (deg) 10 kΩ 1 µF + IN 10 kΩ 2.4 kΩ 37 38 − + + 36 OUT −135 −180 −225 10 M 1.5 V 1.0 V Error Amp1 the same as other channels Frequency f (Hz) Maximum Power Dissipation vs. Operating Ambient Temperature (for BCC-48++) Maximum Power Dissipation PD (mW) Maximum Power Dissipation PD (mW) 2250 2000 1800 1600 1400 1200 1000 800 600 400 200 0 −40 −20 0 +20 +40 +60 +80 +100 2250 2000 1800 1600 1400 1200 1000 800 600 400 200 0 −40 −20 0 +20 +40 +60 +80 +100 Maximum Power Dissipation vs. Operating Ambient Temperature (for LQFP-48P) Operating Ambient Temperature Ta ( °C) Operating Ambient Temperature Ta ( °C) 16 MB39A123 ■ FUNCTIONAL DESCRIPTION 1. DC/DC Converter Function (1) Reference voltage block (VREF) The reference voltage circuit uses the voltage supplied from VCC terminal (pin 48) to generate a temperature compensated reference voltage (2.0 V Typ) used as the reference voltage for the internal circuits of the IC. It is also possible to supply the load current of up to 1 mA to external circuits as a reference voltage through the VREF terminal (pin 9) . (2) Triangular wave oscillator block (OSC) The triangular wave oscillator block generates the triangular wave oscillation waveform width of 0.4 V lower limit and 0.5 V amplitude by the timing resistor (RT ) connected to the RT terminal (pin 11) , and the timing capacitor (CT) connected to the CT terminal (pin 12) . The triangular wave is input to the PWM comparator circuits on the IC. (3) Error amplifier block (Error Amp1 to Error Amp6) The error amplifier detects output voltage of the DC/DC converter and outputs PWM control signals. An arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input terminal of the error amplifier, enabling stable phase compensation for the system. You can prevent surge currents when the IC is turned on by connecting soft-start capacitors to the CS1 terminal (pin 39) to CS6 terminal (pin 27) which are the noninverting input terminals of the error amplifier. The IC is started up at constant soft-start time intervals independent of the output load of the DC/DC converter. (4) PWM comparator block (PWM Comp.1 to PWM Comp.6) The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the input/output voltage. An output transistor is turned on, during intervals when the error amplifier output voltage and DTC voltage (ch.2 to ch.6) are higher than the triangular wave voltage. (5) Output block (Drive1 to Drive6) The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectification side of ch.1, ch.5 and ch.6). 17 MB39A123 2. Channel Control Function Use the CTL terminal (pin 1), CTL1 terminal (pin 2), CTL2 terminal (pin 3), CTL3 terminal (pin 4), CTL4 terminal (pin 5), CTL5 terminal (pin 6), and CTL6 terminal (pin 7) to set ON/OFF to the main and each channels. ON/OFF setting conditions for each channel CTL L H H H H H H H H CTL1 X L H L L L L L H CTL2 X L L H L L L L H CTL3 X L L L H L L L H CTL4 X L L L L H L L H CTL5 X L L L L L H L H CTL6 Power X L L L L L L H H OFF ON ON ON ON ON ON ON ON ch.1 OFF OFF ON OFF OFF OFF OFF OFF ON ch.2 OFF OFF OFF ON OFF OFF OFF OFF ON ch.3 OFF OFF OFF OFF ON OFF OFF OFF ON ch.4 OFF OFF OFF OFF OFF ON OFF OFF ON ch.5 OFF OFF OFF OFF OFF OFF ON OFF ON ch.6 OFF OFF OFF OFF OFF OFF OFF ON ON Note : Note that current which is over standby current flows into VCC terminal when the CTL terminal is in “L” level and one of the terminals between CTL1 to CTL6 terminals is set to “H” level. (Refer to the following circuit) • CTL1 to CTL6 terminals equivalent circuit VCC CTL1 ∼ 48 200 kΩ 86 kΩ ESD protection element 223 kΩ CTL6 GND 10 18 MB39A123 3. Protection Function (1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.) The short-circuit detection comparator (SCP) detects the output voltage level of each channel. If the output voltage of any channel is lower than the short-circuit detection voltage, the timer circuit is actuated to start charging to the capacitor (Cscp) externally connected to the CSCP terminal (pin 13). When the capacitor (Cscp) voltage becomes about 0.7 V, the output transistor is turned off and the dead time is set to 100%. The short-circuit detection from external input is capable by using −INS terminal (pin 8) on short-circuit detection comparator (SCP Comp.) . When the protection circuit is actuated, the power supply is rebooted or the CTL terminal (pin 1) is set to "L" level, resetting the latch as the voltage at the VREF terminal (pin 9) becomes 1.27 V (Min) or less (Refer to “■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) . (2) Under voltage lockout protection circuit block (UVLO) The transient state or a momentary decrease in the power supply voltage, which occurs when the power supply is turned on, may cause the control IC to malfunction, resulting in the breakdown or degradation of the system. To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in internal reference voltage level with respect to the power supply voltage, turns off the output transistor, and sets the dead time to 100% while holding the CSCP terminal (pin 13) at the "L" level. The system returns to the normal state when the power supply voltage reaches the reference voltage of the under voltage lockout protection circuit. (3) Protection circuit operating function table The following table shows the output state that the protection circuit is operating. Operation circuit OUT1-1 OUT1-2 OUT2 OUT3 OUT4 Short-circuit protection circuit Under voltage lockout protection circuit H H L L H H H H H H OUT5 L L OUT6 L L 19 MB39A123 ■ SETTING THE OUTPUT VOLTAGE • ch.1 Vo R3 R1 38 −INE1 R2 − + + Error Amp 37 FB1 1.00 V CS1 1.00 V (R1 + R2) R2 VO (R1 + R3) ≥ 100 µA VO = 39 Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula. • ch.2 to ch.6 Vo R3 R1 − −INEX R2 + + Error Amp FBX 1.23 V CSX 1.23 V (R1 + R2) R2 VO (R1 + R3) ≥ 100 µA VO = X : Each channel number Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula. 20 MB39A123 • ch.4 (Negative voltage output) Vo R1 −INA 19 R2 OUTA 18 R3 − + INVAmp Vo = −1.23 V R2 R1 FB4 15 Error Amp R4 16 −INE4 − + + 1.23 V CS4 17 21 MB39A123 ■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency can be set by connecting a timing resistor (RT ) to the RT terminal (pin 11) and a timing capacitor (CT) to the CT terminal (pin 12). Triangular wave oscillation frequency : fOSC 680000 CT (pF) × RT (kΩ) fOSC (kHz) = : 22 MB39A123 ■ SETTING THE SOFT-START TIME To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors (CS1 to CS6) to the CS1 terminal (pin 39) to CS6 terminal (pin 27) respectively. As illustrated below, when each CTLX is set to “H” from “L”, the soft-start capacitors (CS1 to CS6) externally connected to the CS1 to CS6 terminals are charged at about 1.1 µA. The error amplifier output (FB1 to FB6) is determined by comparison between the lower voltage of the two noninverted input terminal voltage (1.23 V (ch.1 : 1.0 V) , CS terminal voltage) and the inverted input terminal voltage (−INE1 to −INE6) . The FB terminal voltage is decided for the soft-start period (CS terminal voltage < 1.23 V (ch.1 : 1.0 V) ) by the comparison between −INE terminal voltage and CS terminal voltage. The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor externally connected to the CS terminal is charged. The soft-start time is obtained from the following formula : Soft-start time : ts (time until output voltage 100%) ch.1 : ts (s) = 0.91 × CS1 (µF) : ch.2 to ch.6 : ts (s) = 1.12 × CSX (µF) : X : Each channel number Vo R1 −INEX VREF R2 1.1 µA L priority Error AmpX − + + CSX CSX FBX 1.23 V (ch.1 : 1.0 V) H : CSX can be charged when CTLX is set to "H" and normal operation is selected L : CSX is discharged when CTLX is set to "L" and protective operation is selected CTLX CHCTL X : Each channel number 23 MB39A123 ■ PROCESSING WHEN NOT USING CS TERMINAL When soft-start function is not used, leave the CS1 terminal (pin 39), the CS2 terminal (pin 40), the CS3 terminal (pin 47), the CS4 terminal (pin 17), the CS5 terminal (pin 20) and the CS6 terminal (pin 27) open. • When not setting soft-start time “Open” 39 CS1 CS6 27 “Open” “Open” 40 CS2 CS5 20 “Open” “Open” 47 CS3 CS4 17 “Open” 24 MB39A123 ■ SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT Each channel uses the short-circuit detection comparator (SCP) to always compare the error amplifier’s output level to the reference voltage. While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator output remains at “L” level, and the CSCP terminal (pin 13) is held at “L” level. If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage to drop, the output of the short-circuit detection comparator on that channel goes to “H” level. This causes the external short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 13) to be charged at 1 µA. Short-circuit detection time : tCSCP tCSCP (s) = 0.70 × CSCP (µF) : When the capacitor CSCP is charged to the threshold voltage (VTH = 0.70 V) , the latch is set to and the external : FET is turned off (dead time is set to 100%) . At this time, the latch input is closed and CSCP terminal (pin 13) is held at “L” level. The short-circuit detection from external input is capable by using −INS terminal (pin 8) . In this case, the shortcircuit detection operates when the −INS terminal voltage becomes the level of the threshold voltage (VTH = IV) : or less. Note that the latch is reset as the voltage at the VREF terminal (pin 9) is decreased to 1.27 V (Min) or less by either recycling the power supply or setting the CTL terminal (pin 1) to “L” level. 25 MB39A123 • Timer-latch short-circuit protection circuit Vo FBX R1 − −INEX R2 + Error AmpX 1.23 V (ch.1 : 1.0 V) SCP Comp. + + − 1.1 V 1 µA To each channel drive CSCP 13 VREF CSCP S R Latch UVLO CTL CTL X : Each channel number 26 MB39A123 ■ PROCESSING WHEN NOT USING CSCP TERMINAL To disable the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 13) to GND in the shortest distance. • Processing when not using the CSCP terminal 13 10 CSCP GND 27 MB39A123 ■ SETTING THE DEAD TIME (ch.2 to ch.6) When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta method, step up/ down Sepic method, or flyback method, the FB terminal voltage may reach and exceed the triangular wave voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON duty = 100%). To prevent this, set the maximum duty of the output transistor. When the DTC terminal is opened, the maximum duty is 92% (Typ) because of this IC built-in resistor which sets the DTC terminal voltage. This is based on the following setting: 1MHz (RT = 6.8kΩ/CT = 100pF). To disable the DTC terminal, connect it to the VREF terminal (pin 9) as illustrated below (when dead time is not set). • When dead time is set: (Setting with built-in resistor: 1MHz [RT = 6.8kΩ/CT = 100pF] = 92%) : • When dead time is not set: 9 VREF “Open” DTCX DTCX X : ch.2 to ch.6 X : ch.2 to ch.6 To change the maximum duty using external resistors, set the DTC terminal voltage by dividing resistance using the VREF voltage. Refer to “• When dead time is set : (Setting by external resistors)”. It is possible to set without regard for the built-in resistance value (including tolerance) when setting the external resistance value to 1/10 of the built-in resistance or less. Note that the VREF load current must be set such that the total current for all the channels does not exceed 1 mA. When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on. The formula for calculating the maximum duty is as follows, assuming that the triangular wave amplitude and triangular wave lower limit voltage are about 0.5 V and 0.4 V, respectively. Vdt − 0.4 V 0.5 V × 100 (%) DUTY (ON) Max = : Vdt = Rb Ra + Rb × VREF (V) (condition : Ra < R1 10 , Rb < R2 10 ) Note : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to “ON Duty cycle vs. DTC terminal voltage”. The maximum duty varies depending on the oscillation frequency, regardless of settings in built-in or external resistors. (This is due to the dependency of the peak value of a triangular wave on the oscillation frequency and RT. Therefore, if RT is greater, the maximum duty decreases, even when the same frequency is used.) 28 MB39A123 Furthermore, the maximum duty increases when the power supply voltage and the temperature are high. It is therefore recommended to set the duty, based on the “■ TYPICAL CHARACTERISTICS” data, so that it does not exceed 95% under the worst conditions. ON duty cycle vs. DTC terminal voltage 100 95 90 Ta = + 25 °C VCC = CTL = 4 V FB = 2 V CT = 100 pF fosc = 200 kHz ON duty cycle Dtr (%) 85 80 75 70 65 60 55 50 0.6 0.65 0.7 fosc = 1 MHz Calculated value fosc = 1 MHz fosc = 2 MHz 0.75 0.8 0.85 0.9 DTC terminal voltage VDTC (V) • When dead time is set (Setting by external resistors) VREF 9 Ra DTCX R1 : 131.9 kΩ To PWM Comp.X Vdt Rb 10 GND R2 : 97.5 kΩ X: ch.2 to ch.6 29 MB39A123 Setting example (for an aim maximum ON duty of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 kΩ) • Calculation using external resistors Ra and Rb only Vdt = Rb Ra + Rb × VREF = 0.80 V : Vdt − 0.4 V 0.5 V × 100 (%) = 80% ⋅ ⋅ ⋅ ⋅ (1) : DUTY (ON) Max= : • Calculation taking account of the built-in resistor (tolerance ± 20%) also Vdt = (Rb, R2 Combined resistance) (Ra, R1 Combined resistance) + (Rb, R2 Combined resistance) Vdt − 0.4 V 0.5 V × 100 (%) = 80% ± 0.2% ⋅ ⋅ ⋅ ⋅ (2) : × VREF = 0.80 V ± 0.13% : DUTY (ON) Max = : Based on (1) and (2) above, selecting external resistances to 1/10th or less of the built-in resistance enables the built-in resistance to be ignored. As for the duty dispersion, please expect ± 5% at (fosc = 1 MHz) due to the dispersion of a triangular wave amplitude. ■ PROCESSING WHEN NOT USING ch.4 INV AMP Short-circuit the - INA terminal (pin 19) and OUTA terminal (pin 18) in the shortest distance when not using ch.4 INV Amp. • When not using ch.4 INV Amp 19 18 −INA OUTA 30 MB39A123 ■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold voltage (VTH) of UVLO (under voltage lockout protection circuit) , UVLO is released, and the operation of output drive circuit of each channel becomes possible. When CTL is off, the CS and CSCP terminals are always set to "L" as soon as output drive circuit of each channel is fixed to full off even if UVLO is released. When VR and VREF fall and VREF decreases the threshold voltage (VRST) of UVLO (under voltage lockout protection circuit), output drive circuit becomes the UVLO state. • CTL block equivalent circuit SCP H : at SCP UVLO1 H : UVLO release To SCP circuit H : Possible to operate SCP L : CSCP terminal low ch.1 to ch.4 To output drive circuit H : Possible to operate L : Forced stop CS1 to CS4 To charge/discharge circuit H : Possible to charge L : Forced discharge ch.5, ch.6 To output drive circuit H : Possible to operate L : Forced stop CS5, CS6 To charge/discharge circuit H : Possible to charge L : Forced discharge Error Amp reference 1.0 V/1.23 V 48 VCC bias Power ON/OFF CTL UVLO2 H : UVLO release VREF VR 1 CTL 9 VREF 31 MB39A123 • Operation waveform when CTL turning on and off H ∗2 CTL L 1.23 V VR 0V 2V VREF 0V H UVLO1 UVLO state L H UVLO2 ch.1 to ch.4 Output Drive circuit control ch.5, ch.6 Output Drive circuit control UVLO state L H Fixed full off L H Fixed full off L Possible operate Possible operate UVLO release UVLO release VTH1 VTH2 ∗1 VRST1 VRST2 UVLO state UVLO state Fixed full off Fixed full off *1 : As shown in the sequence on the above figure, when turning off CTL while each CHCTL is turned on, intermission state may be generated due to noise around the CTL threshold voltage. To prevent this, it is recommended to turn off CTL with a slope of - 1 V/50 µs or higher so that the CTL voltage does not remain in the specified threshold voltage range (0.5 V to 1.5 V) . If the above slope setting is difficult to achieve, it is recommended to turn off CTL after turning off all CHCTLs. Moreover, a voltage remains in the FB terminal, when VCC is turned off at the same time as CTL and CHCTL, or when VCC is turned off at the same time as CTL while each CHCTL is still turned on. As this may lead to an overshoot upon restart, it is recommended to turn off VIN and CTL after turning off all the CHCTLs to reduce FB to 0V. Likewise, it is recommended to turn off CHCTL with a slope of - 1 V/50 µs or higher. *2 : When CTL and CHCTL are turned on at the same time, or when CTL is turned on while each CHCTL is turned on, there exists a period (approx. 200 ns) when the error Amp output voltage (FB) is higher than the triangular wave voltage (CT) upon the startup of VREF. As a result, when UVLO is released and then the Output Drive circuit of each channel becomes operable, the output transistor is turned on, generating a voltage at the DC/ DC converter output. The voltage to be generated (Vop) depends on L, Co and VIN. (See • Vo characteristics (Vop) when turning on CTL at CHCTL ON.) It should be noted that the above event does not occur when CTL is turned on while CHCTL is turned off. Therefore, it is recommended to turn on each CHCTL after turning on CTL. 32 MB39A123 • Vo characteristics (Vop) when turning on CTL at CHCTL ON At evaluating Fujitsu EV board system CTL[V] 10 5 0 Vo[V] 5 4 3 2 1 0 Generated voltage Vop = 0.4 V : CTL 2 CS[V] 2 CS 1 0 3 Step-down operation VIN = 7.2 V Vo = 5 V L = 15 µ H Co = 2.2 µF Load = 50 Ω CHCTL = ON Vo VD L IL Vo 1 0 2 4 6 8 10 12 14 16 18 20 t[ms] D Co Generated output voltage - Output capacitor value 600 TON At evaluating Fujitsu EV board system Generated output voltage (mV) VD VIN 500 Ta = + 25 °C VCC = CTL = 7.2 V 400 300 200 100 L = 68 µH 0 1 10 100 Vop = Q / Co Vo Vop When no load is applied IL Ip Ip = VIN / L × TON L = 6.8 µH This energy Q moves to Co Output capacitor value Co (µF) 33 MB39A123 ■ ABOUT THE LOW VOLTAGE OPERATION 1.7 V or more is necessary for the VCC terminal (pin 48) and the VCCO terminal (pin 36) for the self-power supply type to use the step-up circuit as the start voltage. Even if thereafter VIN voltage decreases to 1.5 V, operation is possible if the VCC terminal (pin 48) voltage and the VCCO terminal (pin 36) voltage rise to 2.5 V or more after start-up. However, it is necessary not to exceed the maximum duty set value by the duty due to the VIN decrease. Including other channels, execute an enough operation margin confirmation when using it. A VREF VIN Step-up A R1 21 −INE5 CS5 20 R2 − + + 1.23 V Error Amp5 PWM Comp.5 Drive5 + + N-ch − 0.9 V 0.4 V VCCO 36 30 OUT5 Vo5 (5 V) Max Duty 92% ± 5% DTC5 23 VCC 48 34 MB39A123 ■ I/O EQUIVALENT CIRCUIT • Reference voltage block VCC 48 1.23 V + − • Control block (CTL, CTL1 to CTL6) VCC ESD protection element 9 79 kΩ VREF CTLX 86 kΩ ESD protection element 124 kΩ GND 10 ESD protection element 223 kΩ GND • Soft-start block VREF (2.0 V) VCC • Short-circuit detection block • Short-circuit detection comparator block VCC VREF (2.0 V) CSX 2 kΩ VCC −INS 8 13 CSCP 100 kΩ VREF (2.0 V) (1 V) GND GND GND • Triangular wave oscillator block (RT) VREF (2.0 V) 0.64 V + − 11 RT VCC • Triangular wave oscillator block (CT) VCC VREF (2.0 V) CT 12 GND GND • Error amplifier block (ch.1 to ch.6) VCC VREF (2.0 V) −INEX 1.0 V (ch.1) 1.23 V (ch.2 to ch.6) CSX FBX GND X : Each channel number (Continued) 35 MB39A123 (Continued) • Inverting amplifier block VCC VREF (2.0 V) OUTA −INA 19 18 GND • PWM comparator block VCC • Output block VCCO 36 VREF (2.0 V) FB2 to FB6 DTCX 131.9 kΩ CT OUTX 97.5 kΩ GNDO 28 GND X : Each channel number 36 7.20 7.10 6.75 6.80 0.50 49−∅0.52 49- 0.55 0.70 0.70 0.80 0.90 0.70 0.80 ■ LAND MASK PATTERN (BCC-48++) 6.80 7.20 6.75 C 0. 20 4- 0.55 0.30 Mounting Terminal Dimension C 0. 20 0.23 0.24 Mask Dimension (t = 0.15 mm) 4- 0.55 MB39A123 Unit : mm 7.10 37 MB39A123 ■ USAGE PRECAUTIONS • Printed circuit board ground lines should be set up with consideration for common impedance. • Take appropriate static electricity measures. • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. • Do not apply a negative voltages. • The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation. ■ ORDERING INFORMATION Part number MB39A123PMT-❏❏❏E1 MB39A123PVK-❏❏❏E1 Package 48-pin plastic LQFP (FPT-48P- M26) 48-pin plastic BCC (LCC-48P-M08) Remarks Lead Free version Lead Free version ■ EV BOARD ORDERING INFORMATION EV board part No. MB39A123EVB-02 EV board version No. Board Rev.1.0 Remarks LQFP-48P ■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added “E1” at the end of the part number. 38 MB39A123 ■ MARKING FORMAT (LEAD FREE VERSION) M B3 9A123 XXXX XXX E1 INDEX LQFP-48P (FPT-48P-M26) Lead Free version INDEX J APAN MB 3 9A 123 XXXX XXX E1 Lead Free version BCC-48++ (LCC-48P-M08) 39 MB39A123 ■ LABELING SAMPLE (LEAD FREE VERSION) Lead-free mark JEITA logo JEDEC logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 G Pb (3N)2 1561190005 107210 QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN 1/1 MB123456P - 789 - GE1 0605 - Z01A 1000 1561190005 Lead Free version 40 MB39A123 ■ MB39A123PMT-❏❏❏E1, MB39A123PVK-❏❏❏E1 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL Item Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions Condition IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 8 days Please processes within 8 days after baking (125 °C, 24H) 5 °C to 30 °C, 70%RH or less (the lowest possible humidity) [Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) H rank : 260 °C Max 260 °C 255 °C 170 °C to 190 °C RT (b) (c) (d) (e) (a) (d') (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling : Average 1 °C/s to 4 °C/s : Temperature 170 °C to 190 °C, 60 s to 180 s : Average 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C or more, 10 s or less : Temperature 230 °C or more, 40 s or less or Temperature 225 °C or more, 60 s or less or Temperature 220 °C or more, 80 s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 °C Max Times : 5 s max/pin 41 MB39A123 ■ PACKAGE DIMENSIONS 48-pin plastic BCC Lead pitch Package width × package length Sealing method Mounting height Weight 0.50 mm 7.00 mm × 7.00 mm Plastic mold 0.80 mm Max 0.07 g (LCC-48P-M08) 48-pin plastic BCC (LCC-48P-M08) 7.00±0.10(.276±.004) 37 25 25 0.80(.031)MAX Mount height 0.50(.020) TYP 6.20(.244)TYP 6.10(.240)TYP 0.50±0.10 (.020±.004) 37 0.50(.020) TYP 6.20(.244) TYP 6.10(.240) TYP 0.50±0.10 (.020±.004) 5.00±0.06 (.197±.002) 4.60(.181) 4.60(.181) 5.00±0.06 (.197±.002) 6.25(.246) REF 5.00(.197) REF 0.09(.004) MIN 0.14(.006) MIN 7.00±0.10 (.276±.004) INDEX AREA 1 13 13 "B" 0.075±0.025 (.003±.001) (Stand off) "A" 5.00(.197)REF 6.25(.246)REF "C" 1 Details of "A" part 0.14(.006) MIN 0.05(.002) Details of "B" part 0.70±0.06 (.028±.002) 0.55±0.06 (.022±.002) Details of "C" part C0.20(.008) 0.55±0.06 (.022±.002) 0.60±0.06 (.024±.002) 0.30±0.06 (.012±.002) 0.55±0.06 (.022±.002) 0.55±0.06 (.022±.002) C 2004 FUJITSU LIMITED C48061S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued) 42 MB39A123 (Continued) 48-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 7 × 7 mm Gullwing Plastic mold 1.70 mm MAX 0.17 g P-LFQFP48-7×7-0.50 (FPT-48P-M26) Code (Reference) 48-pin plastic LQFP (FPT-48P-M26) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00±0.20(.354±.008)SQ * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. 43 MB39A123 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0608