MB39C007WQN-G-JN-ERE1

FUJITSU SEMICONDUCTOR DATA SHEET DS04-27246-3E ASSP for Power Management Applications 2 ch DC/DC Converter IC Built-in Switching FET & voltage detection function, PFM/PWM Synchronous Rectification, and Down Conversion Support MB39C007 ■ DESCRIPTION The MB39C007 is a current mode type 2-channel DC/DC converter IC built-in voltage detection, synchronous rectifier, and down conversion support. The device is integrated with a switching FET, oscillator, error amplifier, PFM/PWM control circuit, reference voltage source, and voltage detection circuit. External inductor and decoupling capacitor are needed only for the external component. MB39C007 is small, achieve a highly effective DC/DC converter in the full load range, this is suitable as the built-in power supply for handheld equipment such as mobile phone/PDA, DVDs, and HDDs. ■ FEATURES • • • • • • • • • • • • • • High efficiency : 96% (Max) Low current consumption : 30 μA (At PFM/ch) Output current : 800 mA/ch (Max) Input voltage range : 2.5 V to 5.5 V Operating frequency : 2.0 MHz (Typ) Built-in PWM operation fixed function No flyback diode needed Low dropout operation : For 100% on duty Built-in high-precision reference voltage generator : 1.30 V ± 2% Consumption current in shutdown mode : 1 μA or less Built-in switching FET : P-ch MOS 0.3 Ω (Typ) , N-ch MOS 0.2 Ω (Typ) High speed for input and load transient response in the current mode Over temperature protection Packaged in a compact package : QFN-24 ■ APPLICATIONS • • • • • • • • • Flash ROMs MP3 players Electronic dictionary devices Surveillance cameras Portable GPS navigators DVD drives IP phones Network hubs Mobile phones etc. Copyright©2008-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.1 MB39C007 ■ PIN ASSIGNMENT (Top View) LX2 DGND2 DGND2 DGND1 DGND1 LX1 18 17 16 15 14 13 DVDD2 19 12 DVDD1 DVDD2 20 11 DVDD1 OUT2 21 10 OUT1 MODE2 22 9 MODE1 VREFIN2 23 8 VREFIN1 XPOR 24 7 VDET 1 2 CTLP CTL2 3 CTL1 4 AGND 5 6 AVDD VREF (LCC-24P-M10) 2 DS04-27246-3E MB39C007 ■ PIN DESCRIPTIONS Pin No. Pin Name I/O Description 1 CTLP I Voltage detection circuit block control input pin. (L : Voltage detection function stop , H : Normal operation) 2, 3 CTL2, CTL1 I DC/DC converter block control input pins. (L : Shut down , H : Normal operation) 4 AGND ⎯ Control block ground pin. 5 AVDD ⎯ Control block power supply pin. 6 VREF O Reference voltage output pin. 7 VDET I Voltage detection input pin. 8, 23 VREFIN1, VREFIN2 I Error amplifier (Error Amp) non-inverted input pins. 9, 22 MODE1, MODE2 I Operation mode switch pins. (L : PFM/PWM mode , OPEN : PWM mode) 10, 21 OUT1, OUT2 I Output voltage feedback pins. 11, 12 DVDD1 19, 20 DVDD2 ⎯ Drive block power supply pins. 13, 18 LX1, LX2 O Inductor connection output pins. High impedance during shut down. 14, 15 DGND1 16, 17 DGND2 ⎯ Drive block ground pins. 24 XPOR O VDET circuit output pin. Connected to an N-ch MOS open drain circuit. DS04-27246-3E 3 MB39C007 ■ I/O PIN EQUIVALENT CIRCUIT DIAGRAM VDD VDD ∗ LX1, LX2 VREF ∗ GND GND VDD ∗ ∗ VREFIN1, VREFIN2, VDET OUT1, OUT2 ∗ ∗ GND VDD CTL1, CTL2, CTLP ∗ GND VDD XPOR ∗ MODE1, MODE2 ∗ GND ∗ GND 4 * : ESD Protection device DS04-27246-3E MB39C007 ■ BLOCK DIAGRAM VIN AVDD 5 CTL1 DVDD1 11, 12 DVDD2 19, 20 3 ON/OFF OUT1 10 ×3 − DVDD1 Error Amp + IOUT Comp. VREFIN1 8 DAC PFM/PWM L:PFM/PWM OPEN:PWM LX1 13 Logic VOUT1 Control MODE1 Mode Control 9 VIN VIN CTLP VDET VREF CTL2 OUT2 1 7 − ON/OFF 24 XPOR 1.30 V 6 + VREF 2 ON/OFF ×3 21 − Error Amp DVDD2 + IOUT Comp. VREFIN2 23 PFM/PWM L:PFM/PWM OPEN:PWM MODE2 22 LX2 18 Logic Control Mode Control 4 AGND DS04-27246-3E VOUT2 14, 15 DGND1 16, 17 DGND2 5 MB39C007 • Current mode • Original voltage mode type : Stabilize the output voltage by comparing two items below and on-duty control. - Voltage (VC) obtained through negative feedback of the output voltage by Error Amp - Reference triangular wave (VTRI) • Current mode type : Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the oscillator (rectangular wave generation circuit) and SW FET is used. Stabilize the output voltage by comparing two items below and on-duty control. - Voltage (VC) obtained through negative feedback of the output voltage by Error Amp - Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in the oscillator (rectangular wave generation circuit) and SW FET Voltage mode type model Current mode type model VIN VIN Oscillator Vc − VTRI + Vc S + R VIDET Vc − Q SR-FF VIDET VTRI Vc ton toff toff ton Note : The above models illustrate the general operation and an actual operation will be preferred in the IC. 6 DS04-27246-3E MB39C007 ■ FUNCTION OF EACH BLOCK • PFM/PWM Logic control circuit In normal operation, frequency (2.0 MHz) which is set by the built-in oscillator (square wave oscillation circuit) controls the built-in P-ch MOS FET and N-ch MOS FET for the synchronous rectification operation. In the light load mode, the intermittent (PFM) operation is executed. This circuit protects against pass-through current caused by synchronous rectification and against reverse current caused in a non-successive operation mode. • IOUT Comparator circuit This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing VIDET obtained through I-V conversion of peak current IPK of ILX with the Error Amp output, the built-in P-ch MOS FET is turned off via the PFM/PWM Logic Control circuit. • Error Amp phase compensation circuit This circuit compares the output voltage to reference voltages such as VREF. This IC has a built-in phase compensation circuit that is designed to optimize the operation of this IC. This needs neither to be considered nor addition of a phase compensation circuit and an external phase compensation device. • VREF circuit A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.30 V (Typ). • Voltage Detection (VDET) circuit The voltage detection circuit monitors the VDET pin voltage. Normally, use the XPOR pin through pull-up with an external resistor. When the VDET pin voltage reaches 0.6 V, it reaches the H level. Timing chart example : (XPOR pin pulled up to VIN) VIN VUVLO CTLP VDET VTHHPR VTHLPR XPOR VUVLO : UVLO threshold voltage VTHHPR, VTHLPR : XPOR threshold voltage • Protection circuit This IC has a built-in over-temperature protection circuit. The over-temperature protection circuit turns off both N-ch and P-ch switching FETs when the junction temperature reaches + 135 °C. When the junction temperature comes down to + 110 °C, the switching FET is returned to the normal operation. Since the PFM/PWM control circuit of this IC is in the control method in current mode, the current peak value is also monitored and controlled as required. DS04-27246-3E 7 MB39C007 • Function table Input CTL1 CTL2 Output CTLP L H L L H MODE CH1 function CH2 function * L H VDET function VREF function Switching operation Stopped Operation Stopped Stopped Operation Stopped Operation L L H L L H H Stopped Operation Stopped Stopped Operation H H L L H PFM/PWM mode Operation Operation L H Operation Stopped Stopped Operation 1.3 V output Stopped Operation L Open H L L H H H Stopped Operation Stopped Stopped Operation PWM fixed mode Operation Operation * : Don't care 8 DS04-27246-3E MB39C007 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Signal input voltage XPOR pull-up voltage Symbol Condition VDD VISIG VIXPOR Max AVDD = DVDD1 = DVDD2 −0.3 +6.0 OUT1, OUT2 pins −0.3 VDD + 0.3 CTLP, CTL1, CTL2, MODE1, MODE2 pins −0.3 VDD + 0.3 VREFIN1, VREFIN2 pins −0.3 VDD + 0.3 VDET pin −0.3 VDD + 0.3 XPOR pin −0.3 +6.0 V −0.3 VDD + 0.3 V ⎯ 1.8 A ⎯ 3125*1, *2, *3 ⎯ 1563*1, *2, *4 ⎯ 1250*1, *2, *3 ⎯ 625*1, *2, *4 VLX LX1, LX2 pins LX Peak current IPK The upper limit value of ILX1 and ILX2 Ta ≤ +25 °C PD Ta = +85 °C Operating ambient temperature Storage temperature Unit Min LX voltage Power dissipation Rating V V mW mW Ta ⎯ −40 +85 °C TSTG ⎯ −55 +125 °C *1 : See the diagram of “■ EXAMPLE OF STANDARD OPERATION CHARACTERISTICS. Power dissipation vs. Operating ambient temperature” for the package power dissipation of Ta from + 25 °C to + 85 °C. *2 : When mounted on a four-layer epoxy board of 11.7 cm × 8.4 cm *3 : IC is mounted on a four-layer epoxy board, which has thermal via, and the IC's thermal pad is connected to the epoxy board (Thermal via is 9 holes). *4 : IC is mounted on a four-layer epoxy board, which has no thermal via, and the IC's thermal pad is connected to the epoxy board. Notes: • The use of negative voltages below − 0.3 V to the AGND, DGND1, and DGND2 pin may create parasitic transistors on LSI lines, which can cause abnormal operation. • This device can be damaged if the LX1 pin and LX2 pin are short-circuited to AVDD and DVDD1/DVDD2, or AGND and DGND1/DGND2. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS04-27246-3E 9 MB39C007 ■ RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage VREFIN voltage CTL voltage Symbol VDD ILX VREF output current IROUT Value Unit Min Typ Max 2.5 3.7 5.5 V 0.15 ⎯ 1.30 V CTLP, CTL1, CTL2 pins 0 ⎯ 5.0 V ILX1, ILX2 ⎯ ⎯ 800 mA 2.5 V ≤ AVDD = DVDD1 = DVDD2 < 3.0 V ⎯ ⎯ 0.5 3.0 V ≤ AVDD = DVDD1 = DVDD2 ≤ 5.5 V ⎯ ⎯ 1 AVDD = DVDD1 = DVDD2 ⎯ VREFIN VCTL LX current Condition mA XPOR current IPOR ⎯ ⎯ ⎯ 1 mA Inductor value L ⎯ ⎯ 2.2 ⎯ μH Note : The output current from this device has a situation to decrease if the power supply voltage (VIN) and the DC/DC converter output voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this device. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 10 DS04-27246-3E MB39C007 ■ ELECTRICAL CHARACTERISTICS (Ta = +25 °C, AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V) Parameter Input current IREFIN Output voltage VOUT Input stability LINE Load stability LOAD OUT pin input impedance ROUT LX Peak current DC/DC converter block SymPin No. bol IMSW Oscillation frequency fosc 13, 18 Typ Max VREFIN = 0.15 V to 1.3 V − 100 0 + 100 nA VREFIN = 0.833 V, OUT = −100 mA 2.45 2.50 2.55 V ⎯ ⎯ 10 mV ⎯ ⎯ 10 mV OUT = 2.0 V 0.6 1.0 1.5 MΩ Output shorted to GND 0.9 1.2 1.7 A ⎯ ⎯ 30 ⎯ mA ⎯ 1.6 2.0 2.4 MHz ⎯ 45 80 μs ⎯ − 10* ⎯ mV LX1/LX2 = −100 mA ⎯ 0.30 0.48 Ω ⎯ 0.20 0.42 Ω − 1.0 ⎯ + 8.0 μA − 2.0 ⎯ + 16.0 μA + 120* + 135* + 160* °C + 95* °C 2, 3, C1/C2 = 4.7 μF, OUT = 0 A, 10, 21 OUT1/OUT2 : 0 → 90% VOUT Rise delay time tPG SW NMOS-FET OFF voltage VNOFF SW PMOS-FET ON resistance RONP SW NMOS-FET ON resistance RONN LX1/LX2 = −100 mA ILEAKM 0 ≤ LX ≤ VDD*2 ILEAKH VDD = 5.5 V, 0 ≤ LX ≤ V * Overheating protection (Junction Temp.) ⎯ 13, 18 TOTPH TOTPL Protection UVLO threshold circuit voltage block VTHHUV UVLO hysteresis width VHYSUV VTHLUV XPOR threshold VTHHPR voltage VTHLPR XPOR hysteresis width Unit Min 2.5 V ≤ AVDD = DVDD1 = DVDD2 ≤ 5.5 V*1 10, 21 −100 mA ≥ OUT ≥ −800 mA IPK PFM/PWM switch current LX leak current Voltage detection circuit block 8, 23 Value Condition DD 2 ⎯ ⎯ 5, 11, 12, 19, 20 ⎯ XPOR output voltage VOL XPOR output current IOH 2.17 2.30 2.43 V 2.03 2.15 2.27 V 0.08 0.15 0.25 V 575 600 625 mV 558 583 608 mV ⎯ ⎯ 17 ⎯ mV XPOR = 25 μA ⎯ ⎯ 0.1 V XPOR = 5.5 V ⎯ ⎯ 1.0 μA ⎯ ⎯ 7 VHYSPR + 110* + 125* 24 * : This value is not be specified. This should be used as a reference to support designing the circuits. (Continued) DS04-27246-3E 11 MB39C007 (Continued) (Ta = +25 °C, AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V) Parameter Control block CTL threshold voltage CTL pin input current Reference VREF voltage voltage VREF Load block stability Shut down power supply current Power supply current at DC/DC operation 1 (PFM mode) General Power supply current at DC/DC operation 2 (PWM mode) Power supply current (voltage detection mode) Power-on invalid current Symbol Pin No. Condition VTHHCT VTHLCT 1, 2, 3 Unit Min Typ Max ⎯ 0.55 0.95 1.45 V ⎯ 0.40 0.80 1.30 V ⎯ ⎯ 1.0 μA IICTL 0 V ≤ CTLP/CTL1/CTL2 ≤ 3.7 V VREF VREF = 0 A 6 Value 1.274 1.300 1.326 V VREF = −1.0 mA ⎯ ⎯ 20 mV IVDD1 CTLP/CTL1/CTL2 = 0 V, State of all circuits OFF*3 ⎯ ⎯ 1.0 μA IVDD1H CTLP/CTL1/CTL2 = 0 V, VDD = 5.5 V, State of all circuits OFF*3 ⎯ ⎯ 1.0 μA IVDD21 1. CTLP = 0 V,CTL1 = 3.7 V, CTL2 = 0 V 2. CTLP = 0 V, CTL1 = 0 V, CTL2 = 3.7 V, OUT = 0 A ⎯ 30 48 μA IVDD22 CTLP = 0 V, CTL1/CTL2 = 3.7 V, OUT = 0 A ⎯ 50 80 μA ⎯ 3.5 10.0 mA IVDD32 CTLP = 0 V, CTL1/CTL2 = 3.7 V, MODE1/MODE2 = OPEN, OUT = 0 A ⎯ 7.0 20.0 mA IVDD5 CTLP = 3.7 V, CTL1/CTL2 = 0 V ⎯ 15 24 μA IVDD 1. CTL1 = 3.7 V, CTL2 = 0 V 2. CTL1 = 0 V, CTL2 = 3.7 V, VOUT1/VOUT2 = 90%, OUT = 0 A*4 ⎯ LOADREF IVDD31 1. CTLP = 0 V, CTL1 = 3.7 V, CTL2 = 0 V, MODE1/ MODE2 = OPEN 5, 11, 2. CTLP = 0 V, CTL1 = 0 V, 12, 19, CTL2 = 3.7 V, MODE1/ 20 MODE2 = OPEN, OUT = 0 A 1000 2000 μA *1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher. *2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit. *3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins. *4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included because the device is in full ON state (no switching operation). Also the load current is not included. 12 DS04-27246-3E MB39C007 ■ TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS MB39C007 VDD VDD SW CTL1/CTL2 DVDD1/DVDD2 R1 1 MΩ C2 4.7 µF SW AVDD MODE1/MODE2 R3-1 20 kΩ R3-2 150 kΩ R4 300 kΩ VIN R5 510 kΩ R6 100 kΩ C6 0.1 µF VREF LX1/LX2 VDET OUT1/OUT2 C3 0.1 µF L1 2.2 µH VOUT1/ VOUT2 IOUT C1 4.7µF DGND1/DGND2 VREFIN1/VREFIN2 AGND GND VOUT = 2.97 × VREFIN Component Specification Vendor Part Number R1 1 MΩ KOA RK73G1JTTD D 1 MΩ R3-1 R3-2 20 kΩ 150 kΩ SSM SSM RR0816-203-D RR0816-154-D R4 300 kΩ SSM RR0816-304-D R5 510 kΩ KOA RK73G1JTTD D 510 kΩ R6 100 kΩ SSM RR0816-104-D C1 4.7 μF TDK C2012JB1A475K C2 4.7 μF TDK C2012JB1A475K C3 0.1 μF TDK C1608JB1E104K C6 0.1 μF TDK C1608JB1H104K L1 2.2 μH TDK VLF4012AT-2R2M Remarks VOUT1/VOUT2 = 2.5 V Setting For adjusting slow start time Note : These components are recommended based on the operating tests authorized. TDK : TDK Corporation SSM : SUSUMU Co., Ltd KOA : KOA Corporation DS04-27246-3E 13 MB39C007 ■ APPLICATION NOTES [1] Selection of components • Selection of an external inductor Basically it dose not need to design inductor. This IC is designed to operate efficiently with a 2.2 μH external inductor. The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and should have a minimal DC resistance. (100 mΩ or less is recommended.) LX peak current value IPK is obtained by the following formula. IPK = IOUT + VIN − VOUT L × D fosc × 1 = IOUT + 2 L : External inductor value IOUT : Load current VIN : Power supply voltage VOUT : Output setting voltage D : ON-duty to be switched ( = VOUT/VIN) fosc : Switching frequency (2.0 MHz) (VIN − VOUT) × VOUT 2 × L × fosc × VIN ex) When VIN = 3.7 V, VOUT = 2.5 V, IOUT = 0.8 A, L = 2.2 μH, fosc = 2.0 MHz The maximum peak current value IPK is obtained by the following formula. IPK = IOUT + (VIN − VOUT) × VOUT 2 × L × fosc × VIN = 0.8 A + (3.7 V − 2.5 V) × 2.5 V 2 × 2.2 μH × 2.0 MHz × 3.7 V =: 0.89 A • I/O capacitor selection • Select a low equivalent series resistance (ESR) for the VDD input capacitor to suppress dissipation from ripple currents. • Also select a low equivalent series resistance (ESR) for the output capacitor. The variation in the inductor current causes ripple currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied by the ESR value. The output capacitor value has a significant impact on the operating stability of the device when used as a DC/DC converter. Therefore, FUJITSU SEMICONDUCTOR generally recommends a 4.7 μF capacitor, or a larger capacitor value can be used if ripple voltages are not suitable. If the VIN/VOUT voltage difference is within 0.6 V, the use of a 10 μF output capacitor value is recommended. • Types of capacitors Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply functions as a heat generator, therefore avoid to use capacitor with the F-temperature rating ( − 80% to + 20%) . FUJITSU SEMICONDUCTOR recommends capacitors with the B-temperature rating ( ± 10% to ± 20%). Normal electrolytic capacitors are not recommended due to their high ESR. Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when damaged. If you insist on using a tantalum capacitor, FUJITSU SEMICONDUCTOR recommends the type with an internal fuse. 14 DS04-27246-3E MB39C007 [2] Output voltage setting The output voltage VOUT (VOUT1 or VOUT2) of this IC is defined by the voltage input to VREFIN (VREFIN1 or VREFIN2) . Supply the voltage for inputting to VREFIN from an external power supply, or set the VREF output by dividing it with resistors. The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is obtained by the following formula. VOUT = 2.97 × VREFIN, VREFIN = R2 R1 + R2 × VREF (VREF = 1.30 V) MB39C007 VREF VREF R1 VREFIN VREFIN R2 Note : Refer to “■ APPLICATION CIRCUIT EXAMPLES” for the an example of this circuit. Although the output voltage is defined according to the dividing ratio of resistance, select the resistance value so that the current flowing through the resistance does not exceed the VREF current rating (1 mA) . DS04-27246-3E 15 MB39C007 [3] About conversion efficiency The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit. The total loss (PLOSS) of the DC/DC converter is roughly divided as follows : PLOSS = PCONT + PSW + PC PCONT : Control system circuit loss (The power used for this IC to operate, including the gate driving power for internal SW FETs) PSW : Switching loss (The loss caused during switching of the IC's internal SW FETs) PC : Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits ) The IC's control circuit loss (PCONT) is extremely small, less than 100 mW* (with no load). As the IC contains FETs which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavy-load operation than the control circuit loss (PCONT) and switching loss (PSW) . Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series resistance. PC = IOUT2 × (RDC + D × RONP + (1 − D) × RONN) D : Switching ON-duty cycle ( = VOUT / VIN) RONP : Internal P-ch SW FET ON resistance RONN : Internal N-ch SW FET ON resistance RDC : External inductor series resistance IOUT : Load current The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting components. * : The loss in the successive operation mode. This IC suppresses the loss in order to execute the PFM operation in the low load mode (less than 100 μA in no load mode). Mode is changed by the current peak value IPK which flows into switching FET. The threshold value is about 30 mA. 16 DS04-27246-3E MB39C007 [4] Power dissipation and heat considerations The IC is so efficient that no consideration is required in most cases. However, if the IC is used at a low power supply voltage, heavy load, high output voltage, or high temperature, it requires further consideration for higher efficiency. The internal loss (P) is roughly obtained from the following formula: P = IOUT2 × (D × RONP + (1 − D) × RONN) D : Switching ON-duty cycle ( = VOUT / VIN) RONP : Internal P-ch SW FET ON resistance RONN : Internal N-ch SW FET ON resistance IOUT : Output current The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit loss as well but they are so small compared to the continuity loss they can be ignored. In this IC with RONP greater than RONN, the larger the on-duty cycle, the greater the loss. When assuming VIN = 3.7 V, Ta = + 70 °C, for example, RONP = 0.36 Ω and RONN = 0.30 Ω according to the graph “MOS FET ON resistance vs. Operating ambient temperature”. The IC's internal loss P is 123 mW at VOUT = 2.5 V and IOUT = 0.6 A. According to the graph “Power dissipation vs. Operating ambient temperature”, the power dissipation at an operating ambient temperature Ta of + 70 °C is 300 mW and the internal loss is smaller than the power dissipation. DS04-27246-3E 17 MB39C007 [5] XPOR threshold voltage setting [VPORH, VPORL] Set the detection voltage by applying voltage to the VDET pin via an external resistor calculated according to this formula. VPORH = VPORL = R3 + R4 R4 R3 + R4 R4 × VTHHPR × VTHLPR VTHHPR = 0.600 V VTHLPR = 0.583 V • Example for setting detection voltage to 3.7 V R3 = 510 kΩ R4 = 100 kΩ VPORH = VPORL = 510 kΩ + 100 kΩ 100 kΩ 510 kΩ + 100 kΩ 100 kΩ × 0.600 = 3.66 =: 3.7 [V] × 0.583 = 3.56 =: 3.6 [V] VIN MB39C007 AVDD R3 1 MΩ VDET R4 18 XPOR XPOR DS04-27246-3E MB39C007 [6] Transient response Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and overshoot/undershoot voltage is checked. As this IC has built-in Error Amp with an optimized design, it shows good transient response characteristics. However, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor C6 (e.g. 0.1 μF). (Since this capacitor C6 changes the start time, check the start waveform as well.) This action is not required for DAC input. MB39C007 VREF VREF R1 VREFIN VREFIN1/ VREFIN2 R2 DS04-27246-3E C6 19 MB39C007 [7] Board layout, design example The board layout needs to be designed to ensure the stable operation of this IC. Follow the procedure below for designing the layout. • Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a throughhole (TH) near the pins of this capacitor if the board has planes for power and GND. • Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external inductor (L). Group these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these components on the same surface and arrange wiring without through-hole wiring. Use thick, short, and straight routes to wire the net (The layout by planes is recommended.). • Arrange a bypass capacitor for AVDD as close as possible to both the AVDD and AGND pins. Make a through-hole (TH) near the pins of this capacitor if the board has planes for power and GND. • The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (Co). The OUT pin is extremely sensitive and should thus be kept wired away from the LX1 pin and LX2 pin of this IC as far as possible. • If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor is close to the IC's AGND pin. Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current. If installing a bypass capacitor for the VREFIN, put it close to the VREFIN pin. • If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND pin. Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current. • Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the QFN-24 package, FUJITSU SEMICONDUCTOR recommends providing a thermal via in the footprint of the thermal pad. • Example of arranging IC SW system parts Co L VIN Co L GND Cin Cin VIN Feedback line 1pin Feedback line GND VIN AVDD bypass capacitor 20 DS04-27246-3E MB39C007 • Notes for circuit design The switching operation of this IC works by monitoring and controlling the peak current which, incidentally, serves as a form of short-circuit protection. However, do not leave the output short-circuited for long periods of time. If the output is short-circuited where VIN < 2.9 V, the current limit value (peak current to the inductor) tends to rise. Leaving in the short-circuit state, the temperature of this IC will continue rising and activate the thermal protection. Once the thermal protection stops the output, the temperature of the IC will go down and operation will be restarted, after which the output will repeat the starting and stopping. Although this effect will not destroy the IC, the thermal exposure to the IC over prolonged hours may affect the peripherals surrounding it. DS04-27246-3E 21 MB39C007 ■ EXAMPLE OF STANDARD OPERATION CHARACTERISTICS (Shown below is an example of characteristics for connection according to “■ TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS”.) • Characteristics CH1 Conversion efficiency vs. Load current (PFM/PWM mode) Conversion efficiency vs. Load current (PFM/PWM mode) 100 100 VIN = 3.7 V 90 80 VIN = 4.2 V 70 VIN = 5.0 V Conversion efficiency η (%) Conversion efficiency η (%) VIN = 3.7 V VIN = 3.0 V Ta = +25°C VOUT = 2.5 V MODE = L 60 50 1 10 100 90 VIN = 3.0 V 80 60 50 1000 VIN = 5.0 V 1 10 Ta = +25°C VOUT = 1.2 V MODE = L 100 1000 Load current IOUT (mA) Load current IOUT (mA) Conversion efficiency vs. Load current (PFM/PWM mode) Conversion efficiency vs. Load current (PFM/PWM mode) 100 100 VIN = 3.7 V 90 Conversion efficiency η (%) VIN = 3.7 V Conversion efficiency η (%) VIN = 4.2 V 70 VIN = 3.0 V 80 VIN = 4.2 V 70 VIN = 5.0 V Ta = +25°C 60 50 VOUT = 1.8 V 1 10 100 Load current IOUT (mA) 1000 90 VIN = 4.2 V 80 VIN = 5.0 V 70 Ta = +25°C 60 50 VOUT = 3.3 V MODE = L 1 10 100 1000 Load current IOUT (mA) (Continued) 22 DS04-27246-3E MB39C007 Conversion efficiency vs. Load current (PWM fixed mode) Conversion efficiency vs. Load current (PWM fixed mode) 100 100 VIN = 3.0 V 90 Conversion efficiency η (%) Conversion efficiency η (%) 90 80 70 VIN = 3.7 V 60 50 VIN = 4.2 V 40 VIN = 5.0 V 30 Ta = +25°C VOUT = 2.5 V MODE = OPEN 20 10 0 1 10 100 VIN = 3.7 V 80 70 VIN = 3.0 V VIN = 4.2 V 60 50 VIN = 5.0 V 40 30 Ta = +25°C 20 VOUT = 1.2 V MODE = OPEN 10 0 1000 1 10 Conversion efficiency vs. Load current (PWM fixed mode) Conversion efficiency vs. Load current (PWM fixed mode) 100 100 VIN = 3.7 V 90 Conversion efficiency η (%) Conversion efficiency η (%) 1000 Load current IOUT (mA) Load current IOUT (mA) VIN = 3.0 V 80 70 60 VIN = 4.2 V 50 VIN = 5.0 V 40 30 Ta = +25°C VOUT = 1.8 V MODE = OPEN 20 10 1 10 100 Load current IOUT (mA) VIN = 3.7 V 90 80 70 VIN = 4.2 V 60 50 VIN = 5.0 V 40 30 Ta = +25°C VOUT = 3.3 V MODE = OPEN 20 10 0 0 100 1 10 100 1000 1000 Load current IOUT (mA) (Continued) DS04-27246-3E 23 MB39C007 Output voltage vs. Input voltage (PFM/PWM mode) Output voltage vs. Input voltage (PWM fixed mode) 2.60 2.60 2.56 2.54 IOUT = 0 A 2.52 2.50 2.48 IOUT = -100 mA 2.46 2.56 2.54 2.50 2.48 2.46 2.44 2.42 2.42 3.0 4.0 5.0 2.40 6.0 IOUT = 0 A 2.52 2.44 2.40 2.0 Ta = +25°C V OUT = 2.5 V MODE = OPEN 2.58 Ta = +25°C V OUT = 2.5 V MODE = L Output voltage VOUT (V) Output voltage VOUT (V) 2.58 IOUT = -100 mA 2.0 Input voltage VIN (V) 6.0 5.0 2.60 2.60 Ta = +25°C V IN = 3.7 V V OUT = 2.5 V MODE = L 2.56 Ta = +25°C 2.58 Output voltage VOUT (V) 2.58 Output voltage VOUT (V) 4.0 Output voltage vs. Load current (PWM fixed mode) Output voltage vs. Load current (PFM/PWM mode) 2.54 2.52 2.50 2.48 2.46 2.44 VIN = 3.7 V VOUT = 2.5 V MODE = OPEN 2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.42 2.40 3.0 Input voltage VIN (V) 0 200 400 600 Load current IOUT (mA) 800 2.40 0 200 400 600 800 Load current IOUT (mA) (Continued) 24 DS04-27246-3E MB39C007 Reference voltage vs. Operating ambient temperature Reference voltage vs. Input voltage 1.40 1.40 Ta = +25°C V OUT = 2.5 V 1.36 1.34 IOUT = 0 A 1.32 1.30 1.28 1.26 IOUT = -100 mA 1.24 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 V IN = 3.7 V VOUT = 2.5 V IOUT = 0 A 1.38 Reference voltage VREF (V) Reference voltage VREF (V) 1.38 1.22 2.0 3.0 4.0 5.0 1.20 -50 6.0 10 45 9 40 8 35 7 Input current IIN (mA) Input current IIN (μA) 50 30 25 20 Ta = +25°C VOUT = 2.5 V MODE = L 10 5 4 3 Ta = +25°C V OUT = 2.5 V MODE = OPEN 2 0 2.0 3.0 4.0 5.0 Input voltage VIN (V) +100 6 1 5 0 +50 Input current vs. Input voltage (PWM fixed mode) Input current vs. Input voltage (PFM/PWM mode) 15 0 Operating ambient temperature Ta ( °C) Input voltage VIN (V) 6.0 2.0 3.0 4.0 5.0 6.0 Input voltage VIN (V) (Continued) DS04-27246-3E 25 MB39C007 Input current vs. Operating ambient temperature Input current vs. Operating ambient temperature (PWM fixed mode) 50 10 45 9 40 8 Input current IIN (mA) Input current IIN (μA) (PFM/PWM mode) 35 30 25 20 VIN = 3.7 V VOUT = 2.5 V MODE = L 15 10 5 7 6 5 4 3 VIN = 3.7 V VOUT = 2.5 V MODE = OPEN 2 1 0 -50 0 +50 0 +100 -50 Oscillation frequency vs. Operating ambient temperature Oscillation frequency vs. Power supply voltage 2.4 Oscillation frequency fOSC (MHz) 2.4 Oscillation frequency fOSC (MHz) +100 +50 Operating ambient temperature Ta ( °C) Operating ambient temperature Ta ( °C) Ta = +25°C VOUT = 1.8 V IOUT = -100 mA 2.3 2.2 2.1 2.0 1.9 1.8 VIN = 3.7 V VOUT = 2.5 V IOUT = -100 mA 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.7 1.6 0 1.6 2.0 3.0 4.0 5.0 Power supply voltage VIN (V) 6.0 -50 0 +50 +100 Operating ambient temperature Ta ( °C) (Continued) 26 DS04-27246-3E MB39C007 P-ch MOS FET ON resistor vs. Operating ambient temperature MOS FET ON resistor vs. Input voltage 0.6 0.5 P-ch 0.4 0.3 0.2 N-ch 0.1 Ta = +25°C 0 2.0 3.0 4.0 5.0 6.0 P-ch MOS FET ON resistor RONP (Ω) MOS FET ON resistor RON (Ω) 0.6 0.5 V IN = 3.7 V 0.4 0.3 0.2 V IN = 5.5 V 0.1 0 -50 0 +50 +100 Operating ambient temperature Ta ( °C) Input voltage VIN (V) N-ch MOS FET ON resistor vs. Operating ambient temperature N-ch MOS FET ON resistor RONN (Ω) 0.6 0.5 VIN = 3.7 V 0.4 0.3 0.2 VIN = 5.5 V 0.1 0 -50 0 +50 +100 Operating ambient temperature Ta ( °C) (Continued) DS04-27246-3E 27 MB39C007 MODE VTH vs. Input voltage CTL VTH vs. Input voltage 4.0 1.4 3.5 1.2 1.0 VTHMMD 2.5 CTL VTH (V) MODE VTH (V) VTHHCT VTHLCT 3.0 2.0 1.5 0.8 Ta = +25°C V OUT = 2.5 V 0.6 0.4 1.0 0.5 VTHLMD 0.0 2.0 3.0 Ta = +25°C V OUT = 2.5 V 4.0 5.0 0.2 6.0 Input voltage VIN (V) 0.0 2.0 VTHHCT : Circuit OFF→ON VTHLCT : Circuit ON→OFF 3.0 4.0 5.0 6.0 Input voltage VIN (V) VXPOR vs. Input voltage 6.0 Ta = +25°C 5.0 VXPOR (V) 4.0 3.0 VPORL 2.0 VPORH 1.0 0.0 2.0 3.0 4.0 5.0 6.0 Input voltage VIN (V) (Continued) 28 DS04-27246-3E MB39C007 (Continued) Power dissipation vs. Operating ambient temperature (without thermal via) Power dissipation vs. Operating ambient temperature (with thermal via) 3500 3500 3125 3000 Power dissipation PD (mW) Power dissipation PD (mW) 3000 2500 2000 1500 1250 1000 500 0 -50 0 +50 +85 2000 1563 1500 1000 625 500 0 +100 Operating ambient temperature Ta ( °C) DS04-27246-3E 2500 +85 -50 0 +50 +100 Operating ambient temperature Ta ( °C) 29 MB39C007 • Switching waveform PFM/PWM operation 2 μs/div 2 μs/div VO2 : 20 mV/div (AC) VO1 : 20 mV/div (AC) 1 1 VLX2 : 2.0 V/div VLX1 : 2.0 V/div 2 2 lLX2 : 500 mA/div lLX1 : 500 mA/div 4 4 VIN = 3.7 V, IO1 = −5 mA, VO1 = 2.5 V, MODE = L ,Ta = +25 °C VIN = 3.7 V, IO2 = −5 mA, VO2 = 1.8 V, MODE = L ,Ta = +25 °C PWM operation 2 μs/div 2 μs/div VO1 : 20 mV/div (AC) VO2 : 20 mV/div(AC) 1 1 VLX1 : 2.0 V/div VLX2 : 2.0 V/div 2 2 lLX1 : 500 mA/div 4 VIN = 3.7 V, VO1 = 2.5 V, IO1 = −800 mA, MODE = L ,Ta = +25 °C 30 lLX2 : 500 mA/div 4 VIN = 3.7 V, VO2 = 1.8 V, IO2 = −800 mA, MODE = L ,Ta = +25 °C DS04-27246-3E MB39C007 • Output waveforms at sudden load changes 0 A ←→ − 800 mA 100 μs/div 100 μs/div VO1 : 200 mV/div VO2 : 200 mV/div 1 1 2 VLX1 : 2.0 V/div 2 VLX2 : 2.0 V/div −800 mA lO1 : 1 A/div −800 mA lO2 : 1 A/div 4 4 0A 0A VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 °C VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 °C − 20 mA ←→ − 800 mA 100 μs/div 100 μs/div VO1 : 200 mV/div VO2 : 200 mV/div 1 1 2 VLX1 : 2.0 V/div 2 VLX2 : 2.0 V/div 800 mA 800 mA lO2 : 1 A/div lO1 : 1 A/div 4 4 20 mA 20 mA VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 °C VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 °C − 100 mA ←→ − 800 mA VO1 : 200 mV/div 100 μs/div 100 µs/div VO2 : 200 mV/div 1 1 2 VLX1 : 2.0 V/div 2 VLX2 : 2.0 V/div lO1 : 1 A/div 4 800 mA 100 mA VIN = 3.7 V, VO1 = 2.5 V, MODE = L ,Ta = +25 °C DS04-27246-3E 800 mA lO2 : 1 A/div 4 100 mA VIN = 3.7 V, VO2 = 1.8 V, MODE = L ,Ta = +25 °C 31 MB39C007 • CTL start-up waveform No load, No VREFIN capacitor 10 μs/div 10 μs/div 1 3 CTL1 : 5 V/div CTL2 : 5 V/div VO1 : 1 V/div VO2 : 1 V/div 2 1 VLX2 : 5 V/div VLX1 : 5 V/div 3 2 ILX1 : 1 A/div ILX2 : 1 A/div 4 4 VIN = 3.7 V, VO2 = 1.8 V, MODE = L, Ta = + 25 °C VIN = 3.7 V, VO1 = 2.5 V, MODE = L, Ta = + 25 °C Maximum load, No VREFIN capacitor 10 μs/div 10 μs/div 1 3 CTL1 : 5 V/div CTL2 : 5 V/div VO1 : 1 V/div VO2 : 1 V/div 1 2 VLX2 : 5 V/div VLX1 : 5 V/div 3 2 ILX2 : 1 A/div ILX1 : 1 A/div 4 4 VIN = 3.7 V, VO1 = 2.5 V, IO1 = −800 mA, MODE = L, Ta = + 25 °C VIN = 3.7 V, VO2 = 1.8 V, IO2 = −800 mA, MODE = L, Ta = + 25 °C (Continued) 32 DS04-27246-3E MB39C007 (Continued) No load, VREFIN capacitor = 0.1 μF 1 ms/div 1 ms/div 1 1 CTL2 : 5 V/div CTL1 : 5 V/div VO2 : 1 V/div VO1 : 1 V/div 2 VLX1 : 5 V/div VLX2 : 5 V/div 2 3 3 ILX1 : 1 A/div ILX2 : 1 A/div 4 4 VIN = 3.7 V, VO1 = 2.5 V, MODE = L, Ta = + 25 °C VIN = 3.7 V, VO2 = 1.8 V, MODE = L, Ta = + 25 °C Maximum load, VREFIN capacitor = 0.1 μF 1 ms/div 1 1 ms/div 1 CTL2 : 5 V/div CTL1 : 5 V/div VO1 : 1 V/div 2 VLX1 : 5 V/div VO2 : 1 V/div 2 3 VLX2 : 5 V/div 3 ILX1 : 1 A/div ILX2 : 1 A/div 4 4 VIN = 3.7 V, VO1 = 2.5 V, IO1 = −800 mA, MODE = L, Ta = + 25 °C VIN = 3.7 V, VO2 = 1.8 V, IO2 = −800 mA, MODE = L, Ta = + 25 °C • CTL stop waveform Maximum load, VREFIN capacitor = 0.1 μF 10 μs/div 10 μs/div CTL2 : 5 V/div CTL1 : 5 V/div 1 1 VO1 : 1 V/div VO2 : 1 V/div 2 2 VLX1 : 5 V/div 3 VLX2 : 5 V/div 3 ILX1 : 1 A/div ILX2 : 1 A/div 4 4 VIN = 3.7 V, VO1 = 2.5 V, IO1 = −800 mA, MODE = L, Ta = + 25 °C VIN = 3.7 V, VO2 = 1.8 V, IO2 = −800 mA, MODE = L, Ta = + 25 °C DS04-27246-3E 33 MB39C007 • Current limitation waveform 100 μs/div 100 μs/div VO1 : 1 V/div VO2 : 1 V/div 1 1 1.5 A ILX1 : 1 A/div 1.5 A ILX2 : 1 A/div 600 mA 600 mA 4 4 VIN = 3.7 V, VO1 = 2.5 V, MODE = OPEN, Ta = +25 °C VIN = 3.7 V, VO2 = 1.8 V, MODE = OPEN, Ta = +25 °C • Voltage detection waveform 1 ms/div 1 VIN : 3 V/div 2 VVDET : 1 V/div 3 VXPOR : 3 V/div VIN = 3.7 V, CTLP = VIN, Ta = +25 °C Pull-up XPOR to VIN at 1 kΩ. • Waveform of dynamic output voltage transition (VO1 1.8 V←→2.5 V) 10 μs/div VO1 : 200 mV/div 2.5 V 1.8 VV 1.8 1 VVREFIN1 : 200 mV/div 840 mV 3 610 mV VIN = 3.7 V, lO1 = −800 mA, −576 mA ( 3.125 Ω), MODE = L, Ta = +25 °C, No VREFIN capacitor 34 DS04-27246-3E MB39C007 ■ APPLICATION CIRCUIT EXAMPLES • APPLICATION CIRCUIT EXAMPLE 1 • An external voltage is input to the reference voltage external input (VREFIN1, VREFIN2) , and the VOUT voltage is set to 2.97 times the VOUT setting gain. MB39C007 3 CTL1 CPU R7 DVDD1 11 12 DGND1 14 15 1 MΩ DVDD2 19 20 8 VREFIN1 DAC1 VIN C4 4.7 μF DGND2 16 17 AVDD 5 C5 0.1 μF 2 CTL2 AGND R8 C3 4.7 μF 4 1 MΩ L1 2.2 μH 23 VREFIN2 DAC2 LX1 13 VOUT1 C1 4.7 μF 9 MODE1 OUT1 10 APLI1 L = PFM/PWM OPEN = PWM L2 2.2 μH 22 MODE2 VOUT2 LX2 18 6 VREF OUT2 21 C2 4.7 μF APLI2 7 VDET 1 CTLP DS04-27246-3E XPOR 24 VOUT = 2.97 × VREFIN 35 MB39C007 • APPLICATION CIRCUIT EXAMPLE 2 • The voltage of VREF pin is input to the reference voltage external input (VREFIN1, VREFIN2) by dividing resistors. The VOUT1 voltage is set to 2.5 V and VOUT2 voltage is set to 1.8 V. MB39C0007 3 CTL1 CPU R7 DGND1 14 15 1 MΩ R1 163 kΩ ( 13 kΩ + 150 kΩ ) DVDD1 11 12 DVDD2 19 20 8 VREFIN1 R2 C3 4.7 μF VIN C4 4.7 μF DGND2 16 17 300 kΩ AVDD 5 C5 0.1 μF 2 CTL2 AGND 4 R8 1 MΩ L1 2.2 μH VOUT1 LX1 13 R5 343 kΩ ( 13 kΩ + 330 kΩ ) C1 4.7 μF 23 VREFIN2 OUT1 10 R6 APLI1 300 kΩ 6 VREF 9 MODE1 L2 2.2 μH VOUT2 LX2 18 L = PFM/PWM OPEN = PWM 22 MODE2 C2 4.7 μF OUT2 21 APLI2 7 VDET 1 CTLP XPOR 24 VOUT1 = 2.97 × VREFIN1 VREFIN1 = R2 × VREF R1 + R2 (VREF = 1.30 V) 36 VOUT1 = 2.97 × 300 kΩ × 1.30 V = 2.5 V 163 kΩ + 300 kΩ VOUT2 = 2.97 × 300 kΩ × 1.30 V = 1.8 V 343 kΩ + 300 kΩ DS04-27246-3E MB39C007 • APPLICATION CIRCUIT EXAMPLE COMPONENTS LIST Component Item Part Number Specification Package Vendor VLF4012AT-2R2M 2.2 μH, RDC = 76 mΩ SMD TDK MIPW3226D2R2M 2.2 μH, RDC = 100 mΩ SMD FDK VLF4012AT-2R2M 2.2 μH, RDC = 76 mΩ SMD TDK MIPW3226D2R2M 2.2 μH, RDC = 100 mΩ SMD FDK Ceramic capacitor C2012JB1A475K 4.7 μF (10 V) 2012 TDK C2 Ceramic capacitor C2012JB1A475K 4.7 μF (10 V) 2012 TDK C3 Ceramic capacitor C2012JB1A475K 4.7 μF (10 V) 2012 TDK C4 Ceramic capacitor C2012JB1A475K 4.7 μF (10 V) 2012 TDK C5 Ceramic capacitor C1608JB1E104K 0.1 μF (50 V) 2012 TDK R1 Resistor RK73G1JTTD D 13 kΩ 13 kΩ RK73G1JTTD D 150 kΩ 150 kΩ 1608 1608 KOA KOA R2 Resistor RK73G1JTTD D 300 kΩ 300 kΩ 1608 KOA R5 Resistor RK73G1JTTD D 13 kΩ 13 kΩ RK73G1JTTD D 330 kΩ 330 kΩ 1608 1608 KOA KOA R6 Resistor RK73G1JTTD D 300 kΩ 300 kΩ 1608 KOA R7 Resistor RK73G1JTTD D 1 MΩ 1 MΩ ± 0.5% 1608 KOA R8 Resistor RK73G1JTTD D 1 MΩ 1 MΩ ± 0.5% 1608 KOA L1 Inductor L2 Inductor C1 TDK : TDK Corporation FDK : FDK Corporation KOA : KOA Corporation DS04-27246-3E 37 MB39C007 ■ USAGE PRECAUTIONS 1. Do not configure the IC over the maximum ratings If the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions adversely affect the reliability of the LSI. 2. Use the devices within recommended operating conditions The recommended operating conditions are the conditions under which the LSl is guaranteed to operate. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item. 3. Printed circuit board ground lines should be set up with consideration for common impedance 4. Take appropriate static electricity measures • Containers for semiconductor materials should have anti-static protection or be made of conductive material. • After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. • Work platforms, tools, and instruments should be properly grounded. • Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. 5. Do not apply negative voltages The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation. 38 DS04-27246-3E MB39C007 ■ ORDERING INFORMATION Part number MB39C007WQN DS04-27246-3E Package Remarks 24-pin plastic QFN (LCC-24P-M10) 39 MB39C007 ■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is RoHS compliant. ■ MARKING FORMAT (LEAD FREE VERSION) XE1 XXXXXX Lead-free version(E1) INDEX 40 DS04-27246-3E MB39C007 ■ LABELING SAMPLE (LEAD FREE VERSION) Lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 The part number of a lead-free product has the trailing characters “E1”. DS04-27246-3E “ASSEMBLED IN CHINA” is printed on the label of a product assembled in China. 41 MB39C007 ■ EVALUATION BOARD SPECIFICATION The MB39C007 Evaluation Board provides the proper for evaluating the efficiency and other characteristics of the MB39C007. • Terminal information Symbol Functions Power supply terminal In standard condition 3.1 V to 5.5 V* VIN VOUT1, VOUT2 VCTL CTL1, CTL2 MODE1, MODE2 VREF * : When the VIN/VOUT difference is to be held within 0.6 V or less, such as for devices with a standard output voltage (VOUT1 = 2.5 V) when VIN < 3.1 V, FUJITSU SEMICONDUCTOR recommends changing the output capacity (C1, C2) to 10 μF. Output terminals (VOUT1: CH1, VOUT2: CH2) Power supply terminal for setting the CTL1, CTL2 and CTLP terminals. Use by connecting with VIN (When SW is mounted). Direct supply terminal of CTL (CTL1 : for CH1, CTL2 : for CH2) CTL1, CTL2 = 0 V to 0.8 V (Typ.) : Shutdown CTL1, CTL2 = 0.95 V (Typ.) to VIN (5 V Max) : Normal operation Direct supply terminal of MODE (CH1 : for MODE1, CH2 : for MODE2) MODE1, MODE2 = 0 V to 0.4 V(Max) : PFM/PWM mode MODE1, MODE2 = OPEN(Remove R1 and R4) : PWM mode Reference voltage output terminal VREF = 1.30 V (Typ.) External reference voltage input terminals (VREFIN1 : for CH1, VREFIN2 : for CH2) VREFIN1, VREFIN2 When an external reference voltage is supplied, connect it to the terminal for each channel. 42 VDET Voltage input terminal for voltage detection CTLP Voltage detection circuit block control terminal CTLP = L : Voltage detection circuit block stop CTLP = H : Normal operation XPOR Voltage detection circuit output terminal The N-ch MOS open drain circuit is connected. VXPOR Pull-up voltage terminal for the XPOR terminal PGND Ground terminal Connect power supply GND to the PGND terminal next to the VIN terminal. Connect output (load) GND to the PGND terminal between the VOUT1 terminal and the VOUT2 terminal. AGND Ground terminal DS04-27246-3E MB39C007 • Startup terminal information Terminal name Condition Functions CTL1 L : Open H : Connect to VIN ON/OFF switch for CH1 L : Shutdown H : Normal operation. CTL2 L : Open H : Connect to VIN ON/OFF switch for CH2 L : Shutdown H : Normal operation. CTLP L : Open H : Connect to VIN ON/OFF switch for the voltage detection block L: Stops the voltage detection circuit H: Normal operation. • Jumper information JP • Functions JP1 Short-circuited in the layout pattern of the board (normally used shorted). JP2 Short-circuited in the layout pattern of the board (normally used shorted). JP3 Not mounted JP6 Normally used shorted (0 Ω) Setup and checkup (1) Setup 1. Connect the CTL1 terminal and the CTL2 terminal to the VIN terminal. 2. Put it into “L” state by connecting the CTLP terminal to the AGND pad. 3. Connect the power supply terminal to the VIN terminal, and the power supply GND terminal to the PGND terminal. Make sure PGND is connected to the PGND terminal next to the VIN terminal. (Example of setting power-supply voltage : 3.7 V) (2) Checkup Supply power to VIN. The IC is operating normally if VOUT1 = 2.5 V (Typ) and VOUT2 = 1.8 V (Typ). DS04-27246-3E 43 MB39C007 • Component layout on the evaluation board (Top View) MB39C007EVB-06Rev. 2.0 VOUT2 VOUT1 PGMD C1 C2 MODE2 L2 VIN MODE1 L1 M1 XPOR C3 C6 C4 C7 R5 R4-2 R9 JP6 R4-1 R3 R1 VREFIN1 R2 C5 R1-1R1-2 R4 VREFIN2 R7 R6-2 R6-1 VDET VREF OFF JP3 VXPOR AGND CTLP CTL1 4 CTL2 1 SW1 VCTL CTL2 CTL1 R8 44 CTLP R10 DS04-27246-3E MB39C007 • Evaluation board layout (Top View) DS04-27246-3E Top Side (Layer1) Inside GND (Layer2) Inside VIN & GND (Layer3) Bottom Side (Layer4) 45 MB39C007 • Connection diagram I IN VIN MB39C007 JP3 SW1 3 VCTL R8 1 MΩ CTL1 DVDD1 11 DVDD1 12 CTL1 C3 4.7 μF DGND1 14 MODE1 9 MODE1 R1 0Ω DGND1 15 DVDD2 19 DVDD2 20 PGND VREF R6-1 R6-2 13 kΩ 150 kΩ VREFIN1 C6 0.1 µF R7 300 kΩ 8 VREFIN1 DGND2 16 C4 4.7 μF DGND2 17 JP6 SW1 AVDD 2 R9 1 MΩ CTL2 MODE2 5 CTL2 C5 0.1 μF AGND 4 22 MODE2 R4 0Ω AGND L1 2.2 μH I OUT LX1 13 VOUT1 VREF VREFIN2 JP1 R4-1 R4-2 13 kΩ 330 kΩ R5 300 kΩ C1 4.7 μF C7 0.1 µF 23 VREFIN2 OUT1 10 L2 2.2 μH I OUT LX2 18 6 VREF VREF VREF VDET R1-1 0Ω SW1 46 C2 4.7 μF JP2 OUT2 21 R1-2 300 kΩ 7 VXPOR VDET R2 75 kΩ R3 1MΩ 1 CTLP VOUT2 R10 1 MΩ CTLP XPOR XPOR 24 * Not mounted DS04-27246-3E MB39C007 • Component list CompoPart Name nent Model Number Specification Package Vendor Remark M1 IC MB39C007WQN ⎯ QFN-24 FSL L1 Inductor VLF4012AT-2R2M 2.2 μH, RDC=76 mΩ SMD TDK L2 Inductor VLF4012AT-2R2M 2.2 μH, RDC=76 mΩ SMD TDK C1 Ceramic capacitor C2012JB1A475K 4.7 μF(10 V) 2012 TDK C2 Ceramic capacitor C2012JB1A475K 4.7 μF(10 V) 2012 TDK C3 Ceramic capacitor C2012JB1A475K 4.7 μF(10 V) 2012 TDK C4 Ceramic capacitor C2012JB1A475K 4.7 μF(10 V) 2012 TDK C5 Ceramic capacitor C1608JB1E104K 0.1 μF(50 V) 1608 TDK C6 Ceramic capacitor C1608JB1H104K 0.1 μF(50 V) 1608 TDK C7 Ceramic capacitor C1608JB1H104K 0.1 μF(50 V) 1608 TDK R1 Resistor RK73Z1J 0 Ω, 1 A 1608 KOA R1-1 Resistor RK73Z1J 0 Ω, 1 A 1608 KOA R1-2 Resistor RR0816P-304-D 300 kΩ ± 0.5% 1608 SSM R2 Resistor RR0816P-753-D 75 kΩ ± 0.5% 1608 SSM R3 Resistor RK73G1JTTD D 1MΩ 1 MΩ ± 0.5% 1608 KOA R4 Resistor RK73Z1J 0 Ω, 1 A 1608 KOA R4-1 Resistor RR0816P-133-D 13 kΩ ± 0.5% 1608 SSM R4-2 Resistor RR0816P-334-D 330 kΩ ± 0.5% 1608 SSM R5 Resistor RR0816P-304-D 300 kΩ ± 0.5% 1608 SSM R6-1 Resistor RR0816P-133-D 13 kΩ ± 0.5% 1608 SSM R6-2 Resistor RR0816P-154-D 150 kΩ ± 0.5% 1608 SSM R7 Resistor RR0816P-304-D 300 kΩ ± 0.5% 1608 SSM R8 Resistor RK73G1JTTD D 1MΩ 1 MΩ ± 0.5% 1608 KOA R9 Resistor RK73G1JTTD D 1MΩ 1 MΩ ± 0.5% 1608 KOA R10 Resistor RK73G1JTTD D 1MΩ 1 MΩ ± 0.5% 1608 KOA SW1 DIP switch ⎯ ⎯ ⎯ ⎯ Not mounted JP1 Jumper ⎯ ⎯ ⎯ ⎯ Patternshorted JP2 Jumper ⎯ ⎯ ⎯ ⎯ Patternshorted JP3 Jumper ⎯ ⎯ ⎯ ⎯ Not mounted JP6 Jumper RK73Z1J 0 Ω, 1A 1608 KOA Note : These components are recommended based on the operating tests authorized. FSL TDK KOA SSM : FUJITSU SEMICONDUCTOR LIMITED : TDK Corporation : KOA Corporation : SUSUMU Co., Ltd DS04-27246-3E 47 MB39C007 ■ EV BOARD ORDERING INFORMATION 48 EV Board Part No. EV Board Version No. Remarks MB39C007EVB-06 MB39C007EVB-06 Rev.2.0 QFN-24 DS04-27246-3E MB39C007 ■ PACKAGE DIMENSION 24-pin plastic QFN Lead pitch 0.50 mm Package width × package length 4.00 mm × 4.00 mm Sealing method Plastic mold Mounting height 0.80 mm Max Weight 0.04 g (LCC-24P-M10) 24-pin plastic QFN (LCC-24P-M10) 2.60±0.10 (.102±.004) 4.00±0.10 (.157±.004) 4.00±0.10 (.157±.004) INDEX AREA 2.60±0.10 (.102±.004) 0.25±0.05 (.010±.002) 0.40±0.05 (.016±.002) 0.50(.020) TYP 0.02 (.001 C +0.03 –0.02 +.001 –.001 1PIN CORNER (C0.35(C.014)) 0.75±0.05 (.030±.002) (0.20(.008)) ) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C24060S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS04-27246-3E 49 MB39C007 ■ CONTENTS - 50 page DESCRIPTION .................................................................................................................................................... 1 FEATURES .......................................................................................................................................................... 1 APPLICATIONS .................................................................................................................................................. 1 PIN ASSIGNMENT ............................................................................................................................................. 2 PIN DESCRIPTIONS .......................................................................................................................................... 3 I/O PIN EQUIVALENT CIRCUIT DIAGRAM ................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 FUNCTION OF EACH BLOCK ......................................................................................................................... 7 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9 RECOMMENDED OPERATING CONDITIONS ............................................................................................ 10 ELECTRICAL CHARACTERISTICS ................................................................................................................ 11 TEST CIRCUIT FOR MEASURING TYPICAL OPERATING CHARACTERISTICS ................................ 13 APPLICATION NOTES ...................................................................................................................................... 14 EXAMPLE OF STANDARD OPERATION CHARACTERISTICS ............................................................... 22 APPLICATION CIRCUIT EXAMPLES ............................................................................................................. 35 USAGE PRECAUTIONS ................................................................................................................................... 38 ORDERING INFORMATION ............................................................................................................................. 39 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION .................................................. 40 MARKING FORMAT (LEAD FREE VERSION) .............................................................................................. 40 LABELING SAMPLE (LEAD FREE VERSION) ............................................................................................. 41 EVALUATION BOARD SPECIFICATION ....................................................................................................... 42 EV BOARD ORDERING INFORMATION ....................................................................................................... 48 PACKAGE DIMENSION .................................................................................................................................... 49 DS04-27246-3E MB39C007 MEMO DS04-27246-3E 51 MB39C007 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department